2 * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
3 * Copyright (c) 2006, 2007 Maciej W. Rozycki
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 * This driver is designed for the Broadcom SiByte SOC built-in
20 * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
22 * Updated to the driver model and the PHY abstraction layer
23 * by Maciej W. Rozycki.
26 #include <linux/bug.h>
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/string.h>
30 #include <linux/timer.h>
31 #include <linux/errno.h>
32 #include <linux/ioport.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/bitops.h>
39 #include <linux/err.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/phy.h>
43 #include <linux/platform_device.h>
44 #include <linux/prefetch.h>
46 #include <asm/cache.h>
48 #include <asm/processor.h> /* Processor type for cache alignment. */
50 /* Operational parameters that usually are not changed. */
52 #define CONFIG_SBMAC_COALESCE
54 /* Time in jiffies before concluding the transmitter is hung. */
55 #define TX_TIMEOUT (2*HZ)
58 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
59 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
61 /* A few user-configurable values which may be modified when a driver
64 /* 1 normal messages, 0 quiet .. 7 verbose. */
66 module_param(debug, int, S_IRUGO);
67 MODULE_PARM_DESC(debug, "Debug messages");
69 #ifdef CONFIG_SBMAC_COALESCE
70 static int int_pktcnt_tx = 255;
71 module_param(int_pktcnt_tx, int, S_IRUGO);
72 MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count");
74 static int int_timeout_tx = 255;
75 module_param(int_timeout_tx, int, S_IRUGO);
76 MODULE_PARM_DESC(int_timeout_tx, "TX timeout value");
78 static int int_pktcnt_rx = 64;
79 module_param(int_pktcnt_rx, int, S_IRUGO);
80 MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count");
82 static int int_timeout_rx = 64;
83 module_param(int_timeout_rx, int, S_IRUGO);
84 MODULE_PARM_DESC(int_timeout_rx, "RX timeout value");
87 #include <asm/sibyte/board.h>
88 #include <asm/sibyte/sb1250.h>
89 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
90 #include <asm/sibyte/bcm1480_regs.h>
91 #include <asm/sibyte/bcm1480_int.h>
92 #define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST
93 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
94 #include <asm/sibyte/sb1250_regs.h>
95 #include <asm/sibyte/sb1250_int.h>
97 #error invalid SiByte MAC configuration
99 #include <asm/sibyte/sb1250_scd.h>
100 #include <asm/sibyte/sb1250_mac.h>
101 #include <asm/sibyte/sb1250_dma.h>
103 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
104 #define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2))
105 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
106 #define UNIT_INT(n) (K_INT_MAC_0 + (n))
108 #error invalid SiByte MAC configuration
112 #define SBMAC_PHY_INT K_INT_PHY
114 #define SBMAC_PHY_INT PHY_POLL
117 /**********************************************************************
119 ********************************************************************* */
122 sbmac_speed_none = 0,
123 sbmac_speed_10 = SPEED_10,
124 sbmac_speed_100 = SPEED_100,
125 sbmac_speed_1000 = SPEED_1000,
129 sbmac_duplex_none = -1,
130 sbmac_duplex_half = DUPLEX_HALF,
131 sbmac_duplex_full = DUPLEX_FULL,
150 /**********************************************************************
152 ********************************************************************* */
155 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
156 (d)->sbdma_dscrtable : (d)->f+1)
159 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
161 #define SBMAC_MAX_TXDESCR 256
162 #define SBMAC_MAX_RXDESCR 256
164 #define ENET_PACKET_SIZE 1518
165 /*#define ENET_PACKET_SIZE 9216 */
167 /**********************************************************************
168 * DMA Descriptor structure
169 ********************************************************************* */
176 /**********************************************************************
177 * DMA Controller structure
178 ********************************************************************* */
183 * This stuff is used to identify the channel and the registers
184 * associated with it.
186 struct sbmac_softc *sbdma_eth; /* back pointer to associated
188 int sbdma_channel; /* channel number */
189 int sbdma_txdir; /* direction (1=transmit) */
190 int sbdma_maxdescr; /* total # of descriptors
192 #ifdef CONFIG_SBMAC_COALESCE
193 int sbdma_int_pktcnt;
194 /* # descriptors rx/tx
196 int sbdma_int_timeout;
197 /* # usec rx/tx interrupt */
199 void __iomem *sbdma_config0; /* DMA config register 0 */
200 void __iomem *sbdma_config1; /* DMA config register 1 */
201 void __iomem *sbdma_dscrbase;
202 /* descriptor base address */
203 void __iomem *sbdma_dscrcnt; /* descriptor count register */
204 void __iomem *sbdma_curdscr; /* current descriptor
206 void __iomem *sbdma_oodpktlost;
207 /* pkt drop (rx only) */
210 * This stuff is for maintenance of the ring
212 void *sbdma_dscrtable_unaligned;
213 struct sbdmadscr *sbdma_dscrtable;
214 /* base of descriptor table */
215 struct sbdmadscr *sbdma_dscrtable_end;
216 /* end of descriptor table */
217 struct sk_buff **sbdma_ctxtable;
218 /* context table, one
220 dma_addr_t sbdma_dscrtable_phys;
221 /* and also the phys addr */
222 struct sbdmadscr *sbdma_addptr; /* next dscr for sw to add */
223 struct sbdmadscr *sbdma_remptr; /* next dscr for sw
228 /**********************************************************************
229 * Ethernet softc structure
230 ********************************************************************* */
235 * Linux-specific things
237 struct net_device *sbm_dev; /* pointer to linux device */
238 struct napi_struct napi;
239 struct phy_device *phy_dev; /* the associated PHY device */
240 struct mii_bus *mii_bus; /* the MII bus */
241 int phy_irq[PHY_MAX_ADDR];
242 spinlock_t sbm_lock; /* spin lock */
243 int sbm_devflags; /* current device flags */
246 * Controller-specific things
248 void __iomem *sbm_base; /* MAC's base address */
249 enum sbmac_state sbm_state; /* current state */
251 void __iomem *sbm_macenable; /* MAC Enable Register */
252 void __iomem *sbm_maccfg; /* MAC Config Register */
253 void __iomem *sbm_fifocfg; /* FIFO Config Register */
254 void __iomem *sbm_framecfg; /* Frame Config Register */
255 void __iomem *sbm_rxfilter; /* Receive Filter Register */
256 void __iomem *sbm_isr; /* Interrupt Status Register */
257 void __iomem *sbm_imr; /* Interrupt Mask Register */
258 void __iomem *sbm_mdio; /* MDIO Register */
260 enum sbmac_speed sbm_speed; /* current speed */
261 enum sbmac_duplex sbm_duplex; /* current duplex */
262 enum sbmac_fc sbm_fc; /* cur. flow control setting */
263 int sbm_pause; /* current pause setting */
264 int sbm_link; /* current link state */
266 unsigned char sbm_hwaddr[ETH_ALEN];
268 struct sbmacdma sbm_txdma; /* only channel 0 for now */
269 struct sbmacdma sbm_rxdma;
275 /**********************************************************************
277 ********************************************************************* */
279 /**********************************************************************
281 ********************************************************************* */
283 static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
284 int txrx, int maxdescr);
285 static void sbdma_channel_start(struct sbmacdma *d, int rxtx);
286 static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d,
288 static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *m);
289 static void sbdma_emptyring(struct sbmacdma *d);
290 static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d);
291 static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
292 int work_to_do, int poll);
293 static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
295 static int sbmac_initctx(struct sbmac_softc *s);
296 static void sbmac_channel_start(struct sbmac_softc *s);
297 static void sbmac_channel_stop(struct sbmac_softc *s);
298 static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *,
300 static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff);
301 static uint64_t sbmac_addr2reg(unsigned char *ptr);
302 static irqreturn_t sbmac_intr(int irq, void *dev_instance);
303 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
304 static void sbmac_setmulti(struct sbmac_softc *sc);
305 static int sbmac_init(struct platform_device *pldev, long long base);
306 static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed);
307 static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
310 static int sbmac_open(struct net_device *dev);
311 static void sbmac_tx_timeout (struct net_device *dev);
312 static void sbmac_set_rx_mode(struct net_device *dev);
313 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
314 static int sbmac_close(struct net_device *dev);
315 static int sbmac_poll(struct napi_struct *napi, int budget);
317 static void sbmac_mii_poll(struct net_device *dev);
318 static int sbmac_mii_probe(struct net_device *dev);
320 static void sbmac_mii_sync(void __iomem *sbm_mdio);
321 static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
323 static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx);
324 static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
328 /**********************************************************************
330 ********************************************************************* */
332 static char sbmac_string[] = "sb1250-mac";
334 static char sbmac_mdio_string[] = "sb1250-mac-mdio";
337 /**********************************************************************
339 ********************************************************************* */
341 #define MII_COMMAND_START 0x01
342 #define MII_COMMAND_READ 0x02
343 #define MII_COMMAND_WRITE 0x01
344 #define MII_COMMAND_ACK 0x02
346 #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
351 /**********************************************************************
352 * SBMAC_MII_SYNC(sbm_mdio)
354 * Synchronize with the MII - send a pattern of bits to the MII
355 * that will guarantee that it is ready to accept a command.
358 * sbm_mdio - address of the MAC's MDIO register
362 ********************************************************************* */
364 static void sbmac_mii_sync(void __iomem *sbm_mdio)
370 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
372 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
374 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
376 for (cnt = 0; cnt < 32; cnt++) {
377 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
378 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
382 /**********************************************************************
383 * SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt)
385 * Send some bits to the MII. The bits to be sent are right-
386 * justified in the 'data' parameter.
389 * sbm_mdio - address of the MAC's MDIO register
390 * data - data to send
391 * bitcnt - number of bits to send
392 ********************************************************************* */
394 static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
399 unsigned int curmask;
402 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
404 bits = M_MAC_MDIO_DIR_OUTPUT;
405 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
407 curmask = 1 << (bitcnt - 1);
409 for (i = 0; i < bitcnt; i++) {
411 bits |= M_MAC_MDIO_OUT;
412 else bits &= ~M_MAC_MDIO_OUT;
413 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
414 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
415 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
422 /**********************************************************************
423 * SBMAC_MII_READ(bus, phyaddr, regidx)
424 * Read a PHY register.
427 * bus - MDIO bus handle
428 * phyaddr - PHY's address
429 * regnum - index of register to read
432 * value read, or 0xffff if an error occurred.
433 ********************************************************************* */
435 static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
437 struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
438 void __iomem *sbm_mdio = sc->sbm_mdio;
445 * Synchronize ourselves so that the PHY knows the next
446 * thing coming down is a command
448 sbmac_mii_sync(sbm_mdio);
451 * Send the data to the PHY. The sequence is
452 * a "start" command (2 bits)
453 * a "read" command (2 bits)
454 * the PHY addr (5 bits)
455 * the register index (5 bits)
457 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
458 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2);
459 sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
460 sbmac_mii_senddata(sbm_mdio, regidx, 5);
462 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
465 * Switch the port around without a clock transition.
467 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
470 * Send out a clock pulse to signal we want the status
472 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
474 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
477 * If an error occurred, the PHY will signal '1' back
479 error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN;
482 * Issue an 'idle' clock pulse, but keep the direction
485 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
487 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
491 for (idx = 0; idx < 16; idx++) {
495 if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN)
499 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
501 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
504 /* Switch back to output */
505 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);
513 /**********************************************************************
514 * SBMAC_MII_WRITE(bus, phyaddr, regidx, regval)
516 * Write a value to a PHY register.
519 * bus - MDIO bus handle
520 * phyaddr - PHY to use
521 * regidx - register within the PHY
522 * regval - data to write to register
526 ********************************************************************* */
528 static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
531 struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
532 void __iomem *sbm_mdio = sc->sbm_mdio;
535 sbmac_mii_sync(sbm_mdio);
537 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
538 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2);
539 sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
540 sbmac_mii_senddata(sbm_mdio, regidx, 5);
541 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2);
542 sbmac_mii_senddata(sbm_mdio, regval, 16);
544 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
546 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);
553 /**********************************************************************
554 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
556 * Initialize a DMA channel context. Since there are potentially
557 * eight DMA channels per MAC, it's nice to do this in a standard
561 * d - struct sbmacdma (DMA channel context)
562 * s - struct sbmac_softc (pointer to a MAC)
563 * chan - channel number (0..1 right now)
564 * txrx - Identifies DMA_TX or DMA_RX for channel direction
565 * maxdescr - number of descriptors
569 ********************************************************************* */
571 static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
572 int txrx, int maxdescr)
574 #ifdef CONFIG_SBMAC_COALESCE
575 int int_pktcnt, int_timeout;
579 * Save away interesting stuff in the structure
583 d->sbdma_channel = chan;
584 d->sbdma_txdir = txrx;
588 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
591 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES);
592 __raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS);
593 __raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL);
594 __raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL);
595 __raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR);
596 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT);
597 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD);
598 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD);
599 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT);
600 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE);
601 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES);
602 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST);
603 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST);
604 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD);
605 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD);
606 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT);
607 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE);
608 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR);
609 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR);
610 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR);
611 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR);
614 * initialize register pointers
618 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
620 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
622 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
624 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
626 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
628 d->sbdma_oodpktlost = NULL;
630 d->sbdma_oodpktlost =
631 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX);
634 * Allocate memory for the ring
637 d->sbdma_maxdescr = maxdescr;
639 d->sbdma_dscrtable_unaligned = kcalloc(d->sbdma_maxdescr + 1,
640 sizeof(*d->sbdma_dscrtable),
644 * The descriptor table must be aligned to at least 16 bytes or the
645 * MAC will corrupt it.
647 d->sbdma_dscrtable = (struct sbdmadscr *)
648 ALIGN((unsigned long)d->sbdma_dscrtable_unaligned,
649 sizeof(*d->sbdma_dscrtable));
651 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
653 d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
659 d->sbdma_ctxtable = kcalloc(d->sbdma_maxdescr,
660 sizeof(*d->sbdma_ctxtable), GFP_KERNEL);
662 #ifdef CONFIG_SBMAC_COALESCE
664 * Setup Rx/Tx DMA coalescing defaults
667 int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx;
669 d->sbdma_int_pktcnt = int_pktcnt;
671 d->sbdma_int_pktcnt = 1;
674 int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx;
676 d->sbdma_int_timeout = int_timeout;
678 d->sbdma_int_timeout = 0;
684 /**********************************************************************
685 * SBDMA_CHANNEL_START(d)
687 * Initialize the hardware registers for a DMA channel.
690 * d - DMA channel to init (context must be previously init'd
691 * rxtx - DMA_RX or DMA_TX depending on what type of channel
695 ********************************************************************* */
697 static void sbdma_channel_start(struct sbmacdma *d, int rxtx)
700 * Turn on the DMA channel
703 #ifdef CONFIG_SBMAC_COALESCE
704 __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
705 0, d->sbdma_config1);
706 __raw_writeq(M_DMA_EOP_INT_EN |
707 V_DMA_RINGSZ(d->sbdma_maxdescr) |
708 V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
709 0, d->sbdma_config0);
711 __raw_writeq(0, d->sbdma_config1);
712 __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
713 0, d->sbdma_config0);
716 __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
719 * Initialize ring pointers
722 d->sbdma_addptr = d->sbdma_dscrtable;
723 d->sbdma_remptr = d->sbdma_dscrtable;
726 /**********************************************************************
727 * SBDMA_CHANNEL_STOP(d)
729 * Initialize the hardware registers for a DMA channel.
732 * d - DMA channel to init (context must be previously init'd
736 ********************************************************************* */
738 static void sbdma_channel_stop(struct sbmacdma *d)
741 * Turn off the DMA channel
744 __raw_writeq(0, d->sbdma_config1);
746 __raw_writeq(0, d->sbdma_dscrbase);
748 __raw_writeq(0, d->sbdma_config0);
754 d->sbdma_addptr = NULL;
755 d->sbdma_remptr = NULL;
758 static inline void sbdma_align_skb(struct sk_buff *skb,
759 unsigned int power2, unsigned int offset)
761 unsigned char *addr = skb->data;
762 unsigned char *newaddr = PTR_ALIGN(addr, power2);
764 skb_reserve(skb, newaddr - addr + offset);
768 /**********************************************************************
769 * SBDMA_ADD_RCVBUFFER(d,sb)
771 * Add a buffer to the specified DMA channel. For receive channels,
772 * this queues a buffer for inbound packets.
775 * sc - softc structure
776 * d - DMA channel descriptor
777 * sb - sk_buff to add, or NULL if we should allocate one
780 * 0 if buffer could not be added (ring is full)
781 * 1 if buffer added successfully
782 ********************************************************************* */
785 static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d,
788 struct net_device *dev = sc->sbm_dev;
789 struct sbdmadscr *dsc;
790 struct sbdmadscr *nextdsc;
791 struct sk_buff *sb_new = NULL;
792 int pktsize = ENET_PACKET_SIZE;
794 /* get pointer to our current place in the ring */
796 dsc = d->sbdma_addptr;
797 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
800 * figure out if the ring is full - if the next descriptor
801 * is the same as the one that we're going to remove from
802 * the ring, the ring is full
805 if (nextdsc == d->sbdma_remptr) {
810 * Allocate a sk_buff if we don't already have one.
811 * If we do have an sk_buff, reset it so that it's empty.
813 * Note: sk_buffs don't seem to be guaranteed to have any sort
814 * of alignment when they are allocated. Therefore, allocate enough
815 * extra space to make sure that:
817 * 1. the data does not start in the middle of a cache line.
818 * 2. The data does not end in the middle of a cache line
819 * 3. The buffer can be aligned such that the IP addresses are
822 * Remember, the SOCs MAC writes whole cache lines at a time,
823 * without reading the old contents first. So, if the sk_buff's
824 * data portion starts in the middle of a cache line, the SOC
825 * DMA will trash the beginning (and ending) portions.
829 sb_new = netdev_alloc_skb(dev, ENET_PACKET_SIZE +
830 SMP_CACHE_BYTES * 2 +
835 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, NET_IP_ALIGN);
840 * nothing special to reinit buffer, it's already aligned
841 * and sb->data already points to a good place.
846 * fill in the descriptor
849 #ifdef CONFIG_SBMAC_COALESCE
851 * Do not interrupt per DMA transfer.
853 dsc->dscr_a = virt_to_phys(sb_new->data) |
854 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | 0;
856 dsc->dscr_a = virt_to_phys(sb_new->data) |
857 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) |
858 M_DMA_DSCRA_INTERRUPT;
861 /* receiving: no options */
865 * fill in the context
868 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
871 * point at next packet
874 d->sbdma_addptr = nextdsc;
877 * Give the buffer to the DMA engine.
880 __raw_writeq(1, d->sbdma_dscrcnt);
882 return 0; /* we did it */
885 /**********************************************************************
886 * SBDMA_ADD_TXBUFFER(d,sb)
888 * Add a transmit buffer to the specified DMA channel, causing a
892 * d - DMA channel descriptor
893 * sb - sk_buff to add
896 * 0 transmit queued successfully
897 * otherwise error code
898 ********************************************************************* */
901 static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *sb)
903 struct sbdmadscr *dsc;
904 struct sbdmadscr *nextdsc;
909 /* get pointer to our current place in the ring */
911 dsc = d->sbdma_addptr;
912 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
915 * figure out if the ring is full - if the next descriptor
916 * is the same as the one that we're going to remove from
917 * the ring, the ring is full
920 if (nextdsc == d->sbdma_remptr) {
925 * Under Linux, it's not necessary to copy/coalesce buffers
926 * like it is on NetBSD. We think they're all contiguous,
927 * but that may not be true for GBE.
933 * fill in the descriptor. Note that the number of cache
934 * blocks in the descriptor is the number of blocks
935 * *spanned*, so we need to add in the offset (if any)
936 * while doing the calculation.
939 phys = virt_to_phys(sb->data);
940 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
943 V_DMA_DSCRA_A_SIZE(ncb) |
944 #ifndef CONFIG_SBMAC_COALESCE
945 M_DMA_DSCRA_INTERRUPT |
949 /* transmitting: set outbound options and length */
951 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
952 V_DMA_DSCRB_PKT_SIZE(length);
955 * fill in the context
958 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
961 * point at next packet
964 d->sbdma_addptr = nextdsc;
967 * Give the buffer to the DMA engine.
970 __raw_writeq(1, d->sbdma_dscrcnt);
972 return 0; /* we did it */
978 /**********************************************************************
981 * Free all allocated sk_buffs on the specified DMA channel;
988 ********************************************************************* */
990 static void sbdma_emptyring(struct sbmacdma *d)
995 for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
996 sb = d->sbdma_ctxtable[idx];
999 d->sbdma_ctxtable[idx] = NULL;
1005 /**********************************************************************
1008 * Fill the specified DMA channel (must be receive channel)
1012 * sc - softc structure
1017 ********************************************************************* */
1019 static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d)
1023 for (idx = 0; idx < SBMAC_MAX_RXDESCR - 1; idx++) {
1024 if (sbdma_add_rcvbuffer(sc, d, NULL) != 0)
1029 #ifdef CONFIG_NET_POLL_CONTROLLER
1030 static void sbmac_netpoll(struct net_device *netdev)
1032 struct sbmac_softc *sc = netdev_priv(netdev);
1033 int irq = sc->sbm_dev->irq;
1035 __raw_writeq(0, sc->sbm_imr);
1037 sbmac_intr(irq, netdev);
1039 #ifdef CONFIG_SBMAC_COALESCE
1040 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1041 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
1044 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1045 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
1050 /**********************************************************************
1051 * SBDMA_RX_PROCESS(sc,d,work_to_do,poll)
1053 * Process "completed" receive buffers on the specified DMA channel.
1056 * sc - softc structure
1057 * d - DMA channel context
1058 * work_to_do - no. of packets to process before enabling interrupt
1060 * poll - 1: using polling (for NAPI)
1064 ********************************************************************* */
1066 static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
1067 int work_to_do, int poll)
1069 struct net_device *dev = sc->sbm_dev;
1072 struct sbdmadscr *dsc;
1081 /* Check if the HW dropped any frames */
1082 dev->stats.rx_fifo_errors
1083 += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff;
1084 __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost);
1086 while (work_to_do-- > 0) {
1088 * figure out where we are (as an index) and where
1089 * the hardware is (also as an index)
1091 * This could be done faster if (for example) the
1092 * descriptor table was page-aligned and contiguous in
1093 * both virtual and physical memory -- you could then
1094 * just compare the low-order bits of the virtual address
1095 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1098 dsc = d->sbdma_remptr;
1099 curidx = dsc - d->sbdma_dscrtable;
1102 prefetch(&d->sbdma_ctxtable[curidx]);
1104 hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1105 d->sbdma_dscrtable_phys) /
1106 sizeof(*d->sbdma_dscrtable);
1109 * If they're the same, that means we've processed all
1110 * of the descriptors up to (but not including) the one that
1111 * the hardware is working on right now.
1114 if (curidx == hwidx)
1118 * Otherwise, get the packet's sk_buff ptr back
1121 sb = d->sbdma_ctxtable[curidx];
1122 d->sbdma_ctxtable[curidx] = NULL;
1124 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1127 * Check packet status. If good, process it.
1128 * If not, silently drop it and put it back on the
1132 if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) {
1135 * Add a new buffer to replace the old one. If we fail
1136 * to allocate a buffer, we're going to drop this
1137 * packet and put it right back on the receive ring.
1140 if (unlikely(sbdma_add_rcvbuffer(sc, d, NULL) ==
1142 dev->stats.rx_dropped++;
1143 /* Re-add old buffer */
1144 sbdma_add_rcvbuffer(sc, d, sb);
1145 /* No point in continuing at the moment */
1146 printk(KERN_ERR "dropped packet (1)\n");
1147 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1151 * Set length into the packet
1156 * Buffer has been replaced on the
1157 * receive ring. Pass the buffer to
1160 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1161 /* Check hw IPv4/TCP checksum if supported */
1162 if (sc->rx_hw_checksum == ENABLE) {
1163 if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1164 !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1165 sb->ip_summed = CHECKSUM_UNNECESSARY;
1166 /* don't need to set sb->csum */
1168 skb_checksum_none_assert(sb);
1172 prefetch((const void *)(((char *)sb->data)+32));
1174 dropped = netif_receive_skb(sb);
1176 dropped = netif_rx(sb);
1178 if (dropped == NET_RX_DROP) {
1179 dev->stats.rx_dropped++;
1180 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1184 dev->stats.rx_bytes += len;
1185 dev->stats.rx_packets++;
1190 * Packet was mangled somehow. Just drop it and
1191 * put it back on the receive ring.
1193 dev->stats.rx_errors++;
1194 sbdma_add_rcvbuffer(sc, d, sb);
1199 * .. and advance to the next buffer.
1202 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1207 goto again; /* collect fifo drop statistics again */
1213 /**********************************************************************
1214 * SBDMA_TX_PROCESS(sc,d)
1216 * Process "completed" transmit buffers on the specified DMA channel.
1217 * This is normally called within the interrupt service routine.
1218 * Note that this isn't really ideal for priority channels, since
1219 * it processes all of the packets on a given channel before
1223 * sc - softc structure
1224 * d - DMA channel context
1225 * poll - 1: using polling (for NAPI)
1229 ********************************************************************* */
1231 static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
1234 struct net_device *dev = sc->sbm_dev;
1237 struct sbdmadscr *dsc;
1239 unsigned long flags;
1240 int packets_handled = 0;
1242 spin_lock_irqsave(&(sc->sbm_lock), flags);
1244 if (d->sbdma_remptr == d->sbdma_addptr)
1247 hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1248 d->sbdma_dscrtable_phys) / sizeof(*d->sbdma_dscrtable);
1252 * figure out where we are (as an index) and where
1253 * the hardware is (also as an index)
1255 * This could be done faster if (for example) the
1256 * descriptor table was page-aligned and contiguous in
1257 * both virtual and physical memory -- you could then
1258 * just compare the low-order bits of the virtual address
1259 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1262 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1265 * If they're the same, that means we've processed all
1266 * of the descriptors up to (but not including) the one that
1267 * the hardware is working on right now.
1270 if (curidx == hwidx)
1274 * Otherwise, get the packet's sk_buff ptr back
1277 dsc = &(d->sbdma_dscrtable[curidx]);
1278 sb = d->sbdma_ctxtable[curidx];
1279 d->sbdma_ctxtable[curidx] = NULL;
1285 dev->stats.tx_bytes += sb->len;
1286 dev->stats.tx_packets++;
1289 * for transmits, we just free buffers.
1292 dev_kfree_skb_irq(sb);
1295 * .. and advance to the next buffer.
1298 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1305 * Decide if we should wake up the protocol or not.
1306 * Other drivers seem to do this when we reach a low
1307 * watermark on the transmit queue.
1310 if (packets_handled)
1311 netif_wake_queue(d->sbdma_eth->sbm_dev);
1314 spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1320 /**********************************************************************
1323 * Initialize an Ethernet context structure - this is called
1324 * once per MAC on the 1250. Memory is allocated here, so don't
1325 * call it again from inside the ioctl routines that bring the
1329 * s - sbmac context structure
1333 ********************************************************************* */
1335 static int sbmac_initctx(struct sbmac_softc *s)
1339 * figure out the addresses of some ports
1342 s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1343 s->sbm_maccfg = s->sbm_base + R_MAC_CFG;
1344 s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG;
1345 s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG;
1346 s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG;
1347 s->sbm_isr = s->sbm_base + R_MAC_STATUS;
1348 s->sbm_imr = s->sbm_base + R_MAC_INT_MASK;
1349 s->sbm_mdio = s->sbm_base + R_MAC_MDIO;
1352 * Initialize the DMA channels. Right now, only one per MAC is used
1353 * Note: Only do this _once_, as it allocates memory from the kernel!
1356 sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1357 sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1360 * initial state is OFF
1363 s->sbm_state = sbmac_state_off;
1369 static void sbdma_uninitctx(struct sbmacdma *d)
1371 if (d->sbdma_dscrtable_unaligned) {
1372 kfree(d->sbdma_dscrtable_unaligned);
1373 d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL;
1376 if (d->sbdma_ctxtable) {
1377 kfree(d->sbdma_ctxtable);
1378 d->sbdma_ctxtable = NULL;
1383 static void sbmac_uninitctx(struct sbmac_softc *sc)
1385 sbdma_uninitctx(&(sc->sbm_txdma));
1386 sbdma_uninitctx(&(sc->sbm_rxdma));
1390 /**********************************************************************
1391 * SBMAC_CHANNEL_START(s)
1393 * Start packet processing on this MAC.
1396 * s - sbmac structure
1400 ********************************************************************* */
1402 static void sbmac_channel_start(struct sbmac_softc *s)
1406 uint64_t cfg,fifo,framecfg;
1410 * Don't do this if running
1413 if (s->sbm_state == sbmac_state_on)
1417 * Bring the controller out of reset, but leave it off.
1420 __raw_writeq(0, s->sbm_macenable);
1423 * Ignore all received packets
1426 __raw_writeq(0, s->sbm_rxfilter);
1429 * Calculate values for various control registers.
1432 cfg = M_MAC_RETRY_EN |
1433 M_MAC_TX_HOLD_SOP_EN |
1434 V_MAC_TX_PAUSE_CNT_16K |
1441 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1442 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1443 * Use a larger RD_THRSH for gigabit
1445 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
1450 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
1451 ((s->sbm_speed == sbmac_speed_1000)
1452 ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1453 V_MAC_TX_RL_THRSH(4) |
1454 V_MAC_RX_PL_THRSH(4) |
1455 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */
1456 V_MAC_RX_RL_THRSH(8) |
1459 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1460 V_MAC_MAX_FRAMESZ_DEFAULT |
1461 V_MAC_BACKOFF_SEL(1);
1464 * Clear out the hash address map
1467 port = s->sbm_base + R_MAC_HASH_BASE;
1468 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1469 __raw_writeq(0, port);
1470 port += sizeof(uint64_t);
1474 * Clear out the exact-match table
1477 port = s->sbm_base + R_MAC_ADDR_BASE;
1478 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1479 __raw_writeq(0, port);
1480 port += sizeof(uint64_t);
1484 * Clear out the DMA Channel mapping table registers
1487 port = s->sbm_base + R_MAC_CHUP0_BASE;
1488 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1489 __raw_writeq(0, port);
1490 port += sizeof(uint64_t);
1494 port = s->sbm_base + R_MAC_CHLO0_BASE;
1495 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1496 __raw_writeq(0, port);
1497 port += sizeof(uint64_t);
1501 * Program the hardware address. It goes into the hardware-address
1502 * register as well as the first filter register.
1505 reg = sbmac_addr2reg(s->sbm_hwaddr);
1507 port = s->sbm_base + R_MAC_ADDR_BASE;
1508 __raw_writeq(reg, port);
1509 port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1511 __raw_writeq(reg, port);
1514 * Set the receive filter for no packets, and write values
1515 * to the various config registers
1518 __raw_writeq(0, s->sbm_rxfilter);
1519 __raw_writeq(0, s->sbm_imr);
1520 __raw_writeq(framecfg, s->sbm_framecfg);
1521 __raw_writeq(fifo, s->sbm_fifocfg);
1522 __raw_writeq(cfg, s->sbm_maccfg);
1525 * Initialize DMA channels (rings should be ok now)
1528 sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1529 sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1532 * Configure the speed, duplex, and flow control
1535 sbmac_set_speed(s,s->sbm_speed);
1536 sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1539 * Fill the receive ring
1542 sbdma_fillring(s, &(s->sbm_rxdma));
1545 * Turn on the rest of the bits in the enable register
1548 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
1549 __raw_writeq(M_MAC_RXDMA_EN0 |
1550 M_MAC_TXDMA_EN0, s->sbm_macenable);
1551 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
1552 __raw_writeq(M_MAC_RXDMA_EN0 |
1555 M_MAC_TX_ENABLE, s->sbm_macenable);
1557 #error invalid SiByte MAC configuration
1560 #ifdef CONFIG_SBMAC_COALESCE
1561 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1562 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1564 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1565 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1569 * Enable receiving unicasts and broadcasts
1572 __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
1575 * we're running now.
1578 s->sbm_state = sbmac_state_on;
1581 * Program multicast addresses
1587 * If channel was in promiscuous mode before, turn that on
1590 if (s->sbm_devflags & IFF_PROMISC) {
1591 sbmac_promiscuous_mode(s,1);
1597 /**********************************************************************
1598 * SBMAC_CHANNEL_STOP(s)
1600 * Stop packet processing on this MAC.
1603 * s - sbmac structure
1607 ********************************************************************* */
1609 static void sbmac_channel_stop(struct sbmac_softc *s)
1611 /* don't do this if already stopped */
1613 if (s->sbm_state == sbmac_state_off)
1616 /* don't accept any packets, disable all interrupts */
1618 __raw_writeq(0, s->sbm_rxfilter);
1619 __raw_writeq(0, s->sbm_imr);
1621 /* Turn off ticker */
1625 /* turn off receiver and transmitter */
1627 __raw_writeq(0, s->sbm_macenable);
1629 /* We're stopped now. */
1631 s->sbm_state = sbmac_state_off;
1634 * Stop DMA channels (rings should be ok now)
1637 sbdma_channel_stop(&(s->sbm_rxdma));
1638 sbdma_channel_stop(&(s->sbm_txdma));
1640 /* Empty the receive and transmit rings */
1642 sbdma_emptyring(&(s->sbm_rxdma));
1643 sbdma_emptyring(&(s->sbm_txdma));
1647 /**********************************************************************
1648 * SBMAC_SET_CHANNEL_STATE(state)
1650 * Set the channel's state ON or OFF
1657 ********************************************************************* */
1658 static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *sc,
1659 enum sbmac_state state)
1661 enum sbmac_state oldstate = sc->sbm_state;
1664 * If same as previous state, return
1667 if (state == oldstate) {
1672 * If new state is ON, turn channel on
1675 if (state == sbmac_state_on) {
1676 sbmac_channel_start(sc);
1679 sbmac_channel_stop(sc);
1683 * Return previous state
1690 /**********************************************************************
1691 * SBMAC_PROMISCUOUS_MODE(sc,onoff)
1693 * Turn on or off promiscuous mode
1697 * onoff - 1 to turn on, 0 to turn off
1701 ********************************************************************* */
1703 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1707 if (sc->sbm_state != sbmac_state_on)
1711 reg = __raw_readq(sc->sbm_rxfilter);
1712 reg |= M_MAC_ALLPKT_EN;
1713 __raw_writeq(reg, sc->sbm_rxfilter);
1716 reg = __raw_readq(sc->sbm_rxfilter);
1717 reg &= ~M_MAC_ALLPKT_EN;
1718 __raw_writeq(reg, sc->sbm_rxfilter);
1722 /**********************************************************************
1723 * SBMAC_SETIPHDR_OFFSET(sc,onoff)
1725 * Set the iphdr offset as 15 assuming ethernet encapsulation
1732 ********************************************************************* */
1734 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1738 /* Hard code the off set to 15 for now */
1739 reg = __raw_readq(sc->sbm_rxfilter);
1740 reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1741 __raw_writeq(reg, sc->sbm_rxfilter);
1743 /* BCM1250 pass1 didn't have hardware checksum. Everything
1745 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
1746 sc->rx_hw_checksum = DISABLE;
1748 sc->rx_hw_checksum = ENABLE;
1753 /**********************************************************************
1754 * SBMAC_ADDR2REG(ptr)
1756 * Convert six bytes into the 64-bit register value that
1757 * we typically write into the SBMAC's address/mcast registers
1760 * ptr - pointer to 6 bytes
1764 ********************************************************************* */
1766 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1772 reg |= (uint64_t) *(--ptr);
1774 reg |= (uint64_t) *(--ptr);
1776 reg |= (uint64_t) *(--ptr);
1778 reg |= (uint64_t) *(--ptr);
1780 reg |= (uint64_t) *(--ptr);
1782 reg |= (uint64_t) *(--ptr);
1788 /**********************************************************************
1789 * SBMAC_SET_SPEED(s,speed)
1791 * Configure LAN speed for the specified MAC.
1792 * Warning: must be called when MAC is off!
1795 * s - sbmac structure
1796 * speed - speed to set MAC to (see enum sbmac_speed)
1800 * 0 indicates invalid parameters
1801 ********************************************************************* */
1803 static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed)
1809 * Save new current values
1812 s->sbm_speed = speed;
1814 if (s->sbm_state == sbmac_state_on)
1815 return 0; /* save for next restart */
1818 * Read current register values
1821 cfg = __raw_readq(s->sbm_maccfg);
1822 framecfg = __raw_readq(s->sbm_framecfg);
1825 * Mask out the stuff we want to change
1828 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1829 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1833 * Now add in the new bits
1837 case sbmac_speed_10:
1838 framecfg |= V_MAC_IFG_RX_10 |
1840 K_MAC_IFG_THRSH_10 |
1842 cfg |= V_MAC_SPEED_SEL_10MBPS;
1845 case sbmac_speed_100:
1846 framecfg |= V_MAC_IFG_RX_100 |
1848 V_MAC_IFG_THRSH_100 |
1849 V_MAC_SLOT_SIZE_100;
1850 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1853 case sbmac_speed_1000:
1854 framecfg |= V_MAC_IFG_RX_1000 |
1856 V_MAC_IFG_THRSH_1000 |
1857 V_MAC_SLOT_SIZE_1000;
1858 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1866 * Send the bits back to the hardware
1869 __raw_writeq(framecfg, s->sbm_framecfg);
1870 __raw_writeq(cfg, s->sbm_maccfg);
1875 /**********************************************************************
1876 * SBMAC_SET_DUPLEX(s,duplex,fc)
1878 * Set Ethernet duplex and flow control options for this MAC
1879 * Warning: must be called when MAC is off!
1882 * s - sbmac structure
1883 * duplex - duplex setting (see enum sbmac_duplex)
1884 * fc - flow control setting (see enum sbmac_fc)
1888 * 0 if an invalid parameter combination was specified
1889 ********************************************************************* */
1891 static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
1897 * Save new current values
1900 s->sbm_duplex = duplex;
1903 if (s->sbm_state == sbmac_state_on)
1904 return 0; /* save for next restart */
1907 * Read current register values
1910 cfg = __raw_readq(s->sbm_maccfg);
1913 * Mask off the stuff we're about to change
1916 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
1920 case sbmac_duplex_half:
1922 case sbmac_fc_disabled:
1923 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
1926 case sbmac_fc_collision:
1927 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
1930 case sbmac_fc_carrier:
1931 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
1934 case sbmac_fc_frame: /* not valid in half duplex */
1935 default: /* invalid selection */
1940 case sbmac_duplex_full:
1942 case sbmac_fc_disabled:
1943 cfg |= V_MAC_FC_CMD_DISABLED;
1946 case sbmac_fc_frame:
1947 cfg |= V_MAC_FC_CMD_ENABLED;
1950 case sbmac_fc_collision: /* not valid in full duplex */
1951 case sbmac_fc_carrier: /* not valid in full duplex */
1961 * Send the bits back to the hardware
1964 __raw_writeq(cfg, s->sbm_maccfg);
1972 /**********************************************************************
1975 * Interrupt handler for MAC interrupts
1982 ********************************************************************* */
1983 static irqreturn_t sbmac_intr(int irq,void *dev_instance)
1985 struct net_device *dev = (struct net_device *) dev_instance;
1986 struct sbmac_softc *sc = netdev_priv(dev);
1991 * Read the ISR (this clears the bits in the real
1992 * register, except for counter addr)
1995 isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
1998 return IRQ_RETVAL(0);
2002 * Transmits on channel 0
2005 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0))
2006 sbdma_tx_process(sc,&(sc->sbm_txdma), 0);
2008 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2009 if (napi_schedule_prep(&sc->napi)) {
2010 __raw_writeq(0, sc->sbm_imr);
2011 __napi_schedule(&sc->napi);
2012 /* Depend on the exit from poll to reenable intr */
2015 /* may leave some packets behind */
2016 sbdma_rx_process(sc,&(sc->sbm_rxdma),
2017 SBMAC_MAX_RXDESCR * 2, 0);
2020 return IRQ_RETVAL(handled);
2023 /**********************************************************************
2024 * SBMAC_START_TX(skb,dev)
2026 * Start output on the specified interface. Basically, we
2027 * queue as many buffers as we can until the ring fills up, or
2028 * we run off the end of the queue, whichever comes first.
2035 ********************************************************************* */
2036 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2038 struct sbmac_softc *sc = netdev_priv(dev);
2039 unsigned long flags;
2042 spin_lock_irqsave(&sc->sbm_lock, flags);
2045 * Put the buffer on the transmit ring. If we
2046 * don't have room, stop the queue.
2049 if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2050 /* XXX save skb that we could not send */
2051 netif_stop_queue(dev);
2052 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2054 return NETDEV_TX_BUSY;
2057 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2059 return NETDEV_TX_OK;
2062 /**********************************************************************
2063 * SBMAC_SETMULTI(sc)
2065 * Reprogram the multicast table into the hardware, given
2066 * the list of multicasts associated with the interface
2074 ********************************************************************* */
2076 static void sbmac_setmulti(struct sbmac_softc *sc)
2081 struct netdev_hw_addr *ha;
2082 struct net_device *dev = sc->sbm_dev;
2085 * Clear out entire multicast table. We do this by nuking
2086 * the entire hash table and all the direct matches except
2087 * the first one, which is used for our station address
2090 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2091 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2092 __raw_writeq(0, port);
2095 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2096 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2097 __raw_writeq(0, port);
2101 * Clear the filter to say we don't want any multicasts.
2104 reg = __raw_readq(sc->sbm_rxfilter);
2105 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2106 __raw_writeq(reg, sc->sbm_rxfilter);
2108 if (dev->flags & IFF_ALLMULTI) {
2110 * Enable ALL multicasts. Do this by inverting the
2111 * multicast enable bit.
2113 reg = __raw_readq(sc->sbm_rxfilter);
2114 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2115 __raw_writeq(reg, sc->sbm_rxfilter);
2121 * Progam new multicast entries. For now, only use the
2122 * perfect filter. In the future we'll need to use the
2123 * hash filter if the perfect filter overflows
2126 /* XXX only using perfect filter for now, need to use hash
2127 * XXX if the table overflows */
2129 idx = 1; /* skip station address */
2130 netdev_for_each_mc_addr(ha, dev) {
2131 if (idx == MAC_ADDR_COUNT)
2133 reg = sbmac_addr2reg(ha->addr);
2134 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2135 __raw_writeq(reg, port);
2140 * Enable the "accept multicast bits" if we programmed at least one
2145 reg = __raw_readq(sc->sbm_rxfilter);
2146 reg |= M_MAC_MCAST_EN;
2147 __raw_writeq(reg, sc->sbm_rxfilter);
2151 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2153 if (new_mtu > ENET_PACKET_SIZE)
2155 _dev->mtu = new_mtu;
2156 pr_info("changing the mtu to %d\n", new_mtu);
2160 static const struct net_device_ops sbmac_netdev_ops = {
2161 .ndo_open = sbmac_open,
2162 .ndo_stop = sbmac_close,
2163 .ndo_start_xmit = sbmac_start_tx,
2164 .ndo_set_rx_mode = sbmac_set_rx_mode,
2165 .ndo_tx_timeout = sbmac_tx_timeout,
2166 .ndo_do_ioctl = sbmac_mii_ioctl,
2167 .ndo_change_mtu = sb1250_change_mtu,
2168 .ndo_validate_addr = eth_validate_addr,
2169 .ndo_set_mac_address = eth_mac_addr,
2170 #ifdef CONFIG_NET_POLL_CONTROLLER
2171 .ndo_poll_controller = sbmac_netpoll,
2175 /**********************************************************************
2178 * Attach routine - init hardware and hook ourselves into linux
2181 * dev - net_device structure
2185 ********************************************************************* */
2187 static int sbmac_init(struct platform_device *pldev, long long base)
2189 struct net_device *dev = platform_get_drvdata(pldev);
2190 int idx = pldev->id;
2191 struct sbmac_softc *sc = netdev_priv(dev);
2192 unsigned char *eaddr;
2200 eaddr = sc->sbm_hwaddr;
2203 * Read the ethernet address. The firmware left this programmed
2204 * for us in the ethernet address register for each mac.
2207 ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2208 __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2209 for (i = 0; i < 6; i++) {
2210 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2214 for (i = 0; i < 6; i++) {
2215 dev->dev_addr[i] = eaddr[i];
2219 * Initialize context (get pointers to registers and stuff), then
2220 * allocate the memory for the descriptor tables.
2226 * Set up Linux device callins
2229 spin_lock_init(&(sc->sbm_lock));
2231 dev->netdev_ops = &sbmac_netdev_ops;
2232 dev->watchdog_timeo = TX_TIMEOUT;
2234 netif_napi_add(dev, &sc->napi, sbmac_poll, 16);
2236 dev->irq = UNIT_INT(idx);
2238 /* This is needed for PASS2 for Rx H/W checksum feature */
2239 sbmac_set_iphdr_offset(sc);
2241 sc->mii_bus = mdiobus_alloc();
2242 if (sc->mii_bus == NULL) {
2247 sc->mii_bus->name = sbmac_mdio_string;
2248 snprintf(sc->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2250 sc->mii_bus->priv = sc;
2251 sc->mii_bus->read = sbmac_mii_read;
2252 sc->mii_bus->write = sbmac_mii_write;
2253 sc->mii_bus->irq = sc->phy_irq;
2254 for (i = 0; i < PHY_MAX_ADDR; ++i)
2255 sc->mii_bus->irq[i] = SBMAC_PHY_INT;
2257 sc->mii_bus->parent = &pldev->dev;
2261 err = mdiobus_register(sc->mii_bus);
2263 printk(KERN_ERR "%s: unable to register MDIO bus\n",
2267 platform_set_drvdata(pldev, sc->mii_bus);
2269 err = register_netdev(dev);
2271 printk(KERN_ERR "%s.%d: unable to register netdev\n",
2276 pr_info("%s.%d: registered as %s\n", sbmac_string, idx, dev->name);
2278 if (sc->rx_hw_checksum == ENABLE)
2279 pr_info("%s: enabling TCP rcv checksum\n", dev->name);
2282 * Display Ethernet address (this is called during the config
2283 * process so we need to finish off the config message that
2284 * was being displayed)
2286 pr_info("%s: SiByte Ethernet at 0x%08Lx, address: %pM\n",
2287 dev->name, base, eaddr);
2291 mdiobus_unregister(sc->mii_bus);
2293 mdiobus_free(sc->mii_bus);
2295 sbmac_uninitctx(sc);
2300 static int sbmac_open(struct net_device *dev)
2302 struct sbmac_softc *sc = netdev_priv(dev);
2306 pr_debug("%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2309 * map/route interrupt (clear status first, in case something
2310 * weird is pending; we haven't initialized the mac registers
2314 __raw_readq(sc->sbm_isr);
2315 err = request_irq(dev->irq, sbmac_intr, IRQF_SHARED, dev->name, dev);
2317 printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name,
2322 sc->sbm_speed = sbmac_speed_none;
2323 sc->sbm_duplex = sbmac_duplex_none;
2324 sc->sbm_fc = sbmac_fc_none;
2331 err = sbmac_mii_probe(dev);
2333 goto out_unregister;
2336 * Turn on the channel
2339 sbmac_set_channel_state(sc,sbmac_state_on);
2341 netif_start_queue(dev);
2343 sbmac_set_rx_mode(dev);
2345 phy_start(sc->phy_dev);
2347 napi_enable(&sc->napi);
2352 free_irq(dev->irq, dev);
2357 static int sbmac_mii_probe(struct net_device *dev)
2359 struct sbmac_softc *sc = netdev_priv(dev);
2360 struct phy_device *phy_dev;
2363 for (i = 0; i < PHY_MAX_ADDR; i++) {
2364 phy_dev = sc->mii_bus->phy_map[i];
2369 printk(KERN_ERR "%s: no PHY found\n", dev->name);
2373 phy_dev = phy_connect(dev, dev_name(&phy_dev->dev), &sbmac_mii_poll,
2374 PHY_INTERFACE_MODE_GMII);
2375 if (IS_ERR(phy_dev)) {
2376 printk(KERN_ERR "%s: could not attach to PHY\n", dev->name);
2377 return PTR_ERR(phy_dev);
2380 /* Remove any features not supported by the controller */
2381 phy_dev->supported &= SUPPORTED_10baseT_Half |
2382 SUPPORTED_10baseT_Full |
2383 SUPPORTED_100baseT_Half |
2384 SUPPORTED_100baseT_Full |
2385 SUPPORTED_1000baseT_Half |
2386 SUPPORTED_1000baseT_Full |
2390 SUPPORTED_Asym_Pause;
2391 phy_dev->advertising = phy_dev->supported;
2393 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2394 dev->name, phy_dev->drv->name,
2395 dev_name(&phy_dev->dev), phy_dev->irq);
2397 sc->phy_dev = phy_dev;
2403 static void sbmac_mii_poll(struct net_device *dev)
2405 struct sbmac_softc *sc = netdev_priv(dev);
2406 struct phy_device *phy_dev = sc->phy_dev;
2407 unsigned long flags;
2409 int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg;
2411 link_chg = (sc->sbm_link != phy_dev->link);
2412 speed_chg = (sc->sbm_speed != phy_dev->speed);
2413 duplex_chg = (sc->sbm_duplex != phy_dev->duplex);
2414 pause_chg = (sc->sbm_pause != phy_dev->pause);
2416 if (!link_chg && !speed_chg && !duplex_chg && !pause_chg)
2417 return; /* Hmmm... */
2419 if (!phy_dev->link) {
2421 sc->sbm_link = phy_dev->link;
2422 sc->sbm_speed = sbmac_speed_none;
2423 sc->sbm_duplex = sbmac_duplex_none;
2424 sc->sbm_fc = sbmac_fc_disabled;
2426 pr_info("%s: link unavailable\n", dev->name);
2431 if (phy_dev->duplex == DUPLEX_FULL) {
2433 fc = sbmac_fc_frame;
2435 fc = sbmac_fc_disabled;
2437 fc = sbmac_fc_collision;
2438 fc_chg = (sc->sbm_fc != fc);
2440 pr_info("%s: link available: %dbase-%cD\n", dev->name, phy_dev->speed,
2441 phy_dev->duplex == DUPLEX_FULL ? 'F' : 'H');
2443 spin_lock_irqsave(&sc->sbm_lock, flags);
2445 sc->sbm_speed = phy_dev->speed;
2446 sc->sbm_duplex = phy_dev->duplex;
2448 sc->sbm_pause = phy_dev->pause;
2449 sc->sbm_link = phy_dev->link;
2451 if ((speed_chg || duplex_chg || fc_chg) &&
2452 sc->sbm_state != sbmac_state_off) {
2454 * something changed, restart the channel
2457 pr_debug("%s: restarting channel "
2458 "because PHY state changed\n", dev->name);
2459 sbmac_channel_stop(sc);
2460 sbmac_channel_start(sc);
2463 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2467 static void sbmac_tx_timeout (struct net_device *dev)
2469 struct sbmac_softc *sc = netdev_priv(dev);
2470 unsigned long flags;
2472 spin_lock_irqsave(&sc->sbm_lock, flags);
2475 dev->trans_start = jiffies; /* prevent tx timeout */
2476 dev->stats.tx_errors++;
2478 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2480 printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2486 static void sbmac_set_rx_mode(struct net_device *dev)
2488 unsigned long flags;
2489 struct sbmac_softc *sc = netdev_priv(dev);
2491 spin_lock_irqsave(&sc->sbm_lock, flags);
2492 if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2494 * Promiscuous changed.
2497 if (dev->flags & IFF_PROMISC) {
2498 sbmac_promiscuous_mode(sc,1);
2501 sbmac_promiscuous_mode(sc,0);
2504 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2507 * Program the multicasts. Do this every time.
2514 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2516 struct sbmac_softc *sc = netdev_priv(dev);
2518 if (!netif_running(dev) || !sc->phy_dev)
2521 return phy_mii_ioctl(sc->phy_dev, rq, cmd);
2524 static int sbmac_close(struct net_device *dev)
2526 struct sbmac_softc *sc = netdev_priv(dev);
2528 napi_disable(&sc->napi);
2530 phy_stop(sc->phy_dev);
2532 sbmac_set_channel_state(sc, sbmac_state_off);
2534 netif_stop_queue(dev);
2537 pr_debug("%s: Shutting down ethercard\n", dev->name);
2539 phy_disconnect(sc->phy_dev);
2541 free_irq(dev->irq, dev);
2543 sbdma_emptyring(&(sc->sbm_txdma));
2544 sbdma_emptyring(&(sc->sbm_rxdma));
2549 static int sbmac_poll(struct napi_struct *napi, int budget)
2551 struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi);
2554 work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1);
2555 sbdma_tx_process(sc, &(sc->sbm_txdma), 1);
2557 if (work_done < budget) {
2558 napi_complete(napi);
2560 #ifdef CONFIG_SBMAC_COALESCE
2561 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
2562 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
2565 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
2566 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
2574 static int sbmac_probe(struct platform_device *pldev)
2576 struct net_device *dev;
2577 struct sbmac_softc *sc;
2578 void __iomem *sbm_base;
2579 struct resource *res;
2580 u64 sbmac_orig_hwaddr;
2583 res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
2585 sbm_base = ioremap_nocache(res->start, resource_size(res));
2587 printk(KERN_ERR "%s: unable to map device registers\n",
2588 dev_name(&pldev->dev));
2594 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2595 * value for us by the firmware if we're going to use this MAC.
2596 * If we find a zero, skip this MAC.
2598 sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR);
2599 pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", dev_name(&pldev->dev),
2600 sbmac_orig_hwaddr ? "" : "not ", (long long)res->start);
2601 if (sbmac_orig_hwaddr == 0) {
2607 * Okay, cool. Initialize this MAC.
2609 dev = alloc_etherdev(sizeof(struct sbmac_softc));
2615 platform_set_drvdata(pldev, dev);
2616 SET_NETDEV_DEV(dev, &pldev->dev);
2618 sc = netdev_priv(dev);
2619 sc->sbm_base = sbm_base;
2621 err = sbmac_init(pldev, res->start);
2629 __raw_writeq(sbmac_orig_hwaddr, sbm_base + R_MAC_ETHERNET_ADDR);
2638 static int __exit sbmac_remove(struct platform_device *pldev)
2640 struct net_device *dev = platform_get_drvdata(pldev);
2641 struct sbmac_softc *sc = netdev_priv(dev);
2643 unregister_netdev(dev);
2644 sbmac_uninitctx(sc);
2645 mdiobus_unregister(sc->mii_bus);
2646 mdiobus_free(sc->mii_bus);
2647 iounmap(sc->sbm_base);
2653 static struct platform_driver sbmac_driver = {
2654 .probe = sbmac_probe,
2655 .remove = __exit_p(sbmac_remove),
2657 .name = sbmac_string,
2661 module_platform_driver(sbmac_driver);