2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2013 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #include <linux/ssb/ssb_driver_gige.h>
48 #include <linux/hwmon.h>
49 #include <linux/hwmon-sysfs.h>
51 #include <net/checksum.h>
55 #include <asm/byteorder.h>
56 #include <linux/uaccess.h>
58 #include <uapi/linux/net_tstamp.h>
59 #include <linux/ptp_clock_kernel.h>
62 #include <asm/idprom.h>
71 /* Functions & macros to verify TG3_FLAGS types */
73 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
75 return test_bit(flag, bits);
78 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
83 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
85 clear_bit(flag, bits);
88 #define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92 #define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define DRV_MODULE_NAME "tg3"
97 #define TG3_MIN_NUM 136
98 #define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
100 #define DRV_MODULE_RELDATE "Jan 03, 2014"
102 #define RESET_KIND_SHUTDOWN 0
103 #define RESET_KIND_INIT 1
104 #define RESET_KIND_SUSPEND 2
106 #define TG3_DEF_RX_MODE 0
107 #define TG3_DEF_TX_MODE 0
108 #define TG3_DEF_MSG_ENABLE \
118 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
120 /* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
124 #define TG3_TX_TIMEOUT (5 * HZ)
126 /* hardware minimum and maximum for a single frame's data payload */
127 #define TG3_MIN_MTU 60
128 #define TG3_MAX_MTU(tp) \
129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
131 /* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
135 #define TG3_RX_STD_RING_SIZE(tp) \
136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
138 #define TG3_DEF_RX_RING_PENDING 200
139 #define TG3_RX_JMB_RING_SIZE(tp) \
140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
142 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
144 /* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
151 #define TG3_TX_RING_SIZE 512
152 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
154 #define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156 #define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158 #define TG3_RX_RCB_RING_BYTES(tp) \
159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
160 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
162 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
164 #define TG3_DMA_BYTE_ENAB 64
166 #define TG3_RX_STD_DMA_SZ 1536
167 #define TG3_RX_JMB_DMA_SZ 9046
169 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
171 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
174 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
177 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
180 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
191 #define TG3_RX_COPY_THRESHOLD 256
192 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
198 #if (NET_IP_ALIGN != 0)
199 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
201 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
206 #define TG3_TX_BD_DMA_MAX_2K 2048
207 #define TG3_TX_BD_DMA_MAX_4K 4096
209 #define TG3_RAW_IP_ALIGN 2
211 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
212 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
214 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
215 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
217 #define FIRMWARE_TG3 "tigon/tg3.bin"
218 #define FIRMWARE_TG357766 "tigon/tg357766.bin"
219 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
220 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
222 static char version[] =
223 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
225 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
226 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
227 MODULE_LICENSE("GPL");
228 MODULE_VERSION(DRV_MODULE_VERSION);
229 MODULE_FIRMWARE(FIRMWARE_TG3);
230 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
231 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
233 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
234 module_param(tg3_debug, int, 0);
235 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
237 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
240 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
263 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
264 TG3_DRV_DATA_FLAG_5705_10_100},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
267 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
268 TG3_DRV_DATA_FLAG_5705_10_100},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
275 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
281 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
289 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
290 PCI_VENDOR_ID_LENOVO,
291 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
295 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
318 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
319 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
323 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
333 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
335 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
348 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
354 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
359 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
361 static const struct {
362 const char string[ETH_GSTRING_LEN];
363 } ethtool_stats_keys[] = {
366 { "rx_ucast_packets" },
367 { "rx_mcast_packets" },
368 { "rx_bcast_packets" },
370 { "rx_align_errors" },
371 { "rx_xon_pause_rcvd" },
372 { "rx_xoff_pause_rcvd" },
373 { "rx_mac_ctrl_rcvd" },
374 { "rx_xoff_entered" },
375 { "rx_frame_too_long_errors" },
377 { "rx_undersize_packets" },
378 { "rx_in_length_errors" },
379 { "rx_out_length_errors" },
380 { "rx_64_or_less_octet_packets" },
381 { "rx_65_to_127_octet_packets" },
382 { "rx_128_to_255_octet_packets" },
383 { "rx_256_to_511_octet_packets" },
384 { "rx_512_to_1023_octet_packets" },
385 { "rx_1024_to_1522_octet_packets" },
386 { "rx_1523_to_2047_octet_packets" },
387 { "rx_2048_to_4095_octet_packets" },
388 { "rx_4096_to_8191_octet_packets" },
389 { "rx_8192_to_9022_octet_packets" },
396 { "tx_flow_control" },
398 { "tx_single_collisions" },
399 { "tx_mult_collisions" },
401 { "tx_excessive_collisions" },
402 { "tx_late_collisions" },
403 { "tx_collide_2times" },
404 { "tx_collide_3times" },
405 { "tx_collide_4times" },
406 { "tx_collide_5times" },
407 { "tx_collide_6times" },
408 { "tx_collide_7times" },
409 { "tx_collide_8times" },
410 { "tx_collide_9times" },
411 { "tx_collide_10times" },
412 { "tx_collide_11times" },
413 { "tx_collide_12times" },
414 { "tx_collide_13times" },
415 { "tx_collide_14times" },
416 { "tx_collide_15times" },
417 { "tx_ucast_packets" },
418 { "tx_mcast_packets" },
419 { "tx_bcast_packets" },
420 { "tx_carrier_sense_errors" },
424 { "dma_writeq_full" },
425 { "dma_write_prioq_full" },
429 { "rx_threshold_hit" },
431 { "dma_readq_full" },
432 { "dma_read_prioq_full" },
433 { "tx_comp_queue_full" },
435 { "ring_set_send_prod_index" },
436 { "ring_status_update" },
438 { "nic_avoided_irqs" },
439 { "nic_tx_threshold_hit" },
441 { "mbuf_lwm_thresh_hit" },
444 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
445 #define TG3_NVRAM_TEST 0
446 #define TG3_LINK_TEST 1
447 #define TG3_REGISTER_TEST 2
448 #define TG3_MEMORY_TEST 3
449 #define TG3_MAC_LOOPB_TEST 4
450 #define TG3_PHY_LOOPB_TEST 5
451 #define TG3_EXT_LOOPB_TEST 6
452 #define TG3_INTERRUPT_TEST 7
455 static const struct {
456 const char string[ETH_GSTRING_LEN];
457 } ethtool_test_keys[] = {
458 [TG3_NVRAM_TEST] = { "nvram test (online) " },
459 [TG3_LINK_TEST] = { "link test (online) " },
460 [TG3_REGISTER_TEST] = { "register test (offline)" },
461 [TG3_MEMORY_TEST] = { "memory test (offline)" },
462 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
463 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
464 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
465 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
468 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
471 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
473 writel(val, tp->regs + off);
476 static u32 tg3_read32(struct tg3 *tp, u32 off)
478 return readl(tp->regs + off);
481 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
483 writel(val, tp->aperegs + off);
486 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
488 return readl(tp->aperegs + off);
491 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
495 spin_lock_irqsave(&tp->indirect_lock, flags);
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
501 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
503 writel(val, tp->regs + off);
504 readl(tp->regs + off);
507 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
512 spin_lock_irqsave(&tp->indirect_lock, flags);
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
519 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
523 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
525 TG3_64BIT_REG_LOW, val);
528 if (off == TG3_RX_STD_PROD_IDX_REG) {
529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
530 TG3_64BIT_REG_LOW, val);
534 spin_lock_irqsave(&tp->indirect_lock, flags);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
537 spin_unlock_irqrestore(&tp->indirect_lock, flags);
539 /* In indirect mode when disabling interrupts, we also need
540 * to clear the interrupt bit in the GRC local ctrl register.
542 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
549 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
554 spin_lock_irqsave(&tp->indirect_lock, flags);
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
561 /* usec_wait specifies the wait time in usec when writing to certain registers
562 * where it is unsafe to read back the register without some delay.
563 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
564 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
566 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
569 /* Non-posted methods */
570 tp->write32(tp, off, val);
573 tg3_write32(tp, off, val);
578 /* Wait again after the read for the posted method to guarantee that
579 * the wait time is met.
585 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
587 tp->write32_mbox(tp, off, val);
588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
590 !tg3_flag(tp, ICH_WORKAROUND)))
591 tp->read32_mbox(tp, off);
594 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
596 void __iomem *mbox = tp->regs + off;
598 if (tg3_flag(tp, TXD_MBOX_HWBUG))
600 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
601 tg3_flag(tp, FLUSH_POSTED_WRITES))
605 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
607 return readl(tp->regs + off + GRCMBOX_BASE);
610 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
612 writel(val, tp->regs + off + GRCMBOX_BASE);
615 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
616 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
617 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
621 #define tw32(reg, val) tp->write32(tp, reg, val)
622 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624 #define tr32(reg) tp->read32(tp, reg)
626 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
630 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
631 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
634 spin_lock_irqsave(&tp->indirect_lock, flags);
635 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
639 /* Always leave this as zero. */
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
642 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
643 tw32_f(TG3PCI_MEM_WIN_DATA, val);
645 /* Always leave this as zero. */
646 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
648 spin_unlock_irqrestore(&tp->indirect_lock, flags);
651 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
655 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
656 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
661 spin_lock_irqsave(&tp->indirect_lock, flags);
662 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
666 /* Always leave this as zero. */
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
669 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
670 *val = tr32(TG3PCI_MEM_WIN_DATA);
672 /* Always leave this as zero. */
673 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
675 spin_unlock_irqrestore(&tp->indirect_lock, flags);
678 static void tg3_ape_lock_init(struct tg3 *tp)
683 if (tg3_asic_rev(tp) == ASIC_REV_5761)
684 regbase = TG3_APE_LOCK_GRANT;
686 regbase = TG3_APE_PER_LOCK_GRANT;
688 /* Make sure the driver hasn't any stale locks. */
689 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
691 case TG3_APE_LOCK_PHY0:
692 case TG3_APE_LOCK_PHY1:
693 case TG3_APE_LOCK_PHY2:
694 case TG3_APE_LOCK_PHY3:
695 bit = APE_LOCK_GRANT_DRIVER;
699 bit = APE_LOCK_GRANT_DRIVER;
701 bit = 1 << tp->pci_fn;
703 tg3_ape_write32(tp, regbase + 4 * i, bit);
708 static int tg3_ape_lock(struct tg3 *tp, int locknum)
712 u32 status, req, gnt, bit;
714 if (!tg3_flag(tp, ENABLE_APE))
718 case TG3_APE_LOCK_GPIO:
719 if (tg3_asic_rev(tp) == ASIC_REV_5761)
721 case TG3_APE_LOCK_GRC:
722 case TG3_APE_LOCK_MEM:
724 bit = APE_LOCK_REQ_DRIVER;
726 bit = 1 << tp->pci_fn;
728 case TG3_APE_LOCK_PHY0:
729 case TG3_APE_LOCK_PHY1:
730 case TG3_APE_LOCK_PHY2:
731 case TG3_APE_LOCK_PHY3:
732 bit = APE_LOCK_REQ_DRIVER;
738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
739 req = TG3_APE_LOCK_REQ;
740 gnt = TG3_APE_LOCK_GRANT;
742 req = TG3_APE_PER_LOCK_REQ;
743 gnt = TG3_APE_PER_LOCK_GRANT;
748 tg3_ape_write32(tp, req + off, bit);
750 /* Wait for up to 1 millisecond to acquire lock. */
751 for (i = 0; i < 100; i++) {
752 status = tg3_ape_read32(tp, gnt + off);
755 if (pci_channel_offline(tp->pdev))
762 /* Revoke the lock request. */
763 tg3_ape_write32(tp, gnt + off, bit);
770 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
774 if (!tg3_flag(tp, ENABLE_APE))
778 case TG3_APE_LOCK_GPIO:
779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
781 case TG3_APE_LOCK_GRC:
782 case TG3_APE_LOCK_MEM:
784 bit = APE_LOCK_GRANT_DRIVER;
786 bit = 1 << tp->pci_fn;
788 case TG3_APE_LOCK_PHY0:
789 case TG3_APE_LOCK_PHY1:
790 case TG3_APE_LOCK_PHY2:
791 case TG3_APE_LOCK_PHY3:
792 bit = APE_LOCK_GRANT_DRIVER;
798 if (tg3_asic_rev(tp) == ASIC_REV_5761)
799 gnt = TG3_APE_LOCK_GRANT;
801 gnt = TG3_APE_PER_LOCK_GRANT;
803 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
806 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
815 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
821 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
824 return timeout_us ? 0 : -EBUSY;
827 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
831 for (i = 0; i < timeout_us / 10; i++) {
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
834 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
840 return i == timeout_us / 10;
843 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
847 u32 i, bufoff, msgoff, maxlen, apedata;
849 if (!tg3_flag(tp, APE_HAS_NCSI))
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
853 if (apedata != APE_SEG_SIG_MAGIC)
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
857 if (!(apedata & APE_FW_STATUS_READY))
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
862 msgoff = bufoff + 2 * sizeof(u32);
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
868 /* Cap xfer sizes to scratchpad limits. */
869 length = (len > maxlen) ? maxlen : len;
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
873 if (!(apedata & APE_FW_STATUS_READY))
876 /* Wait for up to 1 msec for APE to service previous event. */
877 err = tg3_ape_event_lock(tp, 1000);
881 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
882 APE_EVENT_STATUS_SCRTCHPD_READ |
883 APE_EVENT_STATUS_EVENT_PENDING;
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
886 tg3_ape_write32(tp, bufoff, base_off);
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
894 if (tg3_ape_wait_for_event(tp, 30000))
897 for (i = 0; length; i += 4, length -= 4) {
898 u32 val = tg3_ape_read32(tp, msgoff + i);
899 memcpy(data, &val, sizeof(u32));
907 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
912 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
913 if (apedata != APE_SEG_SIG_MAGIC)
916 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
917 if (!(apedata & APE_FW_STATUS_READY))
920 /* Wait for up to 1 millisecond for APE to service previous event. */
921 err = tg3_ape_event_lock(tp, 1000);
925 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
926 event | APE_EVENT_STATUS_EVENT_PENDING);
928 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
929 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
934 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
939 if (!tg3_flag(tp, ENABLE_APE))
943 case RESET_KIND_INIT:
944 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
945 APE_HOST_SEG_SIG_MAGIC);
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
947 APE_HOST_SEG_LEN_MAGIC);
948 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
949 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
950 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
951 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
952 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
953 APE_HOST_BEHAV_NO_PHYLOCK);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
955 TG3_APE_HOST_DRVR_STATE_START);
957 event = APE_EVENT_STATUS_STATE_START;
959 case RESET_KIND_SHUTDOWN:
960 /* With the interface we are currently using,
961 * APE does not track driver state. Wiping
962 * out the HOST SEGMENT SIGNATURE forces
963 * the APE to assume OS absent status.
965 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
967 if (device_may_wakeup(&tp->pdev->dev) &&
968 tg3_flag(tp, WOL_ENABLE)) {
969 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
970 TG3_APE_HOST_WOL_SPEED_AUTO);
971 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
973 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
975 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
977 event = APE_EVENT_STATUS_STATE_UNLOAD;
983 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
985 tg3_ape_send_event(tp, event);
988 static void tg3_disable_ints(struct tg3 *tp)
992 tw32(TG3PCI_MISC_HOST_CTRL,
993 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
994 for (i = 0; i < tp->irq_max; i++)
995 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
998 static void tg3_enable_ints(struct tg3 *tp)
1005 tw32(TG3PCI_MISC_HOST_CTRL,
1006 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1008 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1009 for (i = 0; i < tp->irq_cnt; i++) {
1010 struct tg3_napi *tnapi = &tp->napi[i];
1012 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1013 if (tg3_flag(tp, 1SHOT_MSI))
1014 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1016 tp->coal_now |= tnapi->coal_now;
1019 /* Force an initial interrupt */
1020 if (!tg3_flag(tp, TAGGED_STATUS) &&
1021 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1022 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1024 tw32(HOSTCC_MODE, tp->coal_now);
1026 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1029 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1031 struct tg3 *tp = tnapi->tp;
1032 struct tg3_hw_status *sblk = tnapi->hw_status;
1033 unsigned int work_exists = 0;
1035 /* check for phy events */
1036 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1037 if (sblk->status & SD_STATUS_LINK_CHG)
1041 /* check for TX work to do */
1042 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1045 /* check for RX work to do */
1046 if (tnapi->rx_rcb_prod_idx &&
1047 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1054 * similar to tg3_enable_ints, but it accurately determines whether there
1055 * is new work pending and can return without flushing the PIO write
1056 * which reenables interrupts
1058 static void tg3_int_reenable(struct tg3_napi *tnapi)
1060 struct tg3 *tp = tnapi->tp;
1062 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1065 /* When doing tagged status, this work check is unnecessary.
1066 * The last_tag we write above tells the chip which piece of
1067 * work we've completed.
1069 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1070 tw32(HOSTCC_MODE, tp->coalesce_mode |
1071 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1074 static void tg3_switch_clocks(struct tg3 *tp)
1077 u32 orig_clock_ctrl;
1079 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1082 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1084 orig_clock_ctrl = clock_ctrl;
1085 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1086 CLOCK_CTRL_CLKRUN_OENABLE |
1088 tp->pci_clock_ctrl = clock_ctrl;
1090 if (tg3_flag(tp, 5705_PLUS)) {
1091 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1095 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1096 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1098 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1100 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1101 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1104 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1107 #define PHY_BUSY_LOOPS 5000
1109 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1116 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1118 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1122 tg3_ape_lock(tp, tp->phy_ape_lock);
1126 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1132 tw32_f(MAC_MI_COM, frame_val);
1134 loops = PHY_BUSY_LOOPS;
1135 while (loops != 0) {
1137 frame_val = tr32(MAC_MI_COM);
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1141 frame_val = tr32(MAC_MI_COM);
1149 *val = frame_val & MI_COM_DATA_MASK;
1153 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1154 tw32_f(MAC_MI_MODE, tp->mi_mode);
1158 tg3_ape_unlock(tp, tp->phy_ape_lock);
1163 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1165 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1168 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1176 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1179 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1181 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1185 tg3_ape_lock(tp, tp->phy_ape_lock);
1187 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1188 MI_COM_PHY_ADDR_MASK);
1189 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1190 MI_COM_REG_ADDR_MASK);
1191 frame_val |= (val & MI_COM_DATA_MASK);
1192 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1194 tw32_f(MAC_MI_COM, frame_val);
1196 loops = PHY_BUSY_LOOPS;
1197 while (loops != 0) {
1199 frame_val = tr32(MAC_MI_COM);
1200 if ((frame_val & MI_COM_BUSY) == 0) {
1202 frame_val = tr32(MAC_MI_COM);
1212 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1213 tw32_f(MAC_MI_MODE, tp->mi_mode);
1217 tg3_ape_unlock(tp, tp->phy_ape_lock);
1222 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1224 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1227 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1240 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1250 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1263 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1267 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1273 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1279 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1284 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1295 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1300 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1301 MII_TG3_AUXCTL_SHDWSEL_MISC);
1303 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1308 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1310 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1311 set |= MII_TG3_AUXCTL_MISC_WREN;
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1316 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1321 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1327 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1329 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1331 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1332 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1337 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1340 reg | val | MII_TG3_MISC_SHDW_WREN);
1343 static int tg3_bmcr_reset(struct tg3 *tp)
1348 /* OK, reset it, and poll the BMCR_RESET bit until it
1349 * clears or we time out.
1351 phy_control = BMCR_RESET;
1352 err = tg3_writephy(tp, MII_BMCR, phy_control);
1358 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1362 if ((phy_control & BMCR_RESET) == 0) {
1374 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1376 struct tg3 *tp = bp->priv;
1379 spin_lock_bh(&tp->lock);
1381 if (__tg3_readphy(tp, mii_id, reg, &val))
1384 spin_unlock_bh(&tp->lock);
1389 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1391 struct tg3 *tp = bp->priv;
1394 spin_lock_bh(&tp->lock);
1396 if (__tg3_writephy(tp, mii_id, reg, val))
1399 spin_unlock_bh(&tp->lock);
1404 static int tg3_mdio_reset(struct mii_bus *bp)
1409 static void tg3_mdio_config_5785(struct tg3 *tp)
1412 struct phy_device *phydev;
1414 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1415 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1416 case PHY_ID_BCM50610:
1417 case PHY_ID_BCM50610M:
1418 val = MAC_PHYCFG2_50610_LED_MODES;
1420 case PHY_ID_BCMAC131:
1421 val = MAC_PHYCFG2_AC131_LED_MODES;
1423 case PHY_ID_RTL8211C:
1424 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1426 case PHY_ID_RTL8201E:
1427 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1433 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1434 tw32(MAC_PHYCFG2, val);
1436 val = tr32(MAC_PHYCFG1);
1437 val &= ~(MAC_PHYCFG1_RGMII_INT |
1438 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1439 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1440 tw32(MAC_PHYCFG1, val);
1445 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1446 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1447 MAC_PHYCFG2_FMODE_MASK_MASK |
1448 MAC_PHYCFG2_GMODE_MASK_MASK |
1449 MAC_PHYCFG2_ACT_MASK_MASK |
1450 MAC_PHYCFG2_QUAL_MASK_MASK |
1451 MAC_PHYCFG2_INBAND_ENABLE;
1453 tw32(MAC_PHYCFG2, val);
1455 val = tr32(MAC_PHYCFG1);
1456 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1457 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1458 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1459 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1460 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1461 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1462 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1464 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1465 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1466 tw32(MAC_PHYCFG1, val);
1468 val = tr32(MAC_EXT_RGMII_MODE);
1469 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1470 MAC_RGMII_MODE_RX_QUALITY |
1471 MAC_RGMII_MODE_RX_ACTIVITY |
1472 MAC_RGMII_MODE_RX_ENG_DET |
1473 MAC_RGMII_MODE_TX_ENABLE |
1474 MAC_RGMII_MODE_TX_LOWPWR |
1475 MAC_RGMII_MODE_TX_RESET);
1476 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1477 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1478 val |= MAC_RGMII_MODE_RX_INT_B |
1479 MAC_RGMII_MODE_RX_QUALITY |
1480 MAC_RGMII_MODE_RX_ACTIVITY |
1481 MAC_RGMII_MODE_RX_ENG_DET;
1482 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1483 val |= MAC_RGMII_MODE_TX_ENABLE |
1484 MAC_RGMII_MODE_TX_LOWPWR |
1485 MAC_RGMII_MODE_TX_RESET;
1487 tw32(MAC_EXT_RGMII_MODE, val);
1490 static void tg3_mdio_start(struct tg3 *tp)
1492 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1493 tw32_f(MAC_MI_MODE, tp->mi_mode);
1496 if (tg3_flag(tp, MDIOBUS_INITED) &&
1497 tg3_asic_rev(tp) == ASIC_REV_5785)
1498 tg3_mdio_config_5785(tp);
1501 static int tg3_mdio_init(struct tg3 *tp)
1505 struct phy_device *phydev;
1507 if (tg3_flag(tp, 5717_PLUS)) {
1510 tp->phy_addr = tp->pci_fn + 1;
1512 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1513 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1515 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1516 TG3_CPMU_PHY_STRAP_IS_SERDES;
1519 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1522 addr = ssb_gige_get_phyaddr(tp->pdev);
1525 tp->phy_addr = addr;
1527 tp->phy_addr = TG3_PHY_MII_ADDR;
1531 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1534 tp->mdio_bus = mdiobus_alloc();
1535 if (tp->mdio_bus == NULL)
1538 tp->mdio_bus->name = "tg3 mdio bus";
1539 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1540 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1541 tp->mdio_bus->priv = tp;
1542 tp->mdio_bus->parent = &tp->pdev->dev;
1543 tp->mdio_bus->read = &tg3_mdio_read;
1544 tp->mdio_bus->write = &tg3_mdio_write;
1545 tp->mdio_bus->reset = &tg3_mdio_reset;
1546 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1547 tp->mdio_bus->irq = &tp->mdio_irq[0];
1549 for (i = 0; i < PHY_MAX_ADDR; i++)
1550 tp->mdio_bus->irq[i] = PHY_POLL;
1552 /* The bus registration will look for all the PHYs on the mdio bus.
1553 * Unfortunately, it does not ensure the PHY is powered up before
1554 * accessing the PHY ID registers. A chip reset is the
1555 * quickest way to bring the device back to an operational state..
1557 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1560 i = mdiobus_register(tp->mdio_bus);
1562 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1563 mdiobus_free(tp->mdio_bus);
1567 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1569 if (!phydev || !phydev->drv) {
1570 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1571 mdiobus_unregister(tp->mdio_bus);
1572 mdiobus_free(tp->mdio_bus);
1576 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1577 case PHY_ID_BCM57780:
1578 phydev->interface = PHY_INTERFACE_MODE_GMII;
1579 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1581 case PHY_ID_BCM50610:
1582 case PHY_ID_BCM50610M:
1583 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1584 PHY_BRCM_RX_REFCLK_UNUSED |
1585 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1586 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1587 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1588 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1589 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1590 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1591 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1592 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1594 case PHY_ID_RTL8211C:
1595 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1597 case PHY_ID_RTL8201E:
1598 case PHY_ID_BCMAC131:
1599 phydev->interface = PHY_INTERFACE_MODE_MII;
1600 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1601 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1605 tg3_flag_set(tp, MDIOBUS_INITED);
1607 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1608 tg3_mdio_config_5785(tp);
1613 static void tg3_mdio_fini(struct tg3 *tp)
1615 if (tg3_flag(tp, MDIOBUS_INITED)) {
1616 tg3_flag_clear(tp, MDIOBUS_INITED);
1617 mdiobus_unregister(tp->mdio_bus);
1618 mdiobus_free(tp->mdio_bus);
1622 /* tp->lock is held. */
1623 static inline void tg3_generate_fw_event(struct tg3 *tp)
1627 val = tr32(GRC_RX_CPU_EVENT);
1628 val |= GRC_RX_CPU_DRIVER_EVENT;
1629 tw32_f(GRC_RX_CPU_EVENT, val);
1631 tp->last_event_jiffies = jiffies;
1634 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1636 /* tp->lock is held. */
1637 static void tg3_wait_for_event_ack(struct tg3 *tp)
1640 unsigned int delay_cnt;
1643 /* If enough time has passed, no wait is necessary. */
1644 time_remain = (long)(tp->last_event_jiffies + 1 +
1645 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1647 if (time_remain < 0)
1650 /* Check if we can shorten the wait time. */
1651 delay_cnt = jiffies_to_usecs(time_remain);
1652 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1653 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1654 delay_cnt = (delay_cnt >> 3) + 1;
1656 for (i = 0; i < delay_cnt; i++) {
1657 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1659 if (pci_channel_offline(tp->pdev))
1666 /* tp->lock is held. */
1667 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1672 if (!tg3_readphy(tp, MII_BMCR, ®))
1674 if (!tg3_readphy(tp, MII_BMSR, ®))
1675 val |= (reg & 0xffff);
1679 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1681 if (!tg3_readphy(tp, MII_LPA, ®))
1682 val |= (reg & 0xffff);
1686 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1687 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1689 if (!tg3_readphy(tp, MII_STAT1000, ®))
1690 val |= (reg & 0xffff);
1694 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1701 /* tp->lock is held. */
1702 static void tg3_ump_link_report(struct tg3 *tp)
1706 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1709 tg3_phy_gather_ump_data(tp, data);
1711 tg3_wait_for_event_ack(tp);
1713 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1714 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1715 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1716 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1717 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1718 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1720 tg3_generate_fw_event(tp);
1723 /* tp->lock is held. */
1724 static void tg3_stop_fw(struct tg3 *tp)
1726 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1727 /* Wait for RX cpu to ACK the previous event. */
1728 tg3_wait_for_event_ack(tp);
1730 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1732 tg3_generate_fw_event(tp);
1734 /* Wait for RX cpu to ACK this event. */
1735 tg3_wait_for_event_ack(tp);
1739 /* tp->lock is held. */
1740 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1742 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1743 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1745 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1747 case RESET_KIND_INIT:
1748 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1752 case RESET_KIND_SHUTDOWN:
1753 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1757 case RESET_KIND_SUSPEND:
1758 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1768 /* tp->lock is held. */
1769 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1771 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1773 case RESET_KIND_INIT:
1774 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1775 DRV_STATE_START_DONE);
1778 case RESET_KIND_SHUTDOWN:
1779 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1780 DRV_STATE_UNLOAD_DONE);
1789 /* tp->lock is held. */
1790 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1792 if (tg3_flag(tp, ENABLE_ASF)) {
1794 case RESET_KIND_INIT:
1795 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1799 case RESET_KIND_SHUTDOWN:
1800 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1804 case RESET_KIND_SUSPEND:
1805 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1815 static int tg3_poll_fw(struct tg3 *tp)
1820 if (tg3_flag(tp, NO_FWARE_REPORTED))
1823 if (tg3_flag(tp, IS_SSB_CORE)) {
1824 /* We don't use firmware. */
1828 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1829 /* Wait up to 20ms for init done. */
1830 for (i = 0; i < 200; i++) {
1831 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1833 if (pci_channel_offline(tp->pdev))
1841 /* Wait for firmware initialization to complete. */
1842 for (i = 0; i < 100000; i++) {
1843 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1844 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1846 if (pci_channel_offline(tp->pdev)) {
1847 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1848 tg3_flag_set(tp, NO_FWARE_REPORTED);
1849 netdev_info(tp->dev, "No firmware running\n");
1858 /* Chip might not be fitted with firmware. Some Sun onboard
1859 * parts are configured like that. So don't signal the timeout
1860 * of the above loop as an error, but do report the lack of
1861 * running firmware once.
1863 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1864 tg3_flag_set(tp, NO_FWARE_REPORTED);
1866 netdev_info(tp->dev, "No firmware running\n");
1869 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1870 /* The 57765 A0 needs a little more
1871 * time to do some important work.
1879 static void tg3_link_report(struct tg3 *tp)
1881 if (!netif_carrier_ok(tp->dev)) {
1882 netif_info(tp, link, tp->dev, "Link is down\n");
1883 tg3_ump_link_report(tp);
1884 } else if (netif_msg_link(tp)) {
1885 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1886 (tp->link_config.active_speed == SPEED_1000 ?
1888 (tp->link_config.active_speed == SPEED_100 ?
1890 (tp->link_config.active_duplex == DUPLEX_FULL ?
1893 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1894 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1896 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1899 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1900 netdev_info(tp->dev, "EEE is %s\n",
1901 tp->setlpicnt ? "enabled" : "disabled");
1903 tg3_ump_link_report(tp);
1906 tp->link_up = netif_carrier_ok(tp->dev);
1909 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1913 if (adv & ADVERTISE_PAUSE_CAP) {
1914 flowctrl |= FLOW_CTRL_RX;
1915 if (!(adv & ADVERTISE_PAUSE_ASYM))
1916 flowctrl |= FLOW_CTRL_TX;
1917 } else if (adv & ADVERTISE_PAUSE_ASYM)
1918 flowctrl |= FLOW_CTRL_TX;
1923 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1927 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1928 miireg = ADVERTISE_1000XPAUSE;
1929 else if (flow_ctrl & FLOW_CTRL_TX)
1930 miireg = ADVERTISE_1000XPSE_ASYM;
1931 else if (flow_ctrl & FLOW_CTRL_RX)
1932 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1939 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1943 if (adv & ADVERTISE_1000XPAUSE) {
1944 flowctrl |= FLOW_CTRL_RX;
1945 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1946 flowctrl |= FLOW_CTRL_TX;
1947 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1948 flowctrl |= FLOW_CTRL_TX;
1953 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1957 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1958 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1959 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1960 if (lcladv & ADVERTISE_1000XPAUSE)
1962 if (rmtadv & ADVERTISE_1000XPAUSE)
1969 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1973 u32 old_rx_mode = tp->rx_mode;
1974 u32 old_tx_mode = tp->tx_mode;
1976 if (tg3_flag(tp, USE_PHYLIB))
1977 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
1979 autoneg = tp->link_config.autoneg;
1981 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1982 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1983 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1985 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1987 flowctrl = tp->link_config.flowctrl;
1989 tp->link_config.active_flowctrl = flowctrl;
1991 if (flowctrl & FLOW_CTRL_RX)
1992 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1994 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1996 if (old_rx_mode != tp->rx_mode)
1997 tw32_f(MAC_RX_MODE, tp->rx_mode);
1999 if (flowctrl & FLOW_CTRL_TX)
2000 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
2002 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
2004 if (old_tx_mode != tp->tx_mode)
2005 tw32_f(MAC_TX_MODE, tp->tx_mode);
2008 static void tg3_adjust_link(struct net_device *dev)
2010 u8 oldflowctrl, linkmesg = 0;
2011 u32 mac_mode, lcl_adv, rmt_adv;
2012 struct tg3 *tp = netdev_priv(dev);
2013 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2015 spin_lock_bh(&tp->lock);
2017 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2018 MAC_MODE_HALF_DUPLEX);
2020 oldflowctrl = tp->link_config.active_flowctrl;
2026 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2027 mac_mode |= MAC_MODE_PORT_MODE_MII;
2028 else if (phydev->speed == SPEED_1000 ||
2029 tg3_asic_rev(tp) != ASIC_REV_5785)
2030 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2032 mac_mode |= MAC_MODE_PORT_MODE_MII;
2034 if (phydev->duplex == DUPLEX_HALF)
2035 mac_mode |= MAC_MODE_HALF_DUPLEX;
2037 lcl_adv = mii_advertise_flowctrl(
2038 tp->link_config.flowctrl);
2041 rmt_adv = LPA_PAUSE_CAP;
2042 if (phydev->asym_pause)
2043 rmt_adv |= LPA_PAUSE_ASYM;
2046 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2048 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2050 if (mac_mode != tp->mac_mode) {
2051 tp->mac_mode = mac_mode;
2052 tw32_f(MAC_MODE, tp->mac_mode);
2056 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2057 if (phydev->speed == SPEED_10)
2059 MAC_MI_STAT_10MBPS_MODE |
2060 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2062 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2065 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2066 tw32(MAC_TX_LENGTHS,
2067 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2068 (6 << TX_LENGTHS_IPG_SHIFT) |
2069 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2071 tw32(MAC_TX_LENGTHS,
2072 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2073 (6 << TX_LENGTHS_IPG_SHIFT) |
2074 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2076 if (phydev->link != tp->old_link ||
2077 phydev->speed != tp->link_config.active_speed ||
2078 phydev->duplex != tp->link_config.active_duplex ||
2079 oldflowctrl != tp->link_config.active_flowctrl)
2082 tp->old_link = phydev->link;
2083 tp->link_config.active_speed = phydev->speed;
2084 tp->link_config.active_duplex = phydev->duplex;
2086 spin_unlock_bh(&tp->lock);
2089 tg3_link_report(tp);
2092 static int tg3_phy_init(struct tg3 *tp)
2094 struct phy_device *phydev;
2096 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2099 /* Bring the PHY back to a known state. */
2102 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2104 /* Attach the MAC to the PHY. */
2105 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2106 tg3_adjust_link, phydev->interface);
2107 if (IS_ERR(phydev)) {
2108 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2109 return PTR_ERR(phydev);
2112 /* Mask with MAC supported features. */
2113 switch (phydev->interface) {
2114 case PHY_INTERFACE_MODE_GMII:
2115 case PHY_INTERFACE_MODE_RGMII:
2116 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2117 phydev->supported &= (PHY_GBIT_FEATURES |
2119 SUPPORTED_Asym_Pause);
2123 case PHY_INTERFACE_MODE_MII:
2124 phydev->supported &= (PHY_BASIC_FEATURES |
2126 SUPPORTED_Asym_Pause);
2129 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2133 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2135 phydev->advertising = phydev->supported;
2140 static void tg3_phy_start(struct tg3 *tp)
2142 struct phy_device *phydev;
2144 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2147 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2149 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2150 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2151 phydev->speed = tp->link_config.speed;
2152 phydev->duplex = tp->link_config.duplex;
2153 phydev->autoneg = tp->link_config.autoneg;
2154 phydev->advertising = tp->link_config.advertising;
2159 phy_start_aneg(phydev);
2162 static void tg3_phy_stop(struct tg3 *tp)
2164 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2167 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
2170 static void tg3_phy_fini(struct tg3 *tp)
2172 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2173 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2174 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2178 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2183 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2186 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2187 /* Cannot do read-modify-write on 5401 */
2188 err = tg3_phy_auxctl_write(tp,
2189 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2190 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2195 err = tg3_phy_auxctl_read(tp,
2196 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2200 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2201 err = tg3_phy_auxctl_write(tp,
2202 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2208 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2212 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2215 tg3_writephy(tp, MII_TG3_FET_TEST,
2216 phytest | MII_TG3_FET_SHADOW_EN);
2217 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2219 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2221 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2222 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2224 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2228 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2232 if (!tg3_flag(tp, 5705_PLUS) ||
2233 (tg3_flag(tp, 5717_PLUS) &&
2234 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2237 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2238 tg3_phy_fet_toggle_apd(tp, enable);
2242 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2243 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2244 MII_TG3_MISC_SHDW_SCR5_SDTL |
2245 MII_TG3_MISC_SHDW_SCR5_C125OE;
2246 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2247 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2249 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2252 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2254 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2256 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2259 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2263 if (!tg3_flag(tp, 5705_PLUS) ||
2264 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2267 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2270 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2271 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2273 tg3_writephy(tp, MII_TG3_FET_TEST,
2274 ephy | MII_TG3_FET_SHADOW_EN);
2275 if (!tg3_readphy(tp, reg, &phy)) {
2277 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2279 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2280 tg3_writephy(tp, reg, phy);
2282 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2287 ret = tg3_phy_auxctl_read(tp,
2288 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2291 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2293 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2294 tg3_phy_auxctl_write(tp,
2295 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2300 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2305 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2308 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2310 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2311 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2314 static void tg3_phy_apply_otp(struct tg3 *tp)
2323 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2326 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2327 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2328 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2330 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2331 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2332 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2334 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2335 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2336 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2338 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2339 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2341 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2342 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2344 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2345 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2346 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2348 tg3_phy_toggle_auxctl_smdsp(tp, false);
2351 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2354 struct ethtool_eee *dest = &tp->eee;
2356 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2362 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2365 /* Pull eee_active */
2366 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2367 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2368 dest->eee_active = 1;
2370 dest->eee_active = 0;
2372 /* Pull lp advertised settings */
2373 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2375 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2377 /* Pull advertised and eee_enabled settings */
2378 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2380 dest->eee_enabled = !!val;
2381 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2383 /* Pull tx_lpi_enabled */
2384 val = tr32(TG3_CPMU_EEE_MODE);
2385 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2387 /* Pull lpi timer value */
2388 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2391 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2395 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2400 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2402 tp->link_config.active_duplex == DUPLEX_FULL &&
2403 (tp->link_config.active_speed == SPEED_100 ||
2404 tp->link_config.active_speed == SPEED_1000)) {
2407 if (tp->link_config.active_speed == SPEED_1000)
2408 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2410 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2412 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2414 tg3_eee_pull_config(tp, NULL);
2415 if (tp->eee.eee_active)
2419 if (!tp->setlpicnt) {
2420 if (current_link_up &&
2421 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2422 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2423 tg3_phy_toggle_auxctl_smdsp(tp, false);
2426 val = tr32(TG3_CPMU_EEE_MODE);
2427 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2431 static void tg3_phy_eee_enable(struct tg3 *tp)
2435 if (tp->link_config.active_speed == SPEED_1000 &&
2436 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2437 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2438 tg3_flag(tp, 57765_CLASS)) &&
2439 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2440 val = MII_TG3_DSP_TAP26_ALNOKO |
2441 MII_TG3_DSP_TAP26_RMRXSTO;
2442 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2443 tg3_phy_toggle_auxctl_smdsp(tp, false);
2446 val = tr32(TG3_CPMU_EEE_MODE);
2447 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2450 static int tg3_wait_macro_done(struct tg3 *tp)
2457 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2458 if ((tmp32 & 0x1000) == 0)
2468 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2470 static const u32 test_pat[4][6] = {
2471 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2472 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2473 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2474 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2478 for (chan = 0; chan < 4; chan++) {
2481 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2482 (chan * 0x2000) | 0x0200);
2483 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2485 for (i = 0; i < 6; i++)
2486 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2489 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2490 if (tg3_wait_macro_done(tp)) {
2495 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2496 (chan * 0x2000) | 0x0200);
2497 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2498 if (tg3_wait_macro_done(tp)) {
2503 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2504 if (tg3_wait_macro_done(tp)) {
2509 for (i = 0; i < 6; i += 2) {
2512 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2513 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2514 tg3_wait_macro_done(tp)) {
2520 if (low != test_pat[chan][i] ||
2521 high != test_pat[chan][i+1]) {
2522 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2523 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2524 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2534 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2538 for (chan = 0; chan < 4; chan++) {
2541 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2542 (chan * 0x2000) | 0x0200);
2543 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2544 for (i = 0; i < 6; i++)
2545 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2546 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2547 if (tg3_wait_macro_done(tp))
2554 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2556 u32 reg32, phy9_orig;
2557 int retries, do_phy_reset, err;
2563 err = tg3_bmcr_reset(tp);
2569 /* Disable transmitter and interrupt. */
2570 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2574 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2576 /* Set full-duplex, 1000 mbps. */
2577 tg3_writephy(tp, MII_BMCR,
2578 BMCR_FULLDPLX | BMCR_SPEED1000);
2580 /* Set to master mode. */
2581 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2584 tg3_writephy(tp, MII_CTRL1000,
2585 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2587 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2591 /* Block the PHY control access. */
2592 tg3_phydsp_write(tp, 0x8005, 0x0800);
2594 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2597 } while (--retries);
2599 err = tg3_phy_reset_chanpat(tp);
2603 tg3_phydsp_write(tp, 0x8005, 0x0000);
2605 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2606 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2608 tg3_phy_toggle_auxctl_smdsp(tp, false);
2610 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2612 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2617 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2622 static void tg3_carrier_off(struct tg3 *tp)
2624 netif_carrier_off(tp->dev);
2625 tp->link_up = false;
2628 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2630 if (tg3_flag(tp, ENABLE_ASF))
2631 netdev_warn(tp->dev,
2632 "Management side-band traffic will be interrupted during phy settings change\n");
2635 /* This will reset the tigon3 PHY if there is no valid
2636 * link unless the FORCE argument is non-zero.
2638 static int tg3_phy_reset(struct tg3 *tp)
2643 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2644 val = tr32(GRC_MISC_CFG);
2645 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2648 err = tg3_readphy(tp, MII_BMSR, &val);
2649 err |= tg3_readphy(tp, MII_BMSR, &val);
2653 if (netif_running(tp->dev) && tp->link_up) {
2654 netif_carrier_off(tp->dev);
2655 tg3_link_report(tp);
2658 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2659 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2660 tg3_asic_rev(tp) == ASIC_REV_5705) {
2661 err = tg3_phy_reset_5703_4_5(tp);
2668 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2669 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2670 cpmuctrl = tr32(TG3_CPMU_CTRL);
2671 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2673 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2676 err = tg3_bmcr_reset(tp);
2680 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2681 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2682 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2684 tw32(TG3_CPMU_CTRL, cpmuctrl);
2687 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2688 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2689 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2690 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2691 CPMU_LSPD_1000MB_MACCLK_12_5) {
2692 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2694 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2698 if (tg3_flag(tp, 5717_PLUS) &&
2699 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2702 tg3_phy_apply_otp(tp);
2704 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2705 tg3_phy_toggle_apd(tp, true);
2707 tg3_phy_toggle_apd(tp, false);
2710 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2711 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2712 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2713 tg3_phydsp_write(tp, 0x000a, 0x0323);
2714 tg3_phy_toggle_auxctl_smdsp(tp, false);
2717 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2718 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2719 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2722 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2723 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2724 tg3_phydsp_write(tp, 0x000a, 0x310b);
2725 tg3_phydsp_write(tp, 0x201f, 0x9506);
2726 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2727 tg3_phy_toggle_auxctl_smdsp(tp, false);
2729 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2730 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2731 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2732 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2733 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2734 tg3_writephy(tp, MII_TG3_TEST1,
2735 MII_TG3_TEST1_TRIM_EN | 0x4);
2737 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2739 tg3_phy_toggle_auxctl_smdsp(tp, false);
2743 /* Set Extended packet length bit (bit 14) on all chips that */
2744 /* support jumbo frames */
2745 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2746 /* Cannot do read-modify-write on 5401 */
2747 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2748 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2749 /* Set bit 14 with read-modify-write to preserve other bits */
2750 err = tg3_phy_auxctl_read(tp,
2751 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2753 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2754 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2757 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2758 * jumbo frames transmission.
2760 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2761 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2762 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2763 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2766 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2767 /* adjust output voltage */
2768 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2771 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2772 tg3_phydsp_write(tp, 0xffb, 0x4000);
2774 tg3_phy_toggle_automdix(tp, true);
2775 tg3_phy_set_wirespeed(tp);
2779 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2780 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2781 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2782 TG3_GPIO_MSG_NEED_VAUX)
2783 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2784 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2785 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2786 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2787 (TG3_GPIO_MSG_DRVR_PRES << 12))
2789 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2790 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2791 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2792 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2793 (TG3_GPIO_MSG_NEED_VAUX << 12))
2795 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2799 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2800 tg3_asic_rev(tp) == ASIC_REV_5719)
2801 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2803 status = tr32(TG3_CPMU_DRV_STATUS);
2805 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2806 status &= ~(TG3_GPIO_MSG_MASK << shift);
2807 status |= (newstat << shift);
2809 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2810 tg3_asic_rev(tp) == ASIC_REV_5719)
2811 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2813 tw32(TG3_CPMU_DRV_STATUS, status);
2815 return status >> TG3_APE_GPIO_MSG_SHIFT;
2818 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2820 if (!tg3_flag(tp, IS_NIC))
2823 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2824 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2825 tg3_asic_rev(tp) == ASIC_REV_5720) {
2826 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2829 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2831 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2832 TG3_GRC_LCLCTL_PWRSW_DELAY);
2834 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2836 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2837 TG3_GRC_LCLCTL_PWRSW_DELAY);
2843 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2847 if (!tg3_flag(tp, IS_NIC) ||
2848 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2849 tg3_asic_rev(tp) == ASIC_REV_5701)
2852 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2854 tw32_wait_f(GRC_LOCAL_CTRL,
2855 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2856 TG3_GRC_LCLCTL_PWRSW_DELAY);
2858 tw32_wait_f(GRC_LOCAL_CTRL,
2860 TG3_GRC_LCLCTL_PWRSW_DELAY);
2862 tw32_wait_f(GRC_LOCAL_CTRL,
2863 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2864 TG3_GRC_LCLCTL_PWRSW_DELAY);
2867 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2869 if (!tg3_flag(tp, IS_NIC))
2872 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2873 tg3_asic_rev(tp) == ASIC_REV_5701) {
2874 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2875 (GRC_LCLCTRL_GPIO_OE0 |
2876 GRC_LCLCTRL_GPIO_OE1 |
2877 GRC_LCLCTRL_GPIO_OE2 |
2878 GRC_LCLCTRL_GPIO_OUTPUT0 |
2879 GRC_LCLCTRL_GPIO_OUTPUT1),
2880 TG3_GRC_LCLCTL_PWRSW_DELAY);
2881 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2882 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2883 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2884 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2885 GRC_LCLCTRL_GPIO_OE1 |
2886 GRC_LCLCTRL_GPIO_OE2 |
2887 GRC_LCLCTRL_GPIO_OUTPUT0 |
2888 GRC_LCLCTRL_GPIO_OUTPUT1 |
2890 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2891 TG3_GRC_LCLCTL_PWRSW_DELAY);
2893 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2894 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2895 TG3_GRC_LCLCTL_PWRSW_DELAY);
2897 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2898 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2899 TG3_GRC_LCLCTL_PWRSW_DELAY);
2902 u32 grc_local_ctrl = 0;
2904 /* Workaround to prevent overdrawing Amps. */
2905 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2906 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2907 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2909 TG3_GRC_LCLCTL_PWRSW_DELAY);
2912 /* On 5753 and variants, GPIO2 cannot be used. */
2913 no_gpio2 = tp->nic_sram_data_cfg &
2914 NIC_SRAM_DATA_CFG_NO_GPIO2;
2916 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2917 GRC_LCLCTRL_GPIO_OE1 |
2918 GRC_LCLCTRL_GPIO_OE2 |
2919 GRC_LCLCTRL_GPIO_OUTPUT1 |
2920 GRC_LCLCTRL_GPIO_OUTPUT2;
2922 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2923 GRC_LCLCTRL_GPIO_OUTPUT2);
2925 tw32_wait_f(GRC_LOCAL_CTRL,
2926 tp->grc_local_ctrl | grc_local_ctrl,
2927 TG3_GRC_LCLCTL_PWRSW_DELAY);
2929 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2931 tw32_wait_f(GRC_LOCAL_CTRL,
2932 tp->grc_local_ctrl | grc_local_ctrl,
2933 TG3_GRC_LCLCTL_PWRSW_DELAY);
2936 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2937 tw32_wait_f(GRC_LOCAL_CTRL,
2938 tp->grc_local_ctrl | grc_local_ctrl,
2939 TG3_GRC_LCLCTL_PWRSW_DELAY);
2944 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2948 /* Serialize power state transitions */
2949 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2952 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2953 msg = TG3_GPIO_MSG_NEED_VAUX;
2955 msg = tg3_set_function_status(tp, msg);
2957 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2960 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2961 tg3_pwrsrc_switch_to_vaux(tp);
2963 tg3_pwrsrc_die_with_vmain(tp);
2966 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2969 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2971 bool need_vaux = false;
2973 /* The GPIOs do something completely different on 57765. */
2974 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2977 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2978 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2979 tg3_asic_rev(tp) == ASIC_REV_5720) {
2980 tg3_frob_aux_power_5717(tp, include_wol ?
2981 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2985 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2986 struct net_device *dev_peer;
2988 dev_peer = pci_get_drvdata(tp->pdev_peer);
2990 /* remove_one() may have been run on the peer. */
2992 struct tg3 *tp_peer = netdev_priv(dev_peer);
2994 if (tg3_flag(tp_peer, INIT_COMPLETE))
2997 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2998 tg3_flag(tp_peer, ENABLE_ASF))
3003 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
3004 tg3_flag(tp, ENABLE_ASF))
3008 tg3_pwrsrc_switch_to_vaux(tp);
3010 tg3_pwrsrc_die_with_vmain(tp);
3013 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3015 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3017 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3018 if (speed != SPEED_10)
3020 } else if (speed == SPEED_10)
3026 static bool tg3_phy_power_bug(struct tg3 *tp)
3028 switch (tg3_asic_rev(tp)) {
3033 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3042 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3051 static bool tg3_phy_led_bug(struct tg3 *tp)
3053 switch (tg3_asic_rev(tp)) {
3056 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3065 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3069 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3072 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3073 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3074 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3075 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3078 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3079 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3080 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3085 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3087 val = tr32(GRC_MISC_CFG);
3088 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3091 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3093 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3096 tg3_writephy(tp, MII_ADVERTISE, 0);
3097 tg3_writephy(tp, MII_BMCR,
3098 BMCR_ANENABLE | BMCR_ANRESTART);
3100 tg3_writephy(tp, MII_TG3_FET_TEST,
3101 phytest | MII_TG3_FET_SHADOW_EN);
3102 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3103 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3105 MII_TG3_FET_SHDW_AUXMODE4,
3108 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3111 } else if (do_low_power) {
3112 if (!tg3_phy_led_bug(tp))
3113 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3114 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3116 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3117 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3118 MII_TG3_AUXCTL_PCTL_VREG_11V;
3119 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3122 /* The PHY should not be powered down on some chips because
3125 if (tg3_phy_power_bug(tp))
3128 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3129 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3130 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3131 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3132 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3133 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3136 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3139 /* tp->lock is held. */
3140 static int tg3_nvram_lock(struct tg3 *tp)
3142 if (tg3_flag(tp, NVRAM)) {
3145 if (tp->nvram_lock_cnt == 0) {
3146 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3147 for (i = 0; i < 8000; i++) {
3148 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3153 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3157 tp->nvram_lock_cnt++;
3162 /* tp->lock is held. */
3163 static void tg3_nvram_unlock(struct tg3 *tp)
3165 if (tg3_flag(tp, NVRAM)) {
3166 if (tp->nvram_lock_cnt > 0)
3167 tp->nvram_lock_cnt--;
3168 if (tp->nvram_lock_cnt == 0)
3169 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3173 /* tp->lock is held. */
3174 static void tg3_enable_nvram_access(struct tg3 *tp)
3176 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3177 u32 nvaccess = tr32(NVRAM_ACCESS);
3179 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3183 /* tp->lock is held. */
3184 static void tg3_disable_nvram_access(struct tg3 *tp)
3186 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3187 u32 nvaccess = tr32(NVRAM_ACCESS);
3189 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3193 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3194 u32 offset, u32 *val)
3199 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3202 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3203 EEPROM_ADDR_DEVID_MASK |
3205 tw32(GRC_EEPROM_ADDR,
3207 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3208 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3209 EEPROM_ADDR_ADDR_MASK) |
3210 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3212 for (i = 0; i < 1000; i++) {
3213 tmp = tr32(GRC_EEPROM_ADDR);
3215 if (tmp & EEPROM_ADDR_COMPLETE)
3219 if (!(tmp & EEPROM_ADDR_COMPLETE))
3222 tmp = tr32(GRC_EEPROM_DATA);
3225 * The data will always be opposite the native endian
3226 * format. Perform a blind byteswap to compensate.
3233 #define NVRAM_CMD_TIMEOUT 10000
3235 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3239 tw32(NVRAM_CMD, nvram_cmd);
3240 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3242 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3248 if (i == NVRAM_CMD_TIMEOUT)
3254 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3256 if (tg3_flag(tp, NVRAM) &&
3257 tg3_flag(tp, NVRAM_BUFFERED) &&
3258 tg3_flag(tp, FLASH) &&
3259 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3260 (tp->nvram_jedecnum == JEDEC_ATMEL))
3262 addr = ((addr / tp->nvram_pagesize) <<
3263 ATMEL_AT45DB0X1B_PAGE_POS) +
3264 (addr % tp->nvram_pagesize);
3269 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3271 if (tg3_flag(tp, NVRAM) &&
3272 tg3_flag(tp, NVRAM_BUFFERED) &&
3273 tg3_flag(tp, FLASH) &&
3274 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3275 (tp->nvram_jedecnum == JEDEC_ATMEL))
3277 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3278 tp->nvram_pagesize) +
3279 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3284 /* NOTE: Data read in from NVRAM is byteswapped according to
3285 * the byteswapping settings for all other register accesses.
3286 * tg3 devices are BE devices, so on a BE machine, the data
3287 * returned will be exactly as it is seen in NVRAM. On a LE
3288 * machine, the 32-bit value will be byteswapped.
3290 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3294 if (!tg3_flag(tp, NVRAM))
3295 return tg3_nvram_read_using_eeprom(tp, offset, val);
3297 offset = tg3_nvram_phys_addr(tp, offset);
3299 if (offset > NVRAM_ADDR_MSK)
3302 ret = tg3_nvram_lock(tp);
3306 tg3_enable_nvram_access(tp);
3308 tw32(NVRAM_ADDR, offset);
3309 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3310 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3313 *val = tr32(NVRAM_RDDATA);
3315 tg3_disable_nvram_access(tp);
3317 tg3_nvram_unlock(tp);
3322 /* Ensures NVRAM data is in bytestream format. */
3323 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3326 int res = tg3_nvram_read(tp, offset, &v);
3328 *val = cpu_to_be32(v);
3332 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3333 u32 offset, u32 len, u8 *buf)
3338 for (i = 0; i < len; i += 4) {
3344 memcpy(&data, buf + i, 4);
3347 * The SEEPROM interface expects the data to always be opposite
3348 * the native endian format. We accomplish this by reversing
3349 * all the operations that would have been performed on the
3350 * data from a call to tg3_nvram_read_be32().
3352 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3354 val = tr32(GRC_EEPROM_ADDR);
3355 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3357 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3359 tw32(GRC_EEPROM_ADDR, val |
3360 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3361 (addr & EEPROM_ADDR_ADDR_MASK) |
3365 for (j = 0; j < 1000; j++) {
3366 val = tr32(GRC_EEPROM_ADDR);
3368 if (val & EEPROM_ADDR_COMPLETE)
3372 if (!(val & EEPROM_ADDR_COMPLETE)) {
3381 /* offset and length are dword aligned */
3382 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3386 u32 pagesize = tp->nvram_pagesize;
3387 u32 pagemask = pagesize - 1;
3391 tmp = kmalloc(pagesize, GFP_KERNEL);
3397 u32 phy_addr, page_off, size;
3399 phy_addr = offset & ~pagemask;
3401 for (j = 0; j < pagesize; j += 4) {
3402 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3403 (__be32 *) (tmp + j));
3410 page_off = offset & pagemask;
3417 memcpy(tmp + page_off, buf, size);
3419 offset = offset + (pagesize - page_off);
3421 tg3_enable_nvram_access(tp);
3424 * Before we can erase the flash page, we need
3425 * to issue a special "write enable" command.
3427 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3429 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3432 /* Erase the target page */
3433 tw32(NVRAM_ADDR, phy_addr);
3435 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3436 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3441 /* Issue another write enable to start the write. */
3442 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3444 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3447 for (j = 0; j < pagesize; j += 4) {
3450 data = *((__be32 *) (tmp + j));
3452 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3454 tw32(NVRAM_ADDR, phy_addr + j);
3456 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3460 nvram_cmd |= NVRAM_CMD_FIRST;
3461 else if (j == (pagesize - 4))
3462 nvram_cmd |= NVRAM_CMD_LAST;
3464 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3472 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3473 tg3_nvram_exec_cmd(tp, nvram_cmd);
3480 /* offset and length are dword aligned */
3481 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3486 for (i = 0; i < len; i += 4, offset += 4) {
3487 u32 page_off, phy_addr, nvram_cmd;
3490 memcpy(&data, buf + i, 4);
3491 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3493 page_off = offset % tp->nvram_pagesize;
3495 phy_addr = tg3_nvram_phys_addr(tp, offset);
3497 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3499 if (page_off == 0 || i == 0)
3500 nvram_cmd |= NVRAM_CMD_FIRST;
3501 if (page_off == (tp->nvram_pagesize - 4))
3502 nvram_cmd |= NVRAM_CMD_LAST;
3505 nvram_cmd |= NVRAM_CMD_LAST;
3507 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3508 !tg3_flag(tp, FLASH) ||
3509 !tg3_flag(tp, 57765_PLUS))
3510 tw32(NVRAM_ADDR, phy_addr);
3512 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3513 !tg3_flag(tp, 5755_PLUS) &&
3514 (tp->nvram_jedecnum == JEDEC_ST) &&
3515 (nvram_cmd & NVRAM_CMD_FIRST)) {
3518 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3519 ret = tg3_nvram_exec_cmd(tp, cmd);
3523 if (!tg3_flag(tp, FLASH)) {
3524 /* We always do complete word writes to eeprom. */
3525 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3528 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3535 /* offset and length are dword aligned */
3536 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3540 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3541 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3542 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3546 if (!tg3_flag(tp, NVRAM)) {
3547 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3551 ret = tg3_nvram_lock(tp);
3555 tg3_enable_nvram_access(tp);
3556 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3557 tw32(NVRAM_WRITE1, 0x406);
3559 grc_mode = tr32(GRC_MODE);
3560 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3562 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3563 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3566 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3570 grc_mode = tr32(GRC_MODE);
3571 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3573 tg3_disable_nvram_access(tp);
3574 tg3_nvram_unlock(tp);
3577 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3578 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3585 #define RX_CPU_SCRATCH_BASE 0x30000
3586 #define RX_CPU_SCRATCH_SIZE 0x04000
3587 #define TX_CPU_SCRATCH_BASE 0x34000
3588 #define TX_CPU_SCRATCH_SIZE 0x04000
3590 /* tp->lock is held. */
3591 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3594 const int iters = 10000;
3596 for (i = 0; i < iters; i++) {
3597 tw32(cpu_base + CPU_STATE, 0xffffffff);
3598 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3599 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3601 if (pci_channel_offline(tp->pdev))
3605 return (i == iters) ? -EBUSY : 0;
3608 /* tp->lock is held. */
3609 static int tg3_rxcpu_pause(struct tg3 *tp)
3611 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3613 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3614 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3620 /* tp->lock is held. */
3621 static int tg3_txcpu_pause(struct tg3 *tp)
3623 return tg3_pause_cpu(tp, TX_CPU_BASE);
3626 /* tp->lock is held. */
3627 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3629 tw32(cpu_base + CPU_STATE, 0xffffffff);
3630 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3633 /* tp->lock is held. */
3634 static void tg3_rxcpu_resume(struct tg3 *tp)
3636 tg3_resume_cpu(tp, RX_CPU_BASE);
3639 /* tp->lock is held. */
3640 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3644 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3646 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3647 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3649 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3652 if (cpu_base == RX_CPU_BASE) {
3653 rc = tg3_rxcpu_pause(tp);
3656 * There is only an Rx CPU for the 5750 derivative in the
3659 if (tg3_flag(tp, IS_SSB_CORE))
3662 rc = tg3_txcpu_pause(tp);
3666 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3667 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3671 /* Clear firmware's nvram arbitration. */
3672 if (tg3_flag(tp, NVRAM))
3673 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3677 static int tg3_fw_data_len(struct tg3 *tp,
3678 const struct tg3_firmware_hdr *fw_hdr)
3682 /* Non fragmented firmware have one firmware header followed by a
3683 * contiguous chunk of data to be written. The length field in that
3684 * header is not the length of data to be written but the complete
3685 * length of the bss. The data length is determined based on
3686 * tp->fw->size minus headers.
3688 * Fragmented firmware have a main header followed by multiple
3689 * fragments. Each fragment is identical to non fragmented firmware
3690 * with a firmware header followed by a contiguous chunk of data. In
3691 * the main header, the length field is unused and set to 0xffffffff.
3692 * In each fragment header the length is the entire size of that
3693 * fragment i.e. fragment data + header length. Data length is
3694 * therefore length field in the header minus TG3_FW_HDR_LEN.
3696 if (tp->fw_len == 0xffffffff)
3697 fw_len = be32_to_cpu(fw_hdr->len);
3699 fw_len = tp->fw->size;
3701 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3704 /* tp->lock is held. */
3705 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3706 u32 cpu_scratch_base, int cpu_scratch_size,
3707 const struct tg3_firmware_hdr *fw_hdr)
3710 void (*write_op)(struct tg3 *, u32, u32);
3711 int total_len = tp->fw->size;
3713 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3715 "%s: Trying to load TX cpu firmware which is 5705\n",
3720 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3721 write_op = tg3_write_mem;
3723 write_op = tg3_write_indirect_reg32;
3725 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3726 /* It is possible that bootcode is still loading at this point.
3727 * Get the nvram lock first before halting the cpu.
3729 int lock_err = tg3_nvram_lock(tp);
3730 err = tg3_halt_cpu(tp, cpu_base);
3732 tg3_nvram_unlock(tp);
3736 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3737 write_op(tp, cpu_scratch_base + i, 0);
3738 tw32(cpu_base + CPU_STATE, 0xffffffff);
3739 tw32(cpu_base + CPU_MODE,
3740 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3742 /* Subtract additional main header for fragmented firmware and
3743 * advance to the first fragment
3745 total_len -= TG3_FW_HDR_LEN;
3750 u32 *fw_data = (u32 *)(fw_hdr + 1);
3751 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3752 write_op(tp, cpu_scratch_base +
3753 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3755 be32_to_cpu(fw_data[i]));
3757 total_len -= be32_to_cpu(fw_hdr->len);
3759 /* Advance to next fragment */
3760 fw_hdr = (struct tg3_firmware_hdr *)
3761 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3762 } while (total_len > 0);
3770 /* tp->lock is held. */
3771 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3774 const int iters = 5;
3776 tw32(cpu_base + CPU_STATE, 0xffffffff);
3777 tw32_f(cpu_base + CPU_PC, pc);
3779 for (i = 0; i < iters; i++) {
3780 if (tr32(cpu_base + CPU_PC) == pc)
3782 tw32(cpu_base + CPU_STATE, 0xffffffff);
3783 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3784 tw32_f(cpu_base + CPU_PC, pc);
3788 return (i == iters) ? -EBUSY : 0;
3791 /* tp->lock is held. */
3792 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3794 const struct tg3_firmware_hdr *fw_hdr;
3797 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3799 /* Firmware blob starts with version numbers, followed by
3800 start address and length. We are setting complete length.
3801 length = end_address_of_bss - start_address_of_text.
3802 Remainder is the blob to be loaded contiguously
3803 from start address. */
3805 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3806 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3811 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3812 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3817 /* Now startup only the RX cpu. */
3818 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3819 be32_to_cpu(fw_hdr->base_addr));
3821 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3822 "should be %08x\n", __func__,
3823 tr32(RX_CPU_BASE + CPU_PC),
3824 be32_to_cpu(fw_hdr->base_addr));
3828 tg3_rxcpu_resume(tp);
3833 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3835 const int iters = 1000;
3839 /* Wait for boot code to complete initialization and enter service
3840 * loop. It is then safe to download service patches
3842 for (i = 0; i < iters; i++) {
3843 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3850 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3854 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3856 netdev_warn(tp->dev,
3857 "Other patches exist. Not downloading EEE patch\n");
3864 /* tp->lock is held. */
3865 static void tg3_load_57766_firmware(struct tg3 *tp)
3867 struct tg3_firmware_hdr *fw_hdr;
3869 if (!tg3_flag(tp, NO_NVRAM))
3872 if (tg3_validate_rxcpu_state(tp))
3878 /* This firmware blob has a different format than older firmware
3879 * releases as given below. The main difference is we have fragmented
3880 * data to be written to non-contiguous locations.
3882 * In the beginning we have a firmware header identical to other
3883 * firmware which consists of version, base addr and length. The length
3884 * here is unused and set to 0xffffffff.
3886 * This is followed by a series of firmware fragments which are
3887 * individually identical to previous firmware. i.e. they have the
3888 * firmware header and followed by data for that fragment. The version
3889 * field of the individual fragment header is unused.
3892 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3893 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3896 if (tg3_rxcpu_pause(tp))
3899 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3900 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3902 tg3_rxcpu_resume(tp);
3905 /* tp->lock is held. */
3906 static int tg3_load_tso_firmware(struct tg3 *tp)
3908 const struct tg3_firmware_hdr *fw_hdr;
3909 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3912 if (!tg3_flag(tp, FW_TSO))
3915 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3917 /* Firmware blob starts with version numbers, followed by
3918 start address and length. We are setting complete length.
3919 length = end_address_of_bss - start_address_of_text.
3920 Remainder is the blob to be loaded contiguously
3921 from start address. */
3923 cpu_scratch_size = tp->fw_len;
3925 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3926 cpu_base = RX_CPU_BASE;
3927 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3929 cpu_base = TX_CPU_BASE;
3930 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3931 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3934 err = tg3_load_firmware_cpu(tp, cpu_base,
3935 cpu_scratch_base, cpu_scratch_size,
3940 /* Now startup the cpu. */
3941 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3942 be32_to_cpu(fw_hdr->base_addr));
3945 "%s fails to set CPU PC, is %08x should be %08x\n",
3946 __func__, tr32(cpu_base + CPU_PC),
3947 be32_to_cpu(fw_hdr->base_addr));
3951 tg3_resume_cpu(tp, cpu_base);
3955 /* tp->lock is held. */
3956 static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3958 u32 addr_high, addr_low;
3960 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3961 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3962 (mac_addr[4] << 8) | mac_addr[5]);
3965 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3966 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3969 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3970 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3974 /* tp->lock is held. */
3975 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3980 for (i = 0; i < 4; i++) {
3981 if (i == 1 && skip_mac_1)
3983 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3986 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3987 tg3_asic_rev(tp) == ASIC_REV_5704) {
3988 for (i = 4; i < 16; i++)
3989 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3992 addr_high = (tp->dev->dev_addr[0] +
3993 tp->dev->dev_addr[1] +
3994 tp->dev->dev_addr[2] +
3995 tp->dev->dev_addr[3] +
3996 tp->dev->dev_addr[4] +
3997 tp->dev->dev_addr[5]) &
3998 TX_BACKOFF_SEED_MASK;
3999 tw32(MAC_TX_BACKOFF_SEED, addr_high);
4002 static void tg3_enable_register_access(struct tg3 *tp)
4005 * Make sure register accesses (indirect or otherwise) will function
4008 pci_write_config_dword(tp->pdev,
4009 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4012 static int tg3_power_up(struct tg3 *tp)
4016 tg3_enable_register_access(tp);
4018 err = pci_set_power_state(tp->pdev, PCI_D0);
4020 /* Switch out of Vaux if it is a NIC */
4021 tg3_pwrsrc_switch_to_vmain(tp);
4023 netdev_err(tp->dev, "Transition to D0 failed\n");
4029 static int tg3_setup_phy(struct tg3 *, bool);
4031 static int tg3_power_down_prepare(struct tg3 *tp)
4034 bool device_should_wake, do_low_power;
4036 tg3_enable_register_access(tp);
4038 /* Restore the CLKREQ setting. */
4039 if (tg3_flag(tp, CLKREQ_BUG))
4040 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4041 PCI_EXP_LNKCTL_CLKREQ_EN);
4043 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4044 tw32(TG3PCI_MISC_HOST_CTRL,
4045 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4047 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4048 tg3_flag(tp, WOL_ENABLE);
4050 if (tg3_flag(tp, USE_PHYLIB)) {
4051 do_low_power = false;
4052 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4053 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4054 struct phy_device *phydev;
4055 u32 phyid, advertising;
4057 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
4059 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4061 tp->link_config.speed = phydev->speed;
4062 tp->link_config.duplex = phydev->duplex;
4063 tp->link_config.autoneg = phydev->autoneg;
4064 tp->link_config.advertising = phydev->advertising;
4066 advertising = ADVERTISED_TP |
4068 ADVERTISED_Autoneg |
4069 ADVERTISED_10baseT_Half;
4071 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4072 if (tg3_flag(tp, WOL_SPEED_100MB))
4074 ADVERTISED_100baseT_Half |
4075 ADVERTISED_100baseT_Full |
4076 ADVERTISED_10baseT_Full;
4078 advertising |= ADVERTISED_10baseT_Full;
4081 phydev->advertising = advertising;
4083 phy_start_aneg(phydev);
4085 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
4086 if (phyid != PHY_ID_BCMAC131) {
4087 phyid &= PHY_BCM_OUI_MASK;
4088 if (phyid == PHY_BCM_OUI_1 ||
4089 phyid == PHY_BCM_OUI_2 ||
4090 phyid == PHY_BCM_OUI_3)
4091 do_low_power = true;
4095 do_low_power = true;
4097 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4098 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4100 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4101 tg3_setup_phy(tp, false);
4104 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4107 val = tr32(GRC_VCPU_EXT_CTRL);
4108 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4109 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4113 for (i = 0; i < 200; i++) {
4114 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4115 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4120 if (tg3_flag(tp, WOL_CAP))
4121 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4122 WOL_DRV_STATE_SHUTDOWN |
4126 if (device_should_wake) {
4129 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4131 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4132 tg3_phy_auxctl_write(tp,
4133 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4134 MII_TG3_AUXCTL_PCTL_WOL_EN |
4135 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4136 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4140 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4141 mac_mode = MAC_MODE_PORT_MODE_GMII;
4142 else if (tp->phy_flags &
4143 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4144 if (tp->link_config.active_speed == SPEED_1000)
4145 mac_mode = MAC_MODE_PORT_MODE_GMII;
4147 mac_mode = MAC_MODE_PORT_MODE_MII;
4149 mac_mode = MAC_MODE_PORT_MODE_MII;
4151 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4152 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4153 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4154 SPEED_100 : SPEED_10;
4155 if (tg3_5700_link_polarity(tp, speed))
4156 mac_mode |= MAC_MODE_LINK_POLARITY;
4158 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4161 mac_mode = MAC_MODE_PORT_MODE_TBI;
4164 if (!tg3_flag(tp, 5750_PLUS))
4165 tw32(MAC_LED_CTRL, tp->led_ctrl);
4167 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4168 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4169 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4170 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4172 if (tg3_flag(tp, ENABLE_APE))
4173 mac_mode |= MAC_MODE_APE_TX_EN |
4174 MAC_MODE_APE_RX_EN |
4175 MAC_MODE_TDE_ENABLE;
4177 tw32_f(MAC_MODE, mac_mode);
4180 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4184 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4185 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4186 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4189 base_val = tp->pci_clock_ctrl;
4190 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4191 CLOCK_CTRL_TXCLK_DISABLE);
4193 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4194 CLOCK_CTRL_PWRDOWN_PLL133, 40);
4195 } else if (tg3_flag(tp, 5780_CLASS) ||
4196 tg3_flag(tp, CPMU_PRESENT) ||
4197 tg3_asic_rev(tp) == ASIC_REV_5906) {
4199 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4200 u32 newbits1, newbits2;
4202 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4203 tg3_asic_rev(tp) == ASIC_REV_5701) {
4204 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4205 CLOCK_CTRL_TXCLK_DISABLE |
4207 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4208 } else if (tg3_flag(tp, 5705_PLUS)) {
4209 newbits1 = CLOCK_CTRL_625_CORE;
4210 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4212 newbits1 = CLOCK_CTRL_ALTCLK;
4213 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4216 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4219 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4222 if (!tg3_flag(tp, 5705_PLUS)) {
4225 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4226 tg3_asic_rev(tp) == ASIC_REV_5701) {
4227 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4228 CLOCK_CTRL_TXCLK_DISABLE |
4229 CLOCK_CTRL_44MHZ_CORE);
4231 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4234 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4235 tp->pci_clock_ctrl | newbits3, 40);
4239 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4240 tg3_power_down_phy(tp, do_low_power);
4242 tg3_frob_aux_power(tp, true);
4244 /* Workaround for unstable PLL clock */
4245 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4246 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4247 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4248 u32 val = tr32(0x7d00);
4250 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4252 if (!tg3_flag(tp, ENABLE_ASF)) {
4255 err = tg3_nvram_lock(tp);
4256 tg3_halt_cpu(tp, RX_CPU_BASE);
4258 tg3_nvram_unlock(tp);
4262 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4264 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4269 static void tg3_power_down(struct tg3 *tp)
4271 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4272 pci_set_power_state(tp->pdev, PCI_D3hot);
4275 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4277 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4278 case MII_TG3_AUX_STAT_10HALF:
4280 *duplex = DUPLEX_HALF;
4283 case MII_TG3_AUX_STAT_10FULL:
4285 *duplex = DUPLEX_FULL;
4288 case MII_TG3_AUX_STAT_100HALF:
4290 *duplex = DUPLEX_HALF;
4293 case MII_TG3_AUX_STAT_100FULL:
4295 *duplex = DUPLEX_FULL;
4298 case MII_TG3_AUX_STAT_1000HALF:
4299 *speed = SPEED_1000;
4300 *duplex = DUPLEX_HALF;
4303 case MII_TG3_AUX_STAT_1000FULL:
4304 *speed = SPEED_1000;
4305 *duplex = DUPLEX_FULL;
4309 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4310 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4312 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4316 *speed = SPEED_UNKNOWN;
4317 *duplex = DUPLEX_UNKNOWN;
4322 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4327 new_adv = ADVERTISE_CSMA;
4328 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
4329 new_adv |= mii_advertise_flowctrl(flowctrl);
4331 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4335 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4336 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
4338 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4339 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4340 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4342 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4347 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4350 tw32(TG3_CPMU_EEE_MODE,
4351 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
4353 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4358 /* Advertise 100-BaseTX EEE ability */
4359 if (advertise & ADVERTISED_100baseT_Full)
4360 val |= MDIO_AN_EEE_ADV_100TX;
4361 /* Advertise 1000-BaseT EEE ability */
4362 if (advertise & ADVERTISED_1000baseT_Full)
4363 val |= MDIO_AN_EEE_ADV_1000T;
4365 if (!tp->eee.eee_enabled) {
4367 tp->eee.advertised = 0;
4369 tp->eee.advertised = advertise &
4370 (ADVERTISED_100baseT_Full |
4371 ADVERTISED_1000baseT_Full);
4374 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4378 switch (tg3_asic_rev(tp)) {
4380 case ASIC_REV_57765:
4381 case ASIC_REV_57766:
4383 /* If we advertised any eee advertisements above... */
4385 val = MII_TG3_DSP_TAP26_ALNOKO |
4386 MII_TG3_DSP_TAP26_RMRXSTO |
4387 MII_TG3_DSP_TAP26_OPCSINPT;
4388 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4392 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4393 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4394 MII_TG3_DSP_CH34TP2_HIBW01);
4397 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4406 static void tg3_phy_copper_begin(struct tg3 *tp)
4408 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4409 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4412 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4413 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4414 adv = ADVERTISED_10baseT_Half |
4415 ADVERTISED_10baseT_Full;
4416 if (tg3_flag(tp, WOL_SPEED_100MB))
4417 adv |= ADVERTISED_100baseT_Half |
4418 ADVERTISED_100baseT_Full;
4419 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4420 if (!(tp->phy_flags &
4421 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4422 adv |= ADVERTISED_1000baseT_Half;
4423 adv |= ADVERTISED_1000baseT_Full;
4426 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4428 adv = tp->link_config.advertising;
4429 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4430 adv &= ~(ADVERTISED_1000baseT_Half |
4431 ADVERTISED_1000baseT_Full);
4433 fc = tp->link_config.flowctrl;
4436 tg3_phy_autoneg_cfg(tp, adv, fc);
4438 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4439 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4440 /* Normally during power down we want to autonegotiate
4441 * the lowest possible speed for WOL. However, to avoid
4442 * link flap, we leave it untouched.
4447 tg3_writephy(tp, MII_BMCR,
4448 BMCR_ANENABLE | BMCR_ANRESTART);
4451 u32 bmcr, orig_bmcr;
4453 tp->link_config.active_speed = tp->link_config.speed;
4454 tp->link_config.active_duplex = tp->link_config.duplex;
4456 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4457 /* With autoneg disabled, 5715 only links up when the
4458 * advertisement register has the configured speed
4461 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4465 switch (tp->link_config.speed) {
4471 bmcr |= BMCR_SPEED100;
4475 bmcr |= BMCR_SPEED1000;
4479 if (tp->link_config.duplex == DUPLEX_FULL)
4480 bmcr |= BMCR_FULLDPLX;
4482 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4483 (bmcr != orig_bmcr)) {
4484 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4485 for (i = 0; i < 1500; i++) {
4489 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4490 tg3_readphy(tp, MII_BMSR, &tmp))
4492 if (!(tmp & BMSR_LSTATUS)) {
4497 tg3_writephy(tp, MII_BMCR, bmcr);
4503 static int tg3_phy_pull_config(struct tg3 *tp)
4508 err = tg3_readphy(tp, MII_BMCR, &val);
4512 if (!(val & BMCR_ANENABLE)) {
4513 tp->link_config.autoneg = AUTONEG_DISABLE;
4514 tp->link_config.advertising = 0;
4515 tg3_flag_clear(tp, PAUSE_AUTONEG);
4519 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4524 tp->link_config.speed = SPEED_10;
4527 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4530 tp->link_config.speed = SPEED_100;
4532 case BMCR_SPEED1000:
4533 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4534 tp->link_config.speed = SPEED_1000;
4542 if (val & BMCR_FULLDPLX)
4543 tp->link_config.duplex = DUPLEX_FULL;
4545 tp->link_config.duplex = DUPLEX_HALF;
4547 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4553 tp->link_config.autoneg = AUTONEG_ENABLE;
4554 tp->link_config.advertising = ADVERTISED_Autoneg;
4555 tg3_flag_set(tp, PAUSE_AUTONEG);
4557 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4560 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4564 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4565 tp->link_config.advertising |= adv | ADVERTISED_TP;
4567 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4569 tp->link_config.advertising |= ADVERTISED_FIBRE;
4572 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4575 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4576 err = tg3_readphy(tp, MII_CTRL1000, &val);
4580 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4582 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4586 adv = tg3_decode_flowctrl_1000X(val);
4587 tp->link_config.flowctrl = adv;
4589 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4590 adv = mii_adv_to_ethtool_adv_x(val);
4593 tp->link_config.advertising |= adv;
4600 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4604 /* Turn off tap power management. */
4605 /* Set Extended packet length bit */
4606 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4608 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4609 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4610 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4611 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4612 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4619 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4621 struct ethtool_eee eee;
4623 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4626 tg3_eee_pull_config(tp, &eee);
4628 if (tp->eee.eee_enabled) {
4629 if (tp->eee.advertised != eee.advertised ||
4630 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4631 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4634 /* EEE is disabled but we're advertising */
4642 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4644 u32 advmsk, tgtadv, advertising;
4646 advertising = tp->link_config.advertising;
4647 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4649 advmsk = ADVERTISE_ALL;
4650 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4651 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4652 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4655 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4658 if ((*lcladv & advmsk) != tgtadv)
4661 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4664 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4666 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4670 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4671 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4672 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4673 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4674 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4676 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4679 if (tg3_ctrl != tgtadv)
4686 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4690 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4693 if (tg3_readphy(tp, MII_STAT1000, &val))
4696 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4699 if (tg3_readphy(tp, MII_LPA, rmtadv))
4702 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4703 tp->link_config.rmt_adv = lpeth;
4708 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4710 if (curr_link_up != tp->link_up) {
4712 netif_carrier_on(tp->dev);
4714 netif_carrier_off(tp->dev);
4715 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4716 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4719 tg3_link_report(tp);
4726 static void tg3_clear_mac_status(struct tg3 *tp)
4731 MAC_STATUS_SYNC_CHANGED |
4732 MAC_STATUS_CFG_CHANGED |
4733 MAC_STATUS_MI_COMPLETION |
4734 MAC_STATUS_LNKSTATE_CHANGED);
4738 static void tg3_setup_eee(struct tg3 *tp)
4742 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4743 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4744 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4745 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4747 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4749 tw32_f(TG3_CPMU_EEE_CTRL,
4750 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4752 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4753 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4754 TG3_CPMU_EEEMD_LPI_IN_RX |
4755 TG3_CPMU_EEEMD_EEE_ENABLE;
4757 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4758 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4760 if (tg3_flag(tp, ENABLE_APE))
4761 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4763 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4765 tw32_f(TG3_CPMU_EEE_DBTMR1,
4766 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4767 (tp->eee.tx_lpi_timer & 0xffff));
4769 tw32_f(TG3_CPMU_EEE_DBTMR2,
4770 TG3_CPMU_DBTMR2_APE_TX_2047US |
4771 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4774 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4776 bool current_link_up;
4778 u32 lcl_adv, rmt_adv;
4783 tg3_clear_mac_status(tp);
4785 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4787 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4791 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4793 /* Some third-party PHYs need to be reset on link going
4796 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4797 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4798 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4800 tg3_readphy(tp, MII_BMSR, &bmsr);
4801 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4802 !(bmsr & BMSR_LSTATUS))
4808 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4809 tg3_readphy(tp, MII_BMSR, &bmsr);
4810 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4811 !tg3_flag(tp, INIT_COMPLETE))
4814 if (!(bmsr & BMSR_LSTATUS)) {
4815 err = tg3_init_5401phy_dsp(tp);
4819 tg3_readphy(tp, MII_BMSR, &bmsr);
4820 for (i = 0; i < 1000; i++) {
4822 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4823 (bmsr & BMSR_LSTATUS)) {
4829 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4830 TG3_PHY_REV_BCM5401_B0 &&
4831 !(bmsr & BMSR_LSTATUS) &&
4832 tp->link_config.active_speed == SPEED_1000) {
4833 err = tg3_phy_reset(tp);
4835 err = tg3_init_5401phy_dsp(tp);
4840 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4841 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4842 /* 5701 {A0,B0} CRC bug workaround */
4843 tg3_writephy(tp, 0x15, 0x0a75);
4844 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4845 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4846 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4849 /* Clear pending interrupts... */
4850 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4851 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4853 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4854 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4855 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4856 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4858 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4859 tg3_asic_rev(tp) == ASIC_REV_5701) {
4860 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4861 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4862 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4864 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4867 current_link_up = false;
4868 current_speed = SPEED_UNKNOWN;
4869 current_duplex = DUPLEX_UNKNOWN;
4870 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4871 tp->link_config.rmt_adv = 0;
4873 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4874 err = tg3_phy_auxctl_read(tp,
4875 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4877 if (!err && !(val & (1 << 10))) {
4878 tg3_phy_auxctl_write(tp,
4879 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4886 for (i = 0; i < 100; i++) {
4887 tg3_readphy(tp, MII_BMSR, &bmsr);
4888 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4889 (bmsr & BMSR_LSTATUS))
4894 if (bmsr & BMSR_LSTATUS) {
4897 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4898 for (i = 0; i < 2000; i++) {
4900 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4905 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4910 for (i = 0; i < 200; i++) {
4911 tg3_readphy(tp, MII_BMCR, &bmcr);
4912 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4914 if (bmcr && bmcr != 0x7fff)
4922 tp->link_config.active_speed = current_speed;
4923 tp->link_config.active_duplex = current_duplex;
4925 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4926 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4928 if ((bmcr & BMCR_ANENABLE) &&
4930 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4931 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4932 current_link_up = true;
4934 /* EEE settings changes take effect only after a phy
4935 * reset. If we have skipped a reset due to Link Flap
4936 * Avoidance being enabled, do it now.
4938 if (!eee_config_ok &&
4939 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4945 if (!(bmcr & BMCR_ANENABLE) &&
4946 tp->link_config.speed == current_speed &&
4947 tp->link_config.duplex == current_duplex) {
4948 current_link_up = true;
4952 if (current_link_up &&
4953 tp->link_config.active_duplex == DUPLEX_FULL) {
4956 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4957 reg = MII_TG3_FET_GEN_STAT;
4958 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4960 reg = MII_TG3_EXT_STAT;
4961 bit = MII_TG3_EXT_STAT_MDIX;
4964 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4965 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4967 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4972 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4973 tg3_phy_copper_begin(tp);
4975 if (tg3_flag(tp, ROBOSWITCH)) {
4976 current_link_up = true;
4977 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4978 current_speed = SPEED_1000;
4979 current_duplex = DUPLEX_FULL;
4980 tp->link_config.active_speed = current_speed;
4981 tp->link_config.active_duplex = current_duplex;
4984 tg3_readphy(tp, MII_BMSR, &bmsr);
4985 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4986 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4987 current_link_up = true;
4990 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4991 if (current_link_up) {
4992 if (tp->link_config.active_speed == SPEED_100 ||
4993 tp->link_config.active_speed == SPEED_10)
4994 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4996 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4997 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4998 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5000 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5002 /* In order for the 5750 core in BCM4785 chip to work properly
5003 * in RGMII mode, the Led Control Register must be set up.
5005 if (tg3_flag(tp, RGMII_MODE)) {
5006 u32 led_ctrl = tr32(MAC_LED_CTRL);
5007 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5009 if (tp->link_config.active_speed == SPEED_10)
5010 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5011 else if (tp->link_config.active_speed == SPEED_100)
5012 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5013 LED_CTRL_100MBPS_ON);
5014 else if (tp->link_config.active_speed == SPEED_1000)
5015 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5016 LED_CTRL_1000MBPS_ON);
5018 tw32(MAC_LED_CTRL, led_ctrl);
5022 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5023 if (tp->link_config.active_duplex == DUPLEX_HALF)
5024 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5026 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5027 if (current_link_up &&
5028 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5029 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5031 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5034 /* ??? Without this setting Netgear GA302T PHY does not
5035 * ??? send/receive packets...
5037 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5038 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5039 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5040 tw32_f(MAC_MI_MODE, tp->mi_mode);
5044 tw32_f(MAC_MODE, tp->mac_mode);
5047 tg3_phy_eee_adjust(tp, current_link_up);
5049 if (tg3_flag(tp, USE_LINKCHG_REG)) {
5050 /* Polled via timer. */
5051 tw32_f(MAC_EVENT, 0);
5053 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5057 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5059 tp->link_config.active_speed == SPEED_1000 &&
5060 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5063 (MAC_STATUS_SYNC_CHANGED |
5064 MAC_STATUS_CFG_CHANGED));
5067 NIC_SRAM_FIRMWARE_MBOX,
5068 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5071 /* Prevent send BD corruption. */
5072 if (tg3_flag(tp, CLKREQ_BUG)) {
5073 if (tp->link_config.active_speed == SPEED_100 ||
5074 tp->link_config.active_speed == SPEED_10)
5075 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5076 PCI_EXP_LNKCTL_CLKREQ_EN);
5078 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5079 PCI_EXP_LNKCTL_CLKREQ_EN);
5082 tg3_test_and_report_link_chg(tp, current_link_up);
5087 struct tg3_fiber_aneginfo {
5089 #define ANEG_STATE_UNKNOWN 0
5090 #define ANEG_STATE_AN_ENABLE 1
5091 #define ANEG_STATE_RESTART_INIT 2
5092 #define ANEG_STATE_RESTART 3
5093 #define ANEG_STATE_DISABLE_LINK_OK 4
5094 #define ANEG_STATE_ABILITY_DETECT_INIT 5
5095 #define ANEG_STATE_ABILITY_DETECT 6
5096 #define ANEG_STATE_ACK_DETECT_INIT 7
5097 #define ANEG_STATE_ACK_DETECT 8
5098 #define ANEG_STATE_COMPLETE_ACK_INIT 9
5099 #define ANEG_STATE_COMPLETE_ACK 10
5100 #define ANEG_STATE_IDLE_DETECT_INIT 11
5101 #define ANEG_STATE_IDLE_DETECT 12
5102 #define ANEG_STATE_LINK_OK 13
5103 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5104 #define ANEG_STATE_NEXT_PAGE_WAIT 15
5107 #define MR_AN_ENABLE 0x00000001
5108 #define MR_RESTART_AN 0x00000002
5109 #define MR_AN_COMPLETE 0x00000004
5110 #define MR_PAGE_RX 0x00000008
5111 #define MR_NP_LOADED 0x00000010
5112 #define MR_TOGGLE_TX 0x00000020
5113 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5114 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5115 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5116 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5117 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5118 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5119 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5120 #define MR_TOGGLE_RX 0x00002000
5121 #define MR_NP_RX 0x00004000
5123 #define MR_LINK_OK 0x80000000
5125 unsigned long link_time, cur_time;
5127 u32 ability_match_cfg;
5128 int ability_match_count;
5130 char ability_match, idle_match, ack_match;
5132 u32 txconfig, rxconfig;
5133 #define ANEG_CFG_NP 0x00000080
5134 #define ANEG_CFG_ACK 0x00000040
5135 #define ANEG_CFG_RF2 0x00000020
5136 #define ANEG_CFG_RF1 0x00000010
5137 #define ANEG_CFG_PS2 0x00000001
5138 #define ANEG_CFG_PS1 0x00008000
5139 #define ANEG_CFG_HD 0x00004000
5140 #define ANEG_CFG_FD 0x00002000
5141 #define ANEG_CFG_INVAL 0x00001f06
5146 #define ANEG_TIMER_ENAB 2
5147 #define ANEG_FAILED -1
5149 #define ANEG_STATE_SETTLE_TIME 10000
5151 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5152 struct tg3_fiber_aneginfo *ap)
5155 unsigned long delta;
5159 if (ap->state == ANEG_STATE_UNKNOWN) {
5163 ap->ability_match_cfg = 0;
5164 ap->ability_match_count = 0;
5165 ap->ability_match = 0;
5171 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5172 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5174 if (rx_cfg_reg != ap->ability_match_cfg) {
5175 ap->ability_match_cfg = rx_cfg_reg;
5176 ap->ability_match = 0;
5177 ap->ability_match_count = 0;
5179 if (++ap->ability_match_count > 1) {
5180 ap->ability_match = 1;
5181 ap->ability_match_cfg = rx_cfg_reg;
5184 if (rx_cfg_reg & ANEG_CFG_ACK)
5192 ap->ability_match_cfg = 0;
5193 ap->ability_match_count = 0;
5194 ap->ability_match = 0;
5200 ap->rxconfig = rx_cfg_reg;
5203 switch (ap->state) {
5204 case ANEG_STATE_UNKNOWN:
5205 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5206 ap->state = ANEG_STATE_AN_ENABLE;
5209 case ANEG_STATE_AN_ENABLE:
5210 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5211 if (ap->flags & MR_AN_ENABLE) {
5214 ap->ability_match_cfg = 0;
5215 ap->ability_match_count = 0;
5216 ap->ability_match = 0;
5220 ap->state = ANEG_STATE_RESTART_INIT;
5222 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5226 case ANEG_STATE_RESTART_INIT:
5227 ap->link_time = ap->cur_time;
5228 ap->flags &= ~(MR_NP_LOADED);
5230 tw32(MAC_TX_AUTO_NEG, 0);
5231 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5232 tw32_f(MAC_MODE, tp->mac_mode);
5235 ret = ANEG_TIMER_ENAB;
5236 ap->state = ANEG_STATE_RESTART;
5239 case ANEG_STATE_RESTART:
5240 delta = ap->cur_time - ap->link_time;
5241 if (delta > ANEG_STATE_SETTLE_TIME)
5242 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
5244 ret = ANEG_TIMER_ENAB;
5247 case ANEG_STATE_DISABLE_LINK_OK:
5251 case ANEG_STATE_ABILITY_DETECT_INIT:
5252 ap->flags &= ~(MR_TOGGLE_TX);
5253 ap->txconfig = ANEG_CFG_FD;
5254 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5255 if (flowctrl & ADVERTISE_1000XPAUSE)
5256 ap->txconfig |= ANEG_CFG_PS1;
5257 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5258 ap->txconfig |= ANEG_CFG_PS2;
5259 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5260 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5261 tw32_f(MAC_MODE, tp->mac_mode);
5264 ap->state = ANEG_STATE_ABILITY_DETECT;
5267 case ANEG_STATE_ABILITY_DETECT:
5268 if (ap->ability_match != 0 && ap->rxconfig != 0)
5269 ap->state = ANEG_STATE_ACK_DETECT_INIT;
5272 case ANEG_STATE_ACK_DETECT_INIT:
5273 ap->txconfig |= ANEG_CFG_ACK;
5274 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5275 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5276 tw32_f(MAC_MODE, tp->mac_mode);
5279 ap->state = ANEG_STATE_ACK_DETECT;
5282 case ANEG_STATE_ACK_DETECT:
5283 if (ap->ack_match != 0) {
5284 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5285 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5286 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5288 ap->state = ANEG_STATE_AN_ENABLE;
5290 } else if (ap->ability_match != 0 &&
5291 ap->rxconfig == 0) {
5292 ap->state = ANEG_STATE_AN_ENABLE;
5296 case ANEG_STATE_COMPLETE_ACK_INIT:
5297 if (ap->rxconfig & ANEG_CFG_INVAL) {
5301 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5302 MR_LP_ADV_HALF_DUPLEX |
5303 MR_LP_ADV_SYM_PAUSE |
5304 MR_LP_ADV_ASYM_PAUSE |
5305 MR_LP_ADV_REMOTE_FAULT1 |
5306 MR_LP_ADV_REMOTE_FAULT2 |
5307 MR_LP_ADV_NEXT_PAGE |
5310 if (ap->rxconfig & ANEG_CFG_FD)
5311 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5312 if (ap->rxconfig & ANEG_CFG_HD)
5313 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5314 if (ap->rxconfig & ANEG_CFG_PS1)
5315 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5316 if (ap->rxconfig & ANEG_CFG_PS2)
5317 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5318 if (ap->rxconfig & ANEG_CFG_RF1)
5319 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5320 if (ap->rxconfig & ANEG_CFG_RF2)
5321 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5322 if (ap->rxconfig & ANEG_CFG_NP)
5323 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5325 ap->link_time = ap->cur_time;
5327 ap->flags ^= (MR_TOGGLE_TX);
5328 if (ap->rxconfig & 0x0008)
5329 ap->flags |= MR_TOGGLE_RX;
5330 if (ap->rxconfig & ANEG_CFG_NP)
5331 ap->flags |= MR_NP_RX;
5332 ap->flags |= MR_PAGE_RX;
5334 ap->state = ANEG_STATE_COMPLETE_ACK;
5335 ret = ANEG_TIMER_ENAB;
5338 case ANEG_STATE_COMPLETE_ACK:
5339 if (ap->ability_match != 0 &&
5340 ap->rxconfig == 0) {
5341 ap->state = ANEG_STATE_AN_ENABLE;
5344 delta = ap->cur_time - ap->link_time;
5345 if (delta > ANEG_STATE_SETTLE_TIME) {
5346 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5347 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5349 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5350 !(ap->flags & MR_NP_RX)) {
5351 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5359 case ANEG_STATE_IDLE_DETECT_INIT:
5360 ap->link_time = ap->cur_time;
5361 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5362 tw32_f(MAC_MODE, tp->mac_mode);
5365 ap->state = ANEG_STATE_IDLE_DETECT;
5366 ret = ANEG_TIMER_ENAB;
5369 case ANEG_STATE_IDLE_DETECT:
5370 if (ap->ability_match != 0 &&
5371 ap->rxconfig == 0) {
5372 ap->state = ANEG_STATE_AN_ENABLE;
5375 delta = ap->cur_time - ap->link_time;
5376 if (delta > ANEG_STATE_SETTLE_TIME) {
5377 /* XXX another gem from the Broadcom driver :( */
5378 ap->state = ANEG_STATE_LINK_OK;
5382 case ANEG_STATE_LINK_OK:
5383 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5387 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5388 /* ??? unimplemented */
5391 case ANEG_STATE_NEXT_PAGE_WAIT:
5392 /* ??? unimplemented */
5403 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5406 struct tg3_fiber_aneginfo aninfo;
5407 int status = ANEG_FAILED;
5411 tw32_f(MAC_TX_AUTO_NEG, 0);
5413 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5414 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5417 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5420 memset(&aninfo, 0, sizeof(aninfo));
5421 aninfo.flags |= MR_AN_ENABLE;
5422 aninfo.state = ANEG_STATE_UNKNOWN;
5423 aninfo.cur_time = 0;
5425 while (++tick < 195000) {
5426 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5427 if (status == ANEG_DONE || status == ANEG_FAILED)
5433 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5434 tw32_f(MAC_MODE, tp->mac_mode);
5437 *txflags = aninfo.txconfig;
5438 *rxflags = aninfo.flags;
5440 if (status == ANEG_DONE &&
5441 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5442 MR_LP_ADV_FULL_DUPLEX)))
5448 static void tg3_init_bcm8002(struct tg3 *tp)
5450 u32 mac_status = tr32(MAC_STATUS);
5453 /* Reset when initting first time or we have a link. */
5454 if (tg3_flag(tp, INIT_COMPLETE) &&
5455 !(mac_status & MAC_STATUS_PCS_SYNCED))
5458 /* Set PLL lock range. */
5459 tg3_writephy(tp, 0x16, 0x8007);
5462 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5464 /* Wait for reset to complete. */
5465 /* XXX schedule_timeout() ... */
5466 for (i = 0; i < 500; i++)
5469 /* Config mode; select PMA/Ch 1 regs. */
5470 tg3_writephy(tp, 0x10, 0x8411);
5472 /* Enable auto-lock and comdet, select txclk for tx. */
5473 tg3_writephy(tp, 0x11, 0x0a10);
5475 tg3_writephy(tp, 0x18, 0x00a0);
5476 tg3_writephy(tp, 0x16, 0x41ff);
5478 /* Assert and deassert POR. */
5479 tg3_writephy(tp, 0x13, 0x0400);
5481 tg3_writephy(tp, 0x13, 0x0000);
5483 tg3_writephy(tp, 0x11, 0x0a50);
5485 tg3_writephy(tp, 0x11, 0x0a10);
5487 /* Wait for signal to stabilize */
5488 /* XXX schedule_timeout() ... */
5489 for (i = 0; i < 15000; i++)
5492 /* Deselect the channel register so we can read the PHYID
5495 tg3_writephy(tp, 0x10, 0x8011);
5498 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5501 bool current_link_up;
5502 u32 sg_dig_ctrl, sg_dig_status;
5503 u32 serdes_cfg, expected_sg_dig_ctrl;
5504 int workaround, port_a;
5507 expected_sg_dig_ctrl = 0;
5510 current_link_up = false;
5512 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5513 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5515 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5518 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5519 /* preserve bits 20-23 for voltage regulator */
5520 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5523 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5525 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5526 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
5528 u32 val = serdes_cfg;
5534 tw32_f(MAC_SERDES_CFG, val);
5537 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5539 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5540 tg3_setup_flow_control(tp, 0, 0);
5541 current_link_up = true;
5546 /* Want auto-negotiation. */
5547 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
5549 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5550 if (flowctrl & ADVERTISE_1000XPAUSE)
5551 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5552 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5553 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
5555 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
5556 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5557 tp->serdes_counter &&
5558 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5559 MAC_STATUS_RCVD_CFG)) ==
5560 MAC_STATUS_PCS_SYNCED)) {
5561 tp->serdes_counter--;
5562 current_link_up = true;
5567 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5568 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5570 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5572 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5573 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5574 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5575 MAC_STATUS_SIGNAL_DET)) {
5576 sg_dig_status = tr32(SG_DIG_STATUS);
5577 mac_status = tr32(MAC_STATUS);
5579 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
5580 (mac_status & MAC_STATUS_PCS_SYNCED)) {
5581 u32 local_adv = 0, remote_adv = 0;
5583 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5584 local_adv |= ADVERTISE_1000XPAUSE;
5585 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5586 local_adv |= ADVERTISE_1000XPSE_ASYM;
5588 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
5589 remote_adv |= LPA_1000XPAUSE;
5590 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
5591 remote_adv |= LPA_1000XPAUSE_ASYM;
5593 tp->link_config.rmt_adv =
5594 mii_adv_to_ethtool_adv_x(remote_adv);
5596 tg3_setup_flow_control(tp, local_adv, remote_adv);
5597 current_link_up = true;
5598 tp->serdes_counter = 0;
5599 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5600 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
5601 if (tp->serdes_counter)
5602 tp->serdes_counter--;
5605 u32 val = serdes_cfg;
5612 tw32_f(MAC_SERDES_CFG, val);
5615 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5618 /* Link parallel detection - link is up */
5619 /* only if we have PCS_SYNC and not */
5620 /* receiving config code words */
5621 mac_status = tr32(MAC_STATUS);
5622 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5623 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5624 tg3_setup_flow_control(tp, 0, 0);
5625 current_link_up = true;
5627 TG3_PHYFLG_PARALLEL_DETECT;
5628 tp->serdes_counter =
5629 SERDES_PARALLEL_DET_TIMEOUT;
5631 goto restart_autoneg;
5635 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5636 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5640 return current_link_up;
5643 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5645 bool current_link_up = false;
5647 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5650 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5651 u32 txflags, rxflags;
5654 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5655 u32 local_adv = 0, remote_adv = 0;
5657 if (txflags & ANEG_CFG_PS1)
5658 local_adv |= ADVERTISE_1000XPAUSE;
5659 if (txflags & ANEG_CFG_PS2)
5660 local_adv |= ADVERTISE_1000XPSE_ASYM;
5662 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5663 remote_adv |= LPA_1000XPAUSE;
5664 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5665 remote_adv |= LPA_1000XPAUSE_ASYM;
5667 tp->link_config.rmt_adv =
5668 mii_adv_to_ethtool_adv_x(remote_adv);
5670 tg3_setup_flow_control(tp, local_adv, remote_adv);
5672 current_link_up = true;
5674 for (i = 0; i < 30; i++) {
5677 (MAC_STATUS_SYNC_CHANGED |
5678 MAC_STATUS_CFG_CHANGED));
5680 if ((tr32(MAC_STATUS) &
5681 (MAC_STATUS_SYNC_CHANGED |
5682 MAC_STATUS_CFG_CHANGED)) == 0)
5686 mac_status = tr32(MAC_STATUS);
5687 if (!current_link_up &&
5688 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5689 !(mac_status & MAC_STATUS_RCVD_CFG))
5690 current_link_up = true;
5692 tg3_setup_flow_control(tp, 0, 0);
5694 /* Forcing 1000FD link up. */
5695 current_link_up = true;
5697 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5700 tw32_f(MAC_MODE, tp->mac_mode);
5705 return current_link_up;
5708 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
5711 u16 orig_active_speed;
5712 u8 orig_active_duplex;
5714 bool current_link_up;
5717 orig_pause_cfg = tp->link_config.active_flowctrl;
5718 orig_active_speed = tp->link_config.active_speed;
5719 orig_active_duplex = tp->link_config.active_duplex;
5721 if (!tg3_flag(tp, HW_AUTONEG) &&
5723 tg3_flag(tp, INIT_COMPLETE)) {
5724 mac_status = tr32(MAC_STATUS);
5725 mac_status &= (MAC_STATUS_PCS_SYNCED |
5726 MAC_STATUS_SIGNAL_DET |
5727 MAC_STATUS_CFG_CHANGED |
5728 MAC_STATUS_RCVD_CFG);
5729 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5730 MAC_STATUS_SIGNAL_DET)) {
5731 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5732 MAC_STATUS_CFG_CHANGED));
5737 tw32_f(MAC_TX_AUTO_NEG, 0);
5739 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5740 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5741 tw32_f(MAC_MODE, tp->mac_mode);
5744 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5745 tg3_init_bcm8002(tp);
5747 /* Enable link change event even when serdes polling. */
5748 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5751 current_link_up = false;
5752 tp->link_config.rmt_adv = 0;
5753 mac_status = tr32(MAC_STATUS);
5755 if (tg3_flag(tp, HW_AUTONEG))
5756 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5758 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5760 tp->napi[0].hw_status->status =
5761 (SD_STATUS_UPDATED |
5762 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5764 for (i = 0; i < 100; i++) {
5765 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5766 MAC_STATUS_CFG_CHANGED));
5768 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5769 MAC_STATUS_CFG_CHANGED |
5770 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5774 mac_status = tr32(MAC_STATUS);
5775 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5776 current_link_up = false;
5777 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5778 tp->serdes_counter == 0) {
5779 tw32_f(MAC_MODE, (tp->mac_mode |
5780 MAC_MODE_SEND_CONFIGS));
5782 tw32_f(MAC_MODE, tp->mac_mode);
5786 if (current_link_up) {
5787 tp->link_config.active_speed = SPEED_1000;
5788 tp->link_config.active_duplex = DUPLEX_FULL;
5789 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5790 LED_CTRL_LNKLED_OVERRIDE |
5791 LED_CTRL_1000MBPS_ON));
5793 tp->link_config.active_speed = SPEED_UNKNOWN;
5794 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5795 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5796 LED_CTRL_LNKLED_OVERRIDE |
5797 LED_CTRL_TRAFFIC_OVERRIDE));
5800 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5801 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5802 if (orig_pause_cfg != now_pause_cfg ||
5803 orig_active_speed != tp->link_config.active_speed ||
5804 orig_active_duplex != tp->link_config.active_duplex)
5805 tg3_link_report(tp);
5811 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
5815 u16 current_speed = SPEED_UNKNOWN;
5816 u8 current_duplex = DUPLEX_UNKNOWN;
5817 bool current_link_up = false;
5818 u32 local_adv, remote_adv, sgsr;
5820 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5821 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5822 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5823 (sgsr & SERDES_TG3_SGMII_MODE)) {
5828 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5830 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5831 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5833 current_link_up = true;
5834 if (sgsr & SERDES_TG3_SPEED_1000) {
5835 current_speed = SPEED_1000;
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5837 } else if (sgsr & SERDES_TG3_SPEED_100) {
5838 current_speed = SPEED_100;
5839 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5841 current_speed = SPEED_10;
5842 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5845 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5846 current_duplex = DUPLEX_FULL;
5848 current_duplex = DUPLEX_HALF;
5851 tw32_f(MAC_MODE, tp->mac_mode);
5854 tg3_clear_mac_status(tp);
5856 goto fiber_setup_done;
5859 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5860 tw32_f(MAC_MODE, tp->mac_mode);
5863 tg3_clear_mac_status(tp);
5868 tp->link_config.rmt_adv = 0;
5870 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5871 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5872 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5873 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5874 bmsr |= BMSR_LSTATUS;
5876 bmsr &= ~BMSR_LSTATUS;
5879 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5881 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5882 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5883 /* do nothing, just check for link up at the end */
5884 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5887 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5888 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5889 ADVERTISE_1000XPAUSE |
5890 ADVERTISE_1000XPSE_ASYM |
5893 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5894 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5896 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5897 tg3_writephy(tp, MII_ADVERTISE, newadv);
5898 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5899 tg3_writephy(tp, MII_BMCR, bmcr);
5901 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5902 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5903 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5910 bmcr &= ~BMCR_SPEED1000;
5911 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5913 if (tp->link_config.duplex == DUPLEX_FULL)
5914 new_bmcr |= BMCR_FULLDPLX;
5916 if (new_bmcr != bmcr) {
5917 /* BMCR_SPEED1000 is a reserved bit that needs
5918 * to be set on write.
5920 new_bmcr |= BMCR_SPEED1000;
5922 /* Force a linkdown */
5926 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5927 adv &= ~(ADVERTISE_1000XFULL |
5928 ADVERTISE_1000XHALF |
5930 tg3_writephy(tp, MII_ADVERTISE, adv);
5931 tg3_writephy(tp, MII_BMCR, bmcr |
5935 tg3_carrier_off(tp);
5937 tg3_writephy(tp, MII_BMCR, new_bmcr);
5939 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5940 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5941 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5942 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5943 bmsr |= BMSR_LSTATUS;
5945 bmsr &= ~BMSR_LSTATUS;
5947 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5951 if (bmsr & BMSR_LSTATUS) {
5952 current_speed = SPEED_1000;
5953 current_link_up = true;
5954 if (bmcr & BMCR_FULLDPLX)
5955 current_duplex = DUPLEX_FULL;
5957 current_duplex = DUPLEX_HALF;
5962 if (bmcr & BMCR_ANENABLE) {
5965 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5966 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5967 common = local_adv & remote_adv;
5968 if (common & (ADVERTISE_1000XHALF |
5969 ADVERTISE_1000XFULL)) {
5970 if (common & ADVERTISE_1000XFULL)
5971 current_duplex = DUPLEX_FULL;
5973 current_duplex = DUPLEX_HALF;
5975 tp->link_config.rmt_adv =
5976 mii_adv_to_ethtool_adv_x(remote_adv);
5977 } else if (!tg3_flag(tp, 5780_CLASS)) {
5978 /* Link is up via parallel detect */
5980 current_link_up = false;
5986 if (current_link_up && current_duplex == DUPLEX_FULL)
5987 tg3_setup_flow_control(tp, local_adv, remote_adv);
5989 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5990 if (tp->link_config.active_duplex == DUPLEX_HALF)
5991 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5993 tw32_f(MAC_MODE, tp->mac_mode);
5996 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5998 tp->link_config.active_speed = current_speed;
5999 tp->link_config.active_duplex = current_duplex;
6001 tg3_test_and_report_link_chg(tp, current_link_up);
6005 static void tg3_serdes_parallel_detect(struct tg3 *tp)
6007 if (tp->serdes_counter) {
6008 /* Give autoneg time to complete. */
6009 tp->serdes_counter--;
6014 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6017 tg3_readphy(tp, MII_BMCR, &bmcr);
6018 if (bmcr & BMCR_ANENABLE) {
6021 /* Select shadow register 0x1f */
6022 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6023 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
6025 /* Select expansion interrupt status register */
6026 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6027 MII_TG3_DSP_EXP1_INT_STAT);
6028 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6029 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6031 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6032 /* We have signal detect and not receiving
6033 * config code words, link is up by parallel
6037 bmcr &= ~BMCR_ANENABLE;
6038 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6039 tg3_writephy(tp, MII_BMCR, bmcr);
6040 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
6043 } else if (tp->link_up &&
6044 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
6045 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
6048 /* Select expansion interrupt status register */
6049 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6050 MII_TG3_DSP_EXP1_INT_STAT);
6051 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6055 /* Config code words received, turn on autoneg. */
6056 tg3_readphy(tp, MII_BMCR, &bmcr);
6057 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6059 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
6065 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
6070 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
6071 err = tg3_setup_fiber_phy(tp, force_reset);
6072 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
6073 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6075 err = tg3_setup_copper_phy(tp, force_reset);
6077 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
6080 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6081 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6083 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6088 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6089 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6090 tw32(GRC_MISC_CFG, val);
6093 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6094 (6 << TX_LENGTHS_IPG_SHIFT);
6095 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6096 tg3_asic_rev(tp) == ASIC_REV_5762)
6097 val |= tr32(MAC_TX_LENGTHS) &
6098 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6099 TX_LENGTHS_CNT_DWN_VAL_MSK);
6101 if (tp->link_config.active_speed == SPEED_1000 &&
6102 tp->link_config.active_duplex == DUPLEX_HALF)
6103 tw32(MAC_TX_LENGTHS, val |
6104 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
6106 tw32(MAC_TX_LENGTHS, val |
6107 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6109 if (!tg3_flag(tp, 5705_PLUS)) {
6111 tw32(HOSTCC_STAT_COAL_TICKS,
6112 tp->coal.stats_block_coalesce_usecs);
6114 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6118 if (tg3_flag(tp, ASPM_WORKAROUND)) {
6119 val = tr32(PCIE_PWR_MGMT_THRESH);
6121 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6124 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6125 tw32(PCIE_PWR_MGMT_THRESH, val);
6131 /* tp->lock must be held */
6132 static u64 tg3_refclk_read(struct tg3 *tp)
6134 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6135 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6138 /* tp->lock must be held */
6139 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6141 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6143 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6144 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6145 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6146 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
6149 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6150 static inline void tg3_full_unlock(struct tg3 *tp);
6151 static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6153 struct tg3 *tp = netdev_priv(dev);
6155 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6156 SOF_TIMESTAMPING_RX_SOFTWARE |
6157 SOF_TIMESTAMPING_SOFTWARE;
6159 if (tg3_flag(tp, PTP_CAPABLE)) {
6160 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
6161 SOF_TIMESTAMPING_RX_HARDWARE |
6162 SOF_TIMESTAMPING_RAW_HARDWARE;
6166 info->phc_index = ptp_clock_index(tp->ptp_clock);
6168 info->phc_index = -1;
6170 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6172 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6173 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6174 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6175 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6179 static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6181 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6182 bool neg_adj = false;
6190 /* Frequency adjustment is performed using hardware with a 24 bit
6191 * accumulator and a programmable correction value. On each clk, the
6192 * correction value gets added to the accumulator and when it
6193 * overflows, the time counter is incremented/decremented.
6195 * So conversion from ppb to correction value is
6196 * ppb * (1 << 24) / 1000000000
6198 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6199 TG3_EAV_REF_CLK_CORRECT_MASK;
6201 tg3_full_lock(tp, 0);
6204 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6205 TG3_EAV_REF_CLK_CORRECT_EN |
6206 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6208 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6210 tg3_full_unlock(tp);
6215 static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6217 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6219 tg3_full_lock(tp, 0);
6220 tp->ptp_adjust += delta;
6221 tg3_full_unlock(tp);
6226 static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6230 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6232 tg3_full_lock(tp, 0);
6233 ns = tg3_refclk_read(tp);
6234 ns += tp->ptp_adjust;
6235 tg3_full_unlock(tp);
6237 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6238 ts->tv_nsec = remainder;
6243 static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6244 const struct timespec *ts)
6247 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6249 ns = timespec_to_ns(ts);
6251 tg3_full_lock(tp, 0);
6252 tg3_refclk_write(tp, ns);
6254 tg3_full_unlock(tp);
6259 static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6260 struct ptp_clock_request *rq, int on)
6262 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6267 case PTP_CLK_REQ_PEROUT:
6268 if (rq->perout.index != 0)
6271 tg3_full_lock(tp, 0);
6272 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6273 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6278 nsec = rq->perout.start.sec * 1000000000ULL +
6279 rq->perout.start.nsec;
6281 if (rq->perout.period.sec || rq->perout.period.nsec) {
6282 netdev_warn(tp->dev,
6283 "Device supports only a one-shot timesync output, period must be 0\n");
6288 if (nsec & (1ULL << 63)) {
6289 netdev_warn(tp->dev,
6290 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6295 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6296 tw32(TG3_EAV_WATCHDOG0_MSB,
6297 TG3_EAV_WATCHDOG0_EN |
6298 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6300 tw32(TG3_EAV_REF_CLCK_CTL,
6301 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6303 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6304 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6308 tg3_full_unlock(tp);
6318 static const struct ptp_clock_info tg3_ptp_caps = {
6319 .owner = THIS_MODULE,
6320 .name = "tg3 clock",
6321 .max_adj = 250000000,
6326 .adjfreq = tg3_ptp_adjfreq,
6327 .adjtime = tg3_ptp_adjtime,
6328 .gettime = tg3_ptp_gettime,
6329 .settime = tg3_ptp_settime,
6330 .enable = tg3_ptp_enable,
6333 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6334 struct skb_shared_hwtstamps *timestamp)
6336 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6337 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6341 /* tp->lock must be held */
6342 static void tg3_ptp_init(struct tg3 *tp)
6344 if (!tg3_flag(tp, PTP_CAPABLE))
6347 /* Initialize the hardware clock to the system time. */
6348 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6350 tp->ptp_info = tg3_ptp_caps;
6353 /* tp->lock must be held */
6354 static void tg3_ptp_resume(struct tg3 *tp)
6356 if (!tg3_flag(tp, PTP_CAPABLE))
6359 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6363 static void tg3_ptp_fini(struct tg3 *tp)
6365 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6368 ptp_clock_unregister(tp->ptp_clock);
6369 tp->ptp_clock = NULL;
6373 static inline int tg3_irq_sync(struct tg3 *tp)
6375 return tp->irq_sync;
6378 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6382 dst = (u32 *)((u8 *)dst + off);
6383 for (i = 0; i < len; i += sizeof(u32))
6384 *dst++ = tr32(off + i);
6387 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6389 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6390 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6391 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6392 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6393 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6394 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6395 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6396 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6397 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6398 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6399 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6400 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6401 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6402 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6403 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6404 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6405 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6406 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6407 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6409 if (tg3_flag(tp, SUPPORT_MSIX))
6410 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6412 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6413 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6414 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6415 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6416 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6417 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6418 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6419 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6421 if (!tg3_flag(tp, 5705_PLUS)) {
6422 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6423 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6424 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6427 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6428 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6429 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6430 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6431 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6433 if (tg3_flag(tp, NVRAM))
6434 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6437 static void tg3_dump_state(struct tg3 *tp)
6442 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
6446 if (tg3_flag(tp, PCI_EXPRESS)) {
6447 /* Read up to but not including private PCI registers */
6448 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6449 regs[i / sizeof(u32)] = tr32(i);
6451 tg3_dump_legacy_regs(tp, regs);
6453 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6454 if (!regs[i + 0] && !regs[i + 1] &&
6455 !regs[i + 2] && !regs[i + 3])
6458 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6460 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6465 for (i = 0; i < tp->irq_cnt; i++) {
6466 struct tg3_napi *tnapi = &tp->napi[i];
6468 /* SW status block */
6470 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6472 tnapi->hw_status->status,
6473 tnapi->hw_status->status_tag,
6474 tnapi->hw_status->rx_jumbo_consumer,
6475 tnapi->hw_status->rx_consumer,
6476 tnapi->hw_status->rx_mini_consumer,
6477 tnapi->hw_status->idx[0].rx_producer,
6478 tnapi->hw_status->idx[0].tx_consumer);
6481 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6483 tnapi->last_tag, tnapi->last_irq_tag,
6484 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6486 tnapi->prodring.rx_std_prod_idx,
6487 tnapi->prodring.rx_std_cons_idx,
6488 tnapi->prodring.rx_jmb_prod_idx,
6489 tnapi->prodring.rx_jmb_cons_idx);
6493 /* This is called whenever we suspect that the system chipset is re-
6494 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6495 * is bogus tx completions. We try to recover by setting the
6496 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6499 static void tg3_tx_recover(struct tg3 *tp)
6501 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6502 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6504 netdev_warn(tp->dev,
6505 "The system may be re-ordering memory-mapped I/O "
6506 "cycles to the network device, attempting to recover. "
6507 "Please report the problem to the driver maintainer "
6508 "and include system chipset information.\n");
6510 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6513 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
6515 /* Tell compiler to fetch tx indices from memory. */
6517 return tnapi->tx_pending -
6518 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
6521 /* Tigon3 never reports partial packet sends. So we do not
6522 * need special logic to handle SKBs that have not had all
6523 * of their frags sent yet, like SunGEM does.
6525 static void tg3_tx(struct tg3_napi *tnapi)
6527 struct tg3 *tp = tnapi->tp;
6528 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
6529 u32 sw_idx = tnapi->tx_cons;
6530 struct netdev_queue *txq;
6531 int index = tnapi - tp->napi;
6532 unsigned int pkts_compl = 0, bytes_compl = 0;
6534 if (tg3_flag(tp, ENABLE_TSS))
6537 txq = netdev_get_tx_queue(tp->dev, index);
6539 while (sw_idx != hw_idx) {
6540 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
6541 struct sk_buff *skb = ri->skb;
6544 if (unlikely(skb == NULL)) {
6549 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6550 struct skb_shared_hwtstamps timestamp;
6551 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6552 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6554 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6556 skb_tstamp_tx(skb, ×tamp);
6559 pci_unmap_single(tp->pdev,
6560 dma_unmap_addr(ri, mapping),
6566 while (ri->fragmented) {
6567 ri->fragmented = false;
6568 sw_idx = NEXT_TX(sw_idx);
6569 ri = &tnapi->tx_buffers[sw_idx];
6572 sw_idx = NEXT_TX(sw_idx);
6574 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6575 ri = &tnapi->tx_buffers[sw_idx];
6576 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6579 pci_unmap_page(tp->pdev,
6580 dma_unmap_addr(ri, mapping),
6581 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6584 while (ri->fragmented) {
6585 ri->fragmented = false;
6586 sw_idx = NEXT_TX(sw_idx);
6587 ri = &tnapi->tx_buffers[sw_idx];
6590 sw_idx = NEXT_TX(sw_idx);
6594 bytes_compl += skb->len;
6596 dev_kfree_skb_any(skb);
6598 if (unlikely(tx_bug)) {
6604 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
6606 tnapi->tx_cons = sw_idx;
6608 /* Need to make the tx_cons update visible to tg3_start_xmit()
6609 * before checking for netif_queue_stopped(). Without the
6610 * memory barrier, there is a small possibility that tg3_start_xmit()
6611 * will miss it and cause the queue to be stopped forever.
6615 if (unlikely(netif_tx_queue_stopped(txq) &&
6616 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
6617 __netif_tx_lock(txq, smp_processor_id());
6618 if (netif_tx_queue_stopped(txq) &&
6619 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
6620 netif_tx_wake_queue(txq);
6621 __netif_tx_unlock(txq);
6625 static void tg3_frag_free(bool is_frag, void *data)
6628 put_page(virt_to_head_page(data));
6633 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6635 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6636 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6641 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
6642 map_sz, PCI_DMA_FROMDEVICE);
6643 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
6648 /* Returns size of skb allocated or < 0 on error.
6650 * We only need to fill in the address because the other members
6651 * of the RX descriptor are invariant, see tg3_init_rings.
6653 * Note the purposeful assymetry of cpu vs. chip accesses. For
6654 * posting buffers we only dirty the first cache line of the RX
6655 * descriptor (containing the address). Whereas for the RX status
6656 * buffers the cpu only reads the last cacheline of the RX descriptor
6657 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6659 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6660 u32 opaque_key, u32 dest_idx_unmasked,
6661 unsigned int *frag_size)
6663 struct tg3_rx_buffer_desc *desc;
6664 struct ring_info *map;
6667 int skb_size, data_size, dest_idx;
6669 switch (opaque_key) {
6670 case RXD_OPAQUE_RING_STD:
6671 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6672 desc = &tpr->rx_std[dest_idx];
6673 map = &tpr->rx_std_buffers[dest_idx];
6674 data_size = tp->rx_pkt_map_sz;
6677 case RXD_OPAQUE_RING_JUMBO:
6678 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6679 desc = &tpr->rx_jmb[dest_idx].std;
6680 map = &tpr->rx_jmb_buffers[dest_idx];
6681 data_size = TG3_RX_JMB_MAP_SZ;
6688 /* Do not overwrite any of the map or rp information
6689 * until we are sure we can commit to a new buffer.
6691 * Callers depend upon this behavior and assume that
6692 * we leave everything unchanged if we fail.
6694 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6695 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6696 if (skb_size <= PAGE_SIZE) {
6697 data = netdev_alloc_frag(skb_size);
6698 *frag_size = skb_size;
6700 data = kmalloc(skb_size, GFP_ATOMIC);
6706 mapping = pci_map_single(tp->pdev,
6707 data + TG3_RX_OFFSET(tp),
6709 PCI_DMA_FROMDEVICE);
6710 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
6711 tg3_frag_free(skb_size <= PAGE_SIZE, data);
6716 dma_unmap_addr_set(map, mapping, mapping);
6718 desc->addr_hi = ((u64)mapping >> 32);
6719 desc->addr_lo = ((u64)mapping & 0xffffffff);
6724 /* We only need to move over in the address because the other
6725 * members of the RX descriptor are invariant. See notes above
6726 * tg3_alloc_rx_data for full details.
6728 static void tg3_recycle_rx(struct tg3_napi *tnapi,
6729 struct tg3_rx_prodring_set *dpr,
6730 u32 opaque_key, int src_idx,
6731 u32 dest_idx_unmasked)
6733 struct tg3 *tp = tnapi->tp;
6734 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6735 struct ring_info *src_map, *dest_map;
6736 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6739 switch (opaque_key) {
6740 case RXD_OPAQUE_RING_STD:
6741 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6742 dest_desc = &dpr->rx_std[dest_idx];
6743 dest_map = &dpr->rx_std_buffers[dest_idx];
6744 src_desc = &spr->rx_std[src_idx];
6745 src_map = &spr->rx_std_buffers[src_idx];
6748 case RXD_OPAQUE_RING_JUMBO:
6749 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6750 dest_desc = &dpr->rx_jmb[dest_idx].std;
6751 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6752 src_desc = &spr->rx_jmb[src_idx].std;
6753 src_map = &spr->rx_jmb_buffers[src_idx];
6760 dest_map->data = src_map->data;
6761 dma_unmap_addr_set(dest_map, mapping,
6762 dma_unmap_addr(src_map, mapping));
6763 dest_desc->addr_hi = src_desc->addr_hi;
6764 dest_desc->addr_lo = src_desc->addr_lo;
6766 /* Ensure that the update to the skb happens after the physical
6767 * addresses have been transferred to the new BD location.
6771 src_map->data = NULL;
6774 /* The RX ring scheme is composed of multiple rings which post fresh
6775 * buffers to the chip, and one special ring the chip uses to report
6776 * status back to the host.
6778 * The special ring reports the status of received packets to the
6779 * host. The chip does not write into the original descriptor the
6780 * RX buffer was obtained from. The chip simply takes the original
6781 * descriptor as provided by the host, updates the status and length
6782 * field, then writes this into the next status ring entry.
6784 * Each ring the host uses to post buffers to the chip is described
6785 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6786 * it is first placed into the on-chip ram. When the packet's length
6787 * is known, it walks down the TG3_BDINFO entries to select the ring.
6788 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6789 * which is within the range of the new packet's length is chosen.
6791 * The "separate ring for rx status" scheme may sound queer, but it makes
6792 * sense from a cache coherency perspective. If only the host writes
6793 * to the buffer post rings, and only the chip writes to the rx status
6794 * rings, then cache lines never move beyond shared-modified state.
6795 * If both the host and chip were to write into the same ring, cache line
6796 * eviction could occur since both entities want it in an exclusive state.
6798 static int tg3_rx(struct tg3_napi *tnapi, int budget)
6800 struct tg3 *tp = tnapi->tp;
6801 u32 work_mask, rx_std_posted = 0;
6802 u32 std_prod_idx, jmb_prod_idx;
6803 u32 sw_idx = tnapi->rx_rcb_ptr;
6806 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
6808 hw_idx = *(tnapi->rx_rcb_prod_idx);
6810 * We need to order the read of hw_idx and the read of
6811 * the opaque cookie.
6816 std_prod_idx = tpr->rx_std_prod_idx;
6817 jmb_prod_idx = tpr->rx_jmb_prod_idx;
6818 while (sw_idx != hw_idx && budget > 0) {
6819 struct ring_info *ri;
6820 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
6822 struct sk_buff *skb;
6823 dma_addr_t dma_addr;
6824 u32 opaque_key, desc_idx, *post_ptr;
6828 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6829 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6830 if (opaque_key == RXD_OPAQUE_RING_STD) {
6831 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6832 dma_addr = dma_unmap_addr(ri, mapping);
6834 post_ptr = &std_prod_idx;
6836 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
6837 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6838 dma_addr = dma_unmap_addr(ri, mapping);
6840 post_ptr = &jmb_prod_idx;
6842 goto next_pkt_nopost;
6844 work_mask |= opaque_key;
6846 if (desc->err_vlan & RXD_ERR_MASK) {
6848 tg3_recycle_rx(tnapi, tpr, opaque_key,
6849 desc_idx, *post_ptr);
6851 /* Other statistics kept track of by card. */
6856 prefetch(data + TG3_RX_OFFSET(tp));
6857 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6860 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6861 RXD_FLAG_PTPSTAT_PTPV1 ||
6862 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6863 RXD_FLAG_PTPSTAT_PTPV2) {
6864 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6865 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6868 if (len > TG3_RX_COPY_THRESH(tp)) {
6870 unsigned int frag_size;
6872 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6873 *post_ptr, &frag_size);
6877 pci_unmap_single(tp->pdev, dma_addr, skb_size,
6878 PCI_DMA_FROMDEVICE);
6880 /* Ensure that the update to the data happens
6881 * after the usage of the old DMA mapping.
6887 skb = build_skb(data, frag_size);
6889 tg3_frag_free(frag_size != 0, data);
6890 goto drop_it_no_recycle;
6892 skb_reserve(skb, TG3_RX_OFFSET(tp));
6894 tg3_recycle_rx(tnapi, tpr, opaque_key,
6895 desc_idx, *post_ptr);
6897 skb = netdev_alloc_skb(tp->dev,
6898 len + TG3_RAW_IP_ALIGN);
6900 goto drop_it_no_recycle;
6902 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6903 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6905 data + TG3_RX_OFFSET(tp),
6907 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6912 tg3_hwclock_to_timestamp(tp, tstamp,
6913 skb_hwtstamps(skb));
6915 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6916 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6917 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6918 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6919 skb->ip_summed = CHECKSUM_UNNECESSARY;
6921 skb_checksum_none_assert(skb);
6923 skb->protocol = eth_type_trans(skb, tp->dev);
6925 if (len > (tp->dev->mtu + ETH_HLEN) &&
6926 skb->protocol != htons(ETH_P_8021Q)) {
6927 dev_kfree_skb_any(skb);
6928 goto drop_it_no_recycle;
6931 if (desc->type_flags & RXD_FLAG_VLAN &&
6932 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6933 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
6934 desc->err_vlan & RXD_VLAN_MASK);
6936 napi_gro_receive(&tnapi->napi, skb);
6944 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6945 tpr->rx_std_prod_idx = std_prod_idx &
6946 tp->rx_std_ring_mask;
6947 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6948 tpr->rx_std_prod_idx);
6949 work_mask &= ~RXD_OPAQUE_RING_STD;
6954 sw_idx &= tp->rx_ret_ring_mask;
6956 /* Refresh hw_idx to see if there is new work */
6957 if (sw_idx == hw_idx) {
6958 hw_idx = *(tnapi->rx_rcb_prod_idx);
6963 /* ACK the status ring. */
6964 tnapi->rx_rcb_ptr = sw_idx;
6965 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6967 /* Refill RX ring(s). */
6968 if (!tg3_flag(tp, ENABLE_RSS)) {
6969 /* Sync BD data before updating mailbox */
6972 if (work_mask & RXD_OPAQUE_RING_STD) {
6973 tpr->rx_std_prod_idx = std_prod_idx &
6974 tp->rx_std_ring_mask;
6975 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6976 tpr->rx_std_prod_idx);
6978 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6979 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6980 tp->rx_jmb_ring_mask;
6981 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6982 tpr->rx_jmb_prod_idx);
6985 } else if (work_mask) {
6986 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6987 * updated before the producer indices can be updated.
6991 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6992 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
6994 if (tnapi != &tp->napi[1]) {
6995 tp->rx_refill = true;
6996 napi_schedule(&tp->napi[1].napi);
7003 static void tg3_poll_link(struct tg3 *tp)
7005 /* handle link change and other phy events */
7006 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
7007 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7009 if (sblk->status & SD_STATUS_LINK_CHG) {
7010 sblk->status = SD_STATUS_UPDATED |
7011 (sblk->status & ~SD_STATUS_LINK_CHG);
7012 spin_lock(&tp->lock);
7013 if (tg3_flag(tp, USE_PHYLIB)) {
7015 (MAC_STATUS_SYNC_CHANGED |
7016 MAC_STATUS_CFG_CHANGED |
7017 MAC_STATUS_MI_COMPLETION |
7018 MAC_STATUS_LNKSTATE_CHANGED));
7021 tg3_setup_phy(tp, false);
7022 spin_unlock(&tp->lock);
7027 static int tg3_rx_prodring_xfer(struct tg3 *tp,
7028 struct tg3_rx_prodring_set *dpr,
7029 struct tg3_rx_prodring_set *spr)
7031 u32 si, di, cpycnt, src_prod_idx;
7035 src_prod_idx = spr->rx_std_prod_idx;
7037 /* Make sure updates to the rx_std_buffers[] entries and the
7038 * standard producer index are seen in the correct order.
7042 if (spr->rx_std_cons_idx == src_prod_idx)
7045 if (spr->rx_std_cons_idx < src_prod_idx)
7046 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7048 cpycnt = tp->rx_std_ring_mask + 1 -
7049 spr->rx_std_cons_idx;
7051 cpycnt = min(cpycnt,
7052 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
7054 si = spr->rx_std_cons_idx;
7055 di = dpr->rx_std_prod_idx;
7057 for (i = di; i < di + cpycnt; i++) {
7058 if (dpr->rx_std_buffers[i].data) {
7068 /* Ensure that updates to the rx_std_buffers ring and the
7069 * shadowed hardware producer ring from tg3_recycle_skb() are
7070 * ordered correctly WRT the skb check above.
7074 memcpy(&dpr->rx_std_buffers[di],
7075 &spr->rx_std_buffers[si],
7076 cpycnt * sizeof(struct ring_info));
7078 for (i = 0; i < cpycnt; i++, di++, si++) {
7079 struct tg3_rx_buffer_desc *sbd, *dbd;
7080 sbd = &spr->rx_std[si];
7081 dbd = &dpr->rx_std[di];
7082 dbd->addr_hi = sbd->addr_hi;
7083 dbd->addr_lo = sbd->addr_lo;
7086 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7087 tp->rx_std_ring_mask;
7088 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7089 tp->rx_std_ring_mask;
7093 src_prod_idx = spr->rx_jmb_prod_idx;
7095 /* Make sure updates to the rx_jmb_buffers[] entries and
7096 * the jumbo producer index are seen in the correct order.
7100 if (spr->rx_jmb_cons_idx == src_prod_idx)
7103 if (spr->rx_jmb_cons_idx < src_prod_idx)
7104 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7106 cpycnt = tp->rx_jmb_ring_mask + 1 -
7107 spr->rx_jmb_cons_idx;
7109 cpycnt = min(cpycnt,
7110 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
7112 si = spr->rx_jmb_cons_idx;
7113 di = dpr->rx_jmb_prod_idx;
7115 for (i = di; i < di + cpycnt; i++) {
7116 if (dpr->rx_jmb_buffers[i].data) {
7126 /* Ensure that updates to the rx_jmb_buffers ring and the
7127 * shadowed hardware producer ring from tg3_recycle_skb() are
7128 * ordered correctly WRT the skb check above.
7132 memcpy(&dpr->rx_jmb_buffers[di],
7133 &spr->rx_jmb_buffers[si],
7134 cpycnt * sizeof(struct ring_info));
7136 for (i = 0; i < cpycnt; i++, di++, si++) {
7137 struct tg3_rx_buffer_desc *sbd, *dbd;
7138 sbd = &spr->rx_jmb[si].std;
7139 dbd = &dpr->rx_jmb[di].std;
7140 dbd->addr_hi = sbd->addr_hi;
7141 dbd->addr_lo = sbd->addr_lo;
7144 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7145 tp->rx_jmb_ring_mask;
7146 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7147 tp->rx_jmb_ring_mask;
7153 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7155 struct tg3 *tp = tnapi->tp;
7157 /* run TX completion thread */
7158 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
7160 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7164 if (!tnapi->rx_rcb_prod_idx)
7167 /* run RX thread, within the bounds set by NAPI.
7168 * All RX "locking" is done by ensuring outside
7169 * code synchronizes with tg3->napi.poll()
7171 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
7172 work_done += tg3_rx(tnapi, budget - work_done);
7174 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
7175 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
7177 u32 std_prod_idx = dpr->rx_std_prod_idx;
7178 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
7180 tp->rx_refill = false;
7181 for (i = 1; i <= tp->rxq_cnt; i++)
7182 err |= tg3_rx_prodring_xfer(tp, dpr,
7183 &tp->napi[i].prodring);
7187 if (std_prod_idx != dpr->rx_std_prod_idx)
7188 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7189 dpr->rx_std_prod_idx);
7191 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7192 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7193 dpr->rx_jmb_prod_idx);
7198 tw32_f(HOSTCC_MODE, tp->coal_now);
7204 static inline void tg3_reset_task_schedule(struct tg3 *tp)
7206 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7207 schedule_work(&tp->reset_task);
7210 static inline void tg3_reset_task_cancel(struct tg3 *tp)
7212 cancel_work_sync(&tp->reset_task);
7213 tg3_flag_clear(tp, RESET_TASK_PENDING);
7214 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7217 static int tg3_poll_msix(struct napi_struct *napi, int budget)
7219 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7220 struct tg3 *tp = tnapi->tp;
7222 struct tg3_hw_status *sblk = tnapi->hw_status;
7225 work_done = tg3_poll_work(tnapi, work_done, budget);
7227 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7230 if (unlikely(work_done >= budget))
7233 /* tp->last_tag is used in tg3_int_reenable() below
7234 * to tell the hw how much work has been processed,
7235 * so we must read it before checking for more work.
7237 tnapi->last_tag = sblk->status_tag;
7238 tnapi->last_irq_tag = tnapi->last_tag;
7241 /* check for RX/TX work to do */
7242 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7243 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7245 /* This test here is not race free, but will reduce
7246 * the number of interrupts by looping again.
7248 if (tnapi == &tp->napi[1] && tp->rx_refill)
7251 napi_complete(napi);
7252 /* Reenable interrupts. */
7253 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7255 /* This test here is synchronized by napi_schedule()
7256 * and napi_complete() to close the race condition.
7258 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7259 tw32(HOSTCC_MODE, tp->coalesce_mode |
7260 HOSTCC_MODE_ENABLE |
7271 /* work_done is guaranteed to be less than budget. */
7272 napi_complete(napi);
7273 tg3_reset_task_schedule(tp);
7277 static void tg3_process_error(struct tg3 *tp)
7280 bool real_error = false;
7282 if (tg3_flag(tp, ERROR_PROCESSED))
7285 /* Check Flow Attention register */
7286 val = tr32(HOSTCC_FLOW_ATTN);
7287 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7288 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7292 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7293 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7297 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7298 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7307 tg3_flag_set(tp, ERROR_PROCESSED);
7308 tg3_reset_task_schedule(tp);
7311 static int tg3_poll(struct napi_struct *napi, int budget)
7313 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7314 struct tg3 *tp = tnapi->tp;
7316 struct tg3_hw_status *sblk = tnapi->hw_status;
7319 if (sblk->status & SD_STATUS_ERROR)
7320 tg3_process_error(tp);
7324 work_done = tg3_poll_work(tnapi, work_done, budget);
7326 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7329 if (unlikely(work_done >= budget))
7332 if (tg3_flag(tp, TAGGED_STATUS)) {
7333 /* tp->last_tag is used in tg3_int_reenable() below
7334 * to tell the hw how much work has been processed,
7335 * so we must read it before checking for more work.
7337 tnapi->last_tag = sblk->status_tag;
7338 tnapi->last_irq_tag = tnapi->last_tag;
7341 sblk->status &= ~SD_STATUS_UPDATED;
7343 if (likely(!tg3_has_work(tnapi))) {
7344 napi_complete(napi);
7345 tg3_int_reenable(tnapi);
7353 /* work_done is guaranteed to be less than budget. */
7354 napi_complete(napi);
7355 tg3_reset_task_schedule(tp);
7359 static void tg3_napi_disable(struct tg3 *tp)
7363 for (i = tp->irq_cnt - 1; i >= 0; i--)
7364 napi_disable(&tp->napi[i].napi);
7367 static void tg3_napi_enable(struct tg3 *tp)
7371 for (i = 0; i < tp->irq_cnt; i++)
7372 napi_enable(&tp->napi[i].napi);
7375 static void tg3_napi_init(struct tg3 *tp)
7379 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7380 for (i = 1; i < tp->irq_cnt; i++)
7381 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7384 static void tg3_napi_fini(struct tg3 *tp)
7388 for (i = 0; i < tp->irq_cnt; i++)
7389 netif_napi_del(&tp->napi[i].napi);
7392 static inline void tg3_netif_stop(struct tg3 *tp)
7394 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7395 tg3_napi_disable(tp);
7396 netif_carrier_off(tp->dev);
7397 netif_tx_disable(tp->dev);
7400 /* tp->lock must be held */
7401 static inline void tg3_netif_start(struct tg3 *tp)
7405 /* NOTE: unconditional netif_tx_wake_all_queues is only
7406 * appropriate so long as all callers are assured to
7407 * have free tx slots (such as after tg3_init_hw)
7409 netif_tx_wake_all_queues(tp->dev);
7412 netif_carrier_on(tp->dev);
7414 tg3_napi_enable(tp);
7415 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7416 tg3_enable_ints(tp);
7419 static void tg3_irq_quiesce(struct tg3 *tp)
7423 BUG_ON(tp->irq_sync);
7428 for (i = 0; i < tp->irq_cnt; i++)
7429 synchronize_irq(tp->napi[i].irq_vec);
7432 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7433 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7434 * with as well. Most of the time, this is not necessary except when
7435 * shutting down the device.
7437 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7439 spin_lock_bh(&tp->lock);
7441 tg3_irq_quiesce(tp);
7444 static inline void tg3_full_unlock(struct tg3 *tp)
7446 spin_unlock_bh(&tp->lock);
7449 /* One-shot MSI handler - Chip automatically disables interrupt
7450 * after sending MSI so driver doesn't have to do it.
7452 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
7454 struct tg3_napi *tnapi = dev_id;
7455 struct tg3 *tp = tnapi->tp;
7457 prefetch(tnapi->hw_status);
7459 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7461 if (likely(!tg3_irq_sync(tp)))
7462 napi_schedule(&tnapi->napi);
7467 /* MSI ISR - No need to check for interrupt sharing and no need to
7468 * flush status block and interrupt mailbox. PCI ordering rules
7469 * guarantee that MSI will arrive after the status block.
7471 static irqreturn_t tg3_msi(int irq, void *dev_id)
7473 struct tg3_napi *tnapi = dev_id;
7474 struct tg3 *tp = tnapi->tp;
7476 prefetch(tnapi->hw_status);
7478 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7480 * Writing any value to intr-mbox-0 clears PCI INTA# and
7481 * chip-internal interrupt pending events.
7482 * Writing non-zero to intr-mbox-0 additional tells the
7483 * NIC to stop sending us irqs, engaging "in-intr-handler"
7486 tw32_mailbox(tnapi->int_mbox, 0x00000001);
7487 if (likely(!tg3_irq_sync(tp)))
7488 napi_schedule(&tnapi->napi);
7490 return IRQ_RETVAL(1);
7493 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
7495 struct tg3_napi *tnapi = dev_id;
7496 struct tg3 *tp = tnapi->tp;
7497 struct tg3_hw_status *sblk = tnapi->hw_status;
7498 unsigned int handled = 1;
7500 /* In INTx mode, it is possible for the interrupt to arrive at
7501 * the CPU before the status block posted prior to the interrupt.
7502 * Reading the PCI State register will confirm whether the
7503 * interrupt is ours and will flush the status block.
7505 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
7506 if (tg3_flag(tp, CHIP_RESETTING) ||
7507 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7514 * Writing any value to intr-mbox-0 clears PCI INTA# and
7515 * chip-internal interrupt pending events.
7516 * Writing non-zero to intr-mbox-0 additional tells the
7517 * NIC to stop sending us irqs, engaging "in-intr-handler"
7520 * Flush the mailbox to de-assert the IRQ immediately to prevent
7521 * spurious interrupts. The flush impacts performance but
7522 * excessive spurious interrupts can be worse in some cases.
7524 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7525 if (tg3_irq_sync(tp))
7527 sblk->status &= ~SD_STATUS_UPDATED;
7528 if (likely(tg3_has_work(tnapi))) {
7529 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7530 napi_schedule(&tnapi->napi);
7532 /* No work, shared interrupt perhaps? re-enable
7533 * interrupts, and flush that PCI write
7535 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7539 return IRQ_RETVAL(handled);
7542 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
7544 struct tg3_napi *tnapi = dev_id;
7545 struct tg3 *tp = tnapi->tp;
7546 struct tg3_hw_status *sblk = tnapi->hw_status;
7547 unsigned int handled = 1;
7549 /* In INTx mode, it is possible for the interrupt to arrive at
7550 * the CPU before the status block posted prior to the interrupt.
7551 * Reading the PCI State register will confirm whether the
7552 * interrupt is ours and will flush the status block.
7554 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
7555 if (tg3_flag(tp, CHIP_RESETTING) ||
7556 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7563 * writing any value to intr-mbox-0 clears PCI INTA# and
7564 * chip-internal interrupt pending events.
7565 * writing non-zero to intr-mbox-0 additional tells the
7566 * NIC to stop sending us irqs, engaging "in-intr-handler"
7569 * Flush the mailbox to de-assert the IRQ immediately to prevent
7570 * spurious interrupts. The flush impacts performance but
7571 * excessive spurious interrupts can be worse in some cases.
7573 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7576 * In a shared interrupt configuration, sometimes other devices'
7577 * interrupts will scream. We record the current status tag here
7578 * so that the above check can report that the screaming interrupts
7579 * are unhandled. Eventually they will be silenced.
7581 tnapi->last_irq_tag = sblk->status_tag;
7583 if (tg3_irq_sync(tp))
7586 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7588 napi_schedule(&tnapi->napi);
7591 return IRQ_RETVAL(handled);
7594 /* ISR for interrupt test */
7595 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7597 struct tg3_napi *tnapi = dev_id;
7598 struct tg3 *tp = tnapi->tp;
7599 struct tg3_hw_status *sblk = tnapi->hw_status;
7601 if ((sblk->status & SD_STATUS_UPDATED) ||
7602 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7603 tg3_disable_ints(tp);
7604 return IRQ_RETVAL(1);
7606 return IRQ_RETVAL(0);
7609 #ifdef CONFIG_NET_POLL_CONTROLLER
7610 static void tg3_poll_controller(struct net_device *dev)
7613 struct tg3 *tp = netdev_priv(dev);
7615 if (tg3_irq_sync(tp))
7618 for (i = 0; i < tp->irq_cnt; i++)
7619 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7623 static void tg3_tx_timeout(struct net_device *dev)
7625 struct tg3 *tp = netdev_priv(dev);
7627 if (netif_msg_tx_err(tp)) {
7628 netdev_err(dev, "transmit timed out, resetting\n");
7632 tg3_reset_task_schedule(tp);
7635 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7636 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7638 u32 base = (u32) mapping & 0xffffffff;
7640 return base + len + 8 < base;
7643 /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7644 * of any 4GB boundaries: 4G, 8G, etc
7646 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7649 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7650 u32 base = (u32) mapping & 0xffffffff;
7652 return ((base + len + (mss & 0x3fff)) < base);
7657 /* Test for DMA addresses > 40-bit */
7658 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7661 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7662 if (tg3_flag(tp, 40BIT_DMA_BUG))
7663 return ((u64) mapping + len) > DMA_BIT_MASK(40);
7670 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
7671 dma_addr_t mapping, u32 len, u32 flags,
7674 txbd->addr_hi = ((u64) mapping >> 32);
7675 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7676 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7677 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
7680 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
7681 dma_addr_t map, u32 len, u32 flags,
7684 struct tg3 *tp = tnapi->tp;
7687 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7690 if (tg3_4g_overflow_test(map, len))
7693 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7696 if (tg3_40bit_overflow_test(tp, map, len))
7699 if (tp->dma_limit) {
7700 u32 prvidx = *entry;
7701 u32 tmp_flag = flags & ~TXD_FLAG_END;
7702 while (len > tp->dma_limit && *budget) {
7703 u32 frag_len = tp->dma_limit;
7704 len -= tp->dma_limit;
7706 /* Avoid the 8byte DMA problem */
7708 len += tp->dma_limit / 2;
7709 frag_len = tp->dma_limit / 2;
7712 tnapi->tx_buffers[*entry].fragmented = true;
7714 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7715 frag_len, tmp_flag, mss, vlan);
7718 *entry = NEXT_TX(*entry);
7725 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7726 len, flags, mss, vlan);
7728 *entry = NEXT_TX(*entry);
7731 tnapi->tx_buffers[prvidx].fragmented = false;
7735 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7736 len, flags, mss, vlan);
7737 *entry = NEXT_TX(*entry);
7743 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
7746 struct sk_buff *skb;
7747 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
7752 pci_unmap_single(tnapi->tp->pdev,
7753 dma_unmap_addr(txb, mapping),
7757 while (txb->fragmented) {
7758 txb->fragmented = false;
7759 entry = NEXT_TX(entry);
7760 txb = &tnapi->tx_buffers[entry];
7763 for (i = 0; i <= last; i++) {
7764 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7766 entry = NEXT_TX(entry);
7767 txb = &tnapi->tx_buffers[entry];
7769 pci_unmap_page(tnapi->tp->pdev,
7770 dma_unmap_addr(txb, mapping),
7771 skb_frag_size(frag), PCI_DMA_TODEVICE);
7773 while (txb->fragmented) {
7774 txb->fragmented = false;
7775 entry = NEXT_TX(entry);
7776 txb = &tnapi->tx_buffers[entry];
7781 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7782 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
7783 struct sk_buff **pskb,
7784 u32 *entry, u32 *budget,
7785 u32 base_flags, u32 mss, u32 vlan)
7787 struct tg3 *tp = tnapi->tp;
7788 struct sk_buff *new_skb, *skb = *pskb;
7789 dma_addr_t new_addr = 0;
7792 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7793 new_skb = skb_copy(skb, GFP_ATOMIC);
7795 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7797 new_skb = skb_copy_expand(skb,
7798 skb_headroom(skb) + more_headroom,
7799 skb_tailroom(skb), GFP_ATOMIC);
7805 /* New SKB is guaranteed to be linear. */
7806 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7808 /* Make sure the mapping succeeded */
7809 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
7810 dev_kfree_skb_any(new_skb);
7813 u32 save_entry = *entry;
7815 base_flags |= TXD_FLAG_END;
7817 tnapi->tx_buffers[*entry].skb = new_skb;
7818 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
7821 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
7822 new_skb->len, base_flags,
7824 tg3_tx_skb_unmap(tnapi, save_entry, -1);
7825 dev_kfree_skb_any(new_skb);
7831 dev_kfree_skb_any(skb);
7836 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
7838 /* Use GSO to workaround a rare TSO bug that may be triggered when the
7839 * TSO header is greater than 80 bytes.
7841 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
7843 struct sk_buff *segs, *nskb;
7844 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
7846 /* Estimate the number of fragments in the worst case */
7847 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
7848 netif_stop_queue(tp->dev);
7850 /* netif_tx_stop_queue() must be done before checking
7851 * checking tx index in tg3_tx_avail() below, because in
7852 * tg3_tx(), we update tx index before checking for
7853 * netif_tx_queue_stopped().
7856 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7857 return NETDEV_TX_BUSY;
7859 netif_wake_queue(tp->dev);
7862 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
7864 goto tg3_tso_bug_end;
7870 tg3_start_xmit(nskb, tp->dev);
7874 dev_kfree_skb_any(skb);
7876 return NETDEV_TX_OK;
7879 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
7880 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
7882 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
7884 struct tg3 *tp = netdev_priv(dev);
7885 u32 len, entry, base_flags, mss, vlan = 0;
7887 int i = -1, would_hit_hwbug;
7889 struct tg3_napi *tnapi;
7890 struct netdev_queue *txq;
7893 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7894 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7895 if (tg3_flag(tp, ENABLE_TSS))
7898 budget = tg3_tx_avail(tnapi);
7900 /* We are running in BH disabled context with netif_tx_lock
7901 * and TX reclaim runs via tp->napi.poll inside of a software
7902 * interrupt. Furthermore, IRQ processing runs lockless so we have
7903 * no IRQ context deadlocks to worry about either. Rejoice!
7905 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
7906 if (!netif_tx_queue_stopped(txq)) {
7907 netif_tx_stop_queue(txq);
7909 /* This is a hard error, log it. */
7911 "BUG! Tx Ring full when queue awake!\n");
7913 return NETDEV_TX_BUSY;
7916 entry = tnapi->tx_prod;
7918 if (skb->ip_summed == CHECKSUM_PARTIAL)
7919 base_flags |= TXD_FLAG_TCPUDP_CSUM;
7921 mss = skb_shinfo(skb)->gso_size;
7924 u32 tcp_opt_len, hdr_len;
7926 if (skb_header_cloned(skb) &&
7927 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7931 tcp_opt_len = tcp_optlen(skb);
7933 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
7935 if (!skb_is_gso_v6(skb)) {
7937 iph->tot_len = htons(mss + hdr_len);
7940 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7941 tg3_flag(tp, TSO_BUG))
7942 return tg3_tso_bug(tp, skb);
7944 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7945 TXD_FLAG_CPU_POST_DMA);
7947 if (tg3_flag(tp, HW_TSO_1) ||
7948 tg3_flag(tp, HW_TSO_2) ||
7949 tg3_flag(tp, HW_TSO_3)) {
7950 tcp_hdr(skb)->check = 0;
7951 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7953 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7958 if (tg3_flag(tp, HW_TSO_3)) {
7959 mss |= (hdr_len & 0xc) << 12;
7961 base_flags |= 0x00000010;
7962 base_flags |= (hdr_len & 0x3e0) << 5;
7963 } else if (tg3_flag(tp, HW_TSO_2))
7964 mss |= hdr_len << 9;
7965 else if (tg3_flag(tp, HW_TSO_1) ||
7966 tg3_asic_rev(tp) == ASIC_REV_5705) {
7967 if (tcp_opt_len || iph->ihl > 5) {
7970 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7971 mss |= (tsflags << 11);
7974 if (tcp_opt_len || iph->ihl > 5) {
7977 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7978 base_flags |= tsflags << 12;
7983 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7984 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7985 base_flags |= TXD_FLAG_JMB_PKT;
7987 if (vlan_tx_tag_present(skb)) {
7988 base_flags |= TXD_FLAG_VLAN;
7989 vlan = vlan_tx_tag_get(skb);
7992 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7993 tg3_flag(tp, TX_TSTAMP_EN)) {
7994 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7995 base_flags |= TXD_FLAG_HWTSTAMP;
7998 len = skb_headlen(skb);
8000 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
8001 if (pci_dma_mapping_error(tp->pdev, mapping))
8005 tnapi->tx_buffers[entry].skb = skb;
8006 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
8008 would_hit_hwbug = 0;
8010 if (tg3_flag(tp, 5701_DMA_BUG))
8011 would_hit_hwbug = 1;
8013 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
8014 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
8016 would_hit_hwbug = 1;
8017 } else if (skb_shinfo(skb)->nr_frags > 0) {
8020 if (!tg3_flag(tp, HW_TSO_1) &&
8021 !tg3_flag(tp, HW_TSO_2) &&
8022 !tg3_flag(tp, HW_TSO_3))
8025 /* Now loop through additional data
8026 * fragments, and queue them.
8028 last = skb_shinfo(skb)->nr_frags - 1;
8029 for (i = 0; i <= last; i++) {
8030 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8032 len = skb_frag_size(frag);
8033 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
8034 len, DMA_TO_DEVICE);
8036 tnapi->tx_buffers[entry].skb = NULL;
8037 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
8039 if (dma_mapping_error(&tp->pdev->dev, mapping))
8043 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
8045 ((i == last) ? TXD_FLAG_END : 0),
8047 would_hit_hwbug = 1;
8053 if (would_hit_hwbug) {
8054 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
8056 /* If the workaround fails due to memory/mapping
8057 * failure, silently drop this packet.
8059 entry = tnapi->tx_prod;
8060 budget = tg3_tx_avail(tnapi);
8061 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
8062 base_flags, mss, vlan))
8066 skb_tx_timestamp(skb);
8067 netdev_tx_sent_queue(txq, skb->len);
8069 /* Sync BD data before updating mailbox */
8072 /* Packets are ready, update Tx producer idx local and on card. */
8073 tw32_tx_mbox(tnapi->prodmbox, entry);
8075 tnapi->tx_prod = entry;
8076 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
8077 netif_tx_stop_queue(txq);
8079 /* netif_tx_stop_queue() must be done before checking
8080 * checking tx index in tg3_tx_avail() below, because in
8081 * tg3_tx(), we update tx index before checking for
8082 * netif_tx_queue_stopped().
8085 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
8086 netif_tx_wake_queue(txq);
8090 return NETDEV_TX_OK;
8093 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
8094 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
8096 dev_kfree_skb_any(skb);
8099 return NETDEV_TX_OK;
8102 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8105 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8106 MAC_MODE_PORT_MODE_MASK);
8108 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8110 if (!tg3_flag(tp, 5705_PLUS))
8111 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8113 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8114 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8116 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8118 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8120 if (tg3_flag(tp, 5705_PLUS) ||
8121 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
8122 tg3_asic_rev(tp) == ASIC_REV_5700)
8123 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8126 tw32(MAC_MODE, tp->mac_mode);
8130 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
8132 u32 val, bmcr, mac_mode, ptest = 0;
8134 tg3_phy_toggle_apd(tp, false);
8135 tg3_phy_toggle_automdix(tp, false);
8137 if (extlpbk && tg3_phy_set_extloopbk(tp))
8140 bmcr = BMCR_FULLDPLX;
8145 bmcr |= BMCR_SPEED100;
8149 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8151 bmcr |= BMCR_SPEED100;
8154 bmcr |= BMCR_SPEED1000;
8159 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8160 tg3_readphy(tp, MII_CTRL1000, &val);
8161 val |= CTL1000_AS_MASTER |
8162 CTL1000_ENABLE_MASTER;
8163 tg3_writephy(tp, MII_CTRL1000, val);
8165 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8166 MII_TG3_FET_PTEST_TRIM_2;
8167 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8170 bmcr |= BMCR_LOOPBACK;
8172 tg3_writephy(tp, MII_BMCR, bmcr);
8174 /* The write needs to be flushed for the FETs */
8175 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8176 tg3_readphy(tp, MII_BMCR, &bmcr);
8180 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
8181 tg3_asic_rev(tp) == ASIC_REV_5785) {
8182 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8183 MII_TG3_FET_PTEST_FRC_TX_LINK |
8184 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8186 /* The write needs to be flushed for the AC131 */
8187 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8190 /* Reset to prevent losing 1st rx packet intermittently */
8191 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8192 tg3_flag(tp, 5780_CLASS)) {
8193 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8195 tw32_f(MAC_RX_MODE, tp->rx_mode);
8198 mac_mode = tp->mac_mode &
8199 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8200 if (speed == SPEED_1000)
8201 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8203 mac_mode |= MAC_MODE_PORT_MODE_MII;
8205 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
8206 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8208 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8209 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8210 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8211 mac_mode |= MAC_MODE_LINK_POLARITY;
8213 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8214 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8217 tw32(MAC_MODE, mac_mode);
8223 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
8225 struct tg3 *tp = netdev_priv(dev);
8227 if (features & NETIF_F_LOOPBACK) {
8228 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8231 spin_lock_bh(&tp->lock);
8232 tg3_mac_loopback(tp, true);
8233 netif_carrier_on(tp->dev);
8234 spin_unlock_bh(&tp->lock);
8235 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8237 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8240 spin_lock_bh(&tp->lock);
8241 tg3_mac_loopback(tp, false);
8242 /* Force link status check */
8243 tg3_setup_phy(tp, true);
8244 spin_unlock_bh(&tp->lock);
8245 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8249 static netdev_features_t tg3_fix_features(struct net_device *dev,
8250 netdev_features_t features)
8252 struct tg3 *tp = netdev_priv(dev);
8254 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8255 features &= ~NETIF_F_ALL_TSO;
8260 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
8262 netdev_features_t changed = dev->features ^ features;
8264 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8265 tg3_set_loopback(dev, features);
8270 static void tg3_rx_prodring_free(struct tg3 *tp,
8271 struct tg3_rx_prodring_set *tpr)
8275 if (tpr != &tp->napi[0].prodring) {
8276 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
8277 i = (i + 1) & tp->rx_std_ring_mask)
8278 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8281 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8282 for (i = tpr->rx_jmb_cons_idx;
8283 i != tpr->rx_jmb_prod_idx;
8284 i = (i + 1) & tp->rx_jmb_ring_mask) {
8285 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8293 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8294 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8297 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8298 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8299 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8304 /* Initialize rx rings for packet processing.
8306 * The chip has been shut down and the driver detached from
8307 * the networking, so no interrupts or new tx packets will
8308 * end up in the driver. tp->{tx,}lock are held and thus
8311 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8312 struct tg3_rx_prodring_set *tpr)
8314 u32 i, rx_pkt_dma_sz;
8316 tpr->rx_std_cons_idx = 0;
8317 tpr->rx_std_prod_idx = 0;
8318 tpr->rx_jmb_cons_idx = 0;
8319 tpr->rx_jmb_prod_idx = 0;
8321 if (tpr != &tp->napi[0].prodring) {
8322 memset(&tpr->rx_std_buffers[0], 0,
8323 TG3_RX_STD_BUFF_RING_SIZE(tp));
8324 if (tpr->rx_jmb_buffers)
8325 memset(&tpr->rx_jmb_buffers[0], 0,
8326 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8330 /* Zero out all descriptors. */
8331 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8333 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
8334 if (tg3_flag(tp, 5780_CLASS) &&
8335 tp->dev->mtu > ETH_DATA_LEN)
8336 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8337 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8339 /* Initialize invariants of the rings, we only set this
8340 * stuff once. This works because the card does not
8341 * write into the rx buffer posting rings.
8343 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8344 struct tg3_rx_buffer_desc *rxd;
8346 rxd = &tpr->rx_std[i];
8347 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
8348 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8349 rxd->opaque = (RXD_OPAQUE_RING_STD |
8350 (i << RXD_OPAQUE_INDEX_SHIFT));
8353 /* Now allocate fresh SKBs for each rx ring. */
8354 for (i = 0; i < tp->rx_pending; i++) {
8355 unsigned int frag_size;
8357 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8359 netdev_warn(tp->dev,
8360 "Using a smaller RX standard ring. Only "
8361 "%d out of %d buffers were allocated "
8362 "successfully\n", i, tp->rx_pending);
8370 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8373 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8375 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8378 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8379 struct tg3_rx_buffer_desc *rxd;
8381 rxd = &tpr->rx_jmb[i].std;
8382 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8383 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8385 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8386 (i << RXD_OPAQUE_INDEX_SHIFT));
8389 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8390 unsigned int frag_size;
8392 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8394 netdev_warn(tp->dev,
8395 "Using a smaller RX jumbo ring. Only %d "
8396 "out of %d buffers were allocated "
8397 "successfully\n", i, tp->rx_jumbo_pending);
8400 tp->rx_jumbo_pending = i;
8409 tg3_rx_prodring_free(tp, tpr);
8413 static void tg3_rx_prodring_fini(struct tg3 *tp,
8414 struct tg3_rx_prodring_set *tpr)
8416 kfree(tpr->rx_std_buffers);
8417 tpr->rx_std_buffers = NULL;
8418 kfree(tpr->rx_jmb_buffers);
8419 tpr->rx_jmb_buffers = NULL;
8421 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8422 tpr->rx_std, tpr->rx_std_mapping);
8426 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8427 tpr->rx_jmb, tpr->rx_jmb_mapping);
8432 static int tg3_rx_prodring_init(struct tg3 *tp,
8433 struct tg3_rx_prodring_set *tpr)
8435 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8437 if (!tpr->rx_std_buffers)
8440 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8441 TG3_RX_STD_RING_BYTES(tp),
8442 &tpr->rx_std_mapping,
8447 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8448 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8450 if (!tpr->rx_jmb_buffers)
8453 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8454 TG3_RX_JMB_RING_BYTES(tp),
8455 &tpr->rx_jmb_mapping,
8464 tg3_rx_prodring_fini(tp, tpr);
8468 /* Free up pending packets in all rx/tx rings.
8470 * The chip has been shut down and the driver detached from
8471 * the networking, so no interrupts or new tx packets will
8472 * end up in the driver. tp->{tx,}lock is not held and we are not
8473 * in an interrupt context and thus may sleep.
8475 static void tg3_free_rings(struct tg3 *tp)
8479 for (j = 0; j < tp->irq_cnt; j++) {
8480 struct tg3_napi *tnapi = &tp->napi[j];
8482 tg3_rx_prodring_free(tp, &tnapi->prodring);
8484 if (!tnapi->tx_buffers)
8487 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8488 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
8493 tg3_tx_skb_unmap(tnapi, i,
8494 skb_shinfo(skb)->nr_frags - 1);
8496 dev_kfree_skb_any(skb);
8498 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8502 /* Initialize tx/rx rings for packet processing.
8504 * The chip has been shut down and the driver detached from
8505 * the networking, so no interrupts or new tx packets will
8506 * end up in the driver. tp->{tx,}lock are held and thus
8509 static int tg3_init_rings(struct tg3 *tp)
8513 /* Free up all the SKBs. */
8516 for (i = 0; i < tp->irq_cnt; i++) {
8517 struct tg3_napi *tnapi = &tp->napi[i];
8519 tnapi->last_tag = 0;
8520 tnapi->last_irq_tag = 0;
8521 tnapi->hw_status->status = 0;
8522 tnapi->hw_status->status_tag = 0;
8523 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8528 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
8530 tnapi->rx_rcb_ptr = 0;
8532 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8534 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8543 static void tg3_mem_tx_release(struct tg3 *tp)
8547 for (i = 0; i < tp->irq_max; i++) {
8548 struct tg3_napi *tnapi = &tp->napi[i];
8550 if (tnapi->tx_ring) {
8551 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8552 tnapi->tx_ring, tnapi->tx_desc_mapping);
8553 tnapi->tx_ring = NULL;
8556 kfree(tnapi->tx_buffers);
8557 tnapi->tx_buffers = NULL;
8561 static int tg3_mem_tx_acquire(struct tg3 *tp)
8564 struct tg3_napi *tnapi = &tp->napi[0];
8566 /* If multivector TSS is enabled, vector 0 does not handle
8567 * tx interrupts. Don't allocate any resources for it.
8569 if (tg3_flag(tp, ENABLE_TSS))
8572 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8573 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8574 TG3_TX_RING_SIZE, GFP_KERNEL);
8575 if (!tnapi->tx_buffers)
8578 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8580 &tnapi->tx_desc_mapping,
8582 if (!tnapi->tx_ring)
8589 tg3_mem_tx_release(tp);
8593 static void tg3_mem_rx_release(struct tg3 *tp)
8597 for (i = 0; i < tp->irq_max; i++) {
8598 struct tg3_napi *tnapi = &tp->napi[i];
8600 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8605 dma_free_coherent(&tp->pdev->dev,
8606 TG3_RX_RCB_RING_BYTES(tp),
8608 tnapi->rx_rcb_mapping);
8609 tnapi->rx_rcb = NULL;
8613 static int tg3_mem_rx_acquire(struct tg3 *tp)
8615 unsigned int i, limit;
8617 limit = tp->rxq_cnt;
8619 /* If RSS is enabled, we need a (dummy) producer ring
8620 * set on vector zero. This is the true hw prodring.
8622 if (tg3_flag(tp, ENABLE_RSS))
8625 for (i = 0; i < limit; i++) {
8626 struct tg3_napi *tnapi = &tp->napi[i];
8628 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8631 /* If multivector RSS is enabled, vector 0
8632 * does not handle rx or tx interrupts.
8633 * Don't allocate any resources for it.
8635 if (!i && tg3_flag(tp, ENABLE_RSS))
8638 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8639 TG3_RX_RCB_RING_BYTES(tp),
8640 &tnapi->rx_rcb_mapping,
8649 tg3_mem_rx_release(tp);
8654 * Must not be invoked with interrupt sources disabled and
8655 * the hardware shutdown down.
8657 static void tg3_free_consistent(struct tg3 *tp)
8661 for (i = 0; i < tp->irq_cnt; i++) {
8662 struct tg3_napi *tnapi = &tp->napi[i];
8664 if (tnapi->hw_status) {
8665 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8667 tnapi->status_mapping);
8668 tnapi->hw_status = NULL;
8672 tg3_mem_rx_release(tp);
8673 tg3_mem_tx_release(tp);
8676 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8677 tp->hw_stats, tp->stats_mapping);
8678 tp->hw_stats = NULL;
8683 * Must not be invoked with interrupt sources disabled and
8684 * the hardware shutdown down. Can sleep.
8686 static int tg3_alloc_consistent(struct tg3 *tp)
8690 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8691 sizeof(struct tg3_hw_stats),
8692 &tp->stats_mapping, GFP_KERNEL);
8696 for (i = 0; i < tp->irq_cnt; i++) {
8697 struct tg3_napi *tnapi = &tp->napi[i];
8698 struct tg3_hw_status *sblk;
8700 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8702 &tnapi->status_mapping,
8704 if (!tnapi->hw_status)
8707 sblk = tnapi->hw_status;
8709 if (tg3_flag(tp, ENABLE_RSS)) {
8710 u16 *prodptr = NULL;
8713 * When RSS is enabled, the status block format changes
8714 * slightly. The "rx_jumbo_consumer", "reserved",
8715 * and "rx_mini_consumer" members get mapped to the
8716 * other three rx return ring producer indexes.
8720 prodptr = &sblk->idx[0].rx_producer;
8723 prodptr = &sblk->rx_jumbo_consumer;
8726 prodptr = &sblk->reserved;
8729 prodptr = &sblk->rx_mini_consumer;
8732 tnapi->rx_rcb_prod_idx = prodptr;
8734 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8738 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8744 tg3_free_consistent(tp);
8748 #define MAX_WAIT_CNT 1000
8750 /* To stop a block, clear the enable bit and poll till it
8751 * clears. tp->lock is held.
8753 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
8758 if (tg3_flag(tp, 5705_PLUS)) {
8765 /* We can't enable/disable these bits of the
8766 * 5705/5750, just say success.
8779 for (i = 0; i < MAX_WAIT_CNT; i++) {
8780 if (pci_channel_offline(tp->pdev)) {
8781 dev_err(&tp->pdev->dev,
8782 "tg3_stop_block device offline, "
8783 "ofs=%lx enable_bit=%x\n",
8790 if ((val & enable_bit) == 0)
8794 if (i == MAX_WAIT_CNT && !silent) {
8795 dev_err(&tp->pdev->dev,
8796 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8804 /* tp->lock is held. */
8805 static int tg3_abort_hw(struct tg3 *tp, bool silent)
8809 tg3_disable_ints(tp);
8811 if (pci_channel_offline(tp->pdev)) {
8812 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8813 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8818 tp->rx_mode &= ~RX_MODE_ENABLE;
8819 tw32_f(MAC_RX_MODE, tp->rx_mode);
8822 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8823 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8824 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8825 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8826 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8827 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8829 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8830 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8831 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8832 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8833 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8834 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8835 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8837 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8838 tw32_f(MAC_MODE, tp->mac_mode);
8841 tp->tx_mode &= ~TX_MODE_ENABLE;
8842 tw32_f(MAC_TX_MODE, tp->tx_mode);
8844 for (i = 0; i < MAX_WAIT_CNT; i++) {
8846 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8849 if (i >= MAX_WAIT_CNT) {
8850 dev_err(&tp->pdev->dev,
8851 "%s timed out, TX_MODE_ENABLE will not clear "
8852 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
8856 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8857 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8858 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8860 tw32(FTQ_RESET, 0xffffffff);
8861 tw32(FTQ_RESET, 0x00000000);
8863 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8864 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8867 for (i = 0; i < tp->irq_cnt; i++) {
8868 struct tg3_napi *tnapi = &tp->napi[i];
8869 if (tnapi->hw_status)
8870 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8876 /* Save PCI command register before chip reset */
8877 static void tg3_save_pci_state(struct tg3 *tp)
8879 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8882 /* Restore PCI state after chip reset */
8883 static void tg3_restore_pci_state(struct tg3 *tp)
8887 /* Re-enable indirect register accesses. */
8888 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8889 tp->misc_host_ctrl);
8891 /* Set MAX PCI retry to zero. */
8892 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8893 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8894 tg3_flag(tp, PCIX_MODE))
8895 val |= PCISTATE_RETRY_SAME_DMA;
8896 /* Allow reads and writes to the APE register and memory space. */
8897 if (tg3_flag(tp, ENABLE_APE))
8898 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8899 PCISTATE_ALLOW_APE_SHMEM_WR |
8900 PCISTATE_ALLOW_APE_PSPACE_WR;
8901 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8903 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8905 if (!tg3_flag(tp, PCI_EXPRESS)) {
8906 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8907 tp->pci_cacheline_sz);
8908 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8912 /* Make sure PCI-X relaxed ordering bit is clear. */
8913 if (tg3_flag(tp, PCIX_MODE)) {
8916 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8918 pcix_cmd &= ~PCI_X_CMD_ERO;
8919 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8923 if (tg3_flag(tp, 5780_CLASS)) {
8925 /* Chip reset on 5780 will reset MSI enable bit,
8926 * so need to restore it.
8928 if (tg3_flag(tp, USING_MSI)) {
8931 pci_read_config_word(tp->pdev,
8932 tp->msi_cap + PCI_MSI_FLAGS,
8934 pci_write_config_word(tp->pdev,
8935 tp->msi_cap + PCI_MSI_FLAGS,
8936 ctrl | PCI_MSI_FLAGS_ENABLE);
8937 val = tr32(MSGINT_MODE);
8938 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8943 static void tg3_override_clk(struct tg3 *tp)
8947 switch (tg3_asic_rev(tp)) {
8949 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8950 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
8951 TG3_CPMU_MAC_ORIDE_ENABLE);
8956 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8964 static void tg3_restore_clk(struct tg3 *tp)
8968 switch (tg3_asic_rev(tp)) {
8970 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8971 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
8972 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
8977 val = tr32(TG3_CPMU_CLCK_ORIDE);
8978 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8986 /* tp->lock is held. */
8987 static int tg3_chip_reset(struct tg3 *tp)
8990 void (*write_op)(struct tg3 *, u32, u32);
8993 if (!pci_device_is_present(tp->pdev))
8998 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9000 /* No matching tg3_nvram_unlock() after this because
9001 * chip reset below will undo the nvram lock.
9003 tp->nvram_lock_cnt = 0;
9005 /* GRC_MISC_CFG core clock reset will clear the memory
9006 * enable bit in PCI register 4 and the MSI enable bit
9007 * on some chips, so we save relevant registers here.
9009 tg3_save_pci_state(tp);
9011 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
9012 tg3_flag(tp, 5755_PLUS))
9013 tw32(GRC_FASTBOOT_PC, 0);
9016 * We must avoid the readl() that normally takes place.
9017 * It locks machines, causes machine checks, and other
9018 * fun things. So, temporarily disable the 5701
9019 * hardware workaround, while we do the reset.
9021 write_op = tp->write32;
9022 if (write_op == tg3_write_flush_reg32)
9023 tp->write32 = tg3_write32;
9025 /* Prevent the irq handler from reading or writing PCI registers
9026 * during chip reset when the memory enable bit in the PCI command
9027 * register may be cleared. The chip does not generate interrupt
9028 * at this time, but the irq handler may still be called due to irq
9029 * sharing or irqpoll.
9031 tg3_flag_set(tp, CHIP_RESETTING);
9032 for (i = 0; i < tp->irq_cnt; i++) {
9033 struct tg3_napi *tnapi = &tp->napi[i];
9034 if (tnapi->hw_status) {
9035 tnapi->hw_status->status = 0;
9036 tnapi->hw_status->status_tag = 0;
9038 tnapi->last_tag = 0;
9039 tnapi->last_irq_tag = 0;
9043 for (i = 0; i < tp->irq_cnt; i++)
9044 synchronize_irq(tp->napi[i].irq_vec);
9046 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9047 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9048 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9052 val = GRC_MISC_CFG_CORECLK_RESET;
9054 if (tg3_flag(tp, PCI_EXPRESS)) {
9055 /* Force PCIe 1.0a mode */
9056 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
9057 !tg3_flag(tp, 57765_PLUS) &&
9058 tr32(TG3_PCIE_PHY_TSTCTL) ==
9059 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9060 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9062 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
9063 tw32(GRC_MISC_CFG, (1 << 29));
9068 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9069 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9070 tw32(GRC_VCPU_EXT_CTRL,
9071 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9074 /* Set the clock to the highest frequency to avoid timeouts. With link
9075 * aware mode, the clock speed could be slow and bootcode does not
9076 * complete within the expected time. Override the clock to allow the
9077 * bootcode to finish sooner and then restore it.
9079 tg3_override_clk(tp);
9081 /* Manage gphy power for all CPMU absent PCIe devices. */
9082 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
9083 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
9085 tw32(GRC_MISC_CFG, val);
9087 /* restore 5701 hardware bug workaround write method */
9088 tp->write32 = write_op;
9090 /* Unfortunately, we have to delay before the PCI read back.
9091 * Some 575X chips even will not respond to a PCI cfg access
9092 * when the reset command is given to the chip.
9094 * How do these hardware designers expect things to work
9095 * properly if the PCI write is posted for a long period
9096 * of time? It is always necessary to have some method by
9097 * which a register read back can occur to push the write
9098 * out which does the reset.
9100 * For most tg3 variants the trick below was working.
9105 /* Flush PCI posted writes. The normal MMIO registers
9106 * are inaccessible at this time so this is the only
9107 * way to make this reliably (actually, this is no longer
9108 * the case, see above). I tried to use indirect
9109 * register read/write but this upset some 5701 variants.
9111 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9115 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
9118 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
9122 /* Wait for link training to complete. */
9123 for (j = 0; j < 5000; j++)
9126 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9127 pci_write_config_dword(tp->pdev, 0xc4,
9128 cfg_val | (1 << 15));
9131 /* Clear the "no snoop" and "relaxed ordering" bits. */
9132 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
9134 * Older PCIe devices only support the 128 byte
9135 * MPS setting. Enforce the restriction.
9137 if (!tg3_flag(tp, CPMU_PRESENT))
9138 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9139 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
9141 /* Clear error status */
9142 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
9143 PCI_EXP_DEVSTA_CED |
9144 PCI_EXP_DEVSTA_NFED |
9145 PCI_EXP_DEVSTA_FED |
9146 PCI_EXP_DEVSTA_URD);
9149 tg3_restore_pci_state(tp);
9151 tg3_flag_clear(tp, CHIP_RESETTING);
9152 tg3_flag_clear(tp, ERROR_PROCESSED);
9155 if (tg3_flag(tp, 5780_CLASS))
9156 val = tr32(MEMARB_MODE);
9157 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9159 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
9161 tw32(0x5000, 0x400);
9164 if (tg3_flag(tp, IS_SSB_CORE)) {
9166 * BCM4785: In order to avoid repercussions from using
9167 * potentially defective internal ROM, stop the Rx RISC CPU,
9168 * which is not required.
9171 tg3_halt_cpu(tp, RX_CPU_BASE);
9174 err = tg3_poll_fw(tp);
9178 tw32(GRC_MODE, tp->grc_mode);
9180 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
9183 tw32(0xc4, val | (1 << 15));
9186 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
9187 tg3_asic_rev(tp) == ASIC_REV_5705) {
9188 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
9189 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
9190 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9191 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9194 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9195 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
9197 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9198 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
9203 tw32_f(MAC_MODE, val);
9206 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9210 if (tg3_flag(tp, PCI_EXPRESS) &&
9211 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9212 tg3_asic_rev(tp) != ASIC_REV_5785 &&
9213 !tg3_flag(tp, 57765_PLUS)) {
9216 tw32(0x7c00, val | (1 << 25));
9219 tg3_restore_clk(tp);
9221 /* Reprobe ASF enable state. */
9222 tg3_flag_clear(tp, ENABLE_ASF);
9223 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9224 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9226 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
9227 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9228 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9231 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9232 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9233 tg3_flag_set(tp, ENABLE_ASF);
9234 tp->last_event_jiffies = jiffies;
9235 if (tg3_flag(tp, 5750_PLUS))
9236 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
9238 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9239 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9240 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9241 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9242 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
9249 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9250 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
9251 static void __tg3_set_rx_mode(struct net_device *);
9253 /* tp->lock is held. */
9254 static int tg3_halt(struct tg3 *tp, int kind, bool silent)
9260 tg3_write_sig_pre_reset(tp, kind);
9262 tg3_abort_hw(tp, silent);
9263 err = tg3_chip_reset(tp);
9265 __tg3_set_mac_addr(tp, false);
9267 tg3_write_sig_legacy(tp, kind);
9268 tg3_write_sig_post_reset(tp, kind);
9271 /* Save the stats across chip resets... */
9272 tg3_get_nstats(tp, &tp->net_stats_prev);
9273 tg3_get_estats(tp, &tp->estats_prev);
9275 /* And make sure the next sample is new data */
9276 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9282 static int tg3_set_mac_addr(struct net_device *dev, void *p)
9284 struct tg3 *tp = netdev_priv(dev);
9285 struct sockaddr *addr = p;
9287 bool skip_mac_1 = false;
9289 if (!is_valid_ether_addr(addr->sa_data))
9290 return -EADDRNOTAVAIL;
9292 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9294 if (!netif_running(dev))
9297 if (tg3_flag(tp, ENABLE_ASF)) {
9298 u32 addr0_high, addr0_low, addr1_high, addr1_low;
9300 addr0_high = tr32(MAC_ADDR_0_HIGH);
9301 addr0_low = tr32(MAC_ADDR_0_LOW);
9302 addr1_high = tr32(MAC_ADDR_1_HIGH);
9303 addr1_low = tr32(MAC_ADDR_1_LOW);
9305 /* Skip MAC addr 1 if ASF is using it. */
9306 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9307 !(addr1_high == 0 && addr1_low == 0))
9310 spin_lock_bh(&tp->lock);
9311 __tg3_set_mac_addr(tp, skip_mac_1);
9312 __tg3_set_rx_mode(dev);
9313 spin_unlock_bh(&tp->lock);
9318 /* tp->lock is held. */
9319 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9320 dma_addr_t mapping, u32 maxlen_flags,
9324 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9325 ((u64) mapping >> 32));
9327 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9328 ((u64) mapping & 0xffffffff));
9330 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9333 if (!tg3_flag(tp, 5705_PLUS))
9335 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9340 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9344 if (!tg3_flag(tp, ENABLE_TSS)) {
9345 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9346 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9347 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9349 tw32(HOSTCC_TXCOL_TICKS, 0);
9350 tw32(HOSTCC_TXMAX_FRAMES, 0);
9351 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9353 for (; i < tp->txq_cnt; i++) {
9356 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9357 tw32(reg, ec->tx_coalesce_usecs);
9358 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9359 tw32(reg, ec->tx_max_coalesced_frames);
9360 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9361 tw32(reg, ec->tx_max_coalesced_frames_irq);
9365 for (; i < tp->irq_max - 1; i++) {
9366 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9367 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9368 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9372 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9375 u32 limit = tp->rxq_cnt;
9377 if (!tg3_flag(tp, ENABLE_RSS)) {
9378 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9379 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9380 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9383 tw32(HOSTCC_RXCOL_TICKS, 0);
9384 tw32(HOSTCC_RXMAX_FRAMES, 0);
9385 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9388 for (; i < limit; i++) {
9391 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9392 tw32(reg, ec->rx_coalesce_usecs);
9393 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9394 tw32(reg, ec->rx_max_coalesced_frames);
9395 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9396 tw32(reg, ec->rx_max_coalesced_frames_irq);
9399 for (; i < tp->irq_max - 1; i++) {
9400 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9401 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9402 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9406 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9408 tg3_coal_tx_init(tp, ec);
9409 tg3_coal_rx_init(tp, ec);
9411 if (!tg3_flag(tp, 5705_PLUS)) {
9412 u32 val = ec->stats_block_coalesce_usecs;
9414 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9415 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9420 tw32(HOSTCC_STAT_COAL_TICKS, val);
9424 /* tp->lock is held. */
9425 static void tg3_tx_rcbs_disable(struct tg3 *tp)
9429 /* Disable all transmit rings but the first. */
9430 if (!tg3_flag(tp, 5705_PLUS))
9431 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9432 else if (tg3_flag(tp, 5717_PLUS))
9433 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9434 else if (tg3_flag(tp, 57765_CLASS) ||
9435 tg3_asic_rev(tp) == ASIC_REV_5762)
9436 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9438 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9440 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9441 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9442 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9443 BDINFO_FLAGS_DISABLED);
9446 /* tp->lock is held. */
9447 static void tg3_tx_rcbs_init(struct tg3 *tp)
9450 u32 txrcb = NIC_SRAM_SEND_RCB;
9452 if (tg3_flag(tp, ENABLE_TSS))
9455 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9456 struct tg3_napi *tnapi = &tp->napi[i];
9458 if (!tnapi->tx_ring)
9461 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9462 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9463 NIC_SRAM_TX_BUFFER_DESC);
9467 /* tp->lock is held. */
9468 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9472 /* Disable all receive return rings but the first. */
9473 if (tg3_flag(tp, 5717_PLUS))
9474 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9475 else if (!tg3_flag(tp, 5705_PLUS))
9476 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9477 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9478 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9479 tg3_flag(tp, 57765_CLASS))
9480 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9482 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9484 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9485 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9486 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9487 BDINFO_FLAGS_DISABLED);
9490 /* tp->lock is held. */
9491 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9494 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9496 if (tg3_flag(tp, ENABLE_RSS))
9499 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9500 struct tg3_napi *tnapi = &tp->napi[i];
9505 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9506 (tp->rx_ret_ring_mask + 1) <<
9507 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9511 /* tp->lock is held. */
9512 static void tg3_rings_reset(struct tg3 *tp)
9516 struct tg3_napi *tnapi = &tp->napi[0];
9518 tg3_tx_rcbs_disable(tp);
9520 tg3_rx_ret_rcbs_disable(tp);
9522 /* Disable interrupts */
9523 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9524 tp->napi[0].chk_msi_cnt = 0;
9525 tp->napi[0].last_rx_cons = 0;
9526 tp->napi[0].last_tx_cons = 0;
9528 /* Zero mailbox registers. */
9529 if (tg3_flag(tp, SUPPORT_MSIX)) {
9530 for (i = 1; i < tp->irq_max; i++) {
9531 tp->napi[i].tx_prod = 0;
9532 tp->napi[i].tx_cons = 0;
9533 if (tg3_flag(tp, ENABLE_TSS))
9534 tw32_mailbox(tp->napi[i].prodmbox, 0);
9535 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9536 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9537 tp->napi[i].chk_msi_cnt = 0;
9538 tp->napi[i].last_rx_cons = 0;
9539 tp->napi[i].last_tx_cons = 0;
9541 if (!tg3_flag(tp, ENABLE_TSS))
9542 tw32_mailbox(tp->napi[0].prodmbox, 0);
9544 tp->napi[0].tx_prod = 0;
9545 tp->napi[0].tx_cons = 0;
9546 tw32_mailbox(tp->napi[0].prodmbox, 0);
9547 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9550 /* Make sure the NIC-based send BD rings are disabled. */
9551 if (!tg3_flag(tp, 5705_PLUS)) {
9552 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9553 for (i = 0; i < 16; i++)
9554 tw32_tx_mbox(mbox + i * 8, 0);
9557 /* Clear status block in ram. */
9558 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9560 /* Set status block DMA address */
9561 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9562 ((u64) tnapi->status_mapping >> 32));
9563 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9564 ((u64) tnapi->status_mapping & 0xffffffff));
9566 stblk = HOSTCC_STATBLCK_RING1;
9568 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9569 u64 mapping = (u64)tnapi->status_mapping;
9570 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9571 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9574 /* Clear status block in ram. */
9575 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9578 tg3_tx_rcbs_init(tp);
9579 tg3_rx_ret_rcbs_init(tp);
9582 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9584 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9586 if (!tg3_flag(tp, 5750_PLUS) ||
9587 tg3_flag(tp, 5780_CLASS) ||
9588 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9589 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9590 tg3_flag(tp, 57765_PLUS))
9591 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
9592 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9593 tg3_asic_rev(tp) == ASIC_REV_5787)
9594 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9596 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9598 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9599 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9601 val = min(nic_rep_thresh, host_rep_thresh);
9602 tw32(RCVBDI_STD_THRESH, val);
9604 if (tg3_flag(tp, 57765_PLUS))
9605 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9607 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9610 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
9612 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9614 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9615 tw32(RCVBDI_JUMBO_THRESH, val);
9617 if (tg3_flag(tp, 57765_PLUS))
9618 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9621 static inline u32 calc_crc(unsigned char *buf, int len)
9629 for (j = 0; j < len; j++) {
9632 for (k = 0; k < 8; k++) {
9645 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9647 /* accept or reject all multicast frames */
9648 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9649 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9650 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9651 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9654 static void __tg3_set_rx_mode(struct net_device *dev)
9656 struct tg3 *tp = netdev_priv(dev);
9659 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9660 RX_MODE_KEEP_VLAN_TAG);
9662 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9663 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9666 if (!tg3_flag(tp, ENABLE_ASF))
9667 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9670 if (dev->flags & IFF_PROMISC) {
9671 /* Promiscuous mode. */
9672 rx_mode |= RX_MODE_PROMISC;
9673 } else if (dev->flags & IFF_ALLMULTI) {
9674 /* Accept all multicast. */
9675 tg3_set_multi(tp, 1);
9676 } else if (netdev_mc_empty(dev)) {
9677 /* Reject all multicast. */
9678 tg3_set_multi(tp, 0);
9680 /* Accept one or more multicast(s). */
9681 struct netdev_hw_addr *ha;
9682 u32 mc_filter[4] = { 0, };
9687 netdev_for_each_mc_addr(ha, dev) {
9688 crc = calc_crc(ha->addr, ETH_ALEN);
9690 regidx = (bit & 0x60) >> 5;
9692 mc_filter[regidx] |= (1 << bit);
9695 tw32(MAC_HASH_REG_0, mc_filter[0]);
9696 tw32(MAC_HASH_REG_1, mc_filter[1]);
9697 tw32(MAC_HASH_REG_2, mc_filter[2]);
9698 tw32(MAC_HASH_REG_3, mc_filter[3]);
9701 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9702 rx_mode |= RX_MODE_PROMISC;
9703 } else if (!(dev->flags & IFF_PROMISC)) {
9704 /* Add all entries into to the mac addr filter list */
9706 struct netdev_hw_addr *ha;
9708 netdev_for_each_uc_addr(ha, dev) {
9709 __tg3_set_one_mac_addr(tp, ha->addr,
9710 i + TG3_UCAST_ADDR_IDX(tp));
9715 if (rx_mode != tp->rx_mode) {
9716 tp->rx_mode = rx_mode;
9717 tw32_f(MAC_RX_MODE, rx_mode);
9722 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9726 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9727 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9730 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9734 if (!tg3_flag(tp, SUPPORT_MSIX))
9737 if (tp->rxq_cnt == 1) {
9738 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9742 /* Validate table against current IRQ count */
9743 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
9744 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9748 if (i != TG3_RSS_INDIR_TBL_SIZE)
9749 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9752 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9755 u32 reg = MAC_RSS_INDIR_TBL_0;
9757 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9758 u32 val = tp->rss_ind_tbl[i];
9760 for (; i % 8; i++) {
9762 val |= tp->rss_ind_tbl[i];
9769 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9771 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9772 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9774 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9777 /* tp->lock is held. */
9778 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
9780 u32 val, rdmac_mode;
9782 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9784 tg3_disable_ints(tp);
9788 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9790 if (tg3_flag(tp, INIT_COMPLETE))
9791 tg3_abort_hw(tp, 1);
9793 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9794 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9795 tg3_phy_pull_config(tp);
9796 tg3_eee_pull_config(tp, NULL);
9797 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9800 /* Enable MAC control of LPI */
9801 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9807 err = tg3_chip_reset(tp);
9811 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9813 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9814 val = tr32(TG3_CPMU_CTRL);
9815 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9816 tw32(TG3_CPMU_CTRL, val);
9818 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9819 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9820 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9821 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9823 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9824 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9825 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9826 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9828 val = tr32(TG3_CPMU_HST_ACC);
9829 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9830 val |= CPMU_HST_ACC_MACCLK_6_25;
9831 tw32(TG3_CPMU_HST_ACC, val);
9834 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9835 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9836 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9837 PCIE_PWR_MGMT_L1_THRESH_4MS;
9838 tw32(PCIE_PWR_MGMT_THRESH, val);
9840 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9841 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9843 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9845 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9846 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9849 if (tg3_flag(tp, L1PLLPD_EN)) {
9850 u32 grc_mode = tr32(GRC_MODE);
9852 /* Access the lower 1K of PL PCIE block registers. */
9853 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9854 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9856 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9857 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9858 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9860 tw32(GRC_MODE, grc_mode);
9863 if (tg3_flag(tp, 57765_CLASS)) {
9864 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9865 u32 grc_mode = tr32(GRC_MODE);
9867 /* Access the lower 1K of PL PCIE block registers. */
9868 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9869 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9871 val = tr32(TG3_PCIE_TLDLPL_PORT +
9872 TG3_PCIE_PL_LO_PHYCTL5);
9873 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9874 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
9876 tw32(GRC_MODE, grc_mode);
9879 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
9882 /* Fix transmit hangs */
9883 val = tr32(TG3_CPMU_PADRNG_CTL);
9884 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9885 tw32(TG3_CPMU_PADRNG_CTL, val);
9887 grc_mode = tr32(GRC_MODE);
9889 /* Access the lower 1K of DL PCIE block registers. */
9890 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9891 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9893 val = tr32(TG3_PCIE_TLDLPL_PORT +
9894 TG3_PCIE_DL_LO_FTSMAX);
9895 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9896 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9897 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9899 tw32(GRC_MODE, grc_mode);
9902 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9903 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9904 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9905 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9908 /* This works around an issue with Athlon chipsets on
9909 * B3 tigon3 silicon. This bit has no effect on any
9910 * other revision. But do not set this on PCI Express
9911 * chips and don't even touch the clocks if the CPMU is present.
9913 if (!tg3_flag(tp, CPMU_PRESENT)) {
9914 if (!tg3_flag(tp, PCI_EXPRESS))
9915 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9916 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9919 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
9920 tg3_flag(tp, PCIX_MODE)) {
9921 val = tr32(TG3PCI_PCISTATE);
9922 val |= PCISTATE_RETRY_SAME_DMA;
9923 tw32(TG3PCI_PCISTATE, val);
9926 if (tg3_flag(tp, ENABLE_APE)) {
9927 /* Allow reads and writes to the
9928 * APE register and memory space.
9930 val = tr32(TG3PCI_PCISTATE);
9931 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
9932 PCISTATE_ALLOW_APE_SHMEM_WR |
9933 PCISTATE_ALLOW_APE_PSPACE_WR;
9934 tw32(TG3PCI_PCISTATE, val);
9937 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
9938 /* Enable some hw fixes. */
9939 val = tr32(TG3PCI_MSI_DATA);
9940 val |= (1 << 26) | (1 << 28) | (1 << 29);
9941 tw32(TG3PCI_MSI_DATA, val);
9944 /* Descriptor ring init may make accesses to the
9945 * NIC SRAM area to setup the TX descriptors, so we
9946 * can only do this after the hardware has been
9947 * successfully reset.
9949 err = tg3_init_rings(tp);
9953 if (tg3_flag(tp, 57765_PLUS)) {
9954 val = tr32(TG3PCI_DMA_RW_CTRL) &
9955 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
9956 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
9957 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
9958 if (!tg3_flag(tp, 57765_CLASS) &&
9959 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9960 tg3_asic_rev(tp) != ASIC_REV_5762)
9961 val |= DMA_RWCTRL_TAGGED_STAT_WA;
9962 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
9963 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9964 tg3_asic_rev(tp) != ASIC_REV_5761) {
9965 /* This value is determined during the probe time DMA
9966 * engine test, tg3_test_dma.
9968 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9971 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9972 GRC_MODE_4X_NIC_SEND_RINGS |
9973 GRC_MODE_NO_TX_PHDR_CSUM |
9974 GRC_MODE_NO_RX_PHDR_CSUM);
9975 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
9977 /* Pseudo-header checksum is done by hardware logic and not
9978 * the offload processers, so make the chip do the pseudo-
9979 * header checksums on receive. For transmit it is more
9980 * convenient to do the pseudo-header checksum in software
9981 * as Linux does that on transmit for us in all cases.
9983 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
9985 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
9987 tw32(TG3_RX_PTP_CTL,
9988 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
9990 if (tg3_flag(tp, PTP_CAPABLE))
9991 val |= GRC_MODE_TIME_SYNC_ENABLE;
9993 tw32(GRC_MODE, tp->grc_mode | val);
9995 /* Setup the timer prescalar register. Clock is always 66Mhz. */
9996 val = tr32(GRC_MISC_CFG);
9998 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
9999 tw32(GRC_MISC_CFG, val);
10001 /* Initialize MBUF/DESC pool. */
10002 if (tg3_flag(tp, 5750_PLUS)) {
10004 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
10005 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
10006 if (tg3_asic_rev(tp) == ASIC_REV_5704)
10007 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10009 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10010 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10011 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
10012 } else if (tg3_flag(tp, TSO_CAPABLE)) {
10015 fw_len = tp->fw_len;
10016 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10017 tw32(BUFMGR_MB_POOL_ADDR,
10018 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10019 tw32(BUFMGR_MB_POOL_SIZE,
10020 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10023 if (tp->dev->mtu <= ETH_DATA_LEN) {
10024 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10025 tp->bufmgr_config.mbuf_read_dma_low_water);
10026 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10027 tp->bufmgr_config.mbuf_mac_rx_low_water);
10028 tw32(BUFMGR_MB_HIGH_WATER,
10029 tp->bufmgr_config.mbuf_high_water);
10031 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10032 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10033 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10034 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10035 tw32(BUFMGR_MB_HIGH_WATER,
10036 tp->bufmgr_config.mbuf_high_water_jumbo);
10038 tw32(BUFMGR_DMA_LOW_WATER,
10039 tp->bufmgr_config.dma_low_water);
10040 tw32(BUFMGR_DMA_HIGH_WATER,
10041 tp->bufmgr_config.dma_high_water);
10043 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
10044 if (tg3_asic_rev(tp) == ASIC_REV_5719)
10045 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
10046 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10047 tg3_asic_rev(tp) == ASIC_REV_5762 ||
10048 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10049 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
10050 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
10051 tw32(BUFMGR_MODE, val);
10052 for (i = 0; i < 2000; i++) {
10053 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10058 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
10062 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
10063 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10065 tg3_setup_rxbd_thresholds(tp);
10067 /* Initialize TG3_BDINFO's at:
10068 * RCVDBDI_STD_BD: standard eth size rx ring
10069 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10070 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10073 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10074 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10075 * ring attribute flags
10076 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10078 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10079 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10081 * The size of each ring is fixed in the firmware, but the location is
10084 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10085 ((u64) tpr->rx_std_mapping >> 32));
10086 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10087 ((u64) tpr->rx_std_mapping & 0xffffffff));
10088 if (!tg3_flag(tp, 5717_PLUS))
10089 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10090 NIC_SRAM_RX_BUFFER_DESC);
10092 /* Disable the mini ring */
10093 if (!tg3_flag(tp, 5705_PLUS))
10094 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10095 BDINFO_FLAGS_DISABLED);
10097 /* Program the jumbo buffer descriptor ring control
10098 * blocks on those devices that have them.
10100 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10101 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
10103 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
10104 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10105 ((u64) tpr->rx_jmb_mapping >> 32));
10106 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10107 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
10108 val = TG3_RX_JMB_RING_SIZE(tp) <<
10109 BDINFO_FLAGS_MAXLEN_SHIFT;
10110 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10111 val | BDINFO_FLAGS_USE_EXT_RECV);
10112 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
10113 tg3_flag(tp, 57765_CLASS) ||
10114 tg3_asic_rev(tp) == ASIC_REV_5762)
10115 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10116 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
10118 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10119 BDINFO_FLAGS_DISABLED);
10122 if (tg3_flag(tp, 57765_PLUS)) {
10123 val = TG3_RX_STD_RING_SIZE(tp);
10124 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10125 val |= (TG3_RX_STD_DMA_SZ << 2);
10127 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
10129 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
10131 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10133 tpr->rx_std_prod_idx = tp->rx_pending;
10134 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
10136 tpr->rx_jmb_prod_idx =
10137 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
10138 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
10140 tg3_rings_reset(tp);
10142 /* Initialize MAC address and backoff seed. */
10143 __tg3_set_mac_addr(tp, false);
10145 /* MTU + ethernet header + FCS + optional VLAN tag */
10146 tw32(MAC_RX_MTU_SIZE,
10147 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
10149 /* The slot time is changed by tg3_setup_phy if we
10150 * run at gigabit with half duplex.
10152 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10153 (6 << TX_LENGTHS_IPG_SHIFT) |
10154 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10156 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10157 tg3_asic_rev(tp) == ASIC_REV_5762)
10158 val |= tr32(MAC_TX_LENGTHS) &
10159 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10160 TX_LENGTHS_CNT_DWN_VAL_MSK);
10162 tw32(MAC_TX_LENGTHS, val);
10164 /* Receive rules. */
10165 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10166 tw32(RCVLPC_CONFIG, 0x0181);
10168 /* Calculate RDMAC_MODE setting early, we need it to determine
10169 * the RCVLPC_STATE_ENABLE mask.
10171 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10172 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10173 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10174 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10175 RDMAC_MODE_LNGREAD_ENAB);
10177 if (tg3_asic_rev(tp) == ASIC_REV_5717)
10178 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10180 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10181 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10182 tg3_asic_rev(tp) == ASIC_REV_57780)
10183 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10184 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10185 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10187 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10188 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10189 if (tg3_flag(tp, TSO_CAPABLE) &&
10190 tg3_asic_rev(tp) == ASIC_REV_5705) {
10191 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10192 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10193 !tg3_flag(tp, IS_5788)) {
10194 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10198 if (tg3_flag(tp, PCI_EXPRESS))
10199 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10201 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10203 if (tp->dev->mtu <= ETH_DATA_LEN) {
10204 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10205 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10209 if (tg3_flag(tp, HW_TSO_1) ||
10210 tg3_flag(tp, HW_TSO_2) ||
10211 tg3_flag(tp, HW_TSO_3))
10212 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10214 if (tg3_flag(tp, 57765_PLUS) ||
10215 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10216 tg3_asic_rev(tp) == ASIC_REV_57780)
10217 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
10219 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10220 tg3_asic_rev(tp) == ASIC_REV_5762)
10221 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10223 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10224 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10225 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10226 tg3_asic_rev(tp) == ASIC_REV_57780 ||
10227 tg3_flag(tp, 57765_PLUS)) {
10230 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10231 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10233 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10235 val = tr32(tgtreg);
10236 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10237 tg3_asic_rev(tp) == ASIC_REV_5762) {
10238 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10239 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10240 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10241 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10242 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10243 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
10245 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10248 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10249 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10250 tg3_asic_rev(tp) == ASIC_REV_5762) {
10253 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10254 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10256 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10258 val = tr32(tgtreg);
10260 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10261 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10264 /* Receive/send statistics. */
10265 if (tg3_flag(tp, 5750_PLUS)) {
10266 val = tr32(RCVLPC_STATS_ENABLE);
10267 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10268 tw32(RCVLPC_STATS_ENABLE, val);
10269 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
10270 tg3_flag(tp, TSO_CAPABLE)) {
10271 val = tr32(RCVLPC_STATS_ENABLE);
10272 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10273 tw32(RCVLPC_STATS_ENABLE, val);
10275 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10277 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10278 tw32(SNDDATAI_STATSENAB, 0xffffff);
10279 tw32(SNDDATAI_STATSCTRL,
10280 (SNDDATAI_SCTRL_ENABLE |
10281 SNDDATAI_SCTRL_FASTUPD));
10283 /* Setup host coalescing engine. */
10284 tw32(HOSTCC_MODE, 0);
10285 for (i = 0; i < 2000; i++) {
10286 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10291 __tg3_set_coalesce(tp, &tp->coal);
10293 if (!tg3_flag(tp, 5705_PLUS)) {
10294 /* Status/statistics block address. See tg3_timer,
10295 * the tg3_periodic_fetch_stats call there, and
10296 * tg3_get_stats to see how this works for 5705/5750 chips.
10298 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10299 ((u64) tp->stats_mapping >> 32));
10300 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10301 ((u64) tp->stats_mapping & 0xffffffff));
10302 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10304 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10306 /* Clear statistics and status block memory areas */
10307 for (i = NIC_SRAM_STATS_BLK;
10308 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10309 i += sizeof(u32)) {
10310 tg3_write_mem(tp, i, 0);
10315 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10317 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10318 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10319 if (!tg3_flag(tp, 5705_PLUS))
10320 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10322 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10323 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10324 /* reset to prevent losing 1st rx packet intermittently */
10325 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10329 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10330 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10331 MAC_MODE_FHDE_ENABLE;
10332 if (tg3_flag(tp, ENABLE_APE))
10333 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10334 if (!tg3_flag(tp, 5705_PLUS) &&
10335 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10336 tg3_asic_rev(tp) != ASIC_REV_5700)
10337 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10338 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10341 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10342 * If TG3_FLAG_IS_NIC is zero, we should read the
10343 * register to preserve the GPIO settings for LOMs. The GPIOs,
10344 * whether used as inputs or outputs, are set by boot code after
10347 if (!tg3_flag(tp, IS_NIC)) {
10350 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10351 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10352 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
10354 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10355 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10356 GRC_LCLCTRL_GPIO_OUTPUT3;
10358 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10359 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10361 tp->grc_local_ctrl &= ~gpio_mask;
10362 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10364 /* GPIO1 must be driven high for eeprom write protect */
10365 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10366 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10367 GRC_LCLCTRL_GPIO_OUTPUT1);
10369 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10372 if (tg3_flag(tp, USING_MSIX)) {
10373 val = tr32(MSGINT_MODE);
10374 val |= MSGINT_MODE_ENABLE;
10375 if (tp->irq_cnt > 1)
10376 val |= MSGINT_MODE_MULTIVEC_EN;
10377 if (!tg3_flag(tp, 1SHOT_MSI))
10378 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
10379 tw32(MSGINT_MODE, val);
10382 if (!tg3_flag(tp, 5705_PLUS)) {
10383 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10387 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10388 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10389 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10390 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10391 WDMAC_MODE_LNGREAD_ENAB);
10393 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10394 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10395 if (tg3_flag(tp, TSO_CAPABLE) &&
10396 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10397 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10399 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10400 !tg3_flag(tp, IS_5788)) {
10401 val |= WDMAC_MODE_RX_ACCEL;
10405 /* Enable host coalescing bug fix */
10406 if (tg3_flag(tp, 5755_PLUS))
10407 val |= WDMAC_MODE_STATUS_TAG_FIX;
10409 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10410 val |= WDMAC_MODE_BURST_ALL_DATA;
10412 tw32_f(WDMAC_MODE, val);
10415 if (tg3_flag(tp, PCIX_MODE)) {
10418 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10420 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10421 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10422 pcix_cmd |= PCI_X_CMD_READ_2K;
10423 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10424 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10425 pcix_cmd |= PCI_X_CMD_READ_2K;
10427 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10431 tw32_f(RDMAC_MODE, rdmac_mode);
10434 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10435 tg3_asic_rev(tp) == ASIC_REV_5720) {
10436 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10437 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10440 if (i < TG3_NUM_RDMA_CHANNELS) {
10441 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10442 val |= tg3_lso_rd_dma_workaround_bit(tp);
10443 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10444 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
10448 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10449 if (!tg3_flag(tp, 5705_PLUS))
10450 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10452 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10453 tw32(SNDDATAC_MODE,
10454 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10456 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10458 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10459 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10460 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
10461 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10462 val |= RCVDBDI_MODE_LRG_RING_SZ;
10463 tw32(RCVDBDI_MODE, val);
10464 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10465 if (tg3_flag(tp, HW_TSO_1) ||
10466 tg3_flag(tp, HW_TSO_2) ||
10467 tg3_flag(tp, HW_TSO_3))
10468 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10469 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
10470 if (tg3_flag(tp, ENABLE_TSS))
10471 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10472 tw32(SNDBDI_MODE, val);
10473 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10475 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10476 err = tg3_load_5701_a0_firmware_fix(tp);
10481 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10482 /* Ignore any errors for the firmware download. If download
10483 * fails, the device will operate with EEE disabled
10485 tg3_load_57766_firmware(tp);
10488 if (tg3_flag(tp, TSO_CAPABLE)) {
10489 err = tg3_load_tso_firmware(tp);
10494 tp->tx_mode = TX_MODE_ENABLE;
10496 if (tg3_flag(tp, 5755_PLUS) ||
10497 tg3_asic_rev(tp) == ASIC_REV_5906)
10498 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10500 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10501 tg3_asic_rev(tp) == ASIC_REV_5762) {
10502 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10503 tp->tx_mode &= ~val;
10504 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10507 tw32_f(MAC_TX_MODE, tp->tx_mode);
10510 if (tg3_flag(tp, ENABLE_RSS)) {
10511 tg3_rss_write_indir_tbl(tp);
10513 /* Setup the "secret" hash key. */
10514 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10515 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10516 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10517 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10518 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10519 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10520 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10521 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10522 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10523 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10526 tp->rx_mode = RX_MODE_ENABLE;
10527 if (tg3_flag(tp, 5755_PLUS))
10528 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10530 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10531 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10533 if (tg3_flag(tp, ENABLE_RSS))
10534 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10535 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10536 RX_MODE_RSS_IPV6_HASH_EN |
10537 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10538 RX_MODE_RSS_IPV4_HASH_EN |
10539 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10541 tw32_f(MAC_RX_MODE, tp->rx_mode);
10544 tw32(MAC_LED_CTRL, tp->led_ctrl);
10546 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10547 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10548 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10551 tw32_f(MAC_RX_MODE, tp->rx_mode);
10554 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10555 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10556 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10557 /* Set drive transmission level to 1.2V */
10558 /* only if the signal pre-emphasis bit is not set */
10559 val = tr32(MAC_SERDES_CFG);
10562 tw32(MAC_SERDES_CFG, val);
10564 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10565 tw32(MAC_SERDES_CFG, 0x616000);
10568 /* Prevent chip from dropping frames when flow control
10571 if (tg3_flag(tp, 57765_CLASS))
10575 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
10577 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10578 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10579 /* Use hardware link auto-negotiation */
10580 tg3_flag_set(tp, HW_AUTONEG);
10583 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10584 tg3_asic_rev(tp) == ASIC_REV_5714) {
10587 tmp = tr32(SERDES_RX_CTRL);
10588 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10589 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10590 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10591 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10594 if (!tg3_flag(tp, USE_PHYLIB)) {
10595 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10596 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10598 err = tg3_setup_phy(tp, false);
10602 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10603 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10606 /* Clear CRC stats. */
10607 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10608 tg3_writephy(tp, MII_TG3_TEST1,
10609 tmp | MII_TG3_TEST1_CRC_EN);
10610 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10615 __tg3_set_rx_mode(tp->dev);
10617 /* Initialize receive rules. */
10618 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10619 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10620 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10621 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10623 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10627 if (tg3_flag(tp, ENABLE_ASF))
10631 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10633 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10635 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10637 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10639 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10641 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10643 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10645 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10647 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10649 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10651 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10653 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10655 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10657 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10665 if (tg3_flag(tp, ENABLE_APE))
10666 /* Write our heartbeat update interval to APE. */
10667 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10668 APE_HOST_HEARTBEAT_INT_DISABLE);
10670 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10675 /* Called at device open time to get the chip ready for
10676 * packet processing. Invoked with tp->lock held.
10678 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
10680 /* Chip may have been just powered on. If so, the boot code may still
10681 * be running initialization. Wait for it to finish to avoid races in
10682 * accessing the hardware.
10684 tg3_enable_register_access(tp);
10687 tg3_switch_clocks(tp);
10689 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10691 return tg3_reset_hw(tp, reset_phy);
10694 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10698 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10699 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10701 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10704 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10705 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10706 memset(ocir, 0, TG3_OCIR_LEN);
10710 /* sysfs attributes for hwmon */
10711 static ssize_t tg3_show_temp(struct device *dev,
10712 struct device_attribute *devattr, char *buf)
10714 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10715 struct tg3 *tp = dev_get_drvdata(dev);
10718 spin_lock_bh(&tp->lock);
10719 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10720 sizeof(temperature));
10721 spin_unlock_bh(&tp->lock);
10722 return sprintf(buf, "%u\n", temperature);
10726 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10727 TG3_TEMP_SENSOR_OFFSET);
10728 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10729 TG3_TEMP_CAUTION_OFFSET);
10730 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10731 TG3_TEMP_MAX_OFFSET);
10733 static struct attribute *tg3_attrs[] = {
10734 &sensor_dev_attr_temp1_input.dev_attr.attr,
10735 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10736 &sensor_dev_attr_temp1_max.dev_attr.attr,
10739 ATTRIBUTE_GROUPS(tg3);
10741 static void tg3_hwmon_close(struct tg3 *tp)
10743 if (tp->hwmon_dev) {
10744 hwmon_device_unregister(tp->hwmon_dev);
10745 tp->hwmon_dev = NULL;
10749 static void tg3_hwmon_open(struct tg3 *tp)
10753 struct pci_dev *pdev = tp->pdev;
10754 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10756 tg3_sd_scan_scratchpad(tp, ocirs);
10758 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10759 if (!ocirs[i].src_data_length)
10762 size += ocirs[i].src_hdr_length;
10763 size += ocirs[i].src_data_length;
10769 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10771 if (IS_ERR(tp->hwmon_dev)) {
10772 tp->hwmon_dev = NULL;
10773 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10778 #define TG3_STAT_ADD32(PSTAT, REG) \
10779 do { u32 __val = tr32(REG); \
10780 (PSTAT)->low += __val; \
10781 if ((PSTAT)->low < __val) \
10782 (PSTAT)->high += 1; \
10785 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10787 struct tg3_hw_stats *sp = tp->hw_stats;
10792 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10793 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10794 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10795 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10796 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10797 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10798 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10799 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10800 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10801 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10802 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10803 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10804 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
10805 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
10806 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10807 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10810 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10811 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10812 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10813 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
10816 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10817 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10818 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10819 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10820 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10821 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10822 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10823 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10824 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10825 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10826 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10827 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10828 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10829 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
10831 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
10832 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10833 tg3_asic_rev(tp) != ASIC_REV_5762 &&
10834 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10835 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10836 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10838 u32 val = tr32(HOSTCC_FLOW_ATTN);
10839 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10841 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10842 sp->rx_discards.low += val;
10843 if (sp->rx_discards.low < val)
10844 sp->rx_discards.high += 1;
10846 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10848 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
10851 static void tg3_chk_missed_msi(struct tg3 *tp)
10855 for (i = 0; i < tp->irq_cnt; i++) {
10856 struct tg3_napi *tnapi = &tp->napi[i];
10858 if (tg3_has_work(tnapi)) {
10859 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10860 tnapi->last_tx_cons == tnapi->tx_cons) {
10861 if (tnapi->chk_msi_cnt < 1) {
10862 tnapi->chk_msi_cnt++;
10868 tnapi->chk_msi_cnt = 0;
10869 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10870 tnapi->last_tx_cons = tnapi->tx_cons;
10874 static void tg3_timer(unsigned long __opaque)
10876 struct tg3 *tp = (struct tg3 *) __opaque;
10878 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
10879 goto restart_timer;
10881 spin_lock(&tp->lock);
10883 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10884 tg3_flag(tp, 57765_CLASS))
10885 tg3_chk_missed_msi(tp);
10887 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10888 /* BCM4785: Flush posted writes from GbE to host memory. */
10892 if (!tg3_flag(tp, TAGGED_STATUS)) {
10893 /* All of this garbage is because when using non-tagged
10894 * IRQ status the mailbox/status_block protocol the chip
10895 * uses with the cpu is race prone.
10897 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
10898 tw32(GRC_LOCAL_CTRL,
10899 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10901 tw32(HOSTCC_MODE, tp->coalesce_mode |
10902 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
10905 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10906 spin_unlock(&tp->lock);
10907 tg3_reset_task_schedule(tp);
10908 goto restart_timer;
10912 /* This part only runs once per second. */
10913 if (!--tp->timer_counter) {
10914 if (tg3_flag(tp, 5705_PLUS))
10915 tg3_periodic_fetch_stats(tp);
10917 if (tp->setlpicnt && !--tp->setlpicnt)
10918 tg3_phy_eee_enable(tp);
10920 if (tg3_flag(tp, USE_LINKCHG_REG)) {
10924 mac_stat = tr32(MAC_STATUS);
10927 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
10928 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10930 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10934 tg3_setup_phy(tp, false);
10935 } else if (tg3_flag(tp, POLL_SERDES)) {
10936 u32 mac_stat = tr32(MAC_STATUS);
10937 int need_setup = 0;
10940 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10943 if (!tp->link_up &&
10944 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10945 MAC_STATUS_SIGNAL_DET))) {
10949 if (!tp->serdes_counter) {
10952 ~MAC_MODE_PORT_MODE_MASK));
10954 tw32_f(MAC_MODE, tp->mac_mode);
10957 tg3_setup_phy(tp, false);
10959 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10960 tg3_flag(tp, 5780_CLASS)) {
10961 tg3_serdes_parallel_detect(tp);
10962 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
10963 u32 cpmu = tr32(TG3_CPMU_STATUS);
10964 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
10965 TG3_CPMU_STATUS_LINK_MASK);
10967 if (link_up != tp->link_up)
10968 tg3_setup_phy(tp, false);
10971 tp->timer_counter = tp->timer_multiplier;
10974 /* Heartbeat is only sent once every 2 seconds.
10976 * The heartbeat is to tell the ASF firmware that the host
10977 * driver is still alive. In the event that the OS crashes,
10978 * ASF needs to reset the hardware to free up the FIFO space
10979 * that may be filled with rx packets destined for the host.
10980 * If the FIFO is full, ASF will no longer function properly.
10982 * Unintended resets have been reported on real time kernels
10983 * where the timer doesn't run on time. Netpoll will also have
10986 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10987 * to check the ring condition when the heartbeat is expiring
10988 * before doing the reset. This will prevent most unintended
10991 if (!--tp->asf_counter) {
10992 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
10993 tg3_wait_for_event_ack(tp);
10995 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
10996 FWCMD_NICDRV_ALIVE3);
10997 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
10998 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
10999 TG3_FW_UPDATE_TIMEOUT_SEC);
11001 tg3_generate_fw_event(tp);
11003 tp->asf_counter = tp->asf_multiplier;
11006 spin_unlock(&tp->lock);
11009 tp->timer.expires = jiffies + tp->timer_offset;
11010 add_timer(&tp->timer);
11013 static void tg3_timer_init(struct tg3 *tp)
11015 if (tg3_flag(tp, TAGGED_STATUS) &&
11016 tg3_asic_rev(tp) != ASIC_REV_5717 &&
11017 !tg3_flag(tp, 57765_CLASS))
11018 tp->timer_offset = HZ;
11020 tp->timer_offset = HZ / 10;
11022 BUG_ON(tp->timer_offset > HZ);
11024 tp->timer_multiplier = (HZ / tp->timer_offset);
11025 tp->asf_multiplier = (HZ / tp->timer_offset) *
11026 TG3_FW_UPDATE_FREQ_SEC;
11028 init_timer(&tp->timer);
11029 tp->timer.data = (unsigned long) tp;
11030 tp->timer.function = tg3_timer;
11033 static void tg3_timer_start(struct tg3 *tp)
11035 tp->asf_counter = tp->asf_multiplier;
11036 tp->timer_counter = tp->timer_multiplier;
11038 tp->timer.expires = jiffies + tp->timer_offset;
11039 add_timer(&tp->timer);
11042 static void tg3_timer_stop(struct tg3 *tp)
11044 del_timer_sync(&tp->timer);
11047 /* Restart hardware after configuration changes, self-test, etc.
11048 * Invoked with tp->lock held.
11050 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
11051 __releases(tp->lock)
11052 __acquires(tp->lock)
11056 err = tg3_init_hw(tp, reset_phy);
11058 netdev_err(tp->dev,
11059 "Failed to re-initialize device, aborting\n");
11060 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11061 tg3_full_unlock(tp);
11062 tg3_timer_stop(tp);
11064 tg3_napi_enable(tp);
11065 dev_close(tp->dev);
11066 tg3_full_lock(tp, 0);
11071 static void tg3_reset_task(struct work_struct *work)
11073 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11076 tg3_full_lock(tp, 0);
11078 if (!netif_running(tp->dev)) {
11079 tg3_flag_clear(tp, RESET_TASK_PENDING);
11080 tg3_full_unlock(tp);
11084 tg3_full_unlock(tp);
11088 tg3_netif_stop(tp);
11090 tg3_full_lock(tp, 1);
11092 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11093 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11094 tp->write32_rx_mbox = tg3_write_flush_reg32;
11095 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11096 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11099 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
11100 err = tg3_init_hw(tp, true);
11104 tg3_netif_start(tp);
11107 tg3_full_unlock(tp);
11112 tg3_flag_clear(tp, RESET_TASK_PENDING);
11115 static int tg3_request_irq(struct tg3 *tp, int irq_num)
11118 unsigned long flags;
11120 struct tg3_napi *tnapi = &tp->napi[irq_num];
11122 if (tp->irq_cnt == 1)
11123 name = tp->dev->name;
11125 name = &tnapi->irq_lbl[0];
11126 if (tnapi->tx_buffers && tnapi->rx_rcb)
11127 snprintf(name, IFNAMSIZ,
11128 "%s-txrx-%d", tp->dev->name, irq_num);
11129 else if (tnapi->tx_buffers)
11130 snprintf(name, IFNAMSIZ,
11131 "%s-tx-%d", tp->dev->name, irq_num);
11132 else if (tnapi->rx_rcb)
11133 snprintf(name, IFNAMSIZ,
11134 "%s-rx-%d", tp->dev->name, irq_num);
11136 snprintf(name, IFNAMSIZ,
11137 "%s-%d", tp->dev->name, irq_num);
11138 name[IFNAMSIZ-1] = 0;
11141 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11143 if (tg3_flag(tp, 1SHOT_MSI))
11144 fn = tg3_msi_1shot;
11147 fn = tg3_interrupt;
11148 if (tg3_flag(tp, TAGGED_STATUS))
11149 fn = tg3_interrupt_tagged;
11150 flags = IRQF_SHARED;
11153 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
11156 static int tg3_test_interrupt(struct tg3 *tp)
11158 struct tg3_napi *tnapi = &tp->napi[0];
11159 struct net_device *dev = tp->dev;
11160 int err, i, intr_ok = 0;
11163 if (!netif_running(dev))
11166 tg3_disable_ints(tp);
11168 free_irq(tnapi->irq_vec, tnapi);
11171 * Turn off MSI one shot mode. Otherwise this test has no
11172 * observable way to know whether the interrupt was delivered.
11174 if (tg3_flag(tp, 57765_PLUS)) {
11175 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11176 tw32(MSGINT_MODE, val);
11179 err = request_irq(tnapi->irq_vec, tg3_test_isr,
11180 IRQF_SHARED, dev->name, tnapi);
11184 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
11185 tg3_enable_ints(tp);
11187 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11190 for (i = 0; i < 5; i++) {
11191 u32 int_mbox, misc_host_ctrl;
11193 int_mbox = tr32_mailbox(tnapi->int_mbox);
11194 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11196 if ((int_mbox != 0) ||
11197 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11202 if (tg3_flag(tp, 57765_PLUS) &&
11203 tnapi->hw_status->status_tag != tnapi->last_tag)
11204 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11209 tg3_disable_ints(tp);
11211 free_irq(tnapi->irq_vec, tnapi);
11213 err = tg3_request_irq(tp, 0);
11219 /* Reenable MSI one shot mode. */
11220 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
11221 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11222 tw32(MSGINT_MODE, val);
11230 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11231 * successfully restored
11233 static int tg3_test_msi(struct tg3 *tp)
11238 if (!tg3_flag(tp, USING_MSI))
11241 /* Turn off SERR reporting in case MSI terminates with Master
11244 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11245 pci_write_config_word(tp->pdev, PCI_COMMAND,
11246 pci_cmd & ~PCI_COMMAND_SERR);
11248 err = tg3_test_interrupt(tp);
11250 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11255 /* other failures */
11259 /* MSI test failed, go back to INTx mode */
11260 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11261 "to INTx mode. Please report this failure to the PCI "
11262 "maintainer and include system chipset information\n");
11264 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11266 pci_disable_msi(tp->pdev);
11268 tg3_flag_clear(tp, USING_MSI);
11269 tp->napi[0].irq_vec = tp->pdev->irq;
11271 err = tg3_request_irq(tp, 0);
11275 /* Need to reset the chip because the MSI cycle may have terminated
11276 * with Master Abort.
11278 tg3_full_lock(tp, 1);
11280 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11281 err = tg3_init_hw(tp, true);
11283 tg3_full_unlock(tp);
11286 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11291 static int tg3_request_firmware(struct tg3 *tp)
11293 const struct tg3_firmware_hdr *fw_hdr;
11295 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
11296 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11301 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
11303 /* Firmware blob starts with version numbers, followed by
11304 * start address and _full_ length including BSS sections
11305 * (which must be longer than the actual data, of course
11308 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11309 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
11310 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11311 tp->fw_len, tp->fw_needed);
11312 release_firmware(tp->fw);
11317 /* We no longer need firmware; we have it. */
11318 tp->fw_needed = NULL;
11322 static u32 tg3_irq_count(struct tg3 *tp)
11324 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
11327 /* We want as many rx rings enabled as there are cpus.
11328 * In multiqueue MSI-X mode, the first MSI-X vector
11329 * only deals with link interrupts, etc, so we add
11330 * one to the number of vectors we are requesting.
11332 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11338 static bool tg3_enable_msix(struct tg3 *tp)
11341 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
11343 tp->txq_cnt = tp->txq_req;
11344 tp->rxq_cnt = tp->rxq_req;
11346 tp->rxq_cnt = netif_get_num_default_rss_queues();
11347 if (tp->rxq_cnt > tp->rxq_max)
11348 tp->rxq_cnt = tp->rxq_max;
11350 /* Disable multiple TX rings by default. Simple round-robin hardware
11351 * scheduling of the TX rings can cause starvation of rings with
11352 * small packets when other rings have TSO or jumbo packets.
11357 tp->irq_cnt = tg3_irq_count(tp);
11359 for (i = 0; i < tp->irq_max; i++) {
11360 msix_ent[i].entry = i;
11361 msix_ent[i].vector = 0;
11364 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
11367 } else if (rc < tp->irq_cnt) {
11368 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11371 tp->rxq_cnt = max(rc - 1, 1);
11373 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11376 for (i = 0; i < tp->irq_max; i++)
11377 tp->napi[i].irq_vec = msix_ent[i].vector;
11379 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11380 pci_disable_msix(tp->pdev);
11384 if (tp->irq_cnt == 1)
11387 tg3_flag_set(tp, ENABLE_RSS);
11389 if (tp->txq_cnt > 1)
11390 tg3_flag_set(tp, ENABLE_TSS);
11392 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11397 static void tg3_ints_init(struct tg3 *tp)
11399 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11400 !tg3_flag(tp, TAGGED_STATUS)) {
11401 /* All MSI supporting chips should support tagged
11402 * status. Assert that this is the case.
11404 netdev_warn(tp->dev,
11405 "MSI without TAGGED_STATUS? Not using MSI\n");
11409 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11410 tg3_flag_set(tp, USING_MSIX);
11411 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11412 tg3_flag_set(tp, USING_MSI);
11414 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11415 u32 msi_mode = tr32(MSGINT_MODE);
11416 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11417 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
11418 if (!tg3_flag(tp, 1SHOT_MSI))
11419 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
11420 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11423 if (!tg3_flag(tp, USING_MSIX)) {
11425 tp->napi[0].irq_vec = tp->pdev->irq;
11428 if (tp->irq_cnt == 1) {
11431 netif_set_real_num_tx_queues(tp->dev, 1);
11432 netif_set_real_num_rx_queues(tp->dev, 1);
11436 static void tg3_ints_fini(struct tg3 *tp)
11438 if (tg3_flag(tp, USING_MSIX))
11439 pci_disable_msix(tp->pdev);
11440 else if (tg3_flag(tp, USING_MSI))
11441 pci_disable_msi(tp->pdev);
11442 tg3_flag_clear(tp, USING_MSI);
11443 tg3_flag_clear(tp, USING_MSIX);
11444 tg3_flag_clear(tp, ENABLE_RSS);
11445 tg3_flag_clear(tp, ENABLE_TSS);
11448 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11451 struct net_device *dev = tp->dev;
11455 * Setup interrupts first so we know how
11456 * many NAPI resources to allocate
11460 tg3_rss_check_indir_tbl(tp);
11462 /* The placement of this call is tied
11463 * to the setup and use of Host TX descriptors.
11465 err = tg3_alloc_consistent(tp);
11467 goto out_ints_fini;
11471 tg3_napi_enable(tp);
11473 for (i = 0; i < tp->irq_cnt; i++) {
11474 struct tg3_napi *tnapi = &tp->napi[i];
11475 err = tg3_request_irq(tp, i);
11477 for (i--; i >= 0; i--) {
11478 tnapi = &tp->napi[i];
11479 free_irq(tnapi->irq_vec, tnapi);
11481 goto out_napi_fini;
11485 tg3_full_lock(tp, 0);
11488 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11490 err = tg3_init_hw(tp, reset_phy);
11492 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11493 tg3_free_rings(tp);
11496 tg3_full_unlock(tp);
11501 if (test_irq && tg3_flag(tp, USING_MSI)) {
11502 err = tg3_test_msi(tp);
11505 tg3_full_lock(tp, 0);
11506 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11507 tg3_free_rings(tp);
11508 tg3_full_unlock(tp);
11510 goto out_napi_fini;
11513 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11514 u32 val = tr32(PCIE_TRANSACTION_CFG);
11516 tw32(PCIE_TRANSACTION_CFG,
11517 val | PCIE_TRANS_CFG_1SHOT_MSI);
11523 tg3_hwmon_open(tp);
11525 tg3_full_lock(tp, 0);
11527 tg3_timer_start(tp);
11528 tg3_flag_set(tp, INIT_COMPLETE);
11529 tg3_enable_ints(tp);
11534 tg3_ptp_resume(tp);
11537 tg3_full_unlock(tp);
11539 netif_tx_start_all_queues(dev);
11542 * Reset loopback feature if it was turned on while the device was down
11543 * make sure that it's installed properly now.
11545 if (dev->features & NETIF_F_LOOPBACK)
11546 tg3_set_loopback(dev, dev->features);
11551 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11552 struct tg3_napi *tnapi = &tp->napi[i];
11553 free_irq(tnapi->irq_vec, tnapi);
11557 tg3_napi_disable(tp);
11559 tg3_free_consistent(tp);
11567 static void tg3_stop(struct tg3 *tp)
11571 tg3_reset_task_cancel(tp);
11572 tg3_netif_stop(tp);
11574 tg3_timer_stop(tp);
11576 tg3_hwmon_close(tp);
11580 tg3_full_lock(tp, 1);
11582 tg3_disable_ints(tp);
11584 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11585 tg3_free_rings(tp);
11586 tg3_flag_clear(tp, INIT_COMPLETE);
11588 tg3_full_unlock(tp);
11590 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11591 struct tg3_napi *tnapi = &tp->napi[i];
11592 free_irq(tnapi->irq_vec, tnapi);
11599 tg3_free_consistent(tp);
11602 static int tg3_open(struct net_device *dev)
11604 struct tg3 *tp = netdev_priv(dev);
11607 if (tp->fw_needed) {
11608 err = tg3_request_firmware(tp);
11609 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11611 netdev_warn(tp->dev, "EEE capability disabled\n");
11612 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11613 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11614 netdev_warn(tp->dev, "EEE capability restored\n");
11615 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11617 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11621 netdev_warn(tp->dev, "TSO capability disabled\n");
11622 tg3_flag_clear(tp, TSO_CAPABLE);
11623 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11624 netdev_notice(tp->dev, "TSO capability restored\n");
11625 tg3_flag_set(tp, TSO_CAPABLE);
11629 tg3_carrier_off(tp);
11631 err = tg3_power_up(tp);
11635 tg3_full_lock(tp, 0);
11637 tg3_disable_ints(tp);
11638 tg3_flag_clear(tp, INIT_COMPLETE);
11640 tg3_full_unlock(tp);
11642 err = tg3_start(tp,
11643 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11646 tg3_frob_aux_power(tp, false);
11647 pci_set_power_state(tp->pdev, PCI_D3hot);
11650 if (tg3_flag(tp, PTP_CAPABLE)) {
11651 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11653 if (IS_ERR(tp->ptp_clock))
11654 tp->ptp_clock = NULL;
11660 static int tg3_close(struct net_device *dev)
11662 struct tg3 *tp = netdev_priv(dev);
11668 /* Clear stats across close / open calls */
11669 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11670 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
11672 if (pci_device_is_present(tp->pdev)) {
11673 tg3_power_down_prepare(tp);
11675 tg3_carrier_off(tp);
11680 static inline u64 get_stat64(tg3_stat64_t *val)
11682 return ((u64)val->high << 32) | ((u64)val->low);
11685 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11687 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11689 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11690 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11691 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11694 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11695 tg3_writephy(tp, MII_TG3_TEST1,
11696 val | MII_TG3_TEST1_CRC_EN);
11697 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11701 tp->phy_crc_errors += val;
11703 return tp->phy_crc_errors;
11706 return get_stat64(&hw_stats->rx_fcs_errors);
11709 #define ESTAT_ADD(member) \
11710 estats->member = old_estats->member + \
11711 get_stat64(&hw_stats->member)
11713 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11715 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11716 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11718 ESTAT_ADD(rx_octets);
11719 ESTAT_ADD(rx_fragments);
11720 ESTAT_ADD(rx_ucast_packets);
11721 ESTAT_ADD(rx_mcast_packets);
11722 ESTAT_ADD(rx_bcast_packets);
11723 ESTAT_ADD(rx_fcs_errors);
11724 ESTAT_ADD(rx_align_errors);
11725 ESTAT_ADD(rx_xon_pause_rcvd);
11726 ESTAT_ADD(rx_xoff_pause_rcvd);
11727 ESTAT_ADD(rx_mac_ctrl_rcvd);
11728 ESTAT_ADD(rx_xoff_entered);
11729 ESTAT_ADD(rx_frame_too_long_errors);
11730 ESTAT_ADD(rx_jabbers);
11731 ESTAT_ADD(rx_undersize_packets);
11732 ESTAT_ADD(rx_in_length_errors);
11733 ESTAT_ADD(rx_out_length_errors);
11734 ESTAT_ADD(rx_64_or_less_octet_packets);
11735 ESTAT_ADD(rx_65_to_127_octet_packets);
11736 ESTAT_ADD(rx_128_to_255_octet_packets);
11737 ESTAT_ADD(rx_256_to_511_octet_packets);
11738 ESTAT_ADD(rx_512_to_1023_octet_packets);
11739 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11740 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11741 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11742 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11743 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11745 ESTAT_ADD(tx_octets);
11746 ESTAT_ADD(tx_collisions);
11747 ESTAT_ADD(tx_xon_sent);
11748 ESTAT_ADD(tx_xoff_sent);
11749 ESTAT_ADD(tx_flow_control);
11750 ESTAT_ADD(tx_mac_errors);
11751 ESTAT_ADD(tx_single_collisions);
11752 ESTAT_ADD(tx_mult_collisions);
11753 ESTAT_ADD(tx_deferred);
11754 ESTAT_ADD(tx_excessive_collisions);
11755 ESTAT_ADD(tx_late_collisions);
11756 ESTAT_ADD(tx_collide_2times);
11757 ESTAT_ADD(tx_collide_3times);
11758 ESTAT_ADD(tx_collide_4times);
11759 ESTAT_ADD(tx_collide_5times);
11760 ESTAT_ADD(tx_collide_6times);
11761 ESTAT_ADD(tx_collide_7times);
11762 ESTAT_ADD(tx_collide_8times);
11763 ESTAT_ADD(tx_collide_9times);
11764 ESTAT_ADD(tx_collide_10times);
11765 ESTAT_ADD(tx_collide_11times);
11766 ESTAT_ADD(tx_collide_12times);
11767 ESTAT_ADD(tx_collide_13times);
11768 ESTAT_ADD(tx_collide_14times);
11769 ESTAT_ADD(tx_collide_15times);
11770 ESTAT_ADD(tx_ucast_packets);
11771 ESTAT_ADD(tx_mcast_packets);
11772 ESTAT_ADD(tx_bcast_packets);
11773 ESTAT_ADD(tx_carrier_sense_errors);
11774 ESTAT_ADD(tx_discards);
11775 ESTAT_ADD(tx_errors);
11777 ESTAT_ADD(dma_writeq_full);
11778 ESTAT_ADD(dma_write_prioq_full);
11779 ESTAT_ADD(rxbds_empty);
11780 ESTAT_ADD(rx_discards);
11781 ESTAT_ADD(rx_errors);
11782 ESTAT_ADD(rx_threshold_hit);
11784 ESTAT_ADD(dma_readq_full);
11785 ESTAT_ADD(dma_read_prioq_full);
11786 ESTAT_ADD(tx_comp_queue_full);
11788 ESTAT_ADD(ring_set_send_prod_index);
11789 ESTAT_ADD(ring_status_update);
11790 ESTAT_ADD(nic_irqs);
11791 ESTAT_ADD(nic_avoided_irqs);
11792 ESTAT_ADD(nic_tx_threshold_hit);
11794 ESTAT_ADD(mbuf_lwm_thresh_hit);
11797 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11799 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11800 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11802 stats->rx_packets = old_stats->rx_packets +
11803 get_stat64(&hw_stats->rx_ucast_packets) +
11804 get_stat64(&hw_stats->rx_mcast_packets) +
11805 get_stat64(&hw_stats->rx_bcast_packets);
11807 stats->tx_packets = old_stats->tx_packets +
11808 get_stat64(&hw_stats->tx_ucast_packets) +
11809 get_stat64(&hw_stats->tx_mcast_packets) +
11810 get_stat64(&hw_stats->tx_bcast_packets);
11812 stats->rx_bytes = old_stats->rx_bytes +
11813 get_stat64(&hw_stats->rx_octets);
11814 stats->tx_bytes = old_stats->tx_bytes +
11815 get_stat64(&hw_stats->tx_octets);
11817 stats->rx_errors = old_stats->rx_errors +
11818 get_stat64(&hw_stats->rx_errors);
11819 stats->tx_errors = old_stats->tx_errors +
11820 get_stat64(&hw_stats->tx_errors) +
11821 get_stat64(&hw_stats->tx_mac_errors) +
11822 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11823 get_stat64(&hw_stats->tx_discards);
11825 stats->multicast = old_stats->multicast +
11826 get_stat64(&hw_stats->rx_mcast_packets);
11827 stats->collisions = old_stats->collisions +
11828 get_stat64(&hw_stats->tx_collisions);
11830 stats->rx_length_errors = old_stats->rx_length_errors +
11831 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11832 get_stat64(&hw_stats->rx_undersize_packets);
11834 stats->rx_frame_errors = old_stats->rx_frame_errors +
11835 get_stat64(&hw_stats->rx_align_errors);
11836 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11837 get_stat64(&hw_stats->tx_discards);
11838 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11839 get_stat64(&hw_stats->tx_carrier_sense_errors);
11841 stats->rx_crc_errors = old_stats->rx_crc_errors +
11842 tg3_calc_crc_errors(tp);
11844 stats->rx_missed_errors = old_stats->rx_missed_errors +
11845 get_stat64(&hw_stats->rx_discards);
11847 stats->rx_dropped = tp->rx_dropped;
11848 stats->tx_dropped = tp->tx_dropped;
11851 static int tg3_get_regs_len(struct net_device *dev)
11853 return TG3_REG_BLK_SIZE;
11856 static void tg3_get_regs(struct net_device *dev,
11857 struct ethtool_regs *regs, void *_p)
11859 struct tg3 *tp = netdev_priv(dev);
11863 memset(_p, 0, TG3_REG_BLK_SIZE);
11865 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11868 tg3_full_lock(tp, 0);
11870 tg3_dump_legacy_regs(tp, (u32 *)_p);
11872 tg3_full_unlock(tp);
11875 static int tg3_get_eeprom_len(struct net_device *dev)
11877 struct tg3 *tp = netdev_priv(dev);
11879 return tp->nvram_size;
11882 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11884 struct tg3 *tp = netdev_priv(dev);
11887 u32 i, offset, len, b_offset, b_count;
11890 if (tg3_flag(tp, NO_NVRAM))
11893 offset = eeprom->offset;
11897 eeprom->magic = TG3_EEPROM_MAGIC;
11900 /* adjustments to start on required 4 byte boundary */
11901 b_offset = offset & 3;
11902 b_count = 4 - b_offset;
11903 if (b_count > len) {
11904 /* i.e. offset=1 len=2 */
11907 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
11910 memcpy(data, ((char *)&val) + b_offset, b_count);
11913 eeprom->len += b_count;
11916 /* read bytes up to the last 4 byte boundary */
11917 pd = &data[eeprom->len];
11918 for (i = 0; i < (len - (len & 3)); i += 4) {
11919 ret = tg3_nvram_read_be32(tp, offset + i, &val);
11924 memcpy(pd + i, &val, 4);
11929 /* read last bytes not ending on 4 byte boundary */
11930 pd = &data[eeprom->len];
11932 b_offset = offset + len - b_count;
11933 ret = tg3_nvram_read_be32(tp, b_offset, &val);
11936 memcpy(pd, &val, b_count);
11937 eeprom->len += b_count;
11942 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11944 struct tg3 *tp = netdev_priv(dev);
11946 u32 offset, len, b_offset, odd_len;
11950 if (tg3_flag(tp, NO_NVRAM) ||
11951 eeprom->magic != TG3_EEPROM_MAGIC)
11954 offset = eeprom->offset;
11957 if ((b_offset = (offset & 3))) {
11958 /* adjustments to start on required 4 byte boundary */
11959 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
11970 /* adjustments to end on required 4 byte boundary */
11972 len = (len + 3) & ~3;
11973 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
11979 if (b_offset || odd_len) {
11980 buf = kmalloc(len, GFP_KERNEL);
11984 memcpy(buf, &start, 4);
11986 memcpy(buf+len-4, &end, 4);
11987 memcpy(buf + b_offset, data, eeprom->len);
11990 ret = tg3_nvram_write_block(tp, offset, len, buf);
11998 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12000 struct tg3 *tp = netdev_priv(dev);
12002 if (tg3_flag(tp, USE_PHYLIB)) {
12003 struct phy_device *phydev;
12004 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12006 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12007 return phy_ethtool_gset(phydev, cmd);
12010 cmd->supported = (SUPPORTED_Autoneg);
12012 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12013 cmd->supported |= (SUPPORTED_1000baseT_Half |
12014 SUPPORTED_1000baseT_Full);
12016 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12017 cmd->supported |= (SUPPORTED_100baseT_Half |
12018 SUPPORTED_100baseT_Full |
12019 SUPPORTED_10baseT_Half |
12020 SUPPORTED_10baseT_Full |
12022 cmd->port = PORT_TP;
12024 cmd->supported |= SUPPORTED_FIBRE;
12025 cmd->port = PORT_FIBRE;
12028 cmd->advertising = tp->link_config.advertising;
12029 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12030 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12031 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12032 cmd->advertising |= ADVERTISED_Pause;
12034 cmd->advertising |= ADVERTISED_Pause |
12035 ADVERTISED_Asym_Pause;
12037 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12038 cmd->advertising |= ADVERTISED_Asym_Pause;
12041 if (netif_running(dev) && tp->link_up) {
12042 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
12043 cmd->duplex = tp->link_config.active_duplex;
12044 cmd->lp_advertising = tp->link_config.rmt_adv;
12045 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12046 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12047 cmd->eth_tp_mdix = ETH_TP_MDI_X;
12049 cmd->eth_tp_mdix = ETH_TP_MDI;
12052 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
12053 cmd->duplex = DUPLEX_UNKNOWN;
12054 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
12056 cmd->phy_address = tp->phy_addr;
12057 cmd->transceiver = XCVR_INTERNAL;
12058 cmd->autoneg = tp->link_config.autoneg;
12064 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12066 struct tg3 *tp = netdev_priv(dev);
12067 u32 speed = ethtool_cmd_speed(cmd);
12069 if (tg3_flag(tp, USE_PHYLIB)) {
12070 struct phy_device *phydev;
12071 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12073 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12074 return phy_ethtool_sset(phydev, cmd);
12077 if (cmd->autoneg != AUTONEG_ENABLE &&
12078 cmd->autoneg != AUTONEG_DISABLE)
12081 if (cmd->autoneg == AUTONEG_DISABLE &&
12082 cmd->duplex != DUPLEX_FULL &&
12083 cmd->duplex != DUPLEX_HALF)
12086 if (cmd->autoneg == AUTONEG_ENABLE) {
12087 u32 mask = ADVERTISED_Autoneg |
12089 ADVERTISED_Asym_Pause;
12091 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12092 mask |= ADVERTISED_1000baseT_Half |
12093 ADVERTISED_1000baseT_Full;
12095 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12096 mask |= ADVERTISED_100baseT_Half |
12097 ADVERTISED_100baseT_Full |
12098 ADVERTISED_10baseT_Half |
12099 ADVERTISED_10baseT_Full |
12102 mask |= ADVERTISED_FIBRE;
12104 if (cmd->advertising & ~mask)
12107 mask &= (ADVERTISED_1000baseT_Half |
12108 ADVERTISED_1000baseT_Full |
12109 ADVERTISED_100baseT_Half |
12110 ADVERTISED_100baseT_Full |
12111 ADVERTISED_10baseT_Half |
12112 ADVERTISED_10baseT_Full);
12114 cmd->advertising &= mask;
12116 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
12117 if (speed != SPEED_1000)
12120 if (cmd->duplex != DUPLEX_FULL)
12123 if (speed != SPEED_100 &&
12129 tg3_full_lock(tp, 0);
12131 tp->link_config.autoneg = cmd->autoneg;
12132 if (cmd->autoneg == AUTONEG_ENABLE) {
12133 tp->link_config.advertising = (cmd->advertising |
12134 ADVERTISED_Autoneg);
12135 tp->link_config.speed = SPEED_UNKNOWN;
12136 tp->link_config.duplex = DUPLEX_UNKNOWN;
12138 tp->link_config.advertising = 0;
12139 tp->link_config.speed = speed;
12140 tp->link_config.duplex = cmd->duplex;
12143 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12145 tg3_warn_mgmt_link_flap(tp);
12147 if (netif_running(dev))
12148 tg3_setup_phy(tp, true);
12150 tg3_full_unlock(tp);
12155 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12157 struct tg3 *tp = netdev_priv(dev);
12159 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12160 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12161 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12162 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
12165 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12167 struct tg3 *tp = netdev_priv(dev);
12169 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
12170 wol->supported = WAKE_MAGIC;
12172 wol->supported = 0;
12174 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
12175 wol->wolopts = WAKE_MAGIC;
12176 memset(&wol->sopass, 0, sizeof(wol->sopass));
12179 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12181 struct tg3 *tp = netdev_priv(dev);
12182 struct device *dp = &tp->pdev->dev;
12184 if (wol->wolopts & ~WAKE_MAGIC)
12186 if ((wol->wolopts & WAKE_MAGIC) &&
12187 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
12190 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12192 if (device_may_wakeup(dp))
12193 tg3_flag_set(tp, WOL_ENABLE);
12195 tg3_flag_clear(tp, WOL_ENABLE);
12200 static u32 tg3_get_msglevel(struct net_device *dev)
12202 struct tg3 *tp = netdev_priv(dev);
12203 return tp->msg_enable;
12206 static void tg3_set_msglevel(struct net_device *dev, u32 value)
12208 struct tg3 *tp = netdev_priv(dev);
12209 tp->msg_enable = value;
12212 static int tg3_nway_reset(struct net_device *dev)
12214 struct tg3 *tp = netdev_priv(dev);
12217 if (!netif_running(dev))
12220 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12223 tg3_warn_mgmt_link_flap(tp);
12225 if (tg3_flag(tp, USE_PHYLIB)) {
12226 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12228 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
12232 spin_lock_bh(&tp->lock);
12234 tg3_readphy(tp, MII_BMCR, &bmcr);
12235 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12236 ((bmcr & BMCR_ANENABLE) ||
12237 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
12238 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12242 spin_unlock_bh(&tp->lock);
12248 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12250 struct tg3 *tp = netdev_priv(dev);
12252 ering->rx_max_pending = tp->rx_std_ring_mask;
12253 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12254 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
12256 ering->rx_jumbo_max_pending = 0;
12258 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
12260 ering->rx_pending = tp->rx_pending;
12261 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12262 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12264 ering->rx_jumbo_pending = 0;
12266 ering->tx_pending = tp->napi[0].tx_pending;
12269 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12271 struct tg3 *tp = netdev_priv(dev);
12272 int i, irq_sync = 0, err = 0;
12274 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12275 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
12276 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12277 (ering->tx_pending <= MAX_SKB_FRAGS) ||
12278 (tg3_flag(tp, TSO_BUG) &&
12279 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
12282 if (netif_running(dev)) {
12284 tg3_netif_stop(tp);
12288 tg3_full_lock(tp, irq_sync);
12290 tp->rx_pending = ering->rx_pending;
12292 if (tg3_flag(tp, MAX_RXPEND_64) &&
12293 tp->rx_pending > 63)
12294 tp->rx_pending = 63;
12295 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
12297 for (i = 0; i < tp->irq_max; i++)
12298 tp->napi[i].tx_pending = ering->tx_pending;
12300 if (netif_running(dev)) {
12301 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12302 err = tg3_restart_hw(tp, false);
12304 tg3_netif_start(tp);
12307 tg3_full_unlock(tp);
12309 if (irq_sync && !err)
12315 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12317 struct tg3 *tp = netdev_priv(dev);
12319 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
12321 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
12322 epause->rx_pause = 1;
12324 epause->rx_pause = 0;
12326 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
12327 epause->tx_pause = 1;
12329 epause->tx_pause = 0;
12332 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12334 struct tg3 *tp = netdev_priv(dev);
12337 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12338 tg3_warn_mgmt_link_flap(tp);
12340 if (tg3_flag(tp, USE_PHYLIB)) {
12342 struct phy_device *phydev;
12344 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12346 if (!(phydev->supported & SUPPORTED_Pause) ||
12347 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
12348 (epause->rx_pause != epause->tx_pause)))
12351 tp->link_config.flowctrl = 0;
12352 if (epause->rx_pause) {
12353 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12355 if (epause->tx_pause) {
12356 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12357 newadv = ADVERTISED_Pause;
12359 newadv = ADVERTISED_Pause |
12360 ADVERTISED_Asym_Pause;
12361 } else if (epause->tx_pause) {
12362 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12363 newadv = ADVERTISED_Asym_Pause;
12367 if (epause->autoneg)
12368 tg3_flag_set(tp, PAUSE_AUTONEG);
12370 tg3_flag_clear(tp, PAUSE_AUTONEG);
12372 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12373 u32 oldadv = phydev->advertising &
12374 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12375 if (oldadv != newadv) {
12376 phydev->advertising &=
12377 ~(ADVERTISED_Pause |
12378 ADVERTISED_Asym_Pause);
12379 phydev->advertising |= newadv;
12380 if (phydev->autoneg) {
12382 * Always renegotiate the link to
12383 * inform our link partner of our
12384 * flow control settings, even if the
12385 * flow control is forced. Let
12386 * tg3_adjust_link() do the final
12387 * flow control setup.
12389 return phy_start_aneg(phydev);
12393 if (!epause->autoneg)
12394 tg3_setup_flow_control(tp, 0, 0);
12396 tp->link_config.advertising &=
12397 ~(ADVERTISED_Pause |
12398 ADVERTISED_Asym_Pause);
12399 tp->link_config.advertising |= newadv;
12404 if (netif_running(dev)) {
12405 tg3_netif_stop(tp);
12409 tg3_full_lock(tp, irq_sync);
12411 if (epause->autoneg)
12412 tg3_flag_set(tp, PAUSE_AUTONEG);
12414 tg3_flag_clear(tp, PAUSE_AUTONEG);
12415 if (epause->rx_pause)
12416 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12418 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12419 if (epause->tx_pause)
12420 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12422 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12424 if (netif_running(dev)) {
12425 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12426 err = tg3_restart_hw(tp, false);
12428 tg3_netif_start(tp);
12431 tg3_full_unlock(tp);
12434 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12439 static int tg3_get_sset_count(struct net_device *dev, int sset)
12443 return TG3_NUM_TEST;
12445 return TG3_NUM_STATS;
12447 return -EOPNOTSUPP;
12451 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12452 u32 *rules __always_unused)
12454 struct tg3 *tp = netdev_priv(dev);
12456 if (!tg3_flag(tp, SUPPORT_MSIX))
12457 return -EOPNOTSUPP;
12459 switch (info->cmd) {
12460 case ETHTOOL_GRXRINGS:
12461 if (netif_running(tp->dev))
12462 info->data = tp->rxq_cnt;
12464 info->data = num_online_cpus();
12465 if (info->data > TG3_RSS_MAX_NUM_QS)
12466 info->data = TG3_RSS_MAX_NUM_QS;
12469 /* The first interrupt vector only
12470 * handles link interrupts.
12476 return -EOPNOTSUPP;
12480 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12483 struct tg3 *tp = netdev_priv(dev);
12485 if (tg3_flag(tp, SUPPORT_MSIX))
12486 size = TG3_RSS_INDIR_TBL_SIZE;
12491 static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
12493 struct tg3 *tp = netdev_priv(dev);
12496 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12497 indir[i] = tp->rss_ind_tbl[i];
12502 static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
12504 struct tg3 *tp = netdev_priv(dev);
12507 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12508 tp->rss_ind_tbl[i] = indir[i];
12510 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12513 /* It is legal to write the indirection
12514 * table while the device is running.
12516 tg3_full_lock(tp, 0);
12517 tg3_rss_write_indir_tbl(tp);
12518 tg3_full_unlock(tp);
12523 static void tg3_get_channels(struct net_device *dev,
12524 struct ethtool_channels *channel)
12526 struct tg3 *tp = netdev_priv(dev);
12527 u32 deflt_qs = netif_get_num_default_rss_queues();
12529 channel->max_rx = tp->rxq_max;
12530 channel->max_tx = tp->txq_max;
12532 if (netif_running(dev)) {
12533 channel->rx_count = tp->rxq_cnt;
12534 channel->tx_count = tp->txq_cnt;
12537 channel->rx_count = tp->rxq_req;
12539 channel->rx_count = min(deflt_qs, tp->rxq_max);
12542 channel->tx_count = tp->txq_req;
12544 channel->tx_count = min(deflt_qs, tp->txq_max);
12548 static int tg3_set_channels(struct net_device *dev,
12549 struct ethtool_channels *channel)
12551 struct tg3 *tp = netdev_priv(dev);
12553 if (!tg3_flag(tp, SUPPORT_MSIX))
12554 return -EOPNOTSUPP;
12556 if (channel->rx_count > tp->rxq_max ||
12557 channel->tx_count > tp->txq_max)
12560 tp->rxq_req = channel->rx_count;
12561 tp->txq_req = channel->tx_count;
12563 if (!netif_running(dev))
12568 tg3_carrier_off(tp);
12570 tg3_start(tp, true, false, false);
12575 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
12577 switch (stringset) {
12579 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
12582 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
12585 WARN_ON(1); /* we need a WARN() */
12590 static int tg3_set_phys_id(struct net_device *dev,
12591 enum ethtool_phys_id_state state)
12593 struct tg3 *tp = netdev_priv(dev);
12595 if (!netif_running(tp->dev))
12599 case ETHTOOL_ID_ACTIVE:
12600 return 1; /* cycle on/off once per second */
12602 case ETHTOOL_ID_ON:
12603 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12604 LED_CTRL_1000MBPS_ON |
12605 LED_CTRL_100MBPS_ON |
12606 LED_CTRL_10MBPS_ON |
12607 LED_CTRL_TRAFFIC_OVERRIDE |
12608 LED_CTRL_TRAFFIC_BLINK |
12609 LED_CTRL_TRAFFIC_LED);
12612 case ETHTOOL_ID_OFF:
12613 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12614 LED_CTRL_TRAFFIC_OVERRIDE);
12617 case ETHTOOL_ID_INACTIVE:
12618 tw32(MAC_LED_CTRL, tp->led_ctrl);
12625 static void tg3_get_ethtool_stats(struct net_device *dev,
12626 struct ethtool_stats *estats, u64 *tmp_stats)
12628 struct tg3 *tp = netdev_priv(dev);
12631 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12633 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
12636 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
12640 u32 offset = 0, len = 0;
12643 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12646 if (magic == TG3_EEPROM_MAGIC) {
12647 for (offset = TG3_NVM_DIR_START;
12648 offset < TG3_NVM_DIR_END;
12649 offset += TG3_NVM_DIRENT_SIZE) {
12650 if (tg3_nvram_read(tp, offset, &val))
12653 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12654 TG3_NVM_DIRTYPE_EXTVPD)
12658 if (offset != TG3_NVM_DIR_END) {
12659 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12660 if (tg3_nvram_read(tp, offset + 4, &offset))
12663 offset = tg3_nvram_logical_addr(tp, offset);
12667 if (!offset || !len) {
12668 offset = TG3_NVM_VPD_OFF;
12669 len = TG3_NVM_VPD_LEN;
12672 buf = kmalloc(len, GFP_KERNEL);
12676 if (magic == TG3_EEPROM_MAGIC) {
12677 for (i = 0; i < len; i += 4) {
12678 /* The data is in little-endian format in NVRAM.
12679 * Use the big-endian read routines to preserve
12680 * the byte order as it exists in NVRAM.
12682 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12688 unsigned int pos = 0;
12690 ptr = (u8 *)&buf[0];
12691 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12692 cnt = pci_read_vpd(tp->pdev, pos,
12694 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12712 #define NVRAM_TEST_SIZE 0x100
12713 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12714 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12715 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12716 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12717 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12718 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12719 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12720 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12722 static int tg3_test_nvram(struct tg3 *tp)
12724 u32 csum, magic, len;
12726 int i, j, k, err = 0, size;
12728 if (tg3_flag(tp, NO_NVRAM))
12731 if (tg3_nvram_read(tp, 0, &magic) != 0)
12734 if (magic == TG3_EEPROM_MAGIC)
12735 size = NVRAM_TEST_SIZE;
12736 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
12737 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12738 TG3_EEPROM_SB_FORMAT_1) {
12739 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12740 case TG3_EEPROM_SB_REVISION_0:
12741 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12743 case TG3_EEPROM_SB_REVISION_2:
12744 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12746 case TG3_EEPROM_SB_REVISION_3:
12747 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12749 case TG3_EEPROM_SB_REVISION_4:
12750 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12752 case TG3_EEPROM_SB_REVISION_5:
12753 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12755 case TG3_EEPROM_SB_REVISION_6:
12756 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12763 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12764 size = NVRAM_SELFBOOT_HW_SIZE;
12768 buf = kmalloc(size, GFP_KERNEL);
12773 for (i = 0, j = 0; i < size; i += 4, j++) {
12774 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12781 /* Selfboot format */
12782 magic = be32_to_cpu(buf[0]);
12783 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
12784 TG3_EEPROM_MAGIC_FW) {
12785 u8 *buf8 = (u8 *) buf, csum8 = 0;
12787 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
12788 TG3_EEPROM_SB_REVISION_2) {
12789 /* For rev 2, the csum doesn't include the MBA. */
12790 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12792 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12795 for (i = 0; i < size; i++)
12808 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
12809 TG3_EEPROM_MAGIC_HW) {
12810 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
12811 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
12812 u8 *buf8 = (u8 *) buf;
12814 /* Separate the parity bits and the data bytes. */
12815 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12816 if ((i == 0) || (i == 8)) {
12820 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12821 parity[k++] = buf8[i] & msk;
12823 } else if (i == 16) {
12827 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12828 parity[k++] = buf8[i] & msk;
12831 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12832 parity[k++] = buf8[i] & msk;
12835 data[j++] = buf8[i];
12839 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12840 u8 hw8 = hweight8(data[i]);
12842 if ((hw8 & 0x1) && parity[i])
12844 else if (!(hw8 & 0x1) && !parity[i])
12853 /* Bootstrap checksum at offset 0x10 */
12854 csum = calc_crc((unsigned char *) buf, 0x10);
12855 if (csum != le32_to_cpu(buf[0x10/4]))
12858 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12859 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
12860 if (csum != le32_to_cpu(buf[0xfc/4]))
12865 buf = tg3_vpd_readblock(tp, &len);
12869 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
12871 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12875 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
12878 i += PCI_VPD_LRDT_TAG_SIZE;
12879 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12880 PCI_VPD_RO_KEYWORD_CHKSUM);
12884 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12886 for (i = 0; i <= j; i++)
12887 csum8 += ((u8 *)buf)[i];
12901 #define TG3_SERDES_TIMEOUT_SEC 2
12902 #define TG3_COPPER_TIMEOUT_SEC 6
12904 static int tg3_test_link(struct tg3 *tp)
12908 if (!netif_running(tp->dev))
12911 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12912 max = TG3_SERDES_TIMEOUT_SEC;
12914 max = TG3_COPPER_TIMEOUT_SEC;
12916 for (i = 0; i < max; i++) {
12920 if (msleep_interruptible(1000))
12927 /* Only test the commonly used registers */
12928 static int tg3_test_registers(struct tg3 *tp)
12930 int i, is_5705, is_5750;
12931 u32 offset, read_mask, write_mask, val, save_val, read_val;
12935 #define TG3_FL_5705 0x1
12936 #define TG3_FL_NOT_5705 0x2
12937 #define TG3_FL_NOT_5788 0x4
12938 #define TG3_FL_NOT_5750 0x8
12942 /* MAC Control Registers */
12943 { MAC_MODE, TG3_FL_NOT_5705,
12944 0x00000000, 0x00ef6f8c },
12945 { MAC_MODE, TG3_FL_5705,
12946 0x00000000, 0x01ef6b8c },
12947 { MAC_STATUS, TG3_FL_NOT_5705,
12948 0x03800107, 0x00000000 },
12949 { MAC_STATUS, TG3_FL_5705,
12950 0x03800100, 0x00000000 },
12951 { MAC_ADDR_0_HIGH, 0x0000,
12952 0x00000000, 0x0000ffff },
12953 { MAC_ADDR_0_LOW, 0x0000,
12954 0x00000000, 0xffffffff },
12955 { MAC_RX_MTU_SIZE, 0x0000,
12956 0x00000000, 0x0000ffff },
12957 { MAC_TX_MODE, 0x0000,
12958 0x00000000, 0x00000070 },
12959 { MAC_TX_LENGTHS, 0x0000,
12960 0x00000000, 0x00003fff },
12961 { MAC_RX_MODE, TG3_FL_NOT_5705,
12962 0x00000000, 0x000007fc },
12963 { MAC_RX_MODE, TG3_FL_5705,
12964 0x00000000, 0x000007dc },
12965 { MAC_HASH_REG_0, 0x0000,
12966 0x00000000, 0xffffffff },
12967 { MAC_HASH_REG_1, 0x0000,
12968 0x00000000, 0xffffffff },
12969 { MAC_HASH_REG_2, 0x0000,
12970 0x00000000, 0xffffffff },
12971 { MAC_HASH_REG_3, 0x0000,
12972 0x00000000, 0xffffffff },
12974 /* Receive Data and Receive BD Initiator Control Registers. */
12975 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
12976 0x00000000, 0xffffffff },
12977 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
12978 0x00000000, 0xffffffff },
12979 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
12980 0x00000000, 0x00000003 },
12981 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
12982 0x00000000, 0xffffffff },
12983 { RCVDBDI_STD_BD+0, 0x0000,
12984 0x00000000, 0xffffffff },
12985 { RCVDBDI_STD_BD+4, 0x0000,
12986 0x00000000, 0xffffffff },
12987 { RCVDBDI_STD_BD+8, 0x0000,
12988 0x00000000, 0xffff0002 },
12989 { RCVDBDI_STD_BD+0xc, 0x0000,
12990 0x00000000, 0xffffffff },
12992 /* Receive BD Initiator Control Registers. */
12993 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
12994 0x00000000, 0xffffffff },
12995 { RCVBDI_STD_THRESH, TG3_FL_5705,
12996 0x00000000, 0x000003ff },
12997 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
12998 0x00000000, 0xffffffff },
13000 /* Host Coalescing Control Registers. */
13001 { HOSTCC_MODE, TG3_FL_NOT_5705,
13002 0x00000000, 0x00000004 },
13003 { HOSTCC_MODE, TG3_FL_5705,
13004 0x00000000, 0x000000f6 },
13005 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13006 0x00000000, 0xffffffff },
13007 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13008 0x00000000, 0x000003ff },
13009 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13010 0x00000000, 0xffffffff },
13011 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13012 0x00000000, 0x000003ff },
13013 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13014 0x00000000, 0xffffffff },
13015 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13016 0x00000000, 0x000000ff },
13017 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13018 0x00000000, 0xffffffff },
13019 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13020 0x00000000, 0x000000ff },
13021 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13022 0x00000000, 0xffffffff },
13023 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13024 0x00000000, 0xffffffff },
13025 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13026 0x00000000, 0xffffffff },
13027 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13028 0x00000000, 0x000000ff },
13029 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13030 0x00000000, 0xffffffff },
13031 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13032 0x00000000, 0x000000ff },
13033 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13034 0x00000000, 0xffffffff },
13035 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13036 0x00000000, 0xffffffff },
13037 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13038 0x00000000, 0xffffffff },
13039 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13040 0x00000000, 0xffffffff },
13041 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13042 0x00000000, 0xffffffff },
13043 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13044 0xffffffff, 0x00000000 },
13045 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13046 0xffffffff, 0x00000000 },
13048 /* Buffer Manager Control Registers. */
13049 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
13050 0x00000000, 0x007fff80 },
13051 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
13052 0x00000000, 0x007fffff },
13053 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13054 0x00000000, 0x0000003f },
13055 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13056 0x00000000, 0x000001ff },
13057 { BUFMGR_MB_HIGH_WATER, 0x0000,
13058 0x00000000, 0x000001ff },
13059 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13060 0xffffffff, 0x00000000 },
13061 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13062 0xffffffff, 0x00000000 },
13064 /* Mailbox Registers */
13065 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13066 0x00000000, 0x000001ff },
13067 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13068 0x00000000, 0x000001ff },
13069 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13070 0x00000000, 0x000007ff },
13071 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13072 0x00000000, 0x000001ff },
13074 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13077 is_5705 = is_5750 = 0;
13078 if (tg3_flag(tp, 5705_PLUS)) {
13080 if (tg3_flag(tp, 5750_PLUS))
13084 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13085 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13088 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13091 if (tg3_flag(tp, IS_5788) &&
13092 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13095 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13098 offset = (u32) reg_tbl[i].offset;
13099 read_mask = reg_tbl[i].read_mask;
13100 write_mask = reg_tbl[i].write_mask;
13102 /* Save the original register content */
13103 save_val = tr32(offset);
13105 /* Determine the read-only value. */
13106 read_val = save_val & read_mask;
13108 /* Write zero to the register, then make sure the read-only bits
13109 * are not changed and the read/write bits are all zeros.
13113 val = tr32(offset);
13115 /* Test the read-only and read/write bits. */
13116 if (((val & read_mask) != read_val) || (val & write_mask))
13119 /* Write ones to all the bits defined by RdMask and WrMask, then
13120 * make sure the read-only bits are not changed and the
13121 * read/write bits are all ones.
13123 tw32(offset, read_mask | write_mask);
13125 val = tr32(offset);
13127 /* Test the read-only bits. */
13128 if ((val & read_mask) != read_val)
13131 /* Test the read/write bits. */
13132 if ((val & write_mask) != write_mask)
13135 tw32(offset, save_val);
13141 if (netif_msg_hw(tp))
13142 netdev_err(tp->dev,
13143 "Register test failed at offset %x\n", offset);
13144 tw32(offset, save_val);
13148 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13150 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
13154 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
13155 for (j = 0; j < len; j += 4) {
13158 tg3_write_mem(tp, offset + j, test_pattern[i]);
13159 tg3_read_mem(tp, offset + j, &val);
13160 if (val != test_pattern[i])
13167 static int tg3_test_memory(struct tg3 *tp)
13169 static struct mem_entry {
13172 } mem_tbl_570x[] = {
13173 { 0x00000000, 0x00b50},
13174 { 0x00002000, 0x1c000},
13175 { 0xffffffff, 0x00000}
13176 }, mem_tbl_5705[] = {
13177 { 0x00000100, 0x0000c},
13178 { 0x00000200, 0x00008},
13179 { 0x00004000, 0x00800},
13180 { 0x00006000, 0x01000},
13181 { 0x00008000, 0x02000},
13182 { 0x00010000, 0x0e000},
13183 { 0xffffffff, 0x00000}
13184 }, mem_tbl_5755[] = {
13185 { 0x00000200, 0x00008},
13186 { 0x00004000, 0x00800},
13187 { 0x00006000, 0x00800},
13188 { 0x00008000, 0x02000},
13189 { 0x00010000, 0x0c000},
13190 { 0xffffffff, 0x00000}
13191 }, mem_tbl_5906[] = {
13192 { 0x00000200, 0x00008},
13193 { 0x00004000, 0x00400},
13194 { 0x00006000, 0x00400},
13195 { 0x00008000, 0x01000},
13196 { 0x00010000, 0x01000},
13197 { 0xffffffff, 0x00000}
13198 }, mem_tbl_5717[] = {
13199 { 0x00000200, 0x00008},
13200 { 0x00010000, 0x0a000},
13201 { 0x00020000, 0x13c00},
13202 { 0xffffffff, 0x00000}
13203 }, mem_tbl_57765[] = {
13204 { 0x00000200, 0x00008},
13205 { 0x00004000, 0x00800},
13206 { 0x00006000, 0x09800},
13207 { 0x00010000, 0x0a000},
13208 { 0xffffffff, 0x00000}
13210 struct mem_entry *mem_tbl;
13214 if (tg3_flag(tp, 5717_PLUS))
13215 mem_tbl = mem_tbl_5717;
13216 else if (tg3_flag(tp, 57765_CLASS) ||
13217 tg3_asic_rev(tp) == ASIC_REV_5762)
13218 mem_tbl = mem_tbl_57765;
13219 else if (tg3_flag(tp, 5755_PLUS))
13220 mem_tbl = mem_tbl_5755;
13221 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
13222 mem_tbl = mem_tbl_5906;
13223 else if (tg3_flag(tp, 5705_PLUS))
13224 mem_tbl = mem_tbl_5705;
13226 mem_tbl = mem_tbl_570x;
13228 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
13229 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13237 #define TG3_TSO_MSS 500
13239 #define TG3_TSO_IP_HDR_LEN 20
13240 #define TG3_TSO_TCP_HDR_LEN 20
13241 #define TG3_TSO_TCP_OPT_LEN 12
13243 static const u8 tg3_tso_header[] = {
13245 0x45, 0x00, 0x00, 0x00,
13246 0x00, 0x00, 0x40, 0x00,
13247 0x40, 0x06, 0x00, 0x00,
13248 0x0a, 0x00, 0x00, 0x01,
13249 0x0a, 0x00, 0x00, 0x02,
13250 0x0d, 0x00, 0xe0, 0x00,
13251 0x00, 0x00, 0x01, 0x00,
13252 0x00, 0x00, 0x02, 0x00,
13253 0x80, 0x10, 0x10, 0x00,
13254 0x14, 0x09, 0x00, 0x00,
13255 0x01, 0x01, 0x08, 0x0a,
13256 0x11, 0x11, 0x11, 0x11,
13257 0x11, 0x11, 0x11, 0x11,
13260 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
13262 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
13263 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
13265 struct sk_buff *skb;
13266 u8 *tx_data, *rx_data;
13268 int num_pkts, tx_len, rx_len, i, err;
13269 struct tg3_rx_buffer_desc *desc;
13270 struct tg3_napi *tnapi, *rnapi;
13271 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
13273 tnapi = &tp->napi[0];
13274 rnapi = &tp->napi[0];
13275 if (tp->irq_cnt > 1) {
13276 if (tg3_flag(tp, ENABLE_RSS))
13277 rnapi = &tp->napi[1];
13278 if (tg3_flag(tp, ENABLE_TSS))
13279 tnapi = &tp->napi[1];
13281 coal_now = tnapi->coal_now | rnapi->coal_now;
13286 skb = netdev_alloc_skb(tp->dev, tx_len);
13290 tx_data = skb_put(skb, tx_len);
13291 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13292 memset(tx_data + ETH_ALEN, 0x0, 8);
13294 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13296 if (tso_loopback) {
13297 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13299 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13300 TG3_TSO_TCP_OPT_LEN;
13302 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13303 sizeof(tg3_tso_header));
13306 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13307 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13309 /* Set the total length field in the IP header */
13310 iph->tot_len = htons((u16)(mss + hdr_len));
13312 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13313 TXD_FLAG_CPU_POST_DMA);
13315 if (tg3_flag(tp, HW_TSO_1) ||
13316 tg3_flag(tp, HW_TSO_2) ||
13317 tg3_flag(tp, HW_TSO_3)) {
13319 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13320 th = (struct tcphdr *)&tx_data[val];
13323 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13325 if (tg3_flag(tp, HW_TSO_3)) {
13326 mss |= (hdr_len & 0xc) << 12;
13327 if (hdr_len & 0x10)
13328 base_flags |= 0x00000010;
13329 base_flags |= (hdr_len & 0x3e0) << 5;
13330 } else if (tg3_flag(tp, HW_TSO_2))
13331 mss |= hdr_len << 9;
13332 else if (tg3_flag(tp, HW_TSO_1) ||
13333 tg3_asic_rev(tp) == ASIC_REV_5705) {
13334 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13336 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13339 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13342 data_off = ETH_HLEN;
13344 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13345 tx_len > VLAN_ETH_FRAME_LEN)
13346 base_flags |= TXD_FLAG_JMB_PKT;
13349 for (i = data_off; i < tx_len; i++)
13350 tx_data[i] = (u8) (i & 0xff);
13352 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13353 if (pci_dma_mapping_error(tp->pdev, map)) {
13354 dev_kfree_skb(skb);
13358 val = tnapi->tx_prod;
13359 tnapi->tx_buffers[val].skb = skb;
13360 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13362 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13367 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
13369 budget = tg3_tx_avail(tnapi);
13370 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
13371 base_flags | TXD_FLAG_END, mss, 0)) {
13372 tnapi->tx_buffers[val].skb = NULL;
13373 dev_kfree_skb(skb);
13379 /* Sync BD data before updating mailbox */
13382 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13383 tr32_mailbox(tnapi->prodmbox);
13387 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13388 for (i = 0; i < 35; i++) {
13389 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13394 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13395 rx_idx = rnapi->hw_status->idx[0].rx_producer;
13396 if ((tx_idx == tnapi->tx_prod) &&
13397 (rx_idx == (rx_start_idx + num_pkts)))
13401 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
13402 dev_kfree_skb(skb);
13404 if (tx_idx != tnapi->tx_prod)
13407 if (rx_idx != rx_start_idx + num_pkts)
13411 while (rx_idx != rx_start_idx) {
13412 desc = &rnapi->rx_rcb[rx_start_idx++];
13413 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13414 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
13416 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13417 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13420 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13423 if (!tso_loopback) {
13424 if (rx_len != tx_len)
13427 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13428 if (opaque_key != RXD_OPAQUE_RING_STD)
13431 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13434 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13435 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
13436 >> RXD_TCPCSUM_SHIFT != 0xffff) {
13440 if (opaque_key == RXD_OPAQUE_RING_STD) {
13441 rx_data = tpr->rx_std_buffers[desc_idx].data;
13442 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13444 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
13445 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
13446 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13451 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13452 PCI_DMA_FROMDEVICE);
13454 rx_data += TG3_RX_OFFSET(tp);
13455 for (i = data_off; i < rx_len; i++, val++) {
13456 if (*(rx_data + i) != (u8) (val & 0xff))
13463 /* tg3_free_rings will unmap and free the rx_data */
13468 #define TG3_STD_LOOPBACK_FAILED 1
13469 #define TG3_JMB_LOOPBACK_FAILED 2
13470 #define TG3_TSO_LOOPBACK_FAILED 4
13471 #define TG3_LOOPBACK_FAILED \
13472 (TG3_STD_LOOPBACK_FAILED | \
13473 TG3_JMB_LOOPBACK_FAILED | \
13474 TG3_TSO_LOOPBACK_FAILED)
13476 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13480 u32 jmb_pkt_sz = 9000;
13483 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13485 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13486 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13488 if (!netif_running(tp->dev)) {
13489 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13490 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13492 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13496 err = tg3_reset_hw(tp, true);
13498 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13499 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13501 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13505 if (tg3_flag(tp, ENABLE_RSS)) {
13508 /* Reroute all rx packets to the 1st queue */
13509 for (i = MAC_RSS_INDIR_TBL_0;
13510 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13514 /* HW errata - mac loopback fails in some cases on 5780.
13515 * Normal traffic and PHY loopback are not affected by
13516 * errata. Also, the MAC loopback test is deprecated for
13517 * all newer ASIC revisions.
13519 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13520 !tg3_flag(tp, CPMU_PRESENT)) {
13521 tg3_mac_loopback(tp, true);
13523 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13524 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13526 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13527 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13528 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13530 tg3_mac_loopback(tp, false);
13533 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13534 !tg3_flag(tp, USE_PHYLIB)) {
13537 tg3_phy_lpbk_set(tp, 0, false);
13539 /* Wait for link */
13540 for (i = 0; i < 100; i++) {
13541 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13546 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13547 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13548 if (tg3_flag(tp, TSO_CAPABLE) &&
13549 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13550 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
13551 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13552 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13553 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13556 tg3_phy_lpbk_set(tp, 0, true);
13558 /* All link indications report up, but the hardware
13559 * isn't really ready for about 20 msec. Double it
13564 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13565 data[TG3_EXT_LOOPB_TEST] |=
13566 TG3_STD_LOOPBACK_FAILED;
13567 if (tg3_flag(tp, TSO_CAPABLE) &&
13568 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13569 data[TG3_EXT_LOOPB_TEST] |=
13570 TG3_TSO_LOOPBACK_FAILED;
13571 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13572 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13573 data[TG3_EXT_LOOPB_TEST] |=
13574 TG3_JMB_LOOPBACK_FAILED;
13577 /* Re-enable gphy autopowerdown. */
13578 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13579 tg3_phy_toggle_apd(tp, true);
13582 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13583 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
13586 tp->phy_flags |= eee_cap;
13591 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13594 struct tg3 *tp = netdev_priv(dev);
13595 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
13597 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13598 if (tg3_power_up(tp)) {
13599 etest->flags |= ETH_TEST_FL_FAILED;
13600 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13603 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
13606 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13608 if (tg3_test_nvram(tp) != 0) {
13609 etest->flags |= ETH_TEST_FL_FAILED;
13610 data[TG3_NVRAM_TEST] = 1;
13612 if (!doextlpbk && tg3_test_link(tp)) {
13613 etest->flags |= ETH_TEST_FL_FAILED;
13614 data[TG3_LINK_TEST] = 1;
13616 if (etest->flags & ETH_TEST_FL_OFFLINE) {
13617 int err, err2 = 0, irq_sync = 0;
13619 if (netif_running(dev)) {
13621 tg3_netif_stop(tp);
13625 tg3_full_lock(tp, irq_sync);
13626 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13627 err = tg3_nvram_lock(tp);
13628 tg3_halt_cpu(tp, RX_CPU_BASE);
13629 if (!tg3_flag(tp, 5705_PLUS))
13630 tg3_halt_cpu(tp, TX_CPU_BASE);
13632 tg3_nvram_unlock(tp);
13634 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13637 if (tg3_test_registers(tp) != 0) {
13638 etest->flags |= ETH_TEST_FL_FAILED;
13639 data[TG3_REGISTER_TEST] = 1;
13642 if (tg3_test_memory(tp) != 0) {
13643 etest->flags |= ETH_TEST_FL_FAILED;
13644 data[TG3_MEMORY_TEST] = 1;
13648 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13650 if (tg3_test_loopback(tp, data, doextlpbk))
13651 etest->flags |= ETH_TEST_FL_FAILED;
13653 tg3_full_unlock(tp);
13655 if (tg3_test_interrupt(tp) != 0) {
13656 etest->flags |= ETH_TEST_FL_FAILED;
13657 data[TG3_INTERRUPT_TEST] = 1;
13660 tg3_full_lock(tp, 0);
13662 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13663 if (netif_running(dev)) {
13664 tg3_flag_set(tp, INIT_COMPLETE);
13665 err2 = tg3_restart_hw(tp, true);
13667 tg3_netif_start(tp);
13670 tg3_full_unlock(tp);
13672 if (irq_sync && !err2)
13675 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13676 tg3_power_down_prepare(tp);
13680 static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
13682 struct tg3 *tp = netdev_priv(dev);
13683 struct hwtstamp_config stmpconf;
13685 if (!tg3_flag(tp, PTP_CAPABLE))
13686 return -EOPNOTSUPP;
13688 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13691 if (stmpconf.flags)
13694 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13695 stmpconf.tx_type != HWTSTAMP_TX_OFF)
13698 switch (stmpconf.rx_filter) {
13699 case HWTSTAMP_FILTER_NONE:
13702 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13703 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13704 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13706 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13707 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13708 TG3_RX_PTP_CTL_SYNC_EVNT;
13710 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13711 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13712 TG3_RX_PTP_CTL_DELAY_REQ;
13714 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13715 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13716 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13718 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13719 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13720 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13722 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13723 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13724 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13726 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13727 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13728 TG3_RX_PTP_CTL_SYNC_EVNT;
13730 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13731 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13732 TG3_RX_PTP_CTL_SYNC_EVNT;
13734 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13735 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13736 TG3_RX_PTP_CTL_SYNC_EVNT;
13738 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13739 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13740 TG3_RX_PTP_CTL_DELAY_REQ;
13742 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13743 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13744 TG3_RX_PTP_CTL_DELAY_REQ;
13746 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13747 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13748 TG3_RX_PTP_CTL_DELAY_REQ;
13754 if (netif_running(dev) && tp->rxptpctl)
13755 tw32(TG3_RX_PTP_CTL,
13756 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13758 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13759 tg3_flag_set(tp, TX_TSTAMP_EN);
13761 tg3_flag_clear(tp, TX_TSTAMP_EN);
13763 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13767 static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13769 struct tg3 *tp = netdev_priv(dev);
13770 struct hwtstamp_config stmpconf;
13772 if (!tg3_flag(tp, PTP_CAPABLE))
13773 return -EOPNOTSUPP;
13775 stmpconf.flags = 0;
13776 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13777 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13779 switch (tp->rxptpctl) {
13781 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13783 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13784 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13786 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13787 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13789 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13790 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13792 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13793 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13795 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13796 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13798 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13799 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13801 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13802 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13804 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13805 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13807 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13808 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13810 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13811 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13813 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13814 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13816 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13817 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13824 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13828 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13830 struct mii_ioctl_data *data = if_mii(ifr);
13831 struct tg3 *tp = netdev_priv(dev);
13834 if (tg3_flag(tp, USE_PHYLIB)) {
13835 struct phy_device *phydev;
13836 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
13838 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
13839 return phy_mii_ioctl(phydev, ifr, cmd);
13844 data->phy_id = tp->phy_addr;
13847 case SIOCGMIIREG: {
13850 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13851 break; /* We have no PHY */
13853 if (!netif_running(dev))
13856 spin_lock_bh(&tp->lock);
13857 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13858 data->reg_num & 0x1f, &mii_regval);
13859 spin_unlock_bh(&tp->lock);
13861 data->val_out = mii_regval;
13867 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13868 break; /* We have no PHY */
13870 if (!netif_running(dev))
13873 spin_lock_bh(&tp->lock);
13874 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13875 data->reg_num & 0x1f, data->val_in);
13876 spin_unlock_bh(&tp->lock);
13880 case SIOCSHWTSTAMP:
13881 return tg3_hwtstamp_set(dev, ifr);
13883 case SIOCGHWTSTAMP:
13884 return tg3_hwtstamp_get(dev, ifr);
13890 return -EOPNOTSUPP;
13893 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13895 struct tg3 *tp = netdev_priv(dev);
13897 memcpy(ec, &tp->coal, sizeof(*ec));
13901 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13903 struct tg3 *tp = netdev_priv(dev);
13904 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13905 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13907 if (!tg3_flag(tp, 5705_PLUS)) {
13908 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13909 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13910 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13911 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13914 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13915 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13916 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13917 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13918 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13919 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13920 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13921 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13922 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13923 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13926 /* No rx interrupts will be generated if both are zero */
13927 if ((ec->rx_coalesce_usecs == 0) &&
13928 (ec->rx_max_coalesced_frames == 0))
13931 /* No tx interrupts will be generated if both are zero */
13932 if ((ec->tx_coalesce_usecs == 0) &&
13933 (ec->tx_max_coalesced_frames == 0))
13936 /* Only copy relevant parameters, ignore all others. */
13937 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13938 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13939 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13940 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13941 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13942 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13943 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13944 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13945 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13947 if (netif_running(dev)) {
13948 tg3_full_lock(tp, 0);
13949 __tg3_set_coalesce(tp, &tp->coal);
13950 tg3_full_unlock(tp);
13955 static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
13957 struct tg3 *tp = netdev_priv(dev);
13959 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13960 netdev_warn(tp->dev, "Board does not support EEE!\n");
13961 return -EOPNOTSUPP;
13964 if (edata->advertised != tp->eee.advertised) {
13965 netdev_warn(tp->dev,
13966 "Direct manipulation of EEE advertisement is not supported\n");
13970 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
13971 netdev_warn(tp->dev,
13972 "Maximal Tx Lpi timer supported is %#x(u)\n",
13973 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
13979 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
13980 tg3_warn_mgmt_link_flap(tp);
13982 if (netif_running(tp->dev)) {
13983 tg3_full_lock(tp, 0);
13986 tg3_full_unlock(tp);
13992 static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
13994 struct tg3 *tp = netdev_priv(dev);
13996 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13997 netdev_warn(tp->dev,
13998 "Board does not support EEE!\n");
13999 return -EOPNOTSUPP;
14006 static const struct ethtool_ops tg3_ethtool_ops = {
14007 .get_settings = tg3_get_settings,
14008 .set_settings = tg3_set_settings,
14009 .get_drvinfo = tg3_get_drvinfo,
14010 .get_regs_len = tg3_get_regs_len,
14011 .get_regs = tg3_get_regs,
14012 .get_wol = tg3_get_wol,
14013 .set_wol = tg3_set_wol,
14014 .get_msglevel = tg3_get_msglevel,
14015 .set_msglevel = tg3_set_msglevel,
14016 .nway_reset = tg3_nway_reset,
14017 .get_link = ethtool_op_get_link,
14018 .get_eeprom_len = tg3_get_eeprom_len,
14019 .get_eeprom = tg3_get_eeprom,
14020 .set_eeprom = tg3_set_eeprom,
14021 .get_ringparam = tg3_get_ringparam,
14022 .set_ringparam = tg3_set_ringparam,
14023 .get_pauseparam = tg3_get_pauseparam,
14024 .set_pauseparam = tg3_set_pauseparam,
14025 .self_test = tg3_self_test,
14026 .get_strings = tg3_get_strings,
14027 .set_phys_id = tg3_set_phys_id,
14028 .get_ethtool_stats = tg3_get_ethtool_stats,
14029 .get_coalesce = tg3_get_coalesce,
14030 .set_coalesce = tg3_set_coalesce,
14031 .get_sset_count = tg3_get_sset_count,
14032 .get_rxnfc = tg3_get_rxnfc,
14033 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
14034 .get_rxfh_indir = tg3_get_rxfh_indir,
14035 .set_rxfh_indir = tg3_set_rxfh_indir,
14036 .get_channels = tg3_get_channels,
14037 .set_channels = tg3_set_channels,
14038 .get_ts_info = tg3_get_ts_info,
14039 .get_eee = tg3_get_eee,
14040 .set_eee = tg3_set_eee,
14043 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
14044 struct rtnl_link_stats64 *stats)
14046 struct tg3 *tp = netdev_priv(dev);
14048 spin_lock_bh(&tp->lock);
14049 if (!tp->hw_stats) {
14050 spin_unlock_bh(&tp->lock);
14051 return &tp->net_stats_prev;
14054 tg3_get_nstats(tp, stats);
14055 spin_unlock_bh(&tp->lock);
14060 static void tg3_set_rx_mode(struct net_device *dev)
14062 struct tg3 *tp = netdev_priv(dev);
14064 if (!netif_running(dev))
14067 tg3_full_lock(tp, 0);
14068 __tg3_set_rx_mode(dev);
14069 tg3_full_unlock(tp);
14072 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14075 dev->mtu = new_mtu;
14077 if (new_mtu > ETH_DATA_LEN) {
14078 if (tg3_flag(tp, 5780_CLASS)) {
14079 netdev_update_features(dev);
14080 tg3_flag_clear(tp, TSO_CAPABLE);
14082 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14085 if (tg3_flag(tp, 5780_CLASS)) {
14086 tg3_flag_set(tp, TSO_CAPABLE);
14087 netdev_update_features(dev);
14089 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14093 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14095 struct tg3 *tp = netdev_priv(dev);
14097 bool reset_phy = false;
14099 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
14102 if (!netif_running(dev)) {
14103 /* We'll just catch it later when the
14106 tg3_set_mtu(dev, tp, new_mtu);
14112 tg3_netif_stop(tp);
14114 tg3_set_mtu(dev, tp, new_mtu);
14116 tg3_full_lock(tp, 1);
14118 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14120 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14121 * breaks all requests to 256 bytes.
14123 if (tg3_asic_rev(tp) == ASIC_REV_57766)
14126 err = tg3_restart_hw(tp, reset_phy);
14129 tg3_netif_start(tp);
14131 tg3_full_unlock(tp);
14139 static const struct net_device_ops tg3_netdev_ops = {
14140 .ndo_open = tg3_open,
14141 .ndo_stop = tg3_close,
14142 .ndo_start_xmit = tg3_start_xmit,
14143 .ndo_get_stats64 = tg3_get_stats64,
14144 .ndo_validate_addr = eth_validate_addr,
14145 .ndo_set_rx_mode = tg3_set_rx_mode,
14146 .ndo_set_mac_address = tg3_set_mac_addr,
14147 .ndo_do_ioctl = tg3_ioctl,
14148 .ndo_tx_timeout = tg3_tx_timeout,
14149 .ndo_change_mtu = tg3_change_mtu,
14150 .ndo_fix_features = tg3_fix_features,
14151 .ndo_set_features = tg3_set_features,
14152 #ifdef CONFIG_NET_POLL_CONTROLLER
14153 .ndo_poll_controller = tg3_poll_controller,
14157 static void tg3_get_eeprom_size(struct tg3 *tp)
14159 u32 cursize, val, magic;
14161 tp->nvram_size = EEPROM_CHIP_SIZE;
14163 if (tg3_nvram_read(tp, 0, &magic) != 0)
14166 if ((magic != TG3_EEPROM_MAGIC) &&
14167 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14168 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
14172 * Size the chip by reading offsets at increasing powers of two.
14173 * When we encounter our validation signature, we know the addressing
14174 * has wrapped around, and thus have our chip size.
14178 while (cursize < tp->nvram_size) {
14179 if (tg3_nvram_read(tp, cursize, &val) != 0)
14188 tp->nvram_size = cursize;
14191 static void tg3_get_nvram_size(struct tg3 *tp)
14195 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14198 /* Selfboot format */
14199 if (val != TG3_EEPROM_MAGIC) {
14200 tg3_get_eeprom_size(tp);
14204 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14206 /* This is confusing. We want to operate on the
14207 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14208 * call will read from NVRAM and byteswap the data
14209 * according to the byteswapping settings for all
14210 * other register accesses. This ensures the data we
14211 * want will always reside in the lower 16-bits.
14212 * However, the data in NVRAM is in LE format, which
14213 * means the data from the NVRAM read will always be
14214 * opposite the endianness of the CPU. The 16-bit
14215 * byteswap then brings the data to CPU endianness.
14217 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14221 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14224 static void tg3_get_nvram_info(struct tg3 *tp)
14228 nvcfg1 = tr32(NVRAM_CFG1);
14229 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
14230 tg3_flag_set(tp, FLASH);
14232 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14233 tw32(NVRAM_CFG1, nvcfg1);
14236 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
14237 tg3_flag(tp, 5780_CLASS)) {
14238 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
14239 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14240 tp->nvram_jedecnum = JEDEC_ATMEL;
14241 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14242 tg3_flag_set(tp, NVRAM_BUFFERED);
14244 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14245 tp->nvram_jedecnum = JEDEC_ATMEL;
14246 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14248 case FLASH_VENDOR_ATMEL_EEPROM:
14249 tp->nvram_jedecnum = JEDEC_ATMEL;
14250 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14251 tg3_flag_set(tp, NVRAM_BUFFERED);
14253 case FLASH_VENDOR_ST:
14254 tp->nvram_jedecnum = JEDEC_ST;
14255 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
14256 tg3_flag_set(tp, NVRAM_BUFFERED);
14258 case FLASH_VENDOR_SAIFUN:
14259 tp->nvram_jedecnum = JEDEC_SAIFUN;
14260 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14262 case FLASH_VENDOR_SST_SMALL:
14263 case FLASH_VENDOR_SST_LARGE:
14264 tp->nvram_jedecnum = JEDEC_SST;
14265 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14269 tp->nvram_jedecnum = JEDEC_ATMEL;
14270 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14271 tg3_flag_set(tp, NVRAM_BUFFERED);
14275 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
14277 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14278 case FLASH_5752PAGE_SIZE_256:
14279 tp->nvram_pagesize = 256;
14281 case FLASH_5752PAGE_SIZE_512:
14282 tp->nvram_pagesize = 512;
14284 case FLASH_5752PAGE_SIZE_1K:
14285 tp->nvram_pagesize = 1024;
14287 case FLASH_5752PAGE_SIZE_2K:
14288 tp->nvram_pagesize = 2048;
14290 case FLASH_5752PAGE_SIZE_4K:
14291 tp->nvram_pagesize = 4096;
14293 case FLASH_5752PAGE_SIZE_264:
14294 tp->nvram_pagesize = 264;
14296 case FLASH_5752PAGE_SIZE_528:
14297 tp->nvram_pagesize = 528;
14302 static void tg3_get_5752_nvram_info(struct tg3 *tp)
14306 nvcfg1 = tr32(NVRAM_CFG1);
14308 /* NVRAM protection for TPM */
14309 if (nvcfg1 & (1 << 27))
14310 tg3_flag_set(tp, PROTECTED_NVRAM);
14312 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14313 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14314 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14315 tp->nvram_jedecnum = JEDEC_ATMEL;
14316 tg3_flag_set(tp, NVRAM_BUFFERED);
14318 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14319 tp->nvram_jedecnum = JEDEC_ATMEL;
14320 tg3_flag_set(tp, NVRAM_BUFFERED);
14321 tg3_flag_set(tp, FLASH);
14323 case FLASH_5752VENDOR_ST_M45PE10:
14324 case FLASH_5752VENDOR_ST_M45PE20:
14325 case FLASH_5752VENDOR_ST_M45PE40:
14326 tp->nvram_jedecnum = JEDEC_ST;
14327 tg3_flag_set(tp, NVRAM_BUFFERED);
14328 tg3_flag_set(tp, FLASH);
14332 if (tg3_flag(tp, FLASH)) {
14333 tg3_nvram_get_pagesize(tp, nvcfg1);
14335 /* For eeprom, set pagesize to maximum eeprom size */
14336 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14338 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14339 tw32(NVRAM_CFG1, nvcfg1);
14343 static void tg3_get_5755_nvram_info(struct tg3 *tp)
14345 u32 nvcfg1, protect = 0;
14347 nvcfg1 = tr32(NVRAM_CFG1);
14349 /* NVRAM protection for TPM */
14350 if (nvcfg1 & (1 << 27)) {
14351 tg3_flag_set(tp, PROTECTED_NVRAM);
14355 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14357 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14358 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14359 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14360 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14361 tp->nvram_jedecnum = JEDEC_ATMEL;
14362 tg3_flag_set(tp, NVRAM_BUFFERED);
14363 tg3_flag_set(tp, FLASH);
14364 tp->nvram_pagesize = 264;
14365 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14366 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14367 tp->nvram_size = (protect ? 0x3e200 :
14368 TG3_NVRAM_SIZE_512KB);
14369 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14370 tp->nvram_size = (protect ? 0x1f200 :
14371 TG3_NVRAM_SIZE_256KB);
14373 tp->nvram_size = (protect ? 0x1f200 :
14374 TG3_NVRAM_SIZE_128KB);
14376 case FLASH_5752VENDOR_ST_M45PE10:
14377 case FLASH_5752VENDOR_ST_M45PE20:
14378 case FLASH_5752VENDOR_ST_M45PE40:
14379 tp->nvram_jedecnum = JEDEC_ST;
14380 tg3_flag_set(tp, NVRAM_BUFFERED);
14381 tg3_flag_set(tp, FLASH);
14382 tp->nvram_pagesize = 256;
14383 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14384 tp->nvram_size = (protect ?
14385 TG3_NVRAM_SIZE_64KB :
14386 TG3_NVRAM_SIZE_128KB);
14387 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14388 tp->nvram_size = (protect ?
14389 TG3_NVRAM_SIZE_64KB :
14390 TG3_NVRAM_SIZE_256KB);
14392 tp->nvram_size = (protect ?
14393 TG3_NVRAM_SIZE_128KB :
14394 TG3_NVRAM_SIZE_512KB);
14399 static void tg3_get_5787_nvram_info(struct tg3 *tp)
14403 nvcfg1 = tr32(NVRAM_CFG1);
14405 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14406 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14407 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14408 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14409 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14410 tp->nvram_jedecnum = JEDEC_ATMEL;
14411 tg3_flag_set(tp, NVRAM_BUFFERED);
14412 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14414 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14415 tw32(NVRAM_CFG1, nvcfg1);
14417 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14418 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14419 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14420 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14421 tp->nvram_jedecnum = JEDEC_ATMEL;
14422 tg3_flag_set(tp, NVRAM_BUFFERED);
14423 tg3_flag_set(tp, FLASH);
14424 tp->nvram_pagesize = 264;
14426 case FLASH_5752VENDOR_ST_M45PE10:
14427 case FLASH_5752VENDOR_ST_M45PE20:
14428 case FLASH_5752VENDOR_ST_M45PE40:
14429 tp->nvram_jedecnum = JEDEC_ST;
14430 tg3_flag_set(tp, NVRAM_BUFFERED);
14431 tg3_flag_set(tp, FLASH);
14432 tp->nvram_pagesize = 256;
14437 static void tg3_get_5761_nvram_info(struct tg3 *tp)
14439 u32 nvcfg1, protect = 0;
14441 nvcfg1 = tr32(NVRAM_CFG1);
14443 /* NVRAM protection for TPM */
14444 if (nvcfg1 & (1 << 27)) {
14445 tg3_flag_set(tp, PROTECTED_NVRAM);
14449 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14451 case FLASH_5761VENDOR_ATMEL_ADB021D:
14452 case FLASH_5761VENDOR_ATMEL_ADB041D:
14453 case FLASH_5761VENDOR_ATMEL_ADB081D:
14454 case FLASH_5761VENDOR_ATMEL_ADB161D:
14455 case FLASH_5761VENDOR_ATMEL_MDB021D:
14456 case FLASH_5761VENDOR_ATMEL_MDB041D:
14457 case FLASH_5761VENDOR_ATMEL_MDB081D:
14458 case FLASH_5761VENDOR_ATMEL_MDB161D:
14459 tp->nvram_jedecnum = JEDEC_ATMEL;
14460 tg3_flag_set(tp, NVRAM_BUFFERED);
14461 tg3_flag_set(tp, FLASH);
14462 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14463 tp->nvram_pagesize = 256;
14465 case FLASH_5761VENDOR_ST_A_M45PE20:
14466 case FLASH_5761VENDOR_ST_A_M45PE40:
14467 case FLASH_5761VENDOR_ST_A_M45PE80:
14468 case FLASH_5761VENDOR_ST_A_M45PE16:
14469 case FLASH_5761VENDOR_ST_M_M45PE20:
14470 case FLASH_5761VENDOR_ST_M_M45PE40:
14471 case FLASH_5761VENDOR_ST_M_M45PE80:
14472 case FLASH_5761VENDOR_ST_M_M45PE16:
14473 tp->nvram_jedecnum = JEDEC_ST;
14474 tg3_flag_set(tp, NVRAM_BUFFERED);
14475 tg3_flag_set(tp, FLASH);
14476 tp->nvram_pagesize = 256;
14481 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14484 case FLASH_5761VENDOR_ATMEL_ADB161D:
14485 case FLASH_5761VENDOR_ATMEL_MDB161D:
14486 case FLASH_5761VENDOR_ST_A_M45PE16:
14487 case FLASH_5761VENDOR_ST_M_M45PE16:
14488 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14490 case FLASH_5761VENDOR_ATMEL_ADB081D:
14491 case FLASH_5761VENDOR_ATMEL_MDB081D:
14492 case FLASH_5761VENDOR_ST_A_M45PE80:
14493 case FLASH_5761VENDOR_ST_M_M45PE80:
14494 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14496 case FLASH_5761VENDOR_ATMEL_ADB041D:
14497 case FLASH_5761VENDOR_ATMEL_MDB041D:
14498 case FLASH_5761VENDOR_ST_A_M45PE40:
14499 case FLASH_5761VENDOR_ST_M_M45PE40:
14500 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14502 case FLASH_5761VENDOR_ATMEL_ADB021D:
14503 case FLASH_5761VENDOR_ATMEL_MDB021D:
14504 case FLASH_5761VENDOR_ST_A_M45PE20:
14505 case FLASH_5761VENDOR_ST_M_M45PE20:
14506 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14512 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14514 tp->nvram_jedecnum = JEDEC_ATMEL;
14515 tg3_flag_set(tp, NVRAM_BUFFERED);
14516 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14519 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14523 nvcfg1 = tr32(NVRAM_CFG1);
14525 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14526 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14527 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14528 tp->nvram_jedecnum = JEDEC_ATMEL;
14529 tg3_flag_set(tp, NVRAM_BUFFERED);
14530 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14532 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14533 tw32(NVRAM_CFG1, nvcfg1);
14535 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14536 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14537 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14538 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14539 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14540 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14541 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14542 tp->nvram_jedecnum = JEDEC_ATMEL;
14543 tg3_flag_set(tp, NVRAM_BUFFERED);
14544 tg3_flag_set(tp, FLASH);
14546 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14547 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14548 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14549 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14550 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14552 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14553 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14554 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14556 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14557 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14558 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14562 case FLASH_5752VENDOR_ST_M45PE10:
14563 case FLASH_5752VENDOR_ST_M45PE20:
14564 case FLASH_5752VENDOR_ST_M45PE40:
14565 tp->nvram_jedecnum = JEDEC_ST;
14566 tg3_flag_set(tp, NVRAM_BUFFERED);
14567 tg3_flag_set(tp, FLASH);
14569 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14570 case FLASH_5752VENDOR_ST_M45PE10:
14571 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14573 case FLASH_5752VENDOR_ST_M45PE20:
14574 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14576 case FLASH_5752VENDOR_ST_M45PE40:
14577 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14582 tg3_flag_set(tp, NO_NVRAM);
14586 tg3_nvram_get_pagesize(tp, nvcfg1);
14587 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14588 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14592 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14596 nvcfg1 = tr32(NVRAM_CFG1);
14598 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14599 case FLASH_5717VENDOR_ATMEL_EEPROM:
14600 case FLASH_5717VENDOR_MICRO_EEPROM:
14601 tp->nvram_jedecnum = JEDEC_ATMEL;
14602 tg3_flag_set(tp, NVRAM_BUFFERED);
14603 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14605 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14606 tw32(NVRAM_CFG1, nvcfg1);
14608 case FLASH_5717VENDOR_ATMEL_MDB011D:
14609 case FLASH_5717VENDOR_ATMEL_ADB011B:
14610 case FLASH_5717VENDOR_ATMEL_ADB011D:
14611 case FLASH_5717VENDOR_ATMEL_MDB021D:
14612 case FLASH_5717VENDOR_ATMEL_ADB021B:
14613 case FLASH_5717VENDOR_ATMEL_ADB021D:
14614 case FLASH_5717VENDOR_ATMEL_45USPT:
14615 tp->nvram_jedecnum = JEDEC_ATMEL;
14616 tg3_flag_set(tp, NVRAM_BUFFERED);
14617 tg3_flag_set(tp, FLASH);
14619 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14620 case FLASH_5717VENDOR_ATMEL_MDB021D:
14621 /* Detect size with tg3_nvram_get_size() */
14623 case FLASH_5717VENDOR_ATMEL_ADB021B:
14624 case FLASH_5717VENDOR_ATMEL_ADB021D:
14625 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14628 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14632 case FLASH_5717VENDOR_ST_M_M25PE10:
14633 case FLASH_5717VENDOR_ST_A_M25PE10:
14634 case FLASH_5717VENDOR_ST_M_M45PE10:
14635 case FLASH_5717VENDOR_ST_A_M45PE10:
14636 case FLASH_5717VENDOR_ST_M_M25PE20:
14637 case FLASH_5717VENDOR_ST_A_M25PE20:
14638 case FLASH_5717VENDOR_ST_M_M45PE20:
14639 case FLASH_5717VENDOR_ST_A_M45PE20:
14640 case FLASH_5717VENDOR_ST_25USPT:
14641 case FLASH_5717VENDOR_ST_45USPT:
14642 tp->nvram_jedecnum = JEDEC_ST;
14643 tg3_flag_set(tp, NVRAM_BUFFERED);
14644 tg3_flag_set(tp, FLASH);
14646 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14647 case FLASH_5717VENDOR_ST_M_M25PE20:
14648 case FLASH_5717VENDOR_ST_M_M45PE20:
14649 /* Detect size with tg3_nvram_get_size() */
14651 case FLASH_5717VENDOR_ST_A_M25PE20:
14652 case FLASH_5717VENDOR_ST_A_M45PE20:
14653 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14656 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14661 tg3_flag_set(tp, NO_NVRAM);
14665 tg3_nvram_get_pagesize(tp, nvcfg1);
14666 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14667 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14670 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14672 u32 nvcfg1, nvmpinstrp;
14674 nvcfg1 = tr32(NVRAM_CFG1);
14675 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14677 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14678 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14679 tg3_flag_set(tp, NO_NVRAM);
14683 switch (nvmpinstrp) {
14684 case FLASH_5762_EEPROM_HD:
14685 nvmpinstrp = FLASH_5720_EEPROM_HD;
14687 case FLASH_5762_EEPROM_LD:
14688 nvmpinstrp = FLASH_5720_EEPROM_LD;
14690 case FLASH_5720VENDOR_M_ST_M45PE20:
14691 /* This pinstrap supports multiple sizes, so force it
14692 * to read the actual size from location 0xf0.
14694 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14699 switch (nvmpinstrp) {
14700 case FLASH_5720_EEPROM_HD:
14701 case FLASH_5720_EEPROM_LD:
14702 tp->nvram_jedecnum = JEDEC_ATMEL;
14703 tg3_flag_set(tp, NVRAM_BUFFERED);
14705 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14706 tw32(NVRAM_CFG1, nvcfg1);
14707 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14708 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14710 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14712 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14713 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14714 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14715 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14716 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14717 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14718 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14719 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14720 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14721 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14722 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14723 case FLASH_5720VENDOR_ATMEL_45USPT:
14724 tp->nvram_jedecnum = JEDEC_ATMEL;
14725 tg3_flag_set(tp, NVRAM_BUFFERED);
14726 tg3_flag_set(tp, FLASH);
14728 switch (nvmpinstrp) {
14729 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14730 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14731 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14732 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14734 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14735 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14736 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14737 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14739 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14740 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14741 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14744 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14745 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14749 case FLASH_5720VENDOR_M_ST_M25PE10:
14750 case FLASH_5720VENDOR_M_ST_M45PE10:
14751 case FLASH_5720VENDOR_A_ST_M25PE10:
14752 case FLASH_5720VENDOR_A_ST_M45PE10:
14753 case FLASH_5720VENDOR_M_ST_M25PE20:
14754 case FLASH_5720VENDOR_M_ST_M45PE20:
14755 case FLASH_5720VENDOR_A_ST_M25PE20:
14756 case FLASH_5720VENDOR_A_ST_M45PE20:
14757 case FLASH_5720VENDOR_M_ST_M25PE40:
14758 case FLASH_5720VENDOR_M_ST_M45PE40:
14759 case FLASH_5720VENDOR_A_ST_M25PE40:
14760 case FLASH_5720VENDOR_A_ST_M45PE40:
14761 case FLASH_5720VENDOR_M_ST_M25PE80:
14762 case FLASH_5720VENDOR_M_ST_M45PE80:
14763 case FLASH_5720VENDOR_A_ST_M25PE80:
14764 case FLASH_5720VENDOR_A_ST_M45PE80:
14765 case FLASH_5720VENDOR_ST_25USPT:
14766 case FLASH_5720VENDOR_ST_45USPT:
14767 tp->nvram_jedecnum = JEDEC_ST;
14768 tg3_flag_set(tp, NVRAM_BUFFERED);
14769 tg3_flag_set(tp, FLASH);
14771 switch (nvmpinstrp) {
14772 case FLASH_5720VENDOR_M_ST_M25PE20:
14773 case FLASH_5720VENDOR_M_ST_M45PE20:
14774 case FLASH_5720VENDOR_A_ST_M25PE20:
14775 case FLASH_5720VENDOR_A_ST_M45PE20:
14776 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14778 case FLASH_5720VENDOR_M_ST_M25PE40:
14779 case FLASH_5720VENDOR_M_ST_M45PE40:
14780 case FLASH_5720VENDOR_A_ST_M25PE40:
14781 case FLASH_5720VENDOR_A_ST_M45PE40:
14782 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14784 case FLASH_5720VENDOR_M_ST_M25PE80:
14785 case FLASH_5720VENDOR_M_ST_M45PE80:
14786 case FLASH_5720VENDOR_A_ST_M25PE80:
14787 case FLASH_5720VENDOR_A_ST_M45PE80:
14788 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14791 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14792 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14797 tg3_flag_set(tp, NO_NVRAM);
14801 tg3_nvram_get_pagesize(tp, nvcfg1);
14802 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14803 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14805 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14808 if (tg3_nvram_read(tp, 0, &val))
14811 if (val != TG3_EEPROM_MAGIC &&
14812 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14813 tg3_flag_set(tp, NO_NVRAM);
14817 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
14818 static void tg3_nvram_init(struct tg3 *tp)
14820 if (tg3_flag(tp, IS_SSB_CORE)) {
14821 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14822 tg3_flag_clear(tp, NVRAM);
14823 tg3_flag_clear(tp, NVRAM_BUFFERED);
14824 tg3_flag_set(tp, NO_NVRAM);
14828 tw32_f(GRC_EEPROM_ADDR,
14829 (EEPROM_ADDR_FSM_RESET |
14830 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14831 EEPROM_ADDR_CLKPERD_SHIFT)));
14835 /* Enable seeprom accesses. */
14836 tw32_f(GRC_LOCAL_CTRL,
14837 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14840 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14841 tg3_asic_rev(tp) != ASIC_REV_5701) {
14842 tg3_flag_set(tp, NVRAM);
14844 if (tg3_nvram_lock(tp)) {
14845 netdev_warn(tp->dev,
14846 "Cannot get nvram lock, %s failed\n",
14850 tg3_enable_nvram_access(tp);
14852 tp->nvram_size = 0;
14854 if (tg3_asic_rev(tp) == ASIC_REV_5752)
14855 tg3_get_5752_nvram_info(tp);
14856 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
14857 tg3_get_5755_nvram_info(tp);
14858 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14859 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14860 tg3_asic_rev(tp) == ASIC_REV_5785)
14861 tg3_get_5787_nvram_info(tp);
14862 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
14863 tg3_get_5761_nvram_info(tp);
14864 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
14865 tg3_get_5906_nvram_info(tp);
14866 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
14867 tg3_flag(tp, 57765_CLASS))
14868 tg3_get_57780_nvram_info(tp);
14869 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14870 tg3_asic_rev(tp) == ASIC_REV_5719)
14871 tg3_get_5717_nvram_info(tp);
14872 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14873 tg3_asic_rev(tp) == ASIC_REV_5762)
14874 tg3_get_5720_nvram_info(tp);
14876 tg3_get_nvram_info(tp);
14878 if (tp->nvram_size == 0)
14879 tg3_get_nvram_size(tp);
14881 tg3_disable_nvram_access(tp);
14882 tg3_nvram_unlock(tp);
14885 tg3_flag_clear(tp, NVRAM);
14886 tg3_flag_clear(tp, NVRAM_BUFFERED);
14888 tg3_get_eeprom_size(tp);
14892 struct subsys_tbl_ent {
14893 u16 subsys_vendor, subsys_devid;
14897 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
14898 /* Broadcom boards. */
14899 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14900 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
14901 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14902 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
14903 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14904 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
14905 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14906 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14907 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14908 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
14909 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14910 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
14911 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14912 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14913 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14914 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
14915 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14916 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
14917 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14918 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
14919 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14920 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
14923 { TG3PCI_SUBVENDOR_ID_3COM,
14924 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
14925 { TG3PCI_SUBVENDOR_ID_3COM,
14926 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
14927 { TG3PCI_SUBVENDOR_ID_3COM,
14928 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
14929 { TG3PCI_SUBVENDOR_ID_3COM,
14930 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
14931 { TG3PCI_SUBVENDOR_ID_3COM,
14932 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
14935 { TG3PCI_SUBVENDOR_ID_DELL,
14936 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
14937 { TG3PCI_SUBVENDOR_ID_DELL,
14938 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
14939 { TG3PCI_SUBVENDOR_ID_DELL,
14940 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
14941 { TG3PCI_SUBVENDOR_ID_DELL,
14942 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
14944 /* Compaq boards. */
14945 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14946 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
14947 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14948 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
14949 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14950 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14951 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14952 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
14953 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14954 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
14957 { TG3PCI_SUBVENDOR_ID_IBM,
14958 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
14961 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
14965 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
14966 if ((subsys_id_to_phy_id[i].subsys_vendor ==
14967 tp->pdev->subsystem_vendor) &&
14968 (subsys_id_to_phy_id[i].subsys_devid ==
14969 tp->pdev->subsystem_device))
14970 return &subsys_id_to_phy_id[i];
14975 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
14979 tp->phy_id = TG3_PHY_ID_INVALID;
14980 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14982 /* Assume an onboard device and WOL capable by default. */
14983 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14984 tg3_flag_set(tp, WOL_CAP);
14986 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
14987 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
14988 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14989 tg3_flag_set(tp, IS_NIC);
14991 val = tr32(VCPU_CFGSHDW);
14992 if (val & VCPU_CFGSHDW_ASPM_DBNC)
14993 tg3_flag_set(tp, ASPM_WORKAROUND);
14994 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
14995 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
14996 tg3_flag_set(tp, WOL_ENABLE);
14997 device_set_wakeup_enable(&tp->pdev->dev, true);
15002 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15003 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15004 u32 nic_cfg, led_cfg;
15005 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15006 u32 nic_phy_id, ver, eeprom_phy_id;
15007 int eeprom_phy_serdes = 0;
15009 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15010 tp->nic_sram_data_cfg = nic_cfg;
15012 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15013 ver >>= NIC_SRAM_DATA_VER_SHIFT;
15014 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15015 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15016 tg3_asic_rev(tp) != ASIC_REV_5703 &&
15017 (ver > 0) && (ver < 0x100))
15018 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15020 if (tg3_asic_rev(tp) == ASIC_REV_5785)
15021 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15023 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15024 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15025 tg3_asic_rev(tp) == ASIC_REV_5720)
15026 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15028 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15029 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15030 eeprom_phy_serdes = 1;
15032 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15033 if (nic_phy_id != 0) {
15034 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15035 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15037 eeprom_phy_id = (id1 >> 16) << 10;
15038 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15039 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15043 tp->phy_id = eeprom_phy_id;
15044 if (eeprom_phy_serdes) {
15045 if (!tg3_flag(tp, 5705_PLUS))
15046 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15048 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
15051 if (tg3_flag(tp, 5750_PLUS))
15052 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15053 SHASTA_EXT_LED_MODE_MASK);
15055 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15059 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15060 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15063 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15064 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15067 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15068 tp->led_ctrl = LED_CTRL_MODE_MAC;
15070 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15071 * read on some older 5700/5701 bootcode.
15073 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15074 tg3_asic_rev(tp) == ASIC_REV_5701)
15075 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15079 case SHASTA_EXT_LED_SHARED:
15080 tp->led_ctrl = LED_CTRL_MODE_SHARED;
15081 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15082 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
15083 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15084 LED_CTRL_MODE_PHY_2);
15086 if (tg3_flag(tp, 5717_PLUS) ||
15087 tg3_asic_rev(tp) == ASIC_REV_5762)
15088 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15089 LED_CTRL_BLINK_RATE_MASK;
15093 case SHASTA_EXT_LED_MAC:
15094 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15097 case SHASTA_EXT_LED_COMBO:
15098 tp->led_ctrl = LED_CTRL_MODE_COMBO;
15099 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
15100 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15101 LED_CTRL_MODE_PHY_2);
15106 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15107 tg3_asic_rev(tp) == ASIC_REV_5701) &&
15108 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15109 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15111 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
15112 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15114 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
15115 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15116 if ((tp->pdev->subsystem_vendor ==
15117 PCI_VENDOR_ID_ARIMA) &&
15118 (tp->pdev->subsystem_device == 0x205a ||
15119 tp->pdev->subsystem_device == 0x2063))
15120 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15122 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15123 tg3_flag_set(tp, IS_NIC);
15126 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
15127 tg3_flag_set(tp, ENABLE_ASF);
15128 if (tg3_flag(tp, 5750_PLUS))
15129 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
15132 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
15133 tg3_flag(tp, 5750_PLUS))
15134 tg3_flag_set(tp, ENABLE_APE);
15136 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
15137 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
15138 tg3_flag_clear(tp, WOL_CAP);
15140 if (tg3_flag(tp, WOL_CAP) &&
15141 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
15142 tg3_flag_set(tp, WOL_ENABLE);
15143 device_set_wakeup_enable(&tp->pdev->dev, true);
15146 if (cfg2 & (1 << 17))
15147 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
15149 /* serdes signal pre-emphasis in register 0x590 set by */
15150 /* bootcode if bit 18 is set */
15151 if (cfg2 & (1 << 18))
15152 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
15154 if ((tg3_flag(tp, 57765_PLUS) ||
15155 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15156 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
15157 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
15158 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
15160 if (tg3_flag(tp, PCI_EXPRESS)) {
15163 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
15164 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15165 !tg3_flag(tp, 57765_PLUS) &&
15166 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
15167 tg3_flag_set(tp, ASPM_WORKAROUND);
15168 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15169 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15170 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15171 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
15174 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
15175 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
15176 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
15177 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
15178 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
15179 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
15181 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15182 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
15185 if (tg3_flag(tp, WOL_CAP))
15186 device_set_wakeup_enable(&tp->pdev->dev,
15187 tg3_flag(tp, WOL_ENABLE));
15189 device_set_wakeup_capable(&tp->pdev->dev, false);
15192 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15195 u32 val2, off = offset * 8;
15197 err = tg3_nvram_lock(tp);
15201 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15202 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15203 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15204 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15207 for (i = 0; i < 100; i++) {
15208 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15209 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15210 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15216 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15218 tg3_nvram_unlock(tp);
15219 if (val2 & APE_OTP_STATUS_CMD_DONE)
15225 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
15230 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15231 tw32(OTP_CTRL, cmd);
15233 /* Wait for up to 1 ms for command to execute. */
15234 for (i = 0; i < 100; i++) {
15235 val = tr32(OTP_STATUS);
15236 if (val & OTP_STATUS_CMD_DONE)
15241 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15244 /* Read the gphy configuration from the OTP region of the chip. The gphy
15245 * configuration is a 32-bit value that straddles the alignment boundary.
15246 * We do two 32-bit reads and then shift and merge the results.
15248 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
15250 u32 bhalf_otp, thalf_otp;
15252 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15254 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15257 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15259 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15262 thalf_otp = tr32(OTP_READ_DATA);
15264 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15266 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15269 bhalf_otp = tr32(OTP_READ_DATA);
15271 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15274 static void tg3_phy_init_link_config(struct tg3 *tp)
15276 u32 adv = ADVERTISED_Autoneg;
15278 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15279 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15280 adv |= ADVERTISED_1000baseT_Half;
15281 adv |= ADVERTISED_1000baseT_Full;
15284 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15285 adv |= ADVERTISED_100baseT_Half |
15286 ADVERTISED_100baseT_Full |
15287 ADVERTISED_10baseT_Half |
15288 ADVERTISED_10baseT_Full |
15291 adv |= ADVERTISED_FIBRE;
15293 tp->link_config.advertising = adv;
15294 tp->link_config.speed = SPEED_UNKNOWN;
15295 tp->link_config.duplex = DUPLEX_UNKNOWN;
15296 tp->link_config.autoneg = AUTONEG_ENABLE;
15297 tp->link_config.active_speed = SPEED_UNKNOWN;
15298 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
15303 static int tg3_phy_probe(struct tg3 *tp)
15305 u32 hw_phy_id_1, hw_phy_id_2;
15306 u32 hw_phy_id, hw_phy_id_masked;
15309 /* flow control autonegotiation is default behavior */
15310 tg3_flag_set(tp, PAUSE_AUTONEG);
15311 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15313 if (tg3_flag(tp, ENABLE_APE)) {
15314 switch (tp->pci_fn) {
15316 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15319 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15322 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15325 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15330 if (!tg3_flag(tp, ENABLE_ASF) &&
15331 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15332 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15333 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15334 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15336 if (tg3_flag(tp, USE_PHYLIB))
15337 return tg3_phy_init(tp);
15339 /* Reading the PHY ID register can conflict with ASF
15340 * firmware access to the PHY hardware.
15343 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
15344 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
15346 /* Now read the physical PHY_ID from the chip and verify
15347 * that it is sane. If it doesn't look good, we fall back
15348 * to either the hard-coded table based PHY_ID and failing
15349 * that the value found in the eeprom area.
15351 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15352 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15354 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15355 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15356 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15358 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
15361 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
15362 tp->phy_id = hw_phy_id;
15363 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
15364 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15366 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
15368 if (tp->phy_id != TG3_PHY_ID_INVALID) {
15369 /* Do nothing, phy ID already set up in
15370 * tg3_get_eeprom_hw_cfg().
15373 struct subsys_tbl_ent *p;
15375 /* No eeprom signature? Try the hardcoded
15376 * subsys device table.
15378 p = tg3_lookup_by_subsys(tp);
15380 tp->phy_id = p->phy_id;
15381 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15382 /* For now we saw the IDs 0xbc050cd0,
15383 * 0xbc050f80 and 0xbc050c30 on devices
15384 * connected to an BCM4785 and there are
15385 * probably more. Just assume that the phy is
15386 * supported when it is connected to a SSB core
15393 tp->phy_id == TG3_PHY_ID_BCM8002)
15394 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15398 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15399 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15400 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15401 tg3_asic_rev(tp) == ASIC_REV_57766 ||
15402 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15403 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15404 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15405 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
15406 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
15407 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15409 tp->eee.supported = SUPPORTED_100baseT_Full |
15410 SUPPORTED_1000baseT_Full;
15411 tp->eee.advertised = ADVERTISED_100baseT_Full |
15412 ADVERTISED_1000baseT_Full;
15413 tp->eee.eee_enabled = 1;
15414 tp->eee.tx_lpi_enabled = 1;
15415 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15418 tg3_phy_init_link_config(tp);
15420 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15421 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15422 !tg3_flag(tp, ENABLE_APE) &&
15423 !tg3_flag(tp, ENABLE_ASF)) {
15426 tg3_readphy(tp, MII_BMSR, &bmsr);
15427 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15428 (bmsr & BMSR_LSTATUS))
15429 goto skip_phy_reset;
15431 err = tg3_phy_reset(tp);
15435 tg3_phy_set_wirespeed(tp);
15437 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
15438 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15439 tp->link_config.flowctrl);
15441 tg3_writephy(tp, MII_BMCR,
15442 BMCR_ANENABLE | BMCR_ANRESTART);
15447 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
15448 err = tg3_init_5401phy_dsp(tp);
15452 err = tg3_init_5401phy_dsp(tp);
15458 static void tg3_read_vpd(struct tg3 *tp)
15461 unsigned int block_end, rosize, len;
15465 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
15469 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
15471 goto out_not_found;
15473 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15474 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15475 i += PCI_VPD_LRDT_TAG_SIZE;
15477 if (block_end > vpdlen)
15478 goto out_not_found;
15480 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15481 PCI_VPD_RO_KEYWORD_MFR_ID);
15483 len = pci_vpd_info_field_size(&vpd_data[j]);
15485 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15486 if (j + len > block_end || len != 4 ||
15487 memcmp(&vpd_data[j], "1028", 4))
15490 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15491 PCI_VPD_RO_KEYWORD_VENDOR0);
15495 len = pci_vpd_info_field_size(&vpd_data[j]);
15497 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15498 if (j + len > block_end)
15501 if (len >= sizeof(tp->fw_ver))
15502 len = sizeof(tp->fw_ver) - 1;
15503 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15504 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15509 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15510 PCI_VPD_RO_KEYWORD_PARTNO);
15512 goto out_not_found;
15514 len = pci_vpd_info_field_size(&vpd_data[i]);
15516 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15517 if (len > TG3_BPN_SIZE ||
15518 (len + i) > vpdlen)
15519 goto out_not_found;
15521 memcpy(tp->board_part_number, &vpd_data[i], len);
15525 if (tp->board_part_number[0])
15529 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15530 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15531 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15532 strcpy(tp->board_part_number, "BCM5717");
15533 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15534 strcpy(tp->board_part_number, "BCM5718");
15537 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15538 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15539 strcpy(tp->board_part_number, "BCM57780");
15540 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15541 strcpy(tp->board_part_number, "BCM57760");
15542 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15543 strcpy(tp->board_part_number, "BCM57790");
15544 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15545 strcpy(tp->board_part_number, "BCM57788");
15548 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15549 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15550 strcpy(tp->board_part_number, "BCM57761");
15551 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15552 strcpy(tp->board_part_number, "BCM57765");
15553 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15554 strcpy(tp->board_part_number, "BCM57781");
15555 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15556 strcpy(tp->board_part_number, "BCM57785");
15557 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15558 strcpy(tp->board_part_number, "BCM57791");
15559 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15560 strcpy(tp->board_part_number, "BCM57795");
15563 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15564 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15565 strcpy(tp->board_part_number, "BCM57762");
15566 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15567 strcpy(tp->board_part_number, "BCM57766");
15568 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15569 strcpy(tp->board_part_number, "BCM57782");
15570 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15571 strcpy(tp->board_part_number, "BCM57786");
15574 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15575 strcpy(tp->board_part_number, "BCM95906");
15578 strcpy(tp->board_part_number, "none");
15582 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15586 if (tg3_nvram_read(tp, offset, &val) ||
15587 (val & 0xfc000000) != 0x0c000000 ||
15588 tg3_nvram_read(tp, offset + 4, &val) ||
15595 static void tg3_read_bc_ver(struct tg3 *tp)
15597 u32 val, offset, start, ver_offset;
15599 bool newver = false;
15601 if (tg3_nvram_read(tp, 0xc, &offset) ||
15602 tg3_nvram_read(tp, 0x4, &start))
15605 offset = tg3_nvram_logical_addr(tp, offset);
15607 if (tg3_nvram_read(tp, offset, &val))
15610 if ((val & 0xfc000000) == 0x0c000000) {
15611 if (tg3_nvram_read(tp, offset + 4, &val))
15618 dst_off = strlen(tp->fw_ver);
15621 if (TG3_VER_SIZE - dst_off < 16 ||
15622 tg3_nvram_read(tp, offset + 8, &ver_offset))
15625 offset = offset + ver_offset - start;
15626 for (i = 0; i < 16; i += 4) {
15628 if (tg3_nvram_read_be32(tp, offset + i, &v))
15631 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15636 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15639 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15640 TG3_NVM_BCVER_MAJSFT;
15641 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
15642 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15643 "v%d.%02d", major, minor);
15647 static void tg3_read_hwsb_ver(struct tg3 *tp)
15649 u32 val, major, minor;
15651 /* Use native endian representation */
15652 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15655 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15656 TG3_NVM_HWSB_CFG1_MAJSFT;
15657 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15658 TG3_NVM_HWSB_CFG1_MINSFT;
15660 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15663 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15665 u32 offset, major, minor, build;
15667 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15669 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15672 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15673 case TG3_EEPROM_SB_REVISION_0:
15674 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15676 case TG3_EEPROM_SB_REVISION_2:
15677 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15679 case TG3_EEPROM_SB_REVISION_3:
15680 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15682 case TG3_EEPROM_SB_REVISION_4:
15683 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15685 case TG3_EEPROM_SB_REVISION_5:
15686 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15688 case TG3_EEPROM_SB_REVISION_6:
15689 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15695 if (tg3_nvram_read(tp, offset, &val))
15698 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15699 TG3_EEPROM_SB_EDH_BLD_SHFT;
15700 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15701 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15702 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15704 if (minor > 99 || build > 26)
15707 offset = strlen(tp->fw_ver);
15708 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15709 " v%d.%02d", major, minor);
15712 offset = strlen(tp->fw_ver);
15713 if (offset < TG3_VER_SIZE - 1)
15714 tp->fw_ver[offset] = 'a' + build - 1;
15718 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15720 u32 val, offset, start;
15723 for (offset = TG3_NVM_DIR_START;
15724 offset < TG3_NVM_DIR_END;
15725 offset += TG3_NVM_DIRENT_SIZE) {
15726 if (tg3_nvram_read(tp, offset, &val))
15729 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15733 if (offset == TG3_NVM_DIR_END)
15736 if (!tg3_flag(tp, 5705_PLUS))
15737 start = 0x08000000;
15738 else if (tg3_nvram_read(tp, offset - 4, &start))
15741 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15742 !tg3_fw_img_is_valid(tp, offset) ||
15743 tg3_nvram_read(tp, offset + 8, &val))
15746 offset += val - start;
15748 vlen = strlen(tp->fw_ver);
15750 tp->fw_ver[vlen++] = ',';
15751 tp->fw_ver[vlen++] = ' ';
15753 for (i = 0; i < 4; i++) {
15755 if (tg3_nvram_read_be32(tp, offset, &v))
15758 offset += sizeof(v);
15760 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15761 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15765 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15770 static void tg3_probe_ncsi(struct tg3 *tp)
15774 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15775 if (apedata != APE_SEG_SIG_MAGIC)
15778 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15779 if (!(apedata & APE_FW_STATUS_READY))
15782 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15783 tg3_flag_set(tp, APE_HAS_NCSI);
15786 static void tg3_read_dash_ver(struct tg3 *tp)
15792 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15794 if (tg3_flag(tp, APE_HAS_NCSI))
15796 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15801 vlen = strlen(tp->fw_ver);
15803 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15805 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15806 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15807 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15808 (apedata & APE_FW_VERSION_BLDMSK));
15811 static void tg3_read_otp_ver(struct tg3 *tp)
15815 if (tg3_asic_rev(tp) != ASIC_REV_5762)
15818 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15819 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15820 TG3_OTP_MAGIC0_VALID(val)) {
15821 u64 val64 = (u64) val << 32 | val2;
15825 for (i = 0; i < 7; i++) {
15826 if ((val64 & 0xff) == 0)
15828 ver = val64 & 0xff;
15831 vlen = strlen(tp->fw_ver);
15832 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15836 static void tg3_read_fw_ver(struct tg3 *tp)
15839 bool vpd_vers = false;
15841 if (tp->fw_ver[0] != 0)
15844 if (tg3_flag(tp, NO_NVRAM)) {
15845 strcat(tp->fw_ver, "sb");
15846 tg3_read_otp_ver(tp);
15850 if (tg3_nvram_read(tp, 0, &val))
15853 if (val == TG3_EEPROM_MAGIC)
15854 tg3_read_bc_ver(tp);
15855 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15856 tg3_read_sb_ver(tp, val);
15857 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15858 tg3_read_hwsb_ver(tp);
15860 if (tg3_flag(tp, ENABLE_ASF)) {
15861 if (tg3_flag(tp, ENABLE_APE)) {
15862 tg3_probe_ncsi(tp);
15864 tg3_read_dash_ver(tp);
15865 } else if (!vpd_vers) {
15866 tg3_read_mgmtfw_ver(tp);
15870 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
15873 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15875 if (tg3_flag(tp, LRG_PROD_RING_CAP))
15876 return TG3_RX_RET_MAX_SIZE_5717;
15877 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
15878 return TG3_RX_RET_MAX_SIZE_5700;
15880 return TG3_RX_RET_MAX_SIZE_5705;
15883 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
15884 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15885 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15886 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15890 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
15892 struct pci_dev *peer;
15893 unsigned int func, devnr = tp->pdev->devfn & ~7;
15895 for (func = 0; func < 8; func++) {
15896 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15897 if (peer && peer != tp->pdev)
15901 /* 5704 can be configured in single-port mode, set peer to
15902 * tp->pdev in that case.
15910 * We don't need to keep the refcount elevated; there's no way
15911 * to remove one half of this device without removing the other
15918 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
15920 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
15921 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
15924 /* All devices that use the alternate
15925 * ASIC REV location have a CPMU.
15927 tg3_flag_set(tp, CPMU_PRESENT);
15929 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15930 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
15931 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15932 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15933 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
15934 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
15935 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
15936 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
15937 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
15938 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
15939 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
15940 reg = TG3PCI_GEN2_PRODID_ASICREV;
15941 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
15942 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
15943 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
15944 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
15945 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15946 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15947 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
15948 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
15949 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
15950 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15951 reg = TG3PCI_GEN15_PRODID_ASICREV;
15953 reg = TG3PCI_PRODID_ASICREV;
15955 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
15958 /* Wrong chip ID in 5752 A0. This code can be removed later
15959 * as A0 is not in production.
15961 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
15962 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
15964 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
15965 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
15967 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15968 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15969 tg3_asic_rev(tp) == ASIC_REV_5720)
15970 tg3_flag_set(tp, 5717_PLUS);
15972 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
15973 tg3_asic_rev(tp) == ASIC_REV_57766)
15974 tg3_flag_set(tp, 57765_CLASS);
15976 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
15977 tg3_asic_rev(tp) == ASIC_REV_5762)
15978 tg3_flag_set(tp, 57765_PLUS);
15980 /* Intentionally exclude ASIC_REV_5906 */
15981 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
15982 tg3_asic_rev(tp) == ASIC_REV_5787 ||
15983 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15984 tg3_asic_rev(tp) == ASIC_REV_5761 ||
15985 tg3_asic_rev(tp) == ASIC_REV_5785 ||
15986 tg3_asic_rev(tp) == ASIC_REV_57780 ||
15987 tg3_flag(tp, 57765_PLUS))
15988 tg3_flag_set(tp, 5755_PLUS);
15990 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
15991 tg3_asic_rev(tp) == ASIC_REV_5714)
15992 tg3_flag_set(tp, 5780_CLASS);
15994 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
15995 tg3_asic_rev(tp) == ASIC_REV_5752 ||
15996 tg3_asic_rev(tp) == ASIC_REV_5906 ||
15997 tg3_flag(tp, 5755_PLUS) ||
15998 tg3_flag(tp, 5780_CLASS))
15999 tg3_flag_set(tp, 5750_PLUS);
16001 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16002 tg3_flag(tp, 5750_PLUS))
16003 tg3_flag_set(tp, 5705_PLUS);
16006 static bool tg3_10_100_only_device(struct tg3 *tp,
16007 const struct pci_device_id *ent)
16009 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16011 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16012 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
16013 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16016 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
16017 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
16018 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16028 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
16031 u32 pci_state_reg, grc_misc_cfg;
16036 /* Force memory write invalidate off. If we leave it on,
16037 * then on 5700_BX chips we have to enable a workaround.
16038 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16039 * to match the cacheline size. The Broadcom driver have this
16040 * workaround but turns MWI off all the times so never uses
16041 * it. This seems to suggest that the workaround is insufficient.
16043 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16044 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16045 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16047 /* Important! -- Make sure register accesses are byteswapped
16048 * correctly. Also, for those chips that require it, make
16049 * sure that indirect register accesses are enabled before
16050 * the first operation.
16052 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16054 tp->misc_host_ctrl |= (misc_ctrl_reg &
16055 MISC_HOST_CTRL_CHIPREV);
16056 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16057 tp->misc_host_ctrl);
16059 tg3_detect_asic_rev(tp, misc_ctrl_reg);
16061 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16062 * we need to disable memory and use config. cycles
16063 * only to access all registers. The 5702/03 chips
16064 * can mistakenly decode the special cycles from the
16065 * ICH chipsets as memory write cycles, causing corruption
16066 * of register and memory space. Only certain ICH bridges
16067 * will drive special cycles with non-zero data during the
16068 * address phase which can fall within the 5703's address
16069 * range. This is not an ICH bug as the PCI spec allows
16070 * non-zero address during special cycles. However, only
16071 * these ICH bridges are known to drive non-zero addresses
16072 * during special cycles.
16074 * Since special cycles do not cross PCI bridges, we only
16075 * enable this workaround if the 5703 is on the secondary
16076 * bus of these ICH bridges.
16078 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16079 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
16080 static struct tg3_dev_id {
16084 } ich_chipsets[] = {
16085 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16087 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16089 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16091 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16095 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16096 struct pci_dev *bridge = NULL;
16098 while (pci_id->vendor != 0) {
16099 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16105 if (pci_id->rev != PCI_ANY_ID) {
16106 if (bridge->revision > pci_id->rev)
16109 if (bridge->subordinate &&
16110 (bridge->subordinate->number ==
16111 tp->pdev->bus->number)) {
16112 tg3_flag_set(tp, ICH_WORKAROUND);
16113 pci_dev_put(bridge);
16119 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
16120 static struct tg3_dev_id {
16123 } bridge_chipsets[] = {
16124 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16125 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16128 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16129 struct pci_dev *bridge = NULL;
16131 while (pci_id->vendor != 0) {
16132 bridge = pci_get_device(pci_id->vendor,
16139 if (bridge->subordinate &&
16140 (bridge->subordinate->number <=
16141 tp->pdev->bus->number) &&
16142 (bridge->subordinate->busn_res.end >=
16143 tp->pdev->bus->number)) {
16144 tg3_flag_set(tp, 5701_DMA_BUG);
16145 pci_dev_put(bridge);
16151 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16152 * DMA addresses > 40-bit. This bridge may have other additional
16153 * 57xx devices behind it in some 4-port NIC designs for example.
16154 * Any tg3 device found behind the bridge will also need the 40-bit
16157 if (tg3_flag(tp, 5780_CLASS)) {
16158 tg3_flag_set(tp, 40BIT_DMA_BUG);
16159 tp->msi_cap = tp->pdev->msi_cap;
16161 struct pci_dev *bridge = NULL;
16164 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16165 PCI_DEVICE_ID_SERVERWORKS_EPB,
16167 if (bridge && bridge->subordinate &&
16168 (bridge->subordinate->number <=
16169 tp->pdev->bus->number) &&
16170 (bridge->subordinate->busn_res.end >=
16171 tp->pdev->bus->number)) {
16172 tg3_flag_set(tp, 40BIT_DMA_BUG);
16173 pci_dev_put(bridge);
16179 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16180 tg3_asic_rev(tp) == ASIC_REV_5714)
16181 tp->pdev_peer = tg3_find_peer(tp);
16183 /* Determine TSO capabilities */
16184 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
16185 ; /* Do nothing. HW bug. */
16186 else if (tg3_flag(tp, 57765_PLUS))
16187 tg3_flag_set(tp, HW_TSO_3);
16188 else if (tg3_flag(tp, 5755_PLUS) ||
16189 tg3_asic_rev(tp) == ASIC_REV_5906)
16190 tg3_flag_set(tp, HW_TSO_2);
16191 else if (tg3_flag(tp, 5750_PLUS)) {
16192 tg3_flag_set(tp, HW_TSO_1);
16193 tg3_flag_set(tp, TSO_BUG);
16194 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16195 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
16196 tg3_flag_clear(tp, TSO_BUG);
16197 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16198 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16199 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
16200 tg3_flag_set(tp, FW_TSO);
16201 tg3_flag_set(tp, TSO_BUG);
16202 if (tg3_asic_rev(tp) == ASIC_REV_5705)
16203 tp->fw_needed = FIRMWARE_TG3TSO5;
16205 tp->fw_needed = FIRMWARE_TG3TSO;
16208 /* Selectively allow TSO based on operating conditions */
16209 if (tg3_flag(tp, HW_TSO_1) ||
16210 tg3_flag(tp, HW_TSO_2) ||
16211 tg3_flag(tp, HW_TSO_3) ||
16212 tg3_flag(tp, FW_TSO)) {
16213 /* For firmware TSO, assume ASF is disabled.
16214 * We'll disable TSO later if we discover ASF
16215 * is enabled in tg3_get_eeprom_hw_cfg().
16217 tg3_flag_set(tp, TSO_CAPABLE);
16219 tg3_flag_clear(tp, TSO_CAPABLE);
16220 tg3_flag_clear(tp, TSO_BUG);
16221 tp->fw_needed = NULL;
16224 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
16225 tp->fw_needed = FIRMWARE_TG3;
16227 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16228 tp->fw_needed = FIRMWARE_TG357766;
16232 if (tg3_flag(tp, 5750_PLUS)) {
16233 tg3_flag_set(tp, SUPPORT_MSI);
16234 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16235 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16236 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16237 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
16238 tp->pdev_peer == tp->pdev))
16239 tg3_flag_clear(tp, SUPPORT_MSI);
16241 if (tg3_flag(tp, 5755_PLUS) ||
16242 tg3_asic_rev(tp) == ASIC_REV_5906) {
16243 tg3_flag_set(tp, 1SHOT_MSI);
16246 if (tg3_flag(tp, 57765_PLUS)) {
16247 tg3_flag_set(tp, SUPPORT_MSIX);
16248 tp->irq_max = TG3_IRQ_MAX_VECS;
16254 if (tp->irq_max > 1) {
16255 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16256 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16258 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16259 tg3_asic_rev(tp) == ASIC_REV_5720)
16260 tp->txq_max = tp->irq_max - 1;
16263 if (tg3_flag(tp, 5755_PLUS) ||
16264 tg3_asic_rev(tp) == ASIC_REV_5906)
16265 tg3_flag_set(tp, SHORT_DMA_BUG);
16267 if (tg3_asic_rev(tp) == ASIC_REV_5719)
16268 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
16270 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16271 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16272 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16273 tg3_asic_rev(tp) == ASIC_REV_5762)
16274 tg3_flag_set(tp, LRG_PROD_RING_CAP);
16276 if (tg3_flag(tp, 57765_PLUS) &&
16277 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
16278 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
16280 if (!tg3_flag(tp, 5705_PLUS) ||
16281 tg3_flag(tp, 5780_CLASS) ||
16282 tg3_flag(tp, USE_JUMBO_BDFLAG))
16283 tg3_flag_set(tp, JUMBO_CAPABLE);
16285 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16288 if (pci_is_pcie(tp->pdev)) {
16291 tg3_flag_set(tp, PCI_EXPRESS);
16293 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
16294 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
16295 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16296 tg3_flag_clear(tp, HW_TSO_2);
16297 tg3_flag_clear(tp, TSO_CAPABLE);
16299 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16300 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16301 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16302 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
16303 tg3_flag_set(tp, CLKREQ_BUG);
16304 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
16305 tg3_flag_set(tp, L1PLLPD_EN);
16307 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
16308 /* BCM5785 devices are effectively PCIe devices, and should
16309 * follow PCIe codepaths, but do not have a PCIe capabilities
16312 tg3_flag_set(tp, PCI_EXPRESS);
16313 } else if (!tg3_flag(tp, 5705_PLUS) ||
16314 tg3_flag(tp, 5780_CLASS)) {
16315 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16316 if (!tp->pcix_cap) {
16317 dev_err(&tp->pdev->dev,
16318 "Cannot find PCI-X capability, aborting\n");
16322 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
16323 tg3_flag_set(tp, PCIX_MODE);
16326 /* If we have an AMD 762 or VIA K8T800 chipset, write
16327 * reordering to the mailbox registers done by the host
16328 * controller can cause major troubles. We read back from
16329 * every mailbox register write to force the writes to be
16330 * posted to the chip in order.
16332 if (pci_dev_present(tg3_write_reorder_chipsets) &&
16333 !tg3_flag(tp, PCI_EXPRESS))
16334 tg3_flag_set(tp, MBOX_WRITE_REORDER);
16336 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16337 &tp->pci_cacheline_sz);
16338 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16339 &tp->pci_lat_timer);
16340 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
16341 tp->pci_lat_timer < 64) {
16342 tp->pci_lat_timer = 64;
16343 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16344 tp->pci_lat_timer);
16347 /* Important! -- It is critical that the PCI-X hw workaround
16348 * situation is decided before the first MMIO register access.
16350 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
16351 /* 5700 BX chips need to have their TX producer index
16352 * mailboxes written twice to workaround a bug.
16354 tg3_flag_set(tp, TXD_MBOX_HWBUG);
16356 /* If we are in PCI-X mode, enable register write workaround.
16358 * The workaround is to use indirect register accesses
16359 * for all chip writes not to mailbox registers.
16361 if (tg3_flag(tp, PCIX_MODE)) {
16364 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16366 /* The chip can have it's power management PCI config
16367 * space registers clobbered due to this bug.
16368 * So explicitly force the chip into D0 here.
16370 pci_read_config_dword(tp->pdev,
16371 tp->pdev->pm_cap + PCI_PM_CTRL,
16373 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16374 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
16375 pci_write_config_dword(tp->pdev,
16376 tp->pdev->pm_cap + PCI_PM_CTRL,
16379 /* Also, force SERR#/PERR# in PCI command. */
16380 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16381 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16382 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16386 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
16387 tg3_flag_set(tp, PCI_HIGH_SPEED);
16388 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
16389 tg3_flag_set(tp, PCI_32BIT);
16391 /* Chip-specific fixup from Broadcom driver */
16392 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
16393 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16394 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16395 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16398 /* Default fast path register access methods */
16399 tp->read32 = tg3_read32;
16400 tp->write32 = tg3_write32;
16401 tp->read32_mbox = tg3_read32;
16402 tp->write32_mbox = tg3_write32;
16403 tp->write32_tx_mbox = tg3_write32;
16404 tp->write32_rx_mbox = tg3_write32;
16406 /* Various workaround register access methods */
16407 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
16408 tp->write32 = tg3_write_indirect_reg32;
16409 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
16410 (tg3_flag(tp, PCI_EXPRESS) &&
16411 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
16413 * Back to back register writes can cause problems on these
16414 * chips, the workaround is to read back all reg writes
16415 * except those to mailbox regs.
16417 * See tg3_write_indirect_reg32().
16419 tp->write32 = tg3_write_flush_reg32;
16422 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
16423 tp->write32_tx_mbox = tg3_write32_tx_mbox;
16424 if (tg3_flag(tp, MBOX_WRITE_REORDER))
16425 tp->write32_rx_mbox = tg3_write_flush_reg32;
16428 if (tg3_flag(tp, ICH_WORKAROUND)) {
16429 tp->read32 = tg3_read_indirect_reg32;
16430 tp->write32 = tg3_write_indirect_reg32;
16431 tp->read32_mbox = tg3_read_indirect_mbox;
16432 tp->write32_mbox = tg3_write_indirect_mbox;
16433 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16434 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16439 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16440 pci_cmd &= ~PCI_COMMAND_MEMORY;
16441 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16443 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16444 tp->read32_mbox = tg3_read32_mbox_5906;
16445 tp->write32_mbox = tg3_write32_mbox_5906;
16446 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16447 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16450 if (tp->write32 == tg3_write_indirect_reg32 ||
16451 (tg3_flag(tp, PCIX_MODE) &&
16452 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16453 tg3_asic_rev(tp) == ASIC_REV_5701)))
16454 tg3_flag_set(tp, SRAM_USE_CONFIG);
16456 /* The memory arbiter has to be enabled in order for SRAM accesses
16457 * to succeed. Normally on powerup the tg3 chip firmware will make
16458 * sure it is enabled, but other entities such as system netboot
16459 * code might disable it.
16461 val = tr32(MEMARB_MODE);
16462 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16464 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
16465 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16466 tg3_flag(tp, 5780_CLASS)) {
16467 if (tg3_flag(tp, PCIX_MODE)) {
16468 pci_read_config_dword(tp->pdev,
16469 tp->pcix_cap + PCI_X_STATUS,
16471 tp->pci_fn = val & 0x7;
16473 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16474 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16475 tg3_asic_rev(tp) == ASIC_REV_5720) {
16476 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16477 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16478 val = tr32(TG3_CPMU_STATUS);
16480 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16481 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16483 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16484 TG3_CPMU_STATUS_FSHFT_5719;
16487 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16488 tp->write32_tx_mbox = tg3_write_flush_reg32;
16489 tp->write32_rx_mbox = tg3_write_flush_reg32;
16492 /* Get eeprom hw config before calling tg3_set_power_state().
16493 * In particular, the TG3_FLAG_IS_NIC flag must be
16494 * determined before calling tg3_set_power_state() so that
16495 * we know whether or not to switch out of Vaux power.
16496 * When the flag is set, it means that GPIO1 is used for eeprom
16497 * write protect and also implies that it is a LOM where GPIOs
16498 * are not used to switch power.
16500 tg3_get_eeprom_hw_cfg(tp);
16502 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16503 tg3_flag_clear(tp, TSO_CAPABLE);
16504 tg3_flag_clear(tp, TSO_BUG);
16505 tp->fw_needed = NULL;
16508 if (tg3_flag(tp, ENABLE_APE)) {
16509 /* Allow reads and writes to the
16510 * APE register and memory space.
16512 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
16513 PCISTATE_ALLOW_APE_SHMEM_WR |
16514 PCISTATE_ALLOW_APE_PSPACE_WR;
16515 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16518 tg3_ape_lock_init(tp);
16521 /* Set up tp->grc_local_ctrl before calling
16522 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16523 * will bring 5700's external PHY out of reset.
16524 * It is also used as eeprom write protect on LOMs.
16526 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16527 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16528 tg3_flag(tp, EEPROM_WRITE_PROT))
16529 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16530 GRC_LCLCTRL_GPIO_OUTPUT1);
16531 /* Unused GPIO3 must be driven as output on 5752 because there
16532 * are no pull-up resistors on unused GPIO pins.
16534 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16535 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16537 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16538 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16539 tg3_flag(tp, 57765_CLASS))
16540 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16542 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16543 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16544 /* Turn off the debug UART. */
16545 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16546 if (tg3_flag(tp, IS_NIC))
16547 /* Keep VMain power. */
16548 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16549 GRC_LCLCTRL_GPIO_OUTPUT0;
16552 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16553 tp->grc_local_ctrl |=
16554 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16556 /* Switch out of Vaux if it is a NIC */
16557 tg3_pwrsrc_switch_to_vmain(tp);
16559 /* Derive initial jumbo mode from MTU assigned in
16560 * ether_setup() via the alloc_etherdev() call
16562 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16563 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16565 /* Determine WakeOnLan speed to use. */
16566 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16567 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16568 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16569 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16570 tg3_flag_clear(tp, WOL_SPEED_100MB);
16572 tg3_flag_set(tp, WOL_SPEED_100MB);
16575 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16576 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16578 /* A few boards don't want Ethernet@WireSpeed phy feature */
16579 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16580 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16581 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16582 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16583 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16584 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16585 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16587 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16588 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16589 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16590 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16591 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16593 if (tg3_flag(tp, 5705_PLUS) &&
16594 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16595 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16596 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16597 !tg3_flag(tp, 57765_PLUS)) {
16598 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16599 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16600 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16601 tg3_asic_rev(tp) == ASIC_REV_5761) {
16602 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16603 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16604 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16605 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16606 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16608 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16611 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16612 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16613 tp->phy_otp = tg3_read_otp_phycfg(tp);
16614 if (tp->phy_otp == 0)
16615 tp->phy_otp = TG3_OTP_DEFAULT;
16618 if (tg3_flag(tp, CPMU_PRESENT))
16619 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16621 tp->mi_mode = MAC_MI_MODE_BASE;
16623 tp->coalesce_mode = 0;
16624 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16625 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16626 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16628 /* Set these bits to enable statistics workaround. */
16629 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16630 tg3_asic_rev(tp) == ASIC_REV_5762 ||
16631 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16632 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16633 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16634 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16637 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16638 tg3_asic_rev(tp) == ASIC_REV_57780)
16639 tg3_flag_set(tp, USE_PHYLIB);
16641 err = tg3_mdio_init(tp);
16645 /* Initialize data/descriptor byte/word swapping. */
16646 val = tr32(GRC_MODE);
16647 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16648 tg3_asic_rev(tp) == ASIC_REV_5762)
16649 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16650 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16651 GRC_MODE_B2HRX_ENABLE |
16652 GRC_MODE_HTX2B_ENABLE |
16653 GRC_MODE_HOST_STACKUP);
16655 val &= GRC_MODE_HOST_STACKUP;
16657 tw32(GRC_MODE, val | tp->grc_mode);
16659 tg3_switch_clocks(tp);
16661 /* Clear this out for sanity. */
16662 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16664 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16665 tw32(TG3PCI_REG_BASE_ADDR, 0);
16667 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16669 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
16670 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16671 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16672 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16673 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16674 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16675 void __iomem *sram_base;
16677 /* Write some dummy words into the SRAM status block
16678 * area, see if it reads back correctly. If the return
16679 * value is bad, force enable the PCIX workaround.
16681 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16683 writel(0x00000000, sram_base);
16684 writel(0x00000000, sram_base + 4);
16685 writel(0xffffffff, sram_base + 4);
16686 if (readl(sram_base) != 0x00000000)
16687 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16692 tg3_nvram_init(tp);
16694 /* If the device has an NVRAM, no need to load patch firmware */
16695 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16696 !tg3_flag(tp, NO_NVRAM))
16697 tp->fw_needed = NULL;
16699 grc_misc_cfg = tr32(GRC_MISC_CFG);
16700 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16702 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16703 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16704 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
16705 tg3_flag_set(tp, IS_5788);
16707 if (!tg3_flag(tp, IS_5788) &&
16708 tg3_asic_rev(tp) != ASIC_REV_5700)
16709 tg3_flag_set(tp, TAGGED_STATUS);
16710 if (tg3_flag(tp, TAGGED_STATUS)) {
16711 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16712 HOSTCC_MODE_CLRTICK_TXBD);
16714 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16715 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16716 tp->misc_host_ctrl);
16719 /* Preserve the APE MAC_MODE bits */
16720 if (tg3_flag(tp, ENABLE_APE))
16721 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16725 if (tg3_10_100_only_device(tp, ent))
16726 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16728 err = tg3_phy_probe(tp);
16730 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16731 /* ... but do not return immediately ... */
16736 tg3_read_fw_ver(tp);
16738 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16739 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16741 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16742 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16744 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16747 /* 5700 {AX,BX} chips have a broken status block link
16748 * change bit implementation, so we must use the
16749 * status register in those cases.
16751 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16752 tg3_flag_set(tp, USE_LINKCHG_REG);
16754 tg3_flag_clear(tp, USE_LINKCHG_REG);
16756 /* The led_ctrl is set during tg3_phy_probe, here we might
16757 * have to force the link status polling mechanism based
16758 * upon subsystem IDs.
16760 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16761 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16762 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16763 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16764 tg3_flag_set(tp, USE_LINKCHG_REG);
16767 /* For all SERDES we poll the MAC status register. */
16768 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16769 tg3_flag_set(tp, POLL_SERDES);
16771 tg3_flag_clear(tp, POLL_SERDES);
16773 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16774 tg3_flag_set(tp, POLL_CPMU_LINK);
16776 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16777 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16778 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16779 tg3_flag(tp, PCIX_MODE)) {
16780 tp->rx_offset = NET_SKB_PAD;
16781 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16782 tp->rx_copy_thresh = ~(u16)0;
16786 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16787 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
16788 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16790 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
16792 /* Increment the rx prod index on the rx std ring by at most
16793 * 8 for these chips to workaround hw errata.
16795 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16796 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16797 tg3_asic_rev(tp) == ASIC_REV_5755)
16798 tp->rx_std_max_post = 8;
16800 if (tg3_flag(tp, ASPM_WORKAROUND))
16801 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16802 PCIE_PWR_MGMT_L1_THRESH_MSK;
16807 #ifdef CONFIG_SPARC
16808 static int tg3_get_macaddr_sparc(struct tg3 *tp)
16810 struct net_device *dev = tp->dev;
16811 struct pci_dev *pdev = tp->pdev;
16812 struct device_node *dp = pci_device_to_OF_node(pdev);
16813 const unsigned char *addr;
16816 addr = of_get_property(dp, "local-mac-address", &len);
16817 if (addr && len == ETH_ALEN) {
16818 memcpy(dev->dev_addr, addr, ETH_ALEN);
16824 static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
16826 struct net_device *dev = tp->dev;
16828 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
16833 static int tg3_get_device_address(struct tg3 *tp)
16835 struct net_device *dev = tp->dev;
16836 u32 hi, lo, mac_offset;
16840 #ifdef CONFIG_SPARC
16841 if (!tg3_get_macaddr_sparc(tp))
16845 if (tg3_flag(tp, IS_SSB_CORE)) {
16846 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16847 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16852 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16853 tg3_flag(tp, 5780_CLASS)) {
16854 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16856 if (tg3_nvram_lock(tp))
16857 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16859 tg3_nvram_unlock(tp);
16860 } else if (tg3_flag(tp, 5717_PLUS)) {
16861 if (tp->pci_fn & 1)
16863 if (tp->pci_fn > 1)
16864 mac_offset += 0x18c;
16865 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
16868 /* First try to get it from MAC address mailbox. */
16869 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16870 if ((hi >> 16) == 0x484b) {
16871 dev->dev_addr[0] = (hi >> 8) & 0xff;
16872 dev->dev_addr[1] = (hi >> 0) & 0xff;
16874 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16875 dev->dev_addr[2] = (lo >> 24) & 0xff;
16876 dev->dev_addr[3] = (lo >> 16) & 0xff;
16877 dev->dev_addr[4] = (lo >> 8) & 0xff;
16878 dev->dev_addr[5] = (lo >> 0) & 0xff;
16880 /* Some old bootcode may report a 0 MAC address in SRAM */
16881 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16884 /* Next, try NVRAM. */
16885 if (!tg3_flag(tp, NO_NVRAM) &&
16886 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
16887 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
16888 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16889 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
16891 /* Finally just fetch it out of the MAC control regs. */
16893 hi = tr32(MAC_ADDR_0_HIGH);
16894 lo = tr32(MAC_ADDR_0_LOW);
16896 dev->dev_addr[5] = lo & 0xff;
16897 dev->dev_addr[4] = (lo >> 8) & 0xff;
16898 dev->dev_addr[3] = (lo >> 16) & 0xff;
16899 dev->dev_addr[2] = (lo >> 24) & 0xff;
16900 dev->dev_addr[1] = hi & 0xff;
16901 dev->dev_addr[0] = (hi >> 8) & 0xff;
16905 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
16906 #ifdef CONFIG_SPARC
16907 if (!tg3_get_default_macaddr_sparc(tp))
16915 #define BOUNDARY_SINGLE_CACHELINE 1
16916 #define BOUNDARY_MULTI_CACHELINE 2
16918 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
16920 int cacheline_size;
16924 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16926 cacheline_size = 1024;
16928 cacheline_size = (int) byte * 4;
16930 /* On 5703 and later chips, the boundary bits have no
16933 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16934 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16935 !tg3_flag(tp, PCI_EXPRESS))
16938 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16939 goal = BOUNDARY_MULTI_CACHELINE;
16941 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16942 goal = BOUNDARY_SINGLE_CACHELINE;
16948 if (tg3_flag(tp, 57765_PLUS)) {
16949 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
16956 /* PCI controllers on most RISC systems tend to disconnect
16957 * when a device tries to burst across a cache-line boundary.
16958 * Therefore, letting tg3 do so just wastes PCI bandwidth.
16960 * Unfortunately, for PCI-E there are only limited
16961 * write-side controls for this, and thus for reads
16962 * we will still get the disconnects. We'll also waste
16963 * these PCI cycles for both read and write for chips
16964 * other than 5700 and 5701 which do not implement the
16967 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
16968 switch (cacheline_size) {
16973 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16974 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
16975 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
16977 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16978 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16983 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
16984 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
16988 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16989 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16992 } else if (tg3_flag(tp, PCI_EXPRESS)) {
16993 switch (cacheline_size) {
16997 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16998 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16999 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17005 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17006 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17010 switch (cacheline_size) {
17012 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17013 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17014 DMA_RWCTRL_WRITE_BNDRY_16);
17019 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17020 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17021 DMA_RWCTRL_WRITE_BNDRY_32);
17026 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17027 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17028 DMA_RWCTRL_WRITE_BNDRY_64);
17033 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17034 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17035 DMA_RWCTRL_WRITE_BNDRY_128);
17040 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17041 DMA_RWCTRL_WRITE_BNDRY_256);
17044 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17045 DMA_RWCTRL_WRITE_BNDRY_512);
17049 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17050 DMA_RWCTRL_WRITE_BNDRY_1024);
17059 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
17060 int size, bool to_device)
17062 struct tg3_internal_buffer_desc test_desc;
17063 u32 sram_dma_descs;
17066 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17068 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17069 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17070 tw32(RDMAC_STATUS, 0);
17071 tw32(WDMAC_STATUS, 0);
17073 tw32(BUFMGR_MODE, 0);
17074 tw32(FTQ_RESET, 0);
17076 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17077 test_desc.addr_lo = buf_dma & 0xffffffff;
17078 test_desc.nic_mbuf = 0x00002100;
17079 test_desc.len = size;
17082 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17083 * the *second* time the tg3 driver was getting loaded after an
17086 * Broadcom tells me:
17087 * ...the DMA engine is connected to the GRC block and a DMA
17088 * reset may affect the GRC block in some unpredictable way...
17089 * The behavior of resets to individual blocks has not been tested.
17091 * Broadcom noted the GRC reset will also reset all sub-components.
17094 test_desc.cqid_sqid = (13 << 8) | 2;
17096 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17099 test_desc.cqid_sqid = (16 << 8) | 7;
17101 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17104 test_desc.flags = 0x00000005;
17106 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17109 val = *(((u32 *)&test_desc) + i);
17110 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17111 sram_dma_descs + (i * sizeof(u32)));
17112 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17114 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17117 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
17119 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
17122 for (i = 0; i < 40; i++) {
17126 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17128 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17129 if ((val & 0xffff) == sram_dma_descs) {
17140 #define TEST_BUFFER_SIZE 0x2000
17142 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
17143 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17147 static int tg3_test_dma(struct tg3 *tp)
17149 dma_addr_t buf_dma;
17150 u32 *buf, saved_dma_rwctrl;
17153 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17154 &buf_dma, GFP_KERNEL);
17160 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17161 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17163 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
17165 if (tg3_flag(tp, 57765_PLUS))
17168 if (tg3_flag(tp, PCI_EXPRESS)) {
17169 /* DMA read watermark not used on PCIE */
17170 tp->dma_rwctrl |= 0x00180000;
17171 } else if (!tg3_flag(tp, PCIX_MODE)) {
17172 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17173 tg3_asic_rev(tp) == ASIC_REV_5750)
17174 tp->dma_rwctrl |= 0x003f0000;
17176 tp->dma_rwctrl |= 0x003f000f;
17178 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17179 tg3_asic_rev(tp) == ASIC_REV_5704) {
17180 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
17181 u32 read_water = 0x7;
17183 /* If the 5704 is behind the EPB bridge, we can
17184 * do the less restrictive ONE_DMA workaround for
17185 * better performance.
17187 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
17188 tg3_asic_rev(tp) == ASIC_REV_5704)
17189 tp->dma_rwctrl |= 0x8000;
17190 else if (ccval == 0x6 || ccval == 0x7)
17191 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17193 if (tg3_asic_rev(tp) == ASIC_REV_5703)
17195 /* Set bit 23 to enable PCIX hw bug fix */
17197 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17198 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17200 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
17201 /* 5780 always in PCIX mode */
17202 tp->dma_rwctrl |= 0x00144000;
17203 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
17204 /* 5714 always in PCIX mode */
17205 tp->dma_rwctrl |= 0x00148000;
17207 tp->dma_rwctrl |= 0x001b000f;
17210 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17211 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17213 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17214 tg3_asic_rev(tp) == ASIC_REV_5704)
17215 tp->dma_rwctrl &= 0xfffffff0;
17217 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17218 tg3_asic_rev(tp) == ASIC_REV_5701) {
17219 /* Remove this if it causes problems for some boards. */
17220 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17222 /* On 5700/5701 chips, we need to set this bit.
17223 * Otherwise the chip will issue cacheline transactions
17224 * to streamable DMA memory with not all the byte
17225 * enables turned on. This is an error on several
17226 * RISC PCI controllers, in particular sparc64.
17228 * On 5703/5704 chips, this bit has been reassigned
17229 * a different meaning. In particular, it is used
17230 * on those chips to enable a PCI-X workaround.
17232 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17235 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17238 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17239 tg3_asic_rev(tp) != ASIC_REV_5701)
17242 /* It is best to perform DMA test with maximum write burst size
17243 * to expose the 5700/5701 write DMA bug.
17245 saved_dma_rwctrl = tp->dma_rwctrl;
17246 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17247 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17252 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17255 /* Send the buffer to the chip. */
17256 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
17258 dev_err(&tp->pdev->dev,
17259 "%s: Buffer write failed. err = %d\n",
17264 /* Now read it back. */
17265 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
17267 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17268 "err = %d\n", __func__, ret);
17273 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17277 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17278 DMA_RWCTRL_WRITE_BNDRY_16) {
17279 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17280 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17281 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17284 dev_err(&tp->pdev->dev,
17285 "%s: Buffer corrupted on read back! "
17286 "(%d != %d)\n", __func__, p[i], i);
17292 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17298 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17299 DMA_RWCTRL_WRITE_BNDRY_16) {
17300 /* DMA test passed without adjusting DMA boundary,
17301 * now look for chipsets that are known to expose the
17302 * DMA bug without failing the test.
17304 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
17305 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17306 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17308 /* Safe to use the calculated DMA boundary. */
17309 tp->dma_rwctrl = saved_dma_rwctrl;
17312 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17316 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
17321 static void tg3_init_bufmgr_config(struct tg3 *tp)
17323 if (tg3_flag(tp, 57765_PLUS)) {
17324 tp->bufmgr_config.mbuf_read_dma_low_water =
17325 DEFAULT_MB_RDMA_LOW_WATER_5705;
17326 tp->bufmgr_config.mbuf_mac_rx_low_water =
17327 DEFAULT_MB_MACRX_LOW_WATER_57765;
17328 tp->bufmgr_config.mbuf_high_water =
17329 DEFAULT_MB_HIGH_WATER_57765;
17331 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17332 DEFAULT_MB_RDMA_LOW_WATER_5705;
17333 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17334 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17335 tp->bufmgr_config.mbuf_high_water_jumbo =
17336 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
17337 } else if (tg3_flag(tp, 5705_PLUS)) {
17338 tp->bufmgr_config.mbuf_read_dma_low_water =
17339 DEFAULT_MB_RDMA_LOW_WATER_5705;
17340 tp->bufmgr_config.mbuf_mac_rx_low_water =
17341 DEFAULT_MB_MACRX_LOW_WATER_5705;
17342 tp->bufmgr_config.mbuf_high_water =
17343 DEFAULT_MB_HIGH_WATER_5705;
17344 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
17345 tp->bufmgr_config.mbuf_mac_rx_low_water =
17346 DEFAULT_MB_MACRX_LOW_WATER_5906;
17347 tp->bufmgr_config.mbuf_high_water =
17348 DEFAULT_MB_HIGH_WATER_5906;
17351 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17352 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17353 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17354 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17355 tp->bufmgr_config.mbuf_high_water_jumbo =
17356 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17358 tp->bufmgr_config.mbuf_read_dma_low_water =
17359 DEFAULT_MB_RDMA_LOW_WATER;
17360 tp->bufmgr_config.mbuf_mac_rx_low_water =
17361 DEFAULT_MB_MACRX_LOW_WATER;
17362 tp->bufmgr_config.mbuf_high_water =
17363 DEFAULT_MB_HIGH_WATER;
17365 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17366 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17367 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17368 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17369 tp->bufmgr_config.mbuf_high_water_jumbo =
17370 DEFAULT_MB_HIGH_WATER_JUMBO;
17373 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17374 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17377 static char *tg3_phy_string(struct tg3 *tp)
17379 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17380 case TG3_PHY_ID_BCM5400: return "5400";
17381 case TG3_PHY_ID_BCM5401: return "5401";
17382 case TG3_PHY_ID_BCM5411: return "5411";
17383 case TG3_PHY_ID_BCM5701: return "5701";
17384 case TG3_PHY_ID_BCM5703: return "5703";
17385 case TG3_PHY_ID_BCM5704: return "5704";
17386 case TG3_PHY_ID_BCM5705: return "5705";
17387 case TG3_PHY_ID_BCM5750: return "5750";
17388 case TG3_PHY_ID_BCM5752: return "5752";
17389 case TG3_PHY_ID_BCM5714: return "5714";
17390 case TG3_PHY_ID_BCM5780: return "5780";
17391 case TG3_PHY_ID_BCM5755: return "5755";
17392 case TG3_PHY_ID_BCM5787: return "5787";
17393 case TG3_PHY_ID_BCM5784: return "5784";
17394 case TG3_PHY_ID_BCM5756: return "5722/5756";
17395 case TG3_PHY_ID_BCM5906: return "5906";
17396 case TG3_PHY_ID_BCM5761: return "5761";
17397 case TG3_PHY_ID_BCM5718C: return "5718C";
17398 case TG3_PHY_ID_BCM5718S: return "5718S";
17399 case TG3_PHY_ID_BCM57765: return "57765";
17400 case TG3_PHY_ID_BCM5719C: return "5719C";
17401 case TG3_PHY_ID_BCM5720C: return "5720C";
17402 case TG3_PHY_ID_BCM5762: return "5762C";
17403 case TG3_PHY_ID_BCM8002: return "8002/serdes";
17404 case 0: return "serdes";
17405 default: return "unknown";
17409 static char *tg3_bus_string(struct tg3 *tp, char *str)
17411 if (tg3_flag(tp, PCI_EXPRESS)) {
17412 strcpy(str, "PCI Express");
17414 } else if (tg3_flag(tp, PCIX_MODE)) {
17415 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17417 strcpy(str, "PCIX:");
17419 if ((clock_ctrl == 7) ||
17420 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17421 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17422 strcat(str, "133MHz");
17423 else if (clock_ctrl == 0)
17424 strcat(str, "33MHz");
17425 else if (clock_ctrl == 2)
17426 strcat(str, "50MHz");
17427 else if (clock_ctrl == 4)
17428 strcat(str, "66MHz");
17429 else if (clock_ctrl == 6)
17430 strcat(str, "100MHz");
17432 strcpy(str, "PCI:");
17433 if (tg3_flag(tp, PCI_HIGH_SPEED))
17434 strcat(str, "66MHz");
17436 strcat(str, "33MHz");
17438 if (tg3_flag(tp, PCI_32BIT))
17439 strcat(str, ":32-bit");
17441 strcat(str, ":64-bit");
17445 static void tg3_init_coal(struct tg3 *tp)
17447 struct ethtool_coalesce *ec = &tp->coal;
17449 memset(ec, 0, sizeof(*ec));
17450 ec->cmd = ETHTOOL_GCOALESCE;
17451 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17452 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17453 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17454 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17455 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17456 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17457 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17458 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17459 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17461 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17462 HOSTCC_MODE_CLRTICK_TXBD)) {
17463 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17464 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17465 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17466 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17469 if (tg3_flag(tp, 5705_PLUS)) {
17470 ec->rx_coalesce_usecs_irq = 0;
17471 ec->tx_coalesce_usecs_irq = 0;
17472 ec->stats_block_coalesce_usecs = 0;
17476 static int tg3_init_one(struct pci_dev *pdev,
17477 const struct pci_device_id *ent)
17479 struct net_device *dev;
17482 u32 sndmbx, rcvmbx, intmbx;
17484 u64 dma_mask, persist_dma_mask;
17485 netdev_features_t features = 0;
17487 printk_once(KERN_INFO "%s\n", version);
17489 err = pci_enable_device(pdev);
17491 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
17495 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17497 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
17498 goto err_out_disable_pdev;
17501 pci_set_master(pdev);
17503 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17506 goto err_out_free_res;
17509 SET_NETDEV_DEV(dev, &pdev->dev);
17511 tp = netdev_priv(dev);
17514 tp->rx_mode = TG3_DEF_RX_MODE;
17515 tp->tx_mode = TG3_DEF_TX_MODE;
17519 tp->msg_enable = tg3_debug;
17521 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17523 if (pdev_is_ssb_gige_core(pdev)) {
17524 tg3_flag_set(tp, IS_SSB_CORE);
17525 if (ssb_gige_must_flush_posted_writes(pdev))
17526 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17527 if (ssb_gige_one_dma_at_once(pdev))
17528 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17529 if (ssb_gige_have_roboswitch(pdev)) {
17530 tg3_flag_set(tp, USE_PHYLIB);
17531 tg3_flag_set(tp, ROBOSWITCH);
17533 if (ssb_gige_is_rgmii(pdev))
17534 tg3_flag_set(tp, RGMII_MODE);
17537 /* The word/byte swap controls here control register access byte
17538 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17541 tp->misc_host_ctrl =
17542 MISC_HOST_CTRL_MASK_PCI_INT |
17543 MISC_HOST_CTRL_WORD_SWAP |
17544 MISC_HOST_CTRL_INDIR_ACCESS |
17545 MISC_HOST_CTRL_PCISTATE_RW;
17547 /* The NONFRM (non-frame) byte/word swap controls take effect
17548 * on descriptor entries, anything which isn't packet data.
17550 * The StrongARM chips on the board (one for tx, one for rx)
17551 * are running in big-endian mode.
17553 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17554 GRC_MODE_WSWAP_NONFRM_DATA);
17555 #ifdef __BIG_ENDIAN
17556 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17558 spin_lock_init(&tp->lock);
17559 spin_lock_init(&tp->indirect_lock);
17560 INIT_WORK(&tp->reset_task, tg3_reset_task);
17562 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17564 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
17566 goto err_out_free_dev;
17569 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17570 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17571 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17572 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17573 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17574 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17575 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17576 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17577 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17578 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17579 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
17580 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17581 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17582 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17583 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
17584 tg3_flag_set(tp, ENABLE_APE);
17585 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17586 if (!tp->aperegs) {
17587 dev_err(&pdev->dev,
17588 "Cannot map APE registers, aborting\n");
17590 goto err_out_iounmap;
17594 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17595 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17597 dev->ethtool_ops = &tg3_ethtool_ops;
17598 dev->watchdog_timeo = TG3_TX_TIMEOUT;
17599 dev->netdev_ops = &tg3_netdev_ops;
17600 dev->irq = pdev->irq;
17602 err = tg3_get_invariants(tp, ent);
17604 dev_err(&pdev->dev,
17605 "Problem fetching invariants of chip, aborting\n");
17606 goto err_out_apeunmap;
17609 /* The EPB bridge inside 5714, 5715, and 5780 and any
17610 * device behind the EPB cannot support DMA addresses > 40-bit.
17611 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17612 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17613 * do DMA address check in tg3_start_xmit().
17615 if (tg3_flag(tp, IS_5788))
17616 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
17617 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17618 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
17619 #ifdef CONFIG_HIGHMEM
17620 dma_mask = DMA_BIT_MASK(64);
17623 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
17625 /* Configure DMA attributes. */
17626 if (dma_mask > DMA_BIT_MASK(32)) {
17627 err = pci_set_dma_mask(pdev, dma_mask);
17629 features |= NETIF_F_HIGHDMA;
17630 err = pci_set_consistent_dma_mask(pdev,
17633 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17634 "DMA for consistent allocations\n");
17635 goto err_out_apeunmap;
17639 if (err || dma_mask == DMA_BIT_MASK(32)) {
17640 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
17642 dev_err(&pdev->dev,
17643 "No usable DMA configuration, aborting\n");
17644 goto err_out_apeunmap;
17648 tg3_init_bufmgr_config(tp);
17650 features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
17652 /* 5700 B0 chips do not support checksumming correctly due
17653 * to hardware bugs.
17655 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17656 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17658 if (tg3_flag(tp, 5755_PLUS))
17659 features |= NETIF_F_IPV6_CSUM;
17662 /* TSO is on by default on chips that support hardware TSO.
17663 * Firmware TSO on older chips gives lower performance, so it
17664 * is off by default, but can be enabled using ethtool.
17666 if ((tg3_flag(tp, HW_TSO_1) ||
17667 tg3_flag(tp, HW_TSO_2) ||
17668 tg3_flag(tp, HW_TSO_3)) &&
17669 (features & NETIF_F_IP_CSUM))
17670 features |= NETIF_F_TSO;
17671 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17672 if (features & NETIF_F_IPV6_CSUM)
17673 features |= NETIF_F_TSO6;
17674 if (tg3_flag(tp, HW_TSO_3) ||
17675 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17676 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17677 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17678 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17679 tg3_asic_rev(tp) == ASIC_REV_57780)
17680 features |= NETIF_F_TSO_ECN;
17683 dev->features |= features;
17684 dev->vlan_features |= features;
17687 * Add loopback capability only for a subset of devices that support
17688 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17689 * loopback for the remaining devices.
17691 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17692 !tg3_flag(tp, CPMU_PRESENT))
17693 /* Add the loopback capability */
17694 features |= NETIF_F_LOOPBACK;
17696 dev->hw_features |= features;
17697 dev->priv_flags |= IFF_UNICAST_FLT;
17699 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17700 !tg3_flag(tp, TSO_CAPABLE) &&
17701 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17702 tg3_flag_set(tp, MAX_RXPEND_64);
17703 tp->rx_pending = 63;
17706 err = tg3_get_device_address(tp);
17708 dev_err(&pdev->dev,
17709 "Could not obtain valid ethernet address, aborting\n");
17710 goto err_out_apeunmap;
17714 * Reset chip in case UNDI or EFI driver did not shutdown
17715 * DMA self test will enable WDMAC and we'll see (spurious)
17716 * pending DMA on the PCI bus at that point.
17718 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17719 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
17720 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
17721 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17724 err = tg3_test_dma(tp);
17726 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
17727 goto err_out_apeunmap;
17730 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17731 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17732 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
17733 for (i = 0; i < tp->irq_max; i++) {
17734 struct tg3_napi *tnapi = &tp->napi[i];
17737 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17739 tnapi->int_mbox = intmbx;
17745 tnapi->consmbox = rcvmbx;
17746 tnapi->prodmbox = sndmbx;
17749 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
17751 tnapi->coal_now = HOSTCC_MODE_NOW;
17753 if (!tg3_flag(tp, SUPPORT_MSIX))
17757 * If we support MSIX, we'll be using RSS. If we're using
17758 * RSS, the first vector only handles link interrupts and the
17759 * remaining vectors handle rx and tx interrupts. Reuse the
17760 * mailbox values for the next iteration. The values we setup
17761 * above are still useful for the single vectored mode.
17776 pci_set_drvdata(pdev, dev);
17778 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17779 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17780 tg3_asic_rev(tp) == ASIC_REV_5762)
17781 tg3_flag_set(tp, PTP_CAPABLE);
17783 tg3_timer_init(tp);
17785 tg3_carrier_off(tp);
17787 err = register_netdev(dev);
17789 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
17790 goto err_out_apeunmap;
17793 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17794 tp->board_part_number,
17795 tg3_chip_rev_id(tp),
17796 tg3_bus_string(tp, str),
17799 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
17800 struct phy_device *phydev;
17801 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
17803 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
17804 phydev->drv->name, dev_name(&phydev->dev));
17808 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17809 ethtype = "10/100Base-TX";
17810 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17811 ethtype = "1000Base-SX";
17813 ethtype = "10/100/1000Base-T";
17815 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
17816 "(WireSpeed[%d], EEE[%d])\n",
17817 tg3_phy_string(tp), ethtype,
17818 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17819 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
17822 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
17823 (dev->features & NETIF_F_RXCSUM) != 0,
17824 tg3_flag(tp, USE_LINKCHG_REG) != 0,
17825 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
17826 tg3_flag(tp, ENABLE_ASF) != 0,
17827 tg3_flag(tp, TSO_CAPABLE) != 0);
17828 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17830 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17831 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
17833 pci_save_state(pdev);
17839 iounmap(tp->aperegs);
17840 tp->aperegs = NULL;
17853 pci_release_regions(pdev);
17855 err_out_disable_pdev:
17856 if (pci_is_enabled(pdev))
17857 pci_disable_device(pdev);
17861 static void tg3_remove_one(struct pci_dev *pdev)
17863 struct net_device *dev = pci_get_drvdata(pdev);
17866 struct tg3 *tp = netdev_priv(dev);
17868 release_firmware(tp->fw);
17870 tg3_reset_task_cancel(tp);
17872 if (tg3_flag(tp, USE_PHYLIB)) {
17877 unregister_netdev(dev);
17879 iounmap(tp->aperegs);
17880 tp->aperegs = NULL;
17887 pci_release_regions(pdev);
17888 pci_disable_device(pdev);
17892 #ifdef CONFIG_PM_SLEEP
17893 static int tg3_suspend(struct device *device)
17895 struct pci_dev *pdev = to_pci_dev(device);
17896 struct net_device *dev = pci_get_drvdata(pdev);
17897 struct tg3 *tp = netdev_priv(dev);
17902 if (!netif_running(dev))
17905 tg3_reset_task_cancel(tp);
17907 tg3_netif_stop(tp);
17909 tg3_timer_stop(tp);
17911 tg3_full_lock(tp, 1);
17912 tg3_disable_ints(tp);
17913 tg3_full_unlock(tp);
17915 netif_device_detach(dev);
17917 tg3_full_lock(tp, 0);
17918 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17919 tg3_flag_clear(tp, INIT_COMPLETE);
17920 tg3_full_unlock(tp);
17922 err = tg3_power_down_prepare(tp);
17926 tg3_full_lock(tp, 0);
17928 tg3_flag_set(tp, INIT_COMPLETE);
17929 err2 = tg3_restart_hw(tp, true);
17933 tg3_timer_start(tp);
17935 netif_device_attach(dev);
17936 tg3_netif_start(tp);
17939 tg3_full_unlock(tp);
17950 static int tg3_resume(struct device *device)
17952 struct pci_dev *pdev = to_pci_dev(device);
17953 struct net_device *dev = pci_get_drvdata(pdev);
17954 struct tg3 *tp = netdev_priv(dev);
17959 if (!netif_running(dev))
17962 netif_device_attach(dev);
17964 tg3_full_lock(tp, 0);
17966 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
17968 tg3_flag_set(tp, INIT_COMPLETE);
17969 err = tg3_restart_hw(tp,
17970 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
17974 tg3_timer_start(tp);
17976 tg3_netif_start(tp);
17979 tg3_full_unlock(tp);
17988 #endif /* CONFIG_PM_SLEEP */
17990 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
17992 static void tg3_shutdown(struct pci_dev *pdev)
17994 struct net_device *dev = pci_get_drvdata(pdev);
17995 struct tg3 *tp = netdev_priv(dev);
17998 netif_device_detach(dev);
18000 if (netif_running(dev))
18003 if (system_state == SYSTEM_POWER_OFF)
18004 tg3_power_down(tp);
18010 * tg3_io_error_detected - called when PCI error is detected
18011 * @pdev: Pointer to PCI device
18012 * @state: The current pci connection state
18014 * This function is called after a PCI bus error affecting
18015 * this device has been detected.
18017 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18018 pci_channel_state_t state)
18020 struct net_device *netdev = pci_get_drvdata(pdev);
18021 struct tg3 *tp = netdev_priv(netdev);
18022 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18024 netdev_info(netdev, "PCI I/O error detected\n");
18028 /* We probably don't have netdev yet */
18029 if (!netdev || !netif_running(netdev))
18034 tg3_netif_stop(tp);
18036 tg3_timer_stop(tp);
18038 /* Want to make sure that the reset task doesn't run */
18039 tg3_reset_task_cancel(tp);
18041 netif_device_detach(netdev);
18043 /* Clean up software state, even if MMIO is blocked */
18044 tg3_full_lock(tp, 0);
18045 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18046 tg3_full_unlock(tp);
18049 if (state == pci_channel_io_perm_failure) {
18051 tg3_napi_enable(tp);
18054 err = PCI_ERS_RESULT_DISCONNECT;
18056 pci_disable_device(pdev);
18065 * tg3_io_slot_reset - called after the pci bus has been reset.
18066 * @pdev: Pointer to PCI device
18068 * Restart the card from scratch, as if from a cold-boot.
18069 * At this point, the card has exprienced a hard reset,
18070 * followed by fixups by BIOS, and has its config space
18071 * set up identically to what it was at cold boot.
18073 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18075 struct net_device *netdev = pci_get_drvdata(pdev);
18076 struct tg3 *tp = netdev_priv(netdev);
18077 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18082 if (pci_enable_device(pdev)) {
18083 dev_err(&pdev->dev,
18084 "Cannot re-enable PCI device after reset.\n");
18088 pci_set_master(pdev);
18089 pci_restore_state(pdev);
18090 pci_save_state(pdev);
18092 if (!netdev || !netif_running(netdev)) {
18093 rc = PCI_ERS_RESULT_RECOVERED;
18097 err = tg3_power_up(tp);
18101 rc = PCI_ERS_RESULT_RECOVERED;
18104 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
18105 tg3_napi_enable(tp);
18114 * tg3_io_resume - called when traffic can start flowing again.
18115 * @pdev: Pointer to PCI device
18117 * This callback is called when the error recovery driver tells
18118 * us that its OK to resume normal operation.
18120 static void tg3_io_resume(struct pci_dev *pdev)
18122 struct net_device *netdev = pci_get_drvdata(pdev);
18123 struct tg3 *tp = netdev_priv(netdev);
18128 if (!netif_running(netdev))
18131 tg3_full_lock(tp, 0);
18132 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18133 tg3_flag_set(tp, INIT_COMPLETE);
18134 err = tg3_restart_hw(tp, true);
18136 tg3_full_unlock(tp);
18137 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18141 netif_device_attach(netdev);
18143 tg3_timer_start(tp);
18145 tg3_netif_start(tp);
18147 tg3_full_unlock(tp);
18155 static const struct pci_error_handlers tg3_err_handler = {
18156 .error_detected = tg3_io_error_detected,
18157 .slot_reset = tg3_io_slot_reset,
18158 .resume = tg3_io_resume
18161 static struct pci_driver tg3_driver = {
18162 .name = DRV_MODULE_NAME,
18163 .id_table = tg3_pci_tbl,
18164 .probe = tg3_init_one,
18165 .remove = tg3_remove_one,
18166 .err_handler = &tg3_err_handler,
18167 .driver.pm = &tg3_pm_ops,
18168 .shutdown = tg3_shutdown,
18171 module_pci_driver(tg3_driver);