2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2014 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #include <linux/ssb/ssb_driver_gige.h>
48 #include <linux/hwmon.h>
49 #include <linux/hwmon-sysfs.h>
51 #include <net/checksum.h>
55 #include <asm/byteorder.h>
56 #include <linux/uaccess.h>
58 #include <uapi/linux/net_tstamp.h>
59 #include <linux/ptp_clock_kernel.h>
62 #include <asm/idprom.h>
71 /* Functions & macros to verify TG3_FLAGS types */
73 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
75 return test_bit(flag, bits);
78 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
83 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
85 clear_bit(flag, bits);
88 #define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92 #define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define DRV_MODULE_NAME "tg3"
97 #define TG3_MIN_NUM 137
98 #define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
100 #define DRV_MODULE_RELDATE "May 11, 2014"
102 #define RESET_KIND_SHUTDOWN 0
103 #define RESET_KIND_INIT 1
104 #define RESET_KIND_SUSPEND 2
106 #define TG3_DEF_RX_MODE 0
107 #define TG3_DEF_TX_MODE 0
108 #define TG3_DEF_MSG_ENABLE \
118 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
120 /* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
124 #define TG3_TX_TIMEOUT (5 * HZ)
126 /* hardware minimum and maximum for a single frame's data payload */
127 #define TG3_MIN_MTU 60
128 #define TG3_MAX_MTU(tp) \
129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
131 /* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
135 #define TG3_RX_STD_RING_SIZE(tp) \
136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
138 #define TG3_DEF_RX_RING_PENDING 200
139 #define TG3_RX_JMB_RING_SIZE(tp) \
140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
142 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
144 /* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
151 #define TG3_TX_RING_SIZE 512
152 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
154 #define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156 #define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158 #define TG3_RX_RCB_RING_BYTES(tp) \
159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
160 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
162 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
164 #define TG3_DMA_BYTE_ENAB 64
166 #define TG3_RX_STD_DMA_SZ 1536
167 #define TG3_RX_JMB_DMA_SZ 9046
169 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
171 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
174 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
177 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
180 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
191 #define TG3_RX_COPY_THRESHOLD 256
192 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
198 #if (NET_IP_ALIGN != 0)
199 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
201 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
206 #define TG3_TX_BD_DMA_MAX_2K 2048
207 #define TG3_TX_BD_DMA_MAX_4K 4096
209 #define TG3_RAW_IP_ALIGN 2
211 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
212 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
214 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
215 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
217 #define FIRMWARE_TG3 "tigon/tg3.bin"
218 #define FIRMWARE_TG357766 "tigon/tg357766.bin"
219 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
220 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
222 static char version[] =
223 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
225 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
226 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
227 MODULE_LICENSE("GPL");
228 MODULE_VERSION(DRV_MODULE_VERSION);
229 MODULE_FIRMWARE(FIRMWARE_TG3);
230 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
231 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
233 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
234 module_param(tg3_debug, int, 0);
235 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
237 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
240 static const struct pci_device_id tg3_pci_tbl[] = {
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
263 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
264 TG3_DRV_DATA_FLAG_5705_10_100},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
267 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
268 TG3_DRV_DATA_FLAG_5705_10_100},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
275 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
281 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
289 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
290 PCI_VENDOR_ID_LENOVO,
291 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
295 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
318 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
319 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
323 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
333 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
335 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
348 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
354 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
359 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
361 static const struct {
362 const char string[ETH_GSTRING_LEN];
363 } ethtool_stats_keys[] = {
366 { "rx_ucast_packets" },
367 { "rx_mcast_packets" },
368 { "rx_bcast_packets" },
370 { "rx_align_errors" },
371 { "rx_xon_pause_rcvd" },
372 { "rx_xoff_pause_rcvd" },
373 { "rx_mac_ctrl_rcvd" },
374 { "rx_xoff_entered" },
375 { "rx_frame_too_long_errors" },
377 { "rx_undersize_packets" },
378 { "rx_in_length_errors" },
379 { "rx_out_length_errors" },
380 { "rx_64_or_less_octet_packets" },
381 { "rx_65_to_127_octet_packets" },
382 { "rx_128_to_255_octet_packets" },
383 { "rx_256_to_511_octet_packets" },
384 { "rx_512_to_1023_octet_packets" },
385 { "rx_1024_to_1522_octet_packets" },
386 { "rx_1523_to_2047_octet_packets" },
387 { "rx_2048_to_4095_octet_packets" },
388 { "rx_4096_to_8191_octet_packets" },
389 { "rx_8192_to_9022_octet_packets" },
396 { "tx_flow_control" },
398 { "tx_single_collisions" },
399 { "tx_mult_collisions" },
401 { "tx_excessive_collisions" },
402 { "tx_late_collisions" },
403 { "tx_collide_2times" },
404 { "tx_collide_3times" },
405 { "tx_collide_4times" },
406 { "tx_collide_5times" },
407 { "tx_collide_6times" },
408 { "tx_collide_7times" },
409 { "tx_collide_8times" },
410 { "tx_collide_9times" },
411 { "tx_collide_10times" },
412 { "tx_collide_11times" },
413 { "tx_collide_12times" },
414 { "tx_collide_13times" },
415 { "tx_collide_14times" },
416 { "tx_collide_15times" },
417 { "tx_ucast_packets" },
418 { "tx_mcast_packets" },
419 { "tx_bcast_packets" },
420 { "tx_carrier_sense_errors" },
424 { "dma_writeq_full" },
425 { "dma_write_prioq_full" },
429 { "rx_threshold_hit" },
431 { "dma_readq_full" },
432 { "dma_read_prioq_full" },
433 { "tx_comp_queue_full" },
435 { "ring_set_send_prod_index" },
436 { "ring_status_update" },
438 { "nic_avoided_irqs" },
439 { "nic_tx_threshold_hit" },
441 { "mbuf_lwm_thresh_hit" },
444 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
445 #define TG3_NVRAM_TEST 0
446 #define TG3_LINK_TEST 1
447 #define TG3_REGISTER_TEST 2
448 #define TG3_MEMORY_TEST 3
449 #define TG3_MAC_LOOPB_TEST 4
450 #define TG3_PHY_LOOPB_TEST 5
451 #define TG3_EXT_LOOPB_TEST 6
452 #define TG3_INTERRUPT_TEST 7
455 static const struct {
456 const char string[ETH_GSTRING_LEN];
457 } ethtool_test_keys[] = {
458 [TG3_NVRAM_TEST] = { "nvram test (online) " },
459 [TG3_LINK_TEST] = { "link test (online) " },
460 [TG3_REGISTER_TEST] = { "register test (offline)" },
461 [TG3_MEMORY_TEST] = { "memory test (offline)" },
462 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
463 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
464 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
465 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
468 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
471 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
473 writel(val, tp->regs + off);
476 static u32 tg3_read32(struct tg3 *tp, u32 off)
478 return readl(tp->regs + off);
481 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
483 writel(val, tp->aperegs + off);
486 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
488 return readl(tp->aperegs + off);
491 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
495 spin_lock_irqsave(&tp->indirect_lock, flags);
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
501 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
503 writel(val, tp->regs + off);
504 readl(tp->regs + off);
507 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
512 spin_lock_irqsave(&tp->indirect_lock, flags);
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
519 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
523 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
525 TG3_64BIT_REG_LOW, val);
528 if (off == TG3_RX_STD_PROD_IDX_REG) {
529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
530 TG3_64BIT_REG_LOW, val);
534 spin_lock_irqsave(&tp->indirect_lock, flags);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
537 spin_unlock_irqrestore(&tp->indirect_lock, flags);
539 /* In indirect mode when disabling interrupts, we also need
540 * to clear the interrupt bit in the GRC local ctrl register.
542 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
549 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
554 spin_lock_irqsave(&tp->indirect_lock, flags);
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
561 /* usec_wait specifies the wait time in usec when writing to certain registers
562 * where it is unsafe to read back the register without some delay.
563 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
564 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
566 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
569 /* Non-posted methods */
570 tp->write32(tp, off, val);
573 tg3_write32(tp, off, val);
578 /* Wait again after the read for the posted method to guarantee that
579 * the wait time is met.
585 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
587 tp->write32_mbox(tp, off, val);
588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
590 !tg3_flag(tp, ICH_WORKAROUND)))
591 tp->read32_mbox(tp, off);
594 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
596 void __iomem *mbox = tp->regs + off;
598 if (tg3_flag(tp, TXD_MBOX_HWBUG))
600 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
601 tg3_flag(tp, FLUSH_POSTED_WRITES))
605 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
607 return readl(tp->regs + off + GRCMBOX_BASE);
610 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
612 writel(val, tp->regs + off + GRCMBOX_BASE);
615 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
616 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
617 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
621 #define tw32(reg, val) tp->write32(tp, reg, val)
622 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624 #define tr32(reg) tp->read32(tp, reg)
626 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
630 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
631 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
634 spin_lock_irqsave(&tp->indirect_lock, flags);
635 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
639 /* Always leave this as zero. */
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
642 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
643 tw32_f(TG3PCI_MEM_WIN_DATA, val);
645 /* Always leave this as zero. */
646 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
648 spin_unlock_irqrestore(&tp->indirect_lock, flags);
651 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
655 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
656 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
661 spin_lock_irqsave(&tp->indirect_lock, flags);
662 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
666 /* Always leave this as zero. */
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
669 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
670 *val = tr32(TG3PCI_MEM_WIN_DATA);
672 /* Always leave this as zero. */
673 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
675 spin_unlock_irqrestore(&tp->indirect_lock, flags);
678 static void tg3_ape_lock_init(struct tg3 *tp)
683 if (tg3_asic_rev(tp) == ASIC_REV_5761)
684 regbase = TG3_APE_LOCK_GRANT;
686 regbase = TG3_APE_PER_LOCK_GRANT;
688 /* Make sure the driver hasn't any stale locks. */
689 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
691 case TG3_APE_LOCK_PHY0:
692 case TG3_APE_LOCK_PHY1:
693 case TG3_APE_LOCK_PHY2:
694 case TG3_APE_LOCK_PHY3:
695 bit = APE_LOCK_GRANT_DRIVER;
699 bit = APE_LOCK_GRANT_DRIVER;
701 bit = 1 << tp->pci_fn;
703 tg3_ape_write32(tp, regbase + 4 * i, bit);
708 static int tg3_ape_lock(struct tg3 *tp, int locknum)
712 u32 status, req, gnt, bit;
714 if (!tg3_flag(tp, ENABLE_APE))
718 case TG3_APE_LOCK_GPIO:
719 if (tg3_asic_rev(tp) == ASIC_REV_5761)
721 case TG3_APE_LOCK_GRC:
722 case TG3_APE_LOCK_MEM:
724 bit = APE_LOCK_REQ_DRIVER;
726 bit = 1 << tp->pci_fn;
728 case TG3_APE_LOCK_PHY0:
729 case TG3_APE_LOCK_PHY1:
730 case TG3_APE_LOCK_PHY2:
731 case TG3_APE_LOCK_PHY3:
732 bit = APE_LOCK_REQ_DRIVER;
738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
739 req = TG3_APE_LOCK_REQ;
740 gnt = TG3_APE_LOCK_GRANT;
742 req = TG3_APE_PER_LOCK_REQ;
743 gnt = TG3_APE_PER_LOCK_GRANT;
748 tg3_ape_write32(tp, req + off, bit);
750 /* Wait for up to 1 millisecond to acquire lock. */
751 for (i = 0; i < 100; i++) {
752 status = tg3_ape_read32(tp, gnt + off);
755 if (pci_channel_offline(tp->pdev))
762 /* Revoke the lock request. */
763 tg3_ape_write32(tp, gnt + off, bit);
770 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
774 if (!tg3_flag(tp, ENABLE_APE))
778 case TG3_APE_LOCK_GPIO:
779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
781 case TG3_APE_LOCK_GRC:
782 case TG3_APE_LOCK_MEM:
784 bit = APE_LOCK_GRANT_DRIVER;
786 bit = 1 << tp->pci_fn;
788 case TG3_APE_LOCK_PHY0:
789 case TG3_APE_LOCK_PHY1:
790 case TG3_APE_LOCK_PHY2:
791 case TG3_APE_LOCK_PHY3:
792 bit = APE_LOCK_GRANT_DRIVER;
798 if (tg3_asic_rev(tp) == ASIC_REV_5761)
799 gnt = TG3_APE_LOCK_GRANT;
801 gnt = TG3_APE_PER_LOCK_GRANT;
803 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
806 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
815 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
821 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
824 return timeout_us ? 0 : -EBUSY;
827 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
831 for (i = 0; i < timeout_us / 10; i++) {
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
834 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
840 return i == timeout_us / 10;
843 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
847 u32 i, bufoff, msgoff, maxlen, apedata;
849 if (!tg3_flag(tp, APE_HAS_NCSI))
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
853 if (apedata != APE_SEG_SIG_MAGIC)
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
857 if (!(apedata & APE_FW_STATUS_READY))
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
862 msgoff = bufoff + 2 * sizeof(u32);
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
868 /* Cap xfer sizes to scratchpad limits. */
869 length = (len > maxlen) ? maxlen : len;
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
873 if (!(apedata & APE_FW_STATUS_READY))
876 /* Wait for up to 1 msec for APE to service previous event. */
877 err = tg3_ape_event_lock(tp, 1000);
881 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
882 APE_EVENT_STATUS_SCRTCHPD_READ |
883 APE_EVENT_STATUS_EVENT_PENDING;
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
886 tg3_ape_write32(tp, bufoff, base_off);
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
894 if (tg3_ape_wait_for_event(tp, 30000))
897 for (i = 0; length; i += 4, length -= 4) {
898 u32 val = tg3_ape_read32(tp, msgoff + i);
899 memcpy(data, &val, sizeof(u32));
907 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
912 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
913 if (apedata != APE_SEG_SIG_MAGIC)
916 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
917 if (!(apedata & APE_FW_STATUS_READY))
920 /* Wait for up to 1 millisecond for APE to service previous event. */
921 err = tg3_ape_event_lock(tp, 1000);
925 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
926 event | APE_EVENT_STATUS_EVENT_PENDING);
928 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
929 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
934 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
939 if (!tg3_flag(tp, ENABLE_APE))
943 case RESET_KIND_INIT:
944 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
945 APE_HOST_SEG_SIG_MAGIC);
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
947 APE_HOST_SEG_LEN_MAGIC);
948 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
949 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
950 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
951 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
952 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
953 APE_HOST_BEHAV_NO_PHYLOCK);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
955 TG3_APE_HOST_DRVR_STATE_START);
957 event = APE_EVENT_STATUS_STATE_START;
959 case RESET_KIND_SHUTDOWN:
960 /* With the interface we are currently using,
961 * APE does not track driver state. Wiping
962 * out the HOST SEGMENT SIGNATURE forces
963 * the APE to assume OS absent status.
965 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
967 if (device_may_wakeup(&tp->pdev->dev) &&
968 tg3_flag(tp, WOL_ENABLE)) {
969 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
970 TG3_APE_HOST_WOL_SPEED_AUTO);
971 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
973 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
975 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
977 event = APE_EVENT_STATUS_STATE_UNLOAD;
983 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
985 tg3_ape_send_event(tp, event);
988 static void tg3_disable_ints(struct tg3 *tp)
992 tw32(TG3PCI_MISC_HOST_CTRL,
993 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
994 for (i = 0; i < tp->irq_max; i++)
995 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
998 static void tg3_enable_ints(struct tg3 *tp)
1005 tw32(TG3PCI_MISC_HOST_CTRL,
1006 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1008 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1009 for (i = 0; i < tp->irq_cnt; i++) {
1010 struct tg3_napi *tnapi = &tp->napi[i];
1012 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1013 if (tg3_flag(tp, 1SHOT_MSI))
1014 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1016 tp->coal_now |= tnapi->coal_now;
1019 /* Force an initial interrupt */
1020 if (!tg3_flag(tp, TAGGED_STATUS) &&
1021 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1022 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1024 tw32(HOSTCC_MODE, tp->coal_now);
1026 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1029 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1031 struct tg3 *tp = tnapi->tp;
1032 struct tg3_hw_status *sblk = tnapi->hw_status;
1033 unsigned int work_exists = 0;
1035 /* check for phy events */
1036 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1037 if (sblk->status & SD_STATUS_LINK_CHG)
1041 /* check for TX work to do */
1042 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1045 /* check for RX work to do */
1046 if (tnapi->rx_rcb_prod_idx &&
1047 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1054 * similar to tg3_enable_ints, but it accurately determines whether there
1055 * is new work pending and can return without flushing the PIO write
1056 * which reenables interrupts
1058 static void tg3_int_reenable(struct tg3_napi *tnapi)
1060 struct tg3 *tp = tnapi->tp;
1062 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1065 /* When doing tagged status, this work check is unnecessary.
1066 * The last_tag we write above tells the chip which piece of
1067 * work we've completed.
1069 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1070 tw32(HOSTCC_MODE, tp->coalesce_mode |
1071 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1074 static void tg3_switch_clocks(struct tg3 *tp)
1077 u32 orig_clock_ctrl;
1079 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1082 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1084 orig_clock_ctrl = clock_ctrl;
1085 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1086 CLOCK_CTRL_CLKRUN_OENABLE |
1088 tp->pci_clock_ctrl = clock_ctrl;
1090 if (tg3_flag(tp, 5705_PLUS)) {
1091 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1095 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1096 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1098 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1100 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1101 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1104 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1107 #define PHY_BUSY_LOOPS 5000
1109 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1116 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1118 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1122 tg3_ape_lock(tp, tp->phy_ape_lock);
1126 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1132 tw32_f(MAC_MI_COM, frame_val);
1134 loops = PHY_BUSY_LOOPS;
1135 while (loops != 0) {
1137 frame_val = tr32(MAC_MI_COM);
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1141 frame_val = tr32(MAC_MI_COM);
1149 *val = frame_val & MI_COM_DATA_MASK;
1153 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1154 tw32_f(MAC_MI_MODE, tp->mi_mode);
1158 tg3_ape_unlock(tp, tp->phy_ape_lock);
1163 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1165 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1168 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1176 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1179 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1181 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1185 tg3_ape_lock(tp, tp->phy_ape_lock);
1187 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1188 MI_COM_PHY_ADDR_MASK);
1189 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1190 MI_COM_REG_ADDR_MASK);
1191 frame_val |= (val & MI_COM_DATA_MASK);
1192 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1194 tw32_f(MAC_MI_COM, frame_val);
1196 loops = PHY_BUSY_LOOPS;
1197 while (loops != 0) {
1199 frame_val = tr32(MAC_MI_COM);
1200 if ((frame_val & MI_COM_BUSY) == 0) {
1202 frame_val = tr32(MAC_MI_COM);
1212 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1213 tw32_f(MAC_MI_MODE, tp->mi_mode);
1217 tg3_ape_unlock(tp, tp->phy_ape_lock);
1222 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1224 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1227 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1240 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1250 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1263 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1267 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1273 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1279 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1284 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1295 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1300 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1301 MII_TG3_AUXCTL_SHDWSEL_MISC);
1303 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1308 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1310 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1311 set |= MII_TG3_AUXCTL_MISC_WREN;
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1316 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1321 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1327 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1329 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1331 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1332 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1337 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1340 reg | val | MII_TG3_MISC_SHDW_WREN);
1343 static int tg3_bmcr_reset(struct tg3 *tp)
1348 /* OK, reset it, and poll the BMCR_RESET bit until it
1349 * clears or we time out.
1351 phy_control = BMCR_RESET;
1352 err = tg3_writephy(tp, MII_BMCR, phy_control);
1358 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1362 if ((phy_control & BMCR_RESET) == 0) {
1374 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1376 struct tg3 *tp = bp->priv;
1379 spin_lock_bh(&tp->lock);
1381 if (__tg3_readphy(tp, mii_id, reg, &val))
1384 spin_unlock_bh(&tp->lock);
1389 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1391 struct tg3 *tp = bp->priv;
1394 spin_lock_bh(&tp->lock);
1396 if (__tg3_writephy(tp, mii_id, reg, val))
1399 spin_unlock_bh(&tp->lock);
1404 static void tg3_mdio_config_5785(struct tg3 *tp)
1407 struct phy_device *phydev;
1409 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1410 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1411 case PHY_ID_BCM50610:
1412 case PHY_ID_BCM50610M:
1413 val = MAC_PHYCFG2_50610_LED_MODES;
1415 case PHY_ID_BCMAC131:
1416 val = MAC_PHYCFG2_AC131_LED_MODES;
1418 case PHY_ID_RTL8211C:
1419 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1421 case PHY_ID_RTL8201E:
1422 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1428 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1429 tw32(MAC_PHYCFG2, val);
1431 val = tr32(MAC_PHYCFG1);
1432 val &= ~(MAC_PHYCFG1_RGMII_INT |
1433 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1434 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1435 tw32(MAC_PHYCFG1, val);
1440 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1441 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1442 MAC_PHYCFG2_FMODE_MASK_MASK |
1443 MAC_PHYCFG2_GMODE_MASK_MASK |
1444 MAC_PHYCFG2_ACT_MASK_MASK |
1445 MAC_PHYCFG2_QUAL_MASK_MASK |
1446 MAC_PHYCFG2_INBAND_ENABLE;
1448 tw32(MAC_PHYCFG2, val);
1450 val = tr32(MAC_PHYCFG1);
1451 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1452 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1453 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1454 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1455 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1456 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1457 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1459 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1460 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1461 tw32(MAC_PHYCFG1, val);
1463 val = tr32(MAC_EXT_RGMII_MODE);
1464 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1465 MAC_RGMII_MODE_RX_QUALITY |
1466 MAC_RGMII_MODE_RX_ACTIVITY |
1467 MAC_RGMII_MODE_RX_ENG_DET |
1468 MAC_RGMII_MODE_TX_ENABLE |
1469 MAC_RGMII_MODE_TX_LOWPWR |
1470 MAC_RGMII_MODE_TX_RESET);
1471 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1472 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1473 val |= MAC_RGMII_MODE_RX_INT_B |
1474 MAC_RGMII_MODE_RX_QUALITY |
1475 MAC_RGMII_MODE_RX_ACTIVITY |
1476 MAC_RGMII_MODE_RX_ENG_DET;
1477 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1478 val |= MAC_RGMII_MODE_TX_ENABLE |
1479 MAC_RGMII_MODE_TX_LOWPWR |
1480 MAC_RGMII_MODE_TX_RESET;
1482 tw32(MAC_EXT_RGMII_MODE, val);
1485 static void tg3_mdio_start(struct tg3 *tp)
1487 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1488 tw32_f(MAC_MI_MODE, tp->mi_mode);
1491 if (tg3_flag(tp, MDIOBUS_INITED) &&
1492 tg3_asic_rev(tp) == ASIC_REV_5785)
1493 tg3_mdio_config_5785(tp);
1496 static int tg3_mdio_init(struct tg3 *tp)
1500 struct phy_device *phydev;
1502 if (tg3_flag(tp, 5717_PLUS)) {
1505 tp->phy_addr = tp->pci_fn + 1;
1507 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1508 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1510 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1511 TG3_CPMU_PHY_STRAP_IS_SERDES;
1514 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1517 addr = ssb_gige_get_phyaddr(tp->pdev);
1520 tp->phy_addr = addr;
1522 tp->phy_addr = TG3_PHY_MII_ADDR;
1526 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1529 tp->mdio_bus = mdiobus_alloc();
1530 if (tp->mdio_bus == NULL)
1533 tp->mdio_bus->name = "tg3 mdio bus";
1534 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1535 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1536 tp->mdio_bus->priv = tp;
1537 tp->mdio_bus->parent = &tp->pdev->dev;
1538 tp->mdio_bus->read = &tg3_mdio_read;
1539 tp->mdio_bus->write = &tg3_mdio_write;
1540 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1541 tp->mdio_bus->irq = &tp->mdio_irq[0];
1543 for (i = 0; i < PHY_MAX_ADDR; i++)
1544 tp->mdio_bus->irq[i] = PHY_POLL;
1546 /* The bus registration will look for all the PHYs on the mdio bus.
1547 * Unfortunately, it does not ensure the PHY is powered up before
1548 * accessing the PHY ID registers. A chip reset is the
1549 * quickest way to bring the device back to an operational state..
1551 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1554 i = mdiobus_register(tp->mdio_bus);
1556 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1557 mdiobus_free(tp->mdio_bus);
1561 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1563 if (!phydev || !phydev->drv) {
1564 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1565 mdiobus_unregister(tp->mdio_bus);
1566 mdiobus_free(tp->mdio_bus);
1570 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1571 case PHY_ID_BCM57780:
1572 phydev->interface = PHY_INTERFACE_MODE_GMII;
1573 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1575 case PHY_ID_BCM50610:
1576 case PHY_ID_BCM50610M:
1577 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1578 PHY_BRCM_RX_REFCLK_UNUSED |
1579 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1580 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1581 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1582 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1583 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1584 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1585 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1586 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1588 case PHY_ID_RTL8211C:
1589 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1591 case PHY_ID_RTL8201E:
1592 case PHY_ID_BCMAC131:
1593 phydev->interface = PHY_INTERFACE_MODE_MII;
1594 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1595 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1599 tg3_flag_set(tp, MDIOBUS_INITED);
1601 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1602 tg3_mdio_config_5785(tp);
1607 static void tg3_mdio_fini(struct tg3 *tp)
1609 if (tg3_flag(tp, MDIOBUS_INITED)) {
1610 tg3_flag_clear(tp, MDIOBUS_INITED);
1611 mdiobus_unregister(tp->mdio_bus);
1612 mdiobus_free(tp->mdio_bus);
1616 /* tp->lock is held. */
1617 static inline void tg3_generate_fw_event(struct tg3 *tp)
1621 val = tr32(GRC_RX_CPU_EVENT);
1622 val |= GRC_RX_CPU_DRIVER_EVENT;
1623 tw32_f(GRC_RX_CPU_EVENT, val);
1625 tp->last_event_jiffies = jiffies;
1628 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1630 /* tp->lock is held. */
1631 static void tg3_wait_for_event_ack(struct tg3 *tp)
1634 unsigned int delay_cnt;
1637 /* If enough time has passed, no wait is necessary. */
1638 time_remain = (long)(tp->last_event_jiffies + 1 +
1639 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1641 if (time_remain < 0)
1644 /* Check if we can shorten the wait time. */
1645 delay_cnt = jiffies_to_usecs(time_remain);
1646 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1647 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1648 delay_cnt = (delay_cnt >> 3) + 1;
1650 for (i = 0; i < delay_cnt; i++) {
1651 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1653 if (pci_channel_offline(tp->pdev))
1660 /* tp->lock is held. */
1661 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1666 if (!tg3_readphy(tp, MII_BMCR, ®))
1668 if (!tg3_readphy(tp, MII_BMSR, ®))
1669 val |= (reg & 0xffff);
1673 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1675 if (!tg3_readphy(tp, MII_LPA, ®))
1676 val |= (reg & 0xffff);
1680 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1681 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1683 if (!tg3_readphy(tp, MII_STAT1000, ®))
1684 val |= (reg & 0xffff);
1688 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1695 /* tp->lock is held. */
1696 static void tg3_ump_link_report(struct tg3 *tp)
1700 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1703 tg3_phy_gather_ump_data(tp, data);
1705 tg3_wait_for_event_ack(tp);
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1711 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1714 tg3_generate_fw_event(tp);
1717 /* tp->lock is held. */
1718 static void tg3_stop_fw(struct tg3 *tp)
1720 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1721 /* Wait for RX cpu to ACK the previous event. */
1722 tg3_wait_for_event_ack(tp);
1724 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1726 tg3_generate_fw_event(tp);
1728 /* Wait for RX cpu to ACK this event. */
1729 tg3_wait_for_event_ack(tp);
1733 /* tp->lock is held. */
1734 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1736 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1737 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1739 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1741 case RESET_KIND_INIT:
1742 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1746 case RESET_KIND_SHUTDOWN:
1747 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1751 case RESET_KIND_SUSPEND:
1752 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1762 /* tp->lock is held. */
1763 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1765 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1767 case RESET_KIND_INIT:
1768 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1769 DRV_STATE_START_DONE);
1772 case RESET_KIND_SHUTDOWN:
1773 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1774 DRV_STATE_UNLOAD_DONE);
1783 /* tp->lock is held. */
1784 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1786 if (tg3_flag(tp, ENABLE_ASF)) {
1788 case RESET_KIND_INIT:
1789 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1793 case RESET_KIND_SHUTDOWN:
1794 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1798 case RESET_KIND_SUSPEND:
1799 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1809 static int tg3_poll_fw(struct tg3 *tp)
1814 if (tg3_flag(tp, NO_FWARE_REPORTED))
1817 if (tg3_flag(tp, IS_SSB_CORE)) {
1818 /* We don't use firmware. */
1822 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1823 /* Wait up to 20ms for init done. */
1824 for (i = 0; i < 200; i++) {
1825 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1827 if (pci_channel_offline(tp->pdev))
1835 /* Wait for firmware initialization to complete. */
1836 for (i = 0; i < 100000; i++) {
1837 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1838 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1840 if (pci_channel_offline(tp->pdev)) {
1841 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1842 tg3_flag_set(tp, NO_FWARE_REPORTED);
1843 netdev_info(tp->dev, "No firmware running\n");
1852 /* Chip might not be fitted with firmware. Some Sun onboard
1853 * parts are configured like that. So don't signal the timeout
1854 * of the above loop as an error, but do report the lack of
1855 * running firmware once.
1857 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1858 tg3_flag_set(tp, NO_FWARE_REPORTED);
1860 netdev_info(tp->dev, "No firmware running\n");
1863 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1864 /* The 57765 A0 needs a little more
1865 * time to do some important work.
1873 static void tg3_link_report(struct tg3 *tp)
1875 if (!netif_carrier_ok(tp->dev)) {
1876 netif_info(tp, link, tp->dev, "Link is down\n");
1877 tg3_ump_link_report(tp);
1878 } else if (netif_msg_link(tp)) {
1879 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1880 (tp->link_config.active_speed == SPEED_1000 ?
1882 (tp->link_config.active_speed == SPEED_100 ?
1884 (tp->link_config.active_duplex == DUPLEX_FULL ?
1887 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1888 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1890 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1893 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1894 netdev_info(tp->dev, "EEE is %s\n",
1895 tp->setlpicnt ? "enabled" : "disabled");
1897 tg3_ump_link_report(tp);
1900 tp->link_up = netif_carrier_ok(tp->dev);
1903 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1907 if (adv & ADVERTISE_PAUSE_CAP) {
1908 flowctrl |= FLOW_CTRL_RX;
1909 if (!(adv & ADVERTISE_PAUSE_ASYM))
1910 flowctrl |= FLOW_CTRL_TX;
1911 } else if (adv & ADVERTISE_PAUSE_ASYM)
1912 flowctrl |= FLOW_CTRL_TX;
1917 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1921 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1922 miireg = ADVERTISE_1000XPAUSE;
1923 else if (flow_ctrl & FLOW_CTRL_TX)
1924 miireg = ADVERTISE_1000XPSE_ASYM;
1925 else if (flow_ctrl & FLOW_CTRL_RX)
1926 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1933 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1937 if (adv & ADVERTISE_1000XPAUSE) {
1938 flowctrl |= FLOW_CTRL_RX;
1939 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1940 flowctrl |= FLOW_CTRL_TX;
1941 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1942 flowctrl |= FLOW_CTRL_TX;
1947 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1951 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1952 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1953 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1954 if (lcladv & ADVERTISE_1000XPAUSE)
1956 if (rmtadv & ADVERTISE_1000XPAUSE)
1963 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1967 u32 old_rx_mode = tp->rx_mode;
1968 u32 old_tx_mode = tp->tx_mode;
1970 if (tg3_flag(tp, USE_PHYLIB))
1971 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
1973 autoneg = tp->link_config.autoneg;
1975 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1976 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1977 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1979 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1981 flowctrl = tp->link_config.flowctrl;
1983 tp->link_config.active_flowctrl = flowctrl;
1985 if (flowctrl & FLOW_CTRL_RX)
1986 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1988 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1990 if (old_rx_mode != tp->rx_mode)
1991 tw32_f(MAC_RX_MODE, tp->rx_mode);
1993 if (flowctrl & FLOW_CTRL_TX)
1994 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1996 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1998 if (old_tx_mode != tp->tx_mode)
1999 tw32_f(MAC_TX_MODE, tp->tx_mode);
2002 static void tg3_adjust_link(struct net_device *dev)
2004 u8 oldflowctrl, linkmesg = 0;
2005 u32 mac_mode, lcl_adv, rmt_adv;
2006 struct tg3 *tp = netdev_priv(dev);
2007 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2009 spin_lock_bh(&tp->lock);
2011 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2012 MAC_MODE_HALF_DUPLEX);
2014 oldflowctrl = tp->link_config.active_flowctrl;
2020 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2021 mac_mode |= MAC_MODE_PORT_MODE_MII;
2022 else if (phydev->speed == SPEED_1000 ||
2023 tg3_asic_rev(tp) != ASIC_REV_5785)
2024 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2026 mac_mode |= MAC_MODE_PORT_MODE_MII;
2028 if (phydev->duplex == DUPLEX_HALF)
2029 mac_mode |= MAC_MODE_HALF_DUPLEX;
2031 lcl_adv = mii_advertise_flowctrl(
2032 tp->link_config.flowctrl);
2035 rmt_adv = LPA_PAUSE_CAP;
2036 if (phydev->asym_pause)
2037 rmt_adv |= LPA_PAUSE_ASYM;
2040 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2042 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2044 if (mac_mode != tp->mac_mode) {
2045 tp->mac_mode = mac_mode;
2046 tw32_f(MAC_MODE, tp->mac_mode);
2050 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2051 if (phydev->speed == SPEED_10)
2053 MAC_MI_STAT_10MBPS_MODE |
2054 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2056 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2059 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2060 tw32(MAC_TX_LENGTHS,
2061 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2062 (6 << TX_LENGTHS_IPG_SHIFT) |
2063 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2065 tw32(MAC_TX_LENGTHS,
2066 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2067 (6 << TX_LENGTHS_IPG_SHIFT) |
2068 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2070 if (phydev->link != tp->old_link ||
2071 phydev->speed != tp->link_config.active_speed ||
2072 phydev->duplex != tp->link_config.active_duplex ||
2073 oldflowctrl != tp->link_config.active_flowctrl)
2076 tp->old_link = phydev->link;
2077 tp->link_config.active_speed = phydev->speed;
2078 tp->link_config.active_duplex = phydev->duplex;
2080 spin_unlock_bh(&tp->lock);
2083 tg3_link_report(tp);
2086 static int tg3_phy_init(struct tg3 *tp)
2088 struct phy_device *phydev;
2090 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2093 /* Bring the PHY back to a known state. */
2096 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2098 /* Attach the MAC to the PHY. */
2099 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2100 tg3_adjust_link, phydev->interface);
2101 if (IS_ERR(phydev)) {
2102 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2103 return PTR_ERR(phydev);
2106 /* Mask with MAC supported features. */
2107 switch (phydev->interface) {
2108 case PHY_INTERFACE_MODE_GMII:
2109 case PHY_INTERFACE_MODE_RGMII:
2110 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2111 phydev->supported &= (PHY_GBIT_FEATURES |
2113 SUPPORTED_Asym_Pause);
2117 case PHY_INTERFACE_MODE_MII:
2118 phydev->supported &= (PHY_BASIC_FEATURES |
2120 SUPPORTED_Asym_Pause);
2123 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2127 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2129 phydev->advertising = phydev->supported;
2134 static void tg3_phy_start(struct tg3 *tp)
2136 struct phy_device *phydev;
2138 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2141 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2143 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2144 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2145 phydev->speed = tp->link_config.speed;
2146 phydev->duplex = tp->link_config.duplex;
2147 phydev->autoneg = tp->link_config.autoneg;
2148 phydev->advertising = tp->link_config.advertising;
2153 phy_start_aneg(phydev);
2156 static void tg3_phy_stop(struct tg3 *tp)
2158 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2161 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
2164 static void tg3_phy_fini(struct tg3 *tp)
2166 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2167 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2168 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2172 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2177 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2180 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2181 /* Cannot do read-modify-write on 5401 */
2182 err = tg3_phy_auxctl_write(tp,
2183 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2184 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2189 err = tg3_phy_auxctl_read(tp,
2190 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2194 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2195 err = tg3_phy_auxctl_write(tp,
2196 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2202 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2206 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2209 tg3_writephy(tp, MII_TG3_FET_TEST,
2210 phytest | MII_TG3_FET_SHADOW_EN);
2211 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2213 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2215 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2216 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2218 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2222 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2226 if (!tg3_flag(tp, 5705_PLUS) ||
2227 (tg3_flag(tp, 5717_PLUS) &&
2228 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2231 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2232 tg3_phy_fet_toggle_apd(tp, enable);
2236 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2237 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2238 MII_TG3_MISC_SHDW_SCR5_SDTL |
2239 MII_TG3_MISC_SHDW_SCR5_C125OE;
2240 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2241 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2243 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2246 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2248 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2250 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2253 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2257 if (!tg3_flag(tp, 5705_PLUS) ||
2258 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2261 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2264 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2265 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2267 tg3_writephy(tp, MII_TG3_FET_TEST,
2268 ephy | MII_TG3_FET_SHADOW_EN);
2269 if (!tg3_readphy(tp, reg, &phy)) {
2271 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2273 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2274 tg3_writephy(tp, reg, phy);
2276 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2281 ret = tg3_phy_auxctl_read(tp,
2282 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2285 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2287 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2288 tg3_phy_auxctl_write(tp,
2289 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2294 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2299 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2302 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2304 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2305 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2308 static void tg3_phy_apply_otp(struct tg3 *tp)
2317 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2320 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2321 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2322 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2324 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2325 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2328 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2329 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2330 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2332 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2333 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2335 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2338 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2339 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2340 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2342 tg3_phy_toggle_auxctl_smdsp(tp, false);
2345 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2348 struct ethtool_eee *dest = &tp->eee;
2350 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2356 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2359 /* Pull eee_active */
2360 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2361 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2362 dest->eee_active = 1;
2364 dest->eee_active = 0;
2366 /* Pull lp advertised settings */
2367 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2369 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2371 /* Pull advertised and eee_enabled settings */
2372 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2374 dest->eee_enabled = !!val;
2375 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2377 /* Pull tx_lpi_enabled */
2378 val = tr32(TG3_CPMU_EEE_MODE);
2379 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2381 /* Pull lpi timer value */
2382 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2385 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2389 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2394 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2396 tp->link_config.active_duplex == DUPLEX_FULL &&
2397 (tp->link_config.active_speed == SPEED_100 ||
2398 tp->link_config.active_speed == SPEED_1000)) {
2401 if (tp->link_config.active_speed == SPEED_1000)
2402 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2404 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2406 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2408 tg3_eee_pull_config(tp, NULL);
2409 if (tp->eee.eee_active)
2413 if (!tp->setlpicnt) {
2414 if (current_link_up &&
2415 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2416 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2417 tg3_phy_toggle_auxctl_smdsp(tp, false);
2420 val = tr32(TG3_CPMU_EEE_MODE);
2421 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2425 static void tg3_phy_eee_enable(struct tg3 *tp)
2429 if (tp->link_config.active_speed == SPEED_1000 &&
2430 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2431 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2432 tg3_flag(tp, 57765_CLASS)) &&
2433 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2434 val = MII_TG3_DSP_TAP26_ALNOKO |
2435 MII_TG3_DSP_TAP26_RMRXSTO;
2436 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2437 tg3_phy_toggle_auxctl_smdsp(tp, false);
2440 val = tr32(TG3_CPMU_EEE_MODE);
2441 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2444 static int tg3_wait_macro_done(struct tg3 *tp)
2451 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2452 if ((tmp32 & 0x1000) == 0)
2462 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2464 static const u32 test_pat[4][6] = {
2465 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2466 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2467 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2468 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2472 for (chan = 0; chan < 4; chan++) {
2475 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2476 (chan * 0x2000) | 0x0200);
2477 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2479 for (i = 0; i < 6; i++)
2480 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2483 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2484 if (tg3_wait_macro_done(tp)) {
2489 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2490 (chan * 0x2000) | 0x0200);
2491 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2492 if (tg3_wait_macro_done(tp)) {
2497 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2498 if (tg3_wait_macro_done(tp)) {
2503 for (i = 0; i < 6; i += 2) {
2506 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2507 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2508 tg3_wait_macro_done(tp)) {
2514 if (low != test_pat[chan][i] ||
2515 high != test_pat[chan][i+1]) {
2516 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2517 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2518 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2528 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2532 for (chan = 0; chan < 4; chan++) {
2535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2536 (chan * 0x2000) | 0x0200);
2537 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2538 for (i = 0; i < 6; i++)
2539 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2540 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2541 if (tg3_wait_macro_done(tp))
2548 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2550 u32 reg32, phy9_orig;
2551 int retries, do_phy_reset, err;
2557 err = tg3_bmcr_reset(tp);
2563 /* Disable transmitter and interrupt. */
2564 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2568 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2570 /* Set full-duplex, 1000 mbps. */
2571 tg3_writephy(tp, MII_BMCR,
2572 BMCR_FULLDPLX | BMCR_SPEED1000);
2574 /* Set to master mode. */
2575 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2578 tg3_writephy(tp, MII_CTRL1000,
2579 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2581 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2585 /* Block the PHY control access. */
2586 tg3_phydsp_write(tp, 0x8005, 0x0800);
2588 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2591 } while (--retries);
2593 err = tg3_phy_reset_chanpat(tp);
2597 tg3_phydsp_write(tp, 0x8005, 0x0000);
2599 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2600 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2602 tg3_phy_toggle_auxctl_smdsp(tp, false);
2604 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2606 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2611 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2616 static void tg3_carrier_off(struct tg3 *tp)
2618 netif_carrier_off(tp->dev);
2619 tp->link_up = false;
2622 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2624 if (tg3_flag(tp, ENABLE_ASF))
2625 netdev_warn(tp->dev,
2626 "Management side-band traffic will be interrupted during phy settings change\n");
2629 /* This will reset the tigon3 PHY if there is no valid
2630 * link unless the FORCE argument is non-zero.
2632 static int tg3_phy_reset(struct tg3 *tp)
2637 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2638 val = tr32(GRC_MISC_CFG);
2639 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2642 err = tg3_readphy(tp, MII_BMSR, &val);
2643 err |= tg3_readphy(tp, MII_BMSR, &val);
2647 if (netif_running(tp->dev) && tp->link_up) {
2648 netif_carrier_off(tp->dev);
2649 tg3_link_report(tp);
2652 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2653 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2654 tg3_asic_rev(tp) == ASIC_REV_5705) {
2655 err = tg3_phy_reset_5703_4_5(tp);
2662 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2663 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2664 cpmuctrl = tr32(TG3_CPMU_CTRL);
2665 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2667 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2670 err = tg3_bmcr_reset(tp);
2674 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2675 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2678 tw32(TG3_CPMU_CTRL, cpmuctrl);
2681 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2682 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2683 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2684 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2685 CPMU_LSPD_1000MB_MACCLK_12_5) {
2686 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2688 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2692 if (tg3_flag(tp, 5717_PLUS) &&
2693 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2696 tg3_phy_apply_otp(tp);
2698 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2699 tg3_phy_toggle_apd(tp, true);
2701 tg3_phy_toggle_apd(tp, false);
2704 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2705 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2706 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2707 tg3_phydsp_write(tp, 0x000a, 0x0323);
2708 tg3_phy_toggle_auxctl_smdsp(tp, false);
2711 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2712 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2713 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2716 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2717 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2718 tg3_phydsp_write(tp, 0x000a, 0x310b);
2719 tg3_phydsp_write(tp, 0x201f, 0x9506);
2720 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2721 tg3_phy_toggle_auxctl_smdsp(tp, false);
2723 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2724 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2725 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2726 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2728 tg3_writephy(tp, MII_TG3_TEST1,
2729 MII_TG3_TEST1_TRIM_EN | 0x4);
2731 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2733 tg3_phy_toggle_auxctl_smdsp(tp, false);
2737 /* Set Extended packet length bit (bit 14) on all chips that */
2738 /* support jumbo frames */
2739 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2740 /* Cannot do read-modify-write on 5401 */
2741 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2742 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2743 /* Set bit 14 with read-modify-write to preserve other bits */
2744 err = tg3_phy_auxctl_read(tp,
2745 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2747 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2748 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2751 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2752 * jumbo frames transmission.
2754 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2755 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2756 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2757 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2760 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2761 /* adjust output voltage */
2762 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2765 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2766 tg3_phydsp_write(tp, 0xffb, 0x4000);
2768 tg3_phy_toggle_automdix(tp, true);
2769 tg3_phy_set_wirespeed(tp);
2773 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2774 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2775 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2776 TG3_GPIO_MSG_NEED_VAUX)
2777 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2778 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2779 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2780 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2781 (TG3_GPIO_MSG_DRVR_PRES << 12))
2783 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2784 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2785 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2786 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2787 (TG3_GPIO_MSG_NEED_VAUX << 12))
2789 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2793 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2794 tg3_asic_rev(tp) == ASIC_REV_5719)
2795 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2797 status = tr32(TG3_CPMU_DRV_STATUS);
2799 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2800 status &= ~(TG3_GPIO_MSG_MASK << shift);
2801 status |= (newstat << shift);
2803 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2804 tg3_asic_rev(tp) == ASIC_REV_5719)
2805 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2807 tw32(TG3_CPMU_DRV_STATUS, status);
2809 return status >> TG3_APE_GPIO_MSG_SHIFT;
2812 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2814 if (!tg3_flag(tp, IS_NIC))
2817 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2818 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2819 tg3_asic_rev(tp) == ASIC_REV_5720) {
2820 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2823 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2825 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2826 TG3_GRC_LCLCTL_PWRSW_DELAY);
2828 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2830 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2831 TG3_GRC_LCLCTL_PWRSW_DELAY);
2837 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2841 if (!tg3_flag(tp, IS_NIC) ||
2842 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2843 tg3_asic_rev(tp) == ASIC_REV_5701)
2846 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2848 tw32_wait_f(GRC_LOCAL_CTRL,
2849 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2850 TG3_GRC_LCLCTL_PWRSW_DELAY);
2852 tw32_wait_f(GRC_LOCAL_CTRL,
2854 TG3_GRC_LCLCTL_PWRSW_DELAY);
2856 tw32_wait_f(GRC_LOCAL_CTRL,
2857 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2858 TG3_GRC_LCLCTL_PWRSW_DELAY);
2861 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2863 if (!tg3_flag(tp, IS_NIC))
2866 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2867 tg3_asic_rev(tp) == ASIC_REV_5701) {
2868 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2869 (GRC_LCLCTRL_GPIO_OE0 |
2870 GRC_LCLCTRL_GPIO_OE1 |
2871 GRC_LCLCTRL_GPIO_OE2 |
2872 GRC_LCLCTRL_GPIO_OUTPUT0 |
2873 GRC_LCLCTRL_GPIO_OUTPUT1),
2874 TG3_GRC_LCLCTL_PWRSW_DELAY);
2875 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2876 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2877 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2878 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2879 GRC_LCLCTRL_GPIO_OE1 |
2880 GRC_LCLCTRL_GPIO_OE2 |
2881 GRC_LCLCTRL_GPIO_OUTPUT0 |
2882 GRC_LCLCTRL_GPIO_OUTPUT1 |
2884 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2885 TG3_GRC_LCLCTL_PWRSW_DELAY);
2887 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2888 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2889 TG3_GRC_LCLCTL_PWRSW_DELAY);
2891 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2892 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2893 TG3_GRC_LCLCTL_PWRSW_DELAY);
2896 u32 grc_local_ctrl = 0;
2898 /* Workaround to prevent overdrawing Amps. */
2899 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2900 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2901 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2903 TG3_GRC_LCLCTL_PWRSW_DELAY);
2906 /* On 5753 and variants, GPIO2 cannot be used. */
2907 no_gpio2 = tp->nic_sram_data_cfg &
2908 NIC_SRAM_DATA_CFG_NO_GPIO2;
2910 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2911 GRC_LCLCTRL_GPIO_OE1 |
2912 GRC_LCLCTRL_GPIO_OE2 |
2913 GRC_LCLCTRL_GPIO_OUTPUT1 |
2914 GRC_LCLCTRL_GPIO_OUTPUT2;
2916 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2917 GRC_LCLCTRL_GPIO_OUTPUT2);
2919 tw32_wait_f(GRC_LOCAL_CTRL,
2920 tp->grc_local_ctrl | grc_local_ctrl,
2921 TG3_GRC_LCLCTL_PWRSW_DELAY);
2923 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2925 tw32_wait_f(GRC_LOCAL_CTRL,
2926 tp->grc_local_ctrl | grc_local_ctrl,
2927 TG3_GRC_LCLCTL_PWRSW_DELAY);
2930 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2931 tw32_wait_f(GRC_LOCAL_CTRL,
2932 tp->grc_local_ctrl | grc_local_ctrl,
2933 TG3_GRC_LCLCTL_PWRSW_DELAY);
2938 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2942 /* Serialize power state transitions */
2943 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2946 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2947 msg = TG3_GPIO_MSG_NEED_VAUX;
2949 msg = tg3_set_function_status(tp, msg);
2951 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2954 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2955 tg3_pwrsrc_switch_to_vaux(tp);
2957 tg3_pwrsrc_die_with_vmain(tp);
2960 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2963 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2965 bool need_vaux = false;
2967 /* The GPIOs do something completely different on 57765. */
2968 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2971 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2972 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2973 tg3_asic_rev(tp) == ASIC_REV_5720) {
2974 tg3_frob_aux_power_5717(tp, include_wol ?
2975 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2979 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2980 struct net_device *dev_peer;
2982 dev_peer = pci_get_drvdata(tp->pdev_peer);
2984 /* remove_one() may have been run on the peer. */
2986 struct tg3 *tp_peer = netdev_priv(dev_peer);
2988 if (tg3_flag(tp_peer, INIT_COMPLETE))
2991 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2992 tg3_flag(tp_peer, ENABLE_ASF))
2997 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2998 tg3_flag(tp, ENABLE_ASF))
3002 tg3_pwrsrc_switch_to_vaux(tp);
3004 tg3_pwrsrc_die_with_vmain(tp);
3007 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3009 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3011 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3012 if (speed != SPEED_10)
3014 } else if (speed == SPEED_10)
3020 static bool tg3_phy_power_bug(struct tg3 *tp)
3022 switch (tg3_asic_rev(tp)) {
3027 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3036 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3045 static bool tg3_phy_led_bug(struct tg3 *tp)
3047 switch (tg3_asic_rev(tp)) {
3050 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3059 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3063 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3066 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3067 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3068 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3069 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3072 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3073 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3074 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3079 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3081 val = tr32(GRC_MISC_CFG);
3082 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3085 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3087 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3090 tg3_writephy(tp, MII_ADVERTISE, 0);
3091 tg3_writephy(tp, MII_BMCR,
3092 BMCR_ANENABLE | BMCR_ANRESTART);
3094 tg3_writephy(tp, MII_TG3_FET_TEST,
3095 phytest | MII_TG3_FET_SHADOW_EN);
3096 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3097 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3099 MII_TG3_FET_SHDW_AUXMODE4,
3102 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3105 } else if (do_low_power) {
3106 if (!tg3_phy_led_bug(tp))
3107 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3108 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3110 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3111 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3112 MII_TG3_AUXCTL_PCTL_VREG_11V;
3113 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3116 /* The PHY should not be powered down on some chips because
3119 if (tg3_phy_power_bug(tp))
3122 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3123 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3124 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3125 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3126 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3127 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3130 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3133 /* tp->lock is held. */
3134 static int tg3_nvram_lock(struct tg3 *tp)
3136 if (tg3_flag(tp, NVRAM)) {
3139 if (tp->nvram_lock_cnt == 0) {
3140 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3141 for (i = 0; i < 8000; i++) {
3142 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3147 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3151 tp->nvram_lock_cnt++;
3156 /* tp->lock is held. */
3157 static void tg3_nvram_unlock(struct tg3 *tp)
3159 if (tg3_flag(tp, NVRAM)) {
3160 if (tp->nvram_lock_cnt > 0)
3161 tp->nvram_lock_cnt--;
3162 if (tp->nvram_lock_cnt == 0)
3163 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3167 /* tp->lock is held. */
3168 static void tg3_enable_nvram_access(struct tg3 *tp)
3170 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3171 u32 nvaccess = tr32(NVRAM_ACCESS);
3173 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3177 /* tp->lock is held. */
3178 static void tg3_disable_nvram_access(struct tg3 *tp)
3180 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3181 u32 nvaccess = tr32(NVRAM_ACCESS);
3183 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3187 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3188 u32 offset, u32 *val)
3193 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3196 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3197 EEPROM_ADDR_DEVID_MASK |
3199 tw32(GRC_EEPROM_ADDR,
3201 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3202 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3203 EEPROM_ADDR_ADDR_MASK) |
3204 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3206 for (i = 0; i < 1000; i++) {
3207 tmp = tr32(GRC_EEPROM_ADDR);
3209 if (tmp & EEPROM_ADDR_COMPLETE)
3213 if (!(tmp & EEPROM_ADDR_COMPLETE))
3216 tmp = tr32(GRC_EEPROM_DATA);
3219 * The data will always be opposite the native endian
3220 * format. Perform a blind byteswap to compensate.
3227 #define NVRAM_CMD_TIMEOUT 5000
3229 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3233 tw32(NVRAM_CMD, nvram_cmd);
3234 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3235 usleep_range(10, 40);
3236 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3242 if (i == NVRAM_CMD_TIMEOUT)
3248 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3250 if (tg3_flag(tp, NVRAM) &&
3251 tg3_flag(tp, NVRAM_BUFFERED) &&
3252 tg3_flag(tp, FLASH) &&
3253 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3254 (tp->nvram_jedecnum == JEDEC_ATMEL))
3256 addr = ((addr / tp->nvram_pagesize) <<
3257 ATMEL_AT45DB0X1B_PAGE_POS) +
3258 (addr % tp->nvram_pagesize);
3263 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3265 if (tg3_flag(tp, NVRAM) &&
3266 tg3_flag(tp, NVRAM_BUFFERED) &&
3267 tg3_flag(tp, FLASH) &&
3268 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3269 (tp->nvram_jedecnum == JEDEC_ATMEL))
3271 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3272 tp->nvram_pagesize) +
3273 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3278 /* NOTE: Data read in from NVRAM is byteswapped according to
3279 * the byteswapping settings for all other register accesses.
3280 * tg3 devices are BE devices, so on a BE machine, the data
3281 * returned will be exactly as it is seen in NVRAM. On a LE
3282 * machine, the 32-bit value will be byteswapped.
3284 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3288 if (!tg3_flag(tp, NVRAM))
3289 return tg3_nvram_read_using_eeprom(tp, offset, val);
3291 offset = tg3_nvram_phys_addr(tp, offset);
3293 if (offset > NVRAM_ADDR_MSK)
3296 ret = tg3_nvram_lock(tp);
3300 tg3_enable_nvram_access(tp);
3302 tw32(NVRAM_ADDR, offset);
3303 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3304 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3307 *val = tr32(NVRAM_RDDATA);
3309 tg3_disable_nvram_access(tp);
3311 tg3_nvram_unlock(tp);
3316 /* Ensures NVRAM data is in bytestream format. */
3317 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3320 int res = tg3_nvram_read(tp, offset, &v);
3322 *val = cpu_to_be32(v);
3326 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3327 u32 offset, u32 len, u8 *buf)
3332 for (i = 0; i < len; i += 4) {
3338 memcpy(&data, buf + i, 4);
3341 * The SEEPROM interface expects the data to always be opposite
3342 * the native endian format. We accomplish this by reversing
3343 * all the operations that would have been performed on the
3344 * data from a call to tg3_nvram_read_be32().
3346 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3348 val = tr32(GRC_EEPROM_ADDR);
3349 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3351 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3353 tw32(GRC_EEPROM_ADDR, val |
3354 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3355 (addr & EEPROM_ADDR_ADDR_MASK) |
3359 for (j = 0; j < 1000; j++) {
3360 val = tr32(GRC_EEPROM_ADDR);
3362 if (val & EEPROM_ADDR_COMPLETE)
3366 if (!(val & EEPROM_ADDR_COMPLETE)) {
3375 /* offset and length are dword aligned */
3376 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3380 u32 pagesize = tp->nvram_pagesize;
3381 u32 pagemask = pagesize - 1;
3385 tmp = kmalloc(pagesize, GFP_KERNEL);
3391 u32 phy_addr, page_off, size;
3393 phy_addr = offset & ~pagemask;
3395 for (j = 0; j < pagesize; j += 4) {
3396 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3397 (__be32 *) (tmp + j));
3404 page_off = offset & pagemask;
3411 memcpy(tmp + page_off, buf, size);
3413 offset = offset + (pagesize - page_off);
3415 tg3_enable_nvram_access(tp);
3418 * Before we can erase the flash page, we need
3419 * to issue a special "write enable" command.
3421 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3423 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3426 /* Erase the target page */
3427 tw32(NVRAM_ADDR, phy_addr);
3429 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3430 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3432 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3435 /* Issue another write enable to start the write. */
3436 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3441 for (j = 0; j < pagesize; j += 4) {
3444 data = *((__be32 *) (tmp + j));
3446 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3448 tw32(NVRAM_ADDR, phy_addr + j);
3450 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3454 nvram_cmd |= NVRAM_CMD_FIRST;
3455 else if (j == (pagesize - 4))
3456 nvram_cmd |= NVRAM_CMD_LAST;
3458 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3466 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3467 tg3_nvram_exec_cmd(tp, nvram_cmd);
3474 /* offset and length are dword aligned */
3475 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3480 for (i = 0; i < len; i += 4, offset += 4) {
3481 u32 page_off, phy_addr, nvram_cmd;
3484 memcpy(&data, buf + i, 4);
3485 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3487 page_off = offset % tp->nvram_pagesize;
3489 phy_addr = tg3_nvram_phys_addr(tp, offset);
3491 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3493 if (page_off == 0 || i == 0)
3494 nvram_cmd |= NVRAM_CMD_FIRST;
3495 if (page_off == (tp->nvram_pagesize - 4))
3496 nvram_cmd |= NVRAM_CMD_LAST;
3499 nvram_cmd |= NVRAM_CMD_LAST;
3501 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3502 !tg3_flag(tp, FLASH) ||
3503 !tg3_flag(tp, 57765_PLUS))
3504 tw32(NVRAM_ADDR, phy_addr);
3506 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3507 !tg3_flag(tp, 5755_PLUS) &&
3508 (tp->nvram_jedecnum == JEDEC_ST) &&
3509 (nvram_cmd & NVRAM_CMD_FIRST)) {
3512 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3513 ret = tg3_nvram_exec_cmd(tp, cmd);
3517 if (!tg3_flag(tp, FLASH)) {
3518 /* We always do complete word writes to eeprom. */
3519 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3522 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3529 /* offset and length are dword aligned */
3530 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3534 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3535 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3536 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3540 if (!tg3_flag(tp, NVRAM)) {
3541 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3545 ret = tg3_nvram_lock(tp);
3549 tg3_enable_nvram_access(tp);
3550 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3551 tw32(NVRAM_WRITE1, 0x406);
3553 grc_mode = tr32(GRC_MODE);
3554 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3556 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3557 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3560 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3564 grc_mode = tr32(GRC_MODE);
3565 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3567 tg3_disable_nvram_access(tp);
3568 tg3_nvram_unlock(tp);
3571 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3572 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3579 #define RX_CPU_SCRATCH_BASE 0x30000
3580 #define RX_CPU_SCRATCH_SIZE 0x04000
3581 #define TX_CPU_SCRATCH_BASE 0x34000
3582 #define TX_CPU_SCRATCH_SIZE 0x04000
3584 /* tp->lock is held. */
3585 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3588 const int iters = 10000;
3590 for (i = 0; i < iters; i++) {
3591 tw32(cpu_base + CPU_STATE, 0xffffffff);
3592 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3593 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3595 if (pci_channel_offline(tp->pdev))
3599 return (i == iters) ? -EBUSY : 0;
3602 /* tp->lock is held. */
3603 static int tg3_rxcpu_pause(struct tg3 *tp)
3605 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3607 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3608 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3614 /* tp->lock is held. */
3615 static int tg3_txcpu_pause(struct tg3 *tp)
3617 return tg3_pause_cpu(tp, TX_CPU_BASE);
3620 /* tp->lock is held. */
3621 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3623 tw32(cpu_base + CPU_STATE, 0xffffffff);
3624 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3627 /* tp->lock is held. */
3628 static void tg3_rxcpu_resume(struct tg3 *tp)
3630 tg3_resume_cpu(tp, RX_CPU_BASE);
3633 /* tp->lock is held. */
3634 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3638 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3640 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3641 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3643 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3646 if (cpu_base == RX_CPU_BASE) {
3647 rc = tg3_rxcpu_pause(tp);
3650 * There is only an Rx CPU for the 5750 derivative in the
3653 if (tg3_flag(tp, IS_SSB_CORE))
3656 rc = tg3_txcpu_pause(tp);
3660 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3661 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3665 /* Clear firmware's nvram arbitration. */
3666 if (tg3_flag(tp, NVRAM))
3667 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3671 static int tg3_fw_data_len(struct tg3 *tp,
3672 const struct tg3_firmware_hdr *fw_hdr)
3676 /* Non fragmented firmware have one firmware header followed by a
3677 * contiguous chunk of data to be written. The length field in that
3678 * header is not the length of data to be written but the complete
3679 * length of the bss. The data length is determined based on
3680 * tp->fw->size minus headers.
3682 * Fragmented firmware have a main header followed by multiple
3683 * fragments. Each fragment is identical to non fragmented firmware
3684 * with a firmware header followed by a contiguous chunk of data. In
3685 * the main header, the length field is unused and set to 0xffffffff.
3686 * In each fragment header the length is the entire size of that
3687 * fragment i.e. fragment data + header length. Data length is
3688 * therefore length field in the header minus TG3_FW_HDR_LEN.
3690 if (tp->fw_len == 0xffffffff)
3691 fw_len = be32_to_cpu(fw_hdr->len);
3693 fw_len = tp->fw->size;
3695 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3698 /* tp->lock is held. */
3699 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3700 u32 cpu_scratch_base, int cpu_scratch_size,
3701 const struct tg3_firmware_hdr *fw_hdr)
3704 void (*write_op)(struct tg3 *, u32, u32);
3705 int total_len = tp->fw->size;
3707 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3709 "%s: Trying to load TX cpu firmware which is 5705\n",
3714 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3715 write_op = tg3_write_mem;
3717 write_op = tg3_write_indirect_reg32;
3719 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3720 /* It is possible that bootcode is still loading at this point.
3721 * Get the nvram lock first before halting the cpu.
3723 int lock_err = tg3_nvram_lock(tp);
3724 err = tg3_halt_cpu(tp, cpu_base);
3726 tg3_nvram_unlock(tp);
3730 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3731 write_op(tp, cpu_scratch_base + i, 0);
3732 tw32(cpu_base + CPU_STATE, 0xffffffff);
3733 tw32(cpu_base + CPU_MODE,
3734 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3736 /* Subtract additional main header for fragmented firmware and
3737 * advance to the first fragment
3739 total_len -= TG3_FW_HDR_LEN;
3744 u32 *fw_data = (u32 *)(fw_hdr + 1);
3745 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3746 write_op(tp, cpu_scratch_base +
3747 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3749 be32_to_cpu(fw_data[i]));
3751 total_len -= be32_to_cpu(fw_hdr->len);
3753 /* Advance to next fragment */
3754 fw_hdr = (struct tg3_firmware_hdr *)
3755 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3756 } while (total_len > 0);
3764 /* tp->lock is held. */
3765 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3768 const int iters = 5;
3770 tw32(cpu_base + CPU_STATE, 0xffffffff);
3771 tw32_f(cpu_base + CPU_PC, pc);
3773 for (i = 0; i < iters; i++) {
3774 if (tr32(cpu_base + CPU_PC) == pc)
3776 tw32(cpu_base + CPU_STATE, 0xffffffff);
3777 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3778 tw32_f(cpu_base + CPU_PC, pc);
3782 return (i == iters) ? -EBUSY : 0;
3785 /* tp->lock is held. */
3786 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3788 const struct tg3_firmware_hdr *fw_hdr;
3791 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3793 /* Firmware blob starts with version numbers, followed by
3794 start address and length. We are setting complete length.
3795 length = end_address_of_bss - start_address_of_text.
3796 Remainder is the blob to be loaded contiguously
3797 from start address. */
3799 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3800 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3805 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3806 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3811 /* Now startup only the RX cpu. */
3812 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3813 be32_to_cpu(fw_hdr->base_addr));
3815 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3816 "should be %08x\n", __func__,
3817 tr32(RX_CPU_BASE + CPU_PC),
3818 be32_to_cpu(fw_hdr->base_addr));
3822 tg3_rxcpu_resume(tp);
3827 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3829 const int iters = 1000;
3833 /* Wait for boot code to complete initialization and enter service
3834 * loop. It is then safe to download service patches
3836 for (i = 0; i < iters; i++) {
3837 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3844 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3848 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3850 netdev_warn(tp->dev,
3851 "Other patches exist. Not downloading EEE patch\n");
3858 /* tp->lock is held. */
3859 static void tg3_load_57766_firmware(struct tg3 *tp)
3861 struct tg3_firmware_hdr *fw_hdr;
3863 if (!tg3_flag(tp, NO_NVRAM))
3866 if (tg3_validate_rxcpu_state(tp))
3872 /* This firmware blob has a different format than older firmware
3873 * releases as given below. The main difference is we have fragmented
3874 * data to be written to non-contiguous locations.
3876 * In the beginning we have a firmware header identical to other
3877 * firmware which consists of version, base addr and length. The length
3878 * here is unused and set to 0xffffffff.
3880 * This is followed by a series of firmware fragments which are
3881 * individually identical to previous firmware. i.e. they have the
3882 * firmware header and followed by data for that fragment. The version
3883 * field of the individual fragment header is unused.
3886 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3887 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3890 if (tg3_rxcpu_pause(tp))
3893 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3894 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3896 tg3_rxcpu_resume(tp);
3899 /* tp->lock is held. */
3900 static int tg3_load_tso_firmware(struct tg3 *tp)
3902 const struct tg3_firmware_hdr *fw_hdr;
3903 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3906 if (!tg3_flag(tp, FW_TSO))
3909 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3911 /* Firmware blob starts with version numbers, followed by
3912 start address and length. We are setting complete length.
3913 length = end_address_of_bss - start_address_of_text.
3914 Remainder is the blob to be loaded contiguously
3915 from start address. */
3917 cpu_scratch_size = tp->fw_len;
3919 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3920 cpu_base = RX_CPU_BASE;
3921 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3923 cpu_base = TX_CPU_BASE;
3924 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3925 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3928 err = tg3_load_firmware_cpu(tp, cpu_base,
3929 cpu_scratch_base, cpu_scratch_size,
3934 /* Now startup the cpu. */
3935 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3936 be32_to_cpu(fw_hdr->base_addr));
3939 "%s fails to set CPU PC, is %08x should be %08x\n",
3940 __func__, tr32(cpu_base + CPU_PC),
3941 be32_to_cpu(fw_hdr->base_addr));
3945 tg3_resume_cpu(tp, cpu_base);
3949 /* tp->lock is held. */
3950 static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3952 u32 addr_high, addr_low;
3954 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3955 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3956 (mac_addr[4] << 8) | mac_addr[5]);
3959 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3960 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3963 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3964 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3968 /* tp->lock is held. */
3969 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3974 for (i = 0; i < 4; i++) {
3975 if (i == 1 && skip_mac_1)
3977 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3980 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3981 tg3_asic_rev(tp) == ASIC_REV_5704) {
3982 for (i = 4; i < 16; i++)
3983 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3986 addr_high = (tp->dev->dev_addr[0] +
3987 tp->dev->dev_addr[1] +
3988 tp->dev->dev_addr[2] +
3989 tp->dev->dev_addr[3] +
3990 tp->dev->dev_addr[4] +
3991 tp->dev->dev_addr[5]) &
3992 TX_BACKOFF_SEED_MASK;
3993 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3996 static void tg3_enable_register_access(struct tg3 *tp)
3999 * Make sure register accesses (indirect or otherwise) will function
4002 pci_write_config_dword(tp->pdev,
4003 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4006 static int tg3_power_up(struct tg3 *tp)
4010 tg3_enable_register_access(tp);
4012 err = pci_set_power_state(tp->pdev, PCI_D0);
4014 /* Switch out of Vaux if it is a NIC */
4015 tg3_pwrsrc_switch_to_vmain(tp);
4017 netdev_err(tp->dev, "Transition to D0 failed\n");
4023 static int tg3_setup_phy(struct tg3 *, bool);
4025 static int tg3_power_down_prepare(struct tg3 *tp)
4028 bool device_should_wake, do_low_power;
4030 tg3_enable_register_access(tp);
4032 /* Restore the CLKREQ setting. */
4033 if (tg3_flag(tp, CLKREQ_BUG))
4034 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4035 PCI_EXP_LNKCTL_CLKREQ_EN);
4037 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4038 tw32(TG3PCI_MISC_HOST_CTRL,
4039 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4041 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4042 tg3_flag(tp, WOL_ENABLE);
4044 if (tg3_flag(tp, USE_PHYLIB)) {
4045 do_low_power = false;
4046 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4047 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4048 struct phy_device *phydev;
4049 u32 phyid, advertising;
4051 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
4053 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4055 tp->link_config.speed = phydev->speed;
4056 tp->link_config.duplex = phydev->duplex;
4057 tp->link_config.autoneg = phydev->autoneg;
4058 tp->link_config.advertising = phydev->advertising;
4060 advertising = ADVERTISED_TP |
4062 ADVERTISED_Autoneg |
4063 ADVERTISED_10baseT_Half;
4065 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4066 if (tg3_flag(tp, WOL_SPEED_100MB))
4068 ADVERTISED_100baseT_Half |
4069 ADVERTISED_100baseT_Full |
4070 ADVERTISED_10baseT_Full;
4072 advertising |= ADVERTISED_10baseT_Full;
4075 phydev->advertising = advertising;
4077 phy_start_aneg(phydev);
4079 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
4080 if (phyid != PHY_ID_BCMAC131) {
4081 phyid &= PHY_BCM_OUI_MASK;
4082 if (phyid == PHY_BCM_OUI_1 ||
4083 phyid == PHY_BCM_OUI_2 ||
4084 phyid == PHY_BCM_OUI_3)
4085 do_low_power = true;
4089 do_low_power = true;
4091 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4092 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4094 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4095 tg3_setup_phy(tp, false);
4098 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4101 val = tr32(GRC_VCPU_EXT_CTRL);
4102 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4103 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4107 for (i = 0; i < 200; i++) {
4108 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4109 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4114 if (tg3_flag(tp, WOL_CAP))
4115 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4116 WOL_DRV_STATE_SHUTDOWN |
4120 if (device_should_wake) {
4123 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4125 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4126 tg3_phy_auxctl_write(tp,
4127 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4128 MII_TG3_AUXCTL_PCTL_WOL_EN |
4129 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4130 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4134 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4135 mac_mode = MAC_MODE_PORT_MODE_GMII;
4136 else if (tp->phy_flags &
4137 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4138 if (tp->link_config.active_speed == SPEED_1000)
4139 mac_mode = MAC_MODE_PORT_MODE_GMII;
4141 mac_mode = MAC_MODE_PORT_MODE_MII;
4143 mac_mode = MAC_MODE_PORT_MODE_MII;
4145 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4146 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4147 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4148 SPEED_100 : SPEED_10;
4149 if (tg3_5700_link_polarity(tp, speed))
4150 mac_mode |= MAC_MODE_LINK_POLARITY;
4152 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4155 mac_mode = MAC_MODE_PORT_MODE_TBI;
4158 if (!tg3_flag(tp, 5750_PLUS))
4159 tw32(MAC_LED_CTRL, tp->led_ctrl);
4161 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4162 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4163 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4164 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4166 if (tg3_flag(tp, ENABLE_APE))
4167 mac_mode |= MAC_MODE_APE_TX_EN |
4168 MAC_MODE_APE_RX_EN |
4169 MAC_MODE_TDE_ENABLE;
4171 tw32_f(MAC_MODE, mac_mode);
4174 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4178 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4179 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4180 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4183 base_val = tp->pci_clock_ctrl;
4184 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4185 CLOCK_CTRL_TXCLK_DISABLE);
4187 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4188 CLOCK_CTRL_PWRDOWN_PLL133, 40);
4189 } else if (tg3_flag(tp, 5780_CLASS) ||
4190 tg3_flag(tp, CPMU_PRESENT) ||
4191 tg3_asic_rev(tp) == ASIC_REV_5906) {
4193 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4194 u32 newbits1, newbits2;
4196 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4197 tg3_asic_rev(tp) == ASIC_REV_5701) {
4198 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4199 CLOCK_CTRL_TXCLK_DISABLE |
4201 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4202 } else if (tg3_flag(tp, 5705_PLUS)) {
4203 newbits1 = CLOCK_CTRL_625_CORE;
4204 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4206 newbits1 = CLOCK_CTRL_ALTCLK;
4207 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4210 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4213 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4216 if (!tg3_flag(tp, 5705_PLUS)) {
4219 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4220 tg3_asic_rev(tp) == ASIC_REV_5701) {
4221 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4222 CLOCK_CTRL_TXCLK_DISABLE |
4223 CLOCK_CTRL_44MHZ_CORE);
4225 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4228 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4229 tp->pci_clock_ctrl | newbits3, 40);
4233 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4234 tg3_power_down_phy(tp, do_low_power);
4236 tg3_frob_aux_power(tp, true);
4238 /* Workaround for unstable PLL clock */
4239 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4240 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4241 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4242 u32 val = tr32(0x7d00);
4244 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4246 if (!tg3_flag(tp, ENABLE_ASF)) {
4249 err = tg3_nvram_lock(tp);
4250 tg3_halt_cpu(tp, RX_CPU_BASE);
4252 tg3_nvram_unlock(tp);
4256 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4258 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4263 static void tg3_power_down(struct tg3 *tp)
4265 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4266 pci_set_power_state(tp->pdev, PCI_D3hot);
4269 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4271 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4272 case MII_TG3_AUX_STAT_10HALF:
4274 *duplex = DUPLEX_HALF;
4277 case MII_TG3_AUX_STAT_10FULL:
4279 *duplex = DUPLEX_FULL;
4282 case MII_TG3_AUX_STAT_100HALF:
4284 *duplex = DUPLEX_HALF;
4287 case MII_TG3_AUX_STAT_100FULL:
4289 *duplex = DUPLEX_FULL;
4292 case MII_TG3_AUX_STAT_1000HALF:
4293 *speed = SPEED_1000;
4294 *duplex = DUPLEX_HALF;
4297 case MII_TG3_AUX_STAT_1000FULL:
4298 *speed = SPEED_1000;
4299 *duplex = DUPLEX_FULL;
4303 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4304 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4306 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4310 *speed = SPEED_UNKNOWN;
4311 *duplex = DUPLEX_UNKNOWN;
4316 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4321 new_adv = ADVERTISE_CSMA;
4322 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
4323 new_adv |= mii_advertise_flowctrl(flowctrl);
4325 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4329 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4330 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
4332 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4333 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4334 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4336 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4341 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4344 tw32(TG3_CPMU_EEE_MODE,
4345 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
4347 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4352 /* Advertise 100-BaseTX EEE ability */
4353 if (advertise & ADVERTISED_100baseT_Full)
4354 val |= MDIO_AN_EEE_ADV_100TX;
4355 /* Advertise 1000-BaseT EEE ability */
4356 if (advertise & ADVERTISED_1000baseT_Full)
4357 val |= MDIO_AN_EEE_ADV_1000T;
4359 if (!tp->eee.eee_enabled) {
4361 tp->eee.advertised = 0;
4363 tp->eee.advertised = advertise &
4364 (ADVERTISED_100baseT_Full |
4365 ADVERTISED_1000baseT_Full);
4368 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4372 switch (tg3_asic_rev(tp)) {
4374 case ASIC_REV_57765:
4375 case ASIC_REV_57766:
4377 /* If we advertised any eee advertisements above... */
4379 val = MII_TG3_DSP_TAP26_ALNOKO |
4380 MII_TG3_DSP_TAP26_RMRXSTO |
4381 MII_TG3_DSP_TAP26_OPCSINPT;
4382 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4386 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4387 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4388 MII_TG3_DSP_CH34TP2_HIBW01);
4391 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4400 static void tg3_phy_copper_begin(struct tg3 *tp)
4402 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4403 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4406 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4407 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4408 adv = ADVERTISED_10baseT_Half |
4409 ADVERTISED_10baseT_Full;
4410 if (tg3_flag(tp, WOL_SPEED_100MB))
4411 adv |= ADVERTISED_100baseT_Half |
4412 ADVERTISED_100baseT_Full;
4413 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4414 if (!(tp->phy_flags &
4415 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4416 adv |= ADVERTISED_1000baseT_Half;
4417 adv |= ADVERTISED_1000baseT_Full;
4420 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4422 adv = tp->link_config.advertising;
4423 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4424 adv &= ~(ADVERTISED_1000baseT_Half |
4425 ADVERTISED_1000baseT_Full);
4427 fc = tp->link_config.flowctrl;
4430 tg3_phy_autoneg_cfg(tp, adv, fc);
4432 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4433 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4434 /* Normally during power down we want to autonegotiate
4435 * the lowest possible speed for WOL. However, to avoid
4436 * link flap, we leave it untouched.
4441 tg3_writephy(tp, MII_BMCR,
4442 BMCR_ANENABLE | BMCR_ANRESTART);
4445 u32 bmcr, orig_bmcr;
4447 tp->link_config.active_speed = tp->link_config.speed;
4448 tp->link_config.active_duplex = tp->link_config.duplex;
4450 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4451 /* With autoneg disabled, 5715 only links up when the
4452 * advertisement register has the configured speed
4455 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4459 switch (tp->link_config.speed) {
4465 bmcr |= BMCR_SPEED100;
4469 bmcr |= BMCR_SPEED1000;
4473 if (tp->link_config.duplex == DUPLEX_FULL)
4474 bmcr |= BMCR_FULLDPLX;
4476 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4477 (bmcr != orig_bmcr)) {
4478 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4479 for (i = 0; i < 1500; i++) {
4483 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4484 tg3_readphy(tp, MII_BMSR, &tmp))
4486 if (!(tmp & BMSR_LSTATUS)) {
4491 tg3_writephy(tp, MII_BMCR, bmcr);
4497 static int tg3_phy_pull_config(struct tg3 *tp)
4502 err = tg3_readphy(tp, MII_BMCR, &val);
4506 if (!(val & BMCR_ANENABLE)) {
4507 tp->link_config.autoneg = AUTONEG_DISABLE;
4508 tp->link_config.advertising = 0;
4509 tg3_flag_clear(tp, PAUSE_AUTONEG);
4513 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4515 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4518 tp->link_config.speed = SPEED_10;
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4524 tp->link_config.speed = SPEED_100;
4526 case BMCR_SPEED1000:
4527 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4528 tp->link_config.speed = SPEED_1000;
4536 if (val & BMCR_FULLDPLX)
4537 tp->link_config.duplex = DUPLEX_FULL;
4539 tp->link_config.duplex = DUPLEX_HALF;
4541 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4547 tp->link_config.autoneg = AUTONEG_ENABLE;
4548 tp->link_config.advertising = ADVERTISED_Autoneg;
4549 tg3_flag_set(tp, PAUSE_AUTONEG);
4551 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4554 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4558 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4559 tp->link_config.advertising |= adv | ADVERTISED_TP;
4561 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4563 tp->link_config.advertising |= ADVERTISED_FIBRE;
4566 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4569 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4570 err = tg3_readphy(tp, MII_CTRL1000, &val);
4574 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4576 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4580 adv = tg3_decode_flowctrl_1000X(val);
4581 tp->link_config.flowctrl = adv;
4583 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4584 adv = mii_adv_to_ethtool_adv_x(val);
4587 tp->link_config.advertising |= adv;
4594 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4598 /* Turn off tap power management. */
4599 /* Set Extended packet length bit */
4600 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4602 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4603 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4604 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4605 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4606 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4613 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4615 struct ethtool_eee eee;
4617 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4620 tg3_eee_pull_config(tp, &eee);
4622 if (tp->eee.eee_enabled) {
4623 if (tp->eee.advertised != eee.advertised ||
4624 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4625 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4628 /* EEE is disabled but we're advertising */
4636 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4638 u32 advmsk, tgtadv, advertising;
4640 advertising = tp->link_config.advertising;
4641 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4643 advmsk = ADVERTISE_ALL;
4644 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4645 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4646 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4649 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4652 if ((*lcladv & advmsk) != tgtadv)
4655 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4658 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4660 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4664 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4665 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4666 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4667 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4668 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4670 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4673 if (tg3_ctrl != tgtadv)
4680 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4684 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4687 if (tg3_readphy(tp, MII_STAT1000, &val))
4690 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4693 if (tg3_readphy(tp, MII_LPA, rmtadv))
4696 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4697 tp->link_config.rmt_adv = lpeth;
4702 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4704 if (curr_link_up != tp->link_up) {
4706 netif_carrier_on(tp->dev);
4708 netif_carrier_off(tp->dev);
4709 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4710 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4713 tg3_link_report(tp);
4720 static void tg3_clear_mac_status(struct tg3 *tp)
4725 MAC_STATUS_SYNC_CHANGED |
4726 MAC_STATUS_CFG_CHANGED |
4727 MAC_STATUS_MI_COMPLETION |
4728 MAC_STATUS_LNKSTATE_CHANGED);
4732 static void tg3_setup_eee(struct tg3 *tp)
4736 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4737 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4738 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4739 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4741 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4743 tw32_f(TG3_CPMU_EEE_CTRL,
4744 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4746 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4747 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4748 TG3_CPMU_EEEMD_LPI_IN_RX |
4749 TG3_CPMU_EEEMD_EEE_ENABLE;
4751 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4752 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4754 if (tg3_flag(tp, ENABLE_APE))
4755 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4757 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4759 tw32_f(TG3_CPMU_EEE_DBTMR1,
4760 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4761 (tp->eee.tx_lpi_timer & 0xffff));
4763 tw32_f(TG3_CPMU_EEE_DBTMR2,
4764 TG3_CPMU_DBTMR2_APE_TX_2047US |
4765 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4768 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4770 bool current_link_up;
4772 u32 lcl_adv, rmt_adv;
4777 tg3_clear_mac_status(tp);
4779 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4781 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4785 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4787 /* Some third-party PHYs need to be reset on link going
4790 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4791 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4792 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4794 tg3_readphy(tp, MII_BMSR, &bmsr);
4795 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4796 !(bmsr & BMSR_LSTATUS))
4802 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4803 tg3_readphy(tp, MII_BMSR, &bmsr);
4804 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4805 !tg3_flag(tp, INIT_COMPLETE))
4808 if (!(bmsr & BMSR_LSTATUS)) {
4809 err = tg3_init_5401phy_dsp(tp);
4813 tg3_readphy(tp, MII_BMSR, &bmsr);
4814 for (i = 0; i < 1000; i++) {
4816 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4817 (bmsr & BMSR_LSTATUS)) {
4823 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4824 TG3_PHY_REV_BCM5401_B0 &&
4825 !(bmsr & BMSR_LSTATUS) &&
4826 tp->link_config.active_speed == SPEED_1000) {
4827 err = tg3_phy_reset(tp);
4829 err = tg3_init_5401phy_dsp(tp);
4834 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4835 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4836 /* 5701 {A0,B0} CRC bug workaround */
4837 tg3_writephy(tp, 0x15, 0x0a75);
4838 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4839 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4840 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4843 /* Clear pending interrupts... */
4844 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4845 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4847 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4848 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4849 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4850 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4852 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4853 tg3_asic_rev(tp) == ASIC_REV_5701) {
4854 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4855 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4856 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4858 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4861 current_link_up = false;
4862 current_speed = SPEED_UNKNOWN;
4863 current_duplex = DUPLEX_UNKNOWN;
4864 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4865 tp->link_config.rmt_adv = 0;
4867 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4868 err = tg3_phy_auxctl_read(tp,
4869 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4871 if (!err && !(val & (1 << 10))) {
4872 tg3_phy_auxctl_write(tp,
4873 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4880 for (i = 0; i < 100; i++) {
4881 tg3_readphy(tp, MII_BMSR, &bmsr);
4882 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4883 (bmsr & BMSR_LSTATUS))
4888 if (bmsr & BMSR_LSTATUS) {
4891 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4892 for (i = 0; i < 2000; i++) {
4894 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4899 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4904 for (i = 0; i < 200; i++) {
4905 tg3_readphy(tp, MII_BMCR, &bmcr);
4906 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4908 if (bmcr && bmcr != 0x7fff)
4916 tp->link_config.active_speed = current_speed;
4917 tp->link_config.active_duplex = current_duplex;
4919 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4920 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4922 if ((bmcr & BMCR_ANENABLE) &&
4924 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4925 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4926 current_link_up = true;
4928 /* EEE settings changes take effect only after a phy
4929 * reset. If we have skipped a reset due to Link Flap
4930 * Avoidance being enabled, do it now.
4932 if (!eee_config_ok &&
4933 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4939 if (!(bmcr & BMCR_ANENABLE) &&
4940 tp->link_config.speed == current_speed &&
4941 tp->link_config.duplex == current_duplex) {
4942 current_link_up = true;
4946 if (current_link_up &&
4947 tp->link_config.active_duplex == DUPLEX_FULL) {
4950 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4951 reg = MII_TG3_FET_GEN_STAT;
4952 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4954 reg = MII_TG3_EXT_STAT;
4955 bit = MII_TG3_EXT_STAT_MDIX;
4958 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4959 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4961 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4966 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4967 tg3_phy_copper_begin(tp);
4969 if (tg3_flag(tp, ROBOSWITCH)) {
4970 current_link_up = true;
4971 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4972 current_speed = SPEED_1000;
4973 current_duplex = DUPLEX_FULL;
4974 tp->link_config.active_speed = current_speed;
4975 tp->link_config.active_duplex = current_duplex;
4978 tg3_readphy(tp, MII_BMSR, &bmsr);
4979 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4980 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4981 current_link_up = true;
4984 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4985 if (current_link_up) {
4986 if (tp->link_config.active_speed == SPEED_100 ||
4987 tp->link_config.active_speed == SPEED_10)
4988 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4990 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4991 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4992 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4994 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4996 /* In order for the 5750 core in BCM4785 chip to work properly
4997 * in RGMII mode, the Led Control Register must be set up.
4999 if (tg3_flag(tp, RGMII_MODE)) {
5000 u32 led_ctrl = tr32(MAC_LED_CTRL);
5001 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5003 if (tp->link_config.active_speed == SPEED_10)
5004 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5005 else if (tp->link_config.active_speed == SPEED_100)
5006 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5007 LED_CTRL_100MBPS_ON);
5008 else if (tp->link_config.active_speed == SPEED_1000)
5009 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5010 LED_CTRL_1000MBPS_ON);
5012 tw32(MAC_LED_CTRL, led_ctrl);
5016 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5017 if (tp->link_config.active_duplex == DUPLEX_HALF)
5018 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5020 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5021 if (current_link_up &&
5022 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5023 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5025 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5028 /* ??? Without this setting Netgear GA302T PHY does not
5029 * ??? send/receive packets...
5031 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5032 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5033 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5034 tw32_f(MAC_MI_MODE, tp->mi_mode);
5038 tw32_f(MAC_MODE, tp->mac_mode);
5041 tg3_phy_eee_adjust(tp, current_link_up);
5043 if (tg3_flag(tp, USE_LINKCHG_REG)) {
5044 /* Polled via timer. */
5045 tw32_f(MAC_EVENT, 0);
5047 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5051 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5053 tp->link_config.active_speed == SPEED_1000 &&
5054 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5057 (MAC_STATUS_SYNC_CHANGED |
5058 MAC_STATUS_CFG_CHANGED));
5061 NIC_SRAM_FIRMWARE_MBOX,
5062 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5065 /* Prevent send BD corruption. */
5066 if (tg3_flag(tp, CLKREQ_BUG)) {
5067 if (tp->link_config.active_speed == SPEED_100 ||
5068 tp->link_config.active_speed == SPEED_10)
5069 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5070 PCI_EXP_LNKCTL_CLKREQ_EN);
5072 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5073 PCI_EXP_LNKCTL_CLKREQ_EN);
5076 tg3_test_and_report_link_chg(tp, current_link_up);
5081 struct tg3_fiber_aneginfo {
5083 #define ANEG_STATE_UNKNOWN 0
5084 #define ANEG_STATE_AN_ENABLE 1
5085 #define ANEG_STATE_RESTART_INIT 2
5086 #define ANEG_STATE_RESTART 3
5087 #define ANEG_STATE_DISABLE_LINK_OK 4
5088 #define ANEG_STATE_ABILITY_DETECT_INIT 5
5089 #define ANEG_STATE_ABILITY_DETECT 6
5090 #define ANEG_STATE_ACK_DETECT_INIT 7
5091 #define ANEG_STATE_ACK_DETECT 8
5092 #define ANEG_STATE_COMPLETE_ACK_INIT 9
5093 #define ANEG_STATE_COMPLETE_ACK 10
5094 #define ANEG_STATE_IDLE_DETECT_INIT 11
5095 #define ANEG_STATE_IDLE_DETECT 12
5096 #define ANEG_STATE_LINK_OK 13
5097 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5098 #define ANEG_STATE_NEXT_PAGE_WAIT 15
5101 #define MR_AN_ENABLE 0x00000001
5102 #define MR_RESTART_AN 0x00000002
5103 #define MR_AN_COMPLETE 0x00000004
5104 #define MR_PAGE_RX 0x00000008
5105 #define MR_NP_LOADED 0x00000010
5106 #define MR_TOGGLE_TX 0x00000020
5107 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5108 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5109 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5110 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5111 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5112 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5113 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5114 #define MR_TOGGLE_RX 0x00002000
5115 #define MR_NP_RX 0x00004000
5117 #define MR_LINK_OK 0x80000000
5119 unsigned long link_time, cur_time;
5121 u32 ability_match_cfg;
5122 int ability_match_count;
5124 char ability_match, idle_match, ack_match;
5126 u32 txconfig, rxconfig;
5127 #define ANEG_CFG_NP 0x00000080
5128 #define ANEG_CFG_ACK 0x00000040
5129 #define ANEG_CFG_RF2 0x00000020
5130 #define ANEG_CFG_RF1 0x00000010
5131 #define ANEG_CFG_PS2 0x00000001
5132 #define ANEG_CFG_PS1 0x00008000
5133 #define ANEG_CFG_HD 0x00004000
5134 #define ANEG_CFG_FD 0x00002000
5135 #define ANEG_CFG_INVAL 0x00001f06
5140 #define ANEG_TIMER_ENAB 2
5141 #define ANEG_FAILED -1
5143 #define ANEG_STATE_SETTLE_TIME 10000
5145 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5146 struct tg3_fiber_aneginfo *ap)
5149 unsigned long delta;
5153 if (ap->state == ANEG_STATE_UNKNOWN) {
5157 ap->ability_match_cfg = 0;
5158 ap->ability_match_count = 0;
5159 ap->ability_match = 0;
5165 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5166 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5168 if (rx_cfg_reg != ap->ability_match_cfg) {
5169 ap->ability_match_cfg = rx_cfg_reg;
5170 ap->ability_match = 0;
5171 ap->ability_match_count = 0;
5173 if (++ap->ability_match_count > 1) {
5174 ap->ability_match = 1;
5175 ap->ability_match_cfg = rx_cfg_reg;
5178 if (rx_cfg_reg & ANEG_CFG_ACK)
5186 ap->ability_match_cfg = 0;
5187 ap->ability_match_count = 0;
5188 ap->ability_match = 0;
5194 ap->rxconfig = rx_cfg_reg;
5197 switch (ap->state) {
5198 case ANEG_STATE_UNKNOWN:
5199 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5200 ap->state = ANEG_STATE_AN_ENABLE;
5203 case ANEG_STATE_AN_ENABLE:
5204 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5205 if (ap->flags & MR_AN_ENABLE) {
5208 ap->ability_match_cfg = 0;
5209 ap->ability_match_count = 0;
5210 ap->ability_match = 0;
5214 ap->state = ANEG_STATE_RESTART_INIT;
5216 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5220 case ANEG_STATE_RESTART_INIT:
5221 ap->link_time = ap->cur_time;
5222 ap->flags &= ~(MR_NP_LOADED);
5224 tw32(MAC_TX_AUTO_NEG, 0);
5225 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5226 tw32_f(MAC_MODE, tp->mac_mode);
5229 ret = ANEG_TIMER_ENAB;
5230 ap->state = ANEG_STATE_RESTART;
5233 case ANEG_STATE_RESTART:
5234 delta = ap->cur_time - ap->link_time;
5235 if (delta > ANEG_STATE_SETTLE_TIME)
5236 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
5238 ret = ANEG_TIMER_ENAB;
5241 case ANEG_STATE_DISABLE_LINK_OK:
5245 case ANEG_STATE_ABILITY_DETECT_INIT:
5246 ap->flags &= ~(MR_TOGGLE_TX);
5247 ap->txconfig = ANEG_CFG_FD;
5248 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5249 if (flowctrl & ADVERTISE_1000XPAUSE)
5250 ap->txconfig |= ANEG_CFG_PS1;
5251 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5252 ap->txconfig |= ANEG_CFG_PS2;
5253 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5254 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5255 tw32_f(MAC_MODE, tp->mac_mode);
5258 ap->state = ANEG_STATE_ABILITY_DETECT;
5261 case ANEG_STATE_ABILITY_DETECT:
5262 if (ap->ability_match != 0 && ap->rxconfig != 0)
5263 ap->state = ANEG_STATE_ACK_DETECT_INIT;
5266 case ANEG_STATE_ACK_DETECT_INIT:
5267 ap->txconfig |= ANEG_CFG_ACK;
5268 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5269 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5270 tw32_f(MAC_MODE, tp->mac_mode);
5273 ap->state = ANEG_STATE_ACK_DETECT;
5276 case ANEG_STATE_ACK_DETECT:
5277 if (ap->ack_match != 0) {
5278 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5279 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5280 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5282 ap->state = ANEG_STATE_AN_ENABLE;
5284 } else if (ap->ability_match != 0 &&
5285 ap->rxconfig == 0) {
5286 ap->state = ANEG_STATE_AN_ENABLE;
5290 case ANEG_STATE_COMPLETE_ACK_INIT:
5291 if (ap->rxconfig & ANEG_CFG_INVAL) {
5295 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5296 MR_LP_ADV_HALF_DUPLEX |
5297 MR_LP_ADV_SYM_PAUSE |
5298 MR_LP_ADV_ASYM_PAUSE |
5299 MR_LP_ADV_REMOTE_FAULT1 |
5300 MR_LP_ADV_REMOTE_FAULT2 |
5301 MR_LP_ADV_NEXT_PAGE |
5304 if (ap->rxconfig & ANEG_CFG_FD)
5305 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5306 if (ap->rxconfig & ANEG_CFG_HD)
5307 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5308 if (ap->rxconfig & ANEG_CFG_PS1)
5309 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5310 if (ap->rxconfig & ANEG_CFG_PS2)
5311 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5312 if (ap->rxconfig & ANEG_CFG_RF1)
5313 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5314 if (ap->rxconfig & ANEG_CFG_RF2)
5315 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5316 if (ap->rxconfig & ANEG_CFG_NP)
5317 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5319 ap->link_time = ap->cur_time;
5321 ap->flags ^= (MR_TOGGLE_TX);
5322 if (ap->rxconfig & 0x0008)
5323 ap->flags |= MR_TOGGLE_RX;
5324 if (ap->rxconfig & ANEG_CFG_NP)
5325 ap->flags |= MR_NP_RX;
5326 ap->flags |= MR_PAGE_RX;
5328 ap->state = ANEG_STATE_COMPLETE_ACK;
5329 ret = ANEG_TIMER_ENAB;
5332 case ANEG_STATE_COMPLETE_ACK:
5333 if (ap->ability_match != 0 &&
5334 ap->rxconfig == 0) {
5335 ap->state = ANEG_STATE_AN_ENABLE;
5338 delta = ap->cur_time - ap->link_time;
5339 if (delta > ANEG_STATE_SETTLE_TIME) {
5340 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5341 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5343 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5344 !(ap->flags & MR_NP_RX)) {
5345 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5353 case ANEG_STATE_IDLE_DETECT_INIT:
5354 ap->link_time = ap->cur_time;
5355 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5356 tw32_f(MAC_MODE, tp->mac_mode);
5359 ap->state = ANEG_STATE_IDLE_DETECT;
5360 ret = ANEG_TIMER_ENAB;
5363 case ANEG_STATE_IDLE_DETECT:
5364 if (ap->ability_match != 0 &&
5365 ap->rxconfig == 0) {
5366 ap->state = ANEG_STATE_AN_ENABLE;
5369 delta = ap->cur_time - ap->link_time;
5370 if (delta > ANEG_STATE_SETTLE_TIME) {
5371 /* XXX another gem from the Broadcom driver :( */
5372 ap->state = ANEG_STATE_LINK_OK;
5376 case ANEG_STATE_LINK_OK:
5377 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5381 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5382 /* ??? unimplemented */
5385 case ANEG_STATE_NEXT_PAGE_WAIT:
5386 /* ??? unimplemented */
5397 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5400 struct tg3_fiber_aneginfo aninfo;
5401 int status = ANEG_FAILED;
5405 tw32_f(MAC_TX_AUTO_NEG, 0);
5407 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5408 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5411 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5414 memset(&aninfo, 0, sizeof(aninfo));
5415 aninfo.flags |= MR_AN_ENABLE;
5416 aninfo.state = ANEG_STATE_UNKNOWN;
5417 aninfo.cur_time = 0;
5419 while (++tick < 195000) {
5420 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5421 if (status == ANEG_DONE || status == ANEG_FAILED)
5427 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5428 tw32_f(MAC_MODE, tp->mac_mode);
5431 *txflags = aninfo.txconfig;
5432 *rxflags = aninfo.flags;
5434 if (status == ANEG_DONE &&
5435 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5436 MR_LP_ADV_FULL_DUPLEX)))
5442 static void tg3_init_bcm8002(struct tg3 *tp)
5444 u32 mac_status = tr32(MAC_STATUS);
5447 /* Reset when initting first time or we have a link. */
5448 if (tg3_flag(tp, INIT_COMPLETE) &&
5449 !(mac_status & MAC_STATUS_PCS_SYNCED))
5452 /* Set PLL lock range. */
5453 tg3_writephy(tp, 0x16, 0x8007);
5456 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5458 /* Wait for reset to complete. */
5459 /* XXX schedule_timeout() ... */
5460 for (i = 0; i < 500; i++)
5463 /* Config mode; select PMA/Ch 1 regs. */
5464 tg3_writephy(tp, 0x10, 0x8411);
5466 /* Enable auto-lock and comdet, select txclk for tx. */
5467 tg3_writephy(tp, 0x11, 0x0a10);
5469 tg3_writephy(tp, 0x18, 0x00a0);
5470 tg3_writephy(tp, 0x16, 0x41ff);
5472 /* Assert and deassert POR. */
5473 tg3_writephy(tp, 0x13, 0x0400);
5475 tg3_writephy(tp, 0x13, 0x0000);
5477 tg3_writephy(tp, 0x11, 0x0a50);
5479 tg3_writephy(tp, 0x11, 0x0a10);
5481 /* Wait for signal to stabilize */
5482 /* XXX schedule_timeout() ... */
5483 for (i = 0; i < 15000; i++)
5486 /* Deselect the channel register so we can read the PHYID
5489 tg3_writephy(tp, 0x10, 0x8011);
5492 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5495 bool current_link_up;
5496 u32 sg_dig_ctrl, sg_dig_status;
5497 u32 serdes_cfg, expected_sg_dig_ctrl;
5498 int workaround, port_a;
5501 expected_sg_dig_ctrl = 0;
5504 current_link_up = false;
5506 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5507 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5509 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5512 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5513 /* preserve bits 20-23 for voltage regulator */
5514 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5517 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5519 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5520 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
5522 u32 val = serdes_cfg;
5528 tw32_f(MAC_SERDES_CFG, val);
5531 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5533 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5534 tg3_setup_flow_control(tp, 0, 0);
5535 current_link_up = true;
5540 /* Want auto-negotiation. */
5541 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
5543 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5544 if (flowctrl & ADVERTISE_1000XPAUSE)
5545 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5546 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5547 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
5549 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
5550 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5551 tp->serdes_counter &&
5552 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5553 MAC_STATUS_RCVD_CFG)) ==
5554 MAC_STATUS_PCS_SYNCED)) {
5555 tp->serdes_counter--;
5556 current_link_up = true;
5561 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5562 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5564 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5566 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5567 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5568 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5569 MAC_STATUS_SIGNAL_DET)) {
5570 sg_dig_status = tr32(SG_DIG_STATUS);
5571 mac_status = tr32(MAC_STATUS);
5573 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
5574 (mac_status & MAC_STATUS_PCS_SYNCED)) {
5575 u32 local_adv = 0, remote_adv = 0;
5577 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5578 local_adv |= ADVERTISE_1000XPAUSE;
5579 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5580 local_adv |= ADVERTISE_1000XPSE_ASYM;
5582 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
5583 remote_adv |= LPA_1000XPAUSE;
5584 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
5585 remote_adv |= LPA_1000XPAUSE_ASYM;
5587 tp->link_config.rmt_adv =
5588 mii_adv_to_ethtool_adv_x(remote_adv);
5590 tg3_setup_flow_control(tp, local_adv, remote_adv);
5591 current_link_up = true;
5592 tp->serdes_counter = 0;
5593 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5594 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
5595 if (tp->serdes_counter)
5596 tp->serdes_counter--;
5599 u32 val = serdes_cfg;
5606 tw32_f(MAC_SERDES_CFG, val);
5609 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5612 /* Link parallel detection - link is up */
5613 /* only if we have PCS_SYNC and not */
5614 /* receiving config code words */
5615 mac_status = tr32(MAC_STATUS);
5616 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5617 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5618 tg3_setup_flow_control(tp, 0, 0);
5619 current_link_up = true;
5621 TG3_PHYFLG_PARALLEL_DETECT;
5622 tp->serdes_counter =
5623 SERDES_PARALLEL_DET_TIMEOUT;
5625 goto restart_autoneg;
5629 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5630 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5634 return current_link_up;
5637 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5639 bool current_link_up = false;
5641 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5644 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5645 u32 txflags, rxflags;
5648 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5649 u32 local_adv = 0, remote_adv = 0;
5651 if (txflags & ANEG_CFG_PS1)
5652 local_adv |= ADVERTISE_1000XPAUSE;
5653 if (txflags & ANEG_CFG_PS2)
5654 local_adv |= ADVERTISE_1000XPSE_ASYM;
5656 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5657 remote_adv |= LPA_1000XPAUSE;
5658 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5659 remote_adv |= LPA_1000XPAUSE_ASYM;
5661 tp->link_config.rmt_adv =
5662 mii_adv_to_ethtool_adv_x(remote_adv);
5664 tg3_setup_flow_control(tp, local_adv, remote_adv);
5666 current_link_up = true;
5668 for (i = 0; i < 30; i++) {
5671 (MAC_STATUS_SYNC_CHANGED |
5672 MAC_STATUS_CFG_CHANGED));
5674 if ((tr32(MAC_STATUS) &
5675 (MAC_STATUS_SYNC_CHANGED |
5676 MAC_STATUS_CFG_CHANGED)) == 0)
5680 mac_status = tr32(MAC_STATUS);
5681 if (!current_link_up &&
5682 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5683 !(mac_status & MAC_STATUS_RCVD_CFG))
5684 current_link_up = true;
5686 tg3_setup_flow_control(tp, 0, 0);
5688 /* Forcing 1000FD link up. */
5689 current_link_up = true;
5691 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5694 tw32_f(MAC_MODE, tp->mac_mode);
5699 return current_link_up;
5702 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
5705 u16 orig_active_speed;
5706 u8 orig_active_duplex;
5708 bool current_link_up;
5711 orig_pause_cfg = tp->link_config.active_flowctrl;
5712 orig_active_speed = tp->link_config.active_speed;
5713 orig_active_duplex = tp->link_config.active_duplex;
5715 if (!tg3_flag(tp, HW_AUTONEG) &&
5717 tg3_flag(tp, INIT_COMPLETE)) {
5718 mac_status = tr32(MAC_STATUS);
5719 mac_status &= (MAC_STATUS_PCS_SYNCED |
5720 MAC_STATUS_SIGNAL_DET |
5721 MAC_STATUS_CFG_CHANGED |
5722 MAC_STATUS_RCVD_CFG);
5723 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5724 MAC_STATUS_SIGNAL_DET)) {
5725 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5726 MAC_STATUS_CFG_CHANGED));
5731 tw32_f(MAC_TX_AUTO_NEG, 0);
5733 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5734 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5735 tw32_f(MAC_MODE, tp->mac_mode);
5738 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5739 tg3_init_bcm8002(tp);
5741 /* Enable link change event even when serdes polling. */
5742 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5745 current_link_up = false;
5746 tp->link_config.rmt_adv = 0;
5747 mac_status = tr32(MAC_STATUS);
5749 if (tg3_flag(tp, HW_AUTONEG))
5750 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5752 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5754 tp->napi[0].hw_status->status =
5755 (SD_STATUS_UPDATED |
5756 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5758 for (i = 0; i < 100; i++) {
5759 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5760 MAC_STATUS_CFG_CHANGED));
5762 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5763 MAC_STATUS_CFG_CHANGED |
5764 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5768 mac_status = tr32(MAC_STATUS);
5769 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5770 current_link_up = false;
5771 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5772 tp->serdes_counter == 0) {
5773 tw32_f(MAC_MODE, (tp->mac_mode |
5774 MAC_MODE_SEND_CONFIGS));
5776 tw32_f(MAC_MODE, tp->mac_mode);
5780 if (current_link_up) {
5781 tp->link_config.active_speed = SPEED_1000;
5782 tp->link_config.active_duplex = DUPLEX_FULL;
5783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5784 LED_CTRL_LNKLED_OVERRIDE |
5785 LED_CTRL_1000MBPS_ON));
5787 tp->link_config.active_speed = SPEED_UNKNOWN;
5788 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5789 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5790 LED_CTRL_LNKLED_OVERRIDE |
5791 LED_CTRL_TRAFFIC_OVERRIDE));
5794 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5795 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5796 if (orig_pause_cfg != now_pause_cfg ||
5797 orig_active_speed != tp->link_config.active_speed ||
5798 orig_active_duplex != tp->link_config.active_duplex)
5799 tg3_link_report(tp);
5805 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
5809 u16 current_speed = SPEED_UNKNOWN;
5810 u8 current_duplex = DUPLEX_UNKNOWN;
5811 bool current_link_up = false;
5812 u32 local_adv, remote_adv, sgsr;
5814 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5815 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5816 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5817 (sgsr & SERDES_TG3_SGMII_MODE)) {
5822 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5824 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5825 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5827 current_link_up = true;
5828 if (sgsr & SERDES_TG3_SPEED_1000) {
5829 current_speed = SPEED_1000;
5830 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5831 } else if (sgsr & SERDES_TG3_SPEED_100) {
5832 current_speed = SPEED_100;
5833 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5835 current_speed = SPEED_10;
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5839 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5840 current_duplex = DUPLEX_FULL;
5842 current_duplex = DUPLEX_HALF;
5845 tw32_f(MAC_MODE, tp->mac_mode);
5848 tg3_clear_mac_status(tp);
5850 goto fiber_setup_done;
5853 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5854 tw32_f(MAC_MODE, tp->mac_mode);
5857 tg3_clear_mac_status(tp);
5862 tp->link_config.rmt_adv = 0;
5864 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5865 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5866 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5867 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5868 bmsr |= BMSR_LSTATUS;
5870 bmsr &= ~BMSR_LSTATUS;
5873 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5875 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5876 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5877 /* do nothing, just check for link up at the end */
5878 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5881 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5882 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5883 ADVERTISE_1000XPAUSE |
5884 ADVERTISE_1000XPSE_ASYM |
5887 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5888 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5890 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5891 tg3_writephy(tp, MII_ADVERTISE, newadv);
5892 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5893 tg3_writephy(tp, MII_BMCR, bmcr);
5895 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5896 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5897 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5904 bmcr &= ~BMCR_SPEED1000;
5905 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5907 if (tp->link_config.duplex == DUPLEX_FULL)
5908 new_bmcr |= BMCR_FULLDPLX;
5910 if (new_bmcr != bmcr) {
5911 /* BMCR_SPEED1000 is a reserved bit that needs
5912 * to be set on write.
5914 new_bmcr |= BMCR_SPEED1000;
5916 /* Force a linkdown */
5920 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5921 adv &= ~(ADVERTISE_1000XFULL |
5922 ADVERTISE_1000XHALF |
5924 tg3_writephy(tp, MII_ADVERTISE, adv);
5925 tg3_writephy(tp, MII_BMCR, bmcr |
5929 tg3_carrier_off(tp);
5931 tg3_writephy(tp, MII_BMCR, new_bmcr);
5933 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5934 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5935 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5936 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5937 bmsr |= BMSR_LSTATUS;
5939 bmsr &= ~BMSR_LSTATUS;
5941 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5945 if (bmsr & BMSR_LSTATUS) {
5946 current_speed = SPEED_1000;
5947 current_link_up = true;
5948 if (bmcr & BMCR_FULLDPLX)
5949 current_duplex = DUPLEX_FULL;
5951 current_duplex = DUPLEX_HALF;
5956 if (bmcr & BMCR_ANENABLE) {
5959 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5960 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5961 common = local_adv & remote_adv;
5962 if (common & (ADVERTISE_1000XHALF |
5963 ADVERTISE_1000XFULL)) {
5964 if (common & ADVERTISE_1000XFULL)
5965 current_duplex = DUPLEX_FULL;
5967 current_duplex = DUPLEX_HALF;
5969 tp->link_config.rmt_adv =
5970 mii_adv_to_ethtool_adv_x(remote_adv);
5971 } else if (!tg3_flag(tp, 5780_CLASS)) {
5972 /* Link is up via parallel detect */
5974 current_link_up = false;
5980 if (current_link_up && current_duplex == DUPLEX_FULL)
5981 tg3_setup_flow_control(tp, local_adv, remote_adv);
5983 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5984 if (tp->link_config.active_duplex == DUPLEX_HALF)
5985 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5987 tw32_f(MAC_MODE, tp->mac_mode);
5990 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5992 tp->link_config.active_speed = current_speed;
5993 tp->link_config.active_duplex = current_duplex;
5995 tg3_test_and_report_link_chg(tp, current_link_up);
5999 static void tg3_serdes_parallel_detect(struct tg3 *tp)
6001 if (tp->serdes_counter) {
6002 /* Give autoneg time to complete. */
6003 tp->serdes_counter--;
6008 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6011 tg3_readphy(tp, MII_BMCR, &bmcr);
6012 if (bmcr & BMCR_ANENABLE) {
6015 /* Select shadow register 0x1f */
6016 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6017 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
6019 /* Select expansion interrupt status register */
6020 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6021 MII_TG3_DSP_EXP1_INT_STAT);
6022 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6023 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6025 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6026 /* We have signal detect and not receiving
6027 * config code words, link is up by parallel
6031 bmcr &= ~BMCR_ANENABLE;
6032 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6033 tg3_writephy(tp, MII_BMCR, bmcr);
6034 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
6037 } else if (tp->link_up &&
6038 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
6039 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
6042 /* Select expansion interrupt status register */
6043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6044 MII_TG3_DSP_EXP1_INT_STAT);
6045 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6049 /* Config code words received, turn on autoneg. */
6050 tg3_readphy(tp, MII_BMCR, &bmcr);
6051 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6053 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
6059 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
6064 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
6065 err = tg3_setup_fiber_phy(tp, force_reset);
6066 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
6067 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6069 err = tg3_setup_copper_phy(tp, force_reset);
6071 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
6074 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6075 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6077 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6082 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6083 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6084 tw32(GRC_MISC_CFG, val);
6087 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6088 (6 << TX_LENGTHS_IPG_SHIFT);
6089 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6090 tg3_asic_rev(tp) == ASIC_REV_5762)
6091 val |= tr32(MAC_TX_LENGTHS) &
6092 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6093 TX_LENGTHS_CNT_DWN_VAL_MSK);
6095 if (tp->link_config.active_speed == SPEED_1000 &&
6096 tp->link_config.active_duplex == DUPLEX_HALF)
6097 tw32(MAC_TX_LENGTHS, val |
6098 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
6100 tw32(MAC_TX_LENGTHS, val |
6101 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6103 if (!tg3_flag(tp, 5705_PLUS)) {
6105 tw32(HOSTCC_STAT_COAL_TICKS,
6106 tp->coal.stats_block_coalesce_usecs);
6108 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6112 if (tg3_flag(tp, ASPM_WORKAROUND)) {
6113 val = tr32(PCIE_PWR_MGMT_THRESH);
6115 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6118 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6119 tw32(PCIE_PWR_MGMT_THRESH, val);
6125 /* tp->lock must be held */
6126 static u64 tg3_refclk_read(struct tg3 *tp)
6128 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6129 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6132 /* tp->lock must be held */
6133 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6135 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6137 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6138 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6139 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6140 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
6143 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6144 static inline void tg3_full_unlock(struct tg3 *tp);
6145 static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6147 struct tg3 *tp = netdev_priv(dev);
6149 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6150 SOF_TIMESTAMPING_RX_SOFTWARE |
6151 SOF_TIMESTAMPING_SOFTWARE;
6153 if (tg3_flag(tp, PTP_CAPABLE)) {
6154 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
6155 SOF_TIMESTAMPING_RX_HARDWARE |
6156 SOF_TIMESTAMPING_RAW_HARDWARE;
6160 info->phc_index = ptp_clock_index(tp->ptp_clock);
6162 info->phc_index = -1;
6164 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6166 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6167 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6168 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6169 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6173 static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6175 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6176 bool neg_adj = false;
6184 /* Frequency adjustment is performed using hardware with a 24 bit
6185 * accumulator and a programmable correction value. On each clk, the
6186 * correction value gets added to the accumulator and when it
6187 * overflows, the time counter is incremented/decremented.
6189 * So conversion from ppb to correction value is
6190 * ppb * (1 << 24) / 1000000000
6192 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6193 TG3_EAV_REF_CLK_CORRECT_MASK;
6195 tg3_full_lock(tp, 0);
6198 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6199 TG3_EAV_REF_CLK_CORRECT_EN |
6200 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6202 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6204 tg3_full_unlock(tp);
6209 static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6211 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6213 tg3_full_lock(tp, 0);
6214 tp->ptp_adjust += delta;
6215 tg3_full_unlock(tp);
6220 static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6224 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6226 tg3_full_lock(tp, 0);
6227 ns = tg3_refclk_read(tp);
6228 ns += tp->ptp_adjust;
6229 tg3_full_unlock(tp);
6231 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6232 ts->tv_nsec = remainder;
6237 static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6238 const struct timespec *ts)
6241 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6243 ns = timespec_to_ns(ts);
6245 tg3_full_lock(tp, 0);
6246 tg3_refclk_write(tp, ns);
6248 tg3_full_unlock(tp);
6253 static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6254 struct ptp_clock_request *rq, int on)
6256 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6261 case PTP_CLK_REQ_PEROUT:
6262 if (rq->perout.index != 0)
6265 tg3_full_lock(tp, 0);
6266 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6267 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6272 nsec = rq->perout.start.sec * 1000000000ULL +
6273 rq->perout.start.nsec;
6275 if (rq->perout.period.sec || rq->perout.period.nsec) {
6276 netdev_warn(tp->dev,
6277 "Device supports only a one-shot timesync output, period must be 0\n");
6282 if (nsec & (1ULL << 63)) {
6283 netdev_warn(tp->dev,
6284 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6289 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6290 tw32(TG3_EAV_WATCHDOG0_MSB,
6291 TG3_EAV_WATCHDOG0_EN |
6292 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6294 tw32(TG3_EAV_REF_CLCK_CTL,
6295 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6297 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6298 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6302 tg3_full_unlock(tp);
6312 static const struct ptp_clock_info tg3_ptp_caps = {
6313 .owner = THIS_MODULE,
6314 .name = "tg3 clock",
6315 .max_adj = 250000000,
6321 .adjfreq = tg3_ptp_adjfreq,
6322 .adjtime = tg3_ptp_adjtime,
6323 .gettime = tg3_ptp_gettime,
6324 .settime = tg3_ptp_settime,
6325 .enable = tg3_ptp_enable,
6328 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6329 struct skb_shared_hwtstamps *timestamp)
6331 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6332 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6336 /* tp->lock must be held */
6337 static void tg3_ptp_init(struct tg3 *tp)
6339 if (!tg3_flag(tp, PTP_CAPABLE))
6342 /* Initialize the hardware clock to the system time. */
6343 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6345 tp->ptp_info = tg3_ptp_caps;
6348 /* tp->lock must be held */
6349 static void tg3_ptp_resume(struct tg3 *tp)
6351 if (!tg3_flag(tp, PTP_CAPABLE))
6354 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6358 static void tg3_ptp_fini(struct tg3 *tp)
6360 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6363 ptp_clock_unregister(tp->ptp_clock);
6364 tp->ptp_clock = NULL;
6368 static inline int tg3_irq_sync(struct tg3 *tp)
6370 return tp->irq_sync;
6373 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6377 dst = (u32 *)((u8 *)dst + off);
6378 for (i = 0; i < len; i += sizeof(u32))
6379 *dst++ = tr32(off + i);
6382 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6384 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6385 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6386 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6387 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6388 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6389 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6390 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6391 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6392 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6393 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6394 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6395 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6396 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6397 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6398 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6399 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6400 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6401 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6402 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6404 if (tg3_flag(tp, SUPPORT_MSIX))
6405 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6407 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6408 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6409 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6410 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6411 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6412 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6413 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6414 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6416 if (!tg3_flag(tp, 5705_PLUS)) {
6417 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6418 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6419 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6422 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6423 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6424 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6425 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6426 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6428 if (tg3_flag(tp, NVRAM))
6429 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6432 static void tg3_dump_state(struct tg3 *tp)
6437 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
6441 if (tg3_flag(tp, PCI_EXPRESS)) {
6442 /* Read up to but not including private PCI registers */
6443 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6444 regs[i / sizeof(u32)] = tr32(i);
6446 tg3_dump_legacy_regs(tp, regs);
6448 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6449 if (!regs[i + 0] && !regs[i + 1] &&
6450 !regs[i + 2] && !regs[i + 3])
6453 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6455 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6460 for (i = 0; i < tp->irq_cnt; i++) {
6461 struct tg3_napi *tnapi = &tp->napi[i];
6463 /* SW status block */
6465 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6467 tnapi->hw_status->status,
6468 tnapi->hw_status->status_tag,
6469 tnapi->hw_status->rx_jumbo_consumer,
6470 tnapi->hw_status->rx_consumer,
6471 tnapi->hw_status->rx_mini_consumer,
6472 tnapi->hw_status->idx[0].rx_producer,
6473 tnapi->hw_status->idx[0].tx_consumer);
6476 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6478 tnapi->last_tag, tnapi->last_irq_tag,
6479 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6481 tnapi->prodring.rx_std_prod_idx,
6482 tnapi->prodring.rx_std_cons_idx,
6483 tnapi->prodring.rx_jmb_prod_idx,
6484 tnapi->prodring.rx_jmb_cons_idx);
6488 /* This is called whenever we suspect that the system chipset is re-
6489 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6490 * is bogus tx completions. We try to recover by setting the
6491 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6494 static void tg3_tx_recover(struct tg3 *tp)
6496 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6497 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6499 netdev_warn(tp->dev,
6500 "The system may be re-ordering memory-mapped I/O "
6501 "cycles to the network device, attempting to recover. "
6502 "Please report the problem to the driver maintainer "
6503 "and include system chipset information.\n");
6505 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6508 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
6510 /* Tell compiler to fetch tx indices from memory. */
6512 return tnapi->tx_pending -
6513 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
6516 /* Tigon3 never reports partial packet sends. So we do not
6517 * need special logic to handle SKBs that have not had all
6518 * of their frags sent yet, like SunGEM does.
6520 static void tg3_tx(struct tg3_napi *tnapi)
6522 struct tg3 *tp = tnapi->tp;
6523 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
6524 u32 sw_idx = tnapi->tx_cons;
6525 struct netdev_queue *txq;
6526 int index = tnapi - tp->napi;
6527 unsigned int pkts_compl = 0, bytes_compl = 0;
6529 if (tg3_flag(tp, ENABLE_TSS))
6532 txq = netdev_get_tx_queue(tp->dev, index);
6534 while (sw_idx != hw_idx) {
6535 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
6536 struct sk_buff *skb = ri->skb;
6539 if (unlikely(skb == NULL)) {
6544 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6545 struct skb_shared_hwtstamps timestamp;
6546 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6547 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6549 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6551 skb_tstamp_tx(skb, ×tamp);
6554 pci_unmap_single(tp->pdev,
6555 dma_unmap_addr(ri, mapping),
6561 while (ri->fragmented) {
6562 ri->fragmented = false;
6563 sw_idx = NEXT_TX(sw_idx);
6564 ri = &tnapi->tx_buffers[sw_idx];
6567 sw_idx = NEXT_TX(sw_idx);
6569 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6570 ri = &tnapi->tx_buffers[sw_idx];
6571 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6574 pci_unmap_page(tp->pdev,
6575 dma_unmap_addr(ri, mapping),
6576 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6579 while (ri->fragmented) {
6580 ri->fragmented = false;
6581 sw_idx = NEXT_TX(sw_idx);
6582 ri = &tnapi->tx_buffers[sw_idx];
6585 sw_idx = NEXT_TX(sw_idx);
6589 bytes_compl += skb->len;
6591 dev_kfree_skb_any(skb);
6593 if (unlikely(tx_bug)) {
6599 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
6601 tnapi->tx_cons = sw_idx;
6603 /* Need to make the tx_cons update visible to tg3_start_xmit()
6604 * before checking for netif_queue_stopped(). Without the
6605 * memory barrier, there is a small possibility that tg3_start_xmit()
6606 * will miss it and cause the queue to be stopped forever.
6610 if (unlikely(netif_tx_queue_stopped(txq) &&
6611 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
6612 __netif_tx_lock(txq, smp_processor_id());
6613 if (netif_tx_queue_stopped(txq) &&
6614 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
6615 netif_tx_wake_queue(txq);
6616 __netif_tx_unlock(txq);
6620 static void tg3_frag_free(bool is_frag, void *data)
6623 put_page(virt_to_head_page(data));
6628 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6630 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6631 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6636 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
6637 map_sz, PCI_DMA_FROMDEVICE);
6638 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
6643 /* Returns size of skb allocated or < 0 on error.
6645 * We only need to fill in the address because the other members
6646 * of the RX descriptor are invariant, see tg3_init_rings.
6648 * Note the purposeful assymetry of cpu vs. chip accesses. For
6649 * posting buffers we only dirty the first cache line of the RX
6650 * descriptor (containing the address). Whereas for the RX status
6651 * buffers the cpu only reads the last cacheline of the RX descriptor
6652 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6654 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6655 u32 opaque_key, u32 dest_idx_unmasked,
6656 unsigned int *frag_size)
6658 struct tg3_rx_buffer_desc *desc;
6659 struct ring_info *map;
6662 int skb_size, data_size, dest_idx;
6664 switch (opaque_key) {
6665 case RXD_OPAQUE_RING_STD:
6666 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6667 desc = &tpr->rx_std[dest_idx];
6668 map = &tpr->rx_std_buffers[dest_idx];
6669 data_size = tp->rx_pkt_map_sz;
6672 case RXD_OPAQUE_RING_JUMBO:
6673 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6674 desc = &tpr->rx_jmb[dest_idx].std;
6675 map = &tpr->rx_jmb_buffers[dest_idx];
6676 data_size = TG3_RX_JMB_MAP_SZ;
6683 /* Do not overwrite any of the map or rp information
6684 * until we are sure we can commit to a new buffer.
6686 * Callers depend upon this behavior and assume that
6687 * we leave everything unchanged if we fail.
6689 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6690 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6691 if (skb_size <= PAGE_SIZE) {
6692 data = netdev_alloc_frag(skb_size);
6693 *frag_size = skb_size;
6695 data = kmalloc(skb_size, GFP_ATOMIC);
6701 mapping = pci_map_single(tp->pdev,
6702 data + TG3_RX_OFFSET(tp),
6704 PCI_DMA_FROMDEVICE);
6705 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
6706 tg3_frag_free(skb_size <= PAGE_SIZE, data);
6711 dma_unmap_addr_set(map, mapping, mapping);
6713 desc->addr_hi = ((u64)mapping >> 32);
6714 desc->addr_lo = ((u64)mapping & 0xffffffff);
6719 /* We only need to move over in the address because the other
6720 * members of the RX descriptor are invariant. See notes above
6721 * tg3_alloc_rx_data for full details.
6723 static void tg3_recycle_rx(struct tg3_napi *tnapi,
6724 struct tg3_rx_prodring_set *dpr,
6725 u32 opaque_key, int src_idx,
6726 u32 dest_idx_unmasked)
6728 struct tg3 *tp = tnapi->tp;
6729 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6730 struct ring_info *src_map, *dest_map;
6731 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6734 switch (opaque_key) {
6735 case RXD_OPAQUE_RING_STD:
6736 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6737 dest_desc = &dpr->rx_std[dest_idx];
6738 dest_map = &dpr->rx_std_buffers[dest_idx];
6739 src_desc = &spr->rx_std[src_idx];
6740 src_map = &spr->rx_std_buffers[src_idx];
6743 case RXD_OPAQUE_RING_JUMBO:
6744 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6745 dest_desc = &dpr->rx_jmb[dest_idx].std;
6746 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6747 src_desc = &spr->rx_jmb[src_idx].std;
6748 src_map = &spr->rx_jmb_buffers[src_idx];
6755 dest_map->data = src_map->data;
6756 dma_unmap_addr_set(dest_map, mapping,
6757 dma_unmap_addr(src_map, mapping));
6758 dest_desc->addr_hi = src_desc->addr_hi;
6759 dest_desc->addr_lo = src_desc->addr_lo;
6761 /* Ensure that the update to the skb happens after the physical
6762 * addresses have been transferred to the new BD location.
6766 src_map->data = NULL;
6769 /* The RX ring scheme is composed of multiple rings which post fresh
6770 * buffers to the chip, and one special ring the chip uses to report
6771 * status back to the host.
6773 * The special ring reports the status of received packets to the
6774 * host. The chip does not write into the original descriptor the
6775 * RX buffer was obtained from. The chip simply takes the original
6776 * descriptor as provided by the host, updates the status and length
6777 * field, then writes this into the next status ring entry.
6779 * Each ring the host uses to post buffers to the chip is described
6780 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6781 * it is first placed into the on-chip ram. When the packet's length
6782 * is known, it walks down the TG3_BDINFO entries to select the ring.
6783 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6784 * which is within the range of the new packet's length is chosen.
6786 * The "separate ring for rx status" scheme may sound queer, but it makes
6787 * sense from a cache coherency perspective. If only the host writes
6788 * to the buffer post rings, and only the chip writes to the rx status
6789 * rings, then cache lines never move beyond shared-modified state.
6790 * If both the host and chip were to write into the same ring, cache line
6791 * eviction could occur since both entities want it in an exclusive state.
6793 static int tg3_rx(struct tg3_napi *tnapi, int budget)
6795 struct tg3 *tp = tnapi->tp;
6796 u32 work_mask, rx_std_posted = 0;
6797 u32 std_prod_idx, jmb_prod_idx;
6798 u32 sw_idx = tnapi->rx_rcb_ptr;
6801 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
6803 hw_idx = *(tnapi->rx_rcb_prod_idx);
6805 * We need to order the read of hw_idx and the read of
6806 * the opaque cookie.
6811 std_prod_idx = tpr->rx_std_prod_idx;
6812 jmb_prod_idx = tpr->rx_jmb_prod_idx;
6813 while (sw_idx != hw_idx && budget > 0) {
6814 struct ring_info *ri;
6815 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
6817 struct sk_buff *skb;
6818 dma_addr_t dma_addr;
6819 u32 opaque_key, desc_idx, *post_ptr;
6823 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6824 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6825 if (opaque_key == RXD_OPAQUE_RING_STD) {
6826 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6827 dma_addr = dma_unmap_addr(ri, mapping);
6829 post_ptr = &std_prod_idx;
6831 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
6832 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6833 dma_addr = dma_unmap_addr(ri, mapping);
6835 post_ptr = &jmb_prod_idx;
6837 goto next_pkt_nopost;
6839 work_mask |= opaque_key;
6841 if (desc->err_vlan & RXD_ERR_MASK) {
6843 tg3_recycle_rx(tnapi, tpr, opaque_key,
6844 desc_idx, *post_ptr);
6846 /* Other statistics kept track of by card. */
6851 prefetch(data + TG3_RX_OFFSET(tp));
6852 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6855 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6856 RXD_FLAG_PTPSTAT_PTPV1 ||
6857 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6858 RXD_FLAG_PTPSTAT_PTPV2) {
6859 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6860 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6863 if (len > TG3_RX_COPY_THRESH(tp)) {
6865 unsigned int frag_size;
6867 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6868 *post_ptr, &frag_size);
6872 pci_unmap_single(tp->pdev, dma_addr, skb_size,
6873 PCI_DMA_FROMDEVICE);
6875 /* Ensure that the update to the data happens
6876 * after the usage of the old DMA mapping.
6882 skb = build_skb(data, frag_size);
6884 tg3_frag_free(frag_size != 0, data);
6885 goto drop_it_no_recycle;
6887 skb_reserve(skb, TG3_RX_OFFSET(tp));
6889 tg3_recycle_rx(tnapi, tpr, opaque_key,
6890 desc_idx, *post_ptr);
6892 skb = netdev_alloc_skb(tp->dev,
6893 len + TG3_RAW_IP_ALIGN);
6895 goto drop_it_no_recycle;
6897 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6898 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6900 data + TG3_RX_OFFSET(tp),
6902 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6907 tg3_hwclock_to_timestamp(tp, tstamp,
6908 skb_hwtstamps(skb));
6910 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6911 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6912 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6913 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6914 skb->ip_summed = CHECKSUM_UNNECESSARY;
6916 skb_checksum_none_assert(skb);
6918 skb->protocol = eth_type_trans(skb, tp->dev);
6920 if (len > (tp->dev->mtu + ETH_HLEN) &&
6921 skb->protocol != htons(ETH_P_8021Q) &&
6922 skb->protocol != htons(ETH_P_8021AD)) {
6923 dev_kfree_skb_any(skb);
6924 goto drop_it_no_recycle;
6927 if (desc->type_flags & RXD_FLAG_VLAN &&
6928 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6929 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
6930 desc->err_vlan & RXD_VLAN_MASK);
6932 napi_gro_receive(&tnapi->napi, skb);
6940 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6941 tpr->rx_std_prod_idx = std_prod_idx &
6942 tp->rx_std_ring_mask;
6943 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6944 tpr->rx_std_prod_idx);
6945 work_mask &= ~RXD_OPAQUE_RING_STD;
6950 sw_idx &= tp->rx_ret_ring_mask;
6952 /* Refresh hw_idx to see if there is new work */
6953 if (sw_idx == hw_idx) {
6954 hw_idx = *(tnapi->rx_rcb_prod_idx);
6959 /* ACK the status ring. */
6960 tnapi->rx_rcb_ptr = sw_idx;
6961 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6963 /* Refill RX ring(s). */
6964 if (!tg3_flag(tp, ENABLE_RSS)) {
6965 /* Sync BD data before updating mailbox */
6968 if (work_mask & RXD_OPAQUE_RING_STD) {
6969 tpr->rx_std_prod_idx = std_prod_idx &
6970 tp->rx_std_ring_mask;
6971 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6972 tpr->rx_std_prod_idx);
6974 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6975 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6976 tp->rx_jmb_ring_mask;
6977 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6978 tpr->rx_jmb_prod_idx);
6981 } else if (work_mask) {
6982 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6983 * updated before the producer indices can be updated.
6987 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6988 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
6990 if (tnapi != &tp->napi[1]) {
6991 tp->rx_refill = true;
6992 napi_schedule(&tp->napi[1].napi);
6999 static void tg3_poll_link(struct tg3 *tp)
7001 /* handle link change and other phy events */
7002 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
7003 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7005 if (sblk->status & SD_STATUS_LINK_CHG) {
7006 sblk->status = SD_STATUS_UPDATED |
7007 (sblk->status & ~SD_STATUS_LINK_CHG);
7008 spin_lock(&tp->lock);
7009 if (tg3_flag(tp, USE_PHYLIB)) {
7011 (MAC_STATUS_SYNC_CHANGED |
7012 MAC_STATUS_CFG_CHANGED |
7013 MAC_STATUS_MI_COMPLETION |
7014 MAC_STATUS_LNKSTATE_CHANGED));
7017 tg3_setup_phy(tp, false);
7018 spin_unlock(&tp->lock);
7023 static int tg3_rx_prodring_xfer(struct tg3 *tp,
7024 struct tg3_rx_prodring_set *dpr,
7025 struct tg3_rx_prodring_set *spr)
7027 u32 si, di, cpycnt, src_prod_idx;
7031 src_prod_idx = spr->rx_std_prod_idx;
7033 /* Make sure updates to the rx_std_buffers[] entries and the
7034 * standard producer index are seen in the correct order.
7038 if (spr->rx_std_cons_idx == src_prod_idx)
7041 if (spr->rx_std_cons_idx < src_prod_idx)
7042 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7044 cpycnt = tp->rx_std_ring_mask + 1 -
7045 spr->rx_std_cons_idx;
7047 cpycnt = min(cpycnt,
7048 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
7050 si = spr->rx_std_cons_idx;
7051 di = dpr->rx_std_prod_idx;
7053 for (i = di; i < di + cpycnt; i++) {
7054 if (dpr->rx_std_buffers[i].data) {
7064 /* Ensure that updates to the rx_std_buffers ring and the
7065 * shadowed hardware producer ring from tg3_recycle_skb() are
7066 * ordered correctly WRT the skb check above.
7070 memcpy(&dpr->rx_std_buffers[di],
7071 &spr->rx_std_buffers[si],
7072 cpycnt * sizeof(struct ring_info));
7074 for (i = 0; i < cpycnt; i++, di++, si++) {
7075 struct tg3_rx_buffer_desc *sbd, *dbd;
7076 sbd = &spr->rx_std[si];
7077 dbd = &dpr->rx_std[di];
7078 dbd->addr_hi = sbd->addr_hi;
7079 dbd->addr_lo = sbd->addr_lo;
7082 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7083 tp->rx_std_ring_mask;
7084 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7085 tp->rx_std_ring_mask;
7089 src_prod_idx = spr->rx_jmb_prod_idx;
7091 /* Make sure updates to the rx_jmb_buffers[] entries and
7092 * the jumbo producer index are seen in the correct order.
7096 if (spr->rx_jmb_cons_idx == src_prod_idx)
7099 if (spr->rx_jmb_cons_idx < src_prod_idx)
7100 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7102 cpycnt = tp->rx_jmb_ring_mask + 1 -
7103 spr->rx_jmb_cons_idx;
7105 cpycnt = min(cpycnt,
7106 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
7108 si = spr->rx_jmb_cons_idx;
7109 di = dpr->rx_jmb_prod_idx;
7111 for (i = di; i < di + cpycnt; i++) {
7112 if (dpr->rx_jmb_buffers[i].data) {
7122 /* Ensure that updates to the rx_jmb_buffers ring and the
7123 * shadowed hardware producer ring from tg3_recycle_skb() are
7124 * ordered correctly WRT the skb check above.
7128 memcpy(&dpr->rx_jmb_buffers[di],
7129 &spr->rx_jmb_buffers[si],
7130 cpycnt * sizeof(struct ring_info));
7132 for (i = 0; i < cpycnt; i++, di++, si++) {
7133 struct tg3_rx_buffer_desc *sbd, *dbd;
7134 sbd = &spr->rx_jmb[si].std;
7135 dbd = &dpr->rx_jmb[di].std;
7136 dbd->addr_hi = sbd->addr_hi;
7137 dbd->addr_lo = sbd->addr_lo;
7140 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7141 tp->rx_jmb_ring_mask;
7142 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7143 tp->rx_jmb_ring_mask;
7149 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7151 struct tg3 *tp = tnapi->tp;
7153 /* run TX completion thread */
7154 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
7156 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7160 if (!tnapi->rx_rcb_prod_idx)
7163 /* run RX thread, within the bounds set by NAPI.
7164 * All RX "locking" is done by ensuring outside
7165 * code synchronizes with tg3->napi.poll()
7167 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
7168 work_done += tg3_rx(tnapi, budget - work_done);
7170 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
7171 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
7173 u32 std_prod_idx = dpr->rx_std_prod_idx;
7174 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
7176 tp->rx_refill = false;
7177 for (i = 1; i <= tp->rxq_cnt; i++)
7178 err |= tg3_rx_prodring_xfer(tp, dpr,
7179 &tp->napi[i].prodring);
7183 if (std_prod_idx != dpr->rx_std_prod_idx)
7184 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7185 dpr->rx_std_prod_idx);
7187 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7188 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7189 dpr->rx_jmb_prod_idx);
7194 tw32_f(HOSTCC_MODE, tp->coal_now);
7200 static inline void tg3_reset_task_schedule(struct tg3 *tp)
7202 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7203 schedule_work(&tp->reset_task);
7206 static inline void tg3_reset_task_cancel(struct tg3 *tp)
7208 cancel_work_sync(&tp->reset_task);
7209 tg3_flag_clear(tp, RESET_TASK_PENDING);
7210 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7213 static int tg3_poll_msix(struct napi_struct *napi, int budget)
7215 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7216 struct tg3 *tp = tnapi->tp;
7218 struct tg3_hw_status *sblk = tnapi->hw_status;
7221 work_done = tg3_poll_work(tnapi, work_done, budget);
7223 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7226 if (unlikely(work_done >= budget))
7229 /* tp->last_tag is used in tg3_int_reenable() below
7230 * to tell the hw how much work has been processed,
7231 * so we must read it before checking for more work.
7233 tnapi->last_tag = sblk->status_tag;
7234 tnapi->last_irq_tag = tnapi->last_tag;
7237 /* check for RX/TX work to do */
7238 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7239 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7241 /* This test here is not race free, but will reduce
7242 * the number of interrupts by looping again.
7244 if (tnapi == &tp->napi[1] && tp->rx_refill)
7247 napi_complete(napi);
7248 /* Reenable interrupts. */
7249 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7251 /* This test here is synchronized by napi_schedule()
7252 * and napi_complete() to close the race condition.
7254 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7255 tw32(HOSTCC_MODE, tp->coalesce_mode |
7256 HOSTCC_MODE_ENABLE |
7267 /* work_done is guaranteed to be less than budget. */
7268 napi_complete(napi);
7269 tg3_reset_task_schedule(tp);
7273 static void tg3_process_error(struct tg3 *tp)
7276 bool real_error = false;
7278 if (tg3_flag(tp, ERROR_PROCESSED))
7281 /* Check Flow Attention register */
7282 val = tr32(HOSTCC_FLOW_ATTN);
7283 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7284 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7288 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7289 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7293 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7294 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7303 tg3_flag_set(tp, ERROR_PROCESSED);
7304 tg3_reset_task_schedule(tp);
7307 static int tg3_poll(struct napi_struct *napi, int budget)
7309 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7310 struct tg3 *tp = tnapi->tp;
7312 struct tg3_hw_status *sblk = tnapi->hw_status;
7315 if (sblk->status & SD_STATUS_ERROR)
7316 tg3_process_error(tp);
7320 work_done = tg3_poll_work(tnapi, work_done, budget);
7322 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7325 if (unlikely(work_done >= budget))
7328 if (tg3_flag(tp, TAGGED_STATUS)) {
7329 /* tp->last_tag is used in tg3_int_reenable() below
7330 * to tell the hw how much work has been processed,
7331 * so we must read it before checking for more work.
7333 tnapi->last_tag = sblk->status_tag;
7334 tnapi->last_irq_tag = tnapi->last_tag;
7337 sblk->status &= ~SD_STATUS_UPDATED;
7339 if (likely(!tg3_has_work(tnapi))) {
7340 napi_complete(napi);
7341 tg3_int_reenable(tnapi);
7349 /* work_done is guaranteed to be less than budget. */
7350 napi_complete(napi);
7351 tg3_reset_task_schedule(tp);
7355 static void tg3_napi_disable(struct tg3 *tp)
7359 for (i = tp->irq_cnt - 1; i >= 0; i--)
7360 napi_disable(&tp->napi[i].napi);
7363 static void tg3_napi_enable(struct tg3 *tp)
7367 for (i = 0; i < tp->irq_cnt; i++)
7368 napi_enable(&tp->napi[i].napi);
7371 static void tg3_napi_init(struct tg3 *tp)
7375 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7376 for (i = 1; i < tp->irq_cnt; i++)
7377 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7380 static void tg3_napi_fini(struct tg3 *tp)
7384 for (i = 0; i < tp->irq_cnt; i++)
7385 netif_napi_del(&tp->napi[i].napi);
7388 static inline void tg3_netif_stop(struct tg3 *tp)
7390 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7391 tg3_napi_disable(tp);
7392 netif_carrier_off(tp->dev);
7393 netif_tx_disable(tp->dev);
7396 /* tp->lock must be held */
7397 static inline void tg3_netif_start(struct tg3 *tp)
7401 /* NOTE: unconditional netif_tx_wake_all_queues is only
7402 * appropriate so long as all callers are assured to
7403 * have free tx slots (such as after tg3_init_hw)
7405 netif_tx_wake_all_queues(tp->dev);
7408 netif_carrier_on(tp->dev);
7410 tg3_napi_enable(tp);
7411 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7412 tg3_enable_ints(tp);
7415 static void tg3_irq_quiesce(struct tg3 *tp)
7419 BUG_ON(tp->irq_sync);
7424 for (i = 0; i < tp->irq_cnt; i++)
7425 synchronize_irq(tp->napi[i].irq_vec);
7428 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7429 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7430 * with as well. Most of the time, this is not necessary except when
7431 * shutting down the device.
7433 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7435 spin_lock_bh(&tp->lock);
7437 tg3_irq_quiesce(tp);
7440 static inline void tg3_full_unlock(struct tg3 *tp)
7442 spin_unlock_bh(&tp->lock);
7445 /* One-shot MSI handler - Chip automatically disables interrupt
7446 * after sending MSI so driver doesn't have to do it.
7448 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
7450 struct tg3_napi *tnapi = dev_id;
7451 struct tg3 *tp = tnapi->tp;
7453 prefetch(tnapi->hw_status);
7455 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7457 if (likely(!tg3_irq_sync(tp)))
7458 napi_schedule(&tnapi->napi);
7463 /* MSI ISR - No need to check for interrupt sharing and no need to
7464 * flush status block and interrupt mailbox. PCI ordering rules
7465 * guarantee that MSI will arrive after the status block.
7467 static irqreturn_t tg3_msi(int irq, void *dev_id)
7469 struct tg3_napi *tnapi = dev_id;
7470 struct tg3 *tp = tnapi->tp;
7472 prefetch(tnapi->hw_status);
7474 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7476 * Writing any value to intr-mbox-0 clears PCI INTA# and
7477 * chip-internal interrupt pending events.
7478 * Writing non-zero to intr-mbox-0 additional tells the
7479 * NIC to stop sending us irqs, engaging "in-intr-handler"
7482 tw32_mailbox(tnapi->int_mbox, 0x00000001);
7483 if (likely(!tg3_irq_sync(tp)))
7484 napi_schedule(&tnapi->napi);
7486 return IRQ_RETVAL(1);
7489 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
7491 struct tg3_napi *tnapi = dev_id;
7492 struct tg3 *tp = tnapi->tp;
7493 struct tg3_hw_status *sblk = tnapi->hw_status;
7494 unsigned int handled = 1;
7496 /* In INTx mode, it is possible for the interrupt to arrive at
7497 * the CPU before the status block posted prior to the interrupt.
7498 * Reading the PCI State register will confirm whether the
7499 * interrupt is ours and will flush the status block.
7501 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
7502 if (tg3_flag(tp, CHIP_RESETTING) ||
7503 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7510 * Writing any value to intr-mbox-0 clears PCI INTA# and
7511 * chip-internal interrupt pending events.
7512 * Writing non-zero to intr-mbox-0 additional tells the
7513 * NIC to stop sending us irqs, engaging "in-intr-handler"
7516 * Flush the mailbox to de-assert the IRQ immediately to prevent
7517 * spurious interrupts. The flush impacts performance but
7518 * excessive spurious interrupts can be worse in some cases.
7520 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7521 if (tg3_irq_sync(tp))
7523 sblk->status &= ~SD_STATUS_UPDATED;
7524 if (likely(tg3_has_work(tnapi))) {
7525 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7526 napi_schedule(&tnapi->napi);
7528 /* No work, shared interrupt perhaps? re-enable
7529 * interrupts, and flush that PCI write
7531 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7535 return IRQ_RETVAL(handled);
7538 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
7540 struct tg3_napi *tnapi = dev_id;
7541 struct tg3 *tp = tnapi->tp;
7542 struct tg3_hw_status *sblk = tnapi->hw_status;
7543 unsigned int handled = 1;
7545 /* In INTx mode, it is possible for the interrupt to arrive at
7546 * the CPU before the status block posted prior to the interrupt.
7547 * Reading the PCI State register will confirm whether the
7548 * interrupt is ours and will flush the status block.
7550 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
7551 if (tg3_flag(tp, CHIP_RESETTING) ||
7552 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7559 * writing any value to intr-mbox-0 clears PCI INTA# and
7560 * chip-internal interrupt pending events.
7561 * writing non-zero to intr-mbox-0 additional tells the
7562 * NIC to stop sending us irqs, engaging "in-intr-handler"
7565 * Flush the mailbox to de-assert the IRQ immediately to prevent
7566 * spurious interrupts. The flush impacts performance but
7567 * excessive spurious interrupts can be worse in some cases.
7569 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7572 * In a shared interrupt configuration, sometimes other devices'
7573 * interrupts will scream. We record the current status tag here
7574 * so that the above check can report that the screaming interrupts
7575 * are unhandled. Eventually they will be silenced.
7577 tnapi->last_irq_tag = sblk->status_tag;
7579 if (tg3_irq_sync(tp))
7582 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7584 napi_schedule(&tnapi->napi);
7587 return IRQ_RETVAL(handled);
7590 /* ISR for interrupt test */
7591 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7593 struct tg3_napi *tnapi = dev_id;
7594 struct tg3 *tp = tnapi->tp;
7595 struct tg3_hw_status *sblk = tnapi->hw_status;
7597 if ((sblk->status & SD_STATUS_UPDATED) ||
7598 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7599 tg3_disable_ints(tp);
7600 return IRQ_RETVAL(1);
7602 return IRQ_RETVAL(0);
7605 #ifdef CONFIG_NET_POLL_CONTROLLER
7606 static void tg3_poll_controller(struct net_device *dev)
7609 struct tg3 *tp = netdev_priv(dev);
7611 if (tg3_irq_sync(tp))
7614 for (i = 0; i < tp->irq_cnt; i++)
7615 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7619 static void tg3_tx_timeout(struct net_device *dev)
7621 struct tg3 *tp = netdev_priv(dev);
7623 if (netif_msg_tx_err(tp)) {
7624 netdev_err(dev, "transmit timed out, resetting\n");
7628 tg3_reset_task_schedule(tp);
7631 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7632 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7634 u32 base = (u32) mapping & 0xffffffff;
7636 return base + len + 8 < base;
7639 /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7640 * of any 4GB boundaries: 4G, 8G, etc
7642 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7645 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7646 u32 base = (u32) mapping & 0xffffffff;
7648 return ((base + len + (mss & 0x3fff)) < base);
7653 /* Test for DMA addresses > 40-bit */
7654 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7657 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7658 if (tg3_flag(tp, 40BIT_DMA_BUG))
7659 return ((u64) mapping + len) > DMA_BIT_MASK(40);
7666 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
7667 dma_addr_t mapping, u32 len, u32 flags,
7670 txbd->addr_hi = ((u64) mapping >> 32);
7671 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7672 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7673 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
7676 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
7677 dma_addr_t map, u32 len, u32 flags,
7680 struct tg3 *tp = tnapi->tp;
7683 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7686 if (tg3_4g_overflow_test(map, len))
7689 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7692 if (tg3_40bit_overflow_test(tp, map, len))
7695 if (tp->dma_limit) {
7696 u32 prvidx = *entry;
7697 u32 tmp_flag = flags & ~TXD_FLAG_END;
7698 while (len > tp->dma_limit && *budget) {
7699 u32 frag_len = tp->dma_limit;
7700 len -= tp->dma_limit;
7702 /* Avoid the 8byte DMA problem */
7704 len += tp->dma_limit / 2;
7705 frag_len = tp->dma_limit / 2;
7708 tnapi->tx_buffers[*entry].fragmented = true;
7710 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7711 frag_len, tmp_flag, mss, vlan);
7714 *entry = NEXT_TX(*entry);
7721 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7722 len, flags, mss, vlan);
7724 *entry = NEXT_TX(*entry);
7727 tnapi->tx_buffers[prvidx].fragmented = false;
7731 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7732 len, flags, mss, vlan);
7733 *entry = NEXT_TX(*entry);
7739 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
7742 struct sk_buff *skb;
7743 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
7748 pci_unmap_single(tnapi->tp->pdev,
7749 dma_unmap_addr(txb, mapping),
7753 while (txb->fragmented) {
7754 txb->fragmented = false;
7755 entry = NEXT_TX(entry);
7756 txb = &tnapi->tx_buffers[entry];
7759 for (i = 0; i <= last; i++) {
7760 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7762 entry = NEXT_TX(entry);
7763 txb = &tnapi->tx_buffers[entry];
7765 pci_unmap_page(tnapi->tp->pdev,
7766 dma_unmap_addr(txb, mapping),
7767 skb_frag_size(frag), PCI_DMA_TODEVICE);
7769 while (txb->fragmented) {
7770 txb->fragmented = false;
7771 entry = NEXT_TX(entry);
7772 txb = &tnapi->tx_buffers[entry];
7777 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7778 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
7779 struct sk_buff **pskb,
7780 u32 *entry, u32 *budget,
7781 u32 base_flags, u32 mss, u32 vlan)
7783 struct tg3 *tp = tnapi->tp;
7784 struct sk_buff *new_skb, *skb = *pskb;
7785 dma_addr_t new_addr = 0;
7788 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7789 new_skb = skb_copy(skb, GFP_ATOMIC);
7791 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7793 new_skb = skb_copy_expand(skb,
7794 skb_headroom(skb) + more_headroom,
7795 skb_tailroom(skb), GFP_ATOMIC);
7801 /* New SKB is guaranteed to be linear. */
7802 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7804 /* Make sure the mapping succeeded */
7805 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
7806 dev_kfree_skb_any(new_skb);
7809 u32 save_entry = *entry;
7811 base_flags |= TXD_FLAG_END;
7813 tnapi->tx_buffers[*entry].skb = new_skb;
7814 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
7817 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
7818 new_skb->len, base_flags,
7820 tg3_tx_skb_unmap(tnapi, save_entry, -1);
7821 dev_kfree_skb_any(new_skb);
7827 dev_kfree_skb_any(skb);
7832 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
7834 /* Use GSO to workaround all TSO packets that meet HW bug conditions
7835 * indicated in tg3_tx_frag_set()
7837 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,
7838 struct netdev_queue *txq, struct sk_buff *skb)
7840 struct sk_buff *segs, *nskb;
7841 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
7843 /* Estimate the number of fragments in the worst case */
7844 if (unlikely(tg3_tx_avail(tnapi) <= frag_cnt_est)) {
7845 netif_tx_stop_queue(txq);
7847 /* netif_tx_stop_queue() must be done before checking
7848 * checking tx index in tg3_tx_avail() below, because in
7849 * tg3_tx(), we update tx index before checking for
7850 * netif_tx_queue_stopped().
7853 if (tg3_tx_avail(tnapi) <= frag_cnt_est)
7854 return NETDEV_TX_BUSY;
7856 netif_tx_wake_queue(txq);
7859 segs = skb_gso_segment(skb, tp->dev->features &
7860 ~(NETIF_F_TSO | NETIF_F_TSO6));
7861 if (IS_ERR(segs) || !segs)
7862 goto tg3_tso_bug_end;
7868 tg3_start_xmit(nskb, tp->dev);
7872 dev_kfree_skb_any(skb);
7874 return NETDEV_TX_OK;
7877 /* hard_start_xmit for all devices */
7878 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
7880 struct tg3 *tp = netdev_priv(dev);
7881 u32 len, entry, base_flags, mss, vlan = 0;
7883 int i = -1, would_hit_hwbug;
7885 struct tg3_napi *tnapi;
7886 struct netdev_queue *txq;
7888 struct iphdr *iph = NULL;
7889 struct tcphdr *tcph = NULL;
7890 __sum16 tcp_csum = 0, ip_csum = 0;
7891 __be16 ip_tot_len = 0;
7893 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7894 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7895 if (tg3_flag(tp, ENABLE_TSS))
7898 budget = tg3_tx_avail(tnapi);
7900 /* We are running in BH disabled context with netif_tx_lock
7901 * and TX reclaim runs via tp->napi.poll inside of a software
7902 * interrupt. Furthermore, IRQ processing runs lockless so we have
7903 * no IRQ context deadlocks to worry about either. Rejoice!
7905 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
7906 if (!netif_tx_queue_stopped(txq)) {
7907 netif_tx_stop_queue(txq);
7909 /* This is a hard error, log it. */
7911 "BUG! Tx Ring full when queue awake!\n");
7913 return NETDEV_TX_BUSY;
7916 entry = tnapi->tx_prod;
7919 mss = skb_shinfo(skb)->gso_size;
7921 u32 tcp_opt_len, hdr_len;
7923 if (skb_cow_head(skb, 0))
7927 tcp_opt_len = tcp_optlen(skb);
7929 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
7931 /* HW/FW can not correctly segment packets that have been
7932 * vlan encapsulated.
7934 if (skb->protocol == htons(ETH_P_8021Q) ||
7935 skb->protocol == htons(ETH_P_8021AD))
7936 return tg3_tso_bug(tp, tnapi, txq, skb);
7938 if (!skb_is_gso_v6(skb)) {
7939 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7940 tg3_flag(tp, TSO_BUG))
7941 return tg3_tso_bug(tp, tnapi, txq, skb);
7943 ip_csum = iph->check;
7944 ip_tot_len = iph->tot_len;
7946 iph->tot_len = htons(mss + hdr_len);
7949 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7950 TXD_FLAG_CPU_POST_DMA);
7952 tcph = tcp_hdr(skb);
7953 tcp_csum = tcph->check;
7955 if (tg3_flag(tp, HW_TSO_1) ||
7956 tg3_flag(tp, HW_TSO_2) ||
7957 tg3_flag(tp, HW_TSO_3)) {
7959 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7961 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
7965 if (tg3_flag(tp, HW_TSO_3)) {
7966 mss |= (hdr_len & 0xc) << 12;
7968 base_flags |= 0x00000010;
7969 base_flags |= (hdr_len & 0x3e0) << 5;
7970 } else if (tg3_flag(tp, HW_TSO_2))
7971 mss |= hdr_len << 9;
7972 else if (tg3_flag(tp, HW_TSO_1) ||
7973 tg3_asic_rev(tp) == ASIC_REV_5705) {
7974 if (tcp_opt_len || iph->ihl > 5) {
7977 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7978 mss |= (tsflags << 11);
7981 if (tcp_opt_len || iph->ihl > 5) {
7984 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7985 base_flags |= tsflags << 12;
7988 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7989 /* HW/FW can not correctly checksum packets that have been
7990 * vlan encapsulated.
7992 if (skb->protocol == htons(ETH_P_8021Q) ||
7993 skb->protocol == htons(ETH_P_8021AD)) {
7994 if (skb_checksum_help(skb))
7997 base_flags |= TXD_FLAG_TCPUDP_CSUM;
8001 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
8002 !mss && skb->len > VLAN_ETH_FRAME_LEN)
8003 base_flags |= TXD_FLAG_JMB_PKT;
8005 if (vlan_tx_tag_present(skb)) {
8006 base_flags |= TXD_FLAG_VLAN;
8007 vlan = vlan_tx_tag_get(skb);
8010 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
8011 tg3_flag(tp, TX_TSTAMP_EN)) {
8012 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8013 base_flags |= TXD_FLAG_HWTSTAMP;
8016 len = skb_headlen(skb);
8018 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
8019 if (pci_dma_mapping_error(tp->pdev, mapping))
8023 tnapi->tx_buffers[entry].skb = skb;
8024 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
8026 would_hit_hwbug = 0;
8028 if (tg3_flag(tp, 5701_DMA_BUG))
8029 would_hit_hwbug = 1;
8031 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
8032 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
8034 would_hit_hwbug = 1;
8035 } else if (skb_shinfo(skb)->nr_frags > 0) {
8038 if (!tg3_flag(tp, HW_TSO_1) &&
8039 !tg3_flag(tp, HW_TSO_2) &&
8040 !tg3_flag(tp, HW_TSO_3))
8043 /* Now loop through additional data
8044 * fragments, and queue them.
8046 last = skb_shinfo(skb)->nr_frags - 1;
8047 for (i = 0; i <= last; i++) {
8048 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8050 len = skb_frag_size(frag);
8051 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
8052 len, DMA_TO_DEVICE);
8054 tnapi->tx_buffers[entry].skb = NULL;
8055 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
8057 if (dma_mapping_error(&tp->pdev->dev, mapping))
8061 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
8063 ((i == last) ? TXD_FLAG_END : 0),
8065 would_hit_hwbug = 1;
8071 if (would_hit_hwbug) {
8072 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
8075 /* If it's a TSO packet, do GSO instead of
8076 * allocating and copying to a large linear SKB
8079 iph->check = ip_csum;
8080 iph->tot_len = ip_tot_len;
8082 tcph->check = tcp_csum;
8083 return tg3_tso_bug(tp, tnapi, txq, skb);
8086 /* If the workaround fails due to memory/mapping
8087 * failure, silently drop this packet.
8089 entry = tnapi->tx_prod;
8090 budget = tg3_tx_avail(tnapi);
8091 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
8092 base_flags, mss, vlan))
8096 skb_tx_timestamp(skb);
8097 netdev_tx_sent_queue(txq, skb->len);
8099 /* Sync BD data before updating mailbox */
8102 tnapi->tx_prod = entry;
8103 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
8104 netif_tx_stop_queue(txq);
8106 /* netif_tx_stop_queue() must be done before checking
8107 * checking tx index in tg3_tx_avail() below, because in
8108 * tg3_tx(), we update tx index before checking for
8109 * netif_tx_queue_stopped().
8112 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
8113 netif_tx_wake_queue(txq);
8116 if (!skb->xmit_more || netif_xmit_stopped(txq)) {
8117 /* Packets are ready, update Tx producer idx on card. */
8118 tw32_tx_mbox(tnapi->prodmbox, entry);
8122 return NETDEV_TX_OK;
8125 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
8126 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
8128 dev_kfree_skb_any(skb);
8131 return NETDEV_TX_OK;
8134 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8137 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8138 MAC_MODE_PORT_MODE_MASK);
8140 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8142 if (!tg3_flag(tp, 5705_PLUS))
8143 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8145 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8146 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8148 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8150 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8152 if (tg3_flag(tp, 5705_PLUS) ||
8153 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
8154 tg3_asic_rev(tp) == ASIC_REV_5700)
8155 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8158 tw32(MAC_MODE, tp->mac_mode);
8162 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
8164 u32 val, bmcr, mac_mode, ptest = 0;
8166 tg3_phy_toggle_apd(tp, false);
8167 tg3_phy_toggle_automdix(tp, false);
8169 if (extlpbk && tg3_phy_set_extloopbk(tp))
8172 bmcr = BMCR_FULLDPLX;
8177 bmcr |= BMCR_SPEED100;
8181 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8183 bmcr |= BMCR_SPEED100;
8186 bmcr |= BMCR_SPEED1000;
8191 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8192 tg3_readphy(tp, MII_CTRL1000, &val);
8193 val |= CTL1000_AS_MASTER |
8194 CTL1000_ENABLE_MASTER;
8195 tg3_writephy(tp, MII_CTRL1000, val);
8197 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8198 MII_TG3_FET_PTEST_TRIM_2;
8199 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8202 bmcr |= BMCR_LOOPBACK;
8204 tg3_writephy(tp, MII_BMCR, bmcr);
8206 /* The write needs to be flushed for the FETs */
8207 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8208 tg3_readphy(tp, MII_BMCR, &bmcr);
8212 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
8213 tg3_asic_rev(tp) == ASIC_REV_5785) {
8214 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8215 MII_TG3_FET_PTEST_FRC_TX_LINK |
8216 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8218 /* The write needs to be flushed for the AC131 */
8219 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8222 /* Reset to prevent losing 1st rx packet intermittently */
8223 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8224 tg3_flag(tp, 5780_CLASS)) {
8225 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8227 tw32_f(MAC_RX_MODE, tp->rx_mode);
8230 mac_mode = tp->mac_mode &
8231 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8232 if (speed == SPEED_1000)
8233 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8235 mac_mode |= MAC_MODE_PORT_MODE_MII;
8237 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
8238 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8240 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8241 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8242 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8243 mac_mode |= MAC_MODE_LINK_POLARITY;
8245 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8246 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8249 tw32(MAC_MODE, mac_mode);
8255 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
8257 struct tg3 *tp = netdev_priv(dev);
8259 if (features & NETIF_F_LOOPBACK) {
8260 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8263 spin_lock_bh(&tp->lock);
8264 tg3_mac_loopback(tp, true);
8265 netif_carrier_on(tp->dev);
8266 spin_unlock_bh(&tp->lock);
8267 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8269 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8272 spin_lock_bh(&tp->lock);
8273 tg3_mac_loopback(tp, false);
8274 /* Force link status check */
8275 tg3_setup_phy(tp, true);
8276 spin_unlock_bh(&tp->lock);
8277 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8281 static netdev_features_t tg3_fix_features(struct net_device *dev,
8282 netdev_features_t features)
8284 struct tg3 *tp = netdev_priv(dev);
8286 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8287 features &= ~NETIF_F_ALL_TSO;
8292 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
8294 netdev_features_t changed = dev->features ^ features;
8296 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8297 tg3_set_loopback(dev, features);
8302 static void tg3_rx_prodring_free(struct tg3 *tp,
8303 struct tg3_rx_prodring_set *tpr)
8307 if (tpr != &tp->napi[0].prodring) {
8308 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
8309 i = (i + 1) & tp->rx_std_ring_mask)
8310 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8313 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8314 for (i = tpr->rx_jmb_cons_idx;
8315 i != tpr->rx_jmb_prod_idx;
8316 i = (i + 1) & tp->rx_jmb_ring_mask) {
8317 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8325 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8326 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8329 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8330 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8331 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8336 /* Initialize rx rings for packet processing.
8338 * The chip has been shut down and the driver detached from
8339 * the networking, so no interrupts or new tx packets will
8340 * end up in the driver. tp->{tx,}lock are held and thus
8343 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8344 struct tg3_rx_prodring_set *tpr)
8346 u32 i, rx_pkt_dma_sz;
8348 tpr->rx_std_cons_idx = 0;
8349 tpr->rx_std_prod_idx = 0;
8350 tpr->rx_jmb_cons_idx = 0;
8351 tpr->rx_jmb_prod_idx = 0;
8353 if (tpr != &tp->napi[0].prodring) {
8354 memset(&tpr->rx_std_buffers[0], 0,
8355 TG3_RX_STD_BUFF_RING_SIZE(tp));
8356 if (tpr->rx_jmb_buffers)
8357 memset(&tpr->rx_jmb_buffers[0], 0,
8358 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8362 /* Zero out all descriptors. */
8363 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8365 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
8366 if (tg3_flag(tp, 5780_CLASS) &&
8367 tp->dev->mtu > ETH_DATA_LEN)
8368 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8369 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8371 /* Initialize invariants of the rings, we only set this
8372 * stuff once. This works because the card does not
8373 * write into the rx buffer posting rings.
8375 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8376 struct tg3_rx_buffer_desc *rxd;
8378 rxd = &tpr->rx_std[i];
8379 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
8380 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8381 rxd->opaque = (RXD_OPAQUE_RING_STD |
8382 (i << RXD_OPAQUE_INDEX_SHIFT));
8385 /* Now allocate fresh SKBs for each rx ring. */
8386 for (i = 0; i < tp->rx_pending; i++) {
8387 unsigned int frag_size;
8389 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8391 netdev_warn(tp->dev,
8392 "Using a smaller RX standard ring. Only "
8393 "%d out of %d buffers were allocated "
8394 "successfully\n", i, tp->rx_pending);
8402 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8405 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8407 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8410 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8411 struct tg3_rx_buffer_desc *rxd;
8413 rxd = &tpr->rx_jmb[i].std;
8414 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8415 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8417 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8418 (i << RXD_OPAQUE_INDEX_SHIFT));
8421 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8422 unsigned int frag_size;
8424 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8426 netdev_warn(tp->dev,
8427 "Using a smaller RX jumbo ring. Only %d "
8428 "out of %d buffers were allocated "
8429 "successfully\n", i, tp->rx_jumbo_pending);
8432 tp->rx_jumbo_pending = i;
8441 tg3_rx_prodring_free(tp, tpr);
8445 static void tg3_rx_prodring_fini(struct tg3 *tp,
8446 struct tg3_rx_prodring_set *tpr)
8448 kfree(tpr->rx_std_buffers);
8449 tpr->rx_std_buffers = NULL;
8450 kfree(tpr->rx_jmb_buffers);
8451 tpr->rx_jmb_buffers = NULL;
8453 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8454 tpr->rx_std, tpr->rx_std_mapping);
8458 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8459 tpr->rx_jmb, tpr->rx_jmb_mapping);
8464 static int tg3_rx_prodring_init(struct tg3 *tp,
8465 struct tg3_rx_prodring_set *tpr)
8467 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8469 if (!tpr->rx_std_buffers)
8472 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8473 TG3_RX_STD_RING_BYTES(tp),
8474 &tpr->rx_std_mapping,
8479 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8480 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8482 if (!tpr->rx_jmb_buffers)
8485 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8486 TG3_RX_JMB_RING_BYTES(tp),
8487 &tpr->rx_jmb_mapping,
8496 tg3_rx_prodring_fini(tp, tpr);
8500 /* Free up pending packets in all rx/tx rings.
8502 * The chip has been shut down and the driver detached from
8503 * the networking, so no interrupts or new tx packets will
8504 * end up in the driver. tp->{tx,}lock is not held and we are not
8505 * in an interrupt context and thus may sleep.
8507 static void tg3_free_rings(struct tg3 *tp)
8511 for (j = 0; j < tp->irq_cnt; j++) {
8512 struct tg3_napi *tnapi = &tp->napi[j];
8514 tg3_rx_prodring_free(tp, &tnapi->prodring);
8516 if (!tnapi->tx_buffers)
8519 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8520 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
8525 tg3_tx_skb_unmap(tnapi, i,
8526 skb_shinfo(skb)->nr_frags - 1);
8528 dev_kfree_skb_any(skb);
8530 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8534 /* Initialize tx/rx rings for packet processing.
8536 * The chip has been shut down and the driver detached from
8537 * the networking, so no interrupts or new tx packets will
8538 * end up in the driver. tp->{tx,}lock are held and thus
8541 static int tg3_init_rings(struct tg3 *tp)
8545 /* Free up all the SKBs. */
8548 for (i = 0; i < tp->irq_cnt; i++) {
8549 struct tg3_napi *tnapi = &tp->napi[i];
8551 tnapi->last_tag = 0;
8552 tnapi->last_irq_tag = 0;
8553 tnapi->hw_status->status = 0;
8554 tnapi->hw_status->status_tag = 0;
8555 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8560 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
8562 tnapi->rx_rcb_ptr = 0;
8564 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8566 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8575 static void tg3_mem_tx_release(struct tg3 *tp)
8579 for (i = 0; i < tp->irq_max; i++) {
8580 struct tg3_napi *tnapi = &tp->napi[i];
8582 if (tnapi->tx_ring) {
8583 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8584 tnapi->tx_ring, tnapi->tx_desc_mapping);
8585 tnapi->tx_ring = NULL;
8588 kfree(tnapi->tx_buffers);
8589 tnapi->tx_buffers = NULL;
8593 static int tg3_mem_tx_acquire(struct tg3 *tp)
8596 struct tg3_napi *tnapi = &tp->napi[0];
8598 /* If multivector TSS is enabled, vector 0 does not handle
8599 * tx interrupts. Don't allocate any resources for it.
8601 if (tg3_flag(tp, ENABLE_TSS))
8604 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8605 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8606 TG3_TX_RING_SIZE, GFP_KERNEL);
8607 if (!tnapi->tx_buffers)
8610 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8612 &tnapi->tx_desc_mapping,
8614 if (!tnapi->tx_ring)
8621 tg3_mem_tx_release(tp);
8625 static void tg3_mem_rx_release(struct tg3 *tp)
8629 for (i = 0; i < tp->irq_max; i++) {
8630 struct tg3_napi *tnapi = &tp->napi[i];
8632 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8637 dma_free_coherent(&tp->pdev->dev,
8638 TG3_RX_RCB_RING_BYTES(tp),
8640 tnapi->rx_rcb_mapping);
8641 tnapi->rx_rcb = NULL;
8645 static int tg3_mem_rx_acquire(struct tg3 *tp)
8647 unsigned int i, limit;
8649 limit = tp->rxq_cnt;
8651 /* If RSS is enabled, we need a (dummy) producer ring
8652 * set on vector zero. This is the true hw prodring.
8654 if (tg3_flag(tp, ENABLE_RSS))
8657 for (i = 0; i < limit; i++) {
8658 struct tg3_napi *tnapi = &tp->napi[i];
8660 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8663 /* If multivector RSS is enabled, vector 0
8664 * does not handle rx or tx interrupts.
8665 * Don't allocate any resources for it.
8667 if (!i && tg3_flag(tp, ENABLE_RSS))
8670 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8671 TG3_RX_RCB_RING_BYTES(tp),
8672 &tnapi->rx_rcb_mapping,
8681 tg3_mem_rx_release(tp);
8686 * Must not be invoked with interrupt sources disabled and
8687 * the hardware shutdown down.
8689 static void tg3_free_consistent(struct tg3 *tp)
8693 for (i = 0; i < tp->irq_cnt; i++) {
8694 struct tg3_napi *tnapi = &tp->napi[i];
8696 if (tnapi->hw_status) {
8697 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8699 tnapi->status_mapping);
8700 tnapi->hw_status = NULL;
8704 tg3_mem_rx_release(tp);
8705 tg3_mem_tx_release(tp);
8708 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8709 tp->hw_stats, tp->stats_mapping);
8710 tp->hw_stats = NULL;
8715 * Must not be invoked with interrupt sources disabled and
8716 * the hardware shutdown down. Can sleep.
8718 static int tg3_alloc_consistent(struct tg3 *tp)
8722 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8723 sizeof(struct tg3_hw_stats),
8724 &tp->stats_mapping, GFP_KERNEL);
8728 for (i = 0; i < tp->irq_cnt; i++) {
8729 struct tg3_napi *tnapi = &tp->napi[i];
8730 struct tg3_hw_status *sblk;
8732 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8734 &tnapi->status_mapping,
8736 if (!tnapi->hw_status)
8739 sblk = tnapi->hw_status;
8741 if (tg3_flag(tp, ENABLE_RSS)) {
8742 u16 *prodptr = NULL;
8745 * When RSS is enabled, the status block format changes
8746 * slightly. The "rx_jumbo_consumer", "reserved",
8747 * and "rx_mini_consumer" members get mapped to the
8748 * other three rx return ring producer indexes.
8752 prodptr = &sblk->idx[0].rx_producer;
8755 prodptr = &sblk->rx_jumbo_consumer;
8758 prodptr = &sblk->reserved;
8761 prodptr = &sblk->rx_mini_consumer;
8764 tnapi->rx_rcb_prod_idx = prodptr;
8766 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8770 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8776 tg3_free_consistent(tp);
8780 #define MAX_WAIT_CNT 1000
8782 /* To stop a block, clear the enable bit and poll till it
8783 * clears. tp->lock is held.
8785 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
8790 if (tg3_flag(tp, 5705_PLUS)) {
8797 /* We can't enable/disable these bits of the
8798 * 5705/5750, just say success.
8811 for (i = 0; i < MAX_WAIT_CNT; i++) {
8812 if (pci_channel_offline(tp->pdev)) {
8813 dev_err(&tp->pdev->dev,
8814 "tg3_stop_block device offline, "
8815 "ofs=%lx enable_bit=%x\n",
8822 if ((val & enable_bit) == 0)
8826 if (i == MAX_WAIT_CNT && !silent) {
8827 dev_err(&tp->pdev->dev,
8828 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8836 /* tp->lock is held. */
8837 static int tg3_abort_hw(struct tg3 *tp, bool silent)
8841 tg3_disable_ints(tp);
8843 if (pci_channel_offline(tp->pdev)) {
8844 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8845 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8850 tp->rx_mode &= ~RX_MODE_ENABLE;
8851 tw32_f(MAC_RX_MODE, tp->rx_mode);
8854 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8855 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8856 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8857 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8858 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8859 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8861 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8862 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8863 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8864 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8865 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8866 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8867 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8869 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8870 tw32_f(MAC_MODE, tp->mac_mode);
8873 tp->tx_mode &= ~TX_MODE_ENABLE;
8874 tw32_f(MAC_TX_MODE, tp->tx_mode);
8876 for (i = 0; i < MAX_WAIT_CNT; i++) {
8878 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8881 if (i >= MAX_WAIT_CNT) {
8882 dev_err(&tp->pdev->dev,
8883 "%s timed out, TX_MODE_ENABLE will not clear "
8884 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
8888 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8889 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8890 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8892 tw32(FTQ_RESET, 0xffffffff);
8893 tw32(FTQ_RESET, 0x00000000);
8895 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8896 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8899 for (i = 0; i < tp->irq_cnt; i++) {
8900 struct tg3_napi *tnapi = &tp->napi[i];
8901 if (tnapi->hw_status)
8902 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8908 /* Save PCI command register before chip reset */
8909 static void tg3_save_pci_state(struct tg3 *tp)
8911 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8914 /* Restore PCI state after chip reset */
8915 static void tg3_restore_pci_state(struct tg3 *tp)
8919 /* Re-enable indirect register accesses. */
8920 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8921 tp->misc_host_ctrl);
8923 /* Set MAX PCI retry to zero. */
8924 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8925 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8926 tg3_flag(tp, PCIX_MODE))
8927 val |= PCISTATE_RETRY_SAME_DMA;
8928 /* Allow reads and writes to the APE register and memory space. */
8929 if (tg3_flag(tp, ENABLE_APE))
8930 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8931 PCISTATE_ALLOW_APE_SHMEM_WR |
8932 PCISTATE_ALLOW_APE_PSPACE_WR;
8933 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8935 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8937 if (!tg3_flag(tp, PCI_EXPRESS)) {
8938 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8939 tp->pci_cacheline_sz);
8940 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8944 /* Make sure PCI-X relaxed ordering bit is clear. */
8945 if (tg3_flag(tp, PCIX_MODE)) {
8948 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8950 pcix_cmd &= ~PCI_X_CMD_ERO;
8951 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8955 if (tg3_flag(tp, 5780_CLASS)) {
8957 /* Chip reset on 5780 will reset MSI enable bit,
8958 * so need to restore it.
8960 if (tg3_flag(tp, USING_MSI)) {
8963 pci_read_config_word(tp->pdev,
8964 tp->msi_cap + PCI_MSI_FLAGS,
8966 pci_write_config_word(tp->pdev,
8967 tp->msi_cap + PCI_MSI_FLAGS,
8968 ctrl | PCI_MSI_FLAGS_ENABLE);
8969 val = tr32(MSGINT_MODE);
8970 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8975 static void tg3_override_clk(struct tg3 *tp)
8979 switch (tg3_asic_rev(tp)) {
8981 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8982 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
8983 TG3_CPMU_MAC_ORIDE_ENABLE);
8988 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8996 static void tg3_restore_clk(struct tg3 *tp)
9000 switch (tg3_asic_rev(tp)) {
9002 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9003 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
9004 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
9009 val = tr32(TG3_CPMU_CLCK_ORIDE);
9010 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9018 /* tp->lock is held. */
9019 static int tg3_chip_reset(struct tg3 *tp)
9022 void (*write_op)(struct tg3 *, u32, u32);
9025 if (!pci_device_is_present(tp->pdev))
9030 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9032 /* No matching tg3_nvram_unlock() after this because
9033 * chip reset below will undo the nvram lock.
9035 tp->nvram_lock_cnt = 0;
9037 /* GRC_MISC_CFG core clock reset will clear the memory
9038 * enable bit in PCI register 4 and the MSI enable bit
9039 * on some chips, so we save relevant registers here.
9041 tg3_save_pci_state(tp);
9043 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
9044 tg3_flag(tp, 5755_PLUS))
9045 tw32(GRC_FASTBOOT_PC, 0);
9048 * We must avoid the readl() that normally takes place.
9049 * It locks machines, causes machine checks, and other
9050 * fun things. So, temporarily disable the 5701
9051 * hardware workaround, while we do the reset.
9053 write_op = tp->write32;
9054 if (write_op == tg3_write_flush_reg32)
9055 tp->write32 = tg3_write32;
9057 /* Prevent the irq handler from reading or writing PCI registers
9058 * during chip reset when the memory enable bit in the PCI command
9059 * register may be cleared. The chip does not generate interrupt
9060 * at this time, but the irq handler may still be called due to irq
9061 * sharing or irqpoll.
9063 tg3_flag_set(tp, CHIP_RESETTING);
9064 for (i = 0; i < tp->irq_cnt; i++) {
9065 struct tg3_napi *tnapi = &tp->napi[i];
9066 if (tnapi->hw_status) {
9067 tnapi->hw_status->status = 0;
9068 tnapi->hw_status->status_tag = 0;
9070 tnapi->last_tag = 0;
9071 tnapi->last_irq_tag = 0;
9075 for (i = 0; i < tp->irq_cnt; i++)
9076 synchronize_irq(tp->napi[i].irq_vec);
9078 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9079 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9080 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9084 val = GRC_MISC_CFG_CORECLK_RESET;
9086 if (tg3_flag(tp, PCI_EXPRESS)) {
9087 /* Force PCIe 1.0a mode */
9088 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
9089 !tg3_flag(tp, 57765_PLUS) &&
9090 tr32(TG3_PCIE_PHY_TSTCTL) ==
9091 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9092 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9094 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
9095 tw32(GRC_MISC_CFG, (1 << 29));
9100 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9101 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9102 tw32(GRC_VCPU_EXT_CTRL,
9103 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9106 /* Set the clock to the highest frequency to avoid timeouts. With link
9107 * aware mode, the clock speed could be slow and bootcode does not
9108 * complete within the expected time. Override the clock to allow the
9109 * bootcode to finish sooner and then restore it.
9111 tg3_override_clk(tp);
9113 /* Manage gphy power for all CPMU absent PCIe devices. */
9114 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
9115 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
9117 tw32(GRC_MISC_CFG, val);
9119 /* restore 5701 hardware bug workaround write method */
9120 tp->write32 = write_op;
9122 /* Unfortunately, we have to delay before the PCI read back.
9123 * Some 575X chips even will not respond to a PCI cfg access
9124 * when the reset command is given to the chip.
9126 * How do these hardware designers expect things to work
9127 * properly if the PCI write is posted for a long period
9128 * of time? It is always necessary to have some method by
9129 * which a register read back can occur to push the write
9130 * out which does the reset.
9132 * For most tg3 variants the trick below was working.
9137 /* Flush PCI posted writes. The normal MMIO registers
9138 * are inaccessible at this time so this is the only
9139 * way to make this reliably (actually, this is no longer
9140 * the case, see above). I tried to use indirect
9141 * register read/write but this upset some 5701 variants.
9143 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9147 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
9150 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
9154 /* Wait for link training to complete. */
9155 for (j = 0; j < 5000; j++)
9158 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9159 pci_write_config_dword(tp->pdev, 0xc4,
9160 cfg_val | (1 << 15));
9163 /* Clear the "no snoop" and "relaxed ordering" bits. */
9164 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
9166 * Older PCIe devices only support the 128 byte
9167 * MPS setting. Enforce the restriction.
9169 if (!tg3_flag(tp, CPMU_PRESENT))
9170 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9171 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
9173 /* Clear error status */
9174 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
9175 PCI_EXP_DEVSTA_CED |
9176 PCI_EXP_DEVSTA_NFED |
9177 PCI_EXP_DEVSTA_FED |
9178 PCI_EXP_DEVSTA_URD);
9181 tg3_restore_pci_state(tp);
9183 tg3_flag_clear(tp, CHIP_RESETTING);
9184 tg3_flag_clear(tp, ERROR_PROCESSED);
9187 if (tg3_flag(tp, 5780_CLASS))
9188 val = tr32(MEMARB_MODE);
9189 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9191 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
9193 tw32(0x5000, 0x400);
9196 if (tg3_flag(tp, IS_SSB_CORE)) {
9198 * BCM4785: In order to avoid repercussions from using
9199 * potentially defective internal ROM, stop the Rx RISC CPU,
9200 * which is not required.
9203 tg3_halt_cpu(tp, RX_CPU_BASE);
9206 err = tg3_poll_fw(tp);
9210 tw32(GRC_MODE, tp->grc_mode);
9212 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
9215 tw32(0xc4, val | (1 << 15));
9218 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
9219 tg3_asic_rev(tp) == ASIC_REV_5705) {
9220 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
9221 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
9222 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9223 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9226 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9227 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
9229 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9230 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
9235 tw32_f(MAC_MODE, val);
9238 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9242 if (tg3_flag(tp, PCI_EXPRESS) &&
9243 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9244 tg3_asic_rev(tp) != ASIC_REV_5785 &&
9245 !tg3_flag(tp, 57765_PLUS)) {
9248 tw32(0x7c00, val | (1 << 25));
9251 tg3_restore_clk(tp);
9253 /* Reprobe ASF enable state. */
9254 tg3_flag_clear(tp, ENABLE_ASF);
9255 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9256 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9258 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
9259 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9260 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9263 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9264 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9265 tg3_flag_set(tp, ENABLE_ASF);
9266 tp->last_event_jiffies = jiffies;
9267 if (tg3_flag(tp, 5750_PLUS))
9268 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
9270 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9271 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9272 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9273 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9274 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
9281 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9282 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
9283 static void __tg3_set_rx_mode(struct net_device *);
9285 /* tp->lock is held. */
9286 static int tg3_halt(struct tg3 *tp, int kind, bool silent)
9292 tg3_write_sig_pre_reset(tp, kind);
9294 tg3_abort_hw(tp, silent);
9295 err = tg3_chip_reset(tp);
9297 __tg3_set_mac_addr(tp, false);
9299 tg3_write_sig_legacy(tp, kind);
9300 tg3_write_sig_post_reset(tp, kind);
9303 /* Save the stats across chip resets... */
9304 tg3_get_nstats(tp, &tp->net_stats_prev);
9305 tg3_get_estats(tp, &tp->estats_prev);
9307 /* And make sure the next sample is new data */
9308 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9314 static int tg3_set_mac_addr(struct net_device *dev, void *p)
9316 struct tg3 *tp = netdev_priv(dev);
9317 struct sockaddr *addr = p;
9319 bool skip_mac_1 = false;
9321 if (!is_valid_ether_addr(addr->sa_data))
9322 return -EADDRNOTAVAIL;
9324 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9326 if (!netif_running(dev))
9329 if (tg3_flag(tp, ENABLE_ASF)) {
9330 u32 addr0_high, addr0_low, addr1_high, addr1_low;
9332 addr0_high = tr32(MAC_ADDR_0_HIGH);
9333 addr0_low = tr32(MAC_ADDR_0_LOW);
9334 addr1_high = tr32(MAC_ADDR_1_HIGH);
9335 addr1_low = tr32(MAC_ADDR_1_LOW);
9337 /* Skip MAC addr 1 if ASF is using it. */
9338 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9339 !(addr1_high == 0 && addr1_low == 0))
9342 spin_lock_bh(&tp->lock);
9343 __tg3_set_mac_addr(tp, skip_mac_1);
9344 __tg3_set_rx_mode(dev);
9345 spin_unlock_bh(&tp->lock);
9350 /* tp->lock is held. */
9351 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9352 dma_addr_t mapping, u32 maxlen_flags,
9356 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9357 ((u64) mapping >> 32));
9359 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9360 ((u64) mapping & 0xffffffff));
9362 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9365 if (!tg3_flag(tp, 5705_PLUS))
9367 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9372 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9376 if (!tg3_flag(tp, ENABLE_TSS)) {
9377 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9378 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9379 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9381 tw32(HOSTCC_TXCOL_TICKS, 0);
9382 tw32(HOSTCC_TXMAX_FRAMES, 0);
9383 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9385 for (; i < tp->txq_cnt; i++) {
9388 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9389 tw32(reg, ec->tx_coalesce_usecs);
9390 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9391 tw32(reg, ec->tx_max_coalesced_frames);
9392 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9393 tw32(reg, ec->tx_max_coalesced_frames_irq);
9397 for (; i < tp->irq_max - 1; i++) {
9398 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9399 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9400 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9404 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9407 u32 limit = tp->rxq_cnt;
9409 if (!tg3_flag(tp, ENABLE_RSS)) {
9410 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9411 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9412 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9415 tw32(HOSTCC_RXCOL_TICKS, 0);
9416 tw32(HOSTCC_RXMAX_FRAMES, 0);
9417 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9420 for (; i < limit; i++) {
9423 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9424 tw32(reg, ec->rx_coalesce_usecs);
9425 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9426 tw32(reg, ec->rx_max_coalesced_frames);
9427 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9428 tw32(reg, ec->rx_max_coalesced_frames_irq);
9431 for (; i < tp->irq_max - 1; i++) {
9432 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9433 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9434 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9438 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9440 tg3_coal_tx_init(tp, ec);
9441 tg3_coal_rx_init(tp, ec);
9443 if (!tg3_flag(tp, 5705_PLUS)) {
9444 u32 val = ec->stats_block_coalesce_usecs;
9446 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9447 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9452 tw32(HOSTCC_STAT_COAL_TICKS, val);
9456 /* tp->lock is held. */
9457 static void tg3_tx_rcbs_disable(struct tg3 *tp)
9461 /* Disable all transmit rings but the first. */
9462 if (!tg3_flag(tp, 5705_PLUS))
9463 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9464 else if (tg3_flag(tp, 5717_PLUS))
9465 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9466 else if (tg3_flag(tp, 57765_CLASS) ||
9467 tg3_asic_rev(tp) == ASIC_REV_5762)
9468 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9470 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9472 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9473 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9474 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9475 BDINFO_FLAGS_DISABLED);
9478 /* tp->lock is held. */
9479 static void tg3_tx_rcbs_init(struct tg3 *tp)
9482 u32 txrcb = NIC_SRAM_SEND_RCB;
9484 if (tg3_flag(tp, ENABLE_TSS))
9487 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9488 struct tg3_napi *tnapi = &tp->napi[i];
9490 if (!tnapi->tx_ring)
9493 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9494 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9495 NIC_SRAM_TX_BUFFER_DESC);
9499 /* tp->lock is held. */
9500 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9504 /* Disable all receive return rings but the first. */
9505 if (tg3_flag(tp, 5717_PLUS))
9506 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9507 else if (!tg3_flag(tp, 5705_PLUS))
9508 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9509 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9510 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9511 tg3_flag(tp, 57765_CLASS))
9512 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9514 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9516 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9517 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9518 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9519 BDINFO_FLAGS_DISABLED);
9522 /* tp->lock is held. */
9523 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9526 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9528 if (tg3_flag(tp, ENABLE_RSS))
9531 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9532 struct tg3_napi *tnapi = &tp->napi[i];
9537 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9538 (tp->rx_ret_ring_mask + 1) <<
9539 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9543 /* tp->lock is held. */
9544 static void tg3_rings_reset(struct tg3 *tp)
9548 struct tg3_napi *tnapi = &tp->napi[0];
9550 tg3_tx_rcbs_disable(tp);
9552 tg3_rx_ret_rcbs_disable(tp);
9554 /* Disable interrupts */
9555 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9556 tp->napi[0].chk_msi_cnt = 0;
9557 tp->napi[0].last_rx_cons = 0;
9558 tp->napi[0].last_tx_cons = 0;
9560 /* Zero mailbox registers. */
9561 if (tg3_flag(tp, SUPPORT_MSIX)) {
9562 for (i = 1; i < tp->irq_max; i++) {
9563 tp->napi[i].tx_prod = 0;
9564 tp->napi[i].tx_cons = 0;
9565 if (tg3_flag(tp, ENABLE_TSS))
9566 tw32_mailbox(tp->napi[i].prodmbox, 0);
9567 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9568 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9569 tp->napi[i].chk_msi_cnt = 0;
9570 tp->napi[i].last_rx_cons = 0;
9571 tp->napi[i].last_tx_cons = 0;
9573 if (!tg3_flag(tp, ENABLE_TSS))
9574 tw32_mailbox(tp->napi[0].prodmbox, 0);
9576 tp->napi[0].tx_prod = 0;
9577 tp->napi[0].tx_cons = 0;
9578 tw32_mailbox(tp->napi[0].prodmbox, 0);
9579 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9582 /* Make sure the NIC-based send BD rings are disabled. */
9583 if (!tg3_flag(tp, 5705_PLUS)) {
9584 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9585 for (i = 0; i < 16; i++)
9586 tw32_tx_mbox(mbox + i * 8, 0);
9589 /* Clear status block in ram. */
9590 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9592 /* Set status block DMA address */
9593 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9594 ((u64) tnapi->status_mapping >> 32));
9595 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9596 ((u64) tnapi->status_mapping & 0xffffffff));
9598 stblk = HOSTCC_STATBLCK_RING1;
9600 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9601 u64 mapping = (u64)tnapi->status_mapping;
9602 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9603 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9606 /* Clear status block in ram. */
9607 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9610 tg3_tx_rcbs_init(tp);
9611 tg3_rx_ret_rcbs_init(tp);
9614 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9616 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9618 if (!tg3_flag(tp, 5750_PLUS) ||
9619 tg3_flag(tp, 5780_CLASS) ||
9620 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9621 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9622 tg3_flag(tp, 57765_PLUS))
9623 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
9624 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9625 tg3_asic_rev(tp) == ASIC_REV_5787)
9626 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9628 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9630 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9631 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9633 val = min(nic_rep_thresh, host_rep_thresh);
9634 tw32(RCVBDI_STD_THRESH, val);
9636 if (tg3_flag(tp, 57765_PLUS))
9637 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9639 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9642 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
9644 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9646 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9647 tw32(RCVBDI_JUMBO_THRESH, val);
9649 if (tg3_flag(tp, 57765_PLUS))
9650 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9653 static inline u32 calc_crc(unsigned char *buf, int len)
9661 for (j = 0; j < len; j++) {
9664 for (k = 0; k < 8; k++) {
9677 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9679 /* accept or reject all multicast frames */
9680 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9681 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9682 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9683 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9686 static void __tg3_set_rx_mode(struct net_device *dev)
9688 struct tg3 *tp = netdev_priv(dev);
9691 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9692 RX_MODE_KEEP_VLAN_TAG);
9694 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9695 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9698 if (!tg3_flag(tp, ENABLE_ASF))
9699 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9702 if (dev->flags & IFF_PROMISC) {
9703 /* Promiscuous mode. */
9704 rx_mode |= RX_MODE_PROMISC;
9705 } else if (dev->flags & IFF_ALLMULTI) {
9706 /* Accept all multicast. */
9707 tg3_set_multi(tp, 1);
9708 } else if (netdev_mc_empty(dev)) {
9709 /* Reject all multicast. */
9710 tg3_set_multi(tp, 0);
9712 /* Accept one or more multicast(s). */
9713 struct netdev_hw_addr *ha;
9714 u32 mc_filter[4] = { 0, };
9719 netdev_for_each_mc_addr(ha, dev) {
9720 crc = calc_crc(ha->addr, ETH_ALEN);
9722 regidx = (bit & 0x60) >> 5;
9724 mc_filter[regidx] |= (1 << bit);
9727 tw32(MAC_HASH_REG_0, mc_filter[0]);
9728 tw32(MAC_HASH_REG_1, mc_filter[1]);
9729 tw32(MAC_HASH_REG_2, mc_filter[2]);
9730 tw32(MAC_HASH_REG_3, mc_filter[3]);
9733 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9734 rx_mode |= RX_MODE_PROMISC;
9735 } else if (!(dev->flags & IFF_PROMISC)) {
9736 /* Add all entries into to the mac addr filter list */
9738 struct netdev_hw_addr *ha;
9740 netdev_for_each_uc_addr(ha, dev) {
9741 __tg3_set_one_mac_addr(tp, ha->addr,
9742 i + TG3_UCAST_ADDR_IDX(tp));
9747 if (rx_mode != tp->rx_mode) {
9748 tp->rx_mode = rx_mode;
9749 tw32_f(MAC_RX_MODE, rx_mode);
9754 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9758 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9759 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9762 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9766 if (!tg3_flag(tp, SUPPORT_MSIX))
9769 if (tp->rxq_cnt == 1) {
9770 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9774 /* Validate table against current IRQ count */
9775 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
9776 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9780 if (i != TG3_RSS_INDIR_TBL_SIZE)
9781 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9784 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9787 u32 reg = MAC_RSS_INDIR_TBL_0;
9789 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9790 u32 val = tp->rss_ind_tbl[i];
9792 for (; i % 8; i++) {
9794 val |= tp->rss_ind_tbl[i];
9801 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9803 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9804 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9806 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9809 /* tp->lock is held. */
9810 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
9812 u32 val, rdmac_mode;
9814 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9816 tg3_disable_ints(tp);
9820 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9822 if (tg3_flag(tp, INIT_COMPLETE))
9823 tg3_abort_hw(tp, 1);
9825 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9826 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9827 tg3_phy_pull_config(tp);
9828 tg3_eee_pull_config(tp, NULL);
9829 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9832 /* Enable MAC control of LPI */
9833 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9839 err = tg3_chip_reset(tp);
9843 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9845 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9846 val = tr32(TG3_CPMU_CTRL);
9847 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9848 tw32(TG3_CPMU_CTRL, val);
9850 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9851 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9852 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9853 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9855 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9856 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9857 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9858 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9860 val = tr32(TG3_CPMU_HST_ACC);
9861 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9862 val |= CPMU_HST_ACC_MACCLK_6_25;
9863 tw32(TG3_CPMU_HST_ACC, val);
9866 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9867 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9868 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9869 PCIE_PWR_MGMT_L1_THRESH_4MS;
9870 tw32(PCIE_PWR_MGMT_THRESH, val);
9872 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9873 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9875 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9877 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9878 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9881 if (tg3_flag(tp, L1PLLPD_EN)) {
9882 u32 grc_mode = tr32(GRC_MODE);
9884 /* Access the lower 1K of PL PCIE block registers. */
9885 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9886 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9888 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9889 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9890 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9892 tw32(GRC_MODE, grc_mode);
9895 if (tg3_flag(tp, 57765_CLASS)) {
9896 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9897 u32 grc_mode = tr32(GRC_MODE);
9899 /* Access the lower 1K of PL PCIE block registers. */
9900 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9901 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9903 val = tr32(TG3_PCIE_TLDLPL_PORT +
9904 TG3_PCIE_PL_LO_PHYCTL5);
9905 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9906 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
9908 tw32(GRC_MODE, grc_mode);
9911 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
9914 /* Fix transmit hangs */
9915 val = tr32(TG3_CPMU_PADRNG_CTL);
9916 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9917 tw32(TG3_CPMU_PADRNG_CTL, val);
9919 grc_mode = tr32(GRC_MODE);
9921 /* Access the lower 1K of DL PCIE block registers. */
9922 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9923 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9925 val = tr32(TG3_PCIE_TLDLPL_PORT +
9926 TG3_PCIE_DL_LO_FTSMAX);
9927 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9928 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9929 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9931 tw32(GRC_MODE, grc_mode);
9934 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9935 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9936 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9937 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9940 /* This works around an issue with Athlon chipsets on
9941 * B3 tigon3 silicon. This bit has no effect on any
9942 * other revision. But do not set this on PCI Express
9943 * chips and don't even touch the clocks if the CPMU is present.
9945 if (!tg3_flag(tp, CPMU_PRESENT)) {
9946 if (!tg3_flag(tp, PCI_EXPRESS))
9947 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9948 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9951 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
9952 tg3_flag(tp, PCIX_MODE)) {
9953 val = tr32(TG3PCI_PCISTATE);
9954 val |= PCISTATE_RETRY_SAME_DMA;
9955 tw32(TG3PCI_PCISTATE, val);
9958 if (tg3_flag(tp, ENABLE_APE)) {
9959 /* Allow reads and writes to the
9960 * APE register and memory space.
9962 val = tr32(TG3PCI_PCISTATE);
9963 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
9964 PCISTATE_ALLOW_APE_SHMEM_WR |
9965 PCISTATE_ALLOW_APE_PSPACE_WR;
9966 tw32(TG3PCI_PCISTATE, val);
9969 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
9970 /* Enable some hw fixes. */
9971 val = tr32(TG3PCI_MSI_DATA);
9972 val |= (1 << 26) | (1 << 28) | (1 << 29);
9973 tw32(TG3PCI_MSI_DATA, val);
9976 /* Descriptor ring init may make accesses to the
9977 * NIC SRAM area to setup the TX descriptors, so we
9978 * can only do this after the hardware has been
9979 * successfully reset.
9981 err = tg3_init_rings(tp);
9985 if (tg3_flag(tp, 57765_PLUS)) {
9986 val = tr32(TG3PCI_DMA_RW_CTRL) &
9987 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
9988 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
9989 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
9990 if (!tg3_flag(tp, 57765_CLASS) &&
9991 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9992 tg3_asic_rev(tp) != ASIC_REV_5762)
9993 val |= DMA_RWCTRL_TAGGED_STAT_WA;
9994 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
9995 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9996 tg3_asic_rev(tp) != ASIC_REV_5761) {
9997 /* This value is determined during the probe time DMA
9998 * engine test, tg3_test_dma.
10000 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10003 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
10004 GRC_MODE_4X_NIC_SEND_RINGS |
10005 GRC_MODE_NO_TX_PHDR_CSUM |
10006 GRC_MODE_NO_RX_PHDR_CSUM);
10007 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
10009 /* Pseudo-header checksum is done by hardware logic and not
10010 * the offload processers, so make the chip do the pseudo-
10011 * header checksums on receive. For transmit it is more
10012 * convenient to do the pseudo-header checksum in software
10013 * as Linux does that on transmit for us in all cases.
10015 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
10017 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
10019 tw32(TG3_RX_PTP_CTL,
10020 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
10022 if (tg3_flag(tp, PTP_CAPABLE))
10023 val |= GRC_MODE_TIME_SYNC_ENABLE;
10025 tw32(GRC_MODE, tp->grc_mode | val);
10027 /* Setup the timer prescalar register. Clock is always 66Mhz. */
10028 val = tr32(GRC_MISC_CFG);
10030 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
10031 tw32(GRC_MISC_CFG, val);
10033 /* Initialize MBUF/DESC pool. */
10034 if (tg3_flag(tp, 5750_PLUS)) {
10036 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
10037 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
10038 if (tg3_asic_rev(tp) == ASIC_REV_5704)
10039 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10041 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10042 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10043 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
10044 } else if (tg3_flag(tp, TSO_CAPABLE)) {
10047 fw_len = tp->fw_len;
10048 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10049 tw32(BUFMGR_MB_POOL_ADDR,
10050 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10051 tw32(BUFMGR_MB_POOL_SIZE,
10052 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10055 if (tp->dev->mtu <= ETH_DATA_LEN) {
10056 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10057 tp->bufmgr_config.mbuf_read_dma_low_water);
10058 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10059 tp->bufmgr_config.mbuf_mac_rx_low_water);
10060 tw32(BUFMGR_MB_HIGH_WATER,
10061 tp->bufmgr_config.mbuf_high_water);
10063 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10064 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10065 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10066 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10067 tw32(BUFMGR_MB_HIGH_WATER,
10068 tp->bufmgr_config.mbuf_high_water_jumbo);
10070 tw32(BUFMGR_DMA_LOW_WATER,
10071 tp->bufmgr_config.dma_low_water);
10072 tw32(BUFMGR_DMA_HIGH_WATER,
10073 tp->bufmgr_config.dma_high_water);
10075 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
10076 if (tg3_asic_rev(tp) == ASIC_REV_5719)
10077 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
10078 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10079 tg3_asic_rev(tp) == ASIC_REV_5762 ||
10080 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10081 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
10082 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
10083 tw32(BUFMGR_MODE, val);
10084 for (i = 0; i < 2000; i++) {
10085 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10090 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
10094 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
10095 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10097 tg3_setup_rxbd_thresholds(tp);
10099 /* Initialize TG3_BDINFO's at:
10100 * RCVDBDI_STD_BD: standard eth size rx ring
10101 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10102 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10105 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10106 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10107 * ring attribute flags
10108 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10110 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10111 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10113 * The size of each ring is fixed in the firmware, but the location is
10116 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10117 ((u64) tpr->rx_std_mapping >> 32));
10118 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10119 ((u64) tpr->rx_std_mapping & 0xffffffff));
10120 if (!tg3_flag(tp, 5717_PLUS))
10121 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10122 NIC_SRAM_RX_BUFFER_DESC);
10124 /* Disable the mini ring */
10125 if (!tg3_flag(tp, 5705_PLUS))
10126 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10127 BDINFO_FLAGS_DISABLED);
10129 /* Program the jumbo buffer descriptor ring control
10130 * blocks on those devices that have them.
10132 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10133 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
10135 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
10136 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10137 ((u64) tpr->rx_jmb_mapping >> 32));
10138 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10139 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
10140 val = TG3_RX_JMB_RING_SIZE(tp) <<
10141 BDINFO_FLAGS_MAXLEN_SHIFT;
10142 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10143 val | BDINFO_FLAGS_USE_EXT_RECV);
10144 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
10145 tg3_flag(tp, 57765_CLASS) ||
10146 tg3_asic_rev(tp) == ASIC_REV_5762)
10147 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10148 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
10150 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10151 BDINFO_FLAGS_DISABLED);
10154 if (tg3_flag(tp, 57765_PLUS)) {
10155 val = TG3_RX_STD_RING_SIZE(tp);
10156 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10157 val |= (TG3_RX_STD_DMA_SZ << 2);
10159 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
10161 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
10163 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10165 tpr->rx_std_prod_idx = tp->rx_pending;
10166 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
10168 tpr->rx_jmb_prod_idx =
10169 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
10170 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
10172 tg3_rings_reset(tp);
10174 /* Initialize MAC address and backoff seed. */
10175 __tg3_set_mac_addr(tp, false);
10177 /* MTU + ethernet header + FCS + optional VLAN tag */
10178 tw32(MAC_RX_MTU_SIZE,
10179 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
10181 /* The slot time is changed by tg3_setup_phy if we
10182 * run at gigabit with half duplex.
10184 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10185 (6 << TX_LENGTHS_IPG_SHIFT) |
10186 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10188 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10189 tg3_asic_rev(tp) == ASIC_REV_5762)
10190 val |= tr32(MAC_TX_LENGTHS) &
10191 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10192 TX_LENGTHS_CNT_DWN_VAL_MSK);
10194 tw32(MAC_TX_LENGTHS, val);
10196 /* Receive rules. */
10197 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10198 tw32(RCVLPC_CONFIG, 0x0181);
10200 /* Calculate RDMAC_MODE setting early, we need it to determine
10201 * the RCVLPC_STATE_ENABLE mask.
10203 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10204 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10205 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10206 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10207 RDMAC_MODE_LNGREAD_ENAB);
10209 if (tg3_asic_rev(tp) == ASIC_REV_5717)
10210 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10212 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10213 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10214 tg3_asic_rev(tp) == ASIC_REV_57780)
10215 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10216 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10217 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10219 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10220 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10221 if (tg3_flag(tp, TSO_CAPABLE) &&
10222 tg3_asic_rev(tp) == ASIC_REV_5705) {
10223 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10224 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10225 !tg3_flag(tp, IS_5788)) {
10226 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10230 if (tg3_flag(tp, PCI_EXPRESS))
10231 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10233 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10235 if (tp->dev->mtu <= ETH_DATA_LEN) {
10236 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10237 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10241 if (tg3_flag(tp, HW_TSO_1) ||
10242 tg3_flag(tp, HW_TSO_2) ||
10243 tg3_flag(tp, HW_TSO_3))
10244 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10246 if (tg3_flag(tp, 57765_PLUS) ||
10247 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10248 tg3_asic_rev(tp) == ASIC_REV_57780)
10249 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
10251 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10252 tg3_asic_rev(tp) == ASIC_REV_5762)
10253 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10255 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10256 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10257 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10258 tg3_asic_rev(tp) == ASIC_REV_57780 ||
10259 tg3_flag(tp, 57765_PLUS)) {
10262 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10263 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10265 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10267 val = tr32(tgtreg);
10268 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10269 tg3_asic_rev(tp) == ASIC_REV_5762) {
10270 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10271 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10272 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10273 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10274 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10275 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
10277 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10280 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10281 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10282 tg3_asic_rev(tp) == ASIC_REV_5762) {
10285 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10286 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10288 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10290 val = tr32(tgtreg);
10292 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10293 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10296 /* Receive/send statistics. */
10297 if (tg3_flag(tp, 5750_PLUS)) {
10298 val = tr32(RCVLPC_STATS_ENABLE);
10299 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10300 tw32(RCVLPC_STATS_ENABLE, val);
10301 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
10302 tg3_flag(tp, TSO_CAPABLE)) {
10303 val = tr32(RCVLPC_STATS_ENABLE);
10304 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10305 tw32(RCVLPC_STATS_ENABLE, val);
10307 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10309 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10310 tw32(SNDDATAI_STATSENAB, 0xffffff);
10311 tw32(SNDDATAI_STATSCTRL,
10312 (SNDDATAI_SCTRL_ENABLE |
10313 SNDDATAI_SCTRL_FASTUPD));
10315 /* Setup host coalescing engine. */
10316 tw32(HOSTCC_MODE, 0);
10317 for (i = 0; i < 2000; i++) {
10318 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10323 __tg3_set_coalesce(tp, &tp->coal);
10325 if (!tg3_flag(tp, 5705_PLUS)) {
10326 /* Status/statistics block address. See tg3_timer,
10327 * the tg3_periodic_fetch_stats call there, and
10328 * tg3_get_stats to see how this works for 5705/5750 chips.
10330 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10331 ((u64) tp->stats_mapping >> 32));
10332 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10333 ((u64) tp->stats_mapping & 0xffffffff));
10334 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10336 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10338 /* Clear statistics and status block memory areas */
10339 for (i = NIC_SRAM_STATS_BLK;
10340 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10341 i += sizeof(u32)) {
10342 tg3_write_mem(tp, i, 0);
10347 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10349 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10350 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10351 if (!tg3_flag(tp, 5705_PLUS))
10352 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10354 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10355 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10356 /* reset to prevent losing 1st rx packet intermittently */
10357 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10361 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10362 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10363 MAC_MODE_FHDE_ENABLE;
10364 if (tg3_flag(tp, ENABLE_APE))
10365 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10366 if (!tg3_flag(tp, 5705_PLUS) &&
10367 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10368 tg3_asic_rev(tp) != ASIC_REV_5700)
10369 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10370 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10373 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10374 * If TG3_FLAG_IS_NIC is zero, we should read the
10375 * register to preserve the GPIO settings for LOMs. The GPIOs,
10376 * whether used as inputs or outputs, are set by boot code after
10379 if (!tg3_flag(tp, IS_NIC)) {
10382 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10383 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10384 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
10386 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10387 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10388 GRC_LCLCTRL_GPIO_OUTPUT3;
10390 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10391 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10393 tp->grc_local_ctrl &= ~gpio_mask;
10394 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10396 /* GPIO1 must be driven high for eeprom write protect */
10397 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10398 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10399 GRC_LCLCTRL_GPIO_OUTPUT1);
10401 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10404 if (tg3_flag(tp, USING_MSIX)) {
10405 val = tr32(MSGINT_MODE);
10406 val |= MSGINT_MODE_ENABLE;
10407 if (tp->irq_cnt > 1)
10408 val |= MSGINT_MODE_MULTIVEC_EN;
10409 if (!tg3_flag(tp, 1SHOT_MSI))
10410 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
10411 tw32(MSGINT_MODE, val);
10414 if (!tg3_flag(tp, 5705_PLUS)) {
10415 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10419 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10420 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10421 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10422 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10423 WDMAC_MODE_LNGREAD_ENAB);
10425 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10426 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10427 if (tg3_flag(tp, TSO_CAPABLE) &&
10428 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10429 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10431 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10432 !tg3_flag(tp, IS_5788)) {
10433 val |= WDMAC_MODE_RX_ACCEL;
10437 /* Enable host coalescing bug fix */
10438 if (tg3_flag(tp, 5755_PLUS))
10439 val |= WDMAC_MODE_STATUS_TAG_FIX;
10441 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10442 val |= WDMAC_MODE_BURST_ALL_DATA;
10444 tw32_f(WDMAC_MODE, val);
10447 if (tg3_flag(tp, PCIX_MODE)) {
10450 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10452 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10453 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10454 pcix_cmd |= PCI_X_CMD_READ_2K;
10455 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10456 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10457 pcix_cmd |= PCI_X_CMD_READ_2K;
10459 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10463 tw32_f(RDMAC_MODE, rdmac_mode);
10466 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10467 tg3_asic_rev(tp) == ASIC_REV_5720) {
10468 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10469 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10472 if (i < TG3_NUM_RDMA_CHANNELS) {
10473 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10474 val |= tg3_lso_rd_dma_workaround_bit(tp);
10475 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10476 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
10480 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10481 if (!tg3_flag(tp, 5705_PLUS))
10482 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10484 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10485 tw32(SNDDATAC_MODE,
10486 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10488 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10490 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10491 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10492 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
10493 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10494 val |= RCVDBDI_MODE_LRG_RING_SZ;
10495 tw32(RCVDBDI_MODE, val);
10496 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10497 if (tg3_flag(tp, HW_TSO_1) ||
10498 tg3_flag(tp, HW_TSO_2) ||
10499 tg3_flag(tp, HW_TSO_3))
10500 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10501 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
10502 if (tg3_flag(tp, ENABLE_TSS))
10503 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10504 tw32(SNDBDI_MODE, val);
10505 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10507 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10508 err = tg3_load_5701_a0_firmware_fix(tp);
10513 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10514 /* Ignore any errors for the firmware download. If download
10515 * fails, the device will operate with EEE disabled
10517 tg3_load_57766_firmware(tp);
10520 if (tg3_flag(tp, TSO_CAPABLE)) {
10521 err = tg3_load_tso_firmware(tp);
10526 tp->tx_mode = TX_MODE_ENABLE;
10528 if (tg3_flag(tp, 5755_PLUS) ||
10529 tg3_asic_rev(tp) == ASIC_REV_5906)
10530 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10532 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10533 tg3_asic_rev(tp) == ASIC_REV_5762) {
10534 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10535 tp->tx_mode &= ~val;
10536 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10539 tw32_f(MAC_TX_MODE, tp->tx_mode);
10542 if (tg3_flag(tp, ENABLE_RSS)) {
10543 tg3_rss_write_indir_tbl(tp);
10545 /* Setup the "secret" hash key. */
10546 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10547 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10548 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10549 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10550 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10551 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10552 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10553 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10554 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10555 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10558 tp->rx_mode = RX_MODE_ENABLE;
10559 if (tg3_flag(tp, 5755_PLUS))
10560 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10562 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10563 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10565 if (tg3_flag(tp, ENABLE_RSS))
10566 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10567 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10568 RX_MODE_RSS_IPV6_HASH_EN |
10569 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10570 RX_MODE_RSS_IPV4_HASH_EN |
10571 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10573 tw32_f(MAC_RX_MODE, tp->rx_mode);
10576 tw32(MAC_LED_CTRL, tp->led_ctrl);
10578 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10579 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10580 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10583 tw32_f(MAC_RX_MODE, tp->rx_mode);
10586 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10587 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10588 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10589 /* Set drive transmission level to 1.2V */
10590 /* only if the signal pre-emphasis bit is not set */
10591 val = tr32(MAC_SERDES_CFG);
10594 tw32(MAC_SERDES_CFG, val);
10596 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10597 tw32(MAC_SERDES_CFG, 0x616000);
10600 /* Prevent chip from dropping frames when flow control
10603 if (tg3_flag(tp, 57765_CLASS))
10607 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
10609 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10610 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10611 /* Use hardware link auto-negotiation */
10612 tg3_flag_set(tp, HW_AUTONEG);
10615 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10616 tg3_asic_rev(tp) == ASIC_REV_5714) {
10619 tmp = tr32(SERDES_RX_CTRL);
10620 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10621 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10622 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10623 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10626 if (!tg3_flag(tp, USE_PHYLIB)) {
10627 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10628 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10630 err = tg3_setup_phy(tp, false);
10634 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10635 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10638 /* Clear CRC stats. */
10639 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10640 tg3_writephy(tp, MII_TG3_TEST1,
10641 tmp | MII_TG3_TEST1_CRC_EN);
10642 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10647 __tg3_set_rx_mode(tp->dev);
10649 /* Initialize receive rules. */
10650 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10651 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10652 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10653 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10655 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10659 if (tg3_flag(tp, ENABLE_ASF))
10663 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10665 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10667 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10669 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10671 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10673 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10675 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10677 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10679 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10681 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10683 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10685 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10687 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10689 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10697 if (tg3_flag(tp, ENABLE_APE))
10698 /* Write our heartbeat update interval to APE. */
10699 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10700 APE_HOST_HEARTBEAT_INT_DISABLE);
10702 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10707 /* Called at device open time to get the chip ready for
10708 * packet processing. Invoked with tp->lock held.
10710 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
10712 /* Chip may have been just powered on. If so, the boot code may still
10713 * be running initialization. Wait for it to finish to avoid races in
10714 * accessing the hardware.
10716 tg3_enable_register_access(tp);
10719 tg3_switch_clocks(tp);
10721 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10723 return tg3_reset_hw(tp, reset_phy);
10726 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10730 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10731 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10733 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10736 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10737 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10738 memset(ocir, 0, TG3_OCIR_LEN);
10742 /* sysfs attributes for hwmon */
10743 static ssize_t tg3_show_temp(struct device *dev,
10744 struct device_attribute *devattr, char *buf)
10746 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10747 struct tg3 *tp = dev_get_drvdata(dev);
10750 spin_lock_bh(&tp->lock);
10751 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10752 sizeof(temperature));
10753 spin_unlock_bh(&tp->lock);
10754 return sprintf(buf, "%u\n", temperature);
10758 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10759 TG3_TEMP_SENSOR_OFFSET);
10760 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10761 TG3_TEMP_CAUTION_OFFSET);
10762 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10763 TG3_TEMP_MAX_OFFSET);
10765 static struct attribute *tg3_attrs[] = {
10766 &sensor_dev_attr_temp1_input.dev_attr.attr,
10767 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10768 &sensor_dev_attr_temp1_max.dev_attr.attr,
10771 ATTRIBUTE_GROUPS(tg3);
10773 static void tg3_hwmon_close(struct tg3 *tp)
10775 if (tp->hwmon_dev) {
10776 hwmon_device_unregister(tp->hwmon_dev);
10777 tp->hwmon_dev = NULL;
10781 static void tg3_hwmon_open(struct tg3 *tp)
10785 struct pci_dev *pdev = tp->pdev;
10786 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10788 tg3_sd_scan_scratchpad(tp, ocirs);
10790 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10791 if (!ocirs[i].src_data_length)
10794 size += ocirs[i].src_hdr_length;
10795 size += ocirs[i].src_data_length;
10801 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10803 if (IS_ERR(tp->hwmon_dev)) {
10804 tp->hwmon_dev = NULL;
10805 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10810 #define TG3_STAT_ADD32(PSTAT, REG) \
10811 do { u32 __val = tr32(REG); \
10812 (PSTAT)->low += __val; \
10813 if ((PSTAT)->low < __val) \
10814 (PSTAT)->high += 1; \
10817 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10819 struct tg3_hw_stats *sp = tp->hw_stats;
10824 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10825 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10826 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10827 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10828 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10829 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10830 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10831 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10832 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10833 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10834 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10835 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10836 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
10837 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
10838 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10839 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10842 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10843 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10844 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10845 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
10848 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10849 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10850 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10851 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10852 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10853 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10854 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10855 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10856 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10857 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10858 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10859 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10860 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10861 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
10863 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
10864 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10865 tg3_asic_rev(tp) != ASIC_REV_5762 &&
10866 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10867 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10868 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10870 u32 val = tr32(HOSTCC_FLOW_ATTN);
10871 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10873 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10874 sp->rx_discards.low += val;
10875 if (sp->rx_discards.low < val)
10876 sp->rx_discards.high += 1;
10878 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10880 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
10883 static void tg3_chk_missed_msi(struct tg3 *tp)
10887 for (i = 0; i < tp->irq_cnt; i++) {
10888 struct tg3_napi *tnapi = &tp->napi[i];
10890 if (tg3_has_work(tnapi)) {
10891 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10892 tnapi->last_tx_cons == tnapi->tx_cons) {
10893 if (tnapi->chk_msi_cnt < 1) {
10894 tnapi->chk_msi_cnt++;
10900 tnapi->chk_msi_cnt = 0;
10901 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10902 tnapi->last_tx_cons = tnapi->tx_cons;
10906 static void tg3_timer(unsigned long __opaque)
10908 struct tg3 *tp = (struct tg3 *) __opaque;
10910 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
10911 goto restart_timer;
10913 spin_lock(&tp->lock);
10915 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10916 tg3_flag(tp, 57765_CLASS))
10917 tg3_chk_missed_msi(tp);
10919 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10920 /* BCM4785: Flush posted writes from GbE to host memory. */
10924 if (!tg3_flag(tp, TAGGED_STATUS)) {
10925 /* All of this garbage is because when using non-tagged
10926 * IRQ status the mailbox/status_block protocol the chip
10927 * uses with the cpu is race prone.
10929 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
10930 tw32(GRC_LOCAL_CTRL,
10931 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10933 tw32(HOSTCC_MODE, tp->coalesce_mode |
10934 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
10937 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10938 spin_unlock(&tp->lock);
10939 tg3_reset_task_schedule(tp);
10940 goto restart_timer;
10944 /* This part only runs once per second. */
10945 if (!--tp->timer_counter) {
10946 if (tg3_flag(tp, 5705_PLUS))
10947 tg3_periodic_fetch_stats(tp);
10949 if (tp->setlpicnt && !--tp->setlpicnt)
10950 tg3_phy_eee_enable(tp);
10952 if (tg3_flag(tp, USE_LINKCHG_REG)) {
10956 mac_stat = tr32(MAC_STATUS);
10959 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
10960 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10962 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10966 tg3_setup_phy(tp, false);
10967 } else if (tg3_flag(tp, POLL_SERDES)) {
10968 u32 mac_stat = tr32(MAC_STATUS);
10969 int need_setup = 0;
10972 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10975 if (!tp->link_up &&
10976 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10977 MAC_STATUS_SIGNAL_DET))) {
10981 if (!tp->serdes_counter) {
10984 ~MAC_MODE_PORT_MODE_MASK));
10986 tw32_f(MAC_MODE, tp->mac_mode);
10989 tg3_setup_phy(tp, false);
10991 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10992 tg3_flag(tp, 5780_CLASS)) {
10993 tg3_serdes_parallel_detect(tp);
10994 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
10995 u32 cpmu = tr32(TG3_CPMU_STATUS);
10996 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
10997 TG3_CPMU_STATUS_LINK_MASK);
10999 if (link_up != tp->link_up)
11000 tg3_setup_phy(tp, false);
11003 tp->timer_counter = tp->timer_multiplier;
11006 /* Heartbeat is only sent once every 2 seconds.
11008 * The heartbeat is to tell the ASF firmware that the host
11009 * driver is still alive. In the event that the OS crashes,
11010 * ASF needs to reset the hardware to free up the FIFO space
11011 * that may be filled with rx packets destined for the host.
11012 * If the FIFO is full, ASF will no longer function properly.
11014 * Unintended resets have been reported on real time kernels
11015 * where the timer doesn't run on time. Netpoll will also have
11018 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
11019 * to check the ring condition when the heartbeat is expiring
11020 * before doing the reset. This will prevent most unintended
11023 if (!--tp->asf_counter) {
11024 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
11025 tg3_wait_for_event_ack(tp);
11027 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
11028 FWCMD_NICDRV_ALIVE3);
11029 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
11030 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11031 TG3_FW_UPDATE_TIMEOUT_SEC);
11033 tg3_generate_fw_event(tp);
11035 tp->asf_counter = tp->asf_multiplier;
11038 spin_unlock(&tp->lock);
11041 tp->timer.expires = jiffies + tp->timer_offset;
11042 add_timer(&tp->timer);
11045 static void tg3_timer_init(struct tg3 *tp)
11047 if (tg3_flag(tp, TAGGED_STATUS) &&
11048 tg3_asic_rev(tp) != ASIC_REV_5717 &&
11049 !tg3_flag(tp, 57765_CLASS))
11050 tp->timer_offset = HZ;
11052 tp->timer_offset = HZ / 10;
11054 BUG_ON(tp->timer_offset > HZ);
11056 tp->timer_multiplier = (HZ / tp->timer_offset);
11057 tp->asf_multiplier = (HZ / tp->timer_offset) *
11058 TG3_FW_UPDATE_FREQ_SEC;
11060 init_timer(&tp->timer);
11061 tp->timer.data = (unsigned long) tp;
11062 tp->timer.function = tg3_timer;
11065 static void tg3_timer_start(struct tg3 *tp)
11067 tp->asf_counter = tp->asf_multiplier;
11068 tp->timer_counter = tp->timer_multiplier;
11070 tp->timer.expires = jiffies + tp->timer_offset;
11071 add_timer(&tp->timer);
11074 static void tg3_timer_stop(struct tg3 *tp)
11076 del_timer_sync(&tp->timer);
11079 /* Restart hardware after configuration changes, self-test, etc.
11080 * Invoked with tp->lock held.
11082 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
11083 __releases(tp->lock)
11084 __acquires(tp->lock)
11088 err = tg3_init_hw(tp, reset_phy);
11090 netdev_err(tp->dev,
11091 "Failed to re-initialize device, aborting\n");
11092 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11093 tg3_full_unlock(tp);
11094 tg3_timer_stop(tp);
11096 tg3_napi_enable(tp);
11097 dev_close(tp->dev);
11098 tg3_full_lock(tp, 0);
11103 static void tg3_reset_task(struct work_struct *work)
11105 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11108 tg3_full_lock(tp, 0);
11110 if (!netif_running(tp->dev)) {
11111 tg3_flag_clear(tp, RESET_TASK_PENDING);
11112 tg3_full_unlock(tp);
11116 tg3_full_unlock(tp);
11120 tg3_netif_stop(tp);
11122 tg3_full_lock(tp, 1);
11124 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11125 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11126 tp->write32_rx_mbox = tg3_write_flush_reg32;
11127 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11128 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11131 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
11132 err = tg3_init_hw(tp, true);
11136 tg3_netif_start(tp);
11139 tg3_full_unlock(tp);
11144 tg3_flag_clear(tp, RESET_TASK_PENDING);
11147 static int tg3_request_irq(struct tg3 *tp, int irq_num)
11150 unsigned long flags;
11152 struct tg3_napi *tnapi = &tp->napi[irq_num];
11154 if (tp->irq_cnt == 1)
11155 name = tp->dev->name;
11157 name = &tnapi->irq_lbl[0];
11158 if (tnapi->tx_buffers && tnapi->rx_rcb)
11159 snprintf(name, IFNAMSIZ,
11160 "%s-txrx-%d", tp->dev->name, irq_num);
11161 else if (tnapi->tx_buffers)
11162 snprintf(name, IFNAMSIZ,
11163 "%s-tx-%d", tp->dev->name, irq_num);
11164 else if (tnapi->rx_rcb)
11165 snprintf(name, IFNAMSIZ,
11166 "%s-rx-%d", tp->dev->name, irq_num);
11168 snprintf(name, IFNAMSIZ,
11169 "%s-%d", tp->dev->name, irq_num);
11170 name[IFNAMSIZ-1] = 0;
11173 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11175 if (tg3_flag(tp, 1SHOT_MSI))
11176 fn = tg3_msi_1shot;
11179 fn = tg3_interrupt;
11180 if (tg3_flag(tp, TAGGED_STATUS))
11181 fn = tg3_interrupt_tagged;
11182 flags = IRQF_SHARED;
11185 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
11188 static int tg3_test_interrupt(struct tg3 *tp)
11190 struct tg3_napi *tnapi = &tp->napi[0];
11191 struct net_device *dev = tp->dev;
11192 int err, i, intr_ok = 0;
11195 if (!netif_running(dev))
11198 tg3_disable_ints(tp);
11200 free_irq(tnapi->irq_vec, tnapi);
11203 * Turn off MSI one shot mode. Otherwise this test has no
11204 * observable way to know whether the interrupt was delivered.
11206 if (tg3_flag(tp, 57765_PLUS)) {
11207 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11208 tw32(MSGINT_MODE, val);
11211 err = request_irq(tnapi->irq_vec, tg3_test_isr,
11212 IRQF_SHARED, dev->name, tnapi);
11216 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
11217 tg3_enable_ints(tp);
11219 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11222 for (i = 0; i < 5; i++) {
11223 u32 int_mbox, misc_host_ctrl;
11225 int_mbox = tr32_mailbox(tnapi->int_mbox);
11226 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11228 if ((int_mbox != 0) ||
11229 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11234 if (tg3_flag(tp, 57765_PLUS) &&
11235 tnapi->hw_status->status_tag != tnapi->last_tag)
11236 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11241 tg3_disable_ints(tp);
11243 free_irq(tnapi->irq_vec, tnapi);
11245 err = tg3_request_irq(tp, 0);
11251 /* Reenable MSI one shot mode. */
11252 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
11253 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11254 tw32(MSGINT_MODE, val);
11262 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11263 * successfully restored
11265 static int tg3_test_msi(struct tg3 *tp)
11270 if (!tg3_flag(tp, USING_MSI))
11273 /* Turn off SERR reporting in case MSI terminates with Master
11276 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11277 pci_write_config_word(tp->pdev, PCI_COMMAND,
11278 pci_cmd & ~PCI_COMMAND_SERR);
11280 err = tg3_test_interrupt(tp);
11282 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11287 /* other failures */
11291 /* MSI test failed, go back to INTx mode */
11292 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11293 "to INTx mode. Please report this failure to the PCI "
11294 "maintainer and include system chipset information\n");
11296 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11298 pci_disable_msi(tp->pdev);
11300 tg3_flag_clear(tp, USING_MSI);
11301 tp->napi[0].irq_vec = tp->pdev->irq;
11303 err = tg3_request_irq(tp, 0);
11307 /* Need to reset the chip because the MSI cycle may have terminated
11308 * with Master Abort.
11310 tg3_full_lock(tp, 1);
11312 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11313 err = tg3_init_hw(tp, true);
11315 tg3_full_unlock(tp);
11318 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11323 static int tg3_request_firmware(struct tg3 *tp)
11325 const struct tg3_firmware_hdr *fw_hdr;
11327 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
11328 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11333 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
11335 /* Firmware blob starts with version numbers, followed by
11336 * start address and _full_ length including BSS sections
11337 * (which must be longer than the actual data, of course
11340 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11341 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
11342 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11343 tp->fw_len, tp->fw_needed);
11344 release_firmware(tp->fw);
11349 /* We no longer need firmware; we have it. */
11350 tp->fw_needed = NULL;
11354 static u32 tg3_irq_count(struct tg3 *tp)
11356 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
11359 /* We want as many rx rings enabled as there are cpus.
11360 * In multiqueue MSI-X mode, the first MSI-X vector
11361 * only deals with link interrupts, etc, so we add
11362 * one to the number of vectors we are requesting.
11364 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11370 static bool tg3_enable_msix(struct tg3 *tp)
11373 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
11375 tp->txq_cnt = tp->txq_req;
11376 tp->rxq_cnt = tp->rxq_req;
11378 tp->rxq_cnt = netif_get_num_default_rss_queues();
11379 if (tp->rxq_cnt > tp->rxq_max)
11380 tp->rxq_cnt = tp->rxq_max;
11382 /* Disable multiple TX rings by default. Simple round-robin hardware
11383 * scheduling of the TX rings can cause starvation of rings with
11384 * small packets when other rings have TSO or jumbo packets.
11389 tp->irq_cnt = tg3_irq_count(tp);
11391 for (i = 0; i < tp->irq_max; i++) {
11392 msix_ent[i].entry = i;
11393 msix_ent[i].vector = 0;
11396 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
11399 } else if (rc < tp->irq_cnt) {
11400 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11403 tp->rxq_cnt = max(rc - 1, 1);
11405 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11408 for (i = 0; i < tp->irq_max; i++)
11409 tp->napi[i].irq_vec = msix_ent[i].vector;
11411 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11412 pci_disable_msix(tp->pdev);
11416 if (tp->irq_cnt == 1)
11419 tg3_flag_set(tp, ENABLE_RSS);
11421 if (tp->txq_cnt > 1)
11422 tg3_flag_set(tp, ENABLE_TSS);
11424 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11429 static void tg3_ints_init(struct tg3 *tp)
11431 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11432 !tg3_flag(tp, TAGGED_STATUS)) {
11433 /* All MSI supporting chips should support tagged
11434 * status. Assert that this is the case.
11436 netdev_warn(tp->dev,
11437 "MSI without TAGGED_STATUS? Not using MSI\n");
11441 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11442 tg3_flag_set(tp, USING_MSIX);
11443 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11444 tg3_flag_set(tp, USING_MSI);
11446 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11447 u32 msi_mode = tr32(MSGINT_MODE);
11448 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11449 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
11450 if (!tg3_flag(tp, 1SHOT_MSI))
11451 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
11452 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11455 if (!tg3_flag(tp, USING_MSIX)) {
11457 tp->napi[0].irq_vec = tp->pdev->irq;
11460 if (tp->irq_cnt == 1) {
11463 netif_set_real_num_tx_queues(tp->dev, 1);
11464 netif_set_real_num_rx_queues(tp->dev, 1);
11468 static void tg3_ints_fini(struct tg3 *tp)
11470 if (tg3_flag(tp, USING_MSIX))
11471 pci_disable_msix(tp->pdev);
11472 else if (tg3_flag(tp, USING_MSI))
11473 pci_disable_msi(tp->pdev);
11474 tg3_flag_clear(tp, USING_MSI);
11475 tg3_flag_clear(tp, USING_MSIX);
11476 tg3_flag_clear(tp, ENABLE_RSS);
11477 tg3_flag_clear(tp, ENABLE_TSS);
11480 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11483 struct net_device *dev = tp->dev;
11487 * Setup interrupts first so we know how
11488 * many NAPI resources to allocate
11492 tg3_rss_check_indir_tbl(tp);
11494 /* The placement of this call is tied
11495 * to the setup and use of Host TX descriptors.
11497 err = tg3_alloc_consistent(tp);
11499 goto out_ints_fini;
11503 tg3_napi_enable(tp);
11505 for (i = 0; i < tp->irq_cnt; i++) {
11506 struct tg3_napi *tnapi = &tp->napi[i];
11507 err = tg3_request_irq(tp, i);
11509 for (i--; i >= 0; i--) {
11510 tnapi = &tp->napi[i];
11511 free_irq(tnapi->irq_vec, tnapi);
11513 goto out_napi_fini;
11517 tg3_full_lock(tp, 0);
11520 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11522 err = tg3_init_hw(tp, reset_phy);
11524 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11525 tg3_free_rings(tp);
11528 tg3_full_unlock(tp);
11533 if (test_irq && tg3_flag(tp, USING_MSI)) {
11534 err = tg3_test_msi(tp);
11537 tg3_full_lock(tp, 0);
11538 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11539 tg3_free_rings(tp);
11540 tg3_full_unlock(tp);
11542 goto out_napi_fini;
11545 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11546 u32 val = tr32(PCIE_TRANSACTION_CFG);
11548 tw32(PCIE_TRANSACTION_CFG,
11549 val | PCIE_TRANS_CFG_1SHOT_MSI);
11555 tg3_hwmon_open(tp);
11557 tg3_full_lock(tp, 0);
11559 tg3_timer_start(tp);
11560 tg3_flag_set(tp, INIT_COMPLETE);
11561 tg3_enable_ints(tp);
11566 tg3_ptp_resume(tp);
11569 tg3_full_unlock(tp);
11571 netif_tx_start_all_queues(dev);
11574 * Reset loopback feature if it was turned on while the device was down
11575 * make sure that it's installed properly now.
11577 if (dev->features & NETIF_F_LOOPBACK)
11578 tg3_set_loopback(dev, dev->features);
11583 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11584 struct tg3_napi *tnapi = &tp->napi[i];
11585 free_irq(tnapi->irq_vec, tnapi);
11589 tg3_napi_disable(tp);
11591 tg3_free_consistent(tp);
11599 static void tg3_stop(struct tg3 *tp)
11603 tg3_reset_task_cancel(tp);
11604 tg3_netif_stop(tp);
11606 tg3_timer_stop(tp);
11608 tg3_hwmon_close(tp);
11612 tg3_full_lock(tp, 1);
11614 tg3_disable_ints(tp);
11616 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11617 tg3_free_rings(tp);
11618 tg3_flag_clear(tp, INIT_COMPLETE);
11620 tg3_full_unlock(tp);
11622 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11623 struct tg3_napi *tnapi = &tp->napi[i];
11624 free_irq(tnapi->irq_vec, tnapi);
11631 tg3_free_consistent(tp);
11634 static int tg3_open(struct net_device *dev)
11636 struct tg3 *tp = netdev_priv(dev);
11639 if (tp->pcierr_recovery) {
11640 netdev_err(dev, "Failed to open device. PCI error recovery "
11645 if (tp->fw_needed) {
11646 err = tg3_request_firmware(tp);
11647 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11649 netdev_warn(tp->dev, "EEE capability disabled\n");
11650 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11651 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11652 netdev_warn(tp->dev, "EEE capability restored\n");
11653 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11655 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11659 netdev_warn(tp->dev, "TSO capability disabled\n");
11660 tg3_flag_clear(tp, TSO_CAPABLE);
11661 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11662 netdev_notice(tp->dev, "TSO capability restored\n");
11663 tg3_flag_set(tp, TSO_CAPABLE);
11667 tg3_carrier_off(tp);
11669 err = tg3_power_up(tp);
11673 tg3_full_lock(tp, 0);
11675 tg3_disable_ints(tp);
11676 tg3_flag_clear(tp, INIT_COMPLETE);
11678 tg3_full_unlock(tp);
11680 err = tg3_start(tp,
11681 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11684 tg3_frob_aux_power(tp, false);
11685 pci_set_power_state(tp->pdev, PCI_D3hot);
11688 if (tg3_flag(tp, PTP_CAPABLE)) {
11689 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11691 if (IS_ERR(tp->ptp_clock))
11692 tp->ptp_clock = NULL;
11698 static int tg3_close(struct net_device *dev)
11700 struct tg3 *tp = netdev_priv(dev);
11702 if (tp->pcierr_recovery) {
11703 netdev_err(dev, "Failed to close device. PCI error recovery "
11712 /* Clear stats across close / open calls */
11713 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11714 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
11716 if (pci_device_is_present(tp->pdev)) {
11717 tg3_power_down_prepare(tp);
11719 tg3_carrier_off(tp);
11724 static inline u64 get_stat64(tg3_stat64_t *val)
11726 return ((u64)val->high << 32) | ((u64)val->low);
11729 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11731 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11733 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11734 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11735 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11738 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11739 tg3_writephy(tp, MII_TG3_TEST1,
11740 val | MII_TG3_TEST1_CRC_EN);
11741 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11745 tp->phy_crc_errors += val;
11747 return tp->phy_crc_errors;
11750 return get_stat64(&hw_stats->rx_fcs_errors);
11753 #define ESTAT_ADD(member) \
11754 estats->member = old_estats->member + \
11755 get_stat64(&hw_stats->member)
11757 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11759 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11760 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11762 ESTAT_ADD(rx_octets);
11763 ESTAT_ADD(rx_fragments);
11764 ESTAT_ADD(rx_ucast_packets);
11765 ESTAT_ADD(rx_mcast_packets);
11766 ESTAT_ADD(rx_bcast_packets);
11767 ESTAT_ADD(rx_fcs_errors);
11768 ESTAT_ADD(rx_align_errors);
11769 ESTAT_ADD(rx_xon_pause_rcvd);
11770 ESTAT_ADD(rx_xoff_pause_rcvd);
11771 ESTAT_ADD(rx_mac_ctrl_rcvd);
11772 ESTAT_ADD(rx_xoff_entered);
11773 ESTAT_ADD(rx_frame_too_long_errors);
11774 ESTAT_ADD(rx_jabbers);
11775 ESTAT_ADD(rx_undersize_packets);
11776 ESTAT_ADD(rx_in_length_errors);
11777 ESTAT_ADD(rx_out_length_errors);
11778 ESTAT_ADD(rx_64_or_less_octet_packets);
11779 ESTAT_ADD(rx_65_to_127_octet_packets);
11780 ESTAT_ADD(rx_128_to_255_octet_packets);
11781 ESTAT_ADD(rx_256_to_511_octet_packets);
11782 ESTAT_ADD(rx_512_to_1023_octet_packets);
11783 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11784 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11785 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11786 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11787 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11789 ESTAT_ADD(tx_octets);
11790 ESTAT_ADD(tx_collisions);
11791 ESTAT_ADD(tx_xon_sent);
11792 ESTAT_ADD(tx_xoff_sent);
11793 ESTAT_ADD(tx_flow_control);
11794 ESTAT_ADD(tx_mac_errors);
11795 ESTAT_ADD(tx_single_collisions);
11796 ESTAT_ADD(tx_mult_collisions);
11797 ESTAT_ADD(tx_deferred);
11798 ESTAT_ADD(tx_excessive_collisions);
11799 ESTAT_ADD(tx_late_collisions);
11800 ESTAT_ADD(tx_collide_2times);
11801 ESTAT_ADD(tx_collide_3times);
11802 ESTAT_ADD(tx_collide_4times);
11803 ESTAT_ADD(tx_collide_5times);
11804 ESTAT_ADD(tx_collide_6times);
11805 ESTAT_ADD(tx_collide_7times);
11806 ESTAT_ADD(tx_collide_8times);
11807 ESTAT_ADD(tx_collide_9times);
11808 ESTAT_ADD(tx_collide_10times);
11809 ESTAT_ADD(tx_collide_11times);
11810 ESTAT_ADD(tx_collide_12times);
11811 ESTAT_ADD(tx_collide_13times);
11812 ESTAT_ADD(tx_collide_14times);
11813 ESTAT_ADD(tx_collide_15times);
11814 ESTAT_ADD(tx_ucast_packets);
11815 ESTAT_ADD(tx_mcast_packets);
11816 ESTAT_ADD(tx_bcast_packets);
11817 ESTAT_ADD(tx_carrier_sense_errors);
11818 ESTAT_ADD(tx_discards);
11819 ESTAT_ADD(tx_errors);
11821 ESTAT_ADD(dma_writeq_full);
11822 ESTAT_ADD(dma_write_prioq_full);
11823 ESTAT_ADD(rxbds_empty);
11824 ESTAT_ADD(rx_discards);
11825 ESTAT_ADD(rx_errors);
11826 ESTAT_ADD(rx_threshold_hit);
11828 ESTAT_ADD(dma_readq_full);
11829 ESTAT_ADD(dma_read_prioq_full);
11830 ESTAT_ADD(tx_comp_queue_full);
11832 ESTAT_ADD(ring_set_send_prod_index);
11833 ESTAT_ADD(ring_status_update);
11834 ESTAT_ADD(nic_irqs);
11835 ESTAT_ADD(nic_avoided_irqs);
11836 ESTAT_ADD(nic_tx_threshold_hit);
11838 ESTAT_ADD(mbuf_lwm_thresh_hit);
11841 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11843 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11844 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11846 stats->rx_packets = old_stats->rx_packets +
11847 get_stat64(&hw_stats->rx_ucast_packets) +
11848 get_stat64(&hw_stats->rx_mcast_packets) +
11849 get_stat64(&hw_stats->rx_bcast_packets);
11851 stats->tx_packets = old_stats->tx_packets +
11852 get_stat64(&hw_stats->tx_ucast_packets) +
11853 get_stat64(&hw_stats->tx_mcast_packets) +
11854 get_stat64(&hw_stats->tx_bcast_packets);
11856 stats->rx_bytes = old_stats->rx_bytes +
11857 get_stat64(&hw_stats->rx_octets);
11858 stats->tx_bytes = old_stats->tx_bytes +
11859 get_stat64(&hw_stats->tx_octets);
11861 stats->rx_errors = old_stats->rx_errors +
11862 get_stat64(&hw_stats->rx_errors);
11863 stats->tx_errors = old_stats->tx_errors +
11864 get_stat64(&hw_stats->tx_errors) +
11865 get_stat64(&hw_stats->tx_mac_errors) +
11866 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11867 get_stat64(&hw_stats->tx_discards);
11869 stats->multicast = old_stats->multicast +
11870 get_stat64(&hw_stats->rx_mcast_packets);
11871 stats->collisions = old_stats->collisions +
11872 get_stat64(&hw_stats->tx_collisions);
11874 stats->rx_length_errors = old_stats->rx_length_errors +
11875 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11876 get_stat64(&hw_stats->rx_undersize_packets);
11878 stats->rx_frame_errors = old_stats->rx_frame_errors +
11879 get_stat64(&hw_stats->rx_align_errors);
11880 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11881 get_stat64(&hw_stats->tx_discards);
11882 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11883 get_stat64(&hw_stats->tx_carrier_sense_errors);
11885 stats->rx_crc_errors = old_stats->rx_crc_errors +
11886 tg3_calc_crc_errors(tp);
11888 stats->rx_missed_errors = old_stats->rx_missed_errors +
11889 get_stat64(&hw_stats->rx_discards);
11891 stats->rx_dropped = tp->rx_dropped;
11892 stats->tx_dropped = tp->tx_dropped;
11895 static int tg3_get_regs_len(struct net_device *dev)
11897 return TG3_REG_BLK_SIZE;
11900 static void tg3_get_regs(struct net_device *dev,
11901 struct ethtool_regs *regs, void *_p)
11903 struct tg3 *tp = netdev_priv(dev);
11907 memset(_p, 0, TG3_REG_BLK_SIZE);
11909 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11912 tg3_full_lock(tp, 0);
11914 tg3_dump_legacy_regs(tp, (u32 *)_p);
11916 tg3_full_unlock(tp);
11919 static int tg3_get_eeprom_len(struct net_device *dev)
11921 struct tg3 *tp = netdev_priv(dev);
11923 return tp->nvram_size;
11926 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11928 struct tg3 *tp = netdev_priv(dev);
11929 int ret, cpmu_restore = 0;
11931 u32 i, offset, len, b_offset, b_count, cpmu_val = 0;
11934 if (tg3_flag(tp, NO_NVRAM))
11937 offset = eeprom->offset;
11941 eeprom->magic = TG3_EEPROM_MAGIC;
11943 /* Override clock, link aware and link idle modes */
11944 if (tg3_flag(tp, CPMU_PRESENT)) {
11945 cpmu_val = tr32(TG3_CPMU_CTRL);
11946 if (cpmu_val & (CPMU_CTRL_LINK_AWARE_MODE |
11947 CPMU_CTRL_LINK_IDLE_MODE)) {
11948 tw32(TG3_CPMU_CTRL, cpmu_val &
11949 ~(CPMU_CTRL_LINK_AWARE_MODE |
11950 CPMU_CTRL_LINK_IDLE_MODE));
11954 tg3_override_clk(tp);
11957 /* adjustments to start on required 4 byte boundary */
11958 b_offset = offset & 3;
11959 b_count = 4 - b_offset;
11960 if (b_count > len) {
11961 /* i.e. offset=1 len=2 */
11964 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
11967 memcpy(data, ((char *)&val) + b_offset, b_count);
11970 eeprom->len += b_count;
11973 /* read bytes up to the last 4 byte boundary */
11974 pd = &data[eeprom->len];
11975 for (i = 0; i < (len - (len & 3)); i += 4) {
11976 ret = tg3_nvram_read_be32(tp, offset + i, &val);
11983 memcpy(pd + i, &val, 4);
11984 if (need_resched()) {
11985 if (signal_pending(current)) {
11996 /* read last bytes not ending on 4 byte boundary */
11997 pd = &data[eeprom->len];
11999 b_offset = offset + len - b_count;
12000 ret = tg3_nvram_read_be32(tp, b_offset, &val);
12003 memcpy(pd, &val, b_count);
12004 eeprom->len += b_count;
12009 /* Restore clock, link aware and link idle modes */
12010 tg3_restore_clk(tp);
12012 tw32(TG3_CPMU_CTRL, cpmu_val);
12017 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
12019 struct tg3 *tp = netdev_priv(dev);
12021 u32 offset, len, b_offset, odd_len;
12025 if (tg3_flag(tp, NO_NVRAM) ||
12026 eeprom->magic != TG3_EEPROM_MAGIC)
12029 offset = eeprom->offset;
12032 if ((b_offset = (offset & 3))) {
12033 /* adjustments to start on required 4 byte boundary */
12034 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
12045 /* adjustments to end on required 4 byte boundary */
12047 len = (len + 3) & ~3;
12048 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
12054 if (b_offset || odd_len) {
12055 buf = kmalloc(len, GFP_KERNEL);
12059 memcpy(buf, &start, 4);
12061 memcpy(buf+len-4, &end, 4);
12062 memcpy(buf + b_offset, data, eeprom->len);
12065 ret = tg3_nvram_write_block(tp, offset, len, buf);
12073 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12075 struct tg3 *tp = netdev_priv(dev);
12077 if (tg3_flag(tp, USE_PHYLIB)) {
12078 struct phy_device *phydev;
12079 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12081 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12082 return phy_ethtool_gset(phydev, cmd);
12085 cmd->supported = (SUPPORTED_Autoneg);
12087 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12088 cmd->supported |= (SUPPORTED_1000baseT_Half |
12089 SUPPORTED_1000baseT_Full);
12091 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12092 cmd->supported |= (SUPPORTED_100baseT_Half |
12093 SUPPORTED_100baseT_Full |
12094 SUPPORTED_10baseT_Half |
12095 SUPPORTED_10baseT_Full |
12097 cmd->port = PORT_TP;
12099 cmd->supported |= SUPPORTED_FIBRE;
12100 cmd->port = PORT_FIBRE;
12103 cmd->advertising = tp->link_config.advertising;
12104 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12105 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12106 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12107 cmd->advertising |= ADVERTISED_Pause;
12109 cmd->advertising |= ADVERTISED_Pause |
12110 ADVERTISED_Asym_Pause;
12112 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12113 cmd->advertising |= ADVERTISED_Asym_Pause;
12116 if (netif_running(dev) && tp->link_up) {
12117 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
12118 cmd->duplex = tp->link_config.active_duplex;
12119 cmd->lp_advertising = tp->link_config.rmt_adv;
12120 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12121 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12122 cmd->eth_tp_mdix = ETH_TP_MDI_X;
12124 cmd->eth_tp_mdix = ETH_TP_MDI;
12127 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
12128 cmd->duplex = DUPLEX_UNKNOWN;
12129 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
12131 cmd->phy_address = tp->phy_addr;
12132 cmd->transceiver = XCVR_INTERNAL;
12133 cmd->autoneg = tp->link_config.autoneg;
12139 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12141 struct tg3 *tp = netdev_priv(dev);
12142 u32 speed = ethtool_cmd_speed(cmd);
12144 if (tg3_flag(tp, USE_PHYLIB)) {
12145 struct phy_device *phydev;
12146 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12148 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12149 return phy_ethtool_sset(phydev, cmd);
12152 if (cmd->autoneg != AUTONEG_ENABLE &&
12153 cmd->autoneg != AUTONEG_DISABLE)
12156 if (cmd->autoneg == AUTONEG_DISABLE &&
12157 cmd->duplex != DUPLEX_FULL &&
12158 cmd->duplex != DUPLEX_HALF)
12161 if (cmd->autoneg == AUTONEG_ENABLE) {
12162 u32 mask = ADVERTISED_Autoneg |
12164 ADVERTISED_Asym_Pause;
12166 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12167 mask |= ADVERTISED_1000baseT_Half |
12168 ADVERTISED_1000baseT_Full;
12170 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12171 mask |= ADVERTISED_100baseT_Half |
12172 ADVERTISED_100baseT_Full |
12173 ADVERTISED_10baseT_Half |
12174 ADVERTISED_10baseT_Full |
12177 mask |= ADVERTISED_FIBRE;
12179 if (cmd->advertising & ~mask)
12182 mask &= (ADVERTISED_1000baseT_Half |
12183 ADVERTISED_1000baseT_Full |
12184 ADVERTISED_100baseT_Half |
12185 ADVERTISED_100baseT_Full |
12186 ADVERTISED_10baseT_Half |
12187 ADVERTISED_10baseT_Full);
12189 cmd->advertising &= mask;
12191 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
12192 if (speed != SPEED_1000)
12195 if (cmd->duplex != DUPLEX_FULL)
12198 if (speed != SPEED_100 &&
12204 tg3_full_lock(tp, 0);
12206 tp->link_config.autoneg = cmd->autoneg;
12207 if (cmd->autoneg == AUTONEG_ENABLE) {
12208 tp->link_config.advertising = (cmd->advertising |
12209 ADVERTISED_Autoneg);
12210 tp->link_config.speed = SPEED_UNKNOWN;
12211 tp->link_config.duplex = DUPLEX_UNKNOWN;
12213 tp->link_config.advertising = 0;
12214 tp->link_config.speed = speed;
12215 tp->link_config.duplex = cmd->duplex;
12218 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12220 tg3_warn_mgmt_link_flap(tp);
12222 if (netif_running(dev))
12223 tg3_setup_phy(tp, true);
12225 tg3_full_unlock(tp);
12230 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12232 struct tg3 *tp = netdev_priv(dev);
12234 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12235 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12236 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12237 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
12240 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12242 struct tg3 *tp = netdev_priv(dev);
12244 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
12245 wol->supported = WAKE_MAGIC;
12247 wol->supported = 0;
12249 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
12250 wol->wolopts = WAKE_MAGIC;
12251 memset(&wol->sopass, 0, sizeof(wol->sopass));
12254 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12256 struct tg3 *tp = netdev_priv(dev);
12257 struct device *dp = &tp->pdev->dev;
12259 if (wol->wolopts & ~WAKE_MAGIC)
12261 if ((wol->wolopts & WAKE_MAGIC) &&
12262 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
12265 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12267 if (device_may_wakeup(dp))
12268 tg3_flag_set(tp, WOL_ENABLE);
12270 tg3_flag_clear(tp, WOL_ENABLE);
12275 static u32 tg3_get_msglevel(struct net_device *dev)
12277 struct tg3 *tp = netdev_priv(dev);
12278 return tp->msg_enable;
12281 static void tg3_set_msglevel(struct net_device *dev, u32 value)
12283 struct tg3 *tp = netdev_priv(dev);
12284 tp->msg_enable = value;
12287 static int tg3_nway_reset(struct net_device *dev)
12289 struct tg3 *tp = netdev_priv(dev);
12292 if (!netif_running(dev))
12295 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12298 tg3_warn_mgmt_link_flap(tp);
12300 if (tg3_flag(tp, USE_PHYLIB)) {
12301 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12303 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
12307 spin_lock_bh(&tp->lock);
12309 tg3_readphy(tp, MII_BMCR, &bmcr);
12310 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12311 ((bmcr & BMCR_ANENABLE) ||
12312 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
12313 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12317 spin_unlock_bh(&tp->lock);
12323 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12325 struct tg3 *tp = netdev_priv(dev);
12327 ering->rx_max_pending = tp->rx_std_ring_mask;
12328 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12329 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
12331 ering->rx_jumbo_max_pending = 0;
12333 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
12335 ering->rx_pending = tp->rx_pending;
12336 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12337 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12339 ering->rx_jumbo_pending = 0;
12341 ering->tx_pending = tp->napi[0].tx_pending;
12344 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12346 struct tg3 *tp = netdev_priv(dev);
12347 int i, irq_sync = 0, err = 0;
12349 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12350 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
12351 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12352 (ering->tx_pending <= MAX_SKB_FRAGS) ||
12353 (tg3_flag(tp, TSO_BUG) &&
12354 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
12357 if (netif_running(dev)) {
12359 tg3_netif_stop(tp);
12363 tg3_full_lock(tp, irq_sync);
12365 tp->rx_pending = ering->rx_pending;
12367 if (tg3_flag(tp, MAX_RXPEND_64) &&
12368 tp->rx_pending > 63)
12369 tp->rx_pending = 63;
12371 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12372 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
12374 for (i = 0; i < tp->irq_max; i++)
12375 tp->napi[i].tx_pending = ering->tx_pending;
12377 if (netif_running(dev)) {
12378 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12379 err = tg3_restart_hw(tp, false);
12381 tg3_netif_start(tp);
12384 tg3_full_unlock(tp);
12386 if (irq_sync && !err)
12392 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12394 struct tg3 *tp = netdev_priv(dev);
12396 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
12398 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
12399 epause->rx_pause = 1;
12401 epause->rx_pause = 0;
12403 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
12404 epause->tx_pause = 1;
12406 epause->tx_pause = 0;
12409 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12411 struct tg3 *tp = netdev_priv(dev);
12414 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12415 tg3_warn_mgmt_link_flap(tp);
12417 if (tg3_flag(tp, USE_PHYLIB)) {
12419 struct phy_device *phydev;
12421 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12423 if (!(phydev->supported & SUPPORTED_Pause) ||
12424 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
12425 (epause->rx_pause != epause->tx_pause)))
12428 tp->link_config.flowctrl = 0;
12429 if (epause->rx_pause) {
12430 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12432 if (epause->tx_pause) {
12433 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12434 newadv = ADVERTISED_Pause;
12436 newadv = ADVERTISED_Pause |
12437 ADVERTISED_Asym_Pause;
12438 } else if (epause->tx_pause) {
12439 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12440 newadv = ADVERTISED_Asym_Pause;
12444 if (epause->autoneg)
12445 tg3_flag_set(tp, PAUSE_AUTONEG);
12447 tg3_flag_clear(tp, PAUSE_AUTONEG);
12449 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12450 u32 oldadv = phydev->advertising &
12451 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12452 if (oldadv != newadv) {
12453 phydev->advertising &=
12454 ~(ADVERTISED_Pause |
12455 ADVERTISED_Asym_Pause);
12456 phydev->advertising |= newadv;
12457 if (phydev->autoneg) {
12459 * Always renegotiate the link to
12460 * inform our link partner of our
12461 * flow control settings, even if the
12462 * flow control is forced. Let
12463 * tg3_adjust_link() do the final
12464 * flow control setup.
12466 return phy_start_aneg(phydev);
12470 if (!epause->autoneg)
12471 tg3_setup_flow_control(tp, 0, 0);
12473 tp->link_config.advertising &=
12474 ~(ADVERTISED_Pause |
12475 ADVERTISED_Asym_Pause);
12476 tp->link_config.advertising |= newadv;
12481 if (netif_running(dev)) {
12482 tg3_netif_stop(tp);
12486 tg3_full_lock(tp, irq_sync);
12488 if (epause->autoneg)
12489 tg3_flag_set(tp, PAUSE_AUTONEG);
12491 tg3_flag_clear(tp, PAUSE_AUTONEG);
12492 if (epause->rx_pause)
12493 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12495 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12496 if (epause->tx_pause)
12497 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12499 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12501 if (netif_running(dev)) {
12502 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12503 err = tg3_restart_hw(tp, false);
12505 tg3_netif_start(tp);
12508 tg3_full_unlock(tp);
12511 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12516 static int tg3_get_sset_count(struct net_device *dev, int sset)
12520 return TG3_NUM_TEST;
12522 return TG3_NUM_STATS;
12524 return -EOPNOTSUPP;
12528 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12529 u32 *rules __always_unused)
12531 struct tg3 *tp = netdev_priv(dev);
12533 if (!tg3_flag(tp, SUPPORT_MSIX))
12534 return -EOPNOTSUPP;
12536 switch (info->cmd) {
12537 case ETHTOOL_GRXRINGS:
12538 if (netif_running(tp->dev))
12539 info->data = tp->rxq_cnt;
12541 info->data = num_online_cpus();
12542 if (info->data > TG3_RSS_MAX_NUM_QS)
12543 info->data = TG3_RSS_MAX_NUM_QS;
12546 /* The first interrupt vector only
12547 * handles link interrupts.
12553 return -EOPNOTSUPP;
12557 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12560 struct tg3 *tp = netdev_priv(dev);
12562 if (tg3_flag(tp, SUPPORT_MSIX))
12563 size = TG3_RSS_INDIR_TBL_SIZE;
12568 static int tg3_get_rxfh(struct net_device *dev, u32 *indir, u8 *key)
12570 struct tg3 *tp = netdev_priv(dev);
12573 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12574 indir[i] = tp->rss_ind_tbl[i];
12579 static int tg3_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key)
12581 struct tg3 *tp = netdev_priv(dev);
12584 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12585 tp->rss_ind_tbl[i] = indir[i];
12587 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12590 /* It is legal to write the indirection
12591 * table while the device is running.
12593 tg3_full_lock(tp, 0);
12594 tg3_rss_write_indir_tbl(tp);
12595 tg3_full_unlock(tp);
12600 static void tg3_get_channels(struct net_device *dev,
12601 struct ethtool_channels *channel)
12603 struct tg3 *tp = netdev_priv(dev);
12604 u32 deflt_qs = netif_get_num_default_rss_queues();
12606 channel->max_rx = tp->rxq_max;
12607 channel->max_tx = tp->txq_max;
12609 if (netif_running(dev)) {
12610 channel->rx_count = tp->rxq_cnt;
12611 channel->tx_count = tp->txq_cnt;
12614 channel->rx_count = tp->rxq_req;
12616 channel->rx_count = min(deflt_qs, tp->rxq_max);
12619 channel->tx_count = tp->txq_req;
12621 channel->tx_count = min(deflt_qs, tp->txq_max);
12625 static int tg3_set_channels(struct net_device *dev,
12626 struct ethtool_channels *channel)
12628 struct tg3 *tp = netdev_priv(dev);
12630 if (!tg3_flag(tp, SUPPORT_MSIX))
12631 return -EOPNOTSUPP;
12633 if (channel->rx_count > tp->rxq_max ||
12634 channel->tx_count > tp->txq_max)
12637 tp->rxq_req = channel->rx_count;
12638 tp->txq_req = channel->tx_count;
12640 if (!netif_running(dev))
12645 tg3_carrier_off(tp);
12647 tg3_start(tp, true, false, false);
12652 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
12654 switch (stringset) {
12656 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
12659 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
12662 WARN_ON(1); /* we need a WARN() */
12667 static int tg3_set_phys_id(struct net_device *dev,
12668 enum ethtool_phys_id_state state)
12670 struct tg3 *tp = netdev_priv(dev);
12672 if (!netif_running(tp->dev))
12676 case ETHTOOL_ID_ACTIVE:
12677 return 1; /* cycle on/off once per second */
12679 case ETHTOOL_ID_ON:
12680 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12681 LED_CTRL_1000MBPS_ON |
12682 LED_CTRL_100MBPS_ON |
12683 LED_CTRL_10MBPS_ON |
12684 LED_CTRL_TRAFFIC_OVERRIDE |
12685 LED_CTRL_TRAFFIC_BLINK |
12686 LED_CTRL_TRAFFIC_LED);
12689 case ETHTOOL_ID_OFF:
12690 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12691 LED_CTRL_TRAFFIC_OVERRIDE);
12694 case ETHTOOL_ID_INACTIVE:
12695 tw32(MAC_LED_CTRL, tp->led_ctrl);
12702 static void tg3_get_ethtool_stats(struct net_device *dev,
12703 struct ethtool_stats *estats, u64 *tmp_stats)
12705 struct tg3 *tp = netdev_priv(dev);
12708 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12710 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
12713 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
12717 u32 offset = 0, len = 0;
12720 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12723 if (magic == TG3_EEPROM_MAGIC) {
12724 for (offset = TG3_NVM_DIR_START;
12725 offset < TG3_NVM_DIR_END;
12726 offset += TG3_NVM_DIRENT_SIZE) {
12727 if (tg3_nvram_read(tp, offset, &val))
12730 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12731 TG3_NVM_DIRTYPE_EXTVPD)
12735 if (offset != TG3_NVM_DIR_END) {
12736 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12737 if (tg3_nvram_read(tp, offset + 4, &offset))
12740 offset = tg3_nvram_logical_addr(tp, offset);
12744 if (!offset || !len) {
12745 offset = TG3_NVM_VPD_OFF;
12746 len = TG3_NVM_VPD_LEN;
12749 buf = kmalloc(len, GFP_KERNEL);
12753 if (magic == TG3_EEPROM_MAGIC) {
12754 for (i = 0; i < len; i += 4) {
12755 /* The data is in little-endian format in NVRAM.
12756 * Use the big-endian read routines to preserve
12757 * the byte order as it exists in NVRAM.
12759 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12765 unsigned int pos = 0;
12767 ptr = (u8 *)&buf[0];
12768 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12769 cnt = pci_read_vpd(tp->pdev, pos,
12771 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12789 #define NVRAM_TEST_SIZE 0x100
12790 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12791 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12792 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12793 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12794 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12795 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12796 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12797 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12799 static int tg3_test_nvram(struct tg3 *tp)
12801 u32 csum, magic, len;
12803 int i, j, k, err = 0, size;
12805 if (tg3_flag(tp, NO_NVRAM))
12808 if (tg3_nvram_read(tp, 0, &magic) != 0)
12811 if (magic == TG3_EEPROM_MAGIC)
12812 size = NVRAM_TEST_SIZE;
12813 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
12814 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12815 TG3_EEPROM_SB_FORMAT_1) {
12816 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12817 case TG3_EEPROM_SB_REVISION_0:
12818 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12820 case TG3_EEPROM_SB_REVISION_2:
12821 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12823 case TG3_EEPROM_SB_REVISION_3:
12824 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12826 case TG3_EEPROM_SB_REVISION_4:
12827 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12829 case TG3_EEPROM_SB_REVISION_5:
12830 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12832 case TG3_EEPROM_SB_REVISION_6:
12833 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12840 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12841 size = NVRAM_SELFBOOT_HW_SIZE;
12845 buf = kmalloc(size, GFP_KERNEL);
12850 for (i = 0, j = 0; i < size; i += 4, j++) {
12851 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12858 /* Selfboot format */
12859 magic = be32_to_cpu(buf[0]);
12860 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
12861 TG3_EEPROM_MAGIC_FW) {
12862 u8 *buf8 = (u8 *) buf, csum8 = 0;
12864 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
12865 TG3_EEPROM_SB_REVISION_2) {
12866 /* For rev 2, the csum doesn't include the MBA. */
12867 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12869 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12872 for (i = 0; i < size; i++)
12885 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
12886 TG3_EEPROM_MAGIC_HW) {
12887 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
12888 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
12889 u8 *buf8 = (u8 *) buf;
12891 /* Separate the parity bits and the data bytes. */
12892 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12893 if ((i == 0) || (i == 8)) {
12897 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12898 parity[k++] = buf8[i] & msk;
12900 } else if (i == 16) {
12904 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12905 parity[k++] = buf8[i] & msk;
12908 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12909 parity[k++] = buf8[i] & msk;
12912 data[j++] = buf8[i];
12916 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12917 u8 hw8 = hweight8(data[i]);
12919 if ((hw8 & 0x1) && parity[i])
12921 else if (!(hw8 & 0x1) && !parity[i])
12930 /* Bootstrap checksum at offset 0x10 */
12931 csum = calc_crc((unsigned char *) buf, 0x10);
12932 if (csum != le32_to_cpu(buf[0x10/4]))
12935 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12936 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
12937 if (csum != le32_to_cpu(buf[0xfc/4]))
12942 buf = tg3_vpd_readblock(tp, &len);
12946 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
12948 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12952 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
12955 i += PCI_VPD_LRDT_TAG_SIZE;
12956 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12957 PCI_VPD_RO_KEYWORD_CHKSUM);
12961 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12963 for (i = 0; i <= j; i++)
12964 csum8 += ((u8 *)buf)[i];
12978 #define TG3_SERDES_TIMEOUT_SEC 2
12979 #define TG3_COPPER_TIMEOUT_SEC 6
12981 static int tg3_test_link(struct tg3 *tp)
12985 if (!netif_running(tp->dev))
12988 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12989 max = TG3_SERDES_TIMEOUT_SEC;
12991 max = TG3_COPPER_TIMEOUT_SEC;
12993 for (i = 0; i < max; i++) {
12997 if (msleep_interruptible(1000))
13004 /* Only test the commonly used registers */
13005 static int tg3_test_registers(struct tg3 *tp)
13007 int i, is_5705, is_5750;
13008 u32 offset, read_mask, write_mask, val, save_val, read_val;
13012 #define TG3_FL_5705 0x1
13013 #define TG3_FL_NOT_5705 0x2
13014 #define TG3_FL_NOT_5788 0x4
13015 #define TG3_FL_NOT_5750 0x8
13019 /* MAC Control Registers */
13020 { MAC_MODE, TG3_FL_NOT_5705,
13021 0x00000000, 0x00ef6f8c },
13022 { MAC_MODE, TG3_FL_5705,
13023 0x00000000, 0x01ef6b8c },
13024 { MAC_STATUS, TG3_FL_NOT_5705,
13025 0x03800107, 0x00000000 },
13026 { MAC_STATUS, TG3_FL_5705,
13027 0x03800100, 0x00000000 },
13028 { MAC_ADDR_0_HIGH, 0x0000,
13029 0x00000000, 0x0000ffff },
13030 { MAC_ADDR_0_LOW, 0x0000,
13031 0x00000000, 0xffffffff },
13032 { MAC_RX_MTU_SIZE, 0x0000,
13033 0x00000000, 0x0000ffff },
13034 { MAC_TX_MODE, 0x0000,
13035 0x00000000, 0x00000070 },
13036 { MAC_TX_LENGTHS, 0x0000,
13037 0x00000000, 0x00003fff },
13038 { MAC_RX_MODE, TG3_FL_NOT_5705,
13039 0x00000000, 0x000007fc },
13040 { MAC_RX_MODE, TG3_FL_5705,
13041 0x00000000, 0x000007dc },
13042 { MAC_HASH_REG_0, 0x0000,
13043 0x00000000, 0xffffffff },
13044 { MAC_HASH_REG_1, 0x0000,
13045 0x00000000, 0xffffffff },
13046 { MAC_HASH_REG_2, 0x0000,
13047 0x00000000, 0xffffffff },
13048 { MAC_HASH_REG_3, 0x0000,
13049 0x00000000, 0xffffffff },
13051 /* Receive Data and Receive BD Initiator Control Registers. */
13052 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
13053 0x00000000, 0xffffffff },
13054 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
13055 0x00000000, 0xffffffff },
13056 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
13057 0x00000000, 0x00000003 },
13058 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
13059 0x00000000, 0xffffffff },
13060 { RCVDBDI_STD_BD+0, 0x0000,
13061 0x00000000, 0xffffffff },
13062 { RCVDBDI_STD_BD+4, 0x0000,
13063 0x00000000, 0xffffffff },
13064 { RCVDBDI_STD_BD+8, 0x0000,
13065 0x00000000, 0xffff0002 },
13066 { RCVDBDI_STD_BD+0xc, 0x0000,
13067 0x00000000, 0xffffffff },
13069 /* Receive BD Initiator Control Registers. */
13070 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
13071 0x00000000, 0xffffffff },
13072 { RCVBDI_STD_THRESH, TG3_FL_5705,
13073 0x00000000, 0x000003ff },
13074 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
13075 0x00000000, 0xffffffff },
13077 /* Host Coalescing Control Registers. */
13078 { HOSTCC_MODE, TG3_FL_NOT_5705,
13079 0x00000000, 0x00000004 },
13080 { HOSTCC_MODE, TG3_FL_5705,
13081 0x00000000, 0x000000f6 },
13082 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13083 0x00000000, 0xffffffff },
13084 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13085 0x00000000, 0x000003ff },
13086 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13087 0x00000000, 0xffffffff },
13088 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13089 0x00000000, 0x000003ff },
13090 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13091 0x00000000, 0xffffffff },
13092 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13093 0x00000000, 0x000000ff },
13094 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13095 0x00000000, 0xffffffff },
13096 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13097 0x00000000, 0x000000ff },
13098 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13099 0x00000000, 0xffffffff },
13100 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13101 0x00000000, 0xffffffff },
13102 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13103 0x00000000, 0xffffffff },
13104 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13105 0x00000000, 0x000000ff },
13106 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13107 0x00000000, 0xffffffff },
13108 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13109 0x00000000, 0x000000ff },
13110 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13111 0x00000000, 0xffffffff },
13112 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13113 0x00000000, 0xffffffff },
13114 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13115 0x00000000, 0xffffffff },
13116 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13117 0x00000000, 0xffffffff },
13118 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13119 0x00000000, 0xffffffff },
13120 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13121 0xffffffff, 0x00000000 },
13122 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13123 0xffffffff, 0x00000000 },
13125 /* Buffer Manager Control Registers. */
13126 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
13127 0x00000000, 0x007fff80 },
13128 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
13129 0x00000000, 0x007fffff },
13130 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13131 0x00000000, 0x0000003f },
13132 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13133 0x00000000, 0x000001ff },
13134 { BUFMGR_MB_HIGH_WATER, 0x0000,
13135 0x00000000, 0x000001ff },
13136 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13137 0xffffffff, 0x00000000 },
13138 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13139 0xffffffff, 0x00000000 },
13141 /* Mailbox Registers */
13142 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13143 0x00000000, 0x000001ff },
13144 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13145 0x00000000, 0x000001ff },
13146 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13147 0x00000000, 0x000007ff },
13148 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13149 0x00000000, 0x000001ff },
13151 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13154 is_5705 = is_5750 = 0;
13155 if (tg3_flag(tp, 5705_PLUS)) {
13157 if (tg3_flag(tp, 5750_PLUS))
13161 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13162 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13165 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13168 if (tg3_flag(tp, IS_5788) &&
13169 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13172 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13175 offset = (u32) reg_tbl[i].offset;
13176 read_mask = reg_tbl[i].read_mask;
13177 write_mask = reg_tbl[i].write_mask;
13179 /* Save the original register content */
13180 save_val = tr32(offset);
13182 /* Determine the read-only value. */
13183 read_val = save_val & read_mask;
13185 /* Write zero to the register, then make sure the read-only bits
13186 * are not changed and the read/write bits are all zeros.
13190 val = tr32(offset);
13192 /* Test the read-only and read/write bits. */
13193 if (((val & read_mask) != read_val) || (val & write_mask))
13196 /* Write ones to all the bits defined by RdMask and WrMask, then
13197 * make sure the read-only bits are not changed and the
13198 * read/write bits are all ones.
13200 tw32(offset, read_mask | write_mask);
13202 val = tr32(offset);
13204 /* Test the read-only bits. */
13205 if ((val & read_mask) != read_val)
13208 /* Test the read/write bits. */
13209 if ((val & write_mask) != write_mask)
13212 tw32(offset, save_val);
13218 if (netif_msg_hw(tp))
13219 netdev_err(tp->dev,
13220 "Register test failed at offset %x\n", offset);
13221 tw32(offset, save_val);
13225 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13227 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
13231 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
13232 for (j = 0; j < len; j += 4) {
13235 tg3_write_mem(tp, offset + j, test_pattern[i]);
13236 tg3_read_mem(tp, offset + j, &val);
13237 if (val != test_pattern[i])
13244 static int tg3_test_memory(struct tg3 *tp)
13246 static struct mem_entry {
13249 } mem_tbl_570x[] = {
13250 { 0x00000000, 0x00b50},
13251 { 0x00002000, 0x1c000},
13252 { 0xffffffff, 0x00000}
13253 }, mem_tbl_5705[] = {
13254 { 0x00000100, 0x0000c},
13255 { 0x00000200, 0x00008},
13256 { 0x00004000, 0x00800},
13257 { 0x00006000, 0x01000},
13258 { 0x00008000, 0x02000},
13259 { 0x00010000, 0x0e000},
13260 { 0xffffffff, 0x00000}
13261 }, mem_tbl_5755[] = {
13262 { 0x00000200, 0x00008},
13263 { 0x00004000, 0x00800},
13264 { 0x00006000, 0x00800},
13265 { 0x00008000, 0x02000},
13266 { 0x00010000, 0x0c000},
13267 { 0xffffffff, 0x00000}
13268 }, mem_tbl_5906[] = {
13269 { 0x00000200, 0x00008},
13270 { 0x00004000, 0x00400},
13271 { 0x00006000, 0x00400},
13272 { 0x00008000, 0x01000},
13273 { 0x00010000, 0x01000},
13274 { 0xffffffff, 0x00000}
13275 }, mem_tbl_5717[] = {
13276 { 0x00000200, 0x00008},
13277 { 0x00010000, 0x0a000},
13278 { 0x00020000, 0x13c00},
13279 { 0xffffffff, 0x00000}
13280 }, mem_tbl_57765[] = {
13281 { 0x00000200, 0x00008},
13282 { 0x00004000, 0x00800},
13283 { 0x00006000, 0x09800},
13284 { 0x00010000, 0x0a000},
13285 { 0xffffffff, 0x00000}
13287 struct mem_entry *mem_tbl;
13291 if (tg3_flag(tp, 5717_PLUS))
13292 mem_tbl = mem_tbl_5717;
13293 else if (tg3_flag(tp, 57765_CLASS) ||
13294 tg3_asic_rev(tp) == ASIC_REV_5762)
13295 mem_tbl = mem_tbl_57765;
13296 else if (tg3_flag(tp, 5755_PLUS))
13297 mem_tbl = mem_tbl_5755;
13298 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
13299 mem_tbl = mem_tbl_5906;
13300 else if (tg3_flag(tp, 5705_PLUS))
13301 mem_tbl = mem_tbl_5705;
13303 mem_tbl = mem_tbl_570x;
13305 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
13306 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13314 #define TG3_TSO_MSS 500
13316 #define TG3_TSO_IP_HDR_LEN 20
13317 #define TG3_TSO_TCP_HDR_LEN 20
13318 #define TG3_TSO_TCP_OPT_LEN 12
13320 static const u8 tg3_tso_header[] = {
13322 0x45, 0x00, 0x00, 0x00,
13323 0x00, 0x00, 0x40, 0x00,
13324 0x40, 0x06, 0x00, 0x00,
13325 0x0a, 0x00, 0x00, 0x01,
13326 0x0a, 0x00, 0x00, 0x02,
13327 0x0d, 0x00, 0xe0, 0x00,
13328 0x00, 0x00, 0x01, 0x00,
13329 0x00, 0x00, 0x02, 0x00,
13330 0x80, 0x10, 0x10, 0x00,
13331 0x14, 0x09, 0x00, 0x00,
13332 0x01, 0x01, 0x08, 0x0a,
13333 0x11, 0x11, 0x11, 0x11,
13334 0x11, 0x11, 0x11, 0x11,
13337 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
13339 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
13340 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
13342 struct sk_buff *skb;
13343 u8 *tx_data, *rx_data;
13345 int num_pkts, tx_len, rx_len, i, err;
13346 struct tg3_rx_buffer_desc *desc;
13347 struct tg3_napi *tnapi, *rnapi;
13348 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
13350 tnapi = &tp->napi[0];
13351 rnapi = &tp->napi[0];
13352 if (tp->irq_cnt > 1) {
13353 if (tg3_flag(tp, ENABLE_RSS))
13354 rnapi = &tp->napi[1];
13355 if (tg3_flag(tp, ENABLE_TSS))
13356 tnapi = &tp->napi[1];
13358 coal_now = tnapi->coal_now | rnapi->coal_now;
13363 skb = netdev_alloc_skb(tp->dev, tx_len);
13367 tx_data = skb_put(skb, tx_len);
13368 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13369 memset(tx_data + ETH_ALEN, 0x0, 8);
13371 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13373 if (tso_loopback) {
13374 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13376 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13377 TG3_TSO_TCP_OPT_LEN;
13379 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13380 sizeof(tg3_tso_header));
13383 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13384 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13386 /* Set the total length field in the IP header */
13387 iph->tot_len = htons((u16)(mss + hdr_len));
13389 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13390 TXD_FLAG_CPU_POST_DMA);
13392 if (tg3_flag(tp, HW_TSO_1) ||
13393 tg3_flag(tp, HW_TSO_2) ||
13394 tg3_flag(tp, HW_TSO_3)) {
13396 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13397 th = (struct tcphdr *)&tx_data[val];
13400 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13402 if (tg3_flag(tp, HW_TSO_3)) {
13403 mss |= (hdr_len & 0xc) << 12;
13404 if (hdr_len & 0x10)
13405 base_flags |= 0x00000010;
13406 base_flags |= (hdr_len & 0x3e0) << 5;
13407 } else if (tg3_flag(tp, HW_TSO_2))
13408 mss |= hdr_len << 9;
13409 else if (tg3_flag(tp, HW_TSO_1) ||
13410 tg3_asic_rev(tp) == ASIC_REV_5705) {
13411 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13413 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13416 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13419 data_off = ETH_HLEN;
13421 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13422 tx_len > VLAN_ETH_FRAME_LEN)
13423 base_flags |= TXD_FLAG_JMB_PKT;
13426 for (i = data_off; i < tx_len; i++)
13427 tx_data[i] = (u8) (i & 0xff);
13429 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13430 if (pci_dma_mapping_error(tp->pdev, map)) {
13431 dev_kfree_skb(skb);
13435 val = tnapi->tx_prod;
13436 tnapi->tx_buffers[val].skb = skb;
13437 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13439 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13444 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
13446 budget = tg3_tx_avail(tnapi);
13447 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
13448 base_flags | TXD_FLAG_END, mss, 0)) {
13449 tnapi->tx_buffers[val].skb = NULL;
13450 dev_kfree_skb(skb);
13456 /* Sync BD data before updating mailbox */
13459 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13460 tr32_mailbox(tnapi->prodmbox);
13464 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13465 for (i = 0; i < 35; i++) {
13466 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13471 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13472 rx_idx = rnapi->hw_status->idx[0].rx_producer;
13473 if ((tx_idx == tnapi->tx_prod) &&
13474 (rx_idx == (rx_start_idx + num_pkts)))
13478 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
13479 dev_kfree_skb(skb);
13481 if (tx_idx != tnapi->tx_prod)
13484 if (rx_idx != rx_start_idx + num_pkts)
13488 while (rx_idx != rx_start_idx) {
13489 desc = &rnapi->rx_rcb[rx_start_idx++];
13490 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13491 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
13493 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13494 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13497 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13500 if (!tso_loopback) {
13501 if (rx_len != tx_len)
13504 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13505 if (opaque_key != RXD_OPAQUE_RING_STD)
13508 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13511 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13512 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
13513 >> RXD_TCPCSUM_SHIFT != 0xffff) {
13517 if (opaque_key == RXD_OPAQUE_RING_STD) {
13518 rx_data = tpr->rx_std_buffers[desc_idx].data;
13519 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13521 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
13522 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
13523 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13528 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13529 PCI_DMA_FROMDEVICE);
13531 rx_data += TG3_RX_OFFSET(tp);
13532 for (i = data_off; i < rx_len; i++, val++) {
13533 if (*(rx_data + i) != (u8) (val & 0xff))
13540 /* tg3_free_rings will unmap and free the rx_data */
13545 #define TG3_STD_LOOPBACK_FAILED 1
13546 #define TG3_JMB_LOOPBACK_FAILED 2
13547 #define TG3_TSO_LOOPBACK_FAILED 4
13548 #define TG3_LOOPBACK_FAILED \
13549 (TG3_STD_LOOPBACK_FAILED | \
13550 TG3_JMB_LOOPBACK_FAILED | \
13551 TG3_TSO_LOOPBACK_FAILED)
13553 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13557 u32 jmb_pkt_sz = 9000;
13560 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13562 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13563 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13565 if (!netif_running(tp->dev)) {
13566 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13567 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13569 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13573 err = tg3_reset_hw(tp, true);
13575 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13576 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13578 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13582 if (tg3_flag(tp, ENABLE_RSS)) {
13585 /* Reroute all rx packets to the 1st queue */
13586 for (i = MAC_RSS_INDIR_TBL_0;
13587 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13591 /* HW errata - mac loopback fails in some cases on 5780.
13592 * Normal traffic and PHY loopback are not affected by
13593 * errata. Also, the MAC loopback test is deprecated for
13594 * all newer ASIC revisions.
13596 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13597 !tg3_flag(tp, CPMU_PRESENT)) {
13598 tg3_mac_loopback(tp, true);
13600 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13601 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13603 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13604 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13605 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13607 tg3_mac_loopback(tp, false);
13610 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13611 !tg3_flag(tp, USE_PHYLIB)) {
13614 tg3_phy_lpbk_set(tp, 0, false);
13616 /* Wait for link */
13617 for (i = 0; i < 100; i++) {
13618 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13623 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13624 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13625 if (tg3_flag(tp, TSO_CAPABLE) &&
13626 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13627 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
13628 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13629 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13630 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13633 tg3_phy_lpbk_set(tp, 0, true);
13635 /* All link indications report up, but the hardware
13636 * isn't really ready for about 20 msec. Double it
13641 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13642 data[TG3_EXT_LOOPB_TEST] |=
13643 TG3_STD_LOOPBACK_FAILED;
13644 if (tg3_flag(tp, TSO_CAPABLE) &&
13645 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13646 data[TG3_EXT_LOOPB_TEST] |=
13647 TG3_TSO_LOOPBACK_FAILED;
13648 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13649 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13650 data[TG3_EXT_LOOPB_TEST] |=
13651 TG3_JMB_LOOPBACK_FAILED;
13654 /* Re-enable gphy autopowerdown. */
13655 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13656 tg3_phy_toggle_apd(tp, true);
13659 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13660 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
13663 tp->phy_flags |= eee_cap;
13668 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13671 struct tg3 *tp = netdev_priv(dev);
13672 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
13674 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13675 if (tg3_power_up(tp)) {
13676 etest->flags |= ETH_TEST_FL_FAILED;
13677 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13680 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
13683 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13685 if (tg3_test_nvram(tp) != 0) {
13686 etest->flags |= ETH_TEST_FL_FAILED;
13687 data[TG3_NVRAM_TEST] = 1;
13689 if (!doextlpbk && tg3_test_link(tp)) {
13690 etest->flags |= ETH_TEST_FL_FAILED;
13691 data[TG3_LINK_TEST] = 1;
13693 if (etest->flags & ETH_TEST_FL_OFFLINE) {
13694 int err, err2 = 0, irq_sync = 0;
13696 if (netif_running(dev)) {
13698 tg3_netif_stop(tp);
13702 tg3_full_lock(tp, irq_sync);
13703 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13704 err = tg3_nvram_lock(tp);
13705 tg3_halt_cpu(tp, RX_CPU_BASE);
13706 if (!tg3_flag(tp, 5705_PLUS))
13707 tg3_halt_cpu(tp, TX_CPU_BASE);
13709 tg3_nvram_unlock(tp);
13711 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13714 if (tg3_test_registers(tp) != 0) {
13715 etest->flags |= ETH_TEST_FL_FAILED;
13716 data[TG3_REGISTER_TEST] = 1;
13719 if (tg3_test_memory(tp) != 0) {
13720 etest->flags |= ETH_TEST_FL_FAILED;
13721 data[TG3_MEMORY_TEST] = 1;
13725 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13727 if (tg3_test_loopback(tp, data, doextlpbk))
13728 etest->flags |= ETH_TEST_FL_FAILED;
13730 tg3_full_unlock(tp);
13732 if (tg3_test_interrupt(tp) != 0) {
13733 etest->flags |= ETH_TEST_FL_FAILED;
13734 data[TG3_INTERRUPT_TEST] = 1;
13737 tg3_full_lock(tp, 0);
13739 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13740 if (netif_running(dev)) {
13741 tg3_flag_set(tp, INIT_COMPLETE);
13742 err2 = tg3_restart_hw(tp, true);
13744 tg3_netif_start(tp);
13747 tg3_full_unlock(tp);
13749 if (irq_sync && !err2)
13752 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13753 tg3_power_down_prepare(tp);
13757 static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
13759 struct tg3 *tp = netdev_priv(dev);
13760 struct hwtstamp_config stmpconf;
13762 if (!tg3_flag(tp, PTP_CAPABLE))
13763 return -EOPNOTSUPP;
13765 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13768 if (stmpconf.flags)
13771 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13772 stmpconf.tx_type != HWTSTAMP_TX_OFF)
13775 switch (stmpconf.rx_filter) {
13776 case HWTSTAMP_FILTER_NONE:
13779 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13780 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13781 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13783 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13784 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13785 TG3_RX_PTP_CTL_SYNC_EVNT;
13787 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13788 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13789 TG3_RX_PTP_CTL_DELAY_REQ;
13791 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13792 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13793 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13795 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13796 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13797 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13799 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13800 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13801 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13803 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13804 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13805 TG3_RX_PTP_CTL_SYNC_EVNT;
13807 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13808 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13809 TG3_RX_PTP_CTL_SYNC_EVNT;
13811 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13812 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13813 TG3_RX_PTP_CTL_SYNC_EVNT;
13815 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13816 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13817 TG3_RX_PTP_CTL_DELAY_REQ;
13819 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13820 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13821 TG3_RX_PTP_CTL_DELAY_REQ;
13823 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13824 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13825 TG3_RX_PTP_CTL_DELAY_REQ;
13831 if (netif_running(dev) && tp->rxptpctl)
13832 tw32(TG3_RX_PTP_CTL,
13833 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13835 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13836 tg3_flag_set(tp, TX_TSTAMP_EN);
13838 tg3_flag_clear(tp, TX_TSTAMP_EN);
13840 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13844 static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13846 struct tg3 *tp = netdev_priv(dev);
13847 struct hwtstamp_config stmpconf;
13849 if (!tg3_flag(tp, PTP_CAPABLE))
13850 return -EOPNOTSUPP;
13852 stmpconf.flags = 0;
13853 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13854 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13856 switch (tp->rxptpctl) {
13858 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13860 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13861 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13863 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13864 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13866 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13867 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13869 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13870 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13872 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13873 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13875 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13876 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13878 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13879 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13881 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13882 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13884 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13885 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13887 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13888 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13890 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13891 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13893 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13894 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13901 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13905 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13907 struct mii_ioctl_data *data = if_mii(ifr);
13908 struct tg3 *tp = netdev_priv(dev);
13911 if (tg3_flag(tp, USE_PHYLIB)) {
13912 struct phy_device *phydev;
13913 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
13915 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
13916 return phy_mii_ioctl(phydev, ifr, cmd);
13921 data->phy_id = tp->phy_addr;
13924 case SIOCGMIIREG: {
13927 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13928 break; /* We have no PHY */
13930 if (!netif_running(dev))
13933 spin_lock_bh(&tp->lock);
13934 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13935 data->reg_num & 0x1f, &mii_regval);
13936 spin_unlock_bh(&tp->lock);
13938 data->val_out = mii_regval;
13944 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13945 break; /* We have no PHY */
13947 if (!netif_running(dev))
13950 spin_lock_bh(&tp->lock);
13951 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13952 data->reg_num & 0x1f, data->val_in);
13953 spin_unlock_bh(&tp->lock);
13957 case SIOCSHWTSTAMP:
13958 return tg3_hwtstamp_set(dev, ifr);
13960 case SIOCGHWTSTAMP:
13961 return tg3_hwtstamp_get(dev, ifr);
13967 return -EOPNOTSUPP;
13970 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13972 struct tg3 *tp = netdev_priv(dev);
13974 memcpy(ec, &tp->coal, sizeof(*ec));
13978 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13980 struct tg3 *tp = netdev_priv(dev);
13981 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13982 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13984 if (!tg3_flag(tp, 5705_PLUS)) {
13985 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13986 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13987 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13988 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13991 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13992 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13993 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13994 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13995 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13996 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13997 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13998 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13999 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
14000 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
14003 /* No rx interrupts will be generated if both are zero */
14004 if ((ec->rx_coalesce_usecs == 0) &&
14005 (ec->rx_max_coalesced_frames == 0))
14008 /* No tx interrupts will be generated if both are zero */
14009 if ((ec->tx_coalesce_usecs == 0) &&
14010 (ec->tx_max_coalesced_frames == 0))
14013 /* Only copy relevant parameters, ignore all others. */
14014 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
14015 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
14016 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
14017 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
14018 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
14019 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
14020 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
14021 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
14022 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
14024 if (netif_running(dev)) {
14025 tg3_full_lock(tp, 0);
14026 __tg3_set_coalesce(tp, &tp->coal);
14027 tg3_full_unlock(tp);
14032 static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
14034 struct tg3 *tp = netdev_priv(dev);
14036 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14037 netdev_warn(tp->dev, "Board does not support EEE!\n");
14038 return -EOPNOTSUPP;
14041 if (edata->advertised != tp->eee.advertised) {
14042 netdev_warn(tp->dev,
14043 "Direct manipulation of EEE advertisement is not supported\n");
14047 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
14048 netdev_warn(tp->dev,
14049 "Maximal Tx Lpi timer supported is %#x(u)\n",
14050 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
14056 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
14057 tg3_warn_mgmt_link_flap(tp);
14059 if (netif_running(tp->dev)) {
14060 tg3_full_lock(tp, 0);
14063 tg3_full_unlock(tp);
14069 static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
14071 struct tg3 *tp = netdev_priv(dev);
14073 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14074 netdev_warn(tp->dev,
14075 "Board does not support EEE!\n");
14076 return -EOPNOTSUPP;
14083 static const struct ethtool_ops tg3_ethtool_ops = {
14084 .get_settings = tg3_get_settings,
14085 .set_settings = tg3_set_settings,
14086 .get_drvinfo = tg3_get_drvinfo,
14087 .get_regs_len = tg3_get_regs_len,
14088 .get_regs = tg3_get_regs,
14089 .get_wol = tg3_get_wol,
14090 .set_wol = tg3_set_wol,
14091 .get_msglevel = tg3_get_msglevel,
14092 .set_msglevel = tg3_set_msglevel,
14093 .nway_reset = tg3_nway_reset,
14094 .get_link = ethtool_op_get_link,
14095 .get_eeprom_len = tg3_get_eeprom_len,
14096 .get_eeprom = tg3_get_eeprom,
14097 .set_eeprom = tg3_set_eeprom,
14098 .get_ringparam = tg3_get_ringparam,
14099 .set_ringparam = tg3_set_ringparam,
14100 .get_pauseparam = tg3_get_pauseparam,
14101 .set_pauseparam = tg3_set_pauseparam,
14102 .self_test = tg3_self_test,
14103 .get_strings = tg3_get_strings,
14104 .set_phys_id = tg3_set_phys_id,
14105 .get_ethtool_stats = tg3_get_ethtool_stats,
14106 .get_coalesce = tg3_get_coalesce,
14107 .set_coalesce = tg3_set_coalesce,
14108 .get_sset_count = tg3_get_sset_count,
14109 .get_rxnfc = tg3_get_rxnfc,
14110 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
14111 .get_rxfh = tg3_get_rxfh,
14112 .set_rxfh = tg3_set_rxfh,
14113 .get_channels = tg3_get_channels,
14114 .set_channels = tg3_set_channels,
14115 .get_ts_info = tg3_get_ts_info,
14116 .get_eee = tg3_get_eee,
14117 .set_eee = tg3_set_eee,
14120 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
14121 struct rtnl_link_stats64 *stats)
14123 struct tg3 *tp = netdev_priv(dev);
14125 spin_lock_bh(&tp->lock);
14126 if (!tp->hw_stats) {
14127 *stats = tp->net_stats_prev;
14128 spin_unlock_bh(&tp->lock);
14132 tg3_get_nstats(tp, stats);
14133 spin_unlock_bh(&tp->lock);
14138 static void tg3_set_rx_mode(struct net_device *dev)
14140 struct tg3 *tp = netdev_priv(dev);
14142 if (!netif_running(dev))
14145 tg3_full_lock(tp, 0);
14146 __tg3_set_rx_mode(dev);
14147 tg3_full_unlock(tp);
14150 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14153 dev->mtu = new_mtu;
14155 if (new_mtu > ETH_DATA_LEN) {
14156 if (tg3_flag(tp, 5780_CLASS)) {
14157 netdev_update_features(dev);
14158 tg3_flag_clear(tp, TSO_CAPABLE);
14160 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14163 if (tg3_flag(tp, 5780_CLASS)) {
14164 tg3_flag_set(tp, TSO_CAPABLE);
14165 netdev_update_features(dev);
14167 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14171 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14173 struct tg3 *tp = netdev_priv(dev);
14175 bool reset_phy = false;
14177 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
14180 if (!netif_running(dev)) {
14181 /* We'll just catch it later when the
14184 tg3_set_mtu(dev, tp, new_mtu);
14190 tg3_netif_stop(tp);
14192 tg3_set_mtu(dev, tp, new_mtu);
14194 tg3_full_lock(tp, 1);
14196 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14198 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14199 * breaks all requests to 256 bytes.
14201 if (tg3_asic_rev(tp) == ASIC_REV_57766)
14204 err = tg3_restart_hw(tp, reset_phy);
14207 tg3_netif_start(tp);
14209 tg3_full_unlock(tp);
14217 static const struct net_device_ops tg3_netdev_ops = {
14218 .ndo_open = tg3_open,
14219 .ndo_stop = tg3_close,
14220 .ndo_start_xmit = tg3_start_xmit,
14221 .ndo_get_stats64 = tg3_get_stats64,
14222 .ndo_validate_addr = eth_validate_addr,
14223 .ndo_set_rx_mode = tg3_set_rx_mode,
14224 .ndo_set_mac_address = tg3_set_mac_addr,
14225 .ndo_do_ioctl = tg3_ioctl,
14226 .ndo_tx_timeout = tg3_tx_timeout,
14227 .ndo_change_mtu = tg3_change_mtu,
14228 .ndo_fix_features = tg3_fix_features,
14229 .ndo_set_features = tg3_set_features,
14230 #ifdef CONFIG_NET_POLL_CONTROLLER
14231 .ndo_poll_controller = tg3_poll_controller,
14235 static void tg3_get_eeprom_size(struct tg3 *tp)
14237 u32 cursize, val, magic;
14239 tp->nvram_size = EEPROM_CHIP_SIZE;
14241 if (tg3_nvram_read(tp, 0, &magic) != 0)
14244 if ((magic != TG3_EEPROM_MAGIC) &&
14245 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14246 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
14250 * Size the chip by reading offsets at increasing powers of two.
14251 * When we encounter our validation signature, we know the addressing
14252 * has wrapped around, and thus have our chip size.
14256 while (cursize < tp->nvram_size) {
14257 if (tg3_nvram_read(tp, cursize, &val) != 0)
14266 tp->nvram_size = cursize;
14269 static void tg3_get_nvram_size(struct tg3 *tp)
14273 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14276 /* Selfboot format */
14277 if (val != TG3_EEPROM_MAGIC) {
14278 tg3_get_eeprom_size(tp);
14282 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14284 /* This is confusing. We want to operate on the
14285 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14286 * call will read from NVRAM and byteswap the data
14287 * according to the byteswapping settings for all
14288 * other register accesses. This ensures the data we
14289 * want will always reside in the lower 16-bits.
14290 * However, the data in NVRAM is in LE format, which
14291 * means the data from the NVRAM read will always be
14292 * opposite the endianness of the CPU. The 16-bit
14293 * byteswap then brings the data to CPU endianness.
14295 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14299 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14302 static void tg3_get_nvram_info(struct tg3 *tp)
14306 nvcfg1 = tr32(NVRAM_CFG1);
14307 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
14308 tg3_flag_set(tp, FLASH);
14310 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14311 tw32(NVRAM_CFG1, nvcfg1);
14314 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
14315 tg3_flag(tp, 5780_CLASS)) {
14316 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
14317 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14318 tp->nvram_jedecnum = JEDEC_ATMEL;
14319 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14320 tg3_flag_set(tp, NVRAM_BUFFERED);
14322 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14323 tp->nvram_jedecnum = JEDEC_ATMEL;
14324 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14326 case FLASH_VENDOR_ATMEL_EEPROM:
14327 tp->nvram_jedecnum = JEDEC_ATMEL;
14328 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14329 tg3_flag_set(tp, NVRAM_BUFFERED);
14331 case FLASH_VENDOR_ST:
14332 tp->nvram_jedecnum = JEDEC_ST;
14333 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
14334 tg3_flag_set(tp, NVRAM_BUFFERED);
14336 case FLASH_VENDOR_SAIFUN:
14337 tp->nvram_jedecnum = JEDEC_SAIFUN;
14338 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14340 case FLASH_VENDOR_SST_SMALL:
14341 case FLASH_VENDOR_SST_LARGE:
14342 tp->nvram_jedecnum = JEDEC_SST;
14343 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14347 tp->nvram_jedecnum = JEDEC_ATMEL;
14348 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14349 tg3_flag_set(tp, NVRAM_BUFFERED);
14353 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
14355 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14356 case FLASH_5752PAGE_SIZE_256:
14357 tp->nvram_pagesize = 256;
14359 case FLASH_5752PAGE_SIZE_512:
14360 tp->nvram_pagesize = 512;
14362 case FLASH_5752PAGE_SIZE_1K:
14363 tp->nvram_pagesize = 1024;
14365 case FLASH_5752PAGE_SIZE_2K:
14366 tp->nvram_pagesize = 2048;
14368 case FLASH_5752PAGE_SIZE_4K:
14369 tp->nvram_pagesize = 4096;
14371 case FLASH_5752PAGE_SIZE_264:
14372 tp->nvram_pagesize = 264;
14374 case FLASH_5752PAGE_SIZE_528:
14375 tp->nvram_pagesize = 528;
14380 static void tg3_get_5752_nvram_info(struct tg3 *tp)
14384 nvcfg1 = tr32(NVRAM_CFG1);
14386 /* NVRAM protection for TPM */
14387 if (nvcfg1 & (1 << 27))
14388 tg3_flag_set(tp, PROTECTED_NVRAM);
14390 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14391 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14392 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14393 tp->nvram_jedecnum = JEDEC_ATMEL;
14394 tg3_flag_set(tp, NVRAM_BUFFERED);
14396 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14397 tp->nvram_jedecnum = JEDEC_ATMEL;
14398 tg3_flag_set(tp, NVRAM_BUFFERED);
14399 tg3_flag_set(tp, FLASH);
14401 case FLASH_5752VENDOR_ST_M45PE10:
14402 case FLASH_5752VENDOR_ST_M45PE20:
14403 case FLASH_5752VENDOR_ST_M45PE40:
14404 tp->nvram_jedecnum = JEDEC_ST;
14405 tg3_flag_set(tp, NVRAM_BUFFERED);
14406 tg3_flag_set(tp, FLASH);
14410 if (tg3_flag(tp, FLASH)) {
14411 tg3_nvram_get_pagesize(tp, nvcfg1);
14413 /* For eeprom, set pagesize to maximum eeprom size */
14414 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14416 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14417 tw32(NVRAM_CFG1, nvcfg1);
14421 static void tg3_get_5755_nvram_info(struct tg3 *tp)
14423 u32 nvcfg1, protect = 0;
14425 nvcfg1 = tr32(NVRAM_CFG1);
14427 /* NVRAM protection for TPM */
14428 if (nvcfg1 & (1 << 27)) {
14429 tg3_flag_set(tp, PROTECTED_NVRAM);
14433 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14435 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14436 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14437 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14438 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14439 tp->nvram_jedecnum = JEDEC_ATMEL;
14440 tg3_flag_set(tp, NVRAM_BUFFERED);
14441 tg3_flag_set(tp, FLASH);
14442 tp->nvram_pagesize = 264;
14443 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14444 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14445 tp->nvram_size = (protect ? 0x3e200 :
14446 TG3_NVRAM_SIZE_512KB);
14447 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14448 tp->nvram_size = (protect ? 0x1f200 :
14449 TG3_NVRAM_SIZE_256KB);
14451 tp->nvram_size = (protect ? 0x1f200 :
14452 TG3_NVRAM_SIZE_128KB);
14454 case FLASH_5752VENDOR_ST_M45PE10:
14455 case FLASH_5752VENDOR_ST_M45PE20:
14456 case FLASH_5752VENDOR_ST_M45PE40:
14457 tp->nvram_jedecnum = JEDEC_ST;
14458 tg3_flag_set(tp, NVRAM_BUFFERED);
14459 tg3_flag_set(tp, FLASH);
14460 tp->nvram_pagesize = 256;
14461 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14462 tp->nvram_size = (protect ?
14463 TG3_NVRAM_SIZE_64KB :
14464 TG3_NVRAM_SIZE_128KB);
14465 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14466 tp->nvram_size = (protect ?
14467 TG3_NVRAM_SIZE_64KB :
14468 TG3_NVRAM_SIZE_256KB);
14470 tp->nvram_size = (protect ?
14471 TG3_NVRAM_SIZE_128KB :
14472 TG3_NVRAM_SIZE_512KB);
14477 static void tg3_get_5787_nvram_info(struct tg3 *tp)
14481 nvcfg1 = tr32(NVRAM_CFG1);
14483 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14484 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14485 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14486 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14487 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14488 tp->nvram_jedecnum = JEDEC_ATMEL;
14489 tg3_flag_set(tp, NVRAM_BUFFERED);
14490 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14492 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14493 tw32(NVRAM_CFG1, nvcfg1);
14495 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14496 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14497 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14498 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14499 tp->nvram_jedecnum = JEDEC_ATMEL;
14500 tg3_flag_set(tp, NVRAM_BUFFERED);
14501 tg3_flag_set(tp, FLASH);
14502 tp->nvram_pagesize = 264;
14504 case FLASH_5752VENDOR_ST_M45PE10:
14505 case FLASH_5752VENDOR_ST_M45PE20:
14506 case FLASH_5752VENDOR_ST_M45PE40:
14507 tp->nvram_jedecnum = JEDEC_ST;
14508 tg3_flag_set(tp, NVRAM_BUFFERED);
14509 tg3_flag_set(tp, FLASH);
14510 tp->nvram_pagesize = 256;
14515 static void tg3_get_5761_nvram_info(struct tg3 *tp)
14517 u32 nvcfg1, protect = 0;
14519 nvcfg1 = tr32(NVRAM_CFG1);
14521 /* NVRAM protection for TPM */
14522 if (nvcfg1 & (1 << 27)) {
14523 tg3_flag_set(tp, PROTECTED_NVRAM);
14527 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14529 case FLASH_5761VENDOR_ATMEL_ADB021D:
14530 case FLASH_5761VENDOR_ATMEL_ADB041D:
14531 case FLASH_5761VENDOR_ATMEL_ADB081D:
14532 case FLASH_5761VENDOR_ATMEL_ADB161D:
14533 case FLASH_5761VENDOR_ATMEL_MDB021D:
14534 case FLASH_5761VENDOR_ATMEL_MDB041D:
14535 case FLASH_5761VENDOR_ATMEL_MDB081D:
14536 case FLASH_5761VENDOR_ATMEL_MDB161D:
14537 tp->nvram_jedecnum = JEDEC_ATMEL;
14538 tg3_flag_set(tp, NVRAM_BUFFERED);
14539 tg3_flag_set(tp, FLASH);
14540 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14541 tp->nvram_pagesize = 256;
14543 case FLASH_5761VENDOR_ST_A_M45PE20:
14544 case FLASH_5761VENDOR_ST_A_M45PE40:
14545 case FLASH_5761VENDOR_ST_A_M45PE80:
14546 case FLASH_5761VENDOR_ST_A_M45PE16:
14547 case FLASH_5761VENDOR_ST_M_M45PE20:
14548 case FLASH_5761VENDOR_ST_M_M45PE40:
14549 case FLASH_5761VENDOR_ST_M_M45PE80:
14550 case FLASH_5761VENDOR_ST_M_M45PE16:
14551 tp->nvram_jedecnum = JEDEC_ST;
14552 tg3_flag_set(tp, NVRAM_BUFFERED);
14553 tg3_flag_set(tp, FLASH);
14554 tp->nvram_pagesize = 256;
14559 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14562 case FLASH_5761VENDOR_ATMEL_ADB161D:
14563 case FLASH_5761VENDOR_ATMEL_MDB161D:
14564 case FLASH_5761VENDOR_ST_A_M45PE16:
14565 case FLASH_5761VENDOR_ST_M_M45PE16:
14566 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14568 case FLASH_5761VENDOR_ATMEL_ADB081D:
14569 case FLASH_5761VENDOR_ATMEL_MDB081D:
14570 case FLASH_5761VENDOR_ST_A_M45PE80:
14571 case FLASH_5761VENDOR_ST_M_M45PE80:
14572 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14574 case FLASH_5761VENDOR_ATMEL_ADB041D:
14575 case FLASH_5761VENDOR_ATMEL_MDB041D:
14576 case FLASH_5761VENDOR_ST_A_M45PE40:
14577 case FLASH_5761VENDOR_ST_M_M45PE40:
14578 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14580 case FLASH_5761VENDOR_ATMEL_ADB021D:
14581 case FLASH_5761VENDOR_ATMEL_MDB021D:
14582 case FLASH_5761VENDOR_ST_A_M45PE20:
14583 case FLASH_5761VENDOR_ST_M_M45PE20:
14584 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14590 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14592 tp->nvram_jedecnum = JEDEC_ATMEL;
14593 tg3_flag_set(tp, NVRAM_BUFFERED);
14594 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14597 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14601 nvcfg1 = tr32(NVRAM_CFG1);
14603 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14604 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14605 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14606 tp->nvram_jedecnum = JEDEC_ATMEL;
14607 tg3_flag_set(tp, NVRAM_BUFFERED);
14608 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14610 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14611 tw32(NVRAM_CFG1, nvcfg1);
14613 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14614 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14615 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14616 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14617 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14618 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14619 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14620 tp->nvram_jedecnum = JEDEC_ATMEL;
14621 tg3_flag_set(tp, NVRAM_BUFFERED);
14622 tg3_flag_set(tp, FLASH);
14624 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14625 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14626 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14627 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14628 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14630 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14631 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14632 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14634 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14635 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14636 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14640 case FLASH_5752VENDOR_ST_M45PE10:
14641 case FLASH_5752VENDOR_ST_M45PE20:
14642 case FLASH_5752VENDOR_ST_M45PE40:
14643 tp->nvram_jedecnum = JEDEC_ST;
14644 tg3_flag_set(tp, NVRAM_BUFFERED);
14645 tg3_flag_set(tp, FLASH);
14647 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14648 case FLASH_5752VENDOR_ST_M45PE10:
14649 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14651 case FLASH_5752VENDOR_ST_M45PE20:
14652 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14654 case FLASH_5752VENDOR_ST_M45PE40:
14655 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14660 tg3_flag_set(tp, NO_NVRAM);
14664 tg3_nvram_get_pagesize(tp, nvcfg1);
14665 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14666 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14670 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14674 nvcfg1 = tr32(NVRAM_CFG1);
14676 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14677 case FLASH_5717VENDOR_ATMEL_EEPROM:
14678 case FLASH_5717VENDOR_MICRO_EEPROM:
14679 tp->nvram_jedecnum = JEDEC_ATMEL;
14680 tg3_flag_set(tp, NVRAM_BUFFERED);
14681 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14683 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14684 tw32(NVRAM_CFG1, nvcfg1);
14686 case FLASH_5717VENDOR_ATMEL_MDB011D:
14687 case FLASH_5717VENDOR_ATMEL_ADB011B:
14688 case FLASH_5717VENDOR_ATMEL_ADB011D:
14689 case FLASH_5717VENDOR_ATMEL_MDB021D:
14690 case FLASH_5717VENDOR_ATMEL_ADB021B:
14691 case FLASH_5717VENDOR_ATMEL_ADB021D:
14692 case FLASH_5717VENDOR_ATMEL_45USPT:
14693 tp->nvram_jedecnum = JEDEC_ATMEL;
14694 tg3_flag_set(tp, NVRAM_BUFFERED);
14695 tg3_flag_set(tp, FLASH);
14697 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14698 case FLASH_5717VENDOR_ATMEL_MDB021D:
14699 /* Detect size with tg3_nvram_get_size() */
14701 case FLASH_5717VENDOR_ATMEL_ADB021B:
14702 case FLASH_5717VENDOR_ATMEL_ADB021D:
14703 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14706 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14710 case FLASH_5717VENDOR_ST_M_M25PE10:
14711 case FLASH_5717VENDOR_ST_A_M25PE10:
14712 case FLASH_5717VENDOR_ST_M_M45PE10:
14713 case FLASH_5717VENDOR_ST_A_M45PE10:
14714 case FLASH_5717VENDOR_ST_M_M25PE20:
14715 case FLASH_5717VENDOR_ST_A_M25PE20:
14716 case FLASH_5717VENDOR_ST_M_M45PE20:
14717 case FLASH_5717VENDOR_ST_A_M45PE20:
14718 case FLASH_5717VENDOR_ST_25USPT:
14719 case FLASH_5717VENDOR_ST_45USPT:
14720 tp->nvram_jedecnum = JEDEC_ST;
14721 tg3_flag_set(tp, NVRAM_BUFFERED);
14722 tg3_flag_set(tp, FLASH);
14724 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14725 case FLASH_5717VENDOR_ST_M_M25PE20:
14726 case FLASH_5717VENDOR_ST_M_M45PE20:
14727 /* Detect size with tg3_nvram_get_size() */
14729 case FLASH_5717VENDOR_ST_A_M25PE20:
14730 case FLASH_5717VENDOR_ST_A_M45PE20:
14731 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14734 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14739 tg3_flag_set(tp, NO_NVRAM);
14743 tg3_nvram_get_pagesize(tp, nvcfg1);
14744 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14745 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14748 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14750 u32 nvcfg1, nvmpinstrp;
14752 nvcfg1 = tr32(NVRAM_CFG1);
14753 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14755 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14756 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14757 tg3_flag_set(tp, NO_NVRAM);
14761 switch (nvmpinstrp) {
14762 case FLASH_5762_EEPROM_HD:
14763 nvmpinstrp = FLASH_5720_EEPROM_HD;
14765 case FLASH_5762_EEPROM_LD:
14766 nvmpinstrp = FLASH_5720_EEPROM_LD;
14768 case FLASH_5720VENDOR_M_ST_M45PE20:
14769 /* This pinstrap supports multiple sizes, so force it
14770 * to read the actual size from location 0xf0.
14772 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14777 switch (nvmpinstrp) {
14778 case FLASH_5720_EEPROM_HD:
14779 case FLASH_5720_EEPROM_LD:
14780 tp->nvram_jedecnum = JEDEC_ATMEL;
14781 tg3_flag_set(tp, NVRAM_BUFFERED);
14783 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14784 tw32(NVRAM_CFG1, nvcfg1);
14785 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14786 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14788 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14790 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14791 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14792 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14793 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14794 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14795 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14796 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14797 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14798 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14799 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14800 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14801 case FLASH_5720VENDOR_ATMEL_45USPT:
14802 tp->nvram_jedecnum = JEDEC_ATMEL;
14803 tg3_flag_set(tp, NVRAM_BUFFERED);
14804 tg3_flag_set(tp, FLASH);
14806 switch (nvmpinstrp) {
14807 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14808 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14809 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14810 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14812 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14813 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14814 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14815 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14817 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14818 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14819 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14822 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14823 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14827 case FLASH_5720VENDOR_M_ST_M25PE10:
14828 case FLASH_5720VENDOR_M_ST_M45PE10:
14829 case FLASH_5720VENDOR_A_ST_M25PE10:
14830 case FLASH_5720VENDOR_A_ST_M45PE10:
14831 case FLASH_5720VENDOR_M_ST_M25PE20:
14832 case FLASH_5720VENDOR_M_ST_M45PE20:
14833 case FLASH_5720VENDOR_A_ST_M25PE20:
14834 case FLASH_5720VENDOR_A_ST_M45PE20:
14835 case FLASH_5720VENDOR_M_ST_M25PE40:
14836 case FLASH_5720VENDOR_M_ST_M45PE40:
14837 case FLASH_5720VENDOR_A_ST_M25PE40:
14838 case FLASH_5720VENDOR_A_ST_M45PE40:
14839 case FLASH_5720VENDOR_M_ST_M25PE80:
14840 case FLASH_5720VENDOR_M_ST_M45PE80:
14841 case FLASH_5720VENDOR_A_ST_M25PE80:
14842 case FLASH_5720VENDOR_A_ST_M45PE80:
14843 case FLASH_5720VENDOR_ST_25USPT:
14844 case FLASH_5720VENDOR_ST_45USPT:
14845 tp->nvram_jedecnum = JEDEC_ST;
14846 tg3_flag_set(tp, NVRAM_BUFFERED);
14847 tg3_flag_set(tp, FLASH);
14849 switch (nvmpinstrp) {
14850 case FLASH_5720VENDOR_M_ST_M25PE20:
14851 case FLASH_5720VENDOR_M_ST_M45PE20:
14852 case FLASH_5720VENDOR_A_ST_M25PE20:
14853 case FLASH_5720VENDOR_A_ST_M45PE20:
14854 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14856 case FLASH_5720VENDOR_M_ST_M25PE40:
14857 case FLASH_5720VENDOR_M_ST_M45PE40:
14858 case FLASH_5720VENDOR_A_ST_M25PE40:
14859 case FLASH_5720VENDOR_A_ST_M45PE40:
14860 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14862 case FLASH_5720VENDOR_M_ST_M25PE80:
14863 case FLASH_5720VENDOR_M_ST_M45PE80:
14864 case FLASH_5720VENDOR_A_ST_M25PE80:
14865 case FLASH_5720VENDOR_A_ST_M45PE80:
14866 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14869 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14870 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14875 tg3_flag_set(tp, NO_NVRAM);
14879 tg3_nvram_get_pagesize(tp, nvcfg1);
14880 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14881 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14883 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14886 if (tg3_nvram_read(tp, 0, &val))
14889 if (val != TG3_EEPROM_MAGIC &&
14890 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14891 tg3_flag_set(tp, NO_NVRAM);
14895 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
14896 static void tg3_nvram_init(struct tg3 *tp)
14898 if (tg3_flag(tp, IS_SSB_CORE)) {
14899 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14900 tg3_flag_clear(tp, NVRAM);
14901 tg3_flag_clear(tp, NVRAM_BUFFERED);
14902 tg3_flag_set(tp, NO_NVRAM);
14906 tw32_f(GRC_EEPROM_ADDR,
14907 (EEPROM_ADDR_FSM_RESET |
14908 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14909 EEPROM_ADDR_CLKPERD_SHIFT)));
14913 /* Enable seeprom accesses. */
14914 tw32_f(GRC_LOCAL_CTRL,
14915 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14918 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14919 tg3_asic_rev(tp) != ASIC_REV_5701) {
14920 tg3_flag_set(tp, NVRAM);
14922 if (tg3_nvram_lock(tp)) {
14923 netdev_warn(tp->dev,
14924 "Cannot get nvram lock, %s failed\n",
14928 tg3_enable_nvram_access(tp);
14930 tp->nvram_size = 0;
14932 if (tg3_asic_rev(tp) == ASIC_REV_5752)
14933 tg3_get_5752_nvram_info(tp);
14934 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
14935 tg3_get_5755_nvram_info(tp);
14936 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14937 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14938 tg3_asic_rev(tp) == ASIC_REV_5785)
14939 tg3_get_5787_nvram_info(tp);
14940 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
14941 tg3_get_5761_nvram_info(tp);
14942 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
14943 tg3_get_5906_nvram_info(tp);
14944 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
14945 tg3_flag(tp, 57765_CLASS))
14946 tg3_get_57780_nvram_info(tp);
14947 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14948 tg3_asic_rev(tp) == ASIC_REV_5719)
14949 tg3_get_5717_nvram_info(tp);
14950 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14951 tg3_asic_rev(tp) == ASIC_REV_5762)
14952 tg3_get_5720_nvram_info(tp);
14954 tg3_get_nvram_info(tp);
14956 if (tp->nvram_size == 0)
14957 tg3_get_nvram_size(tp);
14959 tg3_disable_nvram_access(tp);
14960 tg3_nvram_unlock(tp);
14963 tg3_flag_clear(tp, NVRAM);
14964 tg3_flag_clear(tp, NVRAM_BUFFERED);
14966 tg3_get_eeprom_size(tp);
14970 struct subsys_tbl_ent {
14971 u16 subsys_vendor, subsys_devid;
14975 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
14976 /* Broadcom boards. */
14977 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14978 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
14979 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14980 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
14981 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14982 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
14983 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14984 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14985 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14986 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
14987 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14988 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
14989 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14990 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14991 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14992 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
14993 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14994 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
14995 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14996 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
14997 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14998 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
15001 { TG3PCI_SUBVENDOR_ID_3COM,
15002 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
15003 { TG3PCI_SUBVENDOR_ID_3COM,
15004 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
15005 { TG3PCI_SUBVENDOR_ID_3COM,
15006 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
15007 { TG3PCI_SUBVENDOR_ID_3COM,
15008 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
15009 { TG3PCI_SUBVENDOR_ID_3COM,
15010 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
15013 { TG3PCI_SUBVENDOR_ID_DELL,
15014 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
15015 { TG3PCI_SUBVENDOR_ID_DELL,
15016 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
15017 { TG3PCI_SUBVENDOR_ID_DELL,
15018 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
15019 { TG3PCI_SUBVENDOR_ID_DELL,
15020 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
15022 /* Compaq boards. */
15023 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15024 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
15025 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15026 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
15027 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15028 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
15029 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15030 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
15031 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15032 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
15035 { TG3PCI_SUBVENDOR_ID_IBM,
15036 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
15039 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
15043 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
15044 if ((subsys_id_to_phy_id[i].subsys_vendor ==
15045 tp->pdev->subsystem_vendor) &&
15046 (subsys_id_to_phy_id[i].subsys_devid ==
15047 tp->pdev->subsystem_device))
15048 return &subsys_id_to_phy_id[i];
15053 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
15057 tp->phy_id = TG3_PHY_ID_INVALID;
15058 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15060 /* Assume an onboard device and WOL capable by default. */
15061 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15062 tg3_flag_set(tp, WOL_CAP);
15064 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15065 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
15066 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15067 tg3_flag_set(tp, IS_NIC);
15069 val = tr32(VCPU_CFGSHDW);
15070 if (val & VCPU_CFGSHDW_ASPM_DBNC)
15071 tg3_flag_set(tp, ASPM_WORKAROUND);
15072 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
15073 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
15074 tg3_flag_set(tp, WOL_ENABLE);
15075 device_set_wakeup_enable(&tp->pdev->dev, true);
15080 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15081 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15082 u32 nic_cfg, led_cfg;
15083 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15084 u32 nic_phy_id, ver, eeprom_phy_id;
15085 int eeprom_phy_serdes = 0;
15087 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15088 tp->nic_sram_data_cfg = nic_cfg;
15090 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15091 ver >>= NIC_SRAM_DATA_VER_SHIFT;
15092 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15093 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15094 tg3_asic_rev(tp) != ASIC_REV_5703 &&
15095 (ver > 0) && (ver < 0x100))
15096 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15098 if (tg3_asic_rev(tp) == ASIC_REV_5785)
15099 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15101 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15102 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15103 tg3_asic_rev(tp) == ASIC_REV_5720)
15104 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15106 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15107 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15108 eeprom_phy_serdes = 1;
15110 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15111 if (nic_phy_id != 0) {
15112 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15113 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15115 eeprom_phy_id = (id1 >> 16) << 10;
15116 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15117 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15121 tp->phy_id = eeprom_phy_id;
15122 if (eeprom_phy_serdes) {
15123 if (!tg3_flag(tp, 5705_PLUS))
15124 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15126 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
15129 if (tg3_flag(tp, 5750_PLUS))
15130 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15131 SHASTA_EXT_LED_MODE_MASK);
15133 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15137 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15138 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15141 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15142 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15145 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15146 tp->led_ctrl = LED_CTRL_MODE_MAC;
15148 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15149 * read on some older 5700/5701 bootcode.
15151 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15152 tg3_asic_rev(tp) == ASIC_REV_5701)
15153 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15157 case SHASTA_EXT_LED_SHARED:
15158 tp->led_ctrl = LED_CTRL_MODE_SHARED;
15159 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15160 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
15161 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15162 LED_CTRL_MODE_PHY_2);
15164 if (tg3_flag(tp, 5717_PLUS) ||
15165 tg3_asic_rev(tp) == ASIC_REV_5762)
15166 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15167 LED_CTRL_BLINK_RATE_MASK;
15171 case SHASTA_EXT_LED_MAC:
15172 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15175 case SHASTA_EXT_LED_COMBO:
15176 tp->led_ctrl = LED_CTRL_MODE_COMBO;
15177 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
15178 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15179 LED_CTRL_MODE_PHY_2);
15184 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15185 tg3_asic_rev(tp) == ASIC_REV_5701) &&
15186 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15187 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15189 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
15190 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15192 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
15193 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15194 if ((tp->pdev->subsystem_vendor ==
15195 PCI_VENDOR_ID_ARIMA) &&
15196 (tp->pdev->subsystem_device == 0x205a ||
15197 tp->pdev->subsystem_device == 0x2063))
15198 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15200 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15201 tg3_flag_set(tp, IS_NIC);
15204 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
15205 tg3_flag_set(tp, ENABLE_ASF);
15206 if (tg3_flag(tp, 5750_PLUS))
15207 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
15210 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
15211 tg3_flag(tp, 5750_PLUS))
15212 tg3_flag_set(tp, ENABLE_APE);
15214 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
15215 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
15216 tg3_flag_clear(tp, WOL_CAP);
15218 if (tg3_flag(tp, WOL_CAP) &&
15219 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
15220 tg3_flag_set(tp, WOL_ENABLE);
15221 device_set_wakeup_enable(&tp->pdev->dev, true);
15224 if (cfg2 & (1 << 17))
15225 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
15227 /* serdes signal pre-emphasis in register 0x590 set by */
15228 /* bootcode if bit 18 is set */
15229 if (cfg2 & (1 << 18))
15230 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
15232 if ((tg3_flag(tp, 57765_PLUS) ||
15233 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15234 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
15235 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
15236 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
15238 if (tg3_flag(tp, PCI_EXPRESS)) {
15241 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
15242 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15243 !tg3_flag(tp, 57765_PLUS) &&
15244 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
15245 tg3_flag_set(tp, ASPM_WORKAROUND);
15246 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15247 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15248 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15249 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
15252 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
15253 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
15254 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
15255 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
15256 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
15257 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
15259 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15260 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
15263 if (tg3_flag(tp, WOL_CAP))
15264 device_set_wakeup_enable(&tp->pdev->dev,
15265 tg3_flag(tp, WOL_ENABLE));
15267 device_set_wakeup_capable(&tp->pdev->dev, false);
15270 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15273 u32 val2, off = offset * 8;
15275 err = tg3_nvram_lock(tp);
15279 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15280 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15281 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15282 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15285 for (i = 0; i < 100; i++) {
15286 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15287 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15288 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15294 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15296 tg3_nvram_unlock(tp);
15297 if (val2 & APE_OTP_STATUS_CMD_DONE)
15303 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
15308 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15309 tw32(OTP_CTRL, cmd);
15311 /* Wait for up to 1 ms for command to execute. */
15312 for (i = 0; i < 100; i++) {
15313 val = tr32(OTP_STATUS);
15314 if (val & OTP_STATUS_CMD_DONE)
15319 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15322 /* Read the gphy configuration from the OTP region of the chip. The gphy
15323 * configuration is a 32-bit value that straddles the alignment boundary.
15324 * We do two 32-bit reads and then shift and merge the results.
15326 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
15328 u32 bhalf_otp, thalf_otp;
15330 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15332 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15335 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15337 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15340 thalf_otp = tr32(OTP_READ_DATA);
15342 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15344 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15347 bhalf_otp = tr32(OTP_READ_DATA);
15349 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15352 static void tg3_phy_init_link_config(struct tg3 *tp)
15354 u32 adv = ADVERTISED_Autoneg;
15356 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15357 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15358 adv |= ADVERTISED_1000baseT_Half;
15359 adv |= ADVERTISED_1000baseT_Full;
15362 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15363 adv |= ADVERTISED_100baseT_Half |
15364 ADVERTISED_100baseT_Full |
15365 ADVERTISED_10baseT_Half |
15366 ADVERTISED_10baseT_Full |
15369 adv |= ADVERTISED_FIBRE;
15371 tp->link_config.advertising = adv;
15372 tp->link_config.speed = SPEED_UNKNOWN;
15373 tp->link_config.duplex = DUPLEX_UNKNOWN;
15374 tp->link_config.autoneg = AUTONEG_ENABLE;
15375 tp->link_config.active_speed = SPEED_UNKNOWN;
15376 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
15381 static int tg3_phy_probe(struct tg3 *tp)
15383 u32 hw_phy_id_1, hw_phy_id_2;
15384 u32 hw_phy_id, hw_phy_id_masked;
15387 /* flow control autonegotiation is default behavior */
15388 tg3_flag_set(tp, PAUSE_AUTONEG);
15389 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15391 if (tg3_flag(tp, ENABLE_APE)) {
15392 switch (tp->pci_fn) {
15394 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15397 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15400 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15403 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15408 if (!tg3_flag(tp, ENABLE_ASF) &&
15409 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15410 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15411 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15412 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15414 if (tg3_flag(tp, USE_PHYLIB))
15415 return tg3_phy_init(tp);
15417 /* Reading the PHY ID register can conflict with ASF
15418 * firmware access to the PHY hardware.
15421 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
15422 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
15424 /* Now read the physical PHY_ID from the chip and verify
15425 * that it is sane. If it doesn't look good, we fall back
15426 * to either the hard-coded table based PHY_ID and failing
15427 * that the value found in the eeprom area.
15429 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15430 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15432 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15433 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15434 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15436 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
15439 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
15440 tp->phy_id = hw_phy_id;
15441 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
15442 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15444 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
15446 if (tp->phy_id != TG3_PHY_ID_INVALID) {
15447 /* Do nothing, phy ID already set up in
15448 * tg3_get_eeprom_hw_cfg().
15451 struct subsys_tbl_ent *p;
15453 /* No eeprom signature? Try the hardcoded
15454 * subsys device table.
15456 p = tg3_lookup_by_subsys(tp);
15458 tp->phy_id = p->phy_id;
15459 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15460 /* For now we saw the IDs 0xbc050cd0,
15461 * 0xbc050f80 and 0xbc050c30 on devices
15462 * connected to an BCM4785 and there are
15463 * probably more. Just assume that the phy is
15464 * supported when it is connected to a SSB core
15471 tp->phy_id == TG3_PHY_ID_BCM8002)
15472 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15476 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15477 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15478 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15479 tg3_asic_rev(tp) == ASIC_REV_57766 ||
15480 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15481 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15482 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15483 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
15484 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
15485 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15487 tp->eee.supported = SUPPORTED_100baseT_Full |
15488 SUPPORTED_1000baseT_Full;
15489 tp->eee.advertised = ADVERTISED_100baseT_Full |
15490 ADVERTISED_1000baseT_Full;
15491 tp->eee.eee_enabled = 1;
15492 tp->eee.tx_lpi_enabled = 1;
15493 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15496 tg3_phy_init_link_config(tp);
15498 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15499 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15500 !tg3_flag(tp, ENABLE_APE) &&
15501 !tg3_flag(tp, ENABLE_ASF)) {
15504 tg3_readphy(tp, MII_BMSR, &bmsr);
15505 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15506 (bmsr & BMSR_LSTATUS))
15507 goto skip_phy_reset;
15509 err = tg3_phy_reset(tp);
15513 tg3_phy_set_wirespeed(tp);
15515 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
15516 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15517 tp->link_config.flowctrl);
15519 tg3_writephy(tp, MII_BMCR,
15520 BMCR_ANENABLE | BMCR_ANRESTART);
15525 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
15526 err = tg3_init_5401phy_dsp(tp);
15530 err = tg3_init_5401phy_dsp(tp);
15536 static void tg3_read_vpd(struct tg3 *tp)
15539 unsigned int block_end, rosize, len;
15543 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
15547 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
15549 goto out_not_found;
15551 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15552 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15553 i += PCI_VPD_LRDT_TAG_SIZE;
15555 if (block_end > vpdlen)
15556 goto out_not_found;
15558 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15559 PCI_VPD_RO_KEYWORD_MFR_ID);
15561 len = pci_vpd_info_field_size(&vpd_data[j]);
15563 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15564 if (j + len > block_end || len != 4 ||
15565 memcmp(&vpd_data[j], "1028", 4))
15568 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15569 PCI_VPD_RO_KEYWORD_VENDOR0);
15573 len = pci_vpd_info_field_size(&vpd_data[j]);
15575 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15576 if (j + len > block_end)
15579 if (len >= sizeof(tp->fw_ver))
15580 len = sizeof(tp->fw_ver) - 1;
15581 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15582 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15587 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15588 PCI_VPD_RO_KEYWORD_PARTNO);
15590 goto out_not_found;
15592 len = pci_vpd_info_field_size(&vpd_data[i]);
15594 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15595 if (len > TG3_BPN_SIZE ||
15596 (len + i) > vpdlen)
15597 goto out_not_found;
15599 memcpy(tp->board_part_number, &vpd_data[i], len);
15603 if (tp->board_part_number[0])
15607 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15608 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15609 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15610 strcpy(tp->board_part_number, "BCM5717");
15611 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15612 strcpy(tp->board_part_number, "BCM5718");
15615 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15616 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15617 strcpy(tp->board_part_number, "BCM57780");
15618 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15619 strcpy(tp->board_part_number, "BCM57760");
15620 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15621 strcpy(tp->board_part_number, "BCM57790");
15622 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15623 strcpy(tp->board_part_number, "BCM57788");
15626 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15627 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15628 strcpy(tp->board_part_number, "BCM57761");
15629 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15630 strcpy(tp->board_part_number, "BCM57765");
15631 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15632 strcpy(tp->board_part_number, "BCM57781");
15633 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15634 strcpy(tp->board_part_number, "BCM57785");
15635 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15636 strcpy(tp->board_part_number, "BCM57791");
15637 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15638 strcpy(tp->board_part_number, "BCM57795");
15641 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15642 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15643 strcpy(tp->board_part_number, "BCM57762");
15644 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15645 strcpy(tp->board_part_number, "BCM57766");
15646 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15647 strcpy(tp->board_part_number, "BCM57782");
15648 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15649 strcpy(tp->board_part_number, "BCM57786");
15652 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15653 strcpy(tp->board_part_number, "BCM95906");
15656 strcpy(tp->board_part_number, "none");
15660 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15664 if (tg3_nvram_read(tp, offset, &val) ||
15665 (val & 0xfc000000) != 0x0c000000 ||
15666 tg3_nvram_read(tp, offset + 4, &val) ||
15673 static void tg3_read_bc_ver(struct tg3 *tp)
15675 u32 val, offset, start, ver_offset;
15677 bool newver = false;
15679 if (tg3_nvram_read(tp, 0xc, &offset) ||
15680 tg3_nvram_read(tp, 0x4, &start))
15683 offset = tg3_nvram_logical_addr(tp, offset);
15685 if (tg3_nvram_read(tp, offset, &val))
15688 if ((val & 0xfc000000) == 0x0c000000) {
15689 if (tg3_nvram_read(tp, offset + 4, &val))
15696 dst_off = strlen(tp->fw_ver);
15699 if (TG3_VER_SIZE - dst_off < 16 ||
15700 tg3_nvram_read(tp, offset + 8, &ver_offset))
15703 offset = offset + ver_offset - start;
15704 for (i = 0; i < 16; i += 4) {
15706 if (tg3_nvram_read_be32(tp, offset + i, &v))
15709 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15714 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15717 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15718 TG3_NVM_BCVER_MAJSFT;
15719 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
15720 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15721 "v%d.%02d", major, minor);
15725 static void tg3_read_hwsb_ver(struct tg3 *tp)
15727 u32 val, major, minor;
15729 /* Use native endian representation */
15730 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15733 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15734 TG3_NVM_HWSB_CFG1_MAJSFT;
15735 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15736 TG3_NVM_HWSB_CFG1_MINSFT;
15738 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15741 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15743 u32 offset, major, minor, build;
15745 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15747 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15750 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15751 case TG3_EEPROM_SB_REVISION_0:
15752 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15754 case TG3_EEPROM_SB_REVISION_2:
15755 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15757 case TG3_EEPROM_SB_REVISION_3:
15758 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15760 case TG3_EEPROM_SB_REVISION_4:
15761 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15763 case TG3_EEPROM_SB_REVISION_5:
15764 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15766 case TG3_EEPROM_SB_REVISION_6:
15767 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15773 if (tg3_nvram_read(tp, offset, &val))
15776 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15777 TG3_EEPROM_SB_EDH_BLD_SHFT;
15778 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15779 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15780 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15782 if (minor > 99 || build > 26)
15785 offset = strlen(tp->fw_ver);
15786 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15787 " v%d.%02d", major, minor);
15790 offset = strlen(tp->fw_ver);
15791 if (offset < TG3_VER_SIZE - 1)
15792 tp->fw_ver[offset] = 'a' + build - 1;
15796 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15798 u32 val, offset, start;
15801 for (offset = TG3_NVM_DIR_START;
15802 offset < TG3_NVM_DIR_END;
15803 offset += TG3_NVM_DIRENT_SIZE) {
15804 if (tg3_nvram_read(tp, offset, &val))
15807 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15811 if (offset == TG3_NVM_DIR_END)
15814 if (!tg3_flag(tp, 5705_PLUS))
15815 start = 0x08000000;
15816 else if (tg3_nvram_read(tp, offset - 4, &start))
15819 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15820 !tg3_fw_img_is_valid(tp, offset) ||
15821 tg3_nvram_read(tp, offset + 8, &val))
15824 offset += val - start;
15826 vlen = strlen(tp->fw_ver);
15828 tp->fw_ver[vlen++] = ',';
15829 tp->fw_ver[vlen++] = ' ';
15831 for (i = 0; i < 4; i++) {
15833 if (tg3_nvram_read_be32(tp, offset, &v))
15836 offset += sizeof(v);
15838 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15839 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15843 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15848 static void tg3_probe_ncsi(struct tg3 *tp)
15852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15853 if (apedata != APE_SEG_SIG_MAGIC)
15856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15857 if (!(apedata & APE_FW_STATUS_READY))
15860 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15861 tg3_flag_set(tp, APE_HAS_NCSI);
15864 static void tg3_read_dash_ver(struct tg3 *tp)
15870 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15872 if (tg3_flag(tp, APE_HAS_NCSI))
15874 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15879 vlen = strlen(tp->fw_ver);
15881 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15883 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15884 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15885 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15886 (apedata & APE_FW_VERSION_BLDMSK));
15889 static void tg3_read_otp_ver(struct tg3 *tp)
15893 if (tg3_asic_rev(tp) != ASIC_REV_5762)
15896 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15897 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15898 TG3_OTP_MAGIC0_VALID(val)) {
15899 u64 val64 = (u64) val << 32 | val2;
15903 for (i = 0; i < 7; i++) {
15904 if ((val64 & 0xff) == 0)
15906 ver = val64 & 0xff;
15909 vlen = strlen(tp->fw_ver);
15910 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15914 static void tg3_read_fw_ver(struct tg3 *tp)
15917 bool vpd_vers = false;
15919 if (tp->fw_ver[0] != 0)
15922 if (tg3_flag(tp, NO_NVRAM)) {
15923 strcat(tp->fw_ver, "sb");
15924 tg3_read_otp_ver(tp);
15928 if (tg3_nvram_read(tp, 0, &val))
15931 if (val == TG3_EEPROM_MAGIC)
15932 tg3_read_bc_ver(tp);
15933 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15934 tg3_read_sb_ver(tp, val);
15935 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15936 tg3_read_hwsb_ver(tp);
15938 if (tg3_flag(tp, ENABLE_ASF)) {
15939 if (tg3_flag(tp, ENABLE_APE)) {
15940 tg3_probe_ncsi(tp);
15942 tg3_read_dash_ver(tp);
15943 } else if (!vpd_vers) {
15944 tg3_read_mgmtfw_ver(tp);
15948 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
15951 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15953 if (tg3_flag(tp, LRG_PROD_RING_CAP))
15954 return TG3_RX_RET_MAX_SIZE_5717;
15955 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
15956 return TG3_RX_RET_MAX_SIZE_5700;
15958 return TG3_RX_RET_MAX_SIZE_5705;
15961 static const struct pci_device_id tg3_write_reorder_chipsets[] = {
15962 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15963 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15964 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15968 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
15970 struct pci_dev *peer;
15971 unsigned int func, devnr = tp->pdev->devfn & ~7;
15973 for (func = 0; func < 8; func++) {
15974 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15975 if (peer && peer != tp->pdev)
15979 /* 5704 can be configured in single-port mode, set peer to
15980 * tp->pdev in that case.
15988 * We don't need to keep the refcount elevated; there's no way
15989 * to remove one half of this device without removing the other
15996 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
15998 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
15999 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
16002 /* All devices that use the alternate
16003 * ASIC REV location have a CPMU.
16005 tg3_flag_set(tp, CPMU_PRESENT);
16007 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
16008 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
16009 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
16010 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
16011 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
16012 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
16013 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
16014 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
16015 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
16016 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
16017 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
16018 reg = TG3PCI_GEN2_PRODID_ASICREV;
16019 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
16020 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
16021 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
16022 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
16023 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
16024 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
16025 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
16026 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
16027 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
16028 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
16029 reg = TG3PCI_GEN15_PRODID_ASICREV;
16031 reg = TG3PCI_PRODID_ASICREV;
16033 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
16036 /* Wrong chip ID in 5752 A0. This code can be removed later
16037 * as A0 is not in production.
16039 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
16040 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
16042 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
16043 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
16045 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16046 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16047 tg3_asic_rev(tp) == ASIC_REV_5720)
16048 tg3_flag_set(tp, 5717_PLUS);
16050 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
16051 tg3_asic_rev(tp) == ASIC_REV_57766)
16052 tg3_flag_set(tp, 57765_CLASS);
16054 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
16055 tg3_asic_rev(tp) == ASIC_REV_5762)
16056 tg3_flag_set(tp, 57765_PLUS);
16058 /* Intentionally exclude ASIC_REV_5906 */
16059 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16060 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16061 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16062 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16063 tg3_asic_rev(tp) == ASIC_REV_5785 ||
16064 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16065 tg3_flag(tp, 57765_PLUS))
16066 tg3_flag_set(tp, 5755_PLUS);
16068 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
16069 tg3_asic_rev(tp) == ASIC_REV_5714)
16070 tg3_flag_set(tp, 5780_CLASS);
16072 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16073 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16074 tg3_asic_rev(tp) == ASIC_REV_5906 ||
16075 tg3_flag(tp, 5755_PLUS) ||
16076 tg3_flag(tp, 5780_CLASS))
16077 tg3_flag_set(tp, 5750_PLUS);
16079 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16080 tg3_flag(tp, 5750_PLUS))
16081 tg3_flag_set(tp, 5705_PLUS);
16084 static bool tg3_10_100_only_device(struct tg3 *tp,
16085 const struct pci_device_id *ent)
16087 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16089 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16090 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
16091 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16094 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
16095 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
16096 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16106 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
16109 u32 pci_state_reg, grc_misc_cfg;
16114 /* Force memory write invalidate off. If we leave it on,
16115 * then on 5700_BX chips we have to enable a workaround.
16116 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16117 * to match the cacheline size. The Broadcom driver have this
16118 * workaround but turns MWI off all the times so never uses
16119 * it. This seems to suggest that the workaround is insufficient.
16121 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16122 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16123 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16125 /* Important! -- Make sure register accesses are byteswapped
16126 * correctly. Also, for those chips that require it, make
16127 * sure that indirect register accesses are enabled before
16128 * the first operation.
16130 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16132 tp->misc_host_ctrl |= (misc_ctrl_reg &
16133 MISC_HOST_CTRL_CHIPREV);
16134 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16135 tp->misc_host_ctrl);
16137 tg3_detect_asic_rev(tp, misc_ctrl_reg);
16139 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16140 * we need to disable memory and use config. cycles
16141 * only to access all registers. The 5702/03 chips
16142 * can mistakenly decode the special cycles from the
16143 * ICH chipsets as memory write cycles, causing corruption
16144 * of register and memory space. Only certain ICH bridges
16145 * will drive special cycles with non-zero data during the
16146 * address phase which can fall within the 5703's address
16147 * range. This is not an ICH bug as the PCI spec allows
16148 * non-zero address during special cycles. However, only
16149 * these ICH bridges are known to drive non-zero addresses
16150 * during special cycles.
16152 * Since special cycles do not cross PCI bridges, we only
16153 * enable this workaround if the 5703 is on the secondary
16154 * bus of these ICH bridges.
16156 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16157 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
16158 static struct tg3_dev_id {
16162 } ich_chipsets[] = {
16163 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16165 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16167 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16169 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16173 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16174 struct pci_dev *bridge = NULL;
16176 while (pci_id->vendor != 0) {
16177 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16183 if (pci_id->rev != PCI_ANY_ID) {
16184 if (bridge->revision > pci_id->rev)
16187 if (bridge->subordinate &&
16188 (bridge->subordinate->number ==
16189 tp->pdev->bus->number)) {
16190 tg3_flag_set(tp, ICH_WORKAROUND);
16191 pci_dev_put(bridge);
16197 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
16198 static struct tg3_dev_id {
16201 } bridge_chipsets[] = {
16202 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16203 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16206 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16207 struct pci_dev *bridge = NULL;
16209 while (pci_id->vendor != 0) {
16210 bridge = pci_get_device(pci_id->vendor,
16217 if (bridge->subordinate &&
16218 (bridge->subordinate->number <=
16219 tp->pdev->bus->number) &&
16220 (bridge->subordinate->busn_res.end >=
16221 tp->pdev->bus->number)) {
16222 tg3_flag_set(tp, 5701_DMA_BUG);
16223 pci_dev_put(bridge);
16229 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16230 * DMA addresses > 40-bit. This bridge may have other additional
16231 * 57xx devices behind it in some 4-port NIC designs for example.
16232 * Any tg3 device found behind the bridge will also need the 40-bit
16235 if (tg3_flag(tp, 5780_CLASS)) {
16236 tg3_flag_set(tp, 40BIT_DMA_BUG);
16237 tp->msi_cap = tp->pdev->msi_cap;
16239 struct pci_dev *bridge = NULL;
16242 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16243 PCI_DEVICE_ID_SERVERWORKS_EPB,
16245 if (bridge && bridge->subordinate &&
16246 (bridge->subordinate->number <=
16247 tp->pdev->bus->number) &&
16248 (bridge->subordinate->busn_res.end >=
16249 tp->pdev->bus->number)) {
16250 tg3_flag_set(tp, 40BIT_DMA_BUG);
16251 pci_dev_put(bridge);
16257 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16258 tg3_asic_rev(tp) == ASIC_REV_5714)
16259 tp->pdev_peer = tg3_find_peer(tp);
16261 /* Determine TSO capabilities */
16262 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
16263 ; /* Do nothing. HW bug. */
16264 else if (tg3_flag(tp, 57765_PLUS))
16265 tg3_flag_set(tp, HW_TSO_3);
16266 else if (tg3_flag(tp, 5755_PLUS) ||
16267 tg3_asic_rev(tp) == ASIC_REV_5906)
16268 tg3_flag_set(tp, HW_TSO_2);
16269 else if (tg3_flag(tp, 5750_PLUS)) {
16270 tg3_flag_set(tp, HW_TSO_1);
16271 tg3_flag_set(tp, TSO_BUG);
16272 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16273 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
16274 tg3_flag_clear(tp, TSO_BUG);
16275 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16276 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16277 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
16278 tg3_flag_set(tp, FW_TSO);
16279 tg3_flag_set(tp, TSO_BUG);
16280 if (tg3_asic_rev(tp) == ASIC_REV_5705)
16281 tp->fw_needed = FIRMWARE_TG3TSO5;
16283 tp->fw_needed = FIRMWARE_TG3TSO;
16286 /* Selectively allow TSO based on operating conditions */
16287 if (tg3_flag(tp, HW_TSO_1) ||
16288 tg3_flag(tp, HW_TSO_2) ||
16289 tg3_flag(tp, HW_TSO_3) ||
16290 tg3_flag(tp, FW_TSO)) {
16291 /* For firmware TSO, assume ASF is disabled.
16292 * We'll disable TSO later if we discover ASF
16293 * is enabled in tg3_get_eeprom_hw_cfg().
16295 tg3_flag_set(tp, TSO_CAPABLE);
16297 tg3_flag_clear(tp, TSO_CAPABLE);
16298 tg3_flag_clear(tp, TSO_BUG);
16299 tp->fw_needed = NULL;
16302 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
16303 tp->fw_needed = FIRMWARE_TG3;
16305 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16306 tp->fw_needed = FIRMWARE_TG357766;
16310 if (tg3_flag(tp, 5750_PLUS)) {
16311 tg3_flag_set(tp, SUPPORT_MSI);
16312 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16313 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16314 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16315 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
16316 tp->pdev_peer == tp->pdev))
16317 tg3_flag_clear(tp, SUPPORT_MSI);
16319 if (tg3_flag(tp, 5755_PLUS) ||
16320 tg3_asic_rev(tp) == ASIC_REV_5906) {
16321 tg3_flag_set(tp, 1SHOT_MSI);
16324 if (tg3_flag(tp, 57765_PLUS)) {
16325 tg3_flag_set(tp, SUPPORT_MSIX);
16326 tp->irq_max = TG3_IRQ_MAX_VECS;
16332 if (tp->irq_max > 1) {
16333 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16334 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16336 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16337 tg3_asic_rev(tp) == ASIC_REV_5720)
16338 tp->txq_max = tp->irq_max - 1;
16341 if (tg3_flag(tp, 5755_PLUS) ||
16342 tg3_asic_rev(tp) == ASIC_REV_5906)
16343 tg3_flag_set(tp, SHORT_DMA_BUG);
16345 if (tg3_asic_rev(tp) == ASIC_REV_5719)
16346 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
16348 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16349 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16350 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16351 tg3_asic_rev(tp) == ASIC_REV_5762)
16352 tg3_flag_set(tp, LRG_PROD_RING_CAP);
16354 if (tg3_flag(tp, 57765_PLUS) &&
16355 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
16356 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
16358 if (!tg3_flag(tp, 5705_PLUS) ||
16359 tg3_flag(tp, 5780_CLASS) ||
16360 tg3_flag(tp, USE_JUMBO_BDFLAG))
16361 tg3_flag_set(tp, JUMBO_CAPABLE);
16363 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16366 if (pci_is_pcie(tp->pdev)) {
16369 tg3_flag_set(tp, PCI_EXPRESS);
16371 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
16372 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
16373 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16374 tg3_flag_clear(tp, HW_TSO_2);
16375 tg3_flag_clear(tp, TSO_CAPABLE);
16377 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16378 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16379 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16380 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
16381 tg3_flag_set(tp, CLKREQ_BUG);
16382 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
16383 tg3_flag_set(tp, L1PLLPD_EN);
16385 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
16386 /* BCM5785 devices are effectively PCIe devices, and should
16387 * follow PCIe codepaths, but do not have a PCIe capabilities
16390 tg3_flag_set(tp, PCI_EXPRESS);
16391 } else if (!tg3_flag(tp, 5705_PLUS) ||
16392 tg3_flag(tp, 5780_CLASS)) {
16393 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16394 if (!tp->pcix_cap) {
16395 dev_err(&tp->pdev->dev,
16396 "Cannot find PCI-X capability, aborting\n");
16400 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
16401 tg3_flag_set(tp, PCIX_MODE);
16404 /* If we have an AMD 762 or VIA K8T800 chipset, write
16405 * reordering to the mailbox registers done by the host
16406 * controller can cause major troubles. We read back from
16407 * every mailbox register write to force the writes to be
16408 * posted to the chip in order.
16410 if (pci_dev_present(tg3_write_reorder_chipsets) &&
16411 !tg3_flag(tp, PCI_EXPRESS))
16412 tg3_flag_set(tp, MBOX_WRITE_REORDER);
16414 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16415 &tp->pci_cacheline_sz);
16416 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16417 &tp->pci_lat_timer);
16418 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
16419 tp->pci_lat_timer < 64) {
16420 tp->pci_lat_timer = 64;
16421 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16422 tp->pci_lat_timer);
16425 /* Important! -- It is critical that the PCI-X hw workaround
16426 * situation is decided before the first MMIO register access.
16428 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
16429 /* 5700 BX chips need to have their TX producer index
16430 * mailboxes written twice to workaround a bug.
16432 tg3_flag_set(tp, TXD_MBOX_HWBUG);
16434 /* If we are in PCI-X mode, enable register write workaround.
16436 * The workaround is to use indirect register accesses
16437 * for all chip writes not to mailbox registers.
16439 if (tg3_flag(tp, PCIX_MODE)) {
16442 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16444 /* The chip can have it's power management PCI config
16445 * space registers clobbered due to this bug.
16446 * So explicitly force the chip into D0 here.
16448 pci_read_config_dword(tp->pdev,
16449 tp->pdev->pm_cap + PCI_PM_CTRL,
16451 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16452 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
16453 pci_write_config_dword(tp->pdev,
16454 tp->pdev->pm_cap + PCI_PM_CTRL,
16457 /* Also, force SERR#/PERR# in PCI command. */
16458 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16459 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16460 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16464 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
16465 tg3_flag_set(tp, PCI_HIGH_SPEED);
16466 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
16467 tg3_flag_set(tp, PCI_32BIT);
16469 /* Chip-specific fixup from Broadcom driver */
16470 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
16471 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16472 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16473 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16476 /* Default fast path register access methods */
16477 tp->read32 = tg3_read32;
16478 tp->write32 = tg3_write32;
16479 tp->read32_mbox = tg3_read32;
16480 tp->write32_mbox = tg3_write32;
16481 tp->write32_tx_mbox = tg3_write32;
16482 tp->write32_rx_mbox = tg3_write32;
16484 /* Various workaround register access methods */
16485 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
16486 tp->write32 = tg3_write_indirect_reg32;
16487 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
16488 (tg3_flag(tp, PCI_EXPRESS) &&
16489 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
16491 * Back to back register writes can cause problems on these
16492 * chips, the workaround is to read back all reg writes
16493 * except those to mailbox regs.
16495 * See tg3_write_indirect_reg32().
16497 tp->write32 = tg3_write_flush_reg32;
16500 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
16501 tp->write32_tx_mbox = tg3_write32_tx_mbox;
16502 if (tg3_flag(tp, MBOX_WRITE_REORDER))
16503 tp->write32_rx_mbox = tg3_write_flush_reg32;
16506 if (tg3_flag(tp, ICH_WORKAROUND)) {
16507 tp->read32 = tg3_read_indirect_reg32;
16508 tp->write32 = tg3_write_indirect_reg32;
16509 tp->read32_mbox = tg3_read_indirect_mbox;
16510 tp->write32_mbox = tg3_write_indirect_mbox;
16511 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16512 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16517 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16518 pci_cmd &= ~PCI_COMMAND_MEMORY;
16519 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16521 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16522 tp->read32_mbox = tg3_read32_mbox_5906;
16523 tp->write32_mbox = tg3_write32_mbox_5906;
16524 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16525 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16528 if (tp->write32 == tg3_write_indirect_reg32 ||
16529 (tg3_flag(tp, PCIX_MODE) &&
16530 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16531 tg3_asic_rev(tp) == ASIC_REV_5701)))
16532 tg3_flag_set(tp, SRAM_USE_CONFIG);
16534 /* The memory arbiter has to be enabled in order for SRAM accesses
16535 * to succeed. Normally on powerup the tg3 chip firmware will make
16536 * sure it is enabled, but other entities such as system netboot
16537 * code might disable it.
16539 val = tr32(MEMARB_MODE);
16540 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16542 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
16543 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16544 tg3_flag(tp, 5780_CLASS)) {
16545 if (tg3_flag(tp, PCIX_MODE)) {
16546 pci_read_config_dword(tp->pdev,
16547 tp->pcix_cap + PCI_X_STATUS,
16549 tp->pci_fn = val & 0x7;
16551 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16552 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16553 tg3_asic_rev(tp) == ASIC_REV_5720) {
16554 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16555 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16556 val = tr32(TG3_CPMU_STATUS);
16558 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16559 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16561 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16562 TG3_CPMU_STATUS_FSHFT_5719;
16565 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16566 tp->write32_tx_mbox = tg3_write_flush_reg32;
16567 tp->write32_rx_mbox = tg3_write_flush_reg32;
16570 /* Get eeprom hw config before calling tg3_set_power_state().
16571 * In particular, the TG3_FLAG_IS_NIC flag must be
16572 * determined before calling tg3_set_power_state() so that
16573 * we know whether or not to switch out of Vaux power.
16574 * When the flag is set, it means that GPIO1 is used for eeprom
16575 * write protect and also implies that it is a LOM where GPIOs
16576 * are not used to switch power.
16578 tg3_get_eeprom_hw_cfg(tp);
16580 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16581 tg3_flag_clear(tp, TSO_CAPABLE);
16582 tg3_flag_clear(tp, TSO_BUG);
16583 tp->fw_needed = NULL;
16586 if (tg3_flag(tp, ENABLE_APE)) {
16587 /* Allow reads and writes to the
16588 * APE register and memory space.
16590 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
16591 PCISTATE_ALLOW_APE_SHMEM_WR |
16592 PCISTATE_ALLOW_APE_PSPACE_WR;
16593 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16596 tg3_ape_lock_init(tp);
16599 /* Set up tp->grc_local_ctrl before calling
16600 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16601 * will bring 5700's external PHY out of reset.
16602 * It is also used as eeprom write protect on LOMs.
16604 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16605 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16606 tg3_flag(tp, EEPROM_WRITE_PROT))
16607 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16608 GRC_LCLCTRL_GPIO_OUTPUT1);
16609 /* Unused GPIO3 must be driven as output on 5752 because there
16610 * are no pull-up resistors on unused GPIO pins.
16612 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16613 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16615 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16616 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16617 tg3_flag(tp, 57765_CLASS))
16618 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16620 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16621 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16622 /* Turn off the debug UART. */
16623 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16624 if (tg3_flag(tp, IS_NIC))
16625 /* Keep VMain power. */
16626 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16627 GRC_LCLCTRL_GPIO_OUTPUT0;
16630 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16631 tp->grc_local_ctrl |=
16632 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16634 /* Switch out of Vaux if it is a NIC */
16635 tg3_pwrsrc_switch_to_vmain(tp);
16637 /* Derive initial jumbo mode from MTU assigned in
16638 * ether_setup() via the alloc_etherdev() call
16640 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16641 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16643 /* Determine WakeOnLan speed to use. */
16644 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16645 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16646 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16647 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16648 tg3_flag_clear(tp, WOL_SPEED_100MB);
16650 tg3_flag_set(tp, WOL_SPEED_100MB);
16653 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16654 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16656 /* A few boards don't want Ethernet@WireSpeed phy feature */
16657 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16658 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16659 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16660 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16661 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16662 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16663 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16665 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16666 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16667 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16668 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16669 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16671 if (tg3_flag(tp, 5705_PLUS) &&
16672 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16673 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16674 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16675 !tg3_flag(tp, 57765_PLUS)) {
16676 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16677 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16678 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16679 tg3_asic_rev(tp) == ASIC_REV_5761) {
16680 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16681 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16682 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16683 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16684 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16686 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16689 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16690 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16691 tp->phy_otp = tg3_read_otp_phycfg(tp);
16692 if (tp->phy_otp == 0)
16693 tp->phy_otp = TG3_OTP_DEFAULT;
16696 if (tg3_flag(tp, CPMU_PRESENT))
16697 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16699 tp->mi_mode = MAC_MI_MODE_BASE;
16701 tp->coalesce_mode = 0;
16702 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16703 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16704 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16706 /* Set these bits to enable statistics workaround. */
16707 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16708 tg3_asic_rev(tp) == ASIC_REV_5762 ||
16709 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16710 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16711 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16712 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16715 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16716 tg3_asic_rev(tp) == ASIC_REV_57780)
16717 tg3_flag_set(tp, USE_PHYLIB);
16719 err = tg3_mdio_init(tp);
16723 /* Initialize data/descriptor byte/word swapping. */
16724 val = tr32(GRC_MODE);
16725 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16726 tg3_asic_rev(tp) == ASIC_REV_5762)
16727 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16728 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16729 GRC_MODE_B2HRX_ENABLE |
16730 GRC_MODE_HTX2B_ENABLE |
16731 GRC_MODE_HOST_STACKUP);
16733 val &= GRC_MODE_HOST_STACKUP;
16735 tw32(GRC_MODE, val | tp->grc_mode);
16737 tg3_switch_clocks(tp);
16739 /* Clear this out for sanity. */
16740 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16742 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16743 tw32(TG3PCI_REG_BASE_ADDR, 0);
16745 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16747 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
16748 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16749 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16750 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16751 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16752 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16753 void __iomem *sram_base;
16755 /* Write some dummy words into the SRAM status block
16756 * area, see if it reads back correctly. If the return
16757 * value is bad, force enable the PCIX workaround.
16759 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16761 writel(0x00000000, sram_base);
16762 writel(0x00000000, sram_base + 4);
16763 writel(0xffffffff, sram_base + 4);
16764 if (readl(sram_base) != 0x00000000)
16765 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16770 tg3_nvram_init(tp);
16772 /* If the device has an NVRAM, no need to load patch firmware */
16773 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16774 !tg3_flag(tp, NO_NVRAM))
16775 tp->fw_needed = NULL;
16777 grc_misc_cfg = tr32(GRC_MISC_CFG);
16778 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16780 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16781 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16782 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
16783 tg3_flag_set(tp, IS_5788);
16785 if (!tg3_flag(tp, IS_5788) &&
16786 tg3_asic_rev(tp) != ASIC_REV_5700)
16787 tg3_flag_set(tp, TAGGED_STATUS);
16788 if (tg3_flag(tp, TAGGED_STATUS)) {
16789 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16790 HOSTCC_MODE_CLRTICK_TXBD);
16792 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16793 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16794 tp->misc_host_ctrl);
16797 /* Preserve the APE MAC_MODE bits */
16798 if (tg3_flag(tp, ENABLE_APE))
16799 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16803 if (tg3_10_100_only_device(tp, ent))
16804 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16806 err = tg3_phy_probe(tp);
16808 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16809 /* ... but do not return immediately ... */
16814 tg3_read_fw_ver(tp);
16816 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16817 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16819 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16820 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16822 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16825 /* 5700 {AX,BX} chips have a broken status block link
16826 * change bit implementation, so we must use the
16827 * status register in those cases.
16829 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16830 tg3_flag_set(tp, USE_LINKCHG_REG);
16832 tg3_flag_clear(tp, USE_LINKCHG_REG);
16834 /* The led_ctrl is set during tg3_phy_probe, here we might
16835 * have to force the link status polling mechanism based
16836 * upon subsystem IDs.
16838 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16839 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16840 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16841 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16842 tg3_flag_set(tp, USE_LINKCHG_REG);
16845 /* For all SERDES we poll the MAC status register. */
16846 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16847 tg3_flag_set(tp, POLL_SERDES);
16849 tg3_flag_clear(tp, POLL_SERDES);
16851 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16852 tg3_flag_set(tp, POLL_CPMU_LINK);
16854 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16855 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16856 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16857 tg3_flag(tp, PCIX_MODE)) {
16858 tp->rx_offset = NET_SKB_PAD;
16859 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16860 tp->rx_copy_thresh = ~(u16)0;
16864 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16865 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
16866 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16868 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
16870 /* Increment the rx prod index on the rx std ring by at most
16871 * 8 for these chips to workaround hw errata.
16873 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16874 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16875 tg3_asic_rev(tp) == ASIC_REV_5755)
16876 tp->rx_std_max_post = 8;
16878 if (tg3_flag(tp, ASPM_WORKAROUND))
16879 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16880 PCIE_PWR_MGMT_L1_THRESH_MSK;
16885 #ifdef CONFIG_SPARC
16886 static int tg3_get_macaddr_sparc(struct tg3 *tp)
16888 struct net_device *dev = tp->dev;
16889 struct pci_dev *pdev = tp->pdev;
16890 struct device_node *dp = pci_device_to_OF_node(pdev);
16891 const unsigned char *addr;
16894 addr = of_get_property(dp, "local-mac-address", &len);
16895 if (addr && len == ETH_ALEN) {
16896 memcpy(dev->dev_addr, addr, ETH_ALEN);
16902 static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
16904 struct net_device *dev = tp->dev;
16906 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
16911 static int tg3_get_device_address(struct tg3 *tp)
16913 struct net_device *dev = tp->dev;
16914 u32 hi, lo, mac_offset;
16918 #ifdef CONFIG_SPARC
16919 if (!tg3_get_macaddr_sparc(tp))
16923 if (tg3_flag(tp, IS_SSB_CORE)) {
16924 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16925 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16930 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16931 tg3_flag(tp, 5780_CLASS)) {
16932 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16934 if (tg3_nvram_lock(tp))
16935 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16937 tg3_nvram_unlock(tp);
16938 } else if (tg3_flag(tp, 5717_PLUS)) {
16939 if (tp->pci_fn & 1)
16941 if (tp->pci_fn > 1)
16942 mac_offset += 0x18c;
16943 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
16946 /* First try to get it from MAC address mailbox. */
16947 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16948 if ((hi >> 16) == 0x484b) {
16949 dev->dev_addr[0] = (hi >> 8) & 0xff;
16950 dev->dev_addr[1] = (hi >> 0) & 0xff;
16952 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16953 dev->dev_addr[2] = (lo >> 24) & 0xff;
16954 dev->dev_addr[3] = (lo >> 16) & 0xff;
16955 dev->dev_addr[4] = (lo >> 8) & 0xff;
16956 dev->dev_addr[5] = (lo >> 0) & 0xff;
16958 /* Some old bootcode may report a 0 MAC address in SRAM */
16959 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16962 /* Next, try NVRAM. */
16963 if (!tg3_flag(tp, NO_NVRAM) &&
16964 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
16965 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
16966 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16967 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
16969 /* Finally just fetch it out of the MAC control regs. */
16971 hi = tr32(MAC_ADDR_0_HIGH);
16972 lo = tr32(MAC_ADDR_0_LOW);
16974 dev->dev_addr[5] = lo & 0xff;
16975 dev->dev_addr[4] = (lo >> 8) & 0xff;
16976 dev->dev_addr[3] = (lo >> 16) & 0xff;
16977 dev->dev_addr[2] = (lo >> 24) & 0xff;
16978 dev->dev_addr[1] = hi & 0xff;
16979 dev->dev_addr[0] = (hi >> 8) & 0xff;
16983 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
16984 #ifdef CONFIG_SPARC
16985 if (!tg3_get_default_macaddr_sparc(tp))
16993 #define BOUNDARY_SINGLE_CACHELINE 1
16994 #define BOUNDARY_MULTI_CACHELINE 2
16996 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
16998 int cacheline_size;
17002 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
17004 cacheline_size = 1024;
17006 cacheline_size = (int) byte * 4;
17008 /* On 5703 and later chips, the boundary bits have no
17011 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17012 tg3_asic_rev(tp) != ASIC_REV_5701 &&
17013 !tg3_flag(tp, PCI_EXPRESS))
17016 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
17017 goal = BOUNDARY_MULTI_CACHELINE;
17019 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
17020 goal = BOUNDARY_SINGLE_CACHELINE;
17026 if (tg3_flag(tp, 57765_PLUS)) {
17027 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
17034 /* PCI controllers on most RISC systems tend to disconnect
17035 * when a device tries to burst across a cache-line boundary.
17036 * Therefore, letting tg3 do so just wastes PCI bandwidth.
17038 * Unfortunately, for PCI-E there are only limited
17039 * write-side controls for this, and thus for reads
17040 * we will still get the disconnects. We'll also waste
17041 * these PCI cycles for both read and write for chips
17042 * other than 5700 and 5701 which do not implement the
17045 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
17046 switch (cacheline_size) {
17051 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17052 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
17053 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
17055 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17056 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17061 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
17062 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
17066 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17067 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17070 } else if (tg3_flag(tp, PCI_EXPRESS)) {
17071 switch (cacheline_size) {
17075 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17076 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17077 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17083 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17084 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17088 switch (cacheline_size) {
17090 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17091 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17092 DMA_RWCTRL_WRITE_BNDRY_16);
17097 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17098 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17099 DMA_RWCTRL_WRITE_BNDRY_32);
17104 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17105 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17106 DMA_RWCTRL_WRITE_BNDRY_64);
17111 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17112 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17113 DMA_RWCTRL_WRITE_BNDRY_128);
17118 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17119 DMA_RWCTRL_WRITE_BNDRY_256);
17122 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17123 DMA_RWCTRL_WRITE_BNDRY_512);
17127 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17128 DMA_RWCTRL_WRITE_BNDRY_1024);
17137 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
17138 int size, bool to_device)
17140 struct tg3_internal_buffer_desc test_desc;
17141 u32 sram_dma_descs;
17144 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17146 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17147 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17148 tw32(RDMAC_STATUS, 0);
17149 tw32(WDMAC_STATUS, 0);
17151 tw32(BUFMGR_MODE, 0);
17152 tw32(FTQ_RESET, 0);
17154 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17155 test_desc.addr_lo = buf_dma & 0xffffffff;
17156 test_desc.nic_mbuf = 0x00002100;
17157 test_desc.len = size;
17160 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17161 * the *second* time the tg3 driver was getting loaded after an
17164 * Broadcom tells me:
17165 * ...the DMA engine is connected to the GRC block and a DMA
17166 * reset may affect the GRC block in some unpredictable way...
17167 * The behavior of resets to individual blocks has not been tested.
17169 * Broadcom noted the GRC reset will also reset all sub-components.
17172 test_desc.cqid_sqid = (13 << 8) | 2;
17174 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17177 test_desc.cqid_sqid = (16 << 8) | 7;
17179 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17182 test_desc.flags = 0x00000005;
17184 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17187 val = *(((u32 *)&test_desc) + i);
17188 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17189 sram_dma_descs + (i * sizeof(u32)));
17190 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17192 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17195 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
17197 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
17200 for (i = 0; i < 40; i++) {
17204 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17206 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17207 if ((val & 0xffff) == sram_dma_descs) {
17218 #define TEST_BUFFER_SIZE 0x2000
17220 static const struct pci_device_id tg3_dma_wait_state_chipsets[] = {
17221 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17225 static int tg3_test_dma(struct tg3 *tp)
17227 dma_addr_t buf_dma;
17228 u32 *buf, saved_dma_rwctrl;
17231 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17232 &buf_dma, GFP_KERNEL);
17238 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17239 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17241 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
17243 if (tg3_flag(tp, 57765_PLUS))
17246 if (tg3_flag(tp, PCI_EXPRESS)) {
17247 /* DMA read watermark not used on PCIE */
17248 tp->dma_rwctrl |= 0x00180000;
17249 } else if (!tg3_flag(tp, PCIX_MODE)) {
17250 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17251 tg3_asic_rev(tp) == ASIC_REV_5750)
17252 tp->dma_rwctrl |= 0x003f0000;
17254 tp->dma_rwctrl |= 0x003f000f;
17256 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17257 tg3_asic_rev(tp) == ASIC_REV_5704) {
17258 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
17259 u32 read_water = 0x7;
17261 /* If the 5704 is behind the EPB bridge, we can
17262 * do the less restrictive ONE_DMA workaround for
17263 * better performance.
17265 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
17266 tg3_asic_rev(tp) == ASIC_REV_5704)
17267 tp->dma_rwctrl |= 0x8000;
17268 else if (ccval == 0x6 || ccval == 0x7)
17269 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17271 if (tg3_asic_rev(tp) == ASIC_REV_5703)
17273 /* Set bit 23 to enable PCIX hw bug fix */
17275 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17276 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17278 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
17279 /* 5780 always in PCIX mode */
17280 tp->dma_rwctrl |= 0x00144000;
17281 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
17282 /* 5714 always in PCIX mode */
17283 tp->dma_rwctrl |= 0x00148000;
17285 tp->dma_rwctrl |= 0x001b000f;
17288 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17289 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17291 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17292 tg3_asic_rev(tp) == ASIC_REV_5704)
17293 tp->dma_rwctrl &= 0xfffffff0;
17295 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17296 tg3_asic_rev(tp) == ASIC_REV_5701) {
17297 /* Remove this if it causes problems for some boards. */
17298 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17300 /* On 5700/5701 chips, we need to set this bit.
17301 * Otherwise the chip will issue cacheline transactions
17302 * to streamable DMA memory with not all the byte
17303 * enables turned on. This is an error on several
17304 * RISC PCI controllers, in particular sparc64.
17306 * On 5703/5704 chips, this bit has been reassigned
17307 * a different meaning. In particular, it is used
17308 * on those chips to enable a PCI-X workaround.
17310 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17313 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17316 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17317 tg3_asic_rev(tp) != ASIC_REV_5701)
17320 /* It is best to perform DMA test with maximum write burst size
17321 * to expose the 5700/5701 write DMA bug.
17323 saved_dma_rwctrl = tp->dma_rwctrl;
17324 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17325 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17330 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17333 /* Send the buffer to the chip. */
17334 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
17336 dev_err(&tp->pdev->dev,
17337 "%s: Buffer write failed. err = %d\n",
17342 /* Now read it back. */
17343 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
17345 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17346 "err = %d\n", __func__, ret);
17351 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17355 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17356 DMA_RWCTRL_WRITE_BNDRY_16) {
17357 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17358 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17359 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17362 dev_err(&tp->pdev->dev,
17363 "%s: Buffer corrupted on read back! "
17364 "(%d != %d)\n", __func__, p[i], i);
17370 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17376 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17377 DMA_RWCTRL_WRITE_BNDRY_16) {
17378 /* DMA test passed without adjusting DMA boundary,
17379 * now look for chipsets that are known to expose the
17380 * DMA bug without failing the test.
17382 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
17383 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17384 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17386 /* Safe to use the calculated DMA boundary. */
17387 tp->dma_rwctrl = saved_dma_rwctrl;
17390 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17394 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
17399 static void tg3_init_bufmgr_config(struct tg3 *tp)
17401 if (tg3_flag(tp, 57765_PLUS)) {
17402 tp->bufmgr_config.mbuf_read_dma_low_water =
17403 DEFAULT_MB_RDMA_LOW_WATER_5705;
17404 tp->bufmgr_config.mbuf_mac_rx_low_water =
17405 DEFAULT_MB_MACRX_LOW_WATER_57765;
17406 tp->bufmgr_config.mbuf_high_water =
17407 DEFAULT_MB_HIGH_WATER_57765;
17409 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17410 DEFAULT_MB_RDMA_LOW_WATER_5705;
17411 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17412 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17413 tp->bufmgr_config.mbuf_high_water_jumbo =
17414 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
17415 } else if (tg3_flag(tp, 5705_PLUS)) {
17416 tp->bufmgr_config.mbuf_read_dma_low_water =
17417 DEFAULT_MB_RDMA_LOW_WATER_5705;
17418 tp->bufmgr_config.mbuf_mac_rx_low_water =
17419 DEFAULT_MB_MACRX_LOW_WATER_5705;
17420 tp->bufmgr_config.mbuf_high_water =
17421 DEFAULT_MB_HIGH_WATER_5705;
17422 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
17423 tp->bufmgr_config.mbuf_mac_rx_low_water =
17424 DEFAULT_MB_MACRX_LOW_WATER_5906;
17425 tp->bufmgr_config.mbuf_high_water =
17426 DEFAULT_MB_HIGH_WATER_5906;
17429 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17430 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17431 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17432 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17433 tp->bufmgr_config.mbuf_high_water_jumbo =
17434 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17436 tp->bufmgr_config.mbuf_read_dma_low_water =
17437 DEFAULT_MB_RDMA_LOW_WATER;
17438 tp->bufmgr_config.mbuf_mac_rx_low_water =
17439 DEFAULT_MB_MACRX_LOW_WATER;
17440 tp->bufmgr_config.mbuf_high_water =
17441 DEFAULT_MB_HIGH_WATER;
17443 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17444 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17445 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17446 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17447 tp->bufmgr_config.mbuf_high_water_jumbo =
17448 DEFAULT_MB_HIGH_WATER_JUMBO;
17451 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17452 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17455 static char *tg3_phy_string(struct tg3 *tp)
17457 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17458 case TG3_PHY_ID_BCM5400: return "5400";
17459 case TG3_PHY_ID_BCM5401: return "5401";
17460 case TG3_PHY_ID_BCM5411: return "5411";
17461 case TG3_PHY_ID_BCM5701: return "5701";
17462 case TG3_PHY_ID_BCM5703: return "5703";
17463 case TG3_PHY_ID_BCM5704: return "5704";
17464 case TG3_PHY_ID_BCM5705: return "5705";
17465 case TG3_PHY_ID_BCM5750: return "5750";
17466 case TG3_PHY_ID_BCM5752: return "5752";
17467 case TG3_PHY_ID_BCM5714: return "5714";
17468 case TG3_PHY_ID_BCM5780: return "5780";
17469 case TG3_PHY_ID_BCM5755: return "5755";
17470 case TG3_PHY_ID_BCM5787: return "5787";
17471 case TG3_PHY_ID_BCM5784: return "5784";
17472 case TG3_PHY_ID_BCM5756: return "5722/5756";
17473 case TG3_PHY_ID_BCM5906: return "5906";
17474 case TG3_PHY_ID_BCM5761: return "5761";
17475 case TG3_PHY_ID_BCM5718C: return "5718C";
17476 case TG3_PHY_ID_BCM5718S: return "5718S";
17477 case TG3_PHY_ID_BCM57765: return "57765";
17478 case TG3_PHY_ID_BCM5719C: return "5719C";
17479 case TG3_PHY_ID_BCM5720C: return "5720C";
17480 case TG3_PHY_ID_BCM5762: return "5762C";
17481 case TG3_PHY_ID_BCM8002: return "8002/serdes";
17482 case 0: return "serdes";
17483 default: return "unknown";
17487 static char *tg3_bus_string(struct tg3 *tp, char *str)
17489 if (tg3_flag(tp, PCI_EXPRESS)) {
17490 strcpy(str, "PCI Express");
17492 } else if (tg3_flag(tp, PCIX_MODE)) {
17493 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17495 strcpy(str, "PCIX:");
17497 if ((clock_ctrl == 7) ||
17498 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17499 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17500 strcat(str, "133MHz");
17501 else if (clock_ctrl == 0)
17502 strcat(str, "33MHz");
17503 else if (clock_ctrl == 2)
17504 strcat(str, "50MHz");
17505 else if (clock_ctrl == 4)
17506 strcat(str, "66MHz");
17507 else if (clock_ctrl == 6)
17508 strcat(str, "100MHz");
17510 strcpy(str, "PCI:");
17511 if (tg3_flag(tp, PCI_HIGH_SPEED))
17512 strcat(str, "66MHz");
17514 strcat(str, "33MHz");
17516 if (tg3_flag(tp, PCI_32BIT))
17517 strcat(str, ":32-bit");
17519 strcat(str, ":64-bit");
17523 static void tg3_init_coal(struct tg3 *tp)
17525 struct ethtool_coalesce *ec = &tp->coal;
17527 memset(ec, 0, sizeof(*ec));
17528 ec->cmd = ETHTOOL_GCOALESCE;
17529 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17530 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17531 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17532 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17533 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17534 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17535 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17536 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17537 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17539 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17540 HOSTCC_MODE_CLRTICK_TXBD)) {
17541 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17542 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17543 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17544 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17547 if (tg3_flag(tp, 5705_PLUS)) {
17548 ec->rx_coalesce_usecs_irq = 0;
17549 ec->tx_coalesce_usecs_irq = 0;
17550 ec->stats_block_coalesce_usecs = 0;
17554 static int tg3_init_one(struct pci_dev *pdev,
17555 const struct pci_device_id *ent)
17557 struct net_device *dev;
17560 u32 sndmbx, rcvmbx, intmbx;
17562 u64 dma_mask, persist_dma_mask;
17563 netdev_features_t features = 0;
17565 printk_once(KERN_INFO "%s\n", version);
17567 err = pci_enable_device(pdev);
17569 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
17573 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17575 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
17576 goto err_out_disable_pdev;
17579 pci_set_master(pdev);
17581 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17584 goto err_out_free_res;
17587 SET_NETDEV_DEV(dev, &pdev->dev);
17589 tp = netdev_priv(dev);
17592 tp->rx_mode = TG3_DEF_RX_MODE;
17593 tp->tx_mode = TG3_DEF_TX_MODE;
17595 tp->pcierr_recovery = false;
17598 tp->msg_enable = tg3_debug;
17600 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17602 if (pdev_is_ssb_gige_core(pdev)) {
17603 tg3_flag_set(tp, IS_SSB_CORE);
17604 if (ssb_gige_must_flush_posted_writes(pdev))
17605 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17606 if (ssb_gige_one_dma_at_once(pdev))
17607 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17608 if (ssb_gige_have_roboswitch(pdev)) {
17609 tg3_flag_set(tp, USE_PHYLIB);
17610 tg3_flag_set(tp, ROBOSWITCH);
17612 if (ssb_gige_is_rgmii(pdev))
17613 tg3_flag_set(tp, RGMII_MODE);
17616 /* The word/byte swap controls here control register access byte
17617 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17620 tp->misc_host_ctrl =
17621 MISC_HOST_CTRL_MASK_PCI_INT |
17622 MISC_HOST_CTRL_WORD_SWAP |
17623 MISC_HOST_CTRL_INDIR_ACCESS |
17624 MISC_HOST_CTRL_PCISTATE_RW;
17626 /* The NONFRM (non-frame) byte/word swap controls take effect
17627 * on descriptor entries, anything which isn't packet data.
17629 * The StrongARM chips on the board (one for tx, one for rx)
17630 * are running in big-endian mode.
17632 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17633 GRC_MODE_WSWAP_NONFRM_DATA);
17634 #ifdef __BIG_ENDIAN
17635 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17637 spin_lock_init(&tp->lock);
17638 spin_lock_init(&tp->indirect_lock);
17639 INIT_WORK(&tp->reset_task, tg3_reset_task);
17641 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17643 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
17645 goto err_out_free_dev;
17648 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17649 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17650 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17651 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17652 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17653 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17654 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17655 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17656 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17657 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17658 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
17659 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17660 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17661 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17662 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
17663 tg3_flag_set(tp, ENABLE_APE);
17664 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17665 if (!tp->aperegs) {
17666 dev_err(&pdev->dev,
17667 "Cannot map APE registers, aborting\n");
17669 goto err_out_iounmap;
17673 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17674 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17676 dev->ethtool_ops = &tg3_ethtool_ops;
17677 dev->watchdog_timeo = TG3_TX_TIMEOUT;
17678 dev->netdev_ops = &tg3_netdev_ops;
17679 dev->irq = pdev->irq;
17681 err = tg3_get_invariants(tp, ent);
17683 dev_err(&pdev->dev,
17684 "Problem fetching invariants of chip, aborting\n");
17685 goto err_out_apeunmap;
17688 /* The EPB bridge inside 5714, 5715, and 5780 and any
17689 * device behind the EPB cannot support DMA addresses > 40-bit.
17690 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17691 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17692 * do DMA address check in tg3_start_xmit().
17694 if (tg3_flag(tp, IS_5788))
17695 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
17696 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17697 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
17698 #ifdef CONFIG_HIGHMEM
17699 dma_mask = DMA_BIT_MASK(64);
17702 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
17704 /* Configure DMA attributes. */
17705 if (dma_mask > DMA_BIT_MASK(32)) {
17706 err = pci_set_dma_mask(pdev, dma_mask);
17708 features |= NETIF_F_HIGHDMA;
17709 err = pci_set_consistent_dma_mask(pdev,
17712 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17713 "DMA for consistent allocations\n");
17714 goto err_out_apeunmap;
17718 if (err || dma_mask == DMA_BIT_MASK(32)) {
17719 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
17721 dev_err(&pdev->dev,
17722 "No usable DMA configuration, aborting\n");
17723 goto err_out_apeunmap;
17727 tg3_init_bufmgr_config(tp);
17729 /* 5700 B0 chips do not support checksumming correctly due
17730 * to hardware bugs.
17732 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17733 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17735 if (tg3_flag(tp, 5755_PLUS))
17736 features |= NETIF_F_IPV6_CSUM;
17739 /* TSO is on by default on chips that support hardware TSO.
17740 * Firmware TSO on older chips gives lower performance, so it
17741 * is off by default, but can be enabled using ethtool.
17743 if ((tg3_flag(tp, HW_TSO_1) ||
17744 tg3_flag(tp, HW_TSO_2) ||
17745 tg3_flag(tp, HW_TSO_3)) &&
17746 (features & NETIF_F_IP_CSUM))
17747 features |= NETIF_F_TSO;
17748 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17749 if (features & NETIF_F_IPV6_CSUM)
17750 features |= NETIF_F_TSO6;
17751 if (tg3_flag(tp, HW_TSO_3) ||
17752 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17753 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17754 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17755 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17756 tg3_asic_rev(tp) == ASIC_REV_57780)
17757 features |= NETIF_F_TSO_ECN;
17760 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX |
17761 NETIF_F_HW_VLAN_CTAG_RX;
17762 dev->vlan_features |= features;
17765 * Add loopback capability only for a subset of devices that support
17766 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17767 * loopback for the remaining devices.
17769 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17770 !tg3_flag(tp, CPMU_PRESENT))
17771 /* Add the loopback capability */
17772 features |= NETIF_F_LOOPBACK;
17774 dev->hw_features |= features;
17775 dev->priv_flags |= IFF_UNICAST_FLT;
17777 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17778 !tg3_flag(tp, TSO_CAPABLE) &&
17779 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17780 tg3_flag_set(tp, MAX_RXPEND_64);
17781 tp->rx_pending = 63;
17784 err = tg3_get_device_address(tp);
17786 dev_err(&pdev->dev,
17787 "Could not obtain valid ethernet address, aborting\n");
17788 goto err_out_apeunmap;
17792 * Reset chip in case UNDI or EFI driver did not shutdown
17793 * DMA self test will enable WDMAC and we'll see (spurious)
17794 * pending DMA on the PCI bus at that point.
17796 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17797 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
17798 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
17799 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17802 err = tg3_test_dma(tp);
17804 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
17805 goto err_out_apeunmap;
17808 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17809 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17810 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
17811 for (i = 0; i < tp->irq_max; i++) {
17812 struct tg3_napi *tnapi = &tp->napi[i];
17815 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17817 tnapi->int_mbox = intmbx;
17823 tnapi->consmbox = rcvmbx;
17824 tnapi->prodmbox = sndmbx;
17827 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
17829 tnapi->coal_now = HOSTCC_MODE_NOW;
17831 if (!tg3_flag(tp, SUPPORT_MSIX))
17835 * If we support MSIX, we'll be using RSS. If we're using
17836 * RSS, the first vector only handles link interrupts and the
17837 * remaining vectors handle rx and tx interrupts. Reuse the
17838 * mailbox values for the next iteration. The values we setup
17839 * above are still useful for the single vectored mode.
17854 pci_set_drvdata(pdev, dev);
17856 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17857 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17858 tg3_asic_rev(tp) == ASIC_REV_5762)
17859 tg3_flag_set(tp, PTP_CAPABLE);
17861 tg3_timer_init(tp);
17863 tg3_carrier_off(tp);
17865 err = register_netdev(dev);
17867 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
17868 goto err_out_apeunmap;
17871 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17872 tp->board_part_number,
17873 tg3_chip_rev_id(tp),
17874 tg3_bus_string(tp, str),
17877 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
17878 struct phy_device *phydev;
17879 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
17881 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
17882 phydev->drv->name, dev_name(&phydev->dev));
17886 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17887 ethtype = "10/100Base-TX";
17888 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17889 ethtype = "1000Base-SX";
17891 ethtype = "10/100/1000Base-T";
17893 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
17894 "(WireSpeed[%d], EEE[%d])\n",
17895 tg3_phy_string(tp), ethtype,
17896 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17897 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
17900 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
17901 (dev->features & NETIF_F_RXCSUM) != 0,
17902 tg3_flag(tp, USE_LINKCHG_REG) != 0,
17903 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
17904 tg3_flag(tp, ENABLE_ASF) != 0,
17905 tg3_flag(tp, TSO_CAPABLE) != 0);
17906 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17908 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17909 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
17911 pci_save_state(pdev);
17917 iounmap(tp->aperegs);
17918 tp->aperegs = NULL;
17931 pci_release_regions(pdev);
17933 err_out_disable_pdev:
17934 if (pci_is_enabled(pdev))
17935 pci_disable_device(pdev);
17939 static void tg3_remove_one(struct pci_dev *pdev)
17941 struct net_device *dev = pci_get_drvdata(pdev);
17944 struct tg3 *tp = netdev_priv(dev);
17946 release_firmware(tp->fw);
17948 tg3_reset_task_cancel(tp);
17950 if (tg3_flag(tp, USE_PHYLIB)) {
17955 unregister_netdev(dev);
17957 iounmap(tp->aperegs);
17958 tp->aperegs = NULL;
17965 pci_release_regions(pdev);
17966 pci_disable_device(pdev);
17970 #ifdef CONFIG_PM_SLEEP
17971 static int tg3_suspend(struct device *device)
17973 struct pci_dev *pdev = to_pci_dev(device);
17974 struct net_device *dev = pci_get_drvdata(pdev);
17975 struct tg3 *tp = netdev_priv(dev);
17980 if (!netif_running(dev))
17983 tg3_reset_task_cancel(tp);
17985 tg3_netif_stop(tp);
17987 tg3_timer_stop(tp);
17989 tg3_full_lock(tp, 1);
17990 tg3_disable_ints(tp);
17991 tg3_full_unlock(tp);
17993 netif_device_detach(dev);
17995 tg3_full_lock(tp, 0);
17996 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17997 tg3_flag_clear(tp, INIT_COMPLETE);
17998 tg3_full_unlock(tp);
18000 err = tg3_power_down_prepare(tp);
18004 tg3_full_lock(tp, 0);
18006 tg3_flag_set(tp, INIT_COMPLETE);
18007 err2 = tg3_restart_hw(tp, true);
18011 tg3_timer_start(tp);
18013 netif_device_attach(dev);
18014 tg3_netif_start(tp);
18017 tg3_full_unlock(tp);
18028 static int tg3_resume(struct device *device)
18030 struct pci_dev *pdev = to_pci_dev(device);
18031 struct net_device *dev = pci_get_drvdata(pdev);
18032 struct tg3 *tp = netdev_priv(dev);
18037 if (!netif_running(dev))
18040 netif_device_attach(dev);
18042 tg3_full_lock(tp, 0);
18044 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18046 tg3_flag_set(tp, INIT_COMPLETE);
18047 err = tg3_restart_hw(tp,
18048 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
18052 tg3_timer_start(tp);
18054 tg3_netif_start(tp);
18057 tg3_full_unlock(tp);
18066 #endif /* CONFIG_PM_SLEEP */
18068 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
18070 static void tg3_shutdown(struct pci_dev *pdev)
18072 struct net_device *dev = pci_get_drvdata(pdev);
18073 struct tg3 *tp = netdev_priv(dev);
18076 netif_device_detach(dev);
18078 if (netif_running(dev))
18081 if (system_state == SYSTEM_POWER_OFF)
18082 tg3_power_down(tp);
18088 * tg3_io_error_detected - called when PCI error is detected
18089 * @pdev: Pointer to PCI device
18090 * @state: The current pci connection state
18092 * This function is called after a PCI bus error affecting
18093 * this device has been detected.
18095 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18096 pci_channel_state_t state)
18098 struct net_device *netdev = pci_get_drvdata(pdev);
18099 struct tg3 *tp = netdev_priv(netdev);
18100 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18102 netdev_info(netdev, "PCI I/O error detected\n");
18106 tp->pcierr_recovery = true;
18108 /* We probably don't have netdev yet */
18109 if (!netdev || !netif_running(netdev))
18114 tg3_netif_stop(tp);
18116 tg3_timer_stop(tp);
18118 /* Want to make sure that the reset task doesn't run */
18119 tg3_reset_task_cancel(tp);
18121 netif_device_detach(netdev);
18123 /* Clean up software state, even if MMIO is blocked */
18124 tg3_full_lock(tp, 0);
18125 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18126 tg3_full_unlock(tp);
18129 if (state == pci_channel_io_perm_failure) {
18131 tg3_napi_enable(tp);
18134 err = PCI_ERS_RESULT_DISCONNECT;
18136 pci_disable_device(pdev);
18145 * tg3_io_slot_reset - called after the pci bus has been reset.
18146 * @pdev: Pointer to PCI device
18148 * Restart the card from scratch, as if from a cold-boot.
18149 * At this point, the card has exprienced a hard reset,
18150 * followed by fixups by BIOS, and has its config space
18151 * set up identically to what it was at cold boot.
18153 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18155 struct net_device *netdev = pci_get_drvdata(pdev);
18156 struct tg3 *tp = netdev_priv(netdev);
18157 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18162 if (pci_enable_device(pdev)) {
18163 dev_err(&pdev->dev,
18164 "Cannot re-enable PCI device after reset.\n");
18168 pci_set_master(pdev);
18169 pci_restore_state(pdev);
18170 pci_save_state(pdev);
18172 if (!netdev || !netif_running(netdev)) {
18173 rc = PCI_ERS_RESULT_RECOVERED;
18177 err = tg3_power_up(tp);
18181 rc = PCI_ERS_RESULT_RECOVERED;
18184 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
18185 tg3_napi_enable(tp);
18194 * tg3_io_resume - called when traffic can start flowing again.
18195 * @pdev: Pointer to PCI device
18197 * This callback is called when the error recovery driver tells
18198 * us that its OK to resume normal operation.
18200 static void tg3_io_resume(struct pci_dev *pdev)
18202 struct net_device *netdev = pci_get_drvdata(pdev);
18203 struct tg3 *tp = netdev_priv(netdev);
18208 if (!netif_running(netdev))
18211 tg3_full_lock(tp, 0);
18212 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18213 tg3_flag_set(tp, INIT_COMPLETE);
18214 err = tg3_restart_hw(tp, true);
18216 tg3_full_unlock(tp);
18217 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18221 netif_device_attach(netdev);
18223 tg3_timer_start(tp);
18225 tg3_netif_start(tp);
18227 tg3_full_unlock(tp);
18232 tp->pcierr_recovery = false;
18236 static const struct pci_error_handlers tg3_err_handler = {
18237 .error_detected = tg3_io_error_detected,
18238 .slot_reset = tg3_io_slot_reset,
18239 .resume = tg3_io_resume
18242 static struct pci_driver tg3_driver = {
18243 .name = DRV_MODULE_NAME,
18244 .id_table = tg3_pci_tbl,
18245 .probe = tg3_init_one,
18246 .remove = tg3_remove_one,
18247 .err_handler = &tg3_err_handler,
18248 .driver.pm = &tg3_pm_ops,
18249 .shutdown = tg3_shutdown,
18252 module_pci_driver(tg3_driver);