2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2013 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #include <linux/ssb/ssb_driver_gige.h>
48 #include <linux/hwmon.h>
49 #include <linux/hwmon-sysfs.h>
51 #include <net/checksum.h>
55 #include <asm/byteorder.h>
56 #include <linux/uaccess.h>
58 #include <uapi/linux/net_tstamp.h>
59 #include <linux/ptp_clock_kernel.h>
62 #include <asm/idprom.h>
71 /* Functions & macros to verify TG3_FLAGS types */
73 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
75 return test_bit(flag, bits);
78 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
83 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
85 clear_bit(flag, bits);
88 #define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92 #define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define DRV_MODULE_NAME "tg3"
97 #define TG3_MIN_NUM 131
98 #define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
100 #define DRV_MODULE_RELDATE "April 09, 2013"
102 #define RESET_KIND_SHUTDOWN 0
103 #define RESET_KIND_INIT 1
104 #define RESET_KIND_SUSPEND 2
106 #define TG3_DEF_RX_MODE 0
107 #define TG3_DEF_TX_MODE 0
108 #define TG3_DEF_MSG_ENABLE \
118 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
120 /* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
124 #define TG3_TX_TIMEOUT (5 * HZ)
126 /* hardware minimum and maximum for a single frame's data payload */
127 #define TG3_MIN_MTU 60
128 #define TG3_MAX_MTU(tp) \
129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
131 /* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
135 #define TG3_RX_STD_RING_SIZE(tp) \
136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
138 #define TG3_DEF_RX_RING_PENDING 200
139 #define TG3_RX_JMB_RING_SIZE(tp) \
140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
142 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
144 /* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
151 #define TG3_TX_RING_SIZE 512
152 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
154 #define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156 #define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158 #define TG3_RX_RCB_RING_BYTES(tp) \
159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
160 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
162 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
164 #define TG3_DMA_BYTE_ENAB 64
166 #define TG3_RX_STD_DMA_SZ 1536
167 #define TG3_RX_JMB_DMA_SZ 9046
169 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
171 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
174 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
177 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
180 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
191 #define TG3_RX_COPY_THRESHOLD 256
192 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
198 #if (NET_IP_ALIGN != 0)
199 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
201 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
206 #define TG3_TX_BD_DMA_MAX_2K 2048
207 #define TG3_TX_BD_DMA_MAX_4K 4096
209 #define TG3_RAW_IP_ALIGN 2
211 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
212 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
214 #define FIRMWARE_TG3 "tigon/tg3.bin"
215 #define FIRMWARE_TG357766 "tigon/tg357766.bin"
216 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
217 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
219 static char version[] =
220 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
222 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
223 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
224 MODULE_LICENSE("GPL");
225 MODULE_VERSION(DRV_MODULE_VERSION);
226 MODULE_FIRMWARE(FIRMWARE_TG3);
227 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
228 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
230 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
231 module_param(tg3_debug, int, 0);
232 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
234 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
235 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
237 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
257 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
258 TG3_DRV_DATA_FLAG_5705_10_100},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
264 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
265 TG3_DRV_DATA_FLAG_5705_10_100},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
272 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
278 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
286 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
287 PCI_VENDOR_ID_LENOVO,
288 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
289 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
311 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
312 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
313 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
318 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
319 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
320 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
323 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
330 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
332 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
333 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
335 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
340 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
341 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
342 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
343 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
344 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
345 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
346 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
347 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
351 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
353 static const struct {
354 const char string[ETH_GSTRING_LEN];
355 } ethtool_stats_keys[] = {
358 { "rx_ucast_packets" },
359 { "rx_mcast_packets" },
360 { "rx_bcast_packets" },
362 { "rx_align_errors" },
363 { "rx_xon_pause_rcvd" },
364 { "rx_xoff_pause_rcvd" },
365 { "rx_mac_ctrl_rcvd" },
366 { "rx_xoff_entered" },
367 { "rx_frame_too_long_errors" },
369 { "rx_undersize_packets" },
370 { "rx_in_length_errors" },
371 { "rx_out_length_errors" },
372 { "rx_64_or_less_octet_packets" },
373 { "rx_65_to_127_octet_packets" },
374 { "rx_128_to_255_octet_packets" },
375 { "rx_256_to_511_octet_packets" },
376 { "rx_512_to_1023_octet_packets" },
377 { "rx_1024_to_1522_octet_packets" },
378 { "rx_1523_to_2047_octet_packets" },
379 { "rx_2048_to_4095_octet_packets" },
380 { "rx_4096_to_8191_octet_packets" },
381 { "rx_8192_to_9022_octet_packets" },
388 { "tx_flow_control" },
390 { "tx_single_collisions" },
391 { "tx_mult_collisions" },
393 { "tx_excessive_collisions" },
394 { "tx_late_collisions" },
395 { "tx_collide_2times" },
396 { "tx_collide_3times" },
397 { "tx_collide_4times" },
398 { "tx_collide_5times" },
399 { "tx_collide_6times" },
400 { "tx_collide_7times" },
401 { "tx_collide_8times" },
402 { "tx_collide_9times" },
403 { "tx_collide_10times" },
404 { "tx_collide_11times" },
405 { "tx_collide_12times" },
406 { "tx_collide_13times" },
407 { "tx_collide_14times" },
408 { "tx_collide_15times" },
409 { "tx_ucast_packets" },
410 { "tx_mcast_packets" },
411 { "tx_bcast_packets" },
412 { "tx_carrier_sense_errors" },
416 { "dma_writeq_full" },
417 { "dma_write_prioq_full" },
421 { "rx_threshold_hit" },
423 { "dma_readq_full" },
424 { "dma_read_prioq_full" },
425 { "tx_comp_queue_full" },
427 { "ring_set_send_prod_index" },
428 { "ring_status_update" },
430 { "nic_avoided_irqs" },
431 { "nic_tx_threshold_hit" },
433 { "mbuf_lwm_thresh_hit" },
436 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
437 #define TG3_NVRAM_TEST 0
438 #define TG3_LINK_TEST 1
439 #define TG3_REGISTER_TEST 2
440 #define TG3_MEMORY_TEST 3
441 #define TG3_MAC_LOOPB_TEST 4
442 #define TG3_PHY_LOOPB_TEST 5
443 #define TG3_EXT_LOOPB_TEST 6
444 #define TG3_INTERRUPT_TEST 7
447 static const struct {
448 const char string[ETH_GSTRING_LEN];
449 } ethtool_test_keys[] = {
450 [TG3_NVRAM_TEST] = { "nvram test (online) " },
451 [TG3_LINK_TEST] = { "link test (online) " },
452 [TG3_REGISTER_TEST] = { "register test (offline)" },
453 [TG3_MEMORY_TEST] = { "memory test (offline)" },
454 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
455 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
456 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
457 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
460 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
463 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
465 writel(val, tp->regs + off);
468 static u32 tg3_read32(struct tg3 *tp, u32 off)
470 return readl(tp->regs + off);
473 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
475 writel(val, tp->aperegs + off);
478 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
480 return readl(tp->aperegs + off);
483 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
487 spin_lock_irqsave(&tp->indirect_lock, flags);
488 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
489 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
490 spin_unlock_irqrestore(&tp->indirect_lock, flags);
493 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
495 writel(val, tp->regs + off);
496 readl(tp->regs + off);
499 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
504 spin_lock_irqsave(&tp->indirect_lock, flags);
505 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
506 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
511 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
515 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
516 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
517 TG3_64BIT_REG_LOW, val);
520 if (off == TG3_RX_STD_PROD_IDX_REG) {
521 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
522 TG3_64BIT_REG_LOW, val);
526 spin_lock_irqsave(&tp->indirect_lock, flags);
527 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
528 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
529 spin_unlock_irqrestore(&tp->indirect_lock, flags);
531 /* In indirect mode when disabling interrupts, we also need
532 * to clear the interrupt bit in the GRC local ctrl register.
534 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
536 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
537 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
541 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
546 spin_lock_irqsave(&tp->indirect_lock, flags);
547 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
548 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
549 spin_unlock_irqrestore(&tp->indirect_lock, flags);
553 /* usec_wait specifies the wait time in usec when writing to certain registers
554 * where it is unsafe to read back the register without some delay.
555 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
556 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
558 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
560 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
561 /* Non-posted methods */
562 tp->write32(tp, off, val);
565 tg3_write32(tp, off, val);
570 /* Wait again after the read for the posted method to guarantee that
571 * the wait time is met.
577 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
579 tp->write32_mbox(tp, off, val);
580 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
581 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
582 !tg3_flag(tp, ICH_WORKAROUND)))
583 tp->read32_mbox(tp, off);
586 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
588 void __iomem *mbox = tp->regs + off;
590 if (tg3_flag(tp, TXD_MBOX_HWBUG))
592 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
593 tg3_flag(tp, FLUSH_POSTED_WRITES))
597 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
599 return readl(tp->regs + off + GRCMBOX_BASE);
602 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
604 writel(val, tp->regs + off + GRCMBOX_BASE);
607 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
608 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
609 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
610 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
611 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
613 #define tw32(reg, val) tp->write32(tp, reg, val)
614 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
615 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
616 #define tr32(reg) tp->read32(tp, reg)
618 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
622 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
623 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
626 spin_lock_irqsave(&tp->indirect_lock, flags);
627 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
628 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
629 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
631 /* Always leave this as zero. */
632 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
634 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
635 tw32_f(TG3PCI_MEM_WIN_DATA, val);
637 /* Always leave this as zero. */
638 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
640 spin_unlock_irqrestore(&tp->indirect_lock, flags);
643 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
647 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
648 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
653 spin_lock_irqsave(&tp->indirect_lock, flags);
654 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
655 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
656 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
658 /* Always leave this as zero. */
659 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
661 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
662 *val = tr32(TG3PCI_MEM_WIN_DATA);
664 /* Always leave this as zero. */
665 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
667 spin_unlock_irqrestore(&tp->indirect_lock, flags);
670 static void tg3_ape_lock_init(struct tg3 *tp)
675 if (tg3_asic_rev(tp) == ASIC_REV_5761)
676 regbase = TG3_APE_LOCK_GRANT;
678 regbase = TG3_APE_PER_LOCK_GRANT;
680 /* Make sure the driver hasn't any stale locks. */
681 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
683 case TG3_APE_LOCK_PHY0:
684 case TG3_APE_LOCK_PHY1:
685 case TG3_APE_LOCK_PHY2:
686 case TG3_APE_LOCK_PHY3:
687 bit = APE_LOCK_GRANT_DRIVER;
691 bit = APE_LOCK_GRANT_DRIVER;
693 bit = 1 << tp->pci_fn;
695 tg3_ape_write32(tp, regbase + 4 * i, bit);
700 static int tg3_ape_lock(struct tg3 *tp, int locknum)
704 u32 status, req, gnt, bit;
706 if (!tg3_flag(tp, ENABLE_APE))
710 case TG3_APE_LOCK_GPIO:
711 if (tg3_asic_rev(tp) == ASIC_REV_5761)
713 case TG3_APE_LOCK_GRC:
714 case TG3_APE_LOCK_MEM:
716 bit = APE_LOCK_REQ_DRIVER;
718 bit = 1 << tp->pci_fn;
720 case TG3_APE_LOCK_PHY0:
721 case TG3_APE_LOCK_PHY1:
722 case TG3_APE_LOCK_PHY2:
723 case TG3_APE_LOCK_PHY3:
724 bit = APE_LOCK_REQ_DRIVER;
730 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
731 req = TG3_APE_LOCK_REQ;
732 gnt = TG3_APE_LOCK_GRANT;
734 req = TG3_APE_PER_LOCK_REQ;
735 gnt = TG3_APE_PER_LOCK_GRANT;
740 tg3_ape_write32(tp, req + off, bit);
742 /* Wait for up to 1 millisecond to acquire lock. */
743 for (i = 0; i < 100; i++) {
744 status = tg3_ape_read32(tp, gnt + off);
751 /* Revoke the lock request. */
752 tg3_ape_write32(tp, gnt + off, bit);
759 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
763 if (!tg3_flag(tp, ENABLE_APE))
767 case TG3_APE_LOCK_GPIO:
768 if (tg3_asic_rev(tp) == ASIC_REV_5761)
770 case TG3_APE_LOCK_GRC:
771 case TG3_APE_LOCK_MEM:
773 bit = APE_LOCK_GRANT_DRIVER;
775 bit = 1 << tp->pci_fn;
777 case TG3_APE_LOCK_PHY0:
778 case TG3_APE_LOCK_PHY1:
779 case TG3_APE_LOCK_PHY2:
780 case TG3_APE_LOCK_PHY3:
781 bit = APE_LOCK_GRANT_DRIVER;
787 if (tg3_asic_rev(tp) == ASIC_REV_5761)
788 gnt = TG3_APE_LOCK_GRANT;
790 gnt = TG3_APE_PER_LOCK_GRANT;
792 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
795 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
800 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
803 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
804 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
807 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
810 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
813 return timeout_us ? 0 : -EBUSY;
816 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
820 for (i = 0; i < timeout_us / 10; i++) {
821 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
823 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
829 return i == timeout_us / 10;
832 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
836 u32 i, bufoff, msgoff, maxlen, apedata;
838 if (!tg3_flag(tp, APE_HAS_NCSI))
841 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
842 if (apedata != APE_SEG_SIG_MAGIC)
845 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
846 if (!(apedata & APE_FW_STATUS_READY))
849 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
851 msgoff = bufoff + 2 * sizeof(u32);
852 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
857 /* Cap xfer sizes to scratchpad limits. */
858 length = (len > maxlen) ? maxlen : len;
861 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
862 if (!(apedata & APE_FW_STATUS_READY))
865 /* Wait for up to 1 msec for APE to service previous event. */
866 err = tg3_ape_event_lock(tp, 1000);
870 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
871 APE_EVENT_STATUS_SCRTCHPD_READ |
872 APE_EVENT_STATUS_EVENT_PENDING;
873 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
875 tg3_ape_write32(tp, bufoff, base_off);
876 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
878 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
879 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
883 if (tg3_ape_wait_for_event(tp, 30000))
886 for (i = 0; length; i += 4, length -= 4) {
887 u32 val = tg3_ape_read32(tp, msgoff + i);
888 memcpy(data, &val, sizeof(u32));
896 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
901 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
902 if (apedata != APE_SEG_SIG_MAGIC)
905 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
906 if (!(apedata & APE_FW_STATUS_READY))
909 /* Wait for up to 1 millisecond for APE to service previous event. */
910 err = tg3_ape_event_lock(tp, 1000);
914 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
915 event | APE_EVENT_STATUS_EVENT_PENDING);
917 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
918 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
923 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
928 if (!tg3_flag(tp, ENABLE_APE))
932 case RESET_KIND_INIT:
933 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
934 APE_HOST_SEG_SIG_MAGIC);
935 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
936 APE_HOST_SEG_LEN_MAGIC);
937 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
938 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
939 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
940 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
941 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
942 APE_HOST_BEHAV_NO_PHYLOCK);
943 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
944 TG3_APE_HOST_DRVR_STATE_START);
946 event = APE_EVENT_STATUS_STATE_START;
948 case RESET_KIND_SHUTDOWN:
949 /* With the interface we are currently using,
950 * APE does not track driver state. Wiping
951 * out the HOST SEGMENT SIGNATURE forces
952 * the APE to assume OS absent status.
954 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
956 if (device_may_wakeup(&tp->pdev->dev) &&
957 tg3_flag(tp, WOL_ENABLE)) {
958 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
959 TG3_APE_HOST_WOL_SPEED_AUTO);
960 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
962 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
964 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
966 event = APE_EVENT_STATUS_STATE_UNLOAD;
968 case RESET_KIND_SUSPEND:
969 event = APE_EVENT_STATUS_STATE_SUSPEND;
975 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
977 tg3_ape_send_event(tp, event);
980 static void tg3_disable_ints(struct tg3 *tp)
984 tw32(TG3PCI_MISC_HOST_CTRL,
985 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
986 for (i = 0; i < tp->irq_max; i++)
987 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
990 static void tg3_enable_ints(struct tg3 *tp)
997 tw32(TG3PCI_MISC_HOST_CTRL,
998 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1000 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1001 for (i = 0; i < tp->irq_cnt; i++) {
1002 struct tg3_napi *tnapi = &tp->napi[i];
1004 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1005 if (tg3_flag(tp, 1SHOT_MSI))
1006 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1008 tp->coal_now |= tnapi->coal_now;
1011 /* Force an initial interrupt */
1012 if (!tg3_flag(tp, TAGGED_STATUS) &&
1013 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1014 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1016 tw32(HOSTCC_MODE, tp->coal_now);
1018 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1021 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1023 struct tg3 *tp = tnapi->tp;
1024 struct tg3_hw_status *sblk = tnapi->hw_status;
1025 unsigned int work_exists = 0;
1027 /* check for phy events */
1028 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1029 if (sblk->status & SD_STATUS_LINK_CHG)
1033 /* check for TX work to do */
1034 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1037 /* check for RX work to do */
1038 if (tnapi->rx_rcb_prod_idx &&
1039 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1046 * similar to tg3_enable_ints, but it accurately determines whether there
1047 * is new work pending and can return without flushing the PIO write
1048 * which reenables interrupts
1050 static void tg3_int_reenable(struct tg3_napi *tnapi)
1052 struct tg3 *tp = tnapi->tp;
1054 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1057 /* When doing tagged status, this work check is unnecessary.
1058 * The last_tag we write above tells the chip which piece of
1059 * work we've completed.
1061 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1062 tw32(HOSTCC_MODE, tp->coalesce_mode |
1063 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1066 static void tg3_switch_clocks(struct tg3 *tp)
1069 u32 orig_clock_ctrl;
1071 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1074 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1076 orig_clock_ctrl = clock_ctrl;
1077 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1078 CLOCK_CTRL_CLKRUN_OENABLE |
1080 tp->pci_clock_ctrl = clock_ctrl;
1082 if (tg3_flag(tp, 5705_PLUS)) {
1083 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1084 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1085 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1087 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1088 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1090 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1096 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1099 #define PHY_BUSY_LOOPS 5000
1101 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1108 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1110 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1114 tg3_ape_lock(tp, tp->phy_ape_lock);
1118 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1119 MI_COM_PHY_ADDR_MASK);
1120 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1121 MI_COM_REG_ADDR_MASK);
1122 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1124 tw32_f(MAC_MI_COM, frame_val);
1126 loops = PHY_BUSY_LOOPS;
1127 while (loops != 0) {
1129 frame_val = tr32(MAC_MI_COM);
1131 if ((frame_val & MI_COM_BUSY) == 0) {
1133 frame_val = tr32(MAC_MI_COM);
1141 *val = frame_val & MI_COM_DATA_MASK;
1145 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1146 tw32_f(MAC_MI_MODE, tp->mi_mode);
1150 tg3_ape_unlock(tp, tp->phy_ape_lock);
1155 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1157 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1160 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1167 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1168 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1171 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1173 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1177 tg3_ape_lock(tp, tp->phy_ape_lock);
1179 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1180 MI_COM_PHY_ADDR_MASK);
1181 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1182 MI_COM_REG_ADDR_MASK);
1183 frame_val |= (val & MI_COM_DATA_MASK);
1184 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1186 tw32_f(MAC_MI_COM, frame_val);
1188 loops = PHY_BUSY_LOOPS;
1189 while (loops != 0) {
1191 frame_val = tr32(MAC_MI_COM);
1192 if ((frame_val & MI_COM_BUSY) == 0) {
1194 frame_val = tr32(MAC_MI_COM);
1204 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1205 tw32_f(MAC_MI_MODE, tp->mi_mode);
1209 tg3_ape_unlock(tp, tp->phy_ape_lock);
1214 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1216 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1219 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1223 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1227 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1232 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1236 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1242 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1246 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1250 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1255 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1259 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1265 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1269 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1271 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1276 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1280 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1282 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1287 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1291 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1292 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1293 MII_TG3_AUXCTL_SHDWSEL_MISC);
1295 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1300 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1302 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1303 set |= MII_TG3_AUXCTL_MISC_WREN;
1305 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1308 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1313 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1319 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1321 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1323 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1324 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1329 static int tg3_bmcr_reset(struct tg3 *tp)
1334 /* OK, reset it, and poll the BMCR_RESET bit until it
1335 * clears or we time out.
1337 phy_control = BMCR_RESET;
1338 err = tg3_writephy(tp, MII_BMCR, phy_control);
1344 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1348 if ((phy_control & BMCR_RESET) == 0) {
1360 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1362 struct tg3 *tp = bp->priv;
1365 spin_lock_bh(&tp->lock);
1367 if (tg3_readphy(tp, reg, &val))
1370 spin_unlock_bh(&tp->lock);
1375 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1377 struct tg3 *tp = bp->priv;
1380 spin_lock_bh(&tp->lock);
1382 if (tg3_writephy(tp, reg, val))
1385 spin_unlock_bh(&tp->lock);
1390 static int tg3_mdio_reset(struct mii_bus *bp)
1395 static void tg3_mdio_config_5785(struct tg3 *tp)
1398 struct phy_device *phydev;
1400 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1401 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1402 case PHY_ID_BCM50610:
1403 case PHY_ID_BCM50610M:
1404 val = MAC_PHYCFG2_50610_LED_MODES;
1406 case PHY_ID_BCMAC131:
1407 val = MAC_PHYCFG2_AC131_LED_MODES;
1409 case PHY_ID_RTL8211C:
1410 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1412 case PHY_ID_RTL8201E:
1413 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1419 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1420 tw32(MAC_PHYCFG2, val);
1422 val = tr32(MAC_PHYCFG1);
1423 val &= ~(MAC_PHYCFG1_RGMII_INT |
1424 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1425 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1426 tw32(MAC_PHYCFG1, val);
1431 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1432 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1433 MAC_PHYCFG2_FMODE_MASK_MASK |
1434 MAC_PHYCFG2_GMODE_MASK_MASK |
1435 MAC_PHYCFG2_ACT_MASK_MASK |
1436 MAC_PHYCFG2_QUAL_MASK_MASK |
1437 MAC_PHYCFG2_INBAND_ENABLE;
1439 tw32(MAC_PHYCFG2, val);
1441 val = tr32(MAC_PHYCFG1);
1442 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1443 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1444 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1445 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1446 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1447 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1448 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1450 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1451 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1452 tw32(MAC_PHYCFG1, val);
1454 val = tr32(MAC_EXT_RGMII_MODE);
1455 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1456 MAC_RGMII_MODE_RX_QUALITY |
1457 MAC_RGMII_MODE_RX_ACTIVITY |
1458 MAC_RGMII_MODE_RX_ENG_DET |
1459 MAC_RGMII_MODE_TX_ENABLE |
1460 MAC_RGMII_MODE_TX_LOWPWR |
1461 MAC_RGMII_MODE_TX_RESET);
1462 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1463 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1464 val |= MAC_RGMII_MODE_RX_INT_B |
1465 MAC_RGMII_MODE_RX_QUALITY |
1466 MAC_RGMII_MODE_RX_ACTIVITY |
1467 MAC_RGMII_MODE_RX_ENG_DET;
1468 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1469 val |= MAC_RGMII_MODE_TX_ENABLE |
1470 MAC_RGMII_MODE_TX_LOWPWR |
1471 MAC_RGMII_MODE_TX_RESET;
1473 tw32(MAC_EXT_RGMII_MODE, val);
1476 static void tg3_mdio_start(struct tg3 *tp)
1478 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1479 tw32_f(MAC_MI_MODE, tp->mi_mode);
1482 if (tg3_flag(tp, MDIOBUS_INITED) &&
1483 tg3_asic_rev(tp) == ASIC_REV_5785)
1484 tg3_mdio_config_5785(tp);
1487 static int tg3_mdio_init(struct tg3 *tp)
1491 struct phy_device *phydev;
1493 if (tg3_flag(tp, 5717_PLUS)) {
1496 tp->phy_addr = tp->pci_fn + 1;
1498 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1499 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1501 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1502 TG3_CPMU_PHY_STRAP_IS_SERDES;
1506 tp->phy_addr = TG3_PHY_MII_ADDR;
1510 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1513 tp->mdio_bus = mdiobus_alloc();
1514 if (tp->mdio_bus == NULL)
1517 tp->mdio_bus->name = "tg3 mdio bus";
1518 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1519 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1520 tp->mdio_bus->priv = tp;
1521 tp->mdio_bus->parent = &tp->pdev->dev;
1522 tp->mdio_bus->read = &tg3_mdio_read;
1523 tp->mdio_bus->write = &tg3_mdio_write;
1524 tp->mdio_bus->reset = &tg3_mdio_reset;
1525 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1526 tp->mdio_bus->irq = &tp->mdio_irq[0];
1528 for (i = 0; i < PHY_MAX_ADDR; i++)
1529 tp->mdio_bus->irq[i] = PHY_POLL;
1531 /* The bus registration will look for all the PHYs on the mdio bus.
1532 * Unfortunately, it does not ensure the PHY is powered up before
1533 * accessing the PHY ID registers. A chip reset is the
1534 * quickest way to bring the device back to an operational state..
1536 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1539 i = mdiobus_register(tp->mdio_bus);
1541 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1542 mdiobus_free(tp->mdio_bus);
1546 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1548 if (!phydev || !phydev->drv) {
1549 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1550 mdiobus_unregister(tp->mdio_bus);
1551 mdiobus_free(tp->mdio_bus);
1555 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1556 case PHY_ID_BCM57780:
1557 phydev->interface = PHY_INTERFACE_MODE_GMII;
1558 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1560 case PHY_ID_BCM50610:
1561 case PHY_ID_BCM50610M:
1562 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1563 PHY_BRCM_RX_REFCLK_UNUSED |
1564 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1565 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1566 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1567 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1568 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1569 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1570 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1571 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1573 case PHY_ID_RTL8211C:
1574 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1576 case PHY_ID_RTL8201E:
1577 case PHY_ID_BCMAC131:
1578 phydev->interface = PHY_INTERFACE_MODE_MII;
1579 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1580 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1584 tg3_flag_set(tp, MDIOBUS_INITED);
1586 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1587 tg3_mdio_config_5785(tp);
1592 static void tg3_mdio_fini(struct tg3 *tp)
1594 if (tg3_flag(tp, MDIOBUS_INITED)) {
1595 tg3_flag_clear(tp, MDIOBUS_INITED);
1596 mdiobus_unregister(tp->mdio_bus);
1597 mdiobus_free(tp->mdio_bus);
1601 /* tp->lock is held. */
1602 static inline void tg3_generate_fw_event(struct tg3 *tp)
1606 val = tr32(GRC_RX_CPU_EVENT);
1607 val |= GRC_RX_CPU_DRIVER_EVENT;
1608 tw32_f(GRC_RX_CPU_EVENT, val);
1610 tp->last_event_jiffies = jiffies;
1613 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1615 /* tp->lock is held. */
1616 static void tg3_wait_for_event_ack(struct tg3 *tp)
1619 unsigned int delay_cnt;
1622 /* If enough time has passed, no wait is necessary. */
1623 time_remain = (long)(tp->last_event_jiffies + 1 +
1624 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1626 if (time_remain < 0)
1629 /* Check if we can shorten the wait time. */
1630 delay_cnt = jiffies_to_usecs(time_remain);
1631 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1632 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1633 delay_cnt = (delay_cnt >> 3) + 1;
1635 for (i = 0; i < delay_cnt; i++) {
1636 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1642 /* tp->lock is held. */
1643 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1648 if (!tg3_readphy(tp, MII_BMCR, ®))
1650 if (!tg3_readphy(tp, MII_BMSR, ®))
1651 val |= (reg & 0xffff);
1655 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1657 if (!tg3_readphy(tp, MII_LPA, ®))
1658 val |= (reg & 0xffff);
1662 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1663 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1665 if (!tg3_readphy(tp, MII_STAT1000, ®))
1666 val |= (reg & 0xffff);
1670 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1677 /* tp->lock is held. */
1678 static void tg3_ump_link_report(struct tg3 *tp)
1682 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1685 tg3_phy_gather_ump_data(tp, data);
1687 tg3_wait_for_event_ack(tp);
1689 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1690 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1691 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1692 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1693 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1694 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1696 tg3_generate_fw_event(tp);
1699 /* tp->lock is held. */
1700 static void tg3_stop_fw(struct tg3 *tp)
1702 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1703 /* Wait for RX cpu to ACK the previous event. */
1704 tg3_wait_for_event_ack(tp);
1706 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1708 tg3_generate_fw_event(tp);
1710 /* Wait for RX cpu to ACK this event. */
1711 tg3_wait_for_event_ack(tp);
1715 /* tp->lock is held. */
1716 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1718 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1719 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1721 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1723 case RESET_KIND_INIT:
1724 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1728 case RESET_KIND_SHUTDOWN:
1729 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1733 case RESET_KIND_SUSPEND:
1734 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1743 if (kind == RESET_KIND_INIT ||
1744 kind == RESET_KIND_SUSPEND)
1745 tg3_ape_driver_state_change(tp, kind);
1748 /* tp->lock is held. */
1749 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1751 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1753 case RESET_KIND_INIT:
1754 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1755 DRV_STATE_START_DONE);
1758 case RESET_KIND_SHUTDOWN:
1759 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1760 DRV_STATE_UNLOAD_DONE);
1768 if (kind == RESET_KIND_SHUTDOWN)
1769 tg3_ape_driver_state_change(tp, kind);
1772 /* tp->lock is held. */
1773 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1775 if (tg3_flag(tp, ENABLE_ASF)) {
1777 case RESET_KIND_INIT:
1778 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1782 case RESET_KIND_SHUTDOWN:
1783 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1787 case RESET_KIND_SUSPEND:
1788 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1798 static int tg3_poll_fw(struct tg3 *tp)
1803 if (tg3_flag(tp, IS_SSB_CORE)) {
1804 /* We don't use firmware. */
1808 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1809 /* Wait up to 20ms for init done. */
1810 for (i = 0; i < 200; i++) {
1811 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1818 /* Wait for firmware initialization to complete. */
1819 for (i = 0; i < 100000; i++) {
1820 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1821 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1826 /* Chip might not be fitted with firmware. Some Sun onboard
1827 * parts are configured like that. So don't signal the timeout
1828 * of the above loop as an error, but do report the lack of
1829 * running firmware once.
1831 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1832 tg3_flag_set(tp, NO_FWARE_REPORTED);
1834 netdev_info(tp->dev, "No firmware running\n");
1837 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1838 /* The 57765 A0 needs a little more
1839 * time to do some important work.
1847 static void tg3_link_report(struct tg3 *tp)
1849 if (!netif_carrier_ok(tp->dev)) {
1850 netif_info(tp, link, tp->dev, "Link is down\n");
1851 tg3_ump_link_report(tp);
1852 } else if (netif_msg_link(tp)) {
1853 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1854 (tp->link_config.active_speed == SPEED_1000 ?
1856 (tp->link_config.active_speed == SPEED_100 ?
1858 (tp->link_config.active_duplex == DUPLEX_FULL ?
1861 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1862 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1864 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1867 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1868 netdev_info(tp->dev, "EEE is %s\n",
1869 tp->setlpicnt ? "enabled" : "disabled");
1871 tg3_ump_link_report(tp);
1874 tp->link_up = netif_carrier_ok(tp->dev);
1877 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1881 if (adv & ADVERTISE_PAUSE_CAP) {
1882 flowctrl |= FLOW_CTRL_RX;
1883 if (!(adv & ADVERTISE_PAUSE_ASYM))
1884 flowctrl |= FLOW_CTRL_TX;
1885 } else if (adv & ADVERTISE_PAUSE_ASYM)
1886 flowctrl |= FLOW_CTRL_TX;
1891 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1895 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1896 miireg = ADVERTISE_1000XPAUSE;
1897 else if (flow_ctrl & FLOW_CTRL_TX)
1898 miireg = ADVERTISE_1000XPSE_ASYM;
1899 else if (flow_ctrl & FLOW_CTRL_RX)
1900 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1907 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1911 if (adv & ADVERTISE_1000XPAUSE) {
1912 flowctrl |= FLOW_CTRL_RX;
1913 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1914 flowctrl |= FLOW_CTRL_TX;
1915 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1916 flowctrl |= FLOW_CTRL_TX;
1921 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1925 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1926 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1927 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1928 if (lcladv & ADVERTISE_1000XPAUSE)
1930 if (rmtadv & ADVERTISE_1000XPAUSE)
1937 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1941 u32 old_rx_mode = tp->rx_mode;
1942 u32 old_tx_mode = tp->tx_mode;
1944 if (tg3_flag(tp, USE_PHYLIB))
1945 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1947 autoneg = tp->link_config.autoneg;
1949 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1950 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1951 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1953 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1955 flowctrl = tp->link_config.flowctrl;
1957 tp->link_config.active_flowctrl = flowctrl;
1959 if (flowctrl & FLOW_CTRL_RX)
1960 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1962 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1964 if (old_rx_mode != tp->rx_mode)
1965 tw32_f(MAC_RX_MODE, tp->rx_mode);
1967 if (flowctrl & FLOW_CTRL_TX)
1968 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1970 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1972 if (old_tx_mode != tp->tx_mode)
1973 tw32_f(MAC_TX_MODE, tp->tx_mode);
1976 static void tg3_adjust_link(struct net_device *dev)
1978 u8 oldflowctrl, linkmesg = 0;
1979 u32 mac_mode, lcl_adv, rmt_adv;
1980 struct tg3 *tp = netdev_priv(dev);
1981 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1983 spin_lock_bh(&tp->lock);
1985 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1986 MAC_MODE_HALF_DUPLEX);
1988 oldflowctrl = tp->link_config.active_flowctrl;
1994 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1995 mac_mode |= MAC_MODE_PORT_MODE_MII;
1996 else if (phydev->speed == SPEED_1000 ||
1997 tg3_asic_rev(tp) != ASIC_REV_5785)
1998 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2000 mac_mode |= MAC_MODE_PORT_MODE_MII;
2002 if (phydev->duplex == DUPLEX_HALF)
2003 mac_mode |= MAC_MODE_HALF_DUPLEX;
2005 lcl_adv = mii_advertise_flowctrl(
2006 tp->link_config.flowctrl);
2009 rmt_adv = LPA_PAUSE_CAP;
2010 if (phydev->asym_pause)
2011 rmt_adv |= LPA_PAUSE_ASYM;
2014 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2016 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2018 if (mac_mode != tp->mac_mode) {
2019 tp->mac_mode = mac_mode;
2020 tw32_f(MAC_MODE, tp->mac_mode);
2024 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2025 if (phydev->speed == SPEED_10)
2027 MAC_MI_STAT_10MBPS_MODE |
2028 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2030 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2033 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2034 tw32(MAC_TX_LENGTHS,
2035 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2036 (6 << TX_LENGTHS_IPG_SHIFT) |
2037 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2039 tw32(MAC_TX_LENGTHS,
2040 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2041 (6 << TX_LENGTHS_IPG_SHIFT) |
2042 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2044 if (phydev->link != tp->old_link ||
2045 phydev->speed != tp->link_config.active_speed ||
2046 phydev->duplex != tp->link_config.active_duplex ||
2047 oldflowctrl != tp->link_config.active_flowctrl)
2050 tp->old_link = phydev->link;
2051 tp->link_config.active_speed = phydev->speed;
2052 tp->link_config.active_duplex = phydev->duplex;
2054 spin_unlock_bh(&tp->lock);
2057 tg3_link_report(tp);
2060 static int tg3_phy_init(struct tg3 *tp)
2062 struct phy_device *phydev;
2064 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2067 /* Bring the PHY back to a known state. */
2070 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2072 /* Attach the MAC to the PHY. */
2073 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2074 tg3_adjust_link, phydev->interface);
2075 if (IS_ERR(phydev)) {
2076 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2077 return PTR_ERR(phydev);
2080 /* Mask with MAC supported features. */
2081 switch (phydev->interface) {
2082 case PHY_INTERFACE_MODE_GMII:
2083 case PHY_INTERFACE_MODE_RGMII:
2084 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2085 phydev->supported &= (PHY_GBIT_FEATURES |
2087 SUPPORTED_Asym_Pause);
2091 case PHY_INTERFACE_MODE_MII:
2092 phydev->supported &= (PHY_BASIC_FEATURES |
2094 SUPPORTED_Asym_Pause);
2097 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2101 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2103 phydev->advertising = phydev->supported;
2108 static void tg3_phy_start(struct tg3 *tp)
2110 struct phy_device *phydev;
2112 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2115 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2117 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2118 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2119 phydev->speed = tp->link_config.speed;
2120 phydev->duplex = tp->link_config.duplex;
2121 phydev->autoneg = tp->link_config.autoneg;
2122 phydev->advertising = tp->link_config.advertising;
2127 phy_start_aneg(phydev);
2130 static void tg3_phy_stop(struct tg3 *tp)
2132 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2135 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2138 static void tg3_phy_fini(struct tg3 *tp)
2140 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2141 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2142 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2146 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2151 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2154 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2155 /* Cannot do read-modify-write on 5401 */
2156 err = tg3_phy_auxctl_write(tp,
2157 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2158 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2163 err = tg3_phy_auxctl_read(tp,
2164 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2168 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2169 err = tg3_phy_auxctl_write(tp,
2170 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2176 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2180 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2183 tg3_writephy(tp, MII_TG3_FET_TEST,
2184 phytest | MII_TG3_FET_SHADOW_EN);
2185 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2187 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2189 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2190 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2192 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2196 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2200 if (!tg3_flag(tp, 5705_PLUS) ||
2201 (tg3_flag(tp, 5717_PLUS) &&
2202 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2205 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2206 tg3_phy_fet_toggle_apd(tp, enable);
2210 reg = MII_TG3_MISC_SHDW_WREN |
2211 MII_TG3_MISC_SHDW_SCR5_SEL |
2212 MII_TG3_MISC_SHDW_SCR5_LPED |
2213 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2214 MII_TG3_MISC_SHDW_SCR5_SDTL |
2215 MII_TG3_MISC_SHDW_SCR5_C125OE;
2216 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2217 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2219 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2222 reg = MII_TG3_MISC_SHDW_WREN |
2223 MII_TG3_MISC_SHDW_APD_SEL |
2224 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2226 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2228 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2231 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2235 if (!tg3_flag(tp, 5705_PLUS) ||
2236 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2239 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2242 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2243 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2245 tg3_writephy(tp, MII_TG3_FET_TEST,
2246 ephy | MII_TG3_FET_SHADOW_EN);
2247 if (!tg3_readphy(tp, reg, &phy)) {
2249 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2251 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2252 tg3_writephy(tp, reg, phy);
2254 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2259 ret = tg3_phy_auxctl_read(tp,
2260 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2263 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2265 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2266 tg3_phy_auxctl_write(tp,
2267 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2272 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2277 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2280 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2282 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2283 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2286 static void tg3_phy_apply_otp(struct tg3 *tp)
2295 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2298 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2299 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2300 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2302 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2303 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2304 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2306 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2307 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2308 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2310 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2311 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2313 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2314 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2316 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2317 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2318 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2320 tg3_phy_toggle_auxctl_smdsp(tp, false);
2323 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2327 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2332 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2333 current_link_up == 1 &&
2334 tp->link_config.active_duplex == DUPLEX_FULL &&
2335 (tp->link_config.active_speed == SPEED_100 ||
2336 tp->link_config.active_speed == SPEED_1000)) {
2339 if (tp->link_config.active_speed == SPEED_1000)
2340 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2342 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2344 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2346 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2347 TG3_CL45_D7_EEERES_STAT, &val);
2349 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2350 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
2354 if (!tp->setlpicnt) {
2355 if (current_link_up == 1 &&
2356 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2357 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2358 tg3_phy_toggle_auxctl_smdsp(tp, false);
2361 val = tr32(TG3_CPMU_EEE_MODE);
2362 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2366 static void tg3_phy_eee_enable(struct tg3 *tp)
2370 if (tp->link_config.active_speed == SPEED_1000 &&
2371 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2372 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2373 tg3_flag(tp, 57765_CLASS)) &&
2374 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2375 val = MII_TG3_DSP_TAP26_ALNOKO |
2376 MII_TG3_DSP_TAP26_RMRXSTO;
2377 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2378 tg3_phy_toggle_auxctl_smdsp(tp, false);
2381 val = tr32(TG3_CPMU_EEE_MODE);
2382 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2385 static int tg3_wait_macro_done(struct tg3 *tp)
2392 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2393 if ((tmp32 & 0x1000) == 0)
2403 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2405 static const u32 test_pat[4][6] = {
2406 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2407 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2408 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2409 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2413 for (chan = 0; chan < 4; chan++) {
2416 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2417 (chan * 0x2000) | 0x0200);
2418 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2420 for (i = 0; i < 6; i++)
2421 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2424 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2425 if (tg3_wait_macro_done(tp)) {
2430 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2431 (chan * 0x2000) | 0x0200);
2432 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2433 if (tg3_wait_macro_done(tp)) {
2438 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2439 if (tg3_wait_macro_done(tp)) {
2444 for (i = 0; i < 6; i += 2) {
2447 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2448 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2449 tg3_wait_macro_done(tp)) {
2455 if (low != test_pat[chan][i] ||
2456 high != test_pat[chan][i+1]) {
2457 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2458 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2459 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2469 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2473 for (chan = 0; chan < 4; chan++) {
2476 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2477 (chan * 0x2000) | 0x0200);
2478 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2479 for (i = 0; i < 6; i++)
2480 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2481 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2482 if (tg3_wait_macro_done(tp))
2489 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2491 u32 reg32, phy9_orig;
2492 int retries, do_phy_reset, err;
2498 err = tg3_bmcr_reset(tp);
2504 /* Disable transmitter and interrupt. */
2505 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2509 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2511 /* Set full-duplex, 1000 mbps. */
2512 tg3_writephy(tp, MII_BMCR,
2513 BMCR_FULLDPLX | BMCR_SPEED1000);
2515 /* Set to master mode. */
2516 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2519 tg3_writephy(tp, MII_CTRL1000,
2520 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2522 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2526 /* Block the PHY control access. */
2527 tg3_phydsp_write(tp, 0x8005, 0x0800);
2529 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2532 } while (--retries);
2534 err = tg3_phy_reset_chanpat(tp);
2538 tg3_phydsp_write(tp, 0x8005, 0x0000);
2540 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2541 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2543 tg3_phy_toggle_auxctl_smdsp(tp, false);
2545 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2547 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
2549 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2556 static void tg3_carrier_off(struct tg3 *tp)
2558 netif_carrier_off(tp->dev);
2559 tp->link_up = false;
2562 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2564 if (tg3_flag(tp, ENABLE_ASF))
2565 netdev_warn(tp->dev,
2566 "Management side-band traffic will be interrupted during phy settings change\n");
2569 /* This will reset the tigon3 PHY if there is no valid
2570 * link unless the FORCE argument is non-zero.
2572 static int tg3_phy_reset(struct tg3 *tp)
2577 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2578 val = tr32(GRC_MISC_CFG);
2579 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2582 err = tg3_readphy(tp, MII_BMSR, &val);
2583 err |= tg3_readphy(tp, MII_BMSR, &val);
2587 if (netif_running(tp->dev) && tp->link_up) {
2588 netif_carrier_off(tp->dev);
2589 tg3_link_report(tp);
2592 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2593 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2594 tg3_asic_rev(tp) == ASIC_REV_5705) {
2595 err = tg3_phy_reset_5703_4_5(tp);
2602 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2603 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2604 cpmuctrl = tr32(TG3_CPMU_CTRL);
2605 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2607 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2610 err = tg3_bmcr_reset(tp);
2614 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2615 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2616 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2618 tw32(TG3_CPMU_CTRL, cpmuctrl);
2621 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2622 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2623 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2624 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2625 CPMU_LSPD_1000MB_MACCLK_12_5) {
2626 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2628 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2632 if (tg3_flag(tp, 5717_PLUS) &&
2633 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2636 tg3_phy_apply_otp(tp);
2638 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2639 tg3_phy_toggle_apd(tp, true);
2641 tg3_phy_toggle_apd(tp, false);
2644 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2645 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2646 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2647 tg3_phydsp_write(tp, 0x000a, 0x0323);
2648 tg3_phy_toggle_auxctl_smdsp(tp, false);
2651 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2652 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2653 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2656 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2657 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2658 tg3_phydsp_write(tp, 0x000a, 0x310b);
2659 tg3_phydsp_write(tp, 0x201f, 0x9506);
2660 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2661 tg3_phy_toggle_auxctl_smdsp(tp, false);
2663 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2664 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2665 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2666 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2667 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2668 tg3_writephy(tp, MII_TG3_TEST1,
2669 MII_TG3_TEST1_TRIM_EN | 0x4);
2671 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2673 tg3_phy_toggle_auxctl_smdsp(tp, false);
2677 /* Set Extended packet length bit (bit 14) on all chips that */
2678 /* support jumbo frames */
2679 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2680 /* Cannot do read-modify-write on 5401 */
2681 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2682 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2683 /* Set bit 14 with read-modify-write to preserve other bits */
2684 err = tg3_phy_auxctl_read(tp,
2685 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2687 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2688 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2691 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2692 * jumbo frames transmission.
2694 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2695 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2696 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2697 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2700 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2701 /* adjust output voltage */
2702 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2705 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2706 tg3_phydsp_write(tp, 0xffb, 0x4000);
2708 tg3_phy_toggle_automdix(tp, 1);
2709 tg3_phy_set_wirespeed(tp);
2713 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2714 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2715 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2716 TG3_GPIO_MSG_NEED_VAUX)
2717 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2718 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2719 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2720 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2721 (TG3_GPIO_MSG_DRVR_PRES << 12))
2723 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2724 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2725 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2726 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2727 (TG3_GPIO_MSG_NEED_VAUX << 12))
2729 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2733 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2734 tg3_asic_rev(tp) == ASIC_REV_5719)
2735 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2737 status = tr32(TG3_CPMU_DRV_STATUS);
2739 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2740 status &= ~(TG3_GPIO_MSG_MASK << shift);
2741 status |= (newstat << shift);
2743 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2744 tg3_asic_rev(tp) == ASIC_REV_5719)
2745 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2747 tw32(TG3_CPMU_DRV_STATUS, status);
2749 return status >> TG3_APE_GPIO_MSG_SHIFT;
2752 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2754 if (!tg3_flag(tp, IS_NIC))
2757 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2758 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2759 tg3_asic_rev(tp) == ASIC_REV_5720) {
2760 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2763 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2765 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2766 TG3_GRC_LCLCTL_PWRSW_DELAY);
2768 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2770 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2771 TG3_GRC_LCLCTL_PWRSW_DELAY);
2777 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2781 if (!tg3_flag(tp, IS_NIC) ||
2782 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2783 tg3_asic_rev(tp) == ASIC_REV_5701)
2786 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2788 tw32_wait_f(GRC_LOCAL_CTRL,
2789 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2790 TG3_GRC_LCLCTL_PWRSW_DELAY);
2792 tw32_wait_f(GRC_LOCAL_CTRL,
2794 TG3_GRC_LCLCTL_PWRSW_DELAY);
2796 tw32_wait_f(GRC_LOCAL_CTRL,
2797 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2798 TG3_GRC_LCLCTL_PWRSW_DELAY);
2801 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2803 if (!tg3_flag(tp, IS_NIC))
2806 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2807 tg3_asic_rev(tp) == ASIC_REV_5701) {
2808 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2809 (GRC_LCLCTRL_GPIO_OE0 |
2810 GRC_LCLCTRL_GPIO_OE1 |
2811 GRC_LCLCTRL_GPIO_OE2 |
2812 GRC_LCLCTRL_GPIO_OUTPUT0 |
2813 GRC_LCLCTRL_GPIO_OUTPUT1),
2814 TG3_GRC_LCLCTL_PWRSW_DELAY);
2815 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2816 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2817 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2818 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2819 GRC_LCLCTRL_GPIO_OE1 |
2820 GRC_LCLCTRL_GPIO_OE2 |
2821 GRC_LCLCTRL_GPIO_OUTPUT0 |
2822 GRC_LCLCTRL_GPIO_OUTPUT1 |
2824 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2825 TG3_GRC_LCLCTL_PWRSW_DELAY);
2827 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2828 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2829 TG3_GRC_LCLCTL_PWRSW_DELAY);
2831 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2832 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2833 TG3_GRC_LCLCTL_PWRSW_DELAY);
2836 u32 grc_local_ctrl = 0;
2838 /* Workaround to prevent overdrawing Amps. */
2839 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2840 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2841 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2843 TG3_GRC_LCLCTL_PWRSW_DELAY);
2846 /* On 5753 and variants, GPIO2 cannot be used. */
2847 no_gpio2 = tp->nic_sram_data_cfg &
2848 NIC_SRAM_DATA_CFG_NO_GPIO2;
2850 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2851 GRC_LCLCTRL_GPIO_OE1 |
2852 GRC_LCLCTRL_GPIO_OE2 |
2853 GRC_LCLCTRL_GPIO_OUTPUT1 |
2854 GRC_LCLCTRL_GPIO_OUTPUT2;
2856 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2857 GRC_LCLCTRL_GPIO_OUTPUT2);
2859 tw32_wait_f(GRC_LOCAL_CTRL,
2860 tp->grc_local_ctrl | grc_local_ctrl,
2861 TG3_GRC_LCLCTL_PWRSW_DELAY);
2863 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2865 tw32_wait_f(GRC_LOCAL_CTRL,
2866 tp->grc_local_ctrl | grc_local_ctrl,
2867 TG3_GRC_LCLCTL_PWRSW_DELAY);
2870 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2871 tw32_wait_f(GRC_LOCAL_CTRL,
2872 tp->grc_local_ctrl | grc_local_ctrl,
2873 TG3_GRC_LCLCTL_PWRSW_DELAY);
2878 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2882 /* Serialize power state transitions */
2883 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2886 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2887 msg = TG3_GPIO_MSG_NEED_VAUX;
2889 msg = tg3_set_function_status(tp, msg);
2891 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2894 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2895 tg3_pwrsrc_switch_to_vaux(tp);
2897 tg3_pwrsrc_die_with_vmain(tp);
2900 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2903 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2905 bool need_vaux = false;
2907 /* The GPIOs do something completely different on 57765. */
2908 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2911 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2912 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2913 tg3_asic_rev(tp) == ASIC_REV_5720) {
2914 tg3_frob_aux_power_5717(tp, include_wol ?
2915 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2919 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2920 struct net_device *dev_peer;
2922 dev_peer = pci_get_drvdata(tp->pdev_peer);
2924 /* remove_one() may have been run on the peer. */
2926 struct tg3 *tp_peer = netdev_priv(dev_peer);
2928 if (tg3_flag(tp_peer, INIT_COMPLETE))
2931 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2932 tg3_flag(tp_peer, ENABLE_ASF))
2937 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2938 tg3_flag(tp, ENABLE_ASF))
2942 tg3_pwrsrc_switch_to_vaux(tp);
2944 tg3_pwrsrc_die_with_vmain(tp);
2947 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2949 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2951 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2952 if (speed != SPEED_10)
2954 } else if (speed == SPEED_10)
2960 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2964 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
2967 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2968 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
2969 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2970 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2973 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2974 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2975 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2980 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2982 val = tr32(GRC_MISC_CFG);
2983 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2986 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2988 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2991 tg3_writephy(tp, MII_ADVERTISE, 0);
2992 tg3_writephy(tp, MII_BMCR,
2993 BMCR_ANENABLE | BMCR_ANRESTART);
2995 tg3_writephy(tp, MII_TG3_FET_TEST,
2996 phytest | MII_TG3_FET_SHADOW_EN);
2997 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2998 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3000 MII_TG3_FET_SHDW_AUXMODE4,
3003 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3006 } else if (do_low_power) {
3007 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3008 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3010 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3011 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3012 MII_TG3_AUXCTL_PCTL_VREG_11V;
3013 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3016 /* The PHY should not be powered down on some chips because
3019 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
3020 tg3_asic_rev(tp) == ASIC_REV_5704 ||
3021 (tg3_asic_rev(tp) == ASIC_REV_5780 &&
3022 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
3023 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
3027 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3028 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3029 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3030 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3031 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3032 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3035 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3038 /* tp->lock is held. */
3039 static int tg3_nvram_lock(struct tg3 *tp)
3041 if (tg3_flag(tp, NVRAM)) {
3044 if (tp->nvram_lock_cnt == 0) {
3045 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3046 for (i = 0; i < 8000; i++) {
3047 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3052 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3056 tp->nvram_lock_cnt++;
3061 /* tp->lock is held. */
3062 static void tg3_nvram_unlock(struct tg3 *tp)
3064 if (tg3_flag(tp, NVRAM)) {
3065 if (tp->nvram_lock_cnt > 0)
3066 tp->nvram_lock_cnt--;
3067 if (tp->nvram_lock_cnt == 0)
3068 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3072 /* tp->lock is held. */
3073 static void tg3_enable_nvram_access(struct tg3 *tp)
3075 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3076 u32 nvaccess = tr32(NVRAM_ACCESS);
3078 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3082 /* tp->lock is held. */
3083 static void tg3_disable_nvram_access(struct tg3 *tp)
3085 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3086 u32 nvaccess = tr32(NVRAM_ACCESS);
3088 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3092 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3093 u32 offset, u32 *val)
3098 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3101 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3102 EEPROM_ADDR_DEVID_MASK |
3104 tw32(GRC_EEPROM_ADDR,
3106 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3107 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3108 EEPROM_ADDR_ADDR_MASK) |
3109 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3111 for (i = 0; i < 1000; i++) {
3112 tmp = tr32(GRC_EEPROM_ADDR);
3114 if (tmp & EEPROM_ADDR_COMPLETE)
3118 if (!(tmp & EEPROM_ADDR_COMPLETE))
3121 tmp = tr32(GRC_EEPROM_DATA);
3124 * The data will always be opposite the native endian
3125 * format. Perform a blind byteswap to compensate.
3132 #define NVRAM_CMD_TIMEOUT 10000
3134 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3138 tw32(NVRAM_CMD, nvram_cmd);
3139 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3141 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3147 if (i == NVRAM_CMD_TIMEOUT)
3153 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3155 if (tg3_flag(tp, NVRAM) &&
3156 tg3_flag(tp, NVRAM_BUFFERED) &&
3157 tg3_flag(tp, FLASH) &&
3158 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3159 (tp->nvram_jedecnum == JEDEC_ATMEL))
3161 addr = ((addr / tp->nvram_pagesize) <<
3162 ATMEL_AT45DB0X1B_PAGE_POS) +
3163 (addr % tp->nvram_pagesize);
3168 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3170 if (tg3_flag(tp, NVRAM) &&
3171 tg3_flag(tp, NVRAM_BUFFERED) &&
3172 tg3_flag(tp, FLASH) &&
3173 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3174 (tp->nvram_jedecnum == JEDEC_ATMEL))
3176 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3177 tp->nvram_pagesize) +
3178 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3183 /* NOTE: Data read in from NVRAM is byteswapped according to
3184 * the byteswapping settings for all other register accesses.
3185 * tg3 devices are BE devices, so on a BE machine, the data
3186 * returned will be exactly as it is seen in NVRAM. On a LE
3187 * machine, the 32-bit value will be byteswapped.
3189 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3193 if (!tg3_flag(tp, NVRAM))
3194 return tg3_nvram_read_using_eeprom(tp, offset, val);
3196 offset = tg3_nvram_phys_addr(tp, offset);
3198 if (offset > NVRAM_ADDR_MSK)
3201 ret = tg3_nvram_lock(tp);
3205 tg3_enable_nvram_access(tp);
3207 tw32(NVRAM_ADDR, offset);
3208 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3209 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3212 *val = tr32(NVRAM_RDDATA);
3214 tg3_disable_nvram_access(tp);
3216 tg3_nvram_unlock(tp);
3221 /* Ensures NVRAM data is in bytestream format. */
3222 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3225 int res = tg3_nvram_read(tp, offset, &v);
3227 *val = cpu_to_be32(v);
3231 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3232 u32 offset, u32 len, u8 *buf)
3237 for (i = 0; i < len; i += 4) {
3243 memcpy(&data, buf + i, 4);
3246 * The SEEPROM interface expects the data to always be opposite
3247 * the native endian format. We accomplish this by reversing
3248 * all the operations that would have been performed on the
3249 * data from a call to tg3_nvram_read_be32().
3251 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3253 val = tr32(GRC_EEPROM_ADDR);
3254 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3256 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3258 tw32(GRC_EEPROM_ADDR, val |
3259 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3260 (addr & EEPROM_ADDR_ADDR_MASK) |
3264 for (j = 0; j < 1000; j++) {
3265 val = tr32(GRC_EEPROM_ADDR);
3267 if (val & EEPROM_ADDR_COMPLETE)
3271 if (!(val & EEPROM_ADDR_COMPLETE)) {
3280 /* offset and length are dword aligned */
3281 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3285 u32 pagesize = tp->nvram_pagesize;
3286 u32 pagemask = pagesize - 1;
3290 tmp = kmalloc(pagesize, GFP_KERNEL);
3296 u32 phy_addr, page_off, size;
3298 phy_addr = offset & ~pagemask;
3300 for (j = 0; j < pagesize; j += 4) {
3301 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3302 (__be32 *) (tmp + j));
3309 page_off = offset & pagemask;
3316 memcpy(tmp + page_off, buf, size);
3318 offset = offset + (pagesize - page_off);
3320 tg3_enable_nvram_access(tp);
3323 * Before we can erase the flash page, we need
3324 * to issue a special "write enable" command.
3326 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3328 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3331 /* Erase the target page */
3332 tw32(NVRAM_ADDR, phy_addr);
3334 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3335 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3337 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3340 /* Issue another write enable to start the write. */
3341 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3343 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3346 for (j = 0; j < pagesize; j += 4) {
3349 data = *((__be32 *) (tmp + j));
3351 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3353 tw32(NVRAM_ADDR, phy_addr + j);
3355 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3359 nvram_cmd |= NVRAM_CMD_FIRST;
3360 else if (j == (pagesize - 4))
3361 nvram_cmd |= NVRAM_CMD_LAST;
3363 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3371 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3372 tg3_nvram_exec_cmd(tp, nvram_cmd);
3379 /* offset and length are dword aligned */
3380 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3385 for (i = 0; i < len; i += 4, offset += 4) {
3386 u32 page_off, phy_addr, nvram_cmd;
3389 memcpy(&data, buf + i, 4);
3390 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3392 page_off = offset % tp->nvram_pagesize;
3394 phy_addr = tg3_nvram_phys_addr(tp, offset);
3396 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3398 if (page_off == 0 || i == 0)
3399 nvram_cmd |= NVRAM_CMD_FIRST;
3400 if (page_off == (tp->nvram_pagesize - 4))
3401 nvram_cmd |= NVRAM_CMD_LAST;
3404 nvram_cmd |= NVRAM_CMD_LAST;
3406 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3407 !tg3_flag(tp, FLASH) ||
3408 !tg3_flag(tp, 57765_PLUS))
3409 tw32(NVRAM_ADDR, phy_addr);
3411 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3412 !tg3_flag(tp, 5755_PLUS) &&
3413 (tp->nvram_jedecnum == JEDEC_ST) &&
3414 (nvram_cmd & NVRAM_CMD_FIRST)) {
3417 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3418 ret = tg3_nvram_exec_cmd(tp, cmd);
3422 if (!tg3_flag(tp, FLASH)) {
3423 /* We always do complete word writes to eeprom. */
3424 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3427 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3434 /* offset and length are dword aligned */
3435 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3439 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3440 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3441 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3445 if (!tg3_flag(tp, NVRAM)) {
3446 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3450 ret = tg3_nvram_lock(tp);
3454 tg3_enable_nvram_access(tp);
3455 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3456 tw32(NVRAM_WRITE1, 0x406);
3458 grc_mode = tr32(GRC_MODE);
3459 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3461 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3462 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3465 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3469 grc_mode = tr32(GRC_MODE);
3470 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3472 tg3_disable_nvram_access(tp);
3473 tg3_nvram_unlock(tp);
3476 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3477 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3484 #define RX_CPU_SCRATCH_BASE 0x30000
3485 #define RX_CPU_SCRATCH_SIZE 0x04000
3486 #define TX_CPU_SCRATCH_BASE 0x34000
3487 #define TX_CPU_SCRATCH_SIZE 0x04000
3489 /* tp->lock is held. */
3490 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3493 const int iters = 10000;
3495 for (i = 0; i < iters; i++) {
3496 tw32(cpu_base + CPU_STATE, 0xffffffff);
3497 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3498 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3502 return (i == iters) ? -EBUSY : 0;
3505 /* tp->lock is held. */
3506 static int tg3_rxcpu_pause(struct tg3 *tp)
3508 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3510 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3511 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3517 /* tp->lock is held. */
3518 static int tg3_txcpu_pause(struct tg3 *tp)
3520 return tg3_pause_cpu(tp, TX_CPU_BASE);
3523 /* tp->lock is held. */
3524 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3526 tw32(cpu_base + CPU_STATE, 0xffffffff);
3527 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3530 /* tp->lock is held. */
3531 static void tg3_rxcpu_resume(struct tg3 *tp)
3533 tg3_resume_cpu(tp, RX_CPU_BASE);
3536 /* tp->lock is held. */
3537 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3541 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3543 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3544 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3546 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3549 if (cpu_base == RX_CPU_BASE) {
3550 rc = tg3_rxcpu_pause(tp);
3553 * There is only an Rx CPU for the 5750 derivative in the
3556 if (tg3_flag(tp, IS_SSB_CORE))
3559 rc = tg3_txcpu_pause(tp);
3563 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3564 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3568 /* Clear firmware's nvram arbitration. */
3569 if (tg3_flag(tp, NVRAM))
3570 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3574 static int tg3_fw_data_len(struct tg3 *tp,
3575 const struct tg3_firmware_hdr *fw_hdr)
3579 /* Non fragmented firmware have one firmware header followed by a
3580 * contiguous chunk of data to be written. The length field in that
3581 * header is not the length of data to be written but the complete
3582 * length of the bss. The data length is determined based on
3583 * tp->fw->size minus headers.
3585 * Fragmented firmware have a main header followed by multiple
3586 * fragments. Each fragment is identical to non fragmented firmware
3587 * with a firmware header followed by a contiguous chunk of data. In
3588 * the main header, the length field is unused and set to 0xffffffff.
3589 * In each fragment header the length is the entire size of that
3590 * fragment i.e. fragment data + header length. Data length is
3591 * therefore length field in the header minus TG3_FW_HDR_LEN.
3593 if (tp->fw_len == 0xffffffff)
3594 fw_len = be32_to_cpu(fw_hdr->len);
3596 fw_len = tp->fw->size;
3598 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3601 /* tp->lock is held. */
3602 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3603 u32 cpu_scratch_base, int cpu_scratch_size,
3604 const struct tg3_firmware_hdr *fw_hdr)
3607 void (*write_op)(struct tg3 *, u32, u32);
3608 int total_len = tp->fw->size;
3610 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3612 "%s: Trying to load TX cpu firmware which is 5705\n",
3617 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3618 write_op = tg3_write_mem;
3620 write_op = tg3_write_indirect_reg32;
3622 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3623 /* It is possible that bootcode is still loading at this point.
3624 * Get the nvram lock first before halting the cpu.
3626 int lock_err = tg3_nvram_lock(tp);
3627 err = tg3_halt_cpu(tp, cpu_base);
3629 tg3_nvram_unlock(tp);
3633 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3634 write_op(tp, cpu_scratch_base + i, 0);
3635 tw32(cpu_base + CPU_STATE, 0xffffffff);
3636 tw32(cpu_base + CPU_MODE,
3637 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3639 /* Subtract additional main header for fragmented firmware and
3640 * advance to the first fragment
3642 total_len -= TG3_FW_HDR_LEN;
3647 u32 *fw_data = (u32 *)(fw_hdr + 1);
3648 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3649 write_op(tp, cpu_scratch_base +
3650 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3652 be32_to_cpu(fw_data[i]));
3654 total_len -= be32_to_cpu(fw_hdr->len);
3656 /* Advance to next fragment */
3657 fw_hdr = (struct tg3_firmware_hdr *)
3658 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3659 } while (total_len > 0);
3667 /* tp->lock is held. */
3668 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3671 const int iters = 5;
3673 tw32(cpu_base + CPU_STATE, 0xffffffff);
3674 tw32_f(cpu_base + CPU_PC, pc);
3676 for (i = 0; i < iters; i++) {
3677 if (tr32(cpu_base + CPU_PC) == pc)
3679 tw32(cpu_base + CPU_STATE, 0xffffffff);
3680 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3681 tw32_f(cpu_base + CPU_PC, pc);
3685 return (i == iters) ? -EBUSY : 0;
3688 /* tp->lock is held. */
3689 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3691 const struct tg3_firmware_hdr *fw_hdr;
3694 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3696 /* Firmware blob starts with version numbers, followed by
3697 start address and length. We are setting complete length.
3698 length = end_address_of_bss - start_address_of_text.
3699 Remainder is the blob to be loaded contiguously
3700 from start address. */
3702 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3703 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3708 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3709 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3714 /* Now startup only the RX cpu. */
3715 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3716 be32_to_cpu(fw_hdr->base_addr));
3718 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3719 "should be %08x\n", __func__,
3720 tr32(RX_CPU_BASE + CPU_PC),
3721 be32_to_cpu(fw_hdr->base_addr));
3725 tg3_rxcpu_resume(tp);
3730 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3732 const int iters = 1000;
3736 /* Wait for boot code to complete initialization and enter service
3737 * loop. It is then safe to download service patches
3739 for (i = 0; i < iters; i++) {
3740 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3747 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3751 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3753 netdev_warn(tp->dev,
3754 "Other patches exist. Not downloading EEE patch\n");
3761 /* tp->lock is held. */
3762 static void tg3_load_57766_firmware(struct tg3 *tp)
3764 struct tg3_firmware_hdr *fw_hdr;
3766 if (!tg3_flag(tp, NO_NVRAM))
3769 if (tg3_validate_rxcpu_state(tp))
3775 /* This firmware blob has a different format than older firmware
3776 * releases as given below. The main difference is we have fragmented
3777 * data to be written to non-contiguous locations.
3779 * In the beginning we have a firmware header identical to other
3780 * firmware which consists of version, base addr and length. The length
3781 * here is unused and set to 0xffffffff.
3783 * This is followed by a series of firmware fragments which are
3784 * individually identical to previous firmware. i.e. they have the
3785 * firmware header and followed by data for that fragment. The version
3786 * field of the individual fragment header is unused.
3789 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3790 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3793 if (tg3_rxcpu_pause(tp))
3796 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3797 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3799 tg3_rxcpu_resume(tp);
3802 /* tp->lock is held. */
3803 static int tg3_load_tso_firmware(struct tg3 *tp)
3805 const struct tg3_firmware_hdr *fw_hdr;
3806 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3809 if (!tg3_flag(tp, FW_TSO))
3812 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3814 /* Firmware blob starts with version numbers, followed by
3815 start address and length. We are setting complete length.
3816 length = end_address_of_bss - start_address_of_text.
3817 Remainder is the blob to be loaded contiguously
3818 from start address. */
3820 cpu_scratch_size = tp->fw_len;
3822 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3823 cpu_base = RX_CPU_BASE;
3824 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3826 cpu_base = TX_CPU_BASE;
3827 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3828 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3831 err = tg3_load_firmware_cpu(tp, cpu_base,
3832 cpu_scratch_base, cpu_scratch_size,
3837 /* Now startup the cpu. */
3838 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3839 be32_to_cpu(fw_hdr->base_addr));
3842 "%s fails to set CPU PC, is %08x should be %08x\n",
3843 __func__, tr32(cpu_base + CPU_PC),
3844 be32_to_cpu(fw_hdr->base_addr));
3848 tg3_resume_cpu(tp, cpu_base);
3853 /* tp->lock is held. */
3854 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3856 u32 addr_high, addr_low;
3859 addr_high = ((tp->dev->dev_addr[0] << 8) |
3860 tp->dev->dev_addr[1]);
3861 addr_low = ((tp->dev->dev_addr[2] << 24) |
3862 (tp->dev->dev_addr[3] << 16) |
3863 (tp->dev->dev_addr[4] << 8) |
3864 (tp->dev->dev_addr[5] << 0));
3865 for (i = 0; i < 4; i++) {
3866 if (i == 1 && skip_mac_1)
3868 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3869 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3872 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3873 tg3_asic_rev(tp) == ASIC_REV_5704) {
3874 for (i = 0; i < 12; i++) {
3875 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3876 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3880 addr_high = (tp->dev->dev_addr[0] +
3881 tp->dev->dev_addr[1] +
3882 tp->dev->dev_addr[2] +
3883 tp->dev->dev_addr[3] +
3884 tp->dev->dev_addr[4] +
3885 tp->dev->dev_addr[5]) &
3886 TX_BACKOFF_SEED_MASK;
3887 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3890 static void tg3_enable_register_access(struct tg3 *tp)
3893 * Make sure register accesses (indirect or otherwise) will function
3896 pci_write_config_dword(tp->pdev,
3897 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3900 static int tg3_power_up(struct tg3 *tp)
3904 tg3_enable_register_access(tp);
3906 err = pci_set_power_state(tp->pdev, PCI_D0);
3908 /* Switch out of Vaux if it is a NIC */
3909 tg3_pwrsrc_switch_to_vmain(tp);
3911 netdev_err(tp->dev, "Transition to D0 failed\n");
3917 static int tg3_setup_phy(struct tg3 *, int);
3919 static int tg3_power_down_prepare(struct tg3 *tp)
3922 bool device_should_wake, do_low_power;
3924 tg3_enable_register_access(tp);
3926 /* Restore the CLKREQ setting. */
3927 if (tg3_flag(tp, CLKREQ_BUG))
3928 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
3929 PCI_EXP_LNKCTL_CLKREQ_EN);
3931 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3932 tw32(TG3PCI_MISC_HOST_CTRL,
3933 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3935 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
3936 tg3_flag(tp, WOL_ENABLE);
3938 if (tg3_flag(tp, USE_PHYLIB)) {
3939 do_low_power = false;
3940 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
3941 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3942 struct phy_device *phydev;
3943 u32 phyid, advertising;
3945 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
3947 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3949 tp->link_config.speed = phydev->speed;
3950 tp->link_config.duplex = phydev->duplex;
3951 tp->link_config.autoneg = phydev->autoneg;
3952 tp->link_config.advertising = phydev->advertising;
3954 advertising = ADVERTISED_TP |
3956 ADVERTISED_Autoneg |
3957 ADVERTISED_10baseT_Half;
3959 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3960 if (tg3_flag(tp, WOL_SPEED_100MB))
3962 ADVERTISED_100baseT_Half |
3963 ADVERTISED_100baseT_Full |
3964 ADVERTISED_10baseT_Full;
3966 advertising |= ADVERTISED_10baseT_Full;
3969 phydev->advertising = advertising;
3971 phy_start_aneg(phydev);
3973 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
3974 if (phyid != PHY_ID_BCMAC131) {
3975 phyid &= PHY_BCM_OUI_MASK;
3976 if (phyid == PHY_BCM_OUI_1 ||
3977 phyid == PHY_BCM_OUI_2 ||
3978 phyid == PHY_BCM_OUI_3)
3979 do_low_power = true;
3983 do_low_power = true;
3985 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
3986 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3988 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
3989 tg3_setup_phy(tp, 0);
3992 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3995 val = tr32(GRC_VCPU_EXT_CTRL);
3996 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
3997 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4001 for (i = 0; i < 200; i++) {
4002 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4003 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4008 if (tg3_flag(tp, WOL_CAP))
4009 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4010 WOL_DRV_STATE_SHUTDOWN |
4014 if (device_should_wake) {
4017 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4019 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4020 tg3_phy_auxctl_write(tp,
4021 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4022 MII_TG3_AUXCTL_PCTL_WOL_EN |
4023 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4024 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4028 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4029 mac_mode = MAC_MODE_PORT_MODE_GMII;
4030 else if (tp->phy_flags &
4031 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4032 if (tp->link_config.active_speed == SPEED_1000)
4033 mac_mode = MAC_MODE_PORT_MODE_GMII;
4035 mac_mode = MAC_MODE_PORT_MODE_MII;
4037 mac_mode = MAC_MODE_PORT_MODE_MII;
4039 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4040 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4041 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4042 SPEED_100 : SPEED_10;
4043 if (tg3_5700_link_polarity(tp, speed))
4044 mac_mode |= MAC_MODE_LINK_POLARITY;
4046 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4049 mac_mode = MAC_MODE_PORT_MODE_TBI;
4052 if (!tg3_flag(tp, 5750_PLUS))
4053 tw32(MAC_LED_CTRL, tp->led_ctrl);
4055 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4056 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4057 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4058 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4060 if (tg3_flag(tp, ENABLE_APE))
4061 mac_mode |= MAC_MODE_APE_TX_EN |
4062 MAC_MODE_APE_RX_EN |
4063 MAC_MODE_TDE_ENABLE;
4065 tw32_f(MAC_MODE, mac_mode);
4068 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4072 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4073 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4074 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4077 base_val = tp->pci_clock_ctrl;
4078 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4079 CLOCK_CTRL_TXCLK_DISABLE);
4081 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4082 CLOCK_CTRL_PWRDOWN_PLL133, 40);
4083 } else if (tg3_flag(tp, 5780_CLASS) ||
4084 tg3_flag(tp, CPMU_PRESENT) ||
4085 tg3_asic_rev(tp) == ASIC_REV_5906) {
4087 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4088 u32 newbits1, newbits2;
4090 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4091 tg3_asic_rev(tp) == ASIC_REV_5701) {
4092 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4093 CLOCK_CTRL_TXCLK_DISABLE |
4095 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4096 } else if (tg3_flag(tp, 5705_PLUS)) {
4097 newbits1 = CLOCK_CTRL_625_CORE;
4098 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4100 newbits1 = CLOCK_CTRL_ALTCLK;
4101 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4104 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4107 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4110 if (!tg3_flag(tp, 5705_PLUS)) {
4113 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4114 tg3_asic_rev(tp) == ASIC_REV_5701) {
4115 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4116 CLOCK_CTRL_TXCLK_DISABLE |
4117 CLOCK_CTRL_44MHZ_CORE);
4119 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4122 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4123 tp->pci_clock_ctrl | newbits3, 40);
4127 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4128 tg3_power_down_phy(tp, do_low_power);
4130 tg3_frob_aux_power(tp, true);
4132 /* Workaround for unstable PLL clock */
4133 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4134 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4135 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4136 u32 val = tr32(0x7d00);
4138 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4140 if (!tg3_flag(tp, ENABLE_ASF)) {
4143 err = tg3_nvram_lock(tp);
4144 tg3_halt_cpu(tp, RX_CPU_BASE);
4146 tg3_nvram_unlock(tp);
4150 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4155 static void tg3_power_down(struct tg3 *tp)
4157 tg3_power_down_prepare(tp);
4159 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4160 pci_set_power_state(tp->pdev, PCI_D3hot);
4163 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4165 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4166 case MII_TG3_AUX_STAT_10HALF:
4168 *duplex = DUPLEX_HALF;
4171 case MII_TG3_AUX_STAT_10FULL:
4173 *duplex = DUPLEX_FULL;
4176 case MII_TG3_AUX_STAT_100HALF:
4178 *duplex = DUPLEX_HALF;
4181 case MII_TG3_AUX_STAT_100FULL:
4183 *duplex = DUPLEX_FULL;
4186 case MII_TG3_AUX_STAT_1000HALF:
4187 *speed = SPEED_1000;
4188 *duplex = DUPLEX_HALF;
4191 case MII_TG3_AUX_STAT_1000FULL:
4192 *speed = SPEED_1000;
4193 *duplex = DUPLEX_FULL;
4197 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4198 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4200 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4204 *speed = SPEED_UNKNOWN;
4205 *duplex = DUPLEX_UNKNOWN;
4210 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4215 new_adv = ADVERTISE_CSMA;
4216 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
4217 new_adv |= mii_advertise_flowctrl(flowctrl);
4219 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4223 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4224 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
4226 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4227 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4228 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4230 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4235 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4238 tw32(TG3_CPMU_EEE_MODE,
4239 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
4241 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4246 /* Advertise 100-BaseTX EEE ability */
4247 if (advertise & ADVERTISED_100baseT_Full)
4248 val |= MDIO_AN_EEE_ADV_100TX;
4249 /* Advertise 1000-BaseT EEE ability */
4250 if (advertise & ADVERTISED_1000baseT_Full)
4251 val |= MDIO_AN_EEE_ADV_1000T;
4252 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4256 switch (tg3_asic_rev(tp)) {
4258 case ASIC_REV_57765:
4259 case ASIC_REV_57766:
4261 /* If we advertised any eee advertisements above... */
4263 val = MII_TG3_DSP_TAP26_ALNOKO |
4264 MII_TG3_DSP_TAP26_RMRXSTO |
4265 MII_TG3_DSP_TAP26_OPCSINPT;
4266 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4270 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4271 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4272 MII_TG3_DSP_CH34TP2_HIBW01);
4275 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4284 static void tg3_phy_copper_begin(struct tg3 *tp)
4286 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4287 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4290 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4291 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4292 adv = ADVERTISED_10baseT_Half |
4293 ADVERTISED_10baseT_Full;
4294 if (tg3_flag(tp, WOL_SPEED_100MB))
4295 adv |= ADVERTISED_100baseT_Half |
4296 ADVERTISED_100baseT_Full;
4297 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK)
4298 adv |= ADVERTISED_1000baseT_Half |
4299 ADVERTISED_1000baseT_Full;
4301 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4303 adv = tp->link_config.advertising;
4304 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4305 adv &= ~(ADVERTISED_1000baseT_Half |
4306 ADVERTISED_1000baseT_Full);
4308 fc = tp->link_config.flowctrl;
4311 tg3_phy_autoneg_cfg(tp, adv, fc);
4313 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4314 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4315 /* Normally during power down we want to autonegotiate
4316 * the lowest possible speed for WOL. However, to avoid
4317 * link flap, we leave it untouched.
4322 tg3_writephy(tp, MII_BMCR,
4323 BMCR_ANENABLE | BMCR_ANRESTART);
4326 u32 bmcr, orig_bmcr;
4328 tp->link_config.active_speed = tp->link_config.speed;
4329 tp->link_config.active_duplex = tp->link_config.duplex;
4331 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4332 /* With autoneg disabled, 5715 only links up when the
4333 * advertisement register has the configured speed
4336 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4340 switch (tp->link_config.speed) {
4346 bmcr |= BMCR_SPEED100;
4350 bmcr |= BMCR_SPEED1000;
4354 if (tp->link_config.duplex == DUPLEX_FULL)
4355 bmcr |= BMCR_FULLDPLX;
4357 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4358 (bmcr != orig_bmcr)) {
4359 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4360 for (i = 0; i < 1500; i++) {
4364 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4365 tg3_readphy(tp, MII_BMSR, &tmp))
4367 if (!(tmp & BMSR_LSTATUS)) {
4372 tg3_writephy(tp, MII_BMCR, bmcr);
4378 static int tg3_phy_pull_config(struct tg3 *tp)
4383 err = tg3_readphy(tp, MII_BMCR, &val);
4387 if (!(val & BMCR_ANENABLE)) {
4388 tp->link_config.autoneg = AUTONEG_DISABLE;
4389 tp->link_config.advertising = 0;
4390 tg3_flag_clear(tp, PAUSE_AUTONEG);
4394 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4396 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4399 tp->link_config.speed = SPEED_10;
4402 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4405 tp->link_config.speed = SPEED_100;
4407 case BMCR_SPEED1000:
4408 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4409 tp->link_config.speed = SPEED_1000;
4417 if (val & BMCR_FULLDPLX)
4418 tp->link_config.duplex = DUPLEX_FULL;
4420 tp->link_config.duplex = DUPLEX_HALF;
4422 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4428 tp->link_config.autoneg = AUTONEG_ENABLE;
4429 tp->link_config.advertising = ADVERTISED_Autoneg;
4430 tg3_flag_set(tp, PAUSE_AUTONEG);
4432 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4435 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4439 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4440 tp->link_config.advertising |= adv | ADVERTISED_TP;
4442 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4444 tp->link_config.advertising |= ADVERTISED_FIBRE;
4447 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4450 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4451 err = tg3_readphy(tp, MII_CTRL1000, &val);
4455 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4457 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4461 adv = tg3_decode_flowctrl_1000X(val);
4462 tp->link_config.flowctrl = adv;
4464 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4465 adv = mii_adv_to_ethtool_adv_x(val);
4468 tp->link_config.advertising |= adv;
4475 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4479 /* Turn off tap power management. */
4480 /* Set Extended packet length bit */
4481 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4483 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4484 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4485 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4486 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4487 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4494 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4498 u32 advertising = tp->link_config.advertising;
4500 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4503 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
4506 val &= (MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T);
4509 if (advertising & ADVERTISED_100baseT_Full)
4510 tgtadv |= MDIO_AN_EEE_ADV_100TX;
4511 if (advertising & ADVERTISED_1000baseT_Full)
4512 tgtadv |= MDIO_AN_EEE_ADV_1000T;
4520 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4522 u32 advmsk, tgtadv, advertising;
4524 advertising = tp->link_config.advertising;
4525 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4527 advmsk = ADVERTISE_ALL;
4528 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4529 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4530 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4533 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4536 if ((*lcladv & advmsk) != tgtadv)
4539 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4542 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4544 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4548 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4549 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4550 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4551 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4552 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4554 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4557 if (tg3_ctrl != tgtadv)
4564 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4568 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4571 if (tg3_readphy(tp, MII_STAT1000, &val))
4574 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4577 if (tg3_readphy(tp, MII_LPA, rmtadv))
4580 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4581 tp->link_config.rmt_adv = lpeth;
4586 static bool tg3_test_and_report_link_chg(struct tg3 *tp, int curr_link_up)
4588 if (curr_link_up != tp->link_up) {
4590 netif_carrier_on(tp->dev);
4592 netif_carrier_off(tp->dev);
4593 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4594 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4597 tg3_link_report(tp);
4604 static void tg3_clear_mac_status(struct tg3 *tp)
4609 MAC_STATUS_SYNC_CHANGED |
4610 MAC_STATUS_CFG_CHANGED |
4611 MAC_STATUS_MI_COMPLETION |
4612 MAC_STATUS_LNKSTATE_CHANGED);
4616 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
4618 int current_link_up;
4620 u32 lcl_adv, rmt_adv;
4625 tg3_clear_mac_status(tp);
4627 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4629 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4633 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4635 /* Some third-party PHYs need to be reset on link going
4638 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4639 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4640 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4642 tg3_readphy(tp, MII_BMSR, &bmsr);
4643 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4644 !(bmsr & BMSR_LSTATUS))
4650 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4651 tg3_readphy(tp, MII_BMSR, &bmsr);
4652 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4653 !tg3_flag(tp, INIT_COMPLETE))
4656 if (!(bmsr & BMSR_LSTATUS)) {
4657 err = tg3_init_5401phy_dsp(tp);
4661 tg3_readphy(tp, MII_BMSR, &bmsr);
4662 for (i = 0; i < 1000; i++) {
4664 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4665 (bmsr & BMSR_LSTATUS)) {
4671 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4672 TG3_PHY_REV_BCM5401_B0 &&
4673 !(bmsr & BMSR_LSTATUS) &&
4674 tp->link_config.active_speed == SPEED_1000) {
4675 err = tg3_phy_reset(tp);
4677 err = tg3_init_5401phy_dsp(tp);
4682 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4683 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4684 /* 5701 {A0,B0} CRC bug workaround */
4685 tg3_writephy(tp, 0x15, 0x0a75);
4686 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4687 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4688 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4691 /* Clear pending interrupts... */
4692 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4693 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4695 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4696 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4697 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4698 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4700 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4701 tg3_asic_rev(tp) == ASIC_REV_5701) {
4702 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4703 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4704 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4706 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4709 current_link_up = 0;
4710 current_speed = SPEED_UNKNOWN;
4711 current_duplex = DUPLEX_UNKNOWN;
4712 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4713 tp->link_config.rmt_adv = 0;
4715 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4716 err = tg3_phy_auxctl_read(tp,
4717 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4719 if (!err && !(val & (1 << 10))) {
4720 tg3_phy_auxctl_write(tp,
4721 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4728 for (i = 0; i < 100; i++) {
4729 tg3_readphy(tp, MII_BMSR, &bmsr);
4730 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4731 (bmsr & BMSR_LSTATUS))
4736 if (bmsr & BMSR_LSTATUS) {
4739 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4740 for (i = 0; i < 2000; i++) {
4742 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4747 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4752 for (i = 0; i < 200; i++) {
4753 tg3_readphy(tp, MII_BMCR, &bmcr);
4754 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4756 if (bmcr && bmcr != 0x7fff)
4764 tp->link_config.active_speed = current_speed;
4765 tp->link_config.active_duplex = current_duplex;
4767 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4768 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4770 if ((bmcr & BMCR_ANENABLE) &&
4772 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4773 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4774 current_link_up = 1;
4776 /* EEE settings changes take effect only after a phy
4777 * reset. If we have skipped a reset due to Link Flap
4778 * Avoidance being enabled, do it now.
4780 if (!eee_config_ok &&
4781 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4785 if (!(bmcr & BMCR_ANENABLE) &&
4786 tp->link_config.speed == current_speed &&
4787 tp->link_config.duplex == current_duplex) {
4788 current_link_up = 1;
4792 if (current_link_up == 1 &&
4793 tp->link_config.active_duplex == DUPLEX_FULL) {
4796 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4797 reg = MII_TG3_FET_GEN_STAT;
4798 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4800 reg = MII_TG3_EXT_STAT;
4801 bit = MII_TG3_EXT_STAT_MDIX;
4804 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4805 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4807 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4812 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4813 tg3_phy_copper_begin(tp);
4815 if (tg3_flag(tp, ROBOSWITCH)) {
4816 current_link_up = 1;
4817 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4818 current_speed = SPEED_1000;
4819 current_duplex = DUPLEX_FULL;
4820 tp->link_config.active_speed = current_speed;
4821 tp->link_config.active_duplex = current_duplex;
4824 tg3_readphy(tp, MII_BMSR, &bmsr);
4825 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4826 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4827 current_link_up = 1;
4830 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4831 if (current_link_up == 1) {
4832 if (tp->link_config.active_speed == SPEED_100 ||
4833 tp->link_config.active_speed == SPEED_10)
4834 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4836 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4837 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4838 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4840 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4842 /* In order for the 5750 core in BCM4785 chip to work properly
4843 * in RGMII mode, the Led Control Register must be set up.
4845 if (tg3_flag(tp, RGMII_MODE)) {
4846 u32 led_ctrl = tr32(MAC_LED_CTRL);
4847 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
4849 if (tp->link_config.active_speed == SPEED_10)
4850 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
4851 else if (tp->link_config.active_speed == SPEED_100)
4852 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
4853 LED_CTRL_100MBPS_ON);
4854 else if (tp->link_config.active_speed == SPEED_1000)
4855 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
4856 LED_CTRL_1000MBPS_ON);
4858 tw32(MAC_LED_CTRL, led_ctrl);
4862 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4863 if (tp->link_config.active_duplex == DUPLEX_HALF)
4864 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4866 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4867 if (current_link_up == 1 &&
4868 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
4869 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
4871 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
4874 /* ??? Without this setting Netgear GA302T PHY does not
4875 * ??? send/receive packets...
4877 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4878 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
4879 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4880 tw32_f(MAC_MI_MODE, tp->mi_mode);
4884 tw32_f(MAC_MODE, tp->mac_mode);
4887 tg3_phy_eee_adjust(tp, current_link_up);
4889 if (tg3_flag(tp, USE_LINKCHG_REG)) {
4890 /* Polled via timer. */
4891 tw32_f(MAC_EVENT, 0);
4893 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4897 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
4898 current_link_up == 1 &&
4899 tp->link_config.active_speed == SPEED_1000 &&
4900 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
4903 (MAC_STATUS_SYNC_CHANGED |
4904 MAC_STATUS_CFG_CHANGED));
4907 NIC_SRAM_FIRMWARE_MBOX,
4908 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
4911 /* Prevent send BD corruption. */
4912 if (tg3_flag(tp, CLKREQ_BUG)) {
4913 if (tp->link_config.active_speed == SPEED_100 ||
4914 tp->link_config.active_speed == SPEED_10)
4915 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
4916 PCI_EXP_LNKCTL_CLKREQ_EN);
4918 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4919 PCI_EXP_LNKCTL_CLKREQ_EN);
4922 tg3_test_and_report_link_chg(tp, current_link_up);
4927 struct tg3_fiber_aneginfo {
4929 #define ANEG_STATE_UNKNOWN 0
4930 #define ANEG_STATE_AN_ENABLE 1
4931 #define ANEG_STATE_RESTART_INIT 2
4932 #define ANEG_STATE_RESTART 3
4933 #define ANEG_STATE_DISABLE_LINK_OK 4
4934 #define ANEG_STATE_ABILITY_DETECT_INIT 5
4935 #define ANEG_STATE_ABILITY_DETECT 6
4936 #define ANEG_STATE_ACK_DETECT_INIT 7
4937 #define ANEG_STATE_ACK_DETECT 8
4938 #define ANEG_STATE_COMPLETE_ACK_INIT 9
4939 #define ANEG_STATE_COMPLETE_ACK 10
4940 #define ANEG_STATE_IDLE_DETECT_INIT 11
4941 #define ANEG_STATE_IDLE_DETECT 12
4942 #define ANEG_STATE_LINK_OK 13
4943 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
4944 #define ANEG_STATE_NEXT_PAGE_WAIT 15
4947 #define MR_AN_ENABLE 0x00000001
4948 #define MR_RESTART_AN 0x00000002
4949 #define MR_AN_COMPLETE 0x00000004
4950 #define MR_PAGE_RX 0x00000008
4951 #define MR_NP_LOADED 0x00000010
4952 #define MR_TOGGLE_TX 0x00000020
4953 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
4954 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
4955 #define MR_LP_ADV_SYM_PAUSE 0x00000100
4956 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
4957 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4958 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4959 #define MR_LP_ADV_NEXT_PAGE 0x00001000
4960 #define MR_TOGGLE_RX 0x00002000
4961 #define MR_NP_RX 0x00004000
4963 #define MR_LINK_OK 0x80000000
4965 unsigned long link_time, cur_time;
4967 u32 ability_match_cfg;
4968 int ability_match_count;
4970 char ability_match, idle_match, ack_match;
4972 u32 txconfig, rxconfig;
4973 #define ANEG_CFG_NP 0x00000080
4974 #define ANEG_CFG_ACK 0x00000040
4975 #define ANEG_CFG_RF2 0x00000020
4976 #define ANEG_CFG_RF1 0x00000010
4977 #define ANEG_CFG_PS2 0x00000001
4978 #define ANEG_CFG_PS1 0x00008000
4979 #define ANEG_CFG_HD 0x00004000
4980 #define ANEG_CFG_FD 0x00002000
4981 #define ANEG_CFG_INVAL 0x00001f06
4986 #define ANEG_TIMER_ENAB 2
4987 #define ANEG_FAILED -1
4989 #define ANEG_STATE_SETTLE_TIME 10000
4991 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4992 struct tg3_fiber_aneginfo *ap)
4995 unsigned long delta;
4999 if (ap->state == ANEG_STATE_UNKNOWN) {
5003 ap->ability_match_cfg = 0;
5004 ap->ability_match_count = 0;
5005 ap->ability_match = 0;
5011 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5012 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5014 if (rx_cfg_reg != ap->ability_match_cfg) {
5015 ap->ability_match_cfg = rx_cfg_reg;
5016 ap->ability_match = 0;
5017 ap->ability_match_count = 0;
5019 if (++ap->ability_match_count > 1) {
5020 ap->ability_match = 1;
5021 ap->ability_match_cfg = rx_cfg_reg;
5024 if (rx_cfg_reg & ANEG_CFG_ACK)
5032 ap->ability_match_cfg = 0;
5033 ap->ability_match_count = 0;
5034 ap->ability_match = 0;
5040 ap->rxconfig = rx_cfg_reg;
5043 switch (ap->state) {
5044 case ANEG_STATE_UNKNOWN:
5045 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5046 ap->state = ANEG_STATE_AN_ENABLE;
5049 case ANEG_STATE_AN_ENABLE:
5050 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5051 if (ap->flags & MR_AN_ENABLE) {
5054 ap->ability_match_cfg = 0;
5055 ap->ability_match_count = 0;
5056 ap->ability_match = 0;
5060 ap->state = ANEG_STATE_RESTART_INIT;
5062 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5066 case ANEG_STATE_RESTART_INIT:
5067 ap->link_time = ap->cur_time;
5068 ap->flags &= ~(MR_NP_LOADED);
5070 tw32(MAC_TX_AUTO_NEG, 0);
5071 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5072 tw32_f(MAC_MODE, tp->mac_mode);
5075 ret = ANEG_TIMER_ENAB;
5076 ap->state = ANEG_STATE_RESTART;
5079 case ANEG_STATE_RESTART:
5080 delta = ap->cur_time - ap->link_time;
5081 if (delta > ANEG_STATE_SETTLE_TIME)
5082 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
5084 ret = ANEG_TIMER_ENAB;
5087 case ANEG_STATE_DISABLE_LINK_OK:
5091 case ANEG_STATE_ABILITY_DETECT_INIT:
5092 ap->flags &= ~(MR_TOGGLE_TX);
5093 ap->txconfig = ANEG_CFG_FD;
5094 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5095 if (flowctrl & ADVERTISE_1000XPAUSE)
5096 ap->txconfig |= ANEG_CFG_PS1;
5097 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5098 ap->txconfig |= ANEG_CFG_PS2;
5099 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5100 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5101 tw32_f(MAC_MODE, tp->mac_mode);
5104 ap->state = ANEG_STATE_ABILITY_DETECT;
5107 case ANEG_STATE_ABILITY_DETECT:
5108 if (ap->ability_match != 0 && ap->rxconfig != 0)
5109 ap->state = ANEG_STATE_ACK_DETECT_INIT;
5112 case ANEG_STATE_ACK_DETECT_INIT:
5113 ap->txconfig |= ANEG_CFG_ACK;
5114 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5115 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5116 tw32_f(MAC_MODE, tp->mac_mode);
5119 ap->state = ANEG_STATE_ACK_DETECT;
5122 case ANEG_STATE_ACK_DETECT:
5123 if (ap->ack_match != 0) {
5124 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5125 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5126 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5128 ap->state = ANEG_STATE_AN_ENABLE;
5130 } else if (ap->ability_match != 0 &&
5131 ap->rxconfig == 0) {
5132 ap->state = ANEG_STATE_AN_ENABLE;
5136 case ANEG_STATE_COMPLETE_ACK_INIT:
5137 if (ap->rxconfig & ANEG_CFG_INVAL) {
5141 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5142 MR_LP_ADV_HALF_DUPLEX |
5143 MR_LP_ADV_SYM_PAUSE |
5144 MR_LP_ADV_ASYM_PAUSE |
5145 MR_LP_ADV_REMOTE_FAULT1 |
5146 MR_LP_ADV_REMOTE_FAULT2 |
5147 MR_LP_ADV_NEXT_PAGE |
5150 if (ap->rxconfig & ANEG_CFG_FD)
5151 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5152 if (ap->rxconfig & ANEG_CFG_HD)
5153 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5154 if (ap->rxconfig & ANEG_CFG_PS1)
5155 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5156 if (ap->rxconfig & ANEG_CFG_PS2)
5157 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5158 if (ap->rxconfig & ANEG_CFG_RF1)
5159 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5160 if (ap->rxconfig & ANEG_CFG_RF2)
5161 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5162 if (ap->rxconfig & ANEG_CFG_NP)
5163 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5165 ap->link_time = ap->cur_time;
5167 ap->flags ^= (MR_TOGGLE_TX);
5168 if (ap->rxconfig & 0x0008)
5169 ap->flags |= MR_TOGGLE_RX;
5170 if (ap->rxconfig & ANEG_CFG_NP)
5171 ap->flags |= MR_NP_RX;
5172 ap->flags |= MR_PAGE_RX;
5174 ap->state = ANEG_STATE_COMPLETE_ACK;
5175 ret = ANEG_TIMER_ENAB;
5178 case ANEG_STATE_COMPLETE_ACK:
5179 if (ap->ability_match != 0 &&
5180 ap->rxconfig == 0) {
5181 ap->state = ANEG_STATE_AN_ENABLE;
5184 delta = ap->cur_time - ap->link_time;
5185 if (delta > ANEG_STATE_SETTLE_TIME) {
5186 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5187 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5189 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5190 !(ap->flags & MR_NP_RX)) {
5191 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5199 case ANEG_STATE_IDLE_DETECT_INIT:
5200 ap->link_time = ap->cur_time;
5201 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5202 tw32_f(MAC_MODE, tp->mac_mode);
5205 ap->state = ANEG_STATE_IDLE_DETECT;
5206 ret = ANEG_TIMER_ENAB;
5209 case ANEG_STATE_IDLE_DETECT:
5210 if (ap->ability_match != 0 &&
5211 ap->rxconfig == 0) {
5212 ap->state = ANEG_STATE_AN_ENABLE;
5215 delta = ap->cur_time - ap->link_time;
5216 if (delta > ANEG_STATE_SETTLE_TIME) {
5217 /* XXX another gem from the Broadcom driver :( */
5218 ap->state = ANEG_STATE_LINK_OK;
5222 case ANEG_STATE_LINK_OK:
5223 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5227 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5228 /* ??? unimplemented */
5231 case ANEG_STATE_NEXT_PAGE_WAIT:
5232 /* ??? unimplemented */
5243 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5246 struct tg3_fiber_aneginfo aninfo;
5247 int status = ANEG_FAILED;
5251 tw32_f(MAC_TX_AUTO_NEG, 0);
5253 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5254 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5257 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5260 memset(&aninfo, 0, sizeof(aninfo));
5261 aninfo.flags |= MR_AN_ENABLE;
5262 aninfo.state = ANEG_STATE_UNKNOWN;
5263 aninfo.cur_time = 0;
5265 while (++tick < 195000) {
5266 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5267 if (status == ANEG_DONE || status == ANEG_FAILED)
5273 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5274 tw32_f(MAC_MODE, tp->mac_mode);
5277 *txflags = aninfo.txconfig;
5278 *rxflags = aninfo.flags;
5280 if (status == ANEG_DONE &&
5281 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5282 MR_LP_ADV_FULL_DUPLEX)))
5288 static void tg3_init_bcm8002(struct tg3 *tp)
5290 u32 mac_status = tr32(MAC_STATUS);
5293 /* Reset when initting first time or we have a link. */
5294 if (tg3_flag(tp, INIT_COMPLETE) &&
5295 !(mac_status & MAC_STATUS_PCS_SYNCED))
5298 /* Set PLL lock range. */
5299 tg3_writephy(tp, 0x16, 0x8007);
5302 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5304 /* Wait for reset to complete. */
5305 /* XXX schedule_timeout() ... */
5306 for (i = 0; i < 500; i++)
5309 /* Config mode; select PMA/Ch 1 regs. */
5310 tg3_writephy(tp, 0x10, 0x8411);
5312 /* Enable auto-lock and comdet, select txclk for tx. */
5313 tg3_writephy(tp, 0x11, 0x0a10);
5315 tg3_writephy(tp, 0x18, 0x00a0);
5316 tg3_writephy(tp, 0x16, 0x41ff);
5318 /* Assert and deassert POR. */
5319 tg3_writephy(tp, 0x13, 0x0400);
5321 tg3_writephy(tp, 0x13, 0x0000);
5323 tg3_writephy(tp, 0x11, 0x0a50);
5325 tg3_writephy(tp, 0x11, 0x0a10);
5327 /* Wait for signal to stabilize */
5328 /* XXX schedule_timeout() ... */
5329 for (i = 0; i < 15000; i++)
5332 /* Deselect the channel register so we can read the PHYID
5335 tg3_writephy(tp, 0x10, 0x8011);
5338 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5341 u32 sg_dig_ctrl, sg_dig_status;
5342 u32 serdes_cfg, expected_sg_dig_ctrl;
5343 int workaround, port_a;
5344 int current_link_up;
5347 expected_sg_dig_ctrl = 0;
5350 current_link_up = 0;
5352 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5353 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5355 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5358 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5359 /* preserve bits 20-23 for voltage regulator */
5360 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5363 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5365 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5366 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
5368 u32 val = serdes_cfg;
5374 tw32_f(MAC_SERDES_CFG, val);
5377 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5379 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5380 tg3_setup_flow_control(tp, 0, 0);
5381 current_link_up = 1;
5386 /* Want auto-negotiation. */
5387 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
5389 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5390 if (flowctrl & ADVERTISE_1000XPAUSE)
5391 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5392 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5393 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
5395 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
5396 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5397 tp->serdes_counter &&
5398 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5399 MAC_STATUS_RCVD_CFG)) ==
5400 MAC_STATUS_PCS_SYNCED)) {
5401 tp->serdes_counter--;
5402 current_link_up = 1;
5407 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5408 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5410 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5412 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5413 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5414 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5415 MAC_STATUS_SIGNAL_DET)) {
5416 sg_dig_status = tr32(SG_DIG_STATUS);
5417 mac_status = tr32(MAC_STATUS);
5419 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
5420 (mac_status & MAC_STATUS_PCS_SYNCED)) {
5421 u32 local_adv = 0, remote_adv = 0;
5423 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5424 local_adv |= ADVERTISE_1000XPAUSE;
5425 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5426 local_adv |= ADVERTISE_1000XPSE_ASYM;
5428 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
5429 remote_adv |= LPA_1000XPAUSE;
5430 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
5431 remote_adv |= LPA_1000XPAUSE_ASYM;
5433 tp->link_config.rmt_adv =
5434 mii_adv_to_ethtool_adv_x(remote_adv);
5436 tg3_setup_flow_control(tp, local_adv, remote_adv);
5437 current_link_up = 1;
5438 tp->serdes_counter = 0;
5439 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5440 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
5441 if (tp->serdes_counter)
5442 tp->serdes_counter--;
5445 u32 val = serdes_cfg;
5452 tw32_f(MAC_SERDES_CFG, val);
5455 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5458 /* Link parallel detection - link is up */
5459 /* only if we have PCS_SYNC and not */
5460 /* receiving config code words */
5461 mac_status = tr32(MAC_STATUS);
5462 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5463 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5464 tg3_setup_flow_control(tp, 0, 0);
5465 current_link_up = 1;
5467 TG3_PHYFLG_PARALLEL_DETECT;
5468 tp->serdes_counter =
5469 SERDES_PARALLEL_DET_TIMEOUT;
5471 goto restart_autoneg;
5475 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5476 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5480 return current_link_up;
5483 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5485 int current_link_up = 0;
5487 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5490 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5491 u32 txflags, rxflags;
5494 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5495 u32 local_adv = 0, remote_adv = 0;
5497 if (txflags & ANEG_CFG_PS1)
5498 local_adv |= ADVERTISE_1000XPAUSE;
5499 if (txflags & ANEG_CFG_PS2)
5500 local_adv |= ADVERTISE_1000XPSE_ASYM;
5502 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5503 remote_adv |= LPA_1000XPAUSE;
5504 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5505 remote_adv |= LPA_1000XPAUSE_ASYM;
5507 tp->link_config.rmt_adv =
5508 mii_adv_to_ethtool_adv_x(remote_adv);
5510 tg3_setup_flow_control(tp, local_adv, remote_adv);
5512 current_link_up = 1;
5514 for (i = 0; i < 30; i++) {
5517 (MAC_STATUS_SYNC_CHANGED |
5518 MAC_STATUS_CFG_CHANGED));
5520 if ((tr32(MAC_STATUS) &
5521 (MAC_STATUS_SYNC_CHANGED |
5522 MAC_STATUS_CFG_CHANGED)) == 0)
5526 mac_status = tr32(MAC_STATUS);
5527 if (current_link_up == 0 &&
5528 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5529 !(mac_status & MAC_STATUS_RCVD_CFG))
5530 current_link_up = 1;
5532 tg3_setup_flow_control(tp, 0, 0);
5534 /* Forcing 1000FD link up. */
5535 current_link_up = 1;
5537 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5540 tw32_f(MAC_MODE, tp->mac_mode);
5545 return current_link_up;
5548 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
5551 u16 orig_active_speed;
5552 u8 orig_active_duplex;
5554 int current_link_up;
5557 orig_pause_cfg = tp->link_config.active_flowctrl;
5558 orig_active_speed = tp->link_config.active_speed;
5559 orig_active_duplex = tp->link_config.active_duplex;
5561 if (!tg3_flag(tp, HW_AUTONEG) &&
5563 tg3_flag(tp, INIT_COMPLETE)) {
5564 mac_status = tr32(MAC_STATUS);
5565 mac_status &= (MAC_STATUS_PCS_SYNCED |
5566 MAC_STATUS_SIGNAL_DET |
5567 MAC_STATUS_CFG_CHANGED |
5568 MAC_STATUS_RCVD_CFG);
5569 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5570 MAC_STATUS_SIGNAL_DET)) {
5571 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5572 MAC_STATUS_CFG_CHANGED));
5577 tw32_f(MAC_TX_AUTO_NEG, 0);
5579 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5580 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5581 tw32_f(MAC_MODE, tp->mac_mode);
5584 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5585 tg3_init_bcm8002(tp);
5587 /* Enable link change event even when serdes polling. */
5588 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5591 current_link_up = 0;
5592 tp->link_config.rmt_adv = 0;
5593 mac_status = tr32(MAC_STATUS);
5595 if (tg3_flag(tp, HW_AUTONEG))
5596 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5598 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5600 tp->napi[0].hw_status->status =
5601 (SD_STATUS_UPDATED |
5602 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5604 for (i = 0; i < 100; i++) {
5605 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5606 MAC_STATUS_CFG_CHANGED));
5608 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5609 MAC_STATUS_CFG_CHANGED |
5610 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5614 mac_status = tr32(MAC_STATUS);
5615 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5616 current_link_up = 0;
5617 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5618 tp->serdes_counter == 0) {
5619 tw32_f(MAC_MODE, (tp->mac_mode |
5620 MAC_MODE_SEND_CONFIGS));
5622 tw32_f(MAC_MODE, tp->mac_mode);
5626 if (current_link_up == 1) {
5627 tp->link_config.active_speed = SPEED_1000;
5628 tp->link_config.active_duplex = DUPLEX_FULL;
5629 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5630 LED_CTRL_LNKLED_OVERRIDE |
5631 LED_CTRL_1000MBPS_ON));
5633 tp->link_config.active_speed = SPEED_UNKNOWN;
5634 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5635 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5636 LED_CTRL_LNKLED_OVERRIDE |
5637 LED_CTRL_TRAFFIC_OVERRIDE));
5640 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5641 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5642 if (orig_pause_cfg != now_pause_cfg ||
5643 orig_active_speed != tp->link_config.active_speed ||
5644 orig_active_duplex != tp->link_config.active_duplex)
5645 tg3_link_report(tp);
5651 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
5653 int current_link_up = 0, err = 0;
5655 u16 current_speed = SPEED_UNKNOWN;
5656 u8 current_duplex = DUPLEX_UNKNOWN;
5657 u32 local_adv, remote_adv, sgsr;
5659 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5660 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5661 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5662 (sgsr & SERDES_TG3_SGMII_MODE)) {
5667 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5669 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5670 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5672 current_link_up = 1;
5673 if (sgsr & SERDES_TG3_SPEED_1000) {
5674 current_speed = SPEED_1000;
5675 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5676 } else if (sgsr & SERDES_TG3_SPEED_100) {
5677 current_speed = SPEED_100;
5678 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5680 current_speed = SPEED_10;
5681 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5684 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5685 current_duplex = DUPLEX_FULL;
5687 current_duplex = DUPLEX_HALF;
5690 tw32_f(MAC_MODE, tp->mac_mode);
5693 tg3_clear_mac_status(tp);
5695 goto fiber_setup_done;
5698 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5699 tw32_f(MAC_MODE, tp->mac_mode);
5702 tg3_clear_mac_status(tp);
5707 tp->link_config.rmt_adv = 0;
5709 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5710 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5711 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5712 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5713 bmsr |= BMSR_LSTATUS;
5715 bmsr &= ~BMSR_LSTATUS;
5718 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5720 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5721 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5722 /* do nothing, just check for link up at the end */
5723 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5726 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5727 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5728 ADVERTISE_1000XPAUSE |
5729 ADVERTISE_1000XPSE_ASYM |
5732 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5733 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5735 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5736 tg3_writephy(tp, MII_ADVERTISE, newadv);
5737 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5738 tg3_writephy(tp, MII_BMCR, bmcr);
5740 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5741 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5742 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5749 bmcr &= ~BMCR_SPEED1000;
5750 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5752 if (tp->link_config.duplex == DUPLEX_FULL)
5753 new_bmcr |= BMCR_FULLDPLX;
5755 if (new_bmcr != bmcr) {
5756 /* BMCR_SPEED1000 is a reserved bit that needs
5757 * to be set on write.
5759 new_bmcr |= BMCR_SPEED1000;
5761 /* Force a linkdown */
5765 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5766 adv &= ~(ADVERTISE_1000XFULL |
5767 ADVERTISE_1000XHALF |
5769 tg3_writephy(tp, MII_ADVERTISE, adv);
5770 tg3_writephy(tp, MII_BMCR, bmcr |
5774 tg3_carrier_off(tp);
5776 tg3_writephy(tp, MII_BMCR, new_bmcr);
5778 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5779 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5780 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5781 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5782 bmsr |= BMSR_LSTATUS;
5784 bmsr &= ~BMSR_LSTATUS;
5786 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5790 if (bmsr & BMSR_LSTATUS) {
5791 current_speed = SPEED_1000;
5792 current_link_up = 1;
5793 if (bmcr & BMCR_FULLDPLX)
5794 current_duplex = DUPLEX_FULL;
5796 current_duplex = DUPLEX_HALF;
5801 if (bmcr & BMCR_ANENABLE) {
5804 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5805 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5806 common = local_adv & remote_adv;
5807 if (common & (ADVERTISE_1000XHALF |
5808 ADVERTISE_1000XFULL)) {
5809 if (common & ADVERTISE_1000XFULL)
5810 current_duplex = DUPLEX_FULL;
5812 current_duplex = DUPLEX_HALF;
5814 tp->link_config.rmt_adv =
5815 mii_adv_to_ethtool_adv_x(remote_adv);
5816 } else if (!tg3_flag(tp, 5780_CLASS)) {
5817 /* Link is up via parallel detect */
5819 current_link_up = 0;
5825 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
5826 tg3_setup_flow_control(tp, local_adv, remote_adv);
5828 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5829 if (tp->link_config.active_duplex == DUPLEX_HALF)
5830 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5832 tw32_f(MAC_MODE, tp->mac_mode);
5835 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5837 tp->link_config.active_speed = current_speed;
5838 tp->link_config.active_duplex = current_duplex;
5840 tg3_test_and_report_link_chg(tp, current_link_up);
5844 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5846 if (tp->serdes_counter) {
5847 /* Give autoneg time to complete. */
5848 tp->serdes_counter--;
5853 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5856 tg3_readphy(tp, MII_BMCR, &bmcr);
5857 if (bmcr & BMCR_ANENABLE) {
5860 /* Select shadow register 0x1f */
5861 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5862 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
5864 /* Select expansion interrupt status register */
5865 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5866 MII_TG3_DSP_EXP1_INT_STAT);
5867 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5868 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5870 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5871 /* We have signal detect and not receiving
5872 * config code words, link is up by parallel
5876 bmcr &= ~BMCR_ANENABLE;
5877 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5878 tg3_writephy(tp, MII_BMCR, bmcr);
5879 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
5882 } else if (tp->link_up &&
5883 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
5884 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5887 /* Select expansion interrupt status register */
5888 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5889 MII_TG3_DSP_EXP1_INT_STAT);
5890 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5894 /* Config code words received, turn on autoneg. */
5895 tg3_readphy(tp, MII_BMCR, &bmcr);
5896 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5898 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5904 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5909 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
5910 err = tg3_setup_fiber_phy(tp, force_reset);
5911 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
5912 err = tg3_setup_fiber_mii_phy(tp, force_reset);
5914 err = tg3_setup_copper_phy(tp, force_reset);
5916 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
5919 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
5920 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5922 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5927 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
5928 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5929 tw32(GRC_MISC_CFG, val);
5932 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5933 (6 << TX_LENGTHS_IPG_SHIFT);
5934 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
5935 tg3_asic_rev(tp) == ASIC_REV_5762)
5936 val |= tr32(MAC_TX_LENGTHS) &
5937 (TX_LENGTHS_JMB_FRM_LEN_MSK |
5938 TX_LENGTHS_CNT_DWN_VAL_MSK);
5940 if (tp->link_config.active_speed == SPEED_1000 &&
5941 tp->link_config.active_duplex == DUPLEX_HALF)
5942 tw32(MAC_TX_LENGTHS, val |
5943 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
5945 tw32(MAC_TX_LENGTHS, val |
5946 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5948 if (!tg3_flag(tp, 5705_PLUS)) {
5950 tw32(HOSTCC_STAT_COAL_TICKS,
5951 tp->coal.stats_block_coalesce_usecs);
5953 tw32(HOSTCC_STAT_COAL_TICKS, 0);
5957 if (tg3_flag(tp, ASPM_WORKAROUND)) {
5958 val = tr32(PCIE_PWR_MGMT_THRESH);
5960 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5963 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
5964 tw32(PCIE_PWR_MGMT_THRESH, val);
5970 /* tp->lock must be held */
5971 static u64 tg3_refclk_read(struct tg3 *tp)
5973 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
5974 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
5977 /* tp->lock must be held */
5978 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
5980 tw32(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_STOP);
5981 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
5982 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
5983 tw32_f(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_RESUME);
5986 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
5987 static inline void tg3_full_unlock(struct tg3 *tp);
5988 static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
5990 struct tg3 *tp = netdev_priv(dev);
5992 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
5993 SOF_TIMESTAMPING_RX_SOFTWARE |
5994 SOF_TIMESTAMPING_SOFTWARE |
5995 SOF_TIMESTAMPING_TX_HARDWARE |
5996 SOF_TIMESTAMPING_RX_HARDWARE |
5997 SOF_TIMESTAMPING_RAW_HARDWARE;
6000 info->phc_index = ptp_clock_index(tp->ptp_clock);
6002 info->phc_index = -1;
6004 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6006 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6007 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6008 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6009 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6013 static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6015 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6016 bool neg_adj = false;
6024 /* Frequency adjustment is performed using hardware with a 24 bit
6025 * accumulator and a programmable correction value. On each clk, the
6026 * correction value gets added to the accumulator and when it
6027 * overflows, the time counter is incremented/decremented.
6029 * So conversion from ppb to correction value is
6030 * ppb * (1 << 24) / 1000000000
6032 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6033 TG3_EAV_REF_CLK_CORRECT_MASK;
6035 tg3_full_lock(tp, 0);
6038 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6039 TG3_EAV_REF_CLK_CORRECT_EN |
6040 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6042 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6044 tg3_full_unlock(tp);
6049 static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6051 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6053 tg3_full_lock(tp, 0);
6054 tp->ptp_adjust += delta;
6055 tg3_full_unlock(tp);
6060 static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6064 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6066 tg3_full_lock(tp, 0);
6067 ns = tg3_refclk_read(tp);
6068 ns += tp->ptp_adjust;
6069 tg3_full_unlock(tp);
6071 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6072 ts->tv_nsec = remainder;
6077 static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6078 const struct timespec *ts)
6081 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6083 ns = timespec_to_ns(ts);
6085 tg3_full_lock(tp, 0);
6086 tg3_refclk_write(tp, ns);
6088 tg3_full_unlock(tp);
6093 static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6094 struct ptp_clock_request *rq, int on)
6099 static const struct ptp_clock_info tg3_ptp_caps = {
6100 .owner = THIS_MODULE,
6101 .name = "tg3 clock",
6102 .max_adj = 250000000,
6107 .adjfreq = tg3_ptp_adjfreq,
6108 .adjtime = tg3_ptp_adjtime,
6109 .gettime = tg3_ptp_gettime,
6110 .settime = tg3_ptp_settime,
6111 .enable = tg3_ptp_enable,
6114 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6115 struct skb_shared_hwtstamps *timestamp)
6117 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6118 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6122 /* tp->lock must be held */
6123 static void tg3_ptp_init(struct tg3 *tp)
6125 if (!tg3_flag(tp, PTP_CAPABLE))
6128 /* Initialize the hardware clock to the system time. */
6129 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6131 tp->ptp_info = tg3_ptp_caps;
6134 /* tp->lock must be held */
6135 static void tg3_ptp_resume(struct tg3 *tp)
6137 if (!tg3_flag(tp, PTP_CAPABLE))
6140 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6144 static void tg3_ptp_fini(struct tg3 *tp)
6146 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6149 ptp_clock_unregister(tp->ptp_clock);
6150 tp->ptp_clock = NULL;
6154 static inline int tg3_irq_sync(struct tg3 *tp)
6156 return tp->irq_sync;
6159 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6163 dst = (u32 *)((u8 *)dst + off);
6164 for (i = 0; i < len; i += sizeof(u32))
6165 *dst++ = tr32(off + i);
6168 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6170 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6171 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6172 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6173 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6174 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6175 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6176 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6177 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6178 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6179 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6180 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6181 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6182 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6183 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6184 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6185 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6186 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6187 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6188 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6190 if (tg3_flag(tp, SUPPORT_MSIX))
6191 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6193 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6194 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6195 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6196 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6197 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6198 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6199 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6200 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6202 if (!tg3_flag(tp, 5705_PLUS)) {
6203 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6204 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6205 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6208 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6209 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6210 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6211 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6212 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6214 if (tg3_flag(tp, NVRAM))
6215 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6218 static void tg3_dump_state(struct tg3 *tp)
6223 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
6227 if (tg3_flag(tp, PCI_EXPRESS)) {
6228 /* Read up to but not including private PCI registers */
6229 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6230 regs[i / sizeof(u32)] = tr32(i);
6232 tg3_dump_legacy_regs(tp, regs);
6234 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6235 if (!regs[i + 0] && !regs[i + 1] &&
6236 !regs[i + 2] && !regs[i + 3])
6239 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6241 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6246 for (i = 0; i < tp->irq_cnt; i++) {
6247 struct tg3_napi *tnapi = &tp->napi[i];
6249 /* SW status block */
6251 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6253 tnapi->hw_status->status,
6254 tnapi->hw_status->status_tag,
6255 tnapi->hw_status->rx_jumbo_consumer,
6256 tnapi->hw_status->rx_consumer,
6257 tnapi->hw_status->rx_mini_consumer,
6258 tnapi->hw_status->idx[0].rx_producer,
6259 tnapi->hw_status->idx[0].tx_consumer);
6262 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6264 tnapi->last_tag, tnapi->last_irq_tag,
6265 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6267 tnapi->prodring.rx_std_prod_idx,
6268 tnapi->prodring.rx_std_cons_idx,
6269 tnapi->prodring.rx_jmb_prod_idx,
6270 tnapi->prodring.rx_jmb_cons_idx);
6274 /* This is called whenever we suspect that the system chipset is re-
6275 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6276 * is bogus tx completions. We try to recover by setting the
6277 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6280 static void tg3_tx_recover(struct tg3 *tp)
6282 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6283 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6285 netdev_warn(tp->dev,
6286 "The system may be re-ordering memory-mapped I/O "
6287 "cycles to the network device, attempting to recover. "
6288 "Please report the problem to the driver maintainer "
6289 "and include system chipset information.\n");
6291 spin_lock(&tp->lock);
6292 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6293 spin_unlock(&tp->lock);
6296 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
6298 /* Tell compiler to fetch tx indices from memory. */
6300 return tnapi->tx_pending -
6301 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
6304 /* Tigon3 never reports partial packet sends. So we do not
6305 * need special logic to handle SKBs that have not had all
6306 * of their frags sent yet, like SunGEM does.
6308 static void tg3_tx(struct tg3_napi *tnapi)
6310 struct tg3 *tp = tnapi->tp;
6311 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
6312 u32 sw_idx = tnapi->tx_cons;
6313 struct netdev_queue *txq;
6314 int index = tnapi - tp->napi;
6315 unsigned int pkts_compl = 0, bytes_compl = 0;
6317 if (tg3_flag(tp, ENABLE_TSS))
6320 txq = netdev_get_tx_queue(tp->dev, index);
6322 while (sw_idx != hw_idx) {
6323 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
6324 struct sk_buff *skb = ri->skb;
6327 if (unlikely(skb == NULL)) {
6332 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6333 struct skb_shared_hwtstamps timestamp;
6334 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6335 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6337 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6339 skb_tstamp_tx(skb, ×tamp);
6342 pci_unmap_single(tp->pdev,
6343 dma_unmap_addr(ri, mapping),
6349 while (ri->fragmented) {
6350 ri->fragmented = false;
6351 sw_idx = NEXT_TX(sw_idx);
6352 ri = &tnapi->tx_buffers[sw_idx];
6355 sw_idx = NEXT_TX(sw_idx);
6357 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6358 ri = &tnapi->tx_buffers[sw_idx];
6359 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6362 pci_unmap_page(tp->pdev,
6363 dma_unmap_addr(ri, mapping),
6364 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6367 while (ri->fragmented) {
6368 ri->fragmented = false;
6369 sw_idx = NEXT_TX(sw_idx);
6370 ri = &tnapi->tx_buffers[sw_idx];
6373 sw_idx = NEXT_TX(sw_idx);
6377 bytes_compl += skb->len;
6381 if (unlikely(tx_bug)) {
6387 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
6389 tnapi->tx_cons = sw_idx;
6391 /* Need to make the tx_cons update visible to tg3_start_xmit()
6392 * before checking for netif_queue_stopped(). Without the
6393 * memory barrier, there is a small possibility that tg3_start_xmit()
6394 * will miss it and cause the queue to be stopped forever.
6398 if (unlikely(netif_tx_queue_stopped(txq) &&
6399 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
6400 __netif_tx_lock(txq, smp_processor_id());
6401 if (netif_tx_queue_stopped(txq) &&
6402 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
6403 netif_tx_wake_queue(txq);
6404 __netif_tx_unlock(txq);
6408 static void tg3_frag_free(bool is_frag, void *data)
6411 put_page(virt_to_head_page(data));
6416 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6418 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6419 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6424 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
6425 map_sz, PCI_DMA_FROMDEVICE);
6426 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
6431 /* Returns size of skb allocated or < 0 on error.
6433 * We only need to fill in the address because the other members
6434 * of the RX descriptor are invariant, see tg3_init_rings.
6436 * Note the purposeful assymetry of cpu vs. chip accesses. For
6437 * posting buffers we only dirty the first cache line of the RX
6438 * descriptor (containing the address). Whereas for the RX status
6439 * buffers the cpu only reads the last cacheline of the RX descriptor
6440 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6442 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6443 u32 opaque_key, u32 dest_idx_unmasked,
6444 unsigned int *frag_size)
6446 struct tg3_rx_buffer_desc *desc;
6447 struct ring_info *map;
6450 int skb_size, data_size, dest_idx;
6452 switch (opaque_key) {
6453 case RXD_OPAQUE_RING_STD:
6454 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6455 desc = &tpr->rx_std[dest_idx];
6456 map = &tpr->rx_std_buffers[dest_idx];
6457 data_size = tp->rx_pkt_map_sz;
6460 case RXD_OPAQUE_RING_JUMBO:
6461 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6462 desc = &tpr->rx_jmb[dest_idx].std;
6463 map = &tpr->rx_jmb_buffers[dest_idx];
6464 data_size = TG3_RX_JMB_MAP_SZ;
6471 /* Do not overwrite any of the map or rp information
6472 * until we are sure we can commit to a new buffer.
6474 * Callers depend upon this behavior and assume that
6475 * we leave everything unchanged if we fail.
6477 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6478 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6479 if (skb_size <= PAGE_SIZE) {
6480 data = netdev_alloc_frag(skb_size);
6481 *frag_size = skb_size;
6483 data = kmalloc(skb_size, GFP_ATOMIC);
6489 mapping = pci_map_single(tp->pdev,
6490 data + TG3_RX_OFFSET(tp),
6492 PCI_DMA_FROMDEVICE);
6493 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
6494 tg3_frag_free(skb_size <= PAGE_SIZE, data);
6499 dma_unmap_addr_set(map, mapping, mapping);
6501 desc->addr_hi = ((u64)mapping >> 32);
6502 desc->addr_lo = ((u64)mapping & 0xffffffff);
6507 /* We only need to move over in the address because the other
6508 * members of the RX descriptor are invariant. See notes above
6509 * tg3_alloc_rx_data for full details.
6511 static void tg3_recycle_rx(struct tg3_napi *tnapi,
6512 struct tg3_rx_prodring_set *dpr,
6513 u32 opaque_key, int src_idx,
6514 u32 dest_idx_unmasked)
6516 struct tg3 *tp = tnapi->tp;
6517 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6518 struct ring_info *src_map, *dest_map;
6519 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6522 switch (opaque_key) {
6523 case RXD_OPAQUE_RING_STD:
6524 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6525 dest_desc = &dpr->rx_std[dest_idx];
6526 dest_map = &dpr->rx_std_buffers[dest_idx];
6527 src_desc = &spr->rx_std[src_idx];
6528 src_map = &spr->rx_std_buffers[src_idx];
6531 case RXD_OPAQUE_RING_JUMBO:
6532 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6533 dest_desc = &dpr->rx_jmb[dest_idx].std;
6534 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6535 src_desc = &spr->rx_jmb[src_idx].std;
6536 src_map = &spr->rx_jmb_buffers[src_idx];
6543 dest_map->data = src_map->data;
6544 dma_unmap_addr_set(dest_map, mapping,
6545 dma_unmap_addr(src_map, mapping));
6546 dest_desc->addr_hi = src_desc->addr_hi;
6547 dest_desc->addr_lo = src_desc->addr_lo;
6549 /* Ensure that the update to the skb happens after the physical
6550 * addresses have been transferred to the new BD location.
6554 src_map->data = NULL;
6557 /* The RX ring scheme is composed of multiple rings which post fresh
6558 * buffers to the chip, and one special ring the chip uses to report
6559 * status back to the host.
6561 * The special ring reports the status of received packets to the
6562 * host. The chip does not write into the original descriptor the
6563 * RX buffer was obtained from. The chip simply takes the original
6564 * descriptor as provided by the host, updates the status and length
6565 * field, then writes this into the next status ring entry.
6567 * Each ring the host uses to post buffers to the chip is described
6568 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6569 * it is first placed into the on-chip ram. When the packet's length
6570 * is known, it walks down the TG3_BDINFO entries to select the ring.
6571 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6572 * which is within the range of the new packet's length is chosen.
6574 * The "separate ring for rx status" scheme may sound queer, but it makes
6575 * sense from a cache coherency perspective. If only the host writes
6576 * to the buffer post rings, and only the chip writes to the rx status
6577 * rings, then cache lines never move beyond shared-modified state.
6578 * If both the host and chip were to write into the same ring, cache line
6579 * eviction could occur since both entities want it in an exclusive state.
6581 static int tg3_rx(struct tg3_napi *tnapi, int budget)
6583 struct tg3 *tp = tnapi->tp;
6584 u32 work_mask, rx_std_posted = 0;
6585 u32 std_prod_idx, jmb_prod_idx;
6586 u32 sw_idx = tnapi->rx_rcb_ptr;
6589 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
6591 hw_idx = *(tnapi->rx_rcb_prod_idx);
6593 * We need to order the read of hw_idx and the read of
6594 * the opaque cookie.
6599 std_prod_idx = tpr->rx_std_prod_idx;
6600 jmb_prod_idx = tpr->rx_jmb_prod_idx;
6601 while (sw_idx != hw_idx && budget > 0) {
6602 struct ring_info *ri;
6603 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
6605 struct sk_buff *skb;
6606 dma_addr_t dma_addr;
6607 u32 opaque_key, desc_idx, *post_ptr;
6611 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6612 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6613 if (opaque_key == RXD_OPAQUE_RING_STD) {
6614 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6615 dma_addr = dma_unmap_addr(ri, mapping);
6617 post_ptr = &std_prod_idx;
6619 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
6620 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6621 dma_addr = dma_unmap_addr(ri, mapping);
6623 post_ptr = &jmb_prod_idx;
6625 goto next_pkt_nopost;
6627 work_mask |= opaque_key;
6629 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
6630 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
6632 tg3_recycle_rx(tnapi, tpr, opaque_key,
6633 desc_idx, *post_ptr);
6635 /* Other statistics kept track of by card. */
6640 prefetch(data + TG3_RX_OFFSET(tp));
6641 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6644 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6645 RXD_FLAG_PTPSTAT_PTPV1 ||
6646 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6647 RXD_FLAG_PTPSTAT_PTPV2) {
6648 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6649 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6652 if (len > TG3_RX_COPY_THRESH(tp)) {
6654 unsigned int frag_size;
6656 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6657 *post_ptr, &frag_size);
6661 pci_unmap_single(tp->pdev, dma_addr, skb_size,
6662 PCI_DMA_FROMDEVICE);
6664 skb = build_skb(data, frag_size);
6666 tg3_frag_free(frag_size != 0, data);
6667 goto drop_it_no_recycle;
6669 skb_reserve(skb, TG3_RX_OFFSET(tp));
6670 /* Ensure that the update to the data happens
6671 * after the usage of the old DMA mapping.
6678 tg3_recycle_rx(tnapi, tpr, opaque_key,
6679 desc_idx, *post_ptr);
6681 skb = netdev_alloc_skb(tp->dev,
6682 len + TG3_RAW_IP_ALIGN);
6684 goto drop_it_no_recycle;
6686 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6687 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6689 data + TG3_RX_OFFSET(tp),
6691 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6696 tg3_hwclock_to_timestamp(tp, tstamp,
6697 skb_hwtstamps(skb));
6699 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6700 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6701 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6702 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6703 skb->ip_summed = CHECKSUM_UNNECESSARY;
6705 skb_checksum_none_assert(skb);
6707 skb->protocol = eth_type_trans(skb, tp->dev);
6709 if (len > (tp->dev->mtu + ETH_HLEN) &&
6710 skb->protocol != htons(ETH_P_8021Q)) {
6712 goto drop_it_no_recycle;
6715 if (desc->type_flags & RXD_FLAG_VLAN &&
6716 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6717 __vlan_hwaccel_put_tag(skb,
6718 desc->err_vlan & RXD_VLAN_MASK);
6720 napi_gro_receive(&tnapi->napi, skb);
6728 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6729 tpr->rx_std_prod_idx = std_prod_idx &
6730 tp->rx_std_ring_mask;
6731 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6732 tpr->rx_std_prod_idx);
6733 work_mask &= ~RXD_OPAQUE_RING_STD;
6738 sw_idx &= tp->rx_ret_ring_mask;
6740 /* Refresh hw_idx to see if there is new work */
6741 if (sw_idx == hw_idx) {
6742 hw_idx = *(tnapi->rx_rcb_prod_idx);
6747 /* ACK the status ring. */
6748 tnapi->rx_rcb_ptr = sw_idx;
6749 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6751 /* Refill RX ring(s). */
6752 if (!tg3_flag(tp, ENABLE_RSS)) {
6753 /* Sync BD data before updating mailbox */
6756 if (work_mask & RXD_OPAQUE_RING_STD) {
6757 tpr->rx_std_prod_idx = std_prod_idx &
6758 tp->rx_std_ring_mask;
6759 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6760 tpr->rx_std_prod_idx);
6762 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6763 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6764 tp->rx_jmb_ring_mask;
6765 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6766 tpr->rx_jmb_prod_idx);
6769 } else if (work_mask) {
6770 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6771 * updated before the producer indices can be updated.
6775 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6776 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
6778 if (tnapi != &tp->napi[1]) {
6779 tp->rx_refill = true;
6780 napi_schedule(&tp->napi[1].napi);
6787 static void tg3_poll_link(struct tg3 *tp)
6789 /* handle link change and other phy events */
6790 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
6791 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
6793 if (sblk->status & SD_STATUS_LINK_CHG) {
6794 sblk->status = SD_STATUS_UPDATED |
6795 (sblk->status & ~SD_STATUS_LINK_CHG);
6796 spin_lock(&tp->lock);
6797 if (tg3_flag(tp, USE_PHYLIB)) {
6799 (MAC_STATUS_SYNC_CHANGED |
6800 MAC_STATUS_CFG_CHANGED |
6801 MAC_STATUS_MI_COMPLETION |
6802 MAC_STATUS_LNKSTATE_CHANGED));
6805 tg3_setup_phy(tp, 0);
6806 spin_unlock(&tp->lock);
6811 static int tg3_rx_prodring_xfer(struct tg3 *tp,
6812 struct tg3_rx_prodring_set *dpr,
6813 struct tg3_rx_prodring_set *spr)
6815 u32 si, di, cpycnt, src_prod_idx;
6819 src_prod_idx = spr->rx_std_prod_idx;
6821 /* Make sure updates to the rx_std_buffers[] entries and the
6822 * standard producer index are seen in the correct order.
6826 if (spr->rx_std_cons_idx == src_prod_idx)
6829 if (spr->rx_std_cons_idx < src_prod_idx)
6830 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
6832 cpycnt = tp->rx_std_ring_mask + 1 -
6833 spr->rx_std_cons_idx;
6835 cpycnt = min(cpycnt,
6836 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
6838 si = spr->rx_std_cons_idx;
6839 di = dpr->rx_std_prod_idx;
6841 for (i = di; i < di + cpycnt; i++) {
6842 if (dpr->rx_std_buffers[i].data) {
6852 /* Ensure that updates to the rx_std_buffers ring and the
6853 * shadowed hardware producer ring from tg3_recycle_skb() are
6854 * ordered correctly WRT the skb check above.
6858 memcpy(&dpr->rx_std_buffers[di],
6859 &spr->rx_std_buffers[si],
6860 cpycnt * sizeof(struct ring_info));
6862 for (i = 0; i < cpycnt; i++, di++, si++) {
6863 struct tg3_rx_buffer_desc *sbd, *dbd;
6864 sbd = &spr->rx_std[si];
6865 dbd = &dpr->rx_std[di];
6866 dbd->addr_hi = sbd->addr_hi;
6867 dbd->addr_lo = sbd->addr_lo;
6870 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
6871 tp->rx_std_ring_mask;
6872 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
6873 tp->rx_std_ring_mask;
6877 src_prod_idx = spr->rx_jmb_prod_idx;
6879 /* Make sure updates to the rx_jmb_buffers[] entries and
6880 * the jumbo producer index are seen in the correct order.
6884 if (spr->rx_jmb_cons_idx == src_prod_idx)
6887 if (spr->rx_jmb_cons_idx < src_prod_idx)
6888 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
6890 cpycnt = tp->rx_jmb_ring_mask + 1 -
6891 spr->rx_jmb_cons_idx;
6893 cpycnt = min(cpycnt,
6894 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
6896 si = spr->rx_jmb_cons_idx;
6897 di = dpr->rx_jmb_prod_idx;
6899 for (i = di; i < di + cpycnt; i++) {
6900 if (dpr->rx_jmb_buffers[i].data) {
6910 /* Ensure that updates to the rx_jmb_buffers ring and the
6911 * shadowed hardware producer ring from tg3_recycle_skb() are
6912 * ordered correctly WRT the skb check above.
6916 memcpy(&dpr->rx_jmb_buffers[di],
6917 &spr->rx_jmb_buffers[si],
6918 cpycnt * sizeof(struct ring_info));
6920 for (i = 0; i < cpycnt; i++, di++, si++) {
6921 struct tg3_rx_buffer_desc *sbd, *dbd;
6922 sbd = &spr->rx_jmb[si].std;
6923 dbd = &dpr->rx_jmb[di].std;
6924 dbd->addr_hi = sbd->addr_hi;
6925 dbd->addr_lo = sbd->addr_lo;
6928 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
6929 tp->rx_jmb_ring_mask;
6930 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
6931 tp->rx_jmb_ring_mask;
6937 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
6939 struct tg3 *tp = tnapi->tp;
6941 /* run TX completion thread */
6942 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
6944 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6948 if (!tnapi->rx_rcb_prod_idx)
6951 /* run RX thread, within the bounds set by NAPI.
6952 * All RX "locking" is done by ensuring outside
6953 * code synchronizes with tg3->napi.poll()
6955 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
6956 work_done += tg3_rx(tnapi, budget - work_done);
6958 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
6959 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
6961 u32 std_prod_idx = dpr->rx_std_prod_idx;
6962 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
6964 tp->rx_refill = false;
6965 for (i = 1; i <= tp->rxq_cnt; i++)
6966 err |= tg3_rx_prodring_xfer(tp, dpr,
6967 &tp->napi[i].prodring);
6971 if (std_prod_idx != dpr->rx_std_prod_idx)
6972 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6973 dpr->rx_std_prod_idx);
6975 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
6976 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6977 dpr->rx_jmb_prod_idx);
6982 tw32_f(HOSTCC_MODE, tp->coal_now);
6988 static inline void tg3_reset_task_schedule(struct tg3 *tp)
6990 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
6991 schedule_work(&tp->reset_task);
6994 static inline void tg3_reset_task_cancel(struct tg3 *tp)
6996 cancel_work_sync(&tp->reset_task);
6997 tg3_flag_clear(tp, RESET_TASK_PENDING);
6998 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7001 static int tg3_poll_msix(struct napi_struct *napi, int budget)
7003 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7004 struct tg3 *tp = tnapi->tp;
7006 struct tg3_hw_status *sblk = tnapi->hw_status;
7009 work_done = tg3_poll_work(tnapi, work_done, budget);
7011 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7014 if (unlikely(work_done >= budget))
7017 /* tp->last_tag is used in tg3_int_reenable() below
7018 * to tell the hw how much work has been processed,
7019 * so we must read it before checking for more work.
7021 tnapi->last_tag = sblk->status_tag;
7022 tnapi->last_irq_tag = tnapi->last_tag;
7025 /* check for RX/TX work to do */
7026 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7027 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7029 /* This test here is not race free, but will reduce
7030 * the number of interrupts by looping again.
7032 if (tnapi == &tp->napi[1] && tp->rx_refill)
7035 napi_complete(napi);
7036 /* Reenable interrupts. */
7037 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7039 /* This test here is synchronized by napi_schedule()
7040 * and napi_complete() to close the race condition.
7042 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7043 tw32(HOSTCC_MODE, tp->coalesce_mode |
7044 HOSTCC_MODE_ENABLE |
7055 /* work_done is guaranteed to be less than budget. */
7056 napi_complete(napi);
7057 tg3_reset_task_schedule(tp);
7061 static void tg3_process_error(struct tg3 *tp)
7064 bool real_error = false;
7066 if (tg3_flag(tp, ERROR_PROCESSED))
7069 /* Check Flow Attention register */
7070 val = tr32(HOSTCC_FLOW_ATTN);
7071 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7072 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7076 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7077 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7081 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7082 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7091 tg3_flag_set(tp, ERROR_PROCESSED);
7092 tg3_reset_task_schedule(tp);
7095 static int tg3_poll(struct napi_struct *napi, int budget)
7097 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7098 struct tg3 *tp = tnapi->tp;
7100 struct tg3_hw_status *sblk = tnapi->hw_status;
7103 if (sblk->status & SD_STATUS_ERROR)
7104 tg3_process_error(tp);
7108 work_done = tg3_poll_work(tnapi, work_done, budget);
7110 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7113 if (unlikely(work_done >= budget))
7116 if (tg3_flag(tp, TAGGED_STATUS)) {
7117 /* tp->last_tag is used in tg3_int_reenable() below
7118 * to tell the hw how much work has been processed,
7119 * so we must read it before checking for more work.
7121 tnapi->last_tag = sblk->status_tag;
7122 tnapi->last_irq_tag = tnapi->last_tag;
7125 sblk->status &= ~SD_STATUS_UPDATED;
7127 if (likely(!tg3_has_work(tnapi))) {
7128 napi_complete(napi);
7129 tg3_int_reenable(tnapi);
7137 /* work_done is guaranteed to be less than budget. */
7138 napi_complete(napi);
7139 tg3_reset_task_schedule(tp);
7143 static void tg3_napi_disable(struct tg3 *tp)
7147 for (i = tp->irq_cnt - 1; i >= 0; i--)
7148 napi_disable(&tp->napi[i].napi);
7151 static void tg3_napi_enable(struct tg3 *tp)
7155 for (i = 0; i < tp->irq_cnt; i++)
7156 napi_enable(&tp->napi[i].napi);
7159 static void tg3_napi_init(struct tg3 *tp)
7163 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7164 for (i = 1; i < tp->irq_cnt; i++)
7165 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7168 static void tg3_napi_fini(struct tg3 *tp)
7172 for (i = 0; i < tp->irq_cnt; i++)
7173 netif_napi_del(&tp->napi[i].napi);
7176 static inline void tg3_netif_stop(struct tg3 *tp)
7178 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7179 tg3_napi_disable(tp);
7180 netif_carrier_off(tp->dev);
7181 netif_tx_disable(tp->dev);
7184 /* tp->lock must be held */
7185 static inline void tg3_netif_start(struct tg3 *tp)
7189 /* NOTE: unconditional netif_tx_wake_all_queues is only
7190 * appropriate so long as all callers are assured to
7191 * have free tx slots (such as after tg3_init_hw)
7193 netif_tx_wake_all_queues(tp->dev);
7196 netif_carrier_on(tp->dev);
7198 tg3_napi_enable(tp);
7199 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7200 tg3_enable_ints(tp);
7203 static void tg3_irq_quiesce(struct tg3 *tp)
7207 BUG_ON(tp->irq_sync);
7212 for (i = 0; i < tp->irq_cnt; i++)
7213 synchronize_irq(tp->napi[i].irq_vec);
7216 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7217 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7218 * with as well. Most of the time, this is not necessary except when
7219 * shutting down the device.
7221 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7223 spin_lock_bh(&tp->lock);
7225 tg3_irq_quiesce(tp);
7228 static inline void tg3_full_unlock(struct tg3 *tp)
7230 spin_unlock_bh(&tp->lock);
7233 /* One-shot MSI handler - Chip automatically disables interrupt
7234 * after sending MSI so driver doesn't have to do it.
7236 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
7238 struct tg3_napi *tnapi = dev_id;
7239 struct tg3 *tp = tnapi->tp;
7241 prefetch(tnapi->hw_status);
7243 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7245 if (likely(!tg3_irq_sync(tp)))
7246 napi_schedule(&tnapi->napi);
7251 /* MSI ISR - No need to check for interrupt sharing and no need to
7252 * flush status block and interrupt mailbox. PCI ordering rules
7253 * guarantee that MSI will arrive after the status block.
7255 static irqreturn_t tg3_msi(int irq, void *dev_id)
7257 struct tg3_napi *tnapi = dev_id;
7258 struct tg3 *tp = tnapi->tp;
7260 prefetch(tnapi->hw_status);
7262 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7264 * Writing any value to intr-mbox-0 clears PCI INTA# and
7265 * chip-internal interrupt pending events.
7266 * Writing non-zero to intr-mbox-0 additional tells the
7267 * NIC to stop sending us irqs, engaging "in-intr-handler"
7270 tw32_mailbox(tnapi->int_mbox, 0x00000001);
7271 if (likely(!tg3_irq_sync(tp)))
7272 napi_schedule(&tnapi->napi);
7274 return IRQ_RETVAL(1);
7277 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
7279 struct tg3_napi *tnapi = dev_id;
7280 struct tg3 *tp = tnapi->tp;
7281 struct tg3_hw_status *sblk = tnapi->hw_status;
7282 unsigned int handled = 1;
7284 /* In INTx mode, it is possible for the interrupt to arrive at
7285 * the CPU before the status block posted prior to the interrupt.
7286 * Reading the PCI State register will confirm whether the
7287 * interrupt is ours and will flush the status block.
7289 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
7290 if (tg3_flag(tp, CHIP_RESETTING) ||
7291 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7298 * Writing any value to intr-mbox-0 clears PCI INTA# and
7299 * chip-internal interrupt pending events.
7300 * Writing non-zero to intr-mbox-0 additional tells the
7301 * NIC to stop sending us irqs, engaging "in-intr-handler"
7304 * Flush the mailbox to de-assert the IRQ immediately to prevent
7305 * spurious interrupts. The flush impacts performance but
7306 * excessive spurious interrupts can be worse in some cases.
7308 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7309 if (tg3_irq_sync(tp))
7311 sblk->status &= ~SD_STATUS_UPDATED;
7312 if (likely(tg3_has_work(tnapi))) {
7313 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7314 napi_schedule(&tnapi->napi);
7316 /* No work, shared interrupt perhaps? re-enable
7317 * interrupts, and flush that PCI write
7319 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7323 return IRQ_RETVAL(handled);
7326 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
7328 struct tg3_napi *tnapi = dev_id;
7329 struct tg3 *tp = tnapi->tp;
7330 struct tg3_hw_status *sblk = tnapi->hw_status;
7331 unsigned int handled = 1;
7333 /* In INTx mode, it is possible for the interrupt to arrive at
7334 * the CPU before the status block posted prior to the interrupt.
7335 * Reading the PCI State register will confirm whether the
7336 * interrupt is ours and will flush the status block.
7338 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
7339 if (tg3_flag(tp, CHIP_RESETTING) ||
7340 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7347 * writing any value to intr-mbox-0 clears PCI INTA# and
7348 * chip-internal interrupt pending events.
7349 * writing non-zero to intr-mbox-0 additional tells the
7350 * NIC to stop sending us irqs, engaging "in-intr-handler"
7353 * Flush the mailbox to de-assert the IRQ immediately to prevent
7354 * spurious interrupts. The flush impacts performance but
7355 * excessive spurious interrupts can be worse in some cases.
7357 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7360 * In a shared interrupt configuration, sometimes other devices'
7361 * interrupts will scream. We record the current status tag here
7362 * so that the above check can report that the screaming interrupts
7363 * are unhandled. Eventually they will be silenced.
7365 tnapi->last_irq_tag = sblk->status_tag;
7367 if (tg3_irq_sync(tp))
7370 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7372 napi_schedule(&tnapi->napi);
7375 return IRQ_RETVAL(handled);
7378 /* ISR for interrupt test */
7379 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7381 struct tg3_napi *tnapi = dev_id;
7382 struct tg3 *tp = tnapi->tp;
7383 struct tg3_hw_status *sblk = tnapi->hw_status;
7385 if ((sblk->status & SD_STATUS_UPDATED) ||
7386 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7387 tg3_disable_ints(tp);
7388 return IRQ_RETVAL(1);
7390 return IRQ_RETVAL(0);
7393 #ifdef CONFIG_NET_POLL_CONTROLLER
7394 static void tg3_poll_controller(struct net_device *dev)
7397 struct tg3 *tp = netdev_priv(dev);
7399 if (tg3_irq_sync(tp))
7402 for (i = 0; i < tp->irq_cnt; i++)
7403 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7407 static void tg3_tx_timeout(struct net_device *dev)
7409 struct tg3 *tp = netdev_priv(dev);
7411 if (netif_msg_tx_err(tp)) {
7412 netdev_err(dev, "transmit timed out, resetting\n");
7416 tg3_reset_task_schedule(tp);
7419 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7420 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7422 u32 base = (u32) mapping & 0xffffffff;
7424 return (base > 0xffffdcc0) && (base + len + 8 < base);
7427 /* Test for DMA addresses > 40-bit */
7428 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7431 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7432 if (tg3_flag(tp, 40BIT_DMA_BUG))
7433 return ((u64) mapping + len) > DMA_BIT_MASK(40);
7440 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
7441 dma_addr_t mapping, u32 len, u32 flags,
7444 txbd->addr_hi = ((u64) mapping >> 32);
7445 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7446 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7447 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
7450 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
7451 dma_addr_t map, u32 len, u32 flags,
7454 struct tg3 *tp = tnapi->tp;
7457 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7460 if (tg3_4g_overflow_test(map, len))
7463 if (tg3_40bit_overflow_test(tp, map, len))
7466 if (tp->dma_limit) {
7467 u32 prvidx = *entry;
7468 u32 tmp_flag = flags & ~TXD_FLAG_END;
7469 while (len > tp->dma_limit && *budget) {
7470 u32 frag_len = tp->dma_limit;
7471 len -= tp->dma_limit;
7473 /* Avoid the 8byte DMA problem */
7475 len += tp->dma_limit / 2;
7476 frag_len = tp->dma_limit / 2;
7479 tnapi->tx_buffers[*entry].fragmented = true;
7481 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7482 frag_len, tmp_flag, mss, vlan);
7485 *entry = NEXT_TX(*entry);
7492 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7493 len, flags, mss, vlan);
7495 *entry = NEXT_TX(*entry);
7498 tnapi->tx_buffers[prvidx].fragmented = false;
7502 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7503 len, flags, mss, vlan);
7504 *entry = NEXT_TX(*entry);
7510 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
7513 struct sk_buff *skb;
7514 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
7519 pci_unmap_single(tnapi->tp->pdev,
7520 dma_unmap_addr(txb, mapping),
7524 while (txb->fragmented) {
7525 txb->fragmented = false;
7526 entry = NEXT_TX(entry);
7527 txb = &tnapi->tx_buffers[entry];
7530 for (i = 0; i <= last; i++) {
7531 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7533 entry = NEXT_TX(entry);
7534 txb = &tnapi->tx_buffers[entry];
7536 pci_unmap_page(tnapi->tp->pdev,
7537 dma_unmap_addr(txb, mapping),
7538 skb_frag_size(frag), PCI_DMA_TODEVICE);
7540 while (txb->fragmented) {
7541 txb->fragmented = false;
7542 entry = NEXT_TX(entry);
7543 txb = &tnapi->tx_buffers[entry];
7548 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7549 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
7550 struct sk_buff **pskb,
7551 u32 *entry, u32 *budget,
7552 u32 base_flags, u32 mss, u32 vlan)
7554 struct tg3 *tp = tnapi->tp;
7555 struct sk_buff *new_skb, *skb = *pskb;
7556 dma_addr_t new_addr = 0;
7559 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7560 new_skb = skb_copy(skb, GFP_ATOMIC);
7562 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7564 new_skb = skb_copy_expand(skb,
7565 skb_headroom(skb) + more_headroom,
7566 skb_tailroom(skb), GFP_ATOMIC);
7572 /* New SKB is guaranteed to be linear. */
7573 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7575 /* Make sure the mapping succeeded */
7576 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
7577 dev_kfree_skb(new_skb);
7580 u32 save_entry = *entry;
7582 base_flags |= TXD_FLAG_END;
7584 tnapi->tx_buffers[*entry].skb = new_skb;
7585 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
7588 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
7589 new_skb->len, base_flags,
7591 tg3_tx_skb_unmap(tnapi, save_entry, -1);
7592 dev_kfree_skb(new_skb);
7603 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
7605 /* Use GSO to workaround a rare TSO bug that may be triggered when the
7606 * TSO header is greater than 80 bytes.
7608 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
7610 struct sk_buff *segs, *nskb;
7611 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
7613 /* Estimate the number of fragments in the worst case */
7614 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
7615 netif_stop_queue(tp->dev);
7617 /* netif_tx_stop_queue() must be done before checking
7618 * checking tx index in tg3_tx_avail() below, because in
7619 * tg3_tx(), we update tx index before checking for
7620 * netif_tx_queue_stopped().
7623 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7624 return NETDEV_TX_BUSY;
7626 netif_wake_queue(tp->dev);
7629 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
7631 goto tg3_tso_bug_end;
7637 tg3_start_xmit(nskb, tp->dev);
7643 return NETDEV_TX_OK;
7646 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
7647 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
7649 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
7651 struct tg3 *tp = netdev_priv(dev);
7652 u32 len, entry, base_flags, mss, vlan = 0;
7654 int i = -1, would_hit_hwbug;
7656 struct tg3_napi *tnapi;
7657 struct netdev_queue *txq;
7660 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7661 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7662 if (tg3_flag(tp, ENABLE_TSS))
7665 budget = tg3_tx_avail(tnapi);
7667 /* We are running in BH disabled context with netif_tx_lock
7668 * and TX reclaim runs via tp->napi.poll inside of a software
7669 * interrupt. Furthermore, IRQ processing runs lockless so we have
7670 * no IRQ context deadlocks to worry about either. Rejoice!
7672 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
7673 if (!netif_tx_queue_stopped(txq)) {
7674 netif_tx_stop_queue(txq);
7676 /* This is a hard error, log it. */
7678 "BUG! Tx Ring full when queue awake!\n");
7680 return NETDEV_TX_BUSY;
7683 entry = tnapi->tx_prod;
7685 if (skb->ip_summed == CHECKSUM_PARTIAL)
7686 base_flags |= TXD_FLAG_TCPUDP_CSUM;
7688 mss = skb_shinfo(skb)->gso_size;
7691 u32 tcp_opt_len, hdr_len;
7693 if (skb_header_cloned(skb) &&
7694 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7698 tcp_opt_len = tcp_optlen(skb);
7700 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
7702 if (!skb_is_gso_v6(skb)) {
7704 iph->tot_len = htons(mss + hdr_len);
7707 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7708 tg3_flag(tp, TSO_BUG))
7709 return tg3_tso_bug(tp, skb);
7711 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7712 TXD_FLAG_CPU_POST_DMA);
7714 if (tg3_flag(tp, HW_TSO_1) ||
7715 tg3_flag(tp, HW_TSO_2) ||
7716 tg3_flag(tp, HW_TSO_3)) {
7717 tcp_hdr(skb)->check = 0;
7718 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7720 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7725 if (tg3_flag(tp, HW_TSO_3)) {
7726 mss |= (hdr_len & 0xc) << 12;
7728 base_flags |= 0x00000010;
7729 base_flags |= (hdr_len & 0x3e0) << 5;
7730 } else if (tg3_flag(tp, HW_TSO_2))
7731 mss |= hdr_len << 9;
7732 else if (tg3_flag(tp, HW_TSO_1) ||
7733 tg3_asic_rev(tp) == ASIC_REV_5705) {
7734 if (tcp_opt_len || iph->ihl > 5) {
7737 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7738 mss |= (tsflags << 11);
7741 if (tcp_opt_len || iph->ihl > 5) {
7744 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7745 base_flags |= tsflags << 12;
7750 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7751 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7752 base_flags |= TXD_FLAG_JMB_PKT;
7754 if (vlan_tx_tag_present(skb)) {
7755 base_flags |= TXD_FLAG_VLAN;
7756 vlan = vlan_tx_tag_get(skb);
7759 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7760 tg3_flag(tp, TX_TSTAMP_EN)) {
7761 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7762 base_flags |= TXD_FLAG_HWTSTAMP;
7765 len = skb_headlen(skb);
7767 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
7768 if (pci_dma_mapping_error(tp->pdev, mapping))
7772 tnapi->tx_buffers[entry].skb = skb;
7773 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
7775 would_hit_hwbug = 0;
7777 if (tg3_flag(tp, 5701_DMA_BUG))
7778 would_hit_hwbug = 1;
7780 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
7781 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
7783 would_hit_hwbug = 1;
7784 } else if (skb_shinfo(skb)->nr_frags > 0) {
7787 if (!tg3_flag(tp, HW_TSO_1) &&
7788 !tg3_flag(tp, HW_TSO_2) &&
7789 !tg3_flag(tp, HW_TSO_3))
7792 /* Now loop through additional data
7793 * fragments, and queue them.
7795 last = skb_shinfo(skb)->nr_frags - 1;
7796 for (i = 0; i <= last; i++) {
7797 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7799 len = skb_frag_size(frag);
7800 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
7801 len, DMA_TO_DEVICE);
7803 tnapi->tx_buffers[entry].skb = NULL;
7804 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
7806 if (dma_mapping_error(&tp->pdev->dev, mapping))
7810 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
7812 ((i == last) ? TXD_FLAG_END : 0),
7814 would_hit_hwbug = 1;
7820 if (would_hit_hwbug) {
7821 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
7823 /* If the workaround fails due to memory/mapping
7824 * failure, silently drop this packet.
7826 entry = tnapi->tx_prod;
7827 budget = tg3_tx_avail(tnapi);
7828 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
7829 base_flags, mss, vlan))
7833 skb_tx_timestamp(skb);
7834 netdev_tx_sent_queue(txq, skb->len);
7836 /* Sync BD data before updating mailbox */
7839 /* Packets are ready, update Tx producer idx local and on card. */
7840 tw32_tx_mbox(tnapi->prodmbox, entry);
7842 tnapi->tx_prod = entry;
7843 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
7844 netif_tx_stop_queue(txq);
7846 /* netif_tx_stop_queue() must be done before checking
7847 * checking tx index in tg3_tx_avail() below, because in
7848 * tg3_tx(), we update tx index before checking for
7849 * netif_tx_queue_stopped().
7852 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
7853 netif_tx_wake_queue(txq);
7857 return NETDEV_TX_OK;
7860 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
7861 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
7866 return NETDEV_TX_OK;
7869 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
7872 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
7873 MAC_MODE_PORT_MODE_MASK);
7875 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
7877 if (!tg3_flag(tp, 5705_PLUS))
7878 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7880 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
7881 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
7883 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7885 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
7887 if (tg3_flag(tp, 5705_PLUS) ||
7888 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
7889 tg3_asic_rev(tp) == ASIC_REV_5700)
7890 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
7893 tw32(MAC_MODE, tp->mac_mode);
7897 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
7899 u32 val, bmcr, mac_mode, ptest = 0;
7901 tg3_phy_toggle_apd(tp, false);
7902 tg3_phy_toggle_automdix(tp, 0);
7904 if (extlpbk && tg3_phy_set_extloopbk(tp))
7907 bmcr = BMCR_FULLDPLX;
7912 bmcr |= BMCR_SPEED100;
7916 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7918 bmcr |= BMCR_SPEED100;
7921 bmcr |= BMCR_SPEED1000;
7926 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
7927 tg3_readphy(tp, MII_CTRL1000, &val);
7928 val |= CTL1000_AS_MASTER |
7929 CTL1000_ENABLE_MASTER;
7930 tg3_writephy(tp, MII_CTRL1000, val);
7932 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
7933 MII_TG3_FET_PTEST_TRIM_2;
7934 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
7937 bmcr |= BMCR_LOOPBACK;
7939 tg3_writephy(tp, MII_BMCR, bmcr);
7941 /* The write needs to be flushed for the FETs */
7942 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7943 tg3_readphy(tp, MII_BMCR, &bmcr);
7947 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
7948 tg3_asic_rev(tp) == ASIC_REV_5785) {
7949 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
7950 MII_TG3_FET_PTEST_FRC_TX_LINK |
7951 MII_TG3_FET_PTEST_FRC_TX_LOCK);
7953 /* The write needs to be flushed for the AC131 */
7954 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
7957 /* Reset to prevent losing 1st rx packet intermittently */
7958 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
7959 tg3_flag(tp, 5780_CLASS)) {
7960 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7962 tw32_f(MAC_RX_MODE, tp->rx_mode);
7965 mac_mode = tp->mac_mode &
7966 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
7967 if (speed == SPEED_1000)
7968 mac_mode |= MAC_MODE_PORT_MODE_GMII;
7970 mac_mode |= MAC_MODE_PORT_MODE_MII;
7972 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
7973 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
7975 if (masked_phy_id == TG3_PHY_ID_BCM5401)
7976 mac_mode &= ~MAC_MODE_LINK_POLARITY;
7977 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
7978 mac_mode |= MAC_MODE_LINK_POLARITY;
7980 tg3_writephy(tp, MII_TG3_EXT_CTRL,
7981 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
7984 tw32(MAC_MODE, mac_mode);
7990 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
7992 struct tg3 *tp = netdev_priv(dev);
7994 if (features & NETIF_F_LOOPBACK) {
7995 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
7998 spin_lock_bh(&tp->lock);
7999 tg3_mac_loopback(tp, true);
8000 netif_carrier_on(tp->dev);
8001 spin_unlock_bh(&tp->lock);
8002 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8004 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8007 spin_lock_bh(&tp->lock);
8008 tg3_mac_loopback(tp, false);
8009 /* Force link status check */
8010 tg3_setup_phy(tp, 1);
8011 spin_unlock_bh(&tp->lock);
8012 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8016 static netdev_features_t tg3_fix_features(struct net_device *dev,
8017 netdev_features_t features)
8019 struct tg3 *tp = netdev_priv(dev);
8021 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8022 features &= ~NETIF_F_ALL_TSO;
8027 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
8029 netdev_features_t changed = dev->features ^ features;
8031 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8032 tg3_set_loopback(dev, features);
8037 static void tg3_rx_prodring_free(struct tg3 *tp,
8038 struct tg3_rx_prodring_set *tpr)
8042 if (tpr != &tp->napi[0].prodring) {
8043 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
8044 i = (i + 1) & tp->rx_std_ring_mask)
8045 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8048 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8049 for (i = tpr->rx_jmb_cons_idx;
8050 i != tpr->rx_jmb_prod_idx;
8051 i = (i + 1) & tp->rx_jmb_ring_mask) {
8052 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8060 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8061 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8064 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8065 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8066 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8071 /* Initialize rx rings for packet processing.
8073 * The chip has been shut down and the driver detached from
8074 * the networking, so no interrupts or new tx packets will
8075 * end up in the driver. tp->{tx,}lock are held and thus
8078 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8079 struct tg3_rx_prodring_set *tpr)
8081 u32 i, rx_pkt_dma_sz;
8083 tpr->rx_std_cons_idx = 0;
8084 tpr->rx_std_prod_idx = 0;
8085 tpr->rx_jmb_cons_idx = 0;
8086 tpr->rx_jmb_prod_idx = 0;
8088 if (tpr != &tp->napi[0].prodring) {
8089 memset(&tpr->rx_std_buffers[0], 0,
8090 TG3_RX_STD_BUFF_RING_SIZE(tp));
8091 if (tpr->rx_jmb_buffers)
8092 memset(&tpr->rx_jmb_buffers[0], 0,
8093 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8097 /* Zero out all descriptors. */
8098 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8100 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
8101 if (tg3_flag(tp, 5780_CLASS) &&
8102 tp->dev->mtu > ETH_DATA_LEN)
8103 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8104 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8106 /* Initialize invariants of the rings, we only set this
8107 * stuff once. This works because the card does not
8108 * write into the rx buffer posting rings.
8110 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8111 struct tg3_rx_buffer_desc *rxd;
8113 rxd = &tpr->rx_std[i];
8114 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
8115 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8116 rxd->opaque = (RXD_OPAQUE_RING_STD |
8117 (i << RXD_OPAQUE_INDEX_SHIFT));
8120 /* Now allocate fresh SKBs for each rx ring. */
8121 for (i = 0; i < tp->rx_pending; i++) {
8122 unsigned int frag_size;
8124 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8126 netdev_warn(tp->dev,
8127 "Using a smaller RX standard ring. Only "
8128 "%d out of %d buffers were allocated "
8129 "successfully\n", i, tp->rx_pending);
8137 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8140 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8142 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8145 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8146 struct tg3_rx_buffer_desc *rxd;
8148 rxd = &tpr->rx_jmb[i].std;
8149 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8150 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8152 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8153 (i << RXD_OPAQUE_INDEX_SHIFT));
8156 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8157 unsigned int frag_size;
8159 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8161 netdev_warn(tp->dev,
8162 "Using a smaller RX jumbo ring. Only %d "
8163 "out of %d buffers were allocated "
8164 "successfully\n", i, tp->rx_jumbo_pending);
8167 tp->rx_jumbo_pending = i;
8176 tg3_rx_prodring_free(tp, tpr);
8180 static void tg3_rx_prodring_fini(struct tg3 *tp,
8181 struct tg3_rx_prodring_set *tpr)
8183 kfree(tpr->rx_std_buffers);
8184 tpr->rx_std_buffers = NULL;
8185 kfree(tpr->rx_jmb_buffers);
8186 tpr->rx_jmb_buffers = NULL;
8188 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8189 tpr->rx_std, tpr->rx_std_mapping);
8193 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8194 tpr->rx_jmb, tpr->rx_jmb_mapping);
8199 static int tg3_rx_prodring_init(struct tg3 *tp,
8200 struct tg3_rx_prodring_set *tpr)
8202 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8204 if (!tpr->rx_std_buffers)
8207 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8208 TG3_RX_STD_RING_BYTES(tp),
8209 &tpr->rx_std_mapping,
8214 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8215 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8217 if (!tpr->rx_jmb_buffers)
8220 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8221 TG3_RX_JMB_RING_BYTES(tp),
8222 &tpr->rx_jmb_mapping,
8231 tg3_rx_prodring_fini(tp, tpr);
8235 /* Free up pending packets in all rx/tx rings.
8237 * The chip has been shut down and the driver detached from
8238 * the networking, so no interrupts or new tx packets will
8239 * end up in the driver. tp->{tx,}lock is not held and we are not
8240 * in an interrupt context and thus may sleep.
8242 static void tg3_free_rings(struct tg3 *tp)
8246 for (j = 0; j < tp->irq_cnt; j++) {
8247 struct tg3_napi *tnapi = &tp->napi[j];
8249 tg3_rx_prodring_free(tp, &tnapi->prodring);
8251 if (!tnapi->tx_buffers)
8254 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8255 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
8260 tg3_tx_skb_unmap(tnapi, i,
8261 skb_shinfo(skb)->nr_frags - 1);
8263 dev_kfree_skb_any(skb);
8265 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8269 /* Initialize tx/rx rings for packet processing.
8271 * The chip has been shut down and the driver detached from
8272 * the networking, so no interrupts or new tx packets will
8273 * end up in the driver. tp->{tx,}lock are held and thus
8276 static int tg3_init_rings(struct tg3 *tp)
8280 /* Free up all the SKBs. */
8283 for (i = 0; i < tp->irq_cnt; i++) {
8284 struct tg3_napi *tnapi = &tp->napi[i];
8286 tnapi->last_tag = 0;
8287 tnapi->last_irq_tag = 0;
8288 tnapi->hw_status->status = 0;
8289 tnapi->hw_status->status_tag = 0;
8290 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8295 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
8297 tnapi->rx_rcb_ptr = 0;
8299 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8301 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8310 static void tg3_mem_tx_release(struct tg3 *tp)
8314 for (i = 0; i < tp->irq_max; i++) {
8315 struct tg3_napi *tnapi = &tp->napi[i];
8317 if (tnapi->tx_ring) {
8318 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8319 tnapi->tx_ring, tnapi->tx_desc_mapping);
8320 tnapi->tx_ring = NULL;
8323 kfree(tnapi->tx_buffers);
8324 tnapi->tx_buffers = NULL;
8328 static int tg3_mem_tx_acquire(struct tg3 *tp)
8331 struct tg3_napi *tnapi = &tp->napi[0];
8333 /* If multivector TSS is enabled, vector 0 does not handle
8334 * tx interrupts. Don't allocate any resources for it.
8336 if (tg3_flag(tp, ENABLE_TSS))
8339 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8340 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8341 TG3_TX_RING_SIZE, GFP_KERNEL);
8342 if (!tnapi->tx_buffers)
8345 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8347 &tnapi->tx_desc_mapping,
8349 if (!tnapi->tx_ring)
8356 tg3_mem_tx_release(tp);
8360 static void tg3_mem_rx_release(struct tg3 *tp)
8364 for (i = 0; i < tp->irq_max; i++) {
8365 struct tg3_napi *tnapi = &tp->napi[i];
8367 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8372 dma_free_coherent(&tp->pdev->dev,
8373 TG3_RX_RCB_RING_BYTES(tp),
8375 tnapi->rx_rcb_mapping);
8376 tnapi->rx_rcb = NULL;
8380 static int tg3_mem_rx_acquire(struct tg3 *tp)
8382 unsigned int i, limit;
8384 limit = tp->rxq_cnt;
8386 /* If RSS is enabled, we need a (dummy) producer ring
8387 * set on vector zero. This is the true hw prodring.
8389 if (tg3_flag(tp, ENABLE_RSS))
8392 for (i = 0; i < limit; i++) {
8393 struct tg3_napi *tnapi = &tp->napi[i];
8395 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8398 /* If multivector RSS is enabled, vector 0
8399 * does not handle rx or tx interrupts.
8400 * Don't allocate any resources for it.
8402 if (!i && tg3_flag(tp, ENABLE_RSS))
8405 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
8406 TG3_RX_RCB_RING_BYTES(tp),
8407 &tnapi->rx_rcb_mapping,
8408 GFP_KERNEL | __GFP_ZERO);
8416 tg3_mem_rx_release(tp);
8421 * Must not be invoked with interrupt sources disabled and
8422 * the hardware shutdown down.
8424 static void tg3_free_consistent(struct tg3 *tp)
8428 for (i = 0; i < tp->irq_cnt; i++) {
8429 struct tg3_napi *tnapi = &tp->napi[i];
8431 if (tnapi->hw_status) {
8432 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8434 tnapi->status_mapping);
8435 tnapi->hw_status = NULL;
8439 tg3_mem_rx_release(tp);
8440 tg3_mem_tx_release(tp);
8443 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8444 tp->hw_stats, tp->stats_mapping);
8445 tp->hw_stats = NULL;
8450 * Must not be invoked with interrupt sources disabled and
8451 * the hardware shutdown down. Can sleep.
8453 static int tg3_alloc_consistent(struct tg3 *tp)
8457 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
8458 sizeof(struct tg3_hw_stats),
8460 GFP_KERNEL | __GFP_ZERO);
8464 for (i = 0; i < tp->irq_cnt; i++) {
8465 struct tg3_napi *tnapi = &tp->napi[i];
8466 struct tg3_hw_status *sblk;
8468 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
8470 &tnapi->status_mapping,
8471 GFP_KERNEL | __GFP_ZERO);
8472 if (!tnapi->hw_status)
8475 sblk = tnapi->hw_status;
8477 if (tg3_flag(tp, ENABLE_RSS)) {
8478 u16 *prodptr = NULL;
8481 * When RSS is enabled, the status block format changes
8482 * slightly. The "rx_jumbo_consumer", "reserved",
8483 * and "rx_mini_consumer" members get mapped to the
8484 * other three rx return ring producer indexes.
8488 prodptr = &sblk->idx[0].rx_producer;
8491 prodptr = &sblk->rx_jumbo_consumer;
8494 prodptr = &sblk->reserved;
8497 prodptr = &sblk->rx_mini_consumer;
8500 tnapi->rx_rcb_prod_idx = prodptr;
8502 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8506 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8512 tg3_free_consistent(tp);
8516 #define MAX_WAIT_CNT 1000
8518 /* To stop a block, clear the enable bit and poll till it
8519 * clears. tp->lock is held.
8521 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
8526 if (tg3_flag(tp, 5705_PLUS)) {
8533 /* We can't enable/disable these bits of the
8534 * 5705/5750, just say success.
8547 for (i = 0; i < MAX_WAIT_CNT; i++) {
8550 if ((val & enable_bit) == 0)
8554 if (i == MAX_WAIT_CNT && !silent) {
8555 dev_err(&tp->pdev->dev,
8556 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8564 /* tp->lock is held. */
8565 static int tg3_abort_hw(struct tg3 *tp, int silent)
8569 tg3_disable_ints(tp);
8571 tp->rx_mode &= ~RX_MODE_ENABLE;
8572 tw32_f(MAC_RX_MODE, tp->rx_mode);
8575 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8576 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8577 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8578 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8579 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8580 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8582 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8583 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8584 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8585 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8586 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8587 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8588 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8590 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8591 tw32_f(MAC_MODE, tp->mac_mode);
8594 tp->tx_mode &= ~TX_MODE_ENABLE;
8595 tw32_f(MAC_TX_MODE, tp->tx_mode);
8597 for (i = 0; i < MAX_WAIT_CNT; i++) {
8599 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8602 if (i >= MAX_WAIT_CNT) {
8603 dev_err(&tp->pdev->dev,
8604 "%s timed out, TX_MODE_ENABLE will not clear "
8605 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
8609 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8610 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8611 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8613 tw32(FTQ_RESET, 0xffffffff);
8614 tw32(FTQ_RESET, 0x00000000);
8616 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8617 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8619 for (i = 0; i < tp->irq_cnt; i++) {
8620 struct tg3_napi *tnapi = &tp->napi[i];
8621 if (tnapi->hw_status)
8622 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8628 /* Save PCI command register before chip reset */
8629 static void tg3_save_pci_state(struct tg3 *tp)
8631 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8634 /* Restore PCI state after chip reset */
8635 static void tg3_restore_pci_state(struct tg3 *tp)
8639 /* Re-enable indirect register accesses. */
8640 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8641 tp->misc_host_ctrl);
8643 /* Set MAX PCI retry to zero. */
8644 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8645 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8646 tg3_flag(tp, PCIX_MODE))
8647 val |= PCISTATE_RETRY_SAME_DMA;
8648 /* Allow reads and writes to the APE register and memory space. */
8649 if (tg3_flag(tp, ENABLE_APE))
8650 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8651 PCISTATE_ALLOW_APE_SHMEM_WR |
8652 PCISTATE_ALLOW_APE_PSPACE_WR;
8653 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8655 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8657 if (!tg3_flag(tp, PCI_EXPRESS)) {
8658 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8659 tp->pci_cacheline_sz);
8660 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8664 /* Make sure PCI-X relaxed ordering bit is clear. */
8665 if (tg3_flag(tp, PCIX_MODE)) {
8668 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8670 pcix_cmd &= ~PCI_X_CMD_ERO;
8671 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8675 if (tg3_flag(tp, 5780_CLASS)) {
8677 /* Chip reset on 5780 will reset MSI enable bit,
8678 * so need to restore it.
8680 if (tg3_flag(tp, USING_MSI)) {
8683 pci_read_config_word(tp->pdev,
8684 tp->msi_cap + PCI_MSI_FLAGS,
8686 pci_write_config_word(tp->pdev,
8687 tp->msi_cap + PCI_MSI_FLAGS,
8688 ctrl | PCI_MSI_FLAGS_ENABLE);
8689 val = tr32(MSGINT_MODE);
8690 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8695 /* tp->lock is held. */
8696 static int tg3_chip_reset(struct tg3 *tp)
8699 void (*write_op)(struct tg3 *, u32, u32);
8704 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
8706 /* No matching tg3_nvram_unlock() after this because
8707 * chip reset below will undo the nvram lock.
8709 tp->nvram_lock_cnt = 0;
8711 /* GRC_MISC_CFG core clock reset will clear the memory
8712 * enable bit in PCI register 4 and the MSI enable bit
8713 * on some chips, so we save relevant registers here.
8715 tg3_save_pci_state(tp);
8717 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
8718 tg3_flag(tp, 5755_PLUS))
8719 tw32(GRC_FASTBOOT_PC, 0);
8722 * We must avoid the readl() that normally takes place.
8723 * It locks machines, causes machine checks, and other
8724 * fun things. So, temporarily disable the 5701
8725 * hardware workaround, while we do the reset.
8727 write_op = tp->write32;
8728 if (write_op == tg3_write_flush_reg32)
8729 tp->write32 = tg3_write32;
8731 /* Prevent the irq handler from reading or writing PCI registers
8732 * during chip reset when the memory enable bit in the PCI command
8733 * register may be cleared. The chip does not generate interrupt
8734 * at this time, but the irq handler may still be called due to irq
8735 * sharing or irqpoll.
8737 tg3_flag_set(tp, CHIP_RESETTING);
8738 for (i = 0; i < tp->irq_cnt; i++) {
8739 struct tg3_napi *tnapi = &tp->napi[i];
8740 if (tnapi->hw_status) {
8741 tnapi->hw_status->status = 0;
8742 tnapi->hw_status->status_tag = 0;
8744 tnapi->last_tag = 0;
8745 tnapi->last_irq_tag = 0;
8749 for (i = 0; i < tp->irq_cnt; i++)
8750 synchronize_irq(tp->napi[i].irq_vec);
8752 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
8753 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8754 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8758 val = GRC_MISC_CFG_CORECLK_RESET;
8760 if (tg3_flag(tp, PCI_EXPRESS)) {
8761 /* Force PCIe 1.0a mode */
8762 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
8763 !tg3_flag(tp, 57765_PLUS) &&
8764 tr32(TG3_PCIE_PHY_TSTCTL) ==
8765 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
8766 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
8768 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
8769 tw32(GRC_MISC_CFG, (1 << 29));
8774 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
8775 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
8776 tw32(GRC_VCPU_EXT_CTRL,
8777 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
8780 /* Manage gphy power for all CPMU absent PCIe devices. */
8781 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
8782 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
8784 tw32(GRC_MISC_CFG, val);
8786 /* restore 5701 hardware bug workaround write method */
8787 tp->write32 = write_op;
8789 /* Unfortunately, we have to delay before the PCI read back.
8790 * Some 575X chips even will not respond to a PCI cfg access
8791 * when the reset command is given to the chip.
8793 * How do these hardware designers expect things to work
8794 * properly if the PCI write is posted for a long period
8795 * of time? It is always necessary to have some method by
8796 * which a register read back can occur to push the write
8797 * out which does the reset.
8799 * For most tg3 variants the trick below was working.
8804 /* Flush PCI posted writes. The normal MMIO registers
8805 * are inaccessible at this time so this is the only
8806 * way to make this reliably (actually, this is no longer
8807 * the case, see above). I tried to use indirect
8808 * register read/write but this upset some 5701 variants.
8810 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
8814 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
8817 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
8821 /* Wait for link training to complete. */
8822 for (j = 0; j < 5000; j++)
8825 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
8826 pci_write_config_dword(tp->pdev, 0xc4,
8827 cfg_val | (1 << 15));
8830 /* Clear the "no snoop" and "relaxed ordering" bits. */
8831 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
8833 * Older PCIe devices only support the 128 byte
8834 * MPS setting. Enforce the restriction.
8836 if (!tg3_flag(tp, CPMU_PRESENT))
8837 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
8838 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
8840 /* Clear error status */
8841 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
8842 PCI_EXP_DEVSTA_CED |
8843 PCI_EXP_DEVSTA_NFED |
8844 PCI_EXP_DEVSTA_FED |
8845 PCI_EXP_DEVSTA_URD);
8848 tg3_restore_pci_state(tp);
8850 tg3_flag_clear(tp, CHIP_RESETTING);
8851 tg3_flag_clear(tp, ERROR_PROCESSED);
8854 if (tg3_flag(tp, 5780_CLASS))
8855 val = tr32(MEMARB_MODE);
8856 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
8858 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
8860 tw32(0x5000, 0x400);
8863 if (tg3_flag(tp, IS_SSB_CORE)) {
8865 * BCM4785: In order to avoid repercussions from using
8866 * potentially defective internal ROM, stop the Rx RISC CPU,
8867 * which is not required.
8870 tg3_halt_cpu(tp, RX_CPU_BASE);
8873 tw32(GRC_MODE, tp->grc_mode);
8875 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
8878 tw32(0xc4, val | (1 << 15));
8881 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
8882 tg3_asic_rev(tp) == ASIC_REV_5705) {
8883 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
8884 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
8885 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
8886 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8889 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8890 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
8892 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8893 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
8898 tw32_f(MAC_MODE, val);
8901 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
8903 err = tg3_poll_fw(tp);
8909 if (tg3_flag(tp, PCI_EXPRESS) &&
8910 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
8911 tg3_asic_rev(tp) != ASIC_REV_5785 &&
8912 !tg3_flag(tp, 57765_PLUS)) {
8915 tw32(0x7c00, val | (1 << 25));
8918 if (tg3_asic_rev(tp) == ASIC_REV_5720) {
8919 val = tr32(TG3_CPMU_CLCK_ORIDE);
8920 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8923 /* Reprobe ASF enable state. */
8924 tg3_flag_clear(tp, ENABLE_ASF);
8925 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
8926 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
8928 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
8929 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8930 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8933 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8934 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
8935 tg3_flag_set(tp, ENABLE_ASF);
8936 tp->last_event_jiffies = jiffies;
8937 if (tg3_flag(tp, 5750_PLUS))
8938 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
8940 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
8941 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
8942 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
8943 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
8944 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
8951 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
8952 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
8954 /* tp->lock is held. */
8955 static int tg3_halt(struct tg3 *tp, int kind, int silent)
8961 tg3_write_sig_pre_reset(tp, kind);
8963 tg3_abort_hw(tp, silent);
8964 err = tg3_chip_reset(tp);
8966 __tg3_set_mac_addr(tp, 0);
8968 tg3_write_sig_legacy(tp, kind);
8969 tg3_write_sig_post_reset(tp, kind);
8972 /* Save the stats across chip resets... */
8973 tg3_get_nstats(tp, &tp->net_stats_prev);
8974 tg3_get_estats(tp, &tp->estats_prev);
8976 /* And make sure the next sample is new data */
8977 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
8986 static int tg3_set_mac_addr(struct net_device *dev, void *p)
8988 struct tg3 *tp = netdev_priv(dev);
8989 struct sockaddr *addr = p;
8990 int err = 0, skip_mac_1 = 0;
8992 if (!is_valid_ether_addr(addr->sa_data))
8993 return -EADDRNOTAVAIL;
8995 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
8997 if (!netif_running(dev))
9000 if (tg3_flag(tp, ENABLE_ASF)) {
9001 u32 addr0_high, addr0_low, addr1_high, addr1_low;
9003 addr0_high = tr32(MAC_ADDR_0_HIGH);
9004 addr0_low = tr32(MAC_ADDR_0_LOW);
9005 addr1_high = tr32(MAC_ADDR_1_HIGH);
9006 addr1_low = tr32(MAC_ADDR_1_LOW);
9008 /* Skip MAC addr 1 if ASF is using it. */
9009 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9010 !(addr1_high == 0 && addr1_low == 0))
9013 spin_lock_bh(&tp->lock);
9014 __tg3_set_mac_addr(tp, skip_mac_1);
9015 spin_unlock_bh(&tp->lock);
9020 /* tp->lock is held. */
9021 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9022 dma_addr_t mapping, u32 maxlen_flags,
9026 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9027 ((u64) mapping >> 32));
9029 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9030 ((u64) mapping & 0xffffffff));
9032 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9035 if (!tg3_flag(tp, 5705_PLUS))
9037 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9042 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9046 if (!tg3_flag(tp, ENABLE_TSS)) {
9047 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9048 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9049 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9051 tw32(HOSTCC_TXCOL_TICKS, 0);
9052 tw32(HOSTCC_TXMAX_FRAMES, 0);
9053 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9055 for (; i < tp->txq_cnt; i++) {
9058 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9059 tw32(reg, ec->tx_coalesce_usecs);
9060 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9061 tw32(reg, ec->tx_max_coalesced_frames);
9062 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9063 tw32(reg, ec->tx_max_coalesced_frames_irq);
9067 for (; i < tp->irq_max - 1; i++) {
9068 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9069 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9070 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9074 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9077 u32 limit = tp->rxq_cnt;
9079 if (!tg3_flag(tp, ENABLE_RSS)) {
9080 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9081 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9082 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9085 tw32(HOSTCC_RXCOL_TICKS, 0);
9086 tw32(HOSTCC_RXMAX_FRAMES, 0);
9087 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9090 for (; i < limit; i++) {
9093 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9094 tw32(reg, ec->rx_coalesce_usecs);
9095 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9096 tw32(reg, ec->rx_max_coalesced_frames);
9097 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9098 tw32(reg, ec->rx_max_coalesced_frames_irq);
9101 for (; i < tp->irq_max - 1; i++) {
9102 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9103 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9104 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9108 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9110 tg3_coal_tx_init(tp, ec);
9111 tg3_coal_rx_init(tp, ec);
9113 if (!tg3_flag(tp, 5705_PLUS)) {
9114 u32 val = ec->stats_block_coalesce_usecs;
9116 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9117 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9122 tw32(HOSTCC_STAT_COAL_TICKS, val);
9126 /* tp->lock is held. */
9127 static void tg3_rings_reset(struct tg3 *tp)
9130 u32 stblk, txrcb, rxrcb, limit;
9131 struct tg3_napi *tnapi = &tp->napi[0];
9133 /* Disable all transmit rings but the first. */
9134 if (!tg3_flag(tp, 5705_PLUS))
9135 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9136 else if (tg3_flag(tp, 5717_PLUS))
9137 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9138 else if (tg3_flag(tp, 57765_CLASS) ||
9139 tg3_asic_rev(tp) == ASIC_REV_5762)
9140 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9142 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9144 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9145 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9146 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9147 BDINFO_FLAGS_DISABLED);
9150 /* Disable all receive return rings but the first. */
9151 if (tg3_flag(tp, 5717_PLUS))
9152 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9153 else if (!tg3_flag(tp, 5705_PLUS))
9154 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9155 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9156 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9157 tg3_flag(tp, 57765_CLASS))
9158 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9160 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9162 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9163 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9164 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9165 BDINFO_FLAGS_DISABLED);
9167 /* Disable interrupts */
9168 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9169 tp->napi[0].chk_msi_cnt = 0;
9170 tp->napi[0].last_rx_cons = 0;
9171 tp->napi[0].last_tx_cons = 0;
9173 /* Zero mailbox registers. */
9174 if (tg3_flag(tp, SUPPORT_MSIX)) {
9175 for (i = 1; i < tp->irq_max; i++) {
9176 tp->napi[i].tx_prod = 0;
9177 tp->napi[i].tx_cons = 0;
9178 if (tg3_flag(tp, ENABLE_TSS))
9179 tw32_mailbox(tp->napi[i].prodmbox, 0);
9180 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9181 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9182 tp->napi[i].chk_msi_cnt = 0;
9183 tp->napi[i].last_rx_cons = 0;
9184 tp->napi[i].last_tx_cons = 0;
9186 if (!tg3_flag(tp, ENABLE_TSS))
9187 tw32_mailbox(tp->napi[0].prodmbox, 0);
9189 tp->napi[0].tx_prod = 0;
9190 tp->napi[0].tx_cons = 0;
9191 tw32_mailbox(tp->napi[0].prodmbox, 0);
9192 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9195 /* Make sure the NIC-based send BD rings are disabled. */
9196 if (!tg3_flag(tp, 5705_PLUS)) {
9197 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9198 for (i = 0; i < 16; i++)
9199 tw32_tx_mbox(mbox + i * 8, 0);
9202 txrcb = NIC_SRAM_SEND_RCB;
9203 rxrcb = NIC_SRAM_RCV_RET_RCB;
9205 /* Clear status block in ram. */
9206 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9208 /* Set status block DMA address */
9209 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9210 ((u64) tnapi->status_mapping >> 32));
9211 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9212 ((u64) tnapi->status_mapping & 0xffffffff));
9214 if (tnapi->tx_ring) {
9215 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9216 (TG3_TX_RING_SIZE <<
9217 BDINFO_FLAGS_MAXLEN_SHIFT),
9218 NIC_SRAM_TX_BUFFER_DESC);
9219 txrcb += TG3_BDINFO_SIZE;
9222 if (tnapi->rx_rcb) {
9223 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9224 (tp->rx_ret_ring_mask + 1) <<
9225 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9226 rxrcb += TG3_BDINFO_SIZE;
9229 stblk = HOSTCC_STATBLCK_RING1;
9231 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9232 u64 mapping = (u64)tnapi->status_mapping;
9233 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9234 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9236 /* Clear status block in ram. */
9237 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9239 if (tnapi->tx_ring) {
9240 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9241 (TG3_TX_RING_SIZE <<
9242 BDINFO_FLAGS_MAXLEN_SHIFT),
9243 NIC_SRAM_TX_BUFFER_DESC);
9244 txrcb += TG3_BDINFO_SIZE;
9247 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9248 ((tp->rx_ret_ring_mask + 1) <<
9249 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
9252 rxrcb += TG3_BDINFO_SIZE;
9256 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9258 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9260 if (!tg3_flag(tp, 5750_PLUS) ||
9261 tg3_flag(tp, 5780_CLASS) ||
9262 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9263 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9264 tg3_flag(tp, 57765_PLUS))
9265 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
9266 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9267 tg3_asic_rev(tp) == ASIC_REV_5787)
9268 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9270 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9272 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9273 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9275 val = min(nic_rep_thresh, host_rep_thresh);
9276 tw32(RCVBDI_STD_THRESH, val);
9278 if (tg3_flag(tp, 57765_PLUS))
9279 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9281 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9284 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
9286 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9288 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9289 tw32(RCVBDI_JUMBO_THRESH, val);
9291 if (tg3_flag(tp, 57765_PLUS))
9292 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9295 static inline u32 calc_crc(unsigned char *buf, int len)
9303 for (j = 0; j < len; j++) {
9306 for (k = 0; k < 8; k++) {
9319 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9321 /* accept or reject all multicast frames */
9322 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9323 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9324 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9325 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9328 static void __tg3_set_rx_mode(struct net_device *dev)
9330 struct tg3 *tp = netdev_priv(dev);
9333 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9334 RX_MODE_KEEP_VLAN_TAG);
9336 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9337 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9340 if (!tg3_flag(tp, ENABLE_ASF))
9341 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9344 if (dev->flags & IFF_PROMISC) {
9345 /* Promiscuous mode. */
9346 rx_mode |= RX_MODE_PROMISC;
9347 } else if (dev->flags & IFF_ALLMULTI) {
9348 /* Accept all multicast. */
9349 tg3_set_multi(tp, 1);
9350 } else if (netdev_mc_empty(dev)) {
9351 /* Reject all multicast. */
9352 tg3_set_multi(tp, 0);
9354 /* Accept one or more multicast(s). */
9355 struct netdev_hw_addr *ha;
9356 u32 mc_filter[4] = { 0, };
9361 netdev_for_each_mc_addr(ha, dev) {
9362 crc = calc_crc(ha->addr, ETH_ALEN);
9364 regidx = (bit & 0x60) >> 5;
9366 mc_filter[regidx] |= (1 << bit);
9369 tw32(MAC_HASH_REG_0, mc_filter[0]);
9370 tw32(MAC_HASH_REG_1, mc_filter[1]);
9371 tw32(MAC_HASH_REG_2, mc_filter[2]);
9372 tw32(MAC_HASH_REG_3, mc_filter[3]);
9375 if (rx_mode != tp->rx_mode) {
9376 tp->rx_mode = rx_mode;
9377 tw32_f(MAC_RX_MODE, rx_mode);
9382 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9386 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9387 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9390 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9394 if (!tg3_flag(tp, SUPPORT_MSIX))
9397 if (tp->rxq_cnt == 1) {
9398 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9402 /* Validate table against current IRQ count */
9403 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
9404 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9408 if (i != TG3_RSS_INDIR_TBL_SIZE)
9409 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9412 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9415 u32 reg = MAC_RSS_INDIR_TBL_0;
9417 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9418 u32 val = tp->rss_ind_tbl[i];
9420 for (; i % 8; i++) {
9422 val |= tp->rss_ind_tbl[i];
9429 /* tp->lock is held. */
9430 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
9432 u32 val, rdmac_mode;
9434 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9436 tg3_disable_ints(tp);
9440 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9442 if (tg3_flag(tp, INIT_COMPLETE))
9443 tg3_abort_hw(tp, 1);
9445 /* Enable MAC control of LPI */
9446 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
9447 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
9448 TG3_CPMU_EEE_LNKIDL_UART_IDL;
9449 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
9450 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
9452 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
9454 tw32_f(TG3_CPMU_EEE_CTRL,
9455 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
9457 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
9458 TG3_CPMU_EEEMD_LPI_IN_TX |
9459 TG3_CPMU_EEEMD_LPI_IN_RX |
9460 TG3_CPMU_EEEMD_EEE_ENABLE;
9462 if (tg3_asic_rev(tp) != ASIC_REV_5717)
9463 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
9465 if (tg3_flag(tp, ENABLE_APE))
9466 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
9468 tw32_f(TG3_CPMU_EEE_MODE, val);
9470 tw32_f(TG3_CPMU_EEE_DBTMR1,
9471 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
9472 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
9474 tw32_f(TG3_CPMU_EEE_DBTMR2,
9475 TG3_CPMU_DBTMR2_APE_TX_2047US |
9476 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
9479 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9480 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9481 tg3_phy_pull_config(tp);
9482 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9488 err = tg3_chip_reset(tp);
9492 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9494 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9495 val = tr32(TG3_CPMU_CTRL);
9496 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9497 tw32(TG3_CPMU_CTRL, val);
9499 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9500 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9501 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9502 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9504 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9505 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9506 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9507 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9509 val = tr32(TG3_CPMU_HST_ACC);
9510 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9511 val |= CPMU_HST_ACC_MACCLK_6_25;
9512 tw32(TG3_CPMU_HST_ACC, val);
9515 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9516 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9517 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9518 PCIE_PWR_MGMT_L1_THRESH_4MS;
9519 tw32(PCIE_PWR_MGMT_THRESH, val);
9521 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9522 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9524 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9526 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9527 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9530 if (tg3_flag(tp, L1PLLPD_EN)) {
9531 u32 grc_mode = tr32(GRC_MODE);
9533 /* Access the lower 1K of PL PCIE block registers. */
9534 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9535 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9537 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9538 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9539 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9541 tw32(GRC_MODE, grc_mode);
9544 if (tg3_flag(tp, 57765_CLASS)) {
9545 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9546 u32 grc_mode = tr32(GRC_MODE);
9548 /* Access the lower 1K of PL PCIE block registers. */
9549 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9550 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9552 val = tr32(TG3_PCIE_TLDLPL_PORT +
9553 TG3_PCIE_PL_LO_PHYCTL5);
9554 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9555 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
9557 tw32(GRC_MODE, grc_mode);
9560 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
9563 /* Fix transmit hangs */
9564 val = tr32(TG3_CPMU_PADRNG_CTL);
9565 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9566 tw32(TG3_CPMU_PADRNG_CTL, val);
9568 grc_mode = tr32(GRC_MODE);
9570 /* Access the lower 1K of DL PCIE block registers. */
9571 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9572 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9574 val = tr32(TG3_PCIE_TLDLPL_PORT +
9575 TG3_PCIE_DL_LO_FTSMAX);
9576 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9577 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9578 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9580 tw32(GRC_MODE, grc_mode);
9583 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9584 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9585 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9586 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9589 /* This works around an issue with Athlon chipsets on
9590 * B3 tigon3 silicon. This bit has no effect on any
9591 * other revision. But do not set this on PCI Express
9592 * chips and don't even touch the clocks if the CPMU is present.
9594 if (!tg3_flag(tp, CPMU_PRESENT)) {
9595 if (!tg3_flag(tp, PCI_EXPRESS))
9596 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9597 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9600 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
9601 tg3_flag(tp, PCIX_MODE)) {
9602 val = tr32(TG3PCI_PCISTATE);
9603 val |= PCISTATE_RETRY_SAME_DMA;
9604 tw32(TG3PCI_PCISTATE, val);
9607 if (tg3_flag(tp, ENABLE_APE)) {
9608 /* Allow reads and writes to the
9609 * APE register and memory space.
9611 val = tr32(TG3PCI_PCISTATE);
9612 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
9613 PCISTATE_ALLOW_APE_SHMEM_WR |
9614 PCISTATE_ALLOW_APE_PSPACE_WR;
9615 tw32(TG3PCI_PCISTATE, val);
9618 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
9619 /* Enable some hw fixes. */
9620 val = tr32(TG3PCI_MSI_DATA);
9621 val |= (1 << 26) | (1 << 28) | (1 << 29);
9622 tw32(TG3PCI_MSI_DATA, val);
9625 /* Descriptor ring init may make accesses to the
9626 * NIC SRAM area to setup the TX descriptors, so we
9627 * can only do this after the hardware has been
9628 * successfully reset.
9630 err = tg3_init_rings(tp);
9634 if (tg3_flag(tp, 57765_PLUS)) {
9635 val = tr32(TG3PCI_DMA_RW_CTRL) &
9636 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
9637 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
9638 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
9639 if (!tg3_flag(tp, 57765_CLASS) &&
9640 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9641 tg3_asic_rev(tp) != ASIC_REV_5762)
9642 val |= DMA_RWCTRL_TAGGED_STAT_WA;
9643 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
9644 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9645 tg3_asic_rev(tp) != ASIC_REV_5761) {
9646 /* This value is determined during the probe time DMA
9647 * engine test, tg3_test_dma.
9649 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9652 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9653 GRC_MODE_4X_NIC_SEND_RINGS |
9654 GRC_MODE_NO_TX_PHDR_CSUM |
9655 GRC_MODE_NO_RX_PHDR_CSUM);
9656 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
9658 /* Pseudo-header checksum is done by hardware logic and not
9659 * the offload processers, so make the chip do the pseudo-
9660 * header checksums on receive. For transmit it is more
9661 * convenient to do the pseudo-header checksum in software
9662 * as Linux does that on transmit for us in all cases.
9664 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
9666 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
9668 tw32(TG3_RX_PTP_CTL,
9669 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
9671 if (tg3_flag(tp, PTP_CAPABLE))
9672 val |= GRC_MODE_TIME_SYNC_ENABLE;
9674 tw32(GRC_MODE, tp->grc_mode | val);
9676 /* Setup the timer prescalar register. Clock is always 66Mhz. */
9677 val = tr32(GRC_MISC_CFG);
9679 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
9680 tw32(GRC_MISC_CFG, val);
9682 /* Initialize MBUF/DESC pool. */
9683 if (tg3_flag(tp, 5750_PLUS)) {
9685 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
9686 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
9687 if (tg3_asic_rev(tp) == ASIC_REV_5704)
9688 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
9690 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
9691 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
9692 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
9693 } else if (tg3_flag(tp, TSO_CAPABLE)) {
9696 fw_len = tp->fw_len;
9697 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
9698 tw32(BUFMGR_MB_POOL_ADDR,
9699 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
9700 tw32(BUFMGR_MB_POOL_SIZE,
9701 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
9704 if (tp->dev->mtu <= ETH_DATA_LEN) {
9705 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9706 tp->bufmgr_config.mbuf_read_dma_low_water);
9707 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9708 tp->bufmgr_config.mbuf_mac_rx_low_water);
9709 tw32(BUFMGR_MB_HIGH_WATER,
9710 tp->bufmgr_config.mbuf_high_water);
9712 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9713 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
9714 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9715 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
9716 tw32(BUFMGR_MB_HIGH_WATER,
9717 tp->bufmgr_config.mbuf_high_water_jumbo);
9719 tw32(BUFMGR_DMA_LOW_WATER,
9720 tp->bufmgr_config.dma_low_water);
9721 tw32(BUFMGR_DMA_HIGH_WATER,
9722 tp->bufmgr_config.dma_high_water);
9724 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
9725 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9726 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
9727 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
9728 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
9729 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
9730 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
9731 tw32(BUFMGR_MODE, val);
9732 for (i = 0; i < 2000; i++) {
9733 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
9738 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
9742 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
9743 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
9745 tg3_setup_rxbd_thresholds(tp);
9747 /* Initialize TG3_BDINFO's at:
9748 * RCVDBDI_STD_BD: standard eth size rx ring
9749 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
9750 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
9753 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
9754 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
9755 * ring attribute flags
9756 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
9758 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
9759 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
9761 * The size of each ring is fixed in the firmware, but the location is
9764 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
9765 ((u64) tpr->rx_std_mapping >> 32));
9766 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
9767 ((u64) tpr->rx_std_mapping & 0xffffffff));
9768 if (!tg3_flag(tp, 5717_PLUS))
9769 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
9770 NIC_SRAM_RX_BUFFER_DESC);
9772 /* Disable the mini ring */
9773 if (!tg3_flag(tp, 5705_PLUS))
9774 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
9775 BDINFO_FLAGS_DISABLED);
9777 /* Program the jumbo buffer descriptor ring control
9778 * blocks on those devices that have them.
9780 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
9781 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
9783 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
9784 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
9785 ((u64) tpr->rx_jmb_mapping >> 32));
9786 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
9787 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
9788 val = TG3_RX_JMB_RING_SIZE(tp) <<
9789 BDINFO_FLAGS_MAXLEN_SHIFT;
9790 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
9791 val | BDINFO_FLAGS_USE_EXT_RECV);
9792 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
9793 tg3_flag(tp, 57765_CLASS) ||
9794 tg3_asic_rev(tp) == ASIC_REV_5762)
9795 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
9796 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
9798 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
9799 BDINFO_FLAGS_DISABLED);
9802 if (tg3_flag(tp, 57765_PLUS)) {
9803 val = TG3_RX_STD_RING_SIZE(tp);
9804 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
9805 val |= (TG3_RX_STD_DMA_SZ << 2);
9807 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
9809 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
9811 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
9813 tpr->rx_std_prod_idx = tp->rx_pending;
9814 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
9816 tpr->rx_jmb_prod_idx =
9817 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
9818 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
9820 tg3_rings_reset(tp);
9822 /* Initialize MAC address and backoff seed. */
9823 __tg3_set_mac_addr(tp, 0);
9825 /* MTU + ethernet header + FCS + optional VLAN tag */
9826 tw32(MAC_RX_MTU_SIZE,
9827 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
9829 /* The slot time is changed by tg3_setup_phy if we
9830 * run at gigabit with half duplex.
9832 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
9833 (6 << TX_LENGTHS_IPG_SHIFT) |
9834 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
9836 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
9837 tg3_asic_rev(tp) == ASIC_REV_5762)
9838 val |= tr32(MAC_TX_LENGTHS) &
9839 (TX_LENGTHS_JMB_FRM_LEN_MSK |
9840 TX_LENGTHS_CNT_DWN_VAL_MSK);
9842 tw32(MAC_TX_LENGTHS, val);
9844 /* Receive rules. */
9845 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
9846 tw32(RCVLPC_CONFIG, 0x0181);
9848 /* Calculate RDMAC_MODE setting early, we need it to determine
9849 * the RCVLPC_STATE_ENABLE mask.
9851 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
9852 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
9853 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
9854 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
9855 RDMAC_MODE_LNGREAD_ENAB);
9857 if (tg3_asic_rev(tp) == ASIC_REV_5717)
9858 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
9860 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
9861 tg3_asic_rev(tp) == ASIC_REV_5785 ||
9862 tg3_asic_rev(tp) == ASIC_REV_57780)
9863 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
9864 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
9865 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
9867 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
9868 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
9869 if (tg3_flag(tp, TSO_CAPABLE) &&
9870 tg3_asic_rev(tp) == ASIC_REV_5705) {
9871 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
9872 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
9873 !tg3_flag(tp, IS_5788)) {
9874 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
9878 if (tg3_flag(tp, PCI_EXPRESS))
9879 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
9881 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
9883 if (tp->dev->mtu <= ETH_DATA_LEN) {
9884 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
9885 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
9889 if (tg3_flag(tp, HW_TSO_1) ||
9890 tg3_flag(tp, HW_TSO_2) ||
9891 tg3_flag(tp, HW_TSO_3))
9892 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
9894 if (tg3_flag(tp, 57765_PLUS) ||
9895 tg3_asic_rev(tp) == ASIC_REV_5785 ||
9896 tg3_asic_rev(tp) == ASIC_REV_57780)
9897 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
9899 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
9900 tg3_asic_rev(tp) == ASIC_REV_5762)
9901 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
9903 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
9904 tg3_asic_rev(tp) == ASIC_REV_5784 ||
9905 tg3_asic_rev(tp) == ASIC_REV_5785 ||
9906 tg3_asic_rev(tp) == ASIC_REV_57780 ||
9907 tg3_flag(tp, 57765_PLUS)) {
9910 if (tg3_asic_rev(tp) == ASIC_REV_5762)
9911 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
9913 tgtreg = TG3_RDMA_RSRVCTRL_REG;
9916 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
9917 tg3_asic_rev(tp) == ASIC_REV_5762) {
9918 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
9919 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
9920 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
9921 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
9922 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
9923 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
9925 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
9928 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
9929 tg3_asic_rev(tp) == ASIC_REV_5720 ||
9930 tg3_asic_rev(tp) == ASIC_REV_5762) {
9933 if (tg3_asic_rev(tp) == ASIC_REV_5762)
9934 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
9936 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
9940 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
9941 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
9944 /* Receive/send statistics. */
9945 if (tg3_flag(tp, 5750_PLUS)) {
9946 val = tr32(RCVLPC_STATS_ENABLE);
9947 val &= ~RCVLPC_STATSENAB_DACK_FIX;
9948 tw32(RCVLPC_STATS_ENABLE, val);
9949 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
9950 tg3_flag(tp, TSO_CAPABLE)) {
9951 val = tr32(RCVLPC_STATS_ENABLE);
9952 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
9953 tw32(RCVLPC_STATS_ENABLE, val);
9955 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
9957 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
9958 tw32(SNDDATAI_STATSENAB, 0xffffff);
9959 tw32(SNDDATAI_STATSCTRL,
9960 (SNDDATAI_SCTRL_ENABLE |
9961 SNDDATAI_SCTRL_FASTUPD));
9963 /* Setup host coalescing engine. */
9964 tw32(HOSTCC_MODE, 0);
9965 for (i = 0; i < 2000; i++) {
9966 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
9971 __tg3_set_coalesce(tp, &tp->coal);
9973 if (!tg3_flag(tp, 5705_PLUS)) {
9974 /* Status/statistics block address. See tg3_timer,
9975 * the tg3_periodic_fetch_stats call there, and
9976 * tg3_get_stats to see how this works for 5705/5750 chips.
9978 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9979 ((u64) tp->stats_mapping >> 32));
9980 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9981 ((u64) tp->stats_mapping & 0xffffffff));
9982 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
9984 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
9986 /* Clear statistics and status block memory areas */
9987 for (i = NIC_SRAM_STATS_BLK;
9988 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
9990 tg3_write_mem(tp, i, 0);
9995 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
9997 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
9998 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
9999 if (!tg3_flag(tp, 5705_PLUS))
10000 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10002 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10003 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10004 /* reset to prevent losing 1st rx packet intermittently */
10005 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10009 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10010 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10011 MAC_MODE_FHDE_ENABLE;
10012 if (tg3_flag(tp, ENABLE_APE))
10013 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10014 if (!tg3_flag(tp, 5705_PLUS) &&
10015 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10016 tg3_asic_rev(tp) != ASIC_REV_5700)
10017 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10018 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10021 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10022 * If TG3_FLAG_IS_NIC is zero, we should read the
10023 * register to preserve the GPIO settings for LOMs. The GPIOs,
10024 * whether used as inputs or outputs, are set by boot code after
10027 if (!tg3_flag(tp, IS_NIC)) {
10030 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10031 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10032 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
10034 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10035 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10036 GRC_LCLCTRL_GPIO_OUTPUT3;
10038 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10039 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10041 tp->grc_local_ctrl &= ~gpio_mask;
10042 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10044 /* GPIO1 must be driven high for eeprom write protect */
10045 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10046 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10047 GRC_LCLCTRL_GPIO_OUTPUT1);
10049 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10052 if (tg3_flag(tp, USING_MSIX)) {
10053 val = tr32(MSGINT_MODE);
10054 val |= MSGINT_MODE_ENABLE;
10055 if (tp->irq_cnt > 1)
10056 val |= MSGINT_MODE_MULTIVEC_EN;
10057 if (!tg3_flag(tp, 1SHOT_MSI))
10058 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
10059 tw32(MSGINT_MODE, val);
10062 if (!tg3_flag(tp, 5705_PLUS)) {
10063 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10067 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10068 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10069 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10070 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10071 WDMAC_MODE_LNGREAD_ENAB);
10073 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10074 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10075 if (tg3_flag(tp, TSO_CAPABLE) &&
10076 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10077 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10079 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10080 !tg3_flag(tp, IS_5788)) {
10081 val |= WDMAC_MODE_RX_ACCEL;
10085 /* Enable host coalescing bug fix */
10086 if (tg3_flag(tp, 5755_PLUS))
10087 val |= WDMAC_MODE_STATUS_TAG_FIX;
10089 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10090 val |= WDMAC_MODE_BURST_ALL_DATA;
10092 tw32_f(WDMAC_MODE, val);
10095 if (tg3_flag(tp, PCIX_MODE)) {
10098 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10100 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10101 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10102 pcix_cmd |= PCI_X_CMD_READ_2K;
10103 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10104 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10105 pcix_cmd |= PCI_X_CMD_READ_2K;
10107 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10111 tw32_f(RDMAC_MODE, rdmac_mode);
10114 if (tg3_asic_rev(tp) == ASIC_REV_5719) {
10115 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10116 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10119 if (i < TG3_NUM_RDMA_CHANNELS) {
10120 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10121 val |= TG3_LSO_RD_DMA_TX_LENGTH_WA;
10122 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10123 tg3_flag_set(tp, 5719_RDMA_BUG);
10127 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10128 if (!tg3_flag(tp, 5705_PLUS))
10129 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10131 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10132 tw32(SNDDATAC_MODE,
10133 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10135 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10137 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10138 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10139 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
10140 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10141 val |= RCVDBDI_MODE_LRG_RING_SZ;
10142 tw32(RCVDBDI_MODE, val);
10143 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10144 if (tg3_flag(tp, HW_TSO_1) ||
10145 tg3_flag(tp, HW_TSO_2) ||
10146 tg3_flag(tp, HW_TSO_3))
10147 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10148 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
10149 if (tg3_flag(tp, ENABLE_TSS))
10150 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10151 tw32(SNDBDI_MODE, val);
10152 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10154 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10155 err = tg3_load_5701_a0_firmware_fix(tp);
10160 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10161 /* Ignore any errors for the firmware download. If download
10162 * fails, the device will operate with EEE disabled
10164 tg3_load_57766_firmware(tp);
10167 if (tg3_flag(tp, TSO_CAPABLE)) {
10168 err = tg3_load_tso_firmware(tp);
10173 tp->tx_mode = TX_MODE_ENABLE;
10175 if (tg3_flag(tp, 5755_PLUS) ||
10176 tg3_asic_rev(tp) == ASIC_REV_5906)
10177 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10179 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10180 tg3_asic_rev(tp) == ASIC_REV_5762) {
10181 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10182 tp->tx_mode &= ~val;
10183 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10186 tw32_f(MAC_TX_MODE, tp->tx_mode);
10189 if (tg3_flag(tp, ENABLE_RSS)) {
10190 tg3_rss_write_indir_tbl(tp);
10192 /* Setup the "secret" hash key. */
10193 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10194 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10195 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10196 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10197 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10198 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10199 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10200 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10201 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10202 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10205 tp->rx_mode = RX_MODE_ENABLE;
10206 if (tg3_flag(tp, 5755_PLUS))
10207 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10209 if (tg3_flag(tp, ENABLE_RSS))
10210 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10211 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10212 RX_MODE_RSS_IPV6_HASH_EN |
10213 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10214 RX_MODE_RSS_IPV4_HASH_EN |
10215 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10217 tw32_f(MAC_RX_MODE, tp->rx_mode);
10220 tw32(MAC_LED_CTRL, tp->led_ctrl);
10222 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10223 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10224 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10227 tw32_f(MAC_RX_MODE, tp->rx_mode);
10230 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10231 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10232 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10233 /* Set drive transmission level to 1.2V */
10234 /* only if the signal pre-emphasis bit is not set */
10235 val = tr32(MAC_SERDES_CFG);
10238 tw32(MAC_SERDES_CFG, val);
10240 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10241 tw32(MAC_SERDES_CFG, 0x616000);
10244 /* Prevent chip from dropping frames when flow control
10247 if (tg3_flag(tp, 57765_CLASS))
10251 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
10253 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10254 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10255 /* Use hardware link auto-negotiation */
10256 tg3_flag_set(tp, HW_AUTONEG);
10259 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10260 tg3_asic_rev(tp) == ASIC_REV_5714) {
10263 tmp = tr32(SERDES_RX_CTRL);
10264 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10265 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10266 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10267 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10270 if (!tg3_flag(tp, USE_PHYLIB)) {
10271 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10272 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10274 err = tg3_setup_phy(tp, 0);
10278 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10279 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10282 /* Clear CRC stats. */
10283 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10284 tg3_writephy(tp, MII_TG3_TEST1,
10285 tmp | MII_TG3_TEST1_CRC_EN);
10286 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10291 __tg3_set_rx_mode(tp->dev);
10293 /* Initialize receive rules. */
10294 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10295 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10296 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10297 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10299 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10303 if (tg3_flag(tp, ENABLE_ASF))
10307 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10309 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10311 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10313 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10315 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10317 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10319 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10321 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10323 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10325 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10327 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10329 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10331 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10333 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10341 if (tg3_flag(tp, ENABLE_APE))
10342 /* Write our heartbeat update interval to APE. */
10343 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10344 APE_HOST_HEARTBEAT_INT_DISABLE);
10346 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10351 /* Called at device open time to get the chip ready for
10352 * packet processing. Invoked with tp->lock held.
10354 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
10356 tg3_switch_clocks(tp);
10358 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10360 return tg3_reset_hw(tp, reset_phy);
10363 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10367 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10368 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10370 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10373 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10374 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10375 memset(ocir, 0, TG3_OCIR_LEN);
10379 /* sysfs attributes for hwmon */
10380 static ssize_t tg3_show_temp(struct device *dev,
10381 struct device_attribute *devattr, char *buf)
10383 struct pci_dev *pdev = to_pci_dev(dev);
10384 struct net_device *netdev = pci_get_drvdata(pdev);
10385 struct tg3 *tp = netdev_priv(netdev);
10386 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10389 spin_lock_bh(&tp->lock);
10390 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10391 sizeof(temperature));
10392 spin_unlock_bh(&tp->lock);
10393 return sprintf(buf, "%u\n", temperature);
10397 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10398 TG3_TEMP_SENSOR_OFFSET);
10399 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10400 TG3_TEMP_CAUTION_OFFSET);
10401 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10402 TG3_TEMP_MAX_OFFSET);
10404 static struct attribute *tg3_attributes[] = {
10405 &sensor_dev_attr_temp1_input.dev_attr.attr,
10406 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10407 &sensor_dev_attr_temp1_max.dev_attr.attr,
10411 static const struct attribute_group tg3_group = {
10412 .attrs = tg3_attributes,
10415 static void tg3_hwmon_close(struct tg3 *tp)
10417 if (tp->hwmon_dev) {
10418 hwmon_device_unregister(tp->hwmon_dev);
10419 tp->hwmon_dev = NULL;
10420 sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group);
10424 static void tg3_hwmon_open(struct tg3 *tp)
10428 struct pci_dev *pdev = tp->pdev;
10429 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10431 tg3_sd_scan_scratchpad(tp, ocirs);
10433 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10434 if (!ocirs[i].src_data_length)
10437 size += ocirs[i].src_hdr_length;
10438 size += ocirs[i].src_data_length;
10444 /* Register hwmon sysfs hooks */
10445 err = sysfs_create_group(&pdev->dev.kobj, &tg3_group);
10447 dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n");
10451 tp->hwmon_dev = hwmon_device_register(&pdev->dev);
10452 if (IS_ERR(tp->hwmon_dev)) {
10453 tp->hwmon_dev = NULL;
10454 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10455 sysfs_remove_group(&pdev->dev.kobj, &tg3_group);
10460 #define TG3_STAT_ADD32(PSTAT, REG) \
10461 do { u32 __val = tr32(REG); \
10462 (PSTAT)->low += __val; \
10463 if ((PSTAT)->low < __val) \
10464 (PSTAT)->high += 1; \
10467 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10469 struct tg3_hw_stats *sp = tp->hw_stats;
10474 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10475 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10476 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10477 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10478 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10479 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10480 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10481 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10482 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10483 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10484 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10485 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10486 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
10487 if (unlikely(tg3_flag(tp, 5719_RDMA_BUG) &&
10488 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10489 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10492 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10493 val &= ~TG3_LSO_RD_DMA_TX_LENGTH_WA;
10494 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10495 tg3_flag_clear(tp, 5719_RDMA_BUG);
10498 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10499 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10500 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10501 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10502 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10503 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10504 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10505 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10506 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10507 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10508 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10509 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10510 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10511 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
10513 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
10514 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10515 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10516 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10517 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10519 u32 val = tr32(HOSTCC_FLOW_ATTN);
10520 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10522 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10523 sp->rx_discards.low += val;
10524 if (sp->rx_discards.low < val)
10525 sp->rx_discards.high += 1;
10527 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10529 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
10532 static void tg3_chk_missed_msi(struct tg3 *tp)
10536 for (i = 0; i < tp->irq_cnt; i++) {
10537 struct tg3_napi *tnapi = &tp->napi[i];
10539 if (tg3_has_work(tnapi)) {
10540 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10541 tnapi->last_tx_cons == tnapi->tx_cons) {
10542 if (tnapi->chk_msi_cnt < 1) {
10543 tnapi->chk_msi_cnt++;
10549 tnapi->chk_msi_cnt = 0;
10550 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10551 tnapi->last_tx_cons = tnapi->tx_cons;
10555 static void tg3_timer(unsigned long __opaque)
10557 struct tg3 *tp = (struct tg3 *) __opaque;
10559 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
10560 goto restart_timer;
10562 spin_lock(&tp->lock);
10564 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10565 tg3_flag(tp, 57765_CLASS))
10566 tg3_chk_missed_msi(tp);
10568 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10569 /* BCM4785: Flush posted writes from GbE to host memory. */
10573 if (!tg3_flag(tp, TAGGED_STATUS)) {
10574 /* All of this garbage is because when using non-tagged
10575 * IRQ status the mailbox/status_block protocol the chip
10576 * uses with the cpu is race prone.
10578 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
10579 tw32(GRC_LOCAL_CTRL,
10580 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10582 tw32(HOSTCC_MODE, tp->coalesce_mode |
10583 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
10586 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10587 spin_unlock(&tp->lock);
10588 tg3_reset_task_schedule(tp);
10589 goto restart_timer;
10593 /* This part only runs once per second. */
10594 if (!--tp->timer_counter) {
10595 if (tg3_flag(tp, 5705_PLUS))
10596 tg3_periodic_fetch_stats(tp);
10598 if (tp->setlpicnt && !--tp->setlpicnt)
10599 tg3_phy_eee_enable(tp);
10601 if (tg3_flag(tp, USE_LINKCHG_REG)) {
10605 mac_stat = tr32(MAC_STATUS);
10608 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
10609 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10611 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10615 tg3_setup_phy(tp, 0);
10616 } else if (tg3_flag(tp, POLL_SERDES)) {
10617 u32 mac_stat = tr32(MAC_STATUS);
10618 int need_setup = 0;
10621 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10624 if (!tp->link_up &&
10625 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10626 MAC_STATUS_SIGNAL_DET))) {
10630 if (!tp->serdes_counter) {
10633 ~MAC_MODE_PORT_MODE_MASK));
10635 tw32_f(MAC_MODE, tp->mac_mode);
10638 tg3_setup_phy(tp, 0);
10640 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10641 tg3_flag(tp, 5780_CLASS)) {
10642 tg3_serdes_parallel_detect(tp);
10645 tp->timer_counter = tp->timer_multiplier;
10648 /* Heartbeat is only sent once every 2 seconds.
10650 * The heartbeat is to tell the ASF firmware that the host
10651 * driver is still alive. In the event that the OS crashes,
10652 * ASF needs to reset the hardware to free up the FIFO space
10653 * that may be filled with rx packets destined for the host.
10654 * If the FIFO is full, ASF will no longer function properly.
10656 * Unintended resets have been reported on real time kernels
10657 * where the timer doesn't run on time. Netpoll will also have
10660 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10661 * to check the ring condition when the heartbeat is expiring
10662 * before doing the reset. This will prevent most unintended
10665 if (!--tp->asf_counter) {
10666 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
10667 tg3_wait_for_event_ack(tp);
10669 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
10670 FWCMD_NICDRV_ALIVE3);
10671 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
10672 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
10673 TG3_FW_UPDATE_TIMEOUT_SEC);
10675 tg3_generate_fw_event(tp);
10677 tp->asf_counter = tp->asf_multiplier;
10680 spin_unlock(&tp->lock);
10683 tp->timer.expires = jiffies + tp->timer_offset;
10684 add_timer(&tp->timer);
10687 static void tg3_timer_init(struct tg3 *tp)
10689 if (tg3_flag(tp, TAGGED_STATUS) &&
10690 tg3_asic_rev(tp) != ASIC_REV_5717 &&
10691 !tg3_flag(tp, 57765_CLASS))
10692 tp->timer_offset = HZ;
10694 tp->timer_offset = HZ / 10;
10696 BUG_ON(tp->timer_offset > HZ);
10698 tp->timer_multiplier = (HZ / tp->timer_offset);
10699 tp->asf_multiplier = (HZ / tp->timer_offset) *
10700 TG3_FW_UPDATE_FREQ_SEC;
10702 init_timer(&tp->timer);
10703 tp->timer.data = (unsigned long) tp;
10704 tp->timer.function = tg3_timer;
10707 static void tg3_timer_start(struct tg3 *tp)
10709 tp->asf_counter = tp->asf_multiplier;
10710 tp->timer_counter = tp->timer_multiplier;
10712 tp->timer.expires = jiffies + tp->timer_offset;
10713 add_timer(&tp->timer);
10716 static void tg3_timer_stop(struct tg3 *tp)
10718 del_timer_sync(&tp->timer);
10721 /* Restart hardware after configuration changes, self-test, etc.
10722 * Invoked with tp->lock held.
10724 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
10725 __releases(tp->lock)
10726 __acquires(tp->lock)
10730 err = tg3_init_hw(tp, reset_phy);
10732 netdev_err(tp->dev,
10733 "Failed to re-initialize device, aborting\n");
10734 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10735 tg3_full_unlock(tp);
10736 tg3_timer_stop(tp);
10738 tg3_napi_enable(tp);
10739 dev_close(tp->dev);
10740 tg3_full_lock(tp, 0);
10745 static void tg3_reset_task(struct work_struct *work)
10747 struct tg3 *tp = container_of(work, struct tg3, reset_task);
10750 tg3_full_lock(tp, 0);
10752 if (!netif_running(tp->dev)) {
10753 tg3_flag_clear(tp, RESET_TASK_PENDING);
10754 tg3_full_unlock(tp);
10758 tg3_full_unlock(tp);
10762 tg3_netif_stop(tp);
10764 tg3_full_lock(tp, 1);
10766 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
10767 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10768 tp->write32_rx_mbox = tg3_write_flush_reg32;
10769 tg3_flag_set(tp, MBOX_WRITE_REORDER);
10770 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
10773 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
10774 err = tg3_init_hw(tp, 1);
10778 tg3_netif_start(tp);
10781 tg3_full_unlock(tp);
10786 tg3_flag_clear(tp, RESET_TASK_PENDING);
10789 static int tg3_request_irq(struct tg3 *tp, int irq_num)
10792 unsigned long flags;
10794 struct tg3_napi *tnapi = &tp->napi[irq_num];
10796 if (tp->irq_cnt == 1)
10797 name = tp->dev->name;
10799 name = &tnapi->irq_lbl[0];
10800 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
10801 name[IFNAMSIZ-1] = 0;
10804 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
10806 if (tg3_flag(tp, 1SHOT_MSI))
10807 fn = tg3_msi_1shot;
10810 fn = tg3_interrupt;
10811 if (tg3_flag(tp, TAGGED_STATUS))
10812 fn = tg3_interrupt_tagged;
10813 flags = IRQF_SHARED;
10816 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
10819 static int tg3_test_interrupt(struct tg3 *tp)
10821 struct tg3_napi *tnapi = &tp->napi[0];
10822 struct net_device *dev = tp->dev;
10823 int err, i, intr_ok = 0;
10826 if (!netif_running(dev))
10829 tg3_disable_ints(tp);
10831 free_irq(tnapi->irq_vec, tnapi);
10834 * Turn off MSI one shot mode. Otherwise this test has no
10835 * observable way to know whether the interrupt was delivered.
10837 if (tg3_flag(tp, 57765_PLUS)) {
10838 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
10839 tw32(MSGINT_MODE, val);
10842 err = request_irq(tnapi->irq_vec, tg3_test_isr,
10843 IRQF_SHARED, dev->name, tnapi);
10847 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
10848 tg3_enable_ints(tp);
10850 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10853 for (i = 0; i < 5; i++) {
10854 u32 int_mbox, misc_host_ctrl;
10856 int_mbox = tr32_mailbox(tnapi->int_mbox);
10857 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
10859 if ((int_mbox != 0) ||
10860 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
10865 if (tg3_flag(tp, 57765_PLUS) &&
10866 tnapi->hw_status->status_tag != tnapi->last_tag)
10867 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
10872 tg3_disable_ints(tp);
10874 free_irq(tnapi->irq_vec, tnapi);
10876 err = tg3_request_irq(tp, 0);
10882 /* Reenable MSI one shot mode. */
10883 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
10884 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
10885 tw32(MSGINT_MODE, val);
10893 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
10894 * successfully restored
10896 static int tg3_test_msi(struct tg3 *tp)
10901 if (!tg3_flag(tp, USING_MSI))
10904 /* Turn off SERR reporting in case MSI terminates with Master
10907 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10908 pci_write_config_word(tp->pdev, PCI_COMMAND,
10909 pci_cmd & ~PCI_COMMAND_SERR);
10911 err = tg3_test_interrupt(tp);
10913 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10918 /* other failures */
10922 /* MSI test failed, go back to INTx mode */
10923 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
10924 "to INTx mode. Please report this failure to the PCI "
10925 "maintainer and include system chipset information\n");
10927 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
10929 pci_disable_msi(tp->pdev);
10931 tg3_flag_clear(tp, USING_MSI);
10932 tp->napi[0].irq_vec = tp->pdev->irq;
10934 err = tg3_request_irq(tp, 0);
10938 /* Need to reset the chip because the MSI cycle may have terminated
10939 * with Master Abort.
10941 tg3_full_lock(tp, 1);
10943 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10944 err = tg3_init_hw(tp, 1);
10946 tg3_full_unlock(tp);
10949 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
10954 static int tg3_request_firmware(struct tg3 *tp)
10956 const struct tg3_firmware_hdr *fw_hdr;
10958 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
10959 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
10964 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
10966 /* Firmware blob starts with version numbers, followed by
10967 * start address and _full_ length including BSS sections
10968 * (which must be longer than the actual data, of course
10971 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
10972 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
10973 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
10974 tp->fw_len, tp->fw_needed);
10975 release_firmware(tp->fw);
10980 /* We no longer need firmware; we have it. */
10981 tp->fw_needed = NULL;
10985 static u32 tg3_irq_count(struct tg3 *tp)
10987 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
10990 /* We want as many rx rings enabled as there are cpus.
10991 * In multiqueue MSI-X mode, the first MSI-X vector
10992 * only deals with link interrupts, etc, so we add
10993 * one to the number of vectors we are requesting.
10995 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11001 static bool tg3_enable_msix(struct tg3 *tp)
11004 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
11006 tp->txq_cnt = tp->txq_req;
11007 tp->rxq_cnt = tp->rxq_req;
11009 tp->rxq_cnt = netif_get_num_default_rss_queues();
11010 if (tp->rxq_cnt > tp->rxq_max)
11011 tp->rxq_cnt = tp->rxq_max;
11013 /* Disable multiple TX rings by default. Simple round-robin hardware
11014 * scheduling of the TX rings can cause starvation of rings with
11015 * small packets when other rings have TSO or jumbo packets.
11020 tp->irq_cnt = tg3_irq_count(tp);
11022 for (i = 0; i < tp->irq_max; i++) {
11023 msix_ent[i].entry = i;
11024 msix_ent[i].vector = 0;
11027 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
11030 } else if (rc != 0) {
11031 if (pci_enable_msix(tp->pdev, msix_ent, rc))
11033 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11036 tp->rxq_cnt = max(rc - 1, 1);
11038 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11041 for (i = 0; i < tp->irq_max; i++)
11042 tp->napi[i].irq_vec = msix_ent[i].vector;
11044 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11045 pci_disable_msix(tp->pdev);
11049 if (tp->irq_cnt == 1)
11052 tg3_flag_set(tp, ENABLE_RSS);
11054 if (tp->txq_cnt > 1)
11055 tg3_flag_set(tp, ENABLE_TSS);
11057 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11062 static void tg3_ints_init(struct tg3 *tp)
11064 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11065 !tg3_flag(tp, TAGGED_STATUS)) {
11066 /* All MSI supporting chips should support tagged
11067 * status. Assert that this is the case.
11069 netdev_warn(tp->dev,
11070 "MSI without TAGGED_STATUS? Not using MSI\n");
11074 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11075 tg3_flag_set(tp, USING_MSIX);
11076 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11077 tg3_flag_set(tp, USING_MSI);
11079 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11080 u32 msi_mode = tr32(MSGINT_MODE);
11081 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11082 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
11083 if (!tg3_flag(tp, 1SHOT_MSI))
11084 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
11085 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11088 if (!tg3_flag(tp, USING_MSIX)) {
11090 tp->napi[0].irq_vec = tp->pdev->irq;
11093 if (tp->irq_cnt == 1) {
11096 netif_set_real_num_tx_queues(tp->dev, 1);
11097 netif_set_real_num_rx_queues(tp->dev, 1);
11101 static void tg3_ints_fini(struct tg3 *tp)
11103 if (tg3_flag(tp, USING_MSIX))
11104 pci_disable_msix(tp->pdev);
11105 else if (tg3_flag(tp, USING_MSI))
11106 pci_disable_msi(tp->pdev);
11107 tg3_flag_clear(tp, USING_MSI);
11108 tg3_flag_clear(tp, USING_MSIX);
11109 tg3_flag_clear(tp, ENABLE_RSS);
11110 tg3_flag_clear(tp, ENABLE_TSS);
11113 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11116 struct net_device *dev = tp->dev;
11120 * Setup interrupts first so we know how
11121 * many NAPI resources to allocate
11125 tg3_rss_check_indir_tbl(tp);
11127 /* The placement of this call is tied
11128 * to the setup and use of Host TX descriptors.
11130 err = tg3_alloc_consistent(tp);
11136 tg3_napi_enable(tp);
11138 for (i = 0; i < tp->irq_cnt; i++) {
11139 struct tg3_napi *tnapi = &tp->napi[i];
11140 err = tg3_request_irq(tp, i);
11142 for (i--; i >= 0; i--) {
11143 tnapi = &tp->napi[i];
11144 free_irq(tnapi->irq_vec, tnapi);
11150 tg3_full_lock(tp, 0);
11152 err = tg3_init_hw(tp, reset_phy);
11154 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11155 tg3_free_rings(tp);
11158 tg3_full_unlock(tp);
11163 if (test_irq && tg3_flag(tp, USING_MSI)) {
11164 err = tg3_test_msi(tp);
11167 tg3_full_lock(tp, 0);
11168 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11169 tg3_free_rings(tp);
11170 tg3_full_unlock(tp);
11175 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11176 u32 val = tr32(PCIE_TRANSACTION_CFG);
11178 tw32(PCIE_TRANSACTION_CFG,
11179 val | PCIE_TRANS_CFG_1SHOT_MSI);
11185 tg3_hwmon_open(tp);
11187 tg3_full_lock(tp, 0);
11189 tg3_timer_start(tp);
11190 tg3_flag_set(tp, INIT_COMPLETE);
11191 tg3_enable_ints(tp);
11196 tg3_ptp_resume(tp);
11199 tg3_full_unlock(tp);
11201 netif_tx_start_all_queues(dev);
11204 * Reset loopback feature if it was turned on while the device was down
11205 * make sure that it's installed properly now.
11207 if (dev->features & NETIF_F_LOOPBACK)
11208 tg3_set_loopback(dev, dev->features);
11213 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11214 struct tg3_napi *tnapi = &tp->napi[i];
11215 free_irq(tnapi->irq_vec, tnapi);
11219 tg3_napi_disable(tp);
11221 tg3_free_consistent(tp);
11229 static void tg3_stop(struct tg3 *tp)
11233 tg3_reset_task_cancel(tp);
11234 tg3_netif_stop(tp);
11236 tg3_timer_stop(tp);
11238 tg3_hwmon_close(tp);
11242 tg3_full_lock(tp, 1);
11244 tg3_disable_ints(tp);
11246 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11247 tg3_free_rings(tp);
11248 tg3_flag_clear(tp, INIT_COMPLETE);
11250 tg3_full_unlock(tp);
11252 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11253 struct tg3_napi *tnapi = &tp->napi[i];
11254 free_irq(tnapi->irq_vec, tnapi);
11261 tg3_free_consistent(tp);
11264 static int tg3_open(struct net_device *dev)
11266 struct tg3 *tp = netdev_priv(dev);
11269 if (tp->fw_needed) {
11270 err = tg3_request_firmware(tp);
11271 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11273 netdev_warn(tp->dev, "EEE capability disabled\n");
11274 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11275 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11276 netdev_warn(tp->dev, "EEE capability restored\n");
11277 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11279 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11283 netdev_warn(tp->dev, "TSO capability disabled\n");
11284 tg3_flag_clear(tp, TSO_CAPABLE);
11285 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11286 netdev_notice(tp->dev, "TSO capability restored\n");
11287 tg3_flag_set(tp, TSO_CAPABLE);
11291 tg3_carrier_off(tp);
11293 err = tg3_power_up(tp);
11297 tg3_full_lock(tp, 0);
11299 tg3_disable_ints(tp);
11300 tg3_flag_clear(tp, INIT_COMPLETE);
11302 tg3_full_unlock(tp);
11304 err = tg3_start(tp,
11305 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11308 tg3_frob_aux_power(tp, false);
11309 pci_set_power_state(tp->pdev, PCI_D3hot);
11312 if (tg3_flag(tp, PTP_CAPABLE)) {
11313 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11315 if (IS_ERR(tp->ptp_clock))
11316 tp->ptp_clock = NULL;
11322 static int tg3_close(struct net_device *dev)
11324 struct tg3 *tp = netdev_priv(dev);
11330 /* Clear stats across close / open calls */
11331 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11332 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
11334 tg3_power_down(tp);
11336 tg3_carrier_off(tp);
11341 static inline u64 get_stat64(tg3_stat64_t *val)
11343 return ((u64)val->high << 32) | ((u64)val->low);
11346 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11348 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11350 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11351 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11352 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11355 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11356 tg3_writephy(tp, MII_TG3_TEST1,
11357 val | MII_TG3_TEST1_CRC_EN);
11358 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11362 tp->phy_crc_errors += val;
11364 return tp->phy_crc_errors;
11367 return get_stat64(&hw_stats->rx_fcs_errors);
11370 #define ESTAT_ADD(member) \
11371 estats->member = old_estats->member + \
11372 get_stat64(&hw_stats->member)
11374 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11376 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11377 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11379 ESTAT_ADD(rx_octets);
11380 ESTAT_ADD(rx_fragments);
11381 ESTAT_ADD(rx_ucast_packets);
11382 ESTAT_ADD(rx_mcast_packets);
11383 ESTAT_ADD(rx_bcast_packets);
11384 ESTAT_ADD(rx_fcs_errors);
11385 ESTAT_ADD(rx_align_errors);
11386 ESTAT_ADD(rx_xon_pause_rcvd);
11387 ESTAT_ADD(rx_xoff_pause_rcvd);
11388 ESTAT_ADD(rx_mac_ctrl_rcvd);
11389 ESTAT_ADD(rx_xoff_entered);
11390 ESTAT_ADD(rx_frame_too_long_errors);
11391 ESTAT_ADD(rx_jabbers);
11392 ESTAT_ADD(rx_undersize_packets);
11393 ESTAT_ADD(rx_in_length_errors);
11394 ESTAT_ADD(rx_out_length_errors);
11395 ESTAT_ADD(rx_64_or_less_octet_packets);
11396 ESTAT_ADD(rx_65_to_127_octet_packets);
11397 ESTAT_ADD(rx_128_to_255_octet_packets);
11398 ESTAT_ADD(rx_256_to_511_octet_packets);
11399 ESTAT_ADD(rx_512_to_1023_octet_packets);
11400 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11401 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11402 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11403 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11404 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11406 ESTAT_ADD(tx_octets);
11407 ESTAT_ADD(tx_collisions);
11408 ESTAT_ADD(tx_xon_sent);
11409 ESTAT_ADD(tx_xoff_sent);
11410 ESTAT_ADD(tx_flow_control);
11411 ESTAT_ADD(tx_mac_errors);
11412 ESTAT_ADD(tx_single_collisions);
11413 ESTAT_ADD(tx_mult_collisions);
11414 ESTAT_ADD(tx_deferred);
11415 ESTAT_ADD(tx_excessive_collisions);
11416 ESTAT_ADD(tx_late_collisions);
11417 ESTAT_ADD(tx_collide_2times);
11418 ESTAT_ADD(tx_collide_3times);
11419 ESTAT_ADD(tx_collide_4times);
11420 ESTAT_ADD(tx_collide_5times);
11421 ESTAT_ADD(tx_collide_6times);
11422 ESTAT_ADD(tx_collide_7times);
11423 ESTAT_ADD(tx_collide_8times);
11424 ESTAT_ADD(tx_collide_9times);
11425 ESTAT_ADD(tx_collide_10times);
11426 ESTAT_ADD(tx_collide_11times);
11427 ESTAT_ADD(tx_collide_12times);
11428 ESTAT_ADD(tx_collide_13times);
11429 ESTAT_ADD(tx_collide_14times);
11430 ESTAT_ADD(tx_collide_15times);
11431 ESTAT_ADD(tx_ucast_packets);
11432 ESTAT_ADD(tx_mcast_packets);
11433 ESTAT_ADD(tx_bcast_packets);
11434 ESTAT_ADD(tx_carrier_sense_errors);
11435 ESTAT_ADD(tx_discards);
11436 ESTAT_ADD(tx_errors);
11438 ESTAT_ADD(dma_writeq_full);
11439 ESTAT_ADD(dma_write_prioq_full);
11440 ESTAT_ADD(rxbds_empty);
11441 ESTAT_ADD(rx_discards);
11442 ESTAT_ADD(rx_errors);
11443 ESTAT_ADD(rx_threshold_hit);
11445 ESTAT_ADD(dma_readq_full);
11446 ESTAT_ADD(dma_read_prioq_full);
11447 ESTAT_ADD(tx_comp_queue_full);
11449 ESTAT_ADD(ring_set_send_prod_index);
11450 ESTAT_ADD(ring_status_update);
11451 ESTAT_ADD(nic_irqs);
11452 ESTAT_ADD(nic_avoided_irqs);
11453 ESTAT_ADD(nic_tx_threshold_hit);
11455 ESTAT_ADD(mbuf_lwm_thresh_hit);
11458 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11460 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11461 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11463 stats->rx_packets = old_stats->rx_packets +
11464 get_stat64(&hw_stats->rx_ucast_packets) +
11465 get_stat64(&hw_stats->rx_mcast_packets) +
11466 get_stat64(&hw_stats->rx_bcast_packets);
11468 stats->tx_packets = old_stats->tx_packets +
11469 get_stat64(&hw_stats->tx_ucast_packets) +
11470 get_stat64(&hw_stats->tx_mcast_packets) +
11471 get_stat64(&hw_stats->tx_bcast_packets);
11473 stats->rx_bytes = old_stats->rx_bytes +
11474 get_stat64(&hw_stats->rx_octets);
11475 stats->tx_bytes = old_stats->tx_bytes +
11476 get_stat64(&hw_stats->tx_octets);
11478 stats->rx_errors = old_stats->rx_errors +
11479 get_stat64(&hw_stats->rx_errors);
11480 stats->tx_errors = old_stats->tx_errors +
11481 get_stat64(&hw_stats->tx_errors) +
11482 get_stat64(&hw_stats->tx_mac_errors) +
11483 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11484 get_stat64(&hw_stats->tx_discards);
11486 stats->multicast = old_stats->multicast +
11487 get_stat64(&hw_stats->rx_mcast_packets);
11488 stats->collisions = old_stats->collisions +
11489 get_stat64(&hw_stats->tx_collisions);
11491 stats->rx_length_errors = old_stats->rx_length_errors +
11492 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11493 get_stat64(&hw_stats->rx_undersize_packets);
11495 stats->rx_over_errors = old_stats->rx_over_errors +
11496 get_stat64(&hw_stats->rxbds_empty);
11497 stats->rx_frame_errors = old_stats->rx_frame_errors +
11498 get_stat64(&hw_stats->rx_align_errors);
11499 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11500 get_stat64(&hw_stats->tx_discards);
11501 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11502 get_stat64(&hw_stats->tx_carrier_sense_errors);
11504 stats->rx_crc_errors = old_stats->rx_crc_errors +
11505 tg3_calc_crc_errors(tp);
11507 stats->rx_missed_errors = old_stats->rx_missed_errors +
11508 get_stat64(&hw_stats->rx_discards);
11510 stats->rx_dropped = tp->rx_dropped;
11511 stats->tx_dropped = tp->tx_dropped;
11514 static int tg3_get_regs_len(struct net_device *dev)
11516 return TG3_REG_BLK_SIZE;
11519 static void tg3_get_regs(struct net_device *dev,
11520 struct ethtool_regs *regs, void *_p)
11522 struct tg3 *tp = netdev_priv(dev);
11526 memset(_p, 0, TG3_REG_BLK_SIZE);
11528 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11531 tg3_full_lock(tp, 0);
11533 tg3_dump_legacy_regs(tp, (u32 *)_p);
11535 tg3_full_unlock(tp);
11538 static int tg3_get_eeprom_len(struct net_device *dev)
11540 struct tg3 *tp = netdev_priv(dev);
11542 return tp->nvram_size;
11545 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11547 struct tg3 *tp = netdev_priv(dev);
11550 u32 i, offset, len, b_offset, b_count;
11553 if (tg3_flag(tp, NO_NVRAM))
11556 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11559 offset = eeprom->offset;
11563 eeprom->magic = TG3_EEPROM_MAGIC;
11566 /* adjustments to start on required 4 byte boundary */
11567 b_offset = offset & 3;
11568 b_count = 4 - b_offset;
11569 if (b_count > len) {
11570 /* i.e. offset=1 len=2 */
11573 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
11576 memcpy(data, ((char *)&val) + b_offset, b_count);
11579 eeprom->len += b_count;
11582 /* read bytes up to the last 4 byte boundary */
11583 pd = &data[eeprom->len];
11584 for (i = 0; i < (len - (len & 3)); i += 4) {
11585 ret = tg3_nvram_read_be32(tp, offset + i, &val);
11590 memcpy(pd + i, &val, 4);
11595 /* read last bytes not ending on 4 byte boundary */
11596 pd = &data[eeprom->len];
11598 b_offset = offset + len - b_count;
11599 ret = tg3_nvram_read_be32(tp, b_offset, &val);
11602 memcpy(pd, &val, b_count);
11603 eeprom->len += b_count;
11608 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11610 struct tg3 *tp = netdev_priv(dev);
11612 u32 offset, len, b_offset, odd_len;
11616 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11619 if (tg3_flag(tp, NO_NVRAM) ||
11620 eeprom->magic != TG3_EEPROM_MAGIC)
11623 offset = eeprom->offset;
11626 if ((b_offset = (offset & 3))) {
11627 /* adjustments to start on required 4 byte boundary */
11628 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
11639 /* adjustments to end on required 4 byte boundary */
11641 len = (len + 3) & ~3;
11642 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
11648 if (b_offset || odd_len) {
11649 buf = kmalloc(len, GFP_KERNEL);
11653 memcpy(buf, &start, 4);
11655 memcpy(buf+len-4, &end, 4);
11656 memcpy(buf + b_offset, data, eeprom->len);
11659 ret = tg3_nvram_write_block(tp, offset, len, buf);
11667 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11669 struct tg3 *tp = netdev_priv(dev);
11671 if (tg3_flag(tp, USE_PHYLIB)) {
11672 struct phy_device *phydev;
11673 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11675 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11676 return phy_ethtool_gset(phydev, cmd);
11679 cmd->supported = (SUPPORTED_Autoneg);
11681 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
11682 cmd->supported |= (SUPPORTED_1000baseT_Half |
11683 SUPPORTED_1000baseT_Full);
11685 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
11686 cmd->supported |= (SUPPORTED_100baseT_Half |
11687 SUPPORTED_100baseT_Full |
11688 SUPPORTED_10baseT_Half |
11689 SUPPORTED_10baseT_Full |
11691 cmd->port = PORT_TP;
11693 cmd->supported |= SUPPORTED_FIBRE;
11694 cmd->port = PORT_FIBRE;
11697 cmd->advertising = tp->link_config.advertising;
11698 if (tg3_flag(tp, PAUSE_AUTONEG)) {
11699 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
11700 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11701 cmd->advertising |= ADVERTISED_Pause;
11703 cmd->advertising |= ADVERTISED_Pause |
11704 ADVERTISED_Asym_Pause;
11706 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11707 cmd->advertising |= ADVERTISED_Asym_Pause;
11710 if (netif_running(dev) && tp->link_up) {
11711 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
11712 cmd->duplex = tp->link_config.active_duplex;
11713 cmd->lp_advertising = tp->link_config.rmt_adv;
11714 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
11715 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
11716 cmd->eth_tp_mdix = ETH_TP_MDI_X;
11718 cmd->eth_tp_mdix = ETH_TP_MDI;
11721 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
11722 cmd->duplex = DUPLEX_UNKNOWN;
11723 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
11725 cmd->phy_address = tp->phy_addr;
11726 cmd->transceiver = XCVR_INTERNAL;
11727 cmd->autoneg = tp->link_config.autoneg;
11733 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11735 struct tg3 *tp = netdev_priv(dev);
11736 u32 speed = ethtool_cmd_speed(cmd);
11738 if (tg3_flag(tp, USE_PHYLIB)) {
11739 struct phy_device *phydev;
11740 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11742 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11743 return phy_ethtool_sset(phydev, cmd);
11746 if (cmd->autoneg != AUTONEG_ENABLE &&
11747 cmd->autoneg != AUTONEG_DISABLE)
11750 if (cmd->autoneg == AUTONEG_DISABLE &&
11751 cmd->duplex != DUPLEX_FULL &&
11752 cmd->duplex != DUPLEX_HALF)
11755 if (cmd->autoneg == AUTONEG_ENABLE) {
11756 u32 mask = ADVERTISED_Autoneg |
11758 ADVERTISED_Asym_Pause;
11760 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
11761 mask |= ADVERTISED_1000baseT_Half |
11762 ADVERTISED_1000baseT_Full;
11764 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
11765 mask |= ADVERTISED_100baseT_Half |
11766 ADVERTISED_100baseT_Full |
11767 ADVERTISED_10baseT_Half |
11768 ADVERTISED_10baseT_Full |
11771 mask |= ADVERTISED_FIBRE;
11773 if (cmd->advertising & ~mask)
11776 mask &= (ADVERTISED_1000baseT_Half |
11777 ADVERTISED_1000baseT_Full |
11778 ADVERTISED_100baseT_Half |
11779 ADVERTISED_100baseT_Full |
11780 ADVERTISED_10baseT_Half |
11781 ADVERTISED_10baseT_Full);
11783 cmd->advertising &= mask;
11785 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
11786 if (speed != SPEED_1000)
11789 if (cmd->duplex != DUPLEX_FULL)
11792 if (speed != SPEED_100 &&
11798 tg3_full_lock(tp, 0);
11800 tp->link_config.autoneg = cmd->autoneg;
11801 if (cmd->autoneg == AUTONEG_ENABLE) {
11802 tp->link_config.advertising = (cmd->advertising |
11803 ADVERTISED_Autoneg);
11804 tp->link_config.speed = SPEED_UNKNOWN;
11805 tp->link_config.duplex = DUPLEX_UNKNOWN;
11807 tp->link_config.advertising = 0;
11808 tp->link_config.speed = speed;
11809 tp->link_config.duplex = cmd->duplex;
11812 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
11814 tg3_warn_mgmt_link_flap(tp);
11816 if (netif_running(dev))
11817 tg3_setup_phy(tp, 1);
11819 tg3_full_unlock(tp);
11824 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
11826 struct tg3 *tp = netdev_priv(dev);
11828 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
11829 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
11830 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
11831 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
11834 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
11836 struct tg3 *tp = netdev_priv(dev);
11838 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
11839 wol->supported = WAKE_MAGIC;
11841 wol->supported = 0;
11843 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
11844 wol->wolopts = WAKE_MAGIC;
11845 memset(&wol->sopass, 0, sizeof(wol->sopass));
11848 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
11850 struct tg3 *tp = netdev_priv(dev);
11851 struct device *dp = &tp->pdev->dev;
11853 if (wol->wolopts & ~WAKE_MAGIC)
11855 if ((wol->wolopts & WAKE_MAGIC) &&
11856 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
11859 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
11861 spin_lock_bh(&tp->lock);
11862 if (device_may_wakeup(dp))
11863 tg3_flag_set(tp, WOL_ENABLE);
11865 tg3_flag_clear(tp, WOL_ENABLE);
11866 spin_unlock_bh(&tp->lock);
11871 static u32 tg3_get_msglevel(struct net_device *dev)
11873 struct tg3 *tp = netdev_priv(dev);
11874 return tp->msg_enable;
11877 static void tg3_set_msglevel(struct net_device *dev, u32 value)
11879 struct tg3 *tp = netdev_priv(dev);
11880 tp->msg_enable = value;
11883 static int tg3_nway_reset(struct net_device *dev)
11885 struct tg3 *tp = netdev_priv(dev);
11888 if (!netif_running(dev))
11891 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11894 tg3_warn_mgmt_link_flap(tp);
11896 if (tg3_flag(tp, USE_PHYLIB)) {
11897 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11899 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
11903 spin_lock_bh(&tp->lock);
11905 tg3_readphy(tp, MII_BMCR, &bmcr);
11906 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
11907 ((bmcr & BMCR_ANENABLE) ||
11908 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
11909 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
11913 spin_unlock_bh(&tp->lock);
11919 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
11921 struct tg3 *tp = netdev_priv(dev);
11923 ering->rx_max_pending = tp->rx_std_ring_mask;
11924 if (tg3_flag(tp, JUMBO_RING_ENABLE))
11925 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
11927 ering->rx_jumbo_max_pending = 0;
11929 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
11931 ering->rx_pending = tp->rx_pending;
11932 if (tg3_flag(tp, JUMBO_RING_ENABLE))
11933 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
11935 ering->rx_jumbo_pending = 0;
11937 ering->tx_pending = tp->napi[0].tx_pending;
11940 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
11942 struct tg3 *tp = netdev_priv(dev);
11943 int i, irq_sync = 0, err = 0;
11945 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
11946 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
11947 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
11948 (ering->tx_pending <= MAX_SKB_FRAGS) ||
11949 (tg3_flag(tp, TSO_BUG) &&
11950 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
11953 if (netif_running(dev)) {
11955 tg3_netif_stop(tp);
11959 tg3_full_lock(tp, irq_sync);
11961 tp->rx_pending = ering->rx_pending;
11963 if (tg3_flag(tp, MAX_RXPEND_64) &&
11964 tp->rx_pending > 63)
11965 tp->rx_pending = 63;
11966 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
11968 for (i = 0; i < tp->irq_max; i++)
11969 tp->napi[i].tx_pending = ering->tx_pending;
11971 if (netif_running(dev)) {
11972 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11973 err = tg3_restart_hw(tp, 0);
11975 tg3_netif_start(tp);
11978 tg3_full_unlock(tp);
11980 if (irq_sync && !err)
11986 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
11988 struct tg3 *tp = netdev_priv(dev);
11990 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
11992 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
11993 epause->rx_pause = 1;
11995 epause->rx_pause = 0;
11997 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
11998 epause->tx_pause = 1;
12000 epause->tx_pause = 0;
12003 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12005 struct tg3 *tp = netdev_priv(dev);
12008 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12009 tg3_warn_mgmt_link_flap(tp);
12011 if (tg3_flag(tp, USE_PHYLIB)) {
12013 struct phy_device *phydev;
12015 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
12017 if (!(phydev->supported & SUPPORTED_Pause) ||
12018 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
12019 (epause->rx_pause != epause->tx_pause)))
12022 tp->link_config.flowctrl = 0;
12023 if (epause->rx_pause) {
12024 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12026 if (epause->tx_pause) {
12027 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12028 newadv = ADVERTISED_Pause;
12030 newadv = ADVERTISED_Pause |
12031 ADVERTISED_Asym_Pause;
12032 } else if (epause->tx_pause) {
12033 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12034 newadv = ADVERTISED_Asym_Pause;
12038 if (epause->autoneg)
12039 tg3_flag_set(tp, PAUSE_AUTONEG);
12041 tg3_flag_clear(tp, PAUSE_AUTONEG);
12043 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12044 u32 oldadv = phydev->advertising &
12045 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12046 if (oldadv != newadv) {
12047 phydev->advertising &=
12048 ~(ADVERTISED_Pause |
12049 ADVERTISED_Asym_Pause);
12050 phydev->advertising |= newadv;
12051 if (phydev->autoneg) {
12053 * Always renegotiate the link to
12054 * inform our link partner of our
12055 * flow control settings, even if the
12056 * flow control is forced. Let
12057 * tg3_adjust_link() do the final
12058 * flow control setup.
12060 return phy_start_aneg(phydev);
12064 if (!epause->autoneg)
12065 tg3_setup_flow_control(tp, 0, 0);
12067 tp->link_config.advertising &=
12068 ~(ADVERTISED_Pause |
12069 ADVERTISED_Asym_Pause);
12070 tp->link_config.advertising |= newadv;
12075 if (netif_running(dev)) {
12076 tg3_netif_stop(tp);
12080 tg3_full_lock(tp, irq_sync);
12082 if (epause->autoneg)
12083 tg3_flag_set(tp, PAUSE_AUTONEG);
12085 tg3_flag_clear(tp, PAUSE_AUTONEG);
12086 if (epause->rx_pause)
12087 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12089 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12090 if (epause->tx_pause)
12091 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12093 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12095 if (netif_running(dev)) {
12096 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12097 err = tg3_restart_hw(tp, 0);
12099 tg3_netif_start(tp);
12102 tg3_full_unlock(tp);
12105 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12110 static int tg3_get_sset_count(struct net_device *dev, int sset)
12114 return TG3_NUM_TEST;
12116 return TG3_NUM_STATS;
12118 return -EOPNOTSUPP;
12122 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12123 u32 *rules __always_unused)
12125 struct tg3 *tp = netdev_priv(dev);
12127 if (!tg3_flag(tp, SUPPORT_MSIX))
12128 return -EOPNOTSUPP;
12130 switch (info->cmd) {
12131 case ETHTOOL_GRXRINGS:
12132 if (netif_running(tp->dev))
12133 info->data = tp->rxq_cnt;
12135 info->data = num_online_cpus();
12136 if (info->data > TG3_RSS_MAX_NUM_QS)
12137 info->data = TG3_RSS_MAX_NUM_QS;
12140 /* The first interrupt vector only
12141 * handles link interrupts.
12147 return -EOPNOTSUPP;
12151 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12154 struct tg3 *tp = netdev_priv(dev);
12156 if (tg3_flag(tp, SUPPORT_MSIX))
12157 size = TG3_RSS_INDIR_TBL_SIZE;
12162 static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
12164 struct tg3 *tp = netdev_priv(dev);
12167 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12168 indir[i] = tp->rss_ind_tbl[i];
12173 static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
12175 struct tg3 *tp = netdev_priv(dev);
12178 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12179 tp->rss_ind_tbl[i] = indir[i];
12181 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12184 /* It is legal to write the indirection
12185 * table while the device is running.
12187 tg3_full_lock(tp, 0);
12188 tg3_rss_write_indir_tbl(tp);
12189 tg3_full_unlock(tp);
12194 static void tg3_get_channels(struct net_device *dev,
12195 struct ethtool_channels *channel)
12197 struct tg3 *tp = netdev_priv(dev);
12198 u32 deflt_qs = netif_get_num_default_rss_queues();
12200 channel->max_rx = tp->rxq_max;
12201 channel->max_tx = tp->txq_max;
12203 if (netif_running(dev)) {
12204 channel->rx_count = tp->rxq_cnt;
12205 channel->tx_count = tp->txq_cnt;
12208 channel->rx_count = tp->rxq_req;
12210 channel->rx_count = min(deflt_qs, tp->rxq_max);
12213 channel->tx_count = tp->txq_req;
12215 channel->tx_count = min(deflt_qs, tp->txq_max);
12219 static int tg3_set_channels(struct net_device *dev,
12220 struct ethtool_channels *channel)
12222 struct tg3 *tp = netdev_priv(dev);
12224 if (!tg3_flag(tp, SUPPORT_MSIX))
12225 return -EOPNOTSUPP;
12227 if (channel->rx_count > tp->rxq_max ||
12228 channel->tx_count > tp->txq_max)
12231 tp->rxq_req = channel->rx_count;
12232 tp->txq_req = channel->tx_count;
12234 if (!netif_running(dev))
12239 tg3_carrier_off(tp);
12241 tg3_start(tp, true, false, false);
12246 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
12248 switch (stringset) {
12250 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
12253 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
12256 WARN_ON(1); /* we need a WARN() */
12261 static int tg3_set_phys_id(struct net_device *dev,
12262 enum ethtool_phys_id_state state)
12264 struct tg3 *tp = netdev_priv(dev);
12266 if (!netif_running(tp->dev))
12270 case ETHTOOL_ID_ACTIVE:
12271 return 1; /* cycle on/off once per second */
12273 case ETHTOOL_ID_ON:
12274 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12275 LED_CTRL_1000MBPS_ON |
12276 LED_CTRL_100MBPS_ON |
12277 LED_CTRL_10MBPS_ON |
12278 LED_CTRL_TRAFFIC_OVERRIDE |
12279 LED_CTRL_TRAFFIC_BLINK |
12280 LED_CTRL_TRAFFIC_LED);
12283 case ETHTOOL_ID_OFF:
12284 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12285 LED_CTRL_TRAFFIC_OVERRIDE);
12288 case ETHTOOL_ID_INACTIVE:
12289 tw32(MAC_LED_CTRL, tp->led_ctrl);
12296 static void tg3_get_ethtool_stats(struct net_device *dev,
12297 struct ethtool_stats *estats, u64 *tmp_stats)
12299 struct tg3 *tp = netdev_priv(dev);
12302 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12304 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
12307 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
12311 u32 offset = 0, len = 0;
12314 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12317 if (magic == TG3_EEPROM_MAGIC) {
12318 for (offset = TG3_NVM_DIR_START;
12319 offset < TG3_NVM_DIR_END;
12320 offset += TG3_NVM_DIRENT_SIZE) {
12321 if (tg3_nvram_read(tp, offset, &val))
12324 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12325 TG3_NVM_DIRTYPE_EXTVPD)
12329 if (offset != TG3_NVM_DIR_END) {
12330 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12331 if (tg3_nvram_read(tp, offset + 4, &offset))
12334 offset = tg3_nvram_logical_addr(tp, offset);
12338 if (!offset || !len) {
12339 offset = TG3_NVM_VPD_OFF;
12340 len = TG3_NVM_VPD_LEN;
12343 buf = kmalloc(len, GFP_KERNEL);
12347 if (magic == TG3_EEPROM_MAGIC) {
12348 for (i = 0; i < len; i += 4) {
12349 /* The data is in little-endian format in NVRAM.
12350 * Use the big-endian read routines to preserve
12351 * the byte order as it exists in NVRAM.
12353 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12359 unsigned int pos = 0;
12361 ptr = (u8 *)&buf[0];
12362 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12363 cnt = pci_read_vpd(tp->pdev, pos,
12365 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12383 #define NVRAM_TEST_SIZE 0x100
12384 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12385 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12386 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12387 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12388 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12389 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12390 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12391 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12393 static int tg3_test_nvram(struct tg3 *tp)
12395 u32 csum, magic, len;
12397 int i, j, k, err = 0, size;
12399 if (tg3_flag(tp, NO_NVRAM))
12402 if (tg3_nvram_read(tp, 0, &magic) != 0)
12405 if (magic == TG3_EEPROM_MAGIC)
12406 size = NVRAM_TEST_SIZE;
12407 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
12408 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12409 TG3_EEPROM_SB_FORMAT_1) {
12410 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12411 case TG3_EEPROM_SB_REVISION_0:
12412 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12414 case TG3_EEPROM_SB_REVISION_2:
12415 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12417 case TG3_EEPROM_SB_REVISION_3:
12418 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12420 case TG3_EEPROM_SB_REVISION_4:
12421 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12423 case TG3_EEPROM_SB_REVISION_5:
12424 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12426 case TG3_EEPROM_SB_REVISION_6:
12427 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12434 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12435 size = NVRAM_SELFBOOT_HW_SIZE;
12439 buf = kmalloc(size, GFP_KERNEL);
12444 for (i = 0, j = 0; i < size; i += 4, j++) {
12445 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12452 /* Selfboot format */
12453 magic = be32_to_cpu(buf[0]);
12454 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
12455 TG3_EEPROM_MAGIC_FW) {
12456 u8 *buf8 = (u8 *) buf, csum8 = 0;
12458 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
12459 TG3_EEPROM_SB_REVISION_2) {
12460 /* For rev 2, the csum doesn't include the MBA. */
12461 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12463 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12466 for (i = 0; i < size; i++)
12479 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
12480 TG3_EEPROM_MAGIC_HW) {
12481 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
12482 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
12483 u8 *buf8 = (u8 *) buf;
12485 /* Separate the parity bits and the data bytes. */
12486 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12487 if ((i == 0) || (i == 8)) {
12491 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12492 parity[k++] = buf8[i] & msk;
12494 } else if (i == 16) {
12498 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12499 parity[k++] = buf8[i] & msk;
12502 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12503 parity[k++] = buf8[i] & msk;
12506 data[j++] = buf8[i];
12510 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12511 u8 hw8 = hweight8(data[i]);
12513 if ((hw8 & 0x1) && parity[i])
12515 else if (!(hw8 & 0x1) && !parity[i])
12524 /* Bootstrap checksum at offset 0x10 */
12525 csum = calc_crc((unsigned char *) buf, 0x10);
12526 if (csum != le32_to_cpu(buf[0x10/4]))
12529 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12530 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
12531 if (csum != le32_to_cpu(buf[0xfc/4]))
12536 buf = tg3_vpd_readblock(tp, &len);
12540 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
12542 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12546 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
12549 i += PCI_VPD_LRDT_TAG_SIZE;
12550 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12551 PCI_VPD_RO_KEYWORD_CHKSUM);
12555 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12557 for (i = 0; i <= j; i++)
12558 csum8 += ((u8 *)buf)[i];
12572 #define TG3_SERDES_TIMEOUT_SEC 2
12573 #define TG3_COPPER_TIMEOUT_SEC 6
12575 static int tg3_test_link(struct tg3 *tp)
12579 if (!netif_running(tp->dev))
12582 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12583 max = TG3_SERDES_TIMEOUT_SEC;
12585 max = TG3_COPPER_TIMEOUT_SEC;
12587 for (i = 0; i < max; i++) {
12591 if (msleep_interruptible(1000))
12598 /* Only test the commonly used registers */
12599 static int tg3_test_registers(struct tg3 *tp)
12601 int i, is_5705, is_5750;
12602 u32 offset, read_mask, write_mask, val, save_val, read_val;
12606 #define TG3_FL_5705 0x1
12607 #define TG3_FL_NOT_5705 0x2
12608 #define TG3_FL_NOT_5788 0x4
12609 #define TG3_FL_NOT_5750 0x8
12613 /* MAC Control Registers */
12614 { MAC_MODE, TG3_FL_NOT_5705,
12615 0x00000000, 0x00ef6f8c },
12616 { MAC_MODE, TG3_FL_5705,
12617 0x00000000, 0x01ef6b8c },
12618 { MAC_STATUS, TG3_FL_NOT_5705,
12619 0x03800107, 0x00000000 },
12620 { MAC_STATUS, TG3_FL_5705,
12621 0x03800100, 0x00000000 },
12622 { MAC_ADDR_0_HIGH, 0x0000,
12623 0x00000000, 0x0000ffff },
12624 { MAC_ADDR_0_LOW, 0x0000,
12625 0x00000000, 0xffffffff },
12626 { MAC_RX_MTU_SIZE, 0x0000,
12627 0x00000000, 0x0000ffff },
12628 { MAC_TX_MODE, 0x0000,
12629 0x00000000, 0x00000070 },
12630 { MAC_TX_LENGTHS, 0x0000,
12631 0x00000000, 0x00003fff },
12632 { MAC_RX_MODE, TG3_FL_NOT_5705,
12633 0x00000000, 0x000007fc },
12634 { MAC_RX_MODE, TG3_FL_5705,
12635 0x00000000, 0x000007dc },
12636 { MAC_HASH_REG_0, 0x0000,
12637 0x00000000, 0xffffffff },
12638 { MAC_HASH_REG_1, 0x0000,
12639 0x00000000, 0xffffffff },
12640 { MAC_HASH_REG_2, 0x0000,
12641 0x00000000, 0xffffffff },
12642 { MAC_HASH_REG_3, 0x0000,
12643 0x00000000, 0xffffffff },
12645 /* Receive Data and Receive BD Initiator Control Registers. */
12646 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
12647 0x00000000, 0xffffffff },
12648 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
12649 0x00000000, 0xffffffff },
12650 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
12651 0x00000000, 0x00000003 },
12652 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
12653 0x00000000, 0xffffffff },
12654 { RCVDBDI_STD_BD+0, 0x0000,
12655 0x00000000, 0xffffffff },
12656 { RCVDBDI_STD_BD+4, 0x0000,
12657 0x00000000, 0xffffffff },
12658 { RCVDBDI_STD_BD+8, 0x0000,
12659 0x00000000, 0xffff0002 },
12660 { RCVDBDI_STD_BD+0xc, 0x0000,
12661 0x00000000, 0xffffffff },
12663 /* Receive BD Initiator Control Registers. */
12664 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
12665 0x00000000, 0xffffffff },
12666 { RCVBDI_STD_THRESH, TG3_FL_5705,
12667 0x00000000, 0x000003ff },
12668 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
12669 0x00000000, 0xffffffff },
12671 /* Host Coalescing Control Registers. */
12672 { HOSTCC_MODE, TG3_FL_NOT_5705,
12673 0x00000000, 0x00000004 },
12674 { HOSTCC_MODE, TG3_FL_5705,
12675 0x00000000, 0x000000f6 },
12676 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
12677 0x00000000, 0xffffffff },
12678 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
12679 0x00000000, 0x000003ff },
12680 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
12681 0x00000000, 0xffffffff },
12682 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
12683 0x00000000, 0x000003ff },
12684 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
12685 0x00000000, 0xffffffff },
12686 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12687 0x00000000, 0x000000ff },
12688 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
12689 0x00000000, 0xffffffff },
12690 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12691 0x00000000, 0x000000ff },
12692 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
12693 0x00000000, 0xffffffff },
12694 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
12695 0x00000000, 0xffffffff },
12696 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12697 0x00000000, 0xffffffff },
12698 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12699 0x00000000, 0x000000ff },
12700 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12701 0x00000000, 0xffffffff },
12702 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12703 0x00000000, 0x000000ff },
12704 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
12705 0x00000000, 0xffffffff },
12706 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
12707 0x00000000, 0xffffffff },
12708 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
12709 0x00000000, 0xffffffff },
12710 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
12711 0x00000000, 0xffffffff },
12712 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
12713 0x00000000, 0xffffffff },
12714 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
12715 0xffffffff, 0x00000000 },
12716 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
12717 0xffffffff, 0x00000000 },
12719 /* Buffer Manager Control Registers. */
12720 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
12721 0x00000000, 0x007fff80 },
12722 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
12723 0x00000000, 0x007fffff },
12724 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
12725 0x00000000, 0x0000003f },
12726 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
12727 0x00000000, 0x000001ff },
12728 { BUFMGR_MB_HIGH_WATER, 0x0000,
12729 0x00000000, 0x000001ff },
12730 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
12731 0xffffffff, 0x00000000 },
12732 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
12733 0xffffffff, 0x00000000 },
12735 /* Mailbox Registers */
12736 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
12737 0x00000000, 0x000001ff },
12738 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
12739 0x00000000, 0x000001ff },
12740 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
12741 0x00000000, 0x000007ff },
12742 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
12743 0x00000000, 0x000001ff },
12745 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
12748 is_5705 = is_5750 = 0;
12749 if (tg3_flag(tp, 5705_PLUS)) {
12751 if (tg3_flag(tp, 5750_PLUS))
12755 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
12756 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
12759 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
12762 if (tg3_flag(tp, IS_5788) &&
12763 (reg_tbl[i].flags & TG3_FL_NOT_5788))
12766 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
12769 offset = (u32) reg_tbl[i].offset;
12770 read_mask = reg_tbl[i].read_mask;
12771 write_mask = reg_tbl[i].write_mask;
12773 /* Save the original register content */
12774 save_val = tr32(offset);
12776 /* Determine the read-only value. */
12777 read_val = save_val & read_mask;
12779 /* Write zero to the register, then make sure the read-only bits
12780 * are not changed and the read/write bits are all zeros.
12784 val = tr32(offset);
12786 /* Test the read-only and read/write bits. */
12787 if (((val & read_mask) != read_val) || (val & write_mask))
12790 /* Write ones to all the bits defined by RdMask and WrMask, then
12791 * make sure the read-only bits are not changed and the
12792 * read/write bits are all ones.
12794 tw32(offset, read_mask | write_mask);
12796 val = tr32(offset);
12798 /* Test the read-only bits. */
12799 if ((val & read_mask) != read_val)
12802 /* Test the read/write bits. */
12803 if ((val & write_mask) != write_mask)
12806 tw32(offset, save_val);
12812 if (netif_msg_hw(tp))
12813 netdev_err(tp->dev,
12814 "Register test failed at offset %x\n", offset);
12815 tw32(offset, save_val);
12819 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
12821 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
12825 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
12826 for (j = 0; j < len; j += 4) {
12829 tg3_write_mem(tp, offset + j, test_pattern[i]);
12830 tg3_read_mem(tp, offset + j, &val);
12831 if (val != test_pattern[i])
12838 static int tg3_test_memory(struct tg3 *tp)
12840 static struct mem_entry {
12843 } mem_tbl_570x[] = {
12844 { 0x00000000, 0x00b50},
12845 { 0x00002000, 0x1c000},
12846 { 0xffffffff, 0x00000}
12847 }, mem_tbl_5705[] = {
12848 { 0x00000100, 0x0000c},
12849 { 0x00000200, 0x00008},
12850 { 0x00004000, 0x00800},
12851 { 0x00006000, 0x01000},
12852 { 0x00008000, 0x02000},
12853 { 0x00010000, 0x0e000},
12854 { 0xffffffff, 0x00000}
12855 }, mem_tbl_5755[] = {
12856 { 0x00000200, 0x00008},
12857 { 0x00004000, 0x00800},
12858 { 0x00006000, 0x00800},
12859 { 0x00008000, 0x02000},
12860 { 0x00010000, 0x0c000},
12861 { 0xffffffff, 0x00000}
12862 }, mem_tbl_5906[] = {
12863 { 0x00000200, 0x00008},
12864 { 0x00004000, 0x00400},
12865 { 0x00006000, 0x00400},
12866 { 0x00008000, 0x01000},
12867 { 0x00010000, 0x01000},
12868 { 0xffffffff, 0x00000}
12869 }, mem_tbl_5717[] = {
12870 { 0x00000200, 0x00008},
12871 { 0x00010000, 0x0a000},
12872 { 0x00020000, 0x13c00},
12873 { 0xffffffff, 0x00000}
12874 }, mem_tbl_57765[] = {
12875 { 0x00000200, 0x00008},
12876 { 0x00004000, 0x00800},
12877 { 0x00006000, 0x09800},
12878 { 0x00010000, 0x0a000},
12879 { 0xffffffff, 0x00000}
12881 struct mem_entry *mem_tbl;
12885 if (tg3_flag(tp, 5717_PLUS))
12886 mem_tbl = mem_tbl_5717;
12887 else if (tg3_flag(tp, 57765_CLASS) ||
12888 tg3_asic_rev(tp) == ASIC_REV_5762)
12889 mem_tbl = mem_tbl_57765;
12890 else if (tg3_flag(tp, 5755_PLUS))
12891 mem_tbl = mem_tbl_5755;
12892 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
12893 mem_tbl = mem_tbl_5906;
12894 else if (tg3_flag(tp, 5705_PLUS))
12895 mem_tbl = mem_tbl_5705;
12897 mem_tbl = mem_tbl_570x;
12899 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
12900 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
12908 #define TG3_TSO_MSS 500
12910 #define TG3_TSO_IP_HDR_LEN 20
12911 #define TG3_TSO_TCP_HDR_LEN 20
12912 #define TG3_TSO_TCP_OPT_LEN 12
12914 static const u8 tg3_tso_header[] = {
12916 0x45, 0x00, 0x00, 0x00,
12917 0x00, 0x00, 0x40, 0x00,
12918 0x40, 0x06, 0x00, 0x00,
12919 0x0a, 0x00, 0x00, 0x01,
12920 0x0a, 0x00, 0x00, 0x02,
12921 0x0d, 0x00, 0xe0, 0x00,
12922 0x00, 0x00, 0x01, 0x00,
12923 0x00, 0x00, 0x02, 0x00,
12924 0x80, 0x10, 0x10, 0x00,
12925 0x14, 0x09, 0x00, 0x00,
12926 0x01, 0x01, 0x08, 0x0a,
12927 0x11, 0x11, 0x11, 0x11,
12928 0x11, 0x11, 0x11, 0x11,
12931 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
12933 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
12934 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
12936 struct sk_buff *skb;
12937 u8 *tx_data, *rx_data;
12939 int num_pkts, tx_len, rx_len, i, err;
12940 struct tg3_rx_buffer_desc *desc;
12941 struct tg3_napi *tnapi, *rnapi;
12942 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
12944 tnapi = &tp->napi[0];
12945 rnapi = &tp->napi[0];
12946 if (tp->irq_cnt > 1) {
12947 if (tg3_flag(tp, ENABLE_RSS))
12948 rnapi = &tp->napi[1];
12949 if (tg3_flag(tp, ENABLE_TSS))
12950 tnapi = &tp->napi[1];
12952 coal_now = tnapi->coal_now | rnapi->coal_now;
12957 skb = netdev_alloc_skb(tp->dev, tx_len);
12961 tx_data = skb_put(skb, tx_len);
12962 memcpy(tx_data, tp->dev->dev_addr, 6);
12963 memset(tx_data + 6, 0x0, 8);
12965 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
12967 if (tso_loopback) {
12968 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
12970 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
12971 TG3_TSO_TCP_OPT_LEN;
12973 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
12974 sizeof(tg3_tso_header));
12977 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
12978 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
12980 /* Set the total length field in the IP header */
12981 iph->tot_len = htons((u16)(mss + hdr_len));
12983 base_flags = (TXD_FLAG_CPU_PRE_DMA |
12984 TXD_FLAG_CPU_POST_DMA);
12986 if (tg3_flag(tp, HW_TSO_1) ||
12987 tg3_flag(tp, HW_TSO_2) ||
12988 tg3_flag(tp, HW_TSO_3)) {
12990 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
12991 th = (struct tcphdr *)&tx_data[val];
12994 base_flags |= TXD_FLAG_TCPUDP_CSUM;
12996 if (tg3_flag(tp, HW_TSO_3)) {
12997 mss |= (hdr_len & 0xc) << 12;
12998 if (hdr_len & 0x10)
12999 base_flags |= 0x00000010;
13000 base_flags |= (hdr_len & 0x3e0) << 5;
13001 } else if (tg3_flag(tp, HW_TSO_2))
13002 mss |= hdr_len << 9;
13003 else if (tg3_flag(tp, HW_TSO_1) ||
13004 tg3_asic_rev(tp) == ASIC_REV_5705) {
13005 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13007 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13010 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13013 data_off = ETH_HLEN;
13015 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13016 tx_len > VLAN_ETH_FRAME_LEN)
13017 base_flags |= TXD_FLAG_JMB_PKT;
13020 for (i = data_off; i < tx_len; i++)
13021 tx_data[i] = (u8) (i & 0xff);
13023 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13024 if (pci_dma_mapping_error(tp->pdev, map)) {
13025 dev_kfree_skb(skb);
13029 val = tnapi->tx_prod;
13030 tnapi->tx_buffers[val].skb = skb;
13031 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13033 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13038 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
13040 budget = tg3_tx_avail(tnapi);
13041 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
13042 base_flags | TXD_FLAG_END, mss, 0)) {
13043 tnapi->tx_buffers[val].skb = NULL;
13044 dev_kfree_skb(skb);
13050 /* Sync BD data before updating mailbox */
13053 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13054 tr32_mailbox(tnapi->prodmbox);
13058 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13059 for (i = 0; i < 35; i++) {
13060 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13065 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13066 rx_idx = rnapi->hw_status->idx[0].rx_producer;
13067 if ((tx_idx == tnapi->tx_prod) &&
13068 (rx_idx == (rx_start_idx + num_pkts)))
13072 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
13073 dev_kfree_skb(skb);
13075 if (tx_idx != tnapi->tx_prod)
13078 if (rx_idx != rx_start_idx + num_pkts)
13082 while (rx_idx != rx_start_idx) {
13083 desc = &rnapi->rx_rcb[rx_start_idx++];
13084 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13085 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
13087 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13088 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13091 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13094 if (!tso_loopback) {
13095 if (rx_len != tx_len)
13098 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13099 if (opaque_key != RXD_OPAQUE_RING_STD)
13102 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13105 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13106 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
13107 >> RXD_TCPCSUM_SHIFT != 0xffff) {
13111 if (opaque_key == RXD_OPAQUE_RING_STD) {
13112 rx_data = tpr->rx_std_buffers[desc_idx].data;
13113 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13115 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
13116 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
13117 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13122 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13123 PCI_DMA_FROMDEVICE);
13125 rx_data += TG3_RX_OFFSET(tp);
13126 for (i = data_off; i < rx_len; i++, val++) {
13127 if (*(rx_data + i) != (u8) (val & 0xff))
13134 /* tg3_free_rings will unmap and free the rx_data */
13139 #define TG3_STD_LOOPBACK_FAILED 1
13140 #define TG3_JMB_LOOPBACK_FAILED 2
13141 #define TG3_TSO_LOOPBACK_FAILED 4
13142 #define TG3_LOOPBACK_FAILED \
13143 (TG3_STD_LOOPBACK_FAILED | \
13144 TG3_JMB_LOOPBACK_FAILED | \
13145 TG3_TSO_LOOPBACK_FAILED)
13147 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13151 u32 jmb_pkt_sz = 9000;
13154 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13156 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13157 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13159 if (!netif_running(tp->dev)) {
13160 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13161 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13163 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13167 err = tg3_reset_hw(tp, 1);
13169 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13170 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13172 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13176 if (tg3_flag(tp, ENABLE_RSS)) {
13179 /* Reroute all rx packets to the 1st queue */
13180 for (i = MAC_RSS_INDIR_TBL_0;
13181 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13185 /* HW errata - mac loopback fails in some cases on 5780.
13186 * Normal traffic and PHY loopback are not affected by
13187 * errata. Also, the MAC loopback test is deprecated for
13188 * all newer ASIC revisions.
13190 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13191 !tg3_flag(tp, CPMU_PRESENT)) {
13192 tg3_mac_loopback(tp, true);
13194 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13195 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13197 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13198 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13199 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13201 tg3_mac_loopback(tp, false);
13204 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13205 !tg3_flag(tp, USE_PHYLIB)) {
13208 tg3_phy_lpbk_set(tp, 0, false);
13210 /* Wait for link */
13211 for (i = 0; i < 100; i++) {
13212 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13217 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13218 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13219 if (tg3_flag(tp, TSO_CAPABLE) &&
13220 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13221 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
13222 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13223 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13224 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13227 tg3_phy_lpbk_set(tp, 0, true);
13229 /* All link indications report up, but the hardware
13230 * isn't really ready for about 20 msec. Double it
13235 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13236 data[TG3_EXT_LOOPB_TEST] |=
13237 TG3_STD_LOOPBACK_FAILED;
13238 if (tg3_flag(tp, TSO_CAPABLE) &&
13239 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13240 data[TG3_EXT_LOOPB_TEST] |=
13241 TG3_TSO_LOOPBACK_FAILED;
13242 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13243 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13244 data[TG3_EXT_LOOPB_TEST] |=
13245 TG3_JMB_LOOPBACK_FAILED;
13248 /* Re-enable gphy autopowerdown. */
13249 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13250 tg3_phy_toggle_apd(tp, true);
13253 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13254 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
13257 tp->phy_flags |= eee_cap;
13262 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13265 struct tg3 *tp = netdev_priv(dev);
13266 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
13268 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
13269 tg3_power_up(tp)) {
13270 etest->flags |= ETH_TEST_FL_FAILED;
13271 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13275 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13277 if (tg3_test_nvram(tp) != 0) {
13278 etest->flags |= ETH_TEST_FL_FAILED;
13279 data[TG3_NVRAM_TEST] = 1;
13281 if (!doextlpbk && tg3_test_link(tp)) {
13282 etest->flags |= ETH_TEST_FL_FAILED;
13283 data[TG3_LINK_TEST] = 1;
13285 if (etest->flags & ETH_TEST_FL_OFFLINE) {
13286 int err, err2 = 0, irq_sync = 0;
13288 if (netif_running(dev)) {
13290 tg3_netif_stop(tp);
13294 tg3_full_lock(tp, irq_sync);
13295 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13296 err = tg3_nvram_lock(tp);
13297 tg3_halt_cpu(tp, RX_CPU_BASE);
13298 if (!tg3_flag(tp, 5705_PLUS))
13299 tg3_halt_cpu(tp, TX_CPU_BASE);
13301 tg3_nvram_unlock(tp);
13303 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13306 if (tg3_test_registers(tp) != 0) {
13307 etest->flags |= ETH_TEST_FL_FAILED;
13308 data[TG3_REGISTER_TEST] = 1;
13311 if (tg3_test_memory(tp) != 0) {
13312 etest->flags |= ETH_TEST_FL_FAILED;
13313 data[TG3_MEMORY_TEST] = 1;
13317 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13319 if (tg3_test_loopback(tp, data, doextlpbk))
13320 etest->flags |= ETH_TEST_FL_FAILED;
13322 tg3_full_unlock(tp);
13324 if (tg3_test_interrupt(tp) != 0) {
13325 etest->flags |= ETH_TEST_FL_FAILED;
13326 data[TG3_INTERRUPT_TEST] = 1;
13329 tg3_full_lock(tp, 0);
13331 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13332 if (netif_running(dev)) {
13333 tg3_flag_set(tp, INIT_COMPLETE);
13334 err2 = tg3_restart_hw(tp, 1);
13336 tg3_netif_start(tp);
13339 tg3_full_unlock(tp);
13341 if (irq_sync && !err2)
13344 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13345 tg3_power_down(tp);
13349 static int tg3_hwtstamp_ioctl(struct net_device *dev,
13350 struct ifreq *ifr, int cmd)
13352 struct tg3 *tp = netdev_priv(dev);
13353 struct hwtstamp_config stmpconf;
13355 if (!tg3_flag(tp, PTP_CAPABLE))
13358 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13361 if (stmpconf.flags)
13364 switch (stmpconf.tx_type) {
13365 case HWTSTAMP_TX_ON:
13366 tg3_flag_set(tp, TX_TSTAMP_EN);
13368 case HWTSTAMP_TX_OFF:
13369 tg3_flag_clear(tp, TX_TSTAMP_EN);
13375 switch (stmpconf.rx_filter) {
13376 case HWTSTAMP_FILTER_NONE:
13379 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13380 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13381 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13383 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13384 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13385 TG3_RX_PTP_CTL_SYNC_EVNT;
13387 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13388 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13389 TG3_RX_PTP_CTL_DELAY_REQ;
13391 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13392 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13393 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13395 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13396 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13397 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13399 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13400 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13401 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13403 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13404 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13405 TG3_RX_PTP_CTL_SYNC_EVNT;
13407 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13408 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13409 TG3_RX_PTP_CTL_SYNC_EVNT;
13411 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13412 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13413 TG3_RX_PTP_CTL_SYNC_EVNT;
13415 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13416 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13417 TG3_RX_PTP_CTL_DELAY_REQ;
13419 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13420 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13421 TG3_RX_PTP_CTL_DELAY_REQ;
13423 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13424 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13425 TG3_RX_PTP_CTL_DELAY_REQ;
13431 if (netif_running(dev) && tp->rxptpctl)
13432 tw32(TG3_RX_PTP_CTL,
13433 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13435 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13439 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13441 struct mii_ioctl_data *data = if_mii(ifr);
13442 struct tg3 *tp = netdev_priv(dev);
13445 if (tg3_flag(tp, USE_PHYLIB)) {
13446 struct phy_device *phydev;
13447 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
13449 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
13450 return phy_mii_ioctl(phydev, ifr, cmd);
13455 data->phy_id = tp->phy_addr;
13458 case SIOCGMIIREG: {
13461 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13462 break; /* We have no PHY */
13464 if (!netif_running(dev))
13467 spin_lock_bh(&tp->lock);
13468 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13469 data->reg_num & 0x1f, &mii_regval);
13470 spin_unlock_bh(&tp->lock);
13472 data->val_out = mii_regval;
13478 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13479 break; /* We have no PHY */
13481 if (!netif_running(dev))
13484 spin_lock_bh(&tp->lock);
13485 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13486 data->reg_num & 0x1f, data->val_in);
13487 spin_unlock_bh(&tp->lock);
13491 case SIOCSHWTSTAMP:
13492 return tg3_hwtstamp_ioctl(dev, ifr, cmd);
13498 return -EOPNOTSUPP;
13501 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13503 struct tg3 *tp = netdev_priv(dev);
13505 memcpy(ec, &tp->coal, sizeof(*ec));
13509 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13511 struct tg3 *tp = netdev_priv(dev);
13512 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13513 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13515 if (!tg3_flag(tp, 5705_PLUS)) {
13516 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13517 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13518 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13519 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13522 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13523 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13524 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13525 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13526 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13527 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13528 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13529 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13530 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13531 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13534 /* No rx interrupts will be generated if both are zero */
13535 if ((ec->rx_coalesce_usecs == 0) &&
13536 (ec->rx_max_coalesced_frames == 0))
13539 /* No tx interrupts will be generated if both are zero */
13540 if ((ec->tx_coalesce_usecs == 0) &&
13541 (ec->tx_max_coalesced_frames == 0))
13544 /* Only copy relevant parameters, ignore all others. */
13545 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13546 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13547 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13548 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13549 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13550 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13551 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13552 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13553 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13555 if (netif_running(dev)) {
13556 tg3_full_lock(tp, 0);
13557 __tg3_set_coalesce(tp, &tp->coal);
13558 tg3_full_unlock(tp);
13563 static const struct ethtool_ops tg3_ethtool_ops = {
13564 .get_settings = tg3_get_settings,
13565 .set_settings = tg3_set_settings,
13566 .get_drvinfo = tg3_get_drvinfo,
13567 .get_regs_len = tg3_get_regs_len,
13568 .get_regs = tg3_get_regs,
13569 .get_wol = tg3_get_wol,
13570 .set_wol = tg3_set_wol,
13571 .get_msglevel = tg3_get_msglevel,
13572 .set_msglevel = tg3_set_msglevel,
13573 .nway_reset = tg3_nway_reset,
13574 .get_link = ethtool_op_get_link,
13575 .get_eeprom_len = tg3_get_eeprom_len,
13576 .get_eeprom = tg3_get_eeprom,
13577 .set_eeprom = tg3_set_eeprom,
13578 .get_ringparam = tg3_get_ringparam,
13579 .set_ringparam = tg3_set_ringparam,
13580 .get_pauseparam = tg3_get_pauseparam,
13581 .set_pauseparam = tg3_set_pauseparam,
13582 .self_test = tg3_self_test,
13583 .get_strings = tg3_get_strings,
13584 .set_phys_id = tg3_set_phys_id,
13585 .get_ethtool_stats = tg3_get_ethtool_stats,
13586 .get_coalesce = tg3_get_coalesce,
13587 .set_coalesce = tg3_set_coalesce,
13588 .get_sset_count = tg3_get_sset_count,
13589 .get_rxnfc = tg3_get_rxnfc,
13590 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
13591 .get_rxfh_indir = tg3_get_rxfh_indir,
13592 .set_rxfh_indir = tg3_set_rxfh_indir,
13593 .get_channels = tg3_get_channels,
13594 .set_channels = tg3_set_channels,
13595 .get_ts_info = tg3_get_ts_info,
13598 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
13599 struct rtnl_link_stats64 *stats)
13601 struct tg3 *tp = netdev_priv(dev);
13603 spin_lock_bh(&tp->lock);
13604 if (!tp->hw_stats) {
13605 spin_unlock_bh(&tp->lock);
13606 return &tp->net_stats_prev;
13609 tg3_get_nstats(tp, stats);
13610 spin_unlock_bh(&tp->lock);
13615 static void tg3_set_rx_mode(struct net_device *dev)
13617 struct tg3 *tp = netdev_priv(dev);
13619 if (!netif_running(dev))
13622 tg3_full_lock(tp, 0);
13623 __tg3_set_rx_mode(dev);
13624 tg3_full_unlock(tp);
13627 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
13630 dev->mtu = new_mtu;
13632 if (new_mtu > ETH_DATA_LEN) {
13633 if (tg3_flag(tp, 5780_CLASS)) {
13634 netdev_update_features(dev);
13635 tg3_flag_clear(tp, TSO_CAPABLE);
13637 tg3_flag_set(tp, JUMBO_RING_ENABLE);
13640 if (tg3_flag(tp, 5780_CLASS)) {
13641 tg3_flag_set(tp, TSO_CAPABLE);
13642 netdev_update_features(dev);
13644 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
13648 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
13650 struct tg3 *tp = netdev_priv(dev);
13651 int err, reset_phy = 0;
13653 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
13656 if (!netif_running(dev)) {
13657 /* We'll just catch it later when the
13660 tg3_set_mtu(dev, tp, new_mtu);
13666 tg3_netif_stop(tp);
13668 tg3_full_lock(tp, 1);
13670 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13672 tg3_set_mtu(dev, tp, new_mtu);
13674 /* Reset PHY, otherwise the read DMA engine will be in a mode that
13675 * breaks all requests to 256 bytes.
13677 if (tg3_asic_rev(tp) == ASIC_REV_57766)
13680 err = tg3_restart_hw(tp, reset_phy);
13683 tg3_netif_start(tp);
13685 tg3_full_unlock(tp);
13693 static const struct net_device_ops tg3_netdev_ops = {
13694 .ndo_open = tg3_open,
13695 .ndo_stop = tg3_close,
13696 .ndo_start_xmit = tg3_start_xmit,
13697 .ndo_get_stats64 = tg3_get_stats64,
13698 .ndo_validate_addr = eth_validate_addr,
13699 .ndo_set_rx_mode = tg3_set_rx_mode,
13700 .ndo_set_mac_address = tg3_set_mac_addr,
13701 .ndo_do_ioctl = tg3_ioctl,
13702 .ndo_tx_timeout = tg3_tx_timeout,
13703 .ndo_change_mtu = tg3_change_mtu,
13704 .ndo_fix_features = tg3_fix_features,
13705 .ndo_set_features = tg3_set_features,
13706 #ifdef CONFIG_NET_POLL_CONTROLLER
13707 .ndo_poll_controller = tg3_poll_controller,
13711 static void tg3_get_eeprom_size(struct tg3 *tp)
13713 u32 cursize, val, magic;
13715 tp->nvram_size = EEPROM_CHIP_SIZE;
13717 if (tg3_nvram_read(tp, 0, &magic) != 0)
13720 if ((magic != TG3_EEPROM_MAGIC) &&
13721 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
13722 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
13726 * Size the chip by reading offsets at increasing powers of two.
13727 * When we encounter our validation signature, we know the addressing
13728 * has wrapped around, and thus have our chip size.
13732 while (cursize < tp->nvram_size) {
13733 if (tg3_nvram_read(tp, cursize, &val) != 0)
13742 tp->nvram_size = cursize;
13745 static void tg3_get_nvram_size(struct tg3 *tp)
13749 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
13752 /* Selfboot format */
13753 if (val != TG3_EEPROM_MAGIC) {
13754 tg3_get_eeprom_size(tp);
13758 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
13760 /* This is confusing. We want to operate on the
13761 * 16-bit value at offset 0xf2. The tg3_nvram_read()
13762 * call will read from NVRAM and byteswap the data
13763 * according to the byteswapping settings for all
13764 * other register accesses. This ensures the data we
13765 * want will always reside in the lower 16-bits.
13766 * However, the data in NVRAM is in LE format, which
13767 * means the data from the NVRAM read will always be
13768 * opposite the endianness of the CPU. The 16-bit
13769 * byteswap then brings the data to CPU endianness.
13771 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
13775 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13778 static void tg3_get_nvram_info(struct tg3 *tp)
13782 nvcfg1 = tr32(NVRAM_CFG1);
13783 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
13784 tg3_flag_set(tp, FLASH);
13786 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13787 tw32(NVRAM_CFG1, nvcfg1);
13790 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
13791 tg3_flag(tp, 5780_CLASS)) {
13792 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
13793 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
13794 tp->nvram_jedecnum = JEDEC_ATMEL;
13795 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
13796 tg3_flag_set(tp, NVRAM_BUFFERED);
13798 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
13799 tp->nvram_jedecnum = JEDEC_ATMEL;
13800 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
13802 case FLASH_VENDOR_ATMEL_EEPROM:
13803 tp->nvram_jedecnum = JEDEC_ATMEL;
13804 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13805 tg3_flag_set(tp, NVRAM_BUFFERED);
13807 case FLASH_VENDOR_ST:
13808 tp->nvram_jedecnum = JEDEC_ST;
13809 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
13810 tg3_flag_set(tp, NVRAM_BUFFERED);
13812 case FLASH_VENDOR_SAIFUN:
13813 tp->nvram_jedecnum = JEDEC_SAIFUN;
13814 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
13816 case FLASH_VENDOR_SST_SMALL:
13817 case FLASH_VENDOR_SST_LARGE:
13818 tp->nvram_jedecnum = JEDEC_SST;
13819 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
13823 tp->nvram_jedecnum = JEDEC_ATMEL;
13824 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
13825 tg3_flag_set(tp, NVRAM_BUFFERED);
13829 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
13831 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
13832 case FLASH_5752PAGE_SIZE_256:
13833 tp->nvram_pagesize = 256;
13835 case FLASH_5752PAGE_SIZE_512:
13836 tp->nvram_pagesize = 512;
13838 case FLASH_5752PAGE_SIZE_1K:
13839 tp->nvram_pagesize = 1024;
13841 case FLASH_5752PAGE_SIZE_2K:
13842 tp->nvram_pagesize = 2048;
13844 case FLASH_5752PAGE_SIZE_4K:
13845 tp->nvram_pagesize = 4096;
13847 case FLASH_5752PAGE_SIZE_264:
13848 tp->nvram_pagesize = 264;
13850 case FLASH_5752PAGE_SIZE_528:
13851 tp->nvram_pagesize = 528;
13856 static void tg3_get_5752_nvram_info(struct tg3 *tp)
13860 nvcfg1 = tr32(NVRAM_CFG1);
13862 /* NVRAM protection for TPM */
13863 if (nvcfg1 & (1 << 27))
13864 tg3_flag_set(tp, PROTECTED_NVRAM);
13866 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13867 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
13868 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
13869 tp->nvram_jedecnum = JEDEC_ATMEL;
13870 tg3_flag_set(tp, NVRAM_BUFFERED);
13872 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
13873 tp->nvram_jedecnum = JEDEC_ATMEL;
13874 tg3_flag_set(tp, NVRAM_BUFFERED);
13875 tg3_flag_set(tp, FLASH);
13877 case FLASH_5752VENDOR_ST_M45PE10:
13878 case FLASH_5752VENDOR_ST_M45PE20:
13879 case FLASH_5752VENDOR_ST_M45PE40:
13880 tp->nvram_jedecnum = JEDEC_ST;
13881 tg3_flag_set(tp, NVRAM_BUFFERED);
13882 tg3_flag_set(tp, FLASH);
13886 if (tg3_flag(tp, FLASH)) {
13887 tg3_nvram_get_pagesize(tp, nvcfg1);
13889 /* For eeprom, set pagesize to maximum eeprom size */
13890 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13892 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13893 tw32(NVRAM_CFG1, nvcfg1);
13897 static void tg3_get_5755_nvram_info(struct tg3 *tp)
13899 u32 nvcfg1, protect = 0;
13901 nvcfg1 = tr32(NVRAM_CFG1);
13903 /* NVRAM protection for TPM */
13904 if (nvcfg1 & (1 << 27)) {
13905 tg3_flag_set(tp, PROTECTED_NVRAM);
13909 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
13911 case FLASH_5755VENDOR_ATMEL_FLASH_1:
13912 case FLASH_5755VENDOR_ATMEL_FLASH_2:
13913 case FLASH_5755VENDOR_ATMEL_FLASH_3:
13914 case FLASH_5755VENDOR_ATMEL_FLASH_5:
13915 tp->nvram_jedecnum = JEDEC_ATMEL;
13916 tg3_flag_set(tp, NVRAM_BUFFERED);
13917 tg3_flag_set(tp, FLASH);
13918 tp->nvram_pagesize = 264;
13919 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
13920 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
13921 tp->nvram_size = (protect ? 0x3e200 :
13922 TG3_NVRAM_SIZE_512KB);
13923 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
13924 tp->nvram_size = (protect ? 0x1f200 :
13925 TG3_NVRAM_SIZE_256KB);
13927 tp->nvram_size = (protect ? 0x1f200 :
13928 TG3_NVRAM_SIZE_128KB);
13930 case FLASH_5752VENDOR_ST_M45PE10:
13931 case FLASH_5752VENDOR_ST_M45PE20:
13932 case FLASH_5752VENDOR_ST_M45PE40:
13933 tp->nvram_jedecnum = JEDEC_ST;
13934 tg3_flag_set(tp, NVRAM_BUFFERED);
13935 tg3_flag_set(tp, FLASH);
13936 tp->nvram_pagesize = 256;
13937 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
13938 tp->nvram_size = (protect ?
13939 TG3_NVRAM_SIZE_64KB :
13940 TG3_NVRAM_SIZE_128KB);
13941 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
13942 tp->nvram_size = (protect ?
13943 TG3_NVRAM_SIZE_64KB :
13944 TG3_NVRAM_SIZE_256KB);
13946 tp->nvram_size = (protect ?
13947 TG3_NVRAM_SIZE_128KB :
13948 TG3_NVRAM_SIZE_512KB);
13953 static void tg3_get_5787_nvram_info(struct tg3 *tp)
13957 nvcfg1 = tr32(NVRAM_CFG1);
13959 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13960 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
13961 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
13962 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
13963 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
13964 tp->nvram_jedecnum = JEDEC_ATMEL;
13965 tg3_flag_set(tp, NVRAM_BUFFERED);
13966 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13968 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13969 tw32(NVRAM_CFG1, nvcfg1);
13971 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
13972 case FLASH_5755VENDOR_ATMEL_FLASH_1:
13973 case FLASH_5755VENDOR_ATMEL_FLASH_2:
13974 case FLASH_5755VENDOR_ATMEL_FLASH_3:
13975 tp->nvram_jedecnum = JEDEC_ATMEL;
13976 tg3_flag_set(tp, NVRAM_BUFFERED);
13977 tg3_flag_set(tp, FLASH);
13978 tp->nvram_pagesize = 264;
13980 case FLASH_5752VENDOR_ST_M45PE10:
13981 case FLASH_5752VENDOR_ST_M45PE20:
13982 case FLASH_5752VENDOR_ST_M45PE40:
13983 tp->nvram_jedecnum = JEDEC_ST;
13984 tg3_flag_set(tp, NVRAM_BUFFERED);
13985 tg3_flag_set(tp, FLASH);
13986 tp->nvram_pagesize = 256;
13991 static void tg3_get_5761_nvram_info(struct tg3 *tp)
13993 u32 nvcfg1, protect = 0;
13995 nvcfg1 = tr32(NVRAM_CFG1);
13997 /* NVRAM protection for TPM */
13998 if (nvcfg1 & (1 << 27)) {
13999 tg3_flag_set(tp, PROTECTED_NVRAM);
14003 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14005 case FLASH_5761VENDOR_ATMEL_ADB021D:
14006 case FLASH_5761VENDOR_ATMEL_ADB041D:
14007 case FLASH_5761VENDOR_ATMEL_ADB081D:
14008 case FLASH_5761VENDOR_ATMEL_ADB161D:
14009 case FLASH_5761VENDOR_ATMEL_MDB021D:
14010 case FLASH_5761VENDOR_ATMEL_MDB041D:
14011 case FLASH_5761VENDOR_ATMEL_MDB081D:
14012 case FLASH_5761VENDOR_ATMEL_MDB161D:
14013 tp->nvram_jedecnum = JEDEC_ATMEL;
14014 tg3_flag_set(tp, NVRAM_BUFFERED);
14015 tg3_flag_set(tp, FLASH);
14016 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14017 tp->nvram_pagesize = 256;
14019 case FLASH_5761VENDOR_ST_A_M45PE20:
14020 case FLASH_5761VENDOR_ST_A_M45PE40:
14021 case FLASH_5761VENDOR_ST_A_M45PE80:
14022 case FLASH_5761VENDOR_ST_A_M45PE16:
14023 case FLASH_5761VENDOR_ST_M_M45PE20:
14024 case FLASH_5761VENDOR_ST_M_M45PE40:
14025 case FLASH_5761VENDOR_ST_M_M45PE80:
14026 case FLASH_5761VENDOR_ST_M_M45PE16:
14027 tp->nvram_jedecnum = JEDEC_ST;
14028 tg3_flag_set(tp, NVRAM_BUFFERED);
14029 tg3_flag_set(tp, FLASH);
14030 tp->nvram_pagesize = 256;
14035 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14038 case FLASH_5761VENDOR_ATMEL_ADB161D:
14039 case FLASH_5761VENDOR_ATMEL_MDB161D:
14040 case FLASH_5761VENDOR_ST_A_M45PE16:
14041 case FLASH_5761VENDOR_ST_M_M45PE16:
14042 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14044 case FLASH_5761VENDOR_ATMEL_ADB081D:
14045 case FLASH_5761VENDOR_ATMEL_MDB081D:
14046 case FLASH_5761VENDOR_ST_A_M45PE80:
14047 case FLASH_5761VENDOR_ST_M_M45PE80:
14048 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14050 case FLASH_5761VENDOR_ATMEL_ADB041D:
14051 case FLASH_5761VENDOR_ATMEL_MDB041D:
14052 case FLASH_5761VENDOR_ST_A_M45PE40:
14053 case FLASH_5761VENDOR_ST_M_M45PE40:
14054 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14056 case FLASH_5761VENDOR_ATMEL_ADB021D:
14057 case FLASH_5761VENDOR_ATMEL_MDB021D:
14058 case FLASH_5761VENDOR_ST_A_M45PE20:
14059 case FLASH_5761VENDOR_ST_M_M45PE20:
14060 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14066 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14068 tp->nvram_jedecnum = JEDEC_ATMEL;
14069 tg3_flag_set(tp, NVRAM_BUFFERED);
14070 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14073 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14077 nvcfg1 = tr32(NVRAM_CFG1);
14079 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14080 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14081 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14082 tp->nvram_jedecnum = JEDEC_ATMEL;
14083 tg3_flag_set(tp, NVRAM_BUFFERED);
14084 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14086 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14087 tw32(NVRAM_CFG1, nvcfg1);
14089 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14090 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14091 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14092 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14093 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14094 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14095 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14096 tp->nvram_jedecnum = JEDEC_ATMEL;
14097 tg3_flag_set(tp, NVRAM_BUFFERED);
14098 tg3_flag_set(tp, FLASH);
14100 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14101 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14102 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14103 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14104 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14106 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14107 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14108 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14110 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14111 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14112 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14116 case FLASH_5752VENDOR_ST_M45PE10:
14117 case FLASH_5752VENDOR_ST_M45PE20:
14118 case FLASH_5752VENDOR_ST_M45PE40:
14119 tp->nvram_jedecnum = JEDEC_ST;
14120 tg3_flag_set(tp, NVRAM_BUFFERED);
14121 tg3_flag_set(tp, FLASH);
14123 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14124 case FLASH_5752VENDOR_ST_M45PE10:
14125 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14127 case FLASH_5752VENDOR_ST_M45PE20:
14128 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14130 case FLASH_5752VENDOR_ST_M45PE40:
14131 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14136 tg3_flag_set(tp, NO_NVRAM);
14140 tg3_nvram_get_pagesize(tp, nvcfg1);
14141 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14142 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14146 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14150 nvcfg1 = tr32(NVRAM_CFG1);
14152 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14153 case FLASH_5717VENDOR_ATMEL_EEPROM:
14154 case FLASH_5717VENDOR_MICRO_EEPROM:
14155 tp->nvram_jedecnum = JEDEC_ATMEL;
14156 tg3_flag_set(tp, NVRAM_BUFFERED);
14157 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14159 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14160 tw32(NVRAM_CFG1, nvcfg1);
14162 case FLASH_5717VENDOR_ATMEL_MDB011D:
14163 case FLASH_5717VENDOR_ATMEL_ADB011B:
14164 case FLASH_5717VENDOR_ATMEL_ADB011D:
14165 case FLASH_5717VENDOR_ATMEL_MDB021D:
14166 case FLASH_5717VENDOR_ATMEL_ADB021B:
14167 case FLASH_5717VENDOR_ATMEL_ADB021D:
14168 case FLASH_5717VENDOR_ATMEL_45USPT:
14169 tp->nvram_jedecnum = JEDEC_ATMEL;
14170 tg3_flag_set(tp, NVRAM_BUFFERED);
14171 tg3_flag_set(tp, FLASH);
14173 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14174 case FLASH_5717VENDOR_ATMEL_MDB021D:
14175 /* Detect size with tg3_nvram_get_size() */
14177 case FLASH_5717VENDOR_ATMEL_ADB021B:
14178 case FLASH_5717VENDOR_ATMEL_ADB021D:
14179 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14182 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14186 case FLASH_5717VENDOR_ST_M_M25PE10:
14187 case FLASH_5717VENDOR_ST_A_M25PE10:
14188 case FLASH_5717VENDOR_ST_M_M45PE10:
14189 case FLASH_5717VENDOR_ST_A_M45PE10:
14190 case FLASH_5717VENDOR_ST_M_M25PE20:
14191 case FLASH_5717VENDOR_ST_A_M25PE20:
14192 case FLASH_5717VENDOR_ST_M_M45PE20:
14193 case FLASH_5717VENDOR_ST_A_M45PE20:
14194 case FLASH_5717VENDOR_ST_25USPT:
14195 case FLASH_5717VENDOR_ST_45USPT:
14196 tp->nvram_jedecnum = JEDEC_ST;
14197 tg3_flag_set(tp, NVRAM_BUFFERED);
14198 tg3_flag_set(tp, FLASH);
14200 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14201 case FLASH_5717VENDOR_ST_M_M25PE20:
14202 case FLASH_5717VENDOR_ST_M_M45PE20:
14203 /* Detect size with tg3_nvram_get_size() */
14205 case FLASH_5717VENDOR_ST_A_M25PE20:
14206 case FLASH_5717VENDOR_ST_A_M45PE20:
14207 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14210 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14215 tg3_flag_set(tp, NO_NVRAM);
14219 tg3_nvram_get_pagesize(tp, nvcfg1);
14220 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14221 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14224 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14226 u32 nvcfg1, nvmpinstrp;
14228 nvcfg1 = tr32(NVRAM_CFG1);
14229 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14231 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14232 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14233 tg3_flag_set(tp, NO_NVRAM);
14237 switch (nvmpinstrp) {
14238 case FLASH_5762_EEPROM_HD:
14239 nvmpinstrp = FLASH_5720_EEPROM_HD;
14241 case FLASH_5762_EEPROM_LD:
14242 nvmpinstrp = FLASH_5720_EEPROM_LD;
14244 case FLASH_5720VENDOR_M_ST_M45PE20:
14245 /* This pinstrap supports multiple sizes, so force it
14246 * to read the actual size from location 0xf0.
14248 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14253 switch (nvmpinstrp) {
14254 case FLASH_5720_EEPROM_HD:
14255 case FLASH_5720_EEPROM_LD:
14256 tp->nvram_jedecnum = JEDEC_ATMEL;
14257 tg3_flag_set(tp, NVRAM_BUFFERED);
14259 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14260 tw32(NVRAM_CFG1, nvcfg1);
14261 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14262 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14264 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14266 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14267 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14268 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14269 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14270 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14271 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14272 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14273 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14274 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14275 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14276 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14277 case FLASH_5720VENDOR_ATMEL_45USPT:
14278 tp->nvram_jedecnum = JEDEC_ATMEL;
14279 tg3_flag_set(tp, NVRAM_BUFFERED);
14280 tg3_flag_set(tp, FLASH);
14282 switch (nvmpinstrp) {
14283 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14284 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14285 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14286 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14288 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14289 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14290 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14291 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14293 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14294 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14295 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14298 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14299 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14303 case FLASH_5720VENDOR_M_ST_M25PE10:
14304 case FLASH_5720VENDOR_M_ST_M45PE10:
14305 case FLASH_5720VENDOR_A_ST_M25PE10:
14306 case FLASH_5720VENDOR_A_ST_M45PE10:
14307 case FLASH_5720VENDOR_M_ST_M25PE20:
14308 case FLASH_5720VENDOR_M_ST_M45PE20:
14309 case FLASH_5720VENDOR_A_ST_M25PE20:
14310 case FLASH_5720VENDOR_A_ST_M45PE20:
14311 case FLASH_5720VENDOR_M_ST_M25PE40:
14312 case FLASH_5720VENDOR_M_ST_M45PE40:
14313 case FLASH_5720VENDOR_A_ST_M25PE40:
14314 case FLASH_5720VENDOR_A_ST_M45PE40:
14315 case FLASH_5720VENDOR_M_ST_M25PE80:
14316 case FLASH_5720VENDOR_M_ST_M45PE80:
14317 case FLASH_5720VENDOR_A_ST_M25PE80:
14318 case FLASH_5720VENDOR_A_ST_M45PE80:
14319 case FLASH_5720VENDOR_ST_25USPT:
14320 case FLASH_5720VENDOR_ST_45USPT:
14321 tp->nvram_jedecnum = JEDEC_ST;
14322 tg3_flag_set(tp, NVRAM_BUFFERED);
14323 tg3_flag_set(tp, FLASH);
14325 switch (nvmpinstrp) {
14326 case FLASH_5720VENDOR_M_ST_M25PE20:
14327 case FLASH_5720VENDOR_M_ST_M45PE20:
14328 case FLASH_5720VENDOR_A_ST_M25PE20:
14329 case FLASH_5720VENDOR_A_ST_M45PE20:
14330 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14332 case FLASH_5720VENDOR_M_ST_M25PE40:
14333 case FLASH_5720VENDOR_M_ST_M45PE40:
14334 case FLASH_5720VENDOR_A_ST_M25PE40:
14335 case FLASH_5720VENDOR_A_ST_M45PE40:
14336 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14338 case FLASH_5720VENDOR_M_ST_M25PE80:
14339 case FLASH_5720VENDOR_M_ST_M45PE80:
14340 case FLASH_5720VENDOR_A_ST_M25PE80:
14341 case FLASH_5720VENDOR_A_ST_M45PE80:
14342 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14345 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14346 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14351 tg3_flag_set(tp, NO_NVRAM);
14355 tg3_nvram_get_pagesize(tp, nvcfg1);
14356 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14357 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14359 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14362 if (tg3_nvram_read(tp, 0, &val))
14365 if (val != TG3_EEPROM_MAGIC &&
14366 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14367 tg3_flag_set(tp, NO_NVRAM);
14371 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
14372 static void tg3_nvram_init(struct tg3 *tp)
14374 if (tg3_flag(tp, IS_SSB_CORE)) {
14375 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14376 tg3_flag_clear(tp, NVRAM);
14377 tg3_flag_clear(tp, NVRAM_BUFFERED);
14378 tg3_flag_set(tp, NO_NVRAM);
14382 tw32_f(GRC_EEPROM_ADDR,
14383 (EEPROM_ADDR_FSM_RESET |
14384 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14385 EEPROM_ADDR_CLKPERD_SHIFT)));
14389 /* Enable seeprom accesses. */
14390 tw32_f(GRC_LOCAL_CTRL,
14391 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14394 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14395 tg3_asic_rev(tp) != ASIC_REV_5701) {
14396 tg3_flag_set(tp, NVRAM);
14398 if (tg3_nvram_lock(tp)) {
14399 netdev_warn(tp->dev,
14400 "Cannot get nvram lock, %s failed\n",
14404 tg3_enable_nvram_access(tp);
14406 tp->nvram_size = 0;
14408 if (tg3_asic_rev(tp) == ASIC_REV_5752)
14409 tg3_get_5752_nvram_info(tp);
14410 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
14411 tg3_get_5755_nvram_info(tp);
14412 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14413 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14414 tg3_asic_rev(tp) == ASIC_REV_5785)
14415 tg3_get_5787_nvram_info(tp);
14416 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
14417 tg3_get_5761_nvram_info(tp);
14418 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
14419 tg3_get_5906_nvram_info(tp);
14420 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
14421 tg3_flag(tp, 57765_CLASS))
14422 tg3_get_57780_nvram_info(tp);
14423 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14424 tg3_asic_rev(tp) == ASIC_REV_5719)
14425 tg3_get_5717_nvram_info(tp);
14426 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14427 tg3_asic_rev(tp) == ASIC_REV_5762)
14428 tg3_get_5720_nvram_info(tp);
14430 tg3_get_nvram_info(tp);
14432 if (tp->nvram_size == 0)
14433 tg3_get_nvram_size(tp);
14435 tg3_disable_nvram_access(tp);
14436 tg3_nvram_unlock(tp);
14439 tg3_flag_clear(tp, NVRAM);
14440 tg3_flag_clear(tp, NVRAM_BUFFERED);
14442 tg3_get_eeprom_size(tp);
14446 struct subsys_tbl_ent {
14447 u16 subsys_vendor, subsys_devid;
14451 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
14452 /* Broadcom boards. */
14453 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14454 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
14455 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14456 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
14457 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14458 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
14459 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14460 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14461 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14462 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
14463 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14464 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
14465 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14466 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14467 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14468 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
14469 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14470 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
14471 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14472 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
14473 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14474 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
14477 { TG3PCI_SUBVENDOR_ID_3COM,
14478 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
14479 { TG3PCI_SUBVENDOR_ID_3COM,
14480 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
14481 { TG3PCI_SUBVENDOR_ID_3COM,
14482 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
14483 { TG3PCI_SUBVENDOR_ID_3COM,
14484 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
14485 { TG3PCI_SUBVENDOR_ID_3COM,
14486 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
14489 { TG3PCI_SUBVENDOR_ID_DELL,
14490 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
14491 { TG3PCI_SUBVENDOR_ID_DELL,
14492 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
14493 { TG3PCI_SUBVENDOR_ID_DELL,
14494 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
14495 { TG3PCI_SUBVENDOR_ID_DELL,
14496 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
14498 /* Compaq boards. */
14499 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14500 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
14501 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14502 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
14503 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14504 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14505 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14506 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
14507 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14508 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
14511 { TG3PCI_SUBVENDOR_ID_IBM,
14512 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
14515 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
14519 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
14520 if ((subsys_id_to_phy_id[i].subsys_vendor ==
14521 tp->pdev->subsystem_vendor) &&
14522 (subsys_id_to_phy_id[i].subsys_devid ==
14523 tp->pdev->subsystem_device))
14524 return &subsys_id_to_phy_id[i];
14529 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
14533 tp->phy_id = TG3_PHY_ID_INVALID;
14534 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14536 /* Assume an onboard device and WOL capable by default. */
14537 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14538 tg3_flag_set(tp, WOL_CAP);
14540 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
14541 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
14542 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14543 tg3_flag_set(tp, IS_NIC);
14545 val = tr32(VCPU_CFGSHDW);
14546 if (val & VCPU_CFGSHDW_ASPM_DBNC)
14547 tg3_flag_set(tp, ASPM_WORKAROUND);
14548 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
14549 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
14550 tg3_flag_set(tp, WOL_ENABLE);
14551 device_set_wakeup_enable(&tp->pdev->dev, true);
14556 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
14557 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
14558 u32 nic_cfg, led_cfg;
14559 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
14560 int eeprom_phy_serdes = 0;
14562 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
14563 tp->nic_sram_data_cfg = nic_cfg;
14565 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
14566 ver >>= NIC_SRAM_DATA_VER_SHIFT;
14567 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14568 tg3_asic_rev(tp) != ASIC_REV_5701 &&
14569 tg3_asic_rev(tp) != ASIC_REV_5703 &&
14570 (ver > 0) && (ver < 0x100))
14571 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
14573 if (tg3_asic_rev(tp) == ASIC_REV_5785)
14574 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
14576 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
14577 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
14578 eeprom_phy_serdes = 1;
14580 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
14581 if (nic_phy_id != 0) {
14582 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
14583 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
14585 eeprom_phy_id = (id1 >> 16) << 10;
14586 eeprom_phy_id |= (id2 & 0xfc00) << 16;
14587 eeprom_phy_id |= (id2 & 0x03ff) << 0;
14591 tp->phy_id = eeprom_phy_id;
14592 if (eeprom_phy_serdes) {
14593 if (!tg3_flag(tp, 5705_PLUS))
14594 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
14596 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
14599 if (tg3_flag(tp, 5750_PLUS))
14600 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
14601 SHASTA_EXT_LED_MODE_MASK);
14603 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
14607 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
14608 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14611 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
14612 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14615 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
14616 tp->led_ctrl = LED_CTRL_MODE_MAC;
14618 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
14619 * read on some older 5700/5701 bootcode.
14621 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
14622 tg3_asic_rev(tp) == ASIC_REV_5701)
14623 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14627 case SHASTA_EXT_LED_SHARED:
14628 tp->led_ctrl = LED_CTRL_MODE_SHARED;
14629 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
14630 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
14631 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14632 LED_CTRL_MODE_PHY_2);
14635 case SHASTA_EXT_LED_MAC:
14636 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
14639 case SHASTA_EXT_LED_COMBO:
14640 tp->led_ctrl = LED_CTRL_MODE_COMBO;
14641 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
14642 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14643 LED_CTRL_MODE_PHY_2);
14648 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
14649 tg3_asic_rev(tp) == ASIC_REV_5701) &&
14650 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
14651 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14653 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
14654 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14656 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
14657 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14658 if ((tp->pdev->subsystem_vendor ==
14659 PCI_VENDOR_ID_ARIMA) &&
14660 (tp->pdev->subsystem_device == 0x205a ||
14661 tp->pdev->subsystem_device == 0x2063))
14662 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14664 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14665 tg3_flag_set(tp, IS_NIC);
14668 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
14669 tg3_flag_set(tp, ENABLE_ASF);
14670 if (tg3_flag(tp, 5750_PLUS))
14671 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
14674 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
14675 tg3_flag(tp, 5750_PLUS))
14676 tg3_flag_set(tp, ENABLE_APE);
14678 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
14679 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
14680 tg3_flag_clear(tp, WOL_CAP);
14682 if (tg3_flag(tp, WOL_CAP) &&
14683 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
14684 tg3_flag_set(tp, WOL_ENABLE);
14685 device_set_wakeup_enable(&tp->pdev->dev, true);
14688 if (cfg2 & (1 << 17))
14689 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
14691 /* serdes signal pre-emphasis in register 0x590 set by */
14692 /* bootcode if bit 18 is set */
14693 if (cfg2 & (1 << 18))
14694 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
14696 if ((tg3_flag(tp, 57765_PLUS) ||
14697 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
14698 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
14699 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
14700 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
14702 if (tg3_flag(tp, PCI_EXPRESS)) {
14705 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
14706 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
14707 !tg3_flag(tp, 57765_PLUS) &&
14708 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
14709 tg3_flag_set(tp, ASPM_WORKAROUND);
14710 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
14711 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
14712 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
14713 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
14716 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
14717 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
14718 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
14719 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
14720 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
14721 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
14724 if (tg3_flag(tp, WOL_CAP))
14725 device_set_wakeup_enable(&tp->pdev->dev,
14726 tg3_flag(tp, WOL_ENABLE));
14728 device_set_wakeup_capable(&tp->pdev->dev, false);
14731 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
14734 u32 val2, off = offset * 8;
14736 err = tg3_nvram_lock(tp);
14740 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
14741 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
14742 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
14743 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
14746 for (i = 0; i < 100; i++) {
14747 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
14748 if (val2 & APE_OTP_STATUS_CMD_DONE) {
14749 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
14755 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
14757 tg3_nvram_unlock(tp);
14758 if (val2 & APE_OTP_STATUS_CMD_DONE)
14764 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
14769 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
14770 tw32(OTP_CTRL, cmd);
14772 /* Wait for up to 1 ms for command to execute. */
14773 for (i = 0; i < 100; i++) {
14774 val = tr32(OTP_STATUS);
14775 if (val & OTP_STATUS_CMD_DONE)
14780 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
14783 /* Read the gphy configuration from the OTP region of the chip. The gphy
14784 * configuration is a 32-bit value that straddles the alignment boundary.
14785 * We do two 32-bit reads and then shift and merge the results.
14787 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
14789 u32 bhalf_otp, thalf_otp;
14791 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
14793 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
14796 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
14798 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
14801 thalf_otp = tr32(OTP_READ_DATA);
14803 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
14805 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
14808 bhalf_otp = tr32(OTP_READ_DATA);
14810 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
14813 static void tg3_phy_init_link_config(struct tg3 *tp)
14815 u32 adv = ADVERTISED_Autoneg;
14817 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
14818 adv |= ADVERTISED_1000baseT_Half |
14819 ADVERTISED_1000baseT_Full;
14821 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
14822 adv |= ADVERTISED_100baseT_Half |
14823 ADVERTISED_100baseT_Full |
14824 ADVERTISED_10baseT_Half |
14825 ADVERTISED_10baseT_Full |
14828 adv |= ADVERTISED_FIBRE;
14830 tp->link_config.advertising = adv;
14831 tp->link_config.speed = SPEED_UNKNOWN;
14832 tp->link_config.duplex = DUPLEX_UNKNOWN;
14833 tp->link_config.autoneg = AUTONEG_ENABLE;
14834 tp->link_config.active_speed = SPEED_UNKNOWN;
14835 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
14840 static int tg3_phy_probe(struct tg3 *tp)
14842 u32 hw_phy_id_1, hw_phy_id_2;
14843 u32 hw_phy_id, hw_phy_id_masked;
14846 /* flow control autonegotiation is default behavior */
14847 tg3_flag_set(tp, PAUSE_AUTONEG);
14848 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14850 if (tg3_flag(tp, ENABLE_APE)) {
14851 switch (tp->pci_fn) {
14853 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
14856 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
14859 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
14862 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
14867 if (!tg3_flag(tp, ENABLE_ASF) &&
14868 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
14869 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
14870 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
14871 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
14873 if (tg3_flag(tp, USE_PHYLIB))
14874 return tg3_phy_init(tp);
14876 /* Reading the PHY ID register can conflict with ASF
14877 * firmware access to the PHY hardware.
14880 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
14881 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
14883 /* Now read the physical PHY_ID from the chip and verify
14884 * that it is sane. If it doesn't look good, we fall back
14885 * to either the hard-coded table based PHY_ID and failing
14886 * that the value found in the eeprom area.
14888 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
14889 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
14891 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
14892 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
14893 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
14895 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
14898 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
14899 tp->phy_id = hw_phy_id;
14900 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
14901 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
14903 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
14905 if (tp->phy_id != TG3_PHY_ID_INVALID) {
14906 /* Do nothing, phy ID already set up in
14907 * tg3_get_eeprom_hw_cfg().
14910 struct subsys_tbl_ent *p;
14912 /* No eeprom signature? Try the hardcoded
14913 * subsys device table.
14915 p = tg3_lookup_by_subsys(tp);
14917 tp->phy_id = p->phy_id;
14918 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
14919 /* For now we saw the IDs 0xbc050cd0,
14920 * 0xbc050f80 and 0xbc050c30 on devices
14921 * connected to an BCM4785 and there are
14922 * probably more. Just assume that the phy is
14923 * supported when it is connected to a SSB core
14930 tp->phy_id == TG3_PHY_ID_BCM8002)
14931 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
14935 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
14936 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
14937 tg3_asic_rev(tp) == ASIC_REV_5720 ||
14938 tg3_asic_rev(tp) == ASIC_REV_57766 ||
14939 tg3_asic_rev(tp) == ASIC_REV_5762 ||
14940 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
14941 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
14942 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
14943 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0)))
14944 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
14946 tg3_phy_init_link_config(tp);
14948 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
14949 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
14950 !tg3_flag(tp, ENABLE_APE) &&
14951 !tg3_flag(tp, ENABLE_ASF)) {
14954 tg3_readphy(tp, MII_BMSR, &bmsr);
14955 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
14956 (bmsr & BMSR_LSTATUS))
14957 goto skip_phy_reset;
14959 err = tg3_phy_reset(tp);
14963 tg3_phy_set_wirespeed(tp);
14965 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
14966 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
14967 tp->link_config.flowctrl);
14969 tg3_writephy(tp, MII_BMCR,
14970 BMCR_ANENABLE | BMCR_ANRESTART);
14975 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
14976 err = tg3_init_5401phy_dsp(tp);
14980 err = tg3_init_5401phy_dsp(tp);
14986 static void tg3_read_vpd(struct tg3 *tp)
14989 unsigned int block_end, rosize, len;
14993 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
14997 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
14999 goto out_not_found;
15001 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15002 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15003 i += PCI_VPD_LRDT_TAG_SIZE;
15005 if (block_end > vpdlen)
15006 goto out_not_found;
15008 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15009 PCI_VPD_RO_KEYWORD_MFR_ID);
15011 len = pci_vpd_info_field_size(&vpd_data[j]);
15013 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15014 if (j + len > block_end || len != 4 ||
15015 memcmp(&vpd_data[j], "1028", 4))
15018 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15019 PCI_VPD_RO_KEYWORD_VENDOR0);
15023 len = pci_vpd_info_field_size(&vpd_data[j]);
15025 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15026 if (j + len > block_end)
15029 if (len >= sizeof(tp->fw_ver))
15030 len = sizeof(tp->fw_ver) - 1;
15031 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15032 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15037 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15038 PCI_VPD_RO_KEYWORD_PARTNO);
15040 goto out_not_found;
15042 len = pci_vpd_info_field_size(&vpd_data[i]);
15044 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15045 if (len > TG3_BPN_SIZE ||
15046 (len + i) > vpdlen)
15047 goto out_not_found;
15049 memcpy(tp->board_part_number, &vpd_data[i], len);
15053 if (tp->board_part_number[0])
15057 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15058 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15059 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15060 strcpy(tp->board_part_number, "BCM5717");
15061 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15062 strcpy(tp->board_part_number, "BCM5718");
15065 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15066 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15067 strcpy(tp->board_part_number, "BCM57780");
15068 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15069 strcpy(tp->board_part_number, "BCM57760");
15070 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15071 strcpy(tp->board_part_number, "BCM57790");
15072 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15073 strcpy(tp->board_part_number, "BCM57788");
15076 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15077 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15078 strcpy(tp->board_part_number, "BCM57761");
15079 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15080 strcpy(tp->board_part_number, "BCM57765");
15081 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15082 strcpy(tp->board_part_number, "BCM57781");
15083 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15084 strcpy(tp->board_part_number, "BCM57785");
15085 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15086 strcpy(tp->board_part_number, "BCM57791");
15087 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15088 strcpy(tp->board_part_number, "BCM57795");
15091 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15092 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15093 strcpy(tp->board_part_number, "BCM57762");
15094 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15095 strcpy(tp->board_part_number, "BCM57766");
15096 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15097 strcpy(tp->board_part_number, "BCM57782");
15098 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15099 strcpy(tp->board_part_number, "BCM57786");
15102 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15103 strcpy(tp->board_part_number, "BCM95906");
15106 strcpy(tp->board_part_number, "none");
15110 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15114 if (tg3_nvram_read(tp, offset, &val) ||
15115 (val & 0xfc000000) != 0x0c000000 ||
15116 tg3_nvram_read(tp, offset + 4, &val) ||
15123 static void tg3_read_bc_ver(struct tg3 *tp)
15125 u32 val, offset, start, ver_offset;
15127 bool newver = false;
15129 if (tg3_nvram_read(tp, 0xc, &offset) ||
15130 tg3_nvram_read(tp, 0x4, &start))
15133 offset = tg3_nvram_logical_addr(tp, offset);
15135 if (tg3_nvram_read(tp, offset, &val))
15138 if ((val & 0xfc000000) == 0x0c000000) {
15139 if (tg3_nvram_read(tp, offset + 4, &val))
15146 dst_off = strlen(tp->fw_ver);
15149 if (TG3_VER_SIZE - dst_off < 16 ||
15150 tg3_nvram_read(tp, offset + 8, &ver_offset))
15153 offset = offset + ver_offset - start;
15154 for (i = 0; i < 16; i += 4) {
15156 if (tg3_nvram_read_be32(tp, offset + i, &v))
15159 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15164 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15167 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15168 TG3_NVM_BCVER_MAJSFT;
15169 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
15170 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15171 "v%d.%02d", major, minor);
15175 static void tg3_read_hwsb_ver(struct tg3 *tp)
15177 u32 val, major, minor;
15179 /* Use native endian representation */
15180 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15183 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15184 TG3_NVM_HWSB_CFG1_MAJSFT;
15185 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15186 TG3_NVM_HWSB_CFG1_MINSFT;
15188 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15191 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15193 u32 offset, major, minor, build;
15195 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15197 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15200 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15201 case TG3_EEPROM_SB_REVISION_0:
15202 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15204 case TG3_EEPROM_SB_REVISION_2:
15205 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15207 case TG3_EEPROM_SB_REVISION_3:
15208 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15210 case TG3_EEPROM_SB_REVISION_4:
15211 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15213 case TG3_EEPROM_SB_REVISION_5:
15214 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15216 case TG3_EEPROM_SB_REVISION_6:
15217 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15223 if (tg3_nvram_read(tp, offset, &val))
15226 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15227 TG3_EEPROM_SB_EDH_BLD_SHFT;
15228 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15229 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15230 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15232 if (minor > 99 || build > 26)
15235 offset = strlen(tp->fw_ver);
15236 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15237 " v%d.%02d", major, minor);
15240 offset = strlen(tp->fw_ver);
15241 if (offset < TG3_VER_SIZE - 1)
15242 tp->fw_ver[offset] = 'a' + build - 1;
15246 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15248 u32 val, offset, start;
15251 for (offset = TG3_NVM_DIR_START;
15252 offset < TG3_NVM_DIR_END;
15253 offset += TG3_NVM_DIRENT_SIZE) {
15254 if (tg3_nvram_read(tp, offset, &val))
15257 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15261 if (offset == TG3_NVM_DIR_END)
15264 if (!tg3_flag(tp, 5705_PLUS))
15265 start = 0x08000000;
15266 else if (tg3_nvram_read(tp, offset - 4, &start))
15269 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15270 !tg3_fw_img_is_valid(tp, offset) ||
15271 tg3_nvram_read(tp, offset + 8, &val))
15274 offset += val - start;
15276 vlen = strlen(tp->fw_ver);
15278 tp->fw_ver[vlen++] = ',';
15279 tp->fw_ver[vlen++] = ' ';
15281 for (i = 0; i < 4; i++) {
15283 if (tg3_nvram_read_be32(tp, offset, &v))
15286 offset += sizeof(v);
15288 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15289 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15293 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15298 static void tg3_probe_ncsi(struct tg3 *tp)
15302 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15303 if (apedata != APE_SEG_SIG_MAGIC)
15306 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15307 if (!(apedata & APE_FW_STATUS_READY))
15310 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15311 tg3_flag_set(tp, APE_HAS_NCSI);
15314 static void tg3_read_dash_ver(struct tg3 *tp)
15320 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15322 if (tg3_flag(tp, APE_HAS_NCSI))
15324 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15329 vlen = strlen(tp->fw_ver);
15331 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15333 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15334 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15335 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15336 (apedata & APE_FW_VERSION_BLDMSK));
15339 static void tg3_read_otp_ver(struct tg3 *tp)
15343 if (tg3_asic_rev(tp) != ASIC_REV_5762)
15346 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15347 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15348 TG3_OTP_MAGIC0_VALID(val)) {
15349 u64 val64 = (u64) val << 32 | val2;
15353 for (i = 0; i < 7; i++) {
15354 if ((val64 & 0xff) == 0)
15356 ver = val64 & 0xff;
15359 vlen = strlen(tp->fw_ver);
15360 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15364 static void tg3_read_fw_ver(struct tg3 *tp)
15367 bool vpd_vers = false;
15369 if (tp->fw_ver[0] != 0)
15372 if (tg3_flag(tp, NO_NVRAM)) {
15373 strcat(tp->fw_ver, "sb");
15374 tg3_read_otp_ver(tp);
15378 if (tg3_nvram_read(tp, 0, &val))
15381 if (val == TG3_EEPROM_MAGIC)
15382 tg3_read_bc_ver(tp);
15383 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15384 tg3_read_sb_ver(tp, val);
15385 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15386 tg3_read_hwsb_ver(tp);
15388 if (tg3_flag(tp, ENABLE_ASF)) {
15389 if (tg3_flag(tp, ENABLE_APE)) {
15390 tg3_probe_ncsi(tp);
15392 tg3_read_dash_ver(tp);
15393 } else if (!vpd_vers) {
15394 tg3_read_mgmtfw_ver(tp);
15398 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
15401 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15403 if (tg3_flag(tp, LRG_PROD_RING_CAP))
15404 return TG3_RX_RET_MAX_SIZE_5717;
15405 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
15406 return TG3_RX_RET_MAX_SIZE_5700;
15408 return TG3_RX_RET_MAX_SIZE_5705;
15411 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
15412 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15413 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15414 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15418 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
15420 struct pci_dev *peer;
15421 unsigned int func, devnr = tp->pdev->devfn & ~7;
15423 for (func = 0; func < 8; func++) {
15424 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15425 if (peer && peer != tp->pdev)
15429 /* 5704 can be configured in single-port mode, set peer to
15430 * tp->pdev in that case.
15438 * We don't need to keep the refcount elevated; there's no way
15439 * to remove one half of this device without removing the other
15446 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
15448 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
15449 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
15452 /* All devices that use the alternate
15453 * ASIC REV location have a CPMU.
15455 tg3_flag_set(tp, CPMU_PRESENT);
15457 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15458 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
15459 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15460 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15461 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
15462 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
15463 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
15464 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727)
15465 reg = TG3PCI_GEN2_PRODID_ASICREV;
15466 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
15467 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
15468 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
15469 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
15470 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15471 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15472 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
15473 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
15474 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
15475 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15476 reg = TG3PCI_GEN15_PRODID_ASICREV;
15478 reg = TG3PCI_PRODID_ASICREV;
15480 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
15483 /* Wrong chip ID in 5752 A0. This code can be removed later
15484 * as A0 is not in production.
15486 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
15487 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
15489 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
15490 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
15492 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15493 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15494 tg3_asic_rev(tp) == ASIC_REV_5720)
15495 tg3_flag_set(tp, 5717_PLUS);
15497 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
15498 tg3_asic_rev(tp) == ASIC_REV_57766)
15499 tg3_flag_set(tp, 57765_CLASS);
15501 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
15502 tg3_asic_rev(tp) == ASIC_REV_5762)
15503 tg3_flag_set(tp, 57765_PLUS);
15505 /* Intentionally exclude ASIC_REV_5906 */
15506 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
15507 tg3_asic_rev(tp) == ASIC_REV_5787 ||
15508 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15509 tg3_asic_rev(tp) == ASIC_REV_5761 ||
15510 tg3_asic_rev(tp) == ASIC_REV_5785 ||
15511 tg3_asic_rev(tp) == ASIC_REV_57780 ||
15512 tg3_flag(tp, 57765_PLUS))
15513 tg3_flag_set(tp, 5755_PLUS);
15515 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
15516 tg3_asic_rev(tp) == ASIC_REV_5714)
15517 tg3_flag_set(tp, 5780_CLASS);
15519 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
15520 tg3_asic_rev(tp) == ASIC_REV_5752 ||
15521 tg3_asic_rev(tp) == ASIC_REV_5906 ||
15522 tg3_flag(tp, 5755_PLUS) ||
15523 tg3_flag(tp, 5780_CLASS))
15524 tg3_flag_set(tp, 5750_PLUS);
15526 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
15527 tg3_flag(tp, 5750_PLUS))
15528 tg3_flag_set(tp, 5705_PLUS);
15531 static bool tg3_10_100_only_device(struct tg3 *tp,
15532 const struct pci_device_id *ent)
15534 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
15536 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
15537 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
15538 (tp->phy_flags & TG3_PHYFLG_IS_FET))
15541 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
15542 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
15543 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
15553 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
15556 u32 pci_state_reg, grc_misc_cfg;
15561 /* Force memory write invalidate off. If we leave it on,
15562 * then on 5700_BX chips we have to enable a workaround.
15563 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
15564 * to match the cacheline size. The Broadcom driver have this
15565 * workaround but turns MWI off all the times so never uses
15566 * it. This seems to suggest that the workaround is insufficient.
15568 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
15569 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
15570 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
15572 /* Important! -- Make sure register accesses are byteswapped
15573 * correctly. Also, for those chips that require it, make
15574 * sure that indirect register accesses are enabled before
15575 * the first operation.
15577 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15579 tp->misc_host_ctrl |= (misc_ctrl_reg &
15580 MISC_HOST_CTRL_CHIPREV);
15581 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15582 tp->misc_host_ctrl);
15584 tg3_detect_asic_rev(tp, misc_ctrl_reg);
15586 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
15587 * we need to disable memory and use config. cycles
15588 * only to access all registers. The 5702/03 chips
15589 * can mistakenly decode the special cycles from the
15590 * ICH chipsets as memory write cycles, causing corruption
15591 * of register and memory space. Only certain ICH bridges
15592 * will drive special cycles with non-zero data during the
15593 * address phase which can fall within the 5703's address
15594 * range. This is not an ICH bug as the PCI spec allows
15595 * non-zero address during special cycles. However, only
15596 * these ICH bridges are known to drive non-zero addresses
15597 * during special cycles.
15599 * Since special cycles do not cross PCI bridges, we only
15600 * enable this workaround if the 5703 is on the secondary
15601 * bus of these ICH bridges.
15603 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
15604 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
15605 static struct tg3_dev_id {
15609 } ich_chipsets[] = {
15610 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
15612 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
15614 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
15616 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
15620 struct tg3_dev_id *pci_id = &ich_chipsets[0];
15621 struct pci_dev *bridge = NULL;
15623 while (pci_id->vendor != 0) {
15624 bridge = pci_get_device(pci_id->vendor, pci_id->device,
15630 if (pci_id->rev != PCI_ANY_ID) {
15631 if (bridge->revision > pci_id->rev)
15634 if (bridge->subordinate &&
15635 (bridge->subordinate->number ==
15636 tp->pdev->bus->number)) {
15637 tg3_flag_set(tp, ICH_WORKAROUND);
15638 pci_dev_put(bridge);
15644 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
15645 static struct tg3_dev_id {
15648 } bridge_chipsets[] = {
15649 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
15650 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
15653 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
15654 struct pci_dev *bridge = NULL;
15656 while (pci_id->vendor != 0) {
15657 bridge = pci_get_device(pci_id->vendor,
15664 if (bridge->subordinate &&
15665 (bridge->subordinate->number <=
15666 tp->pdev->bus->number) &&
15667 (bridge->subordinate->busn_res.end >=
15668 tp->pdev->bus->number)) {
15669 tg3_flag_set(tp, 5701_DMA_BUG);
15670 pci_dev_put(bridge);
15676 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
15677 * DMA addresses > 40-bit. This bridge may have other additional
15678 * 57xx devices behind it in some 4-port NIC designs for example.
15679 * Any tg3 device found behind the bridge will also need the 40-bit
15682 if (tg3_flag(tp, 5780_CLASS)) {
15683 tg3_flag_set(tp, 40BIT_DMA_BUG);
15684 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
15686 struct pci_dev *bridge = NULL;
15689 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
15690 PCI_DEVICE_ID_SERVERWORKS_EPB,
15692 if (bridge && bridge->subordinate &&
15693 (bridge->subordinate->number <=
15694 tp->pdev->bus->number) &&
15695 (bridge->subordinate->busn_res.end >=
15696 tp->pdev->bus->number)) {
15697 tg3_flag_set(tp, 40BIT_DMA_BUG);
15698 pci_dev_put(bridge);
15704 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
15705 tg3_asic_rev(tp) == ASIC_REV_5714)
15706 tp->pdev_peer = tg3_find_peer(tp);
15708 /* Determine TSO capabilities */
15709 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
15710 ; /* Do nothing. HW bug. */
15711 else if (tg3_flag(tp, 57765_PLUS))
15712 tg3_flag_set(tp, HW_TSO_3);
15713 else if (tg3_flag(tp, 5755_PLUS) ||
15714 tg3_asic_rev(tp) == ASIC_REV_5906)
15715 tg3_flag_set(tp, HW_TSO_2);
15716 else if (tg3_flag(tp, 5750_PLUS)) {
15717 tg3_flag_set(tp, HW_TSO_1);
15718 tg3_flag_set(tp, TSO_BUG);
15719 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
15720 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
15721 tg3_flag_clear(tp, TSO_BUG);
15722 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15723 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15724 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
15725 tg3_flag_set(tp, FW_TSO);
15726 tg3_flag_set(tp, TSO_BUG);
15727 if (tg3_asic_rev(tp) == ASIC_REV_5705)
15728 tp->fw_needed = FIRMWARE_TG3TSO5;
15730 tp->fw_needed = FIRMWARE_TG3TSO;
15733 /* Selectively allow TSO based on operating conditions */
15734 if (tg3_flag(tp, HW_TSO_1) ||
15735 tg3_flag(tp, HW_TSO_2) ||
15736 tg3_flag(tp, HW_TSO_3) ||
15737 tg3_flag(tp, FW_TSO)) {
15738 /* For firmware TSO, assume ASF is disabled.
15739 * We'll disable TSO later if we discover ASF
15740 * is enabled in tg3_get_eeprom_hw_cfg().
15742 tg3_flag_set(tp, TSO_CAPABLE);
15744 tg3_flag_clear(tp, TSO_CAPABLE);
15745 tg3_flag_clear(tp, TSO_BUG);
15746 tp->fw_needed = NULL;
15749 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
15750 tp->fw_needed = FIRMWARE_TG3;
15752 if (tg3_asic_rev(tp) == ASIC_REV_57766)
15753 tp->fw_needed = FIRMWARE_TG357766;
15757 if (tg3_flag(tp, 5750_PLUS)) {
15758 tg3_flag_set(tp, SUPPORT_MSI);
15759 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
15760 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
15761 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
15762 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
15763 tp->pdev_peer == tp->pdev))
15764 tg3_flag_clear(tp, SUPPORT_MSI);
15766 if (tg3_flag(tp, 5755_PLUS) ||
15767 tg3_asic_rev(tp) == ASIC_REV_5906) {
15768 tg3_flag_set(tp, 1SHOT_MSI);
15771 if (tg3_flag(tp, 57765_PLUS)) {
15772 tg3_flag_set(tp, SUPPORT_MSIX);
15773 tp->irq_max = TG3_IRQ_MAX_VECS;
15779 if (tp->irq_max > 1) {
15780 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
15781 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
15783 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15784 tg3_asic_rev(tp) == ASIC_REV_5720)
15785 tp->txq_max = tp->irq_max - 1;
15788 if (tg3_flag(tp, 5755_PLUS) ||
15789 tg3_asic_rev(tp) == ASIC_REV_5906)
15790 tg3_flag_set(tp, SHORT_DMA_BUG);
15792 if (tg3_asic_rev(tp) == ASIC_REV_5719)
15793 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
15795 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15796 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15797 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15798 tg3_asic_rev(tp) == ASIC_REV_5762)
15799 tg3_flag_set(tp, LRG_PROD_RING_CAP);
15801 if (tg3_flag(tp, 57765_PLUS) &&
15802 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
15803 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
15805 if (!tg3_flag(tp, 5705_PLUS) ||
15806 tg3_flag(tp, 5780_CLASS) ||
15807 tg3_flag(tp, USE_JUMBO_BDFLAG))
15808 tg3_flag_set(tp, JUMBO_CAPABLE);
15810 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
15813 if (pci_is_pcie(tp->pdev)) {
15816 tg3_flag_set(tp, PCI_EXPRESS);
15818 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
15819 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
15820 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15821 tg3_flag_clear(tp, HW_TSO_2);
15822 tg3_flag_clear(tp, TSO_CAPABLE);
15824 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
15825 tg3_asic_rev(tp) == ASIC_REV_5761 ||
15826 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
15827 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
15828 tg3_flag_set(tp, CLKREQ_BUG);
15829 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
15830 tg3_flag_set(tp, L1PLLPD_EN);
15832 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
15833 /* BCM5785 devices are effectively PCIe devices, and should
15834 * follow PCIe codepaths, but do not have a PCIe capabilities
15837 tg3_flag_set(tp, PCI_EXPRESS);
15838 } else if (!tg3_flag(tp, 5705_PLUS) ||
15839 tg3_flag(tp, 5780_CLASS)) {
15840 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
15841 if (!tp->pcix_cap) {
15842 dev_err(&tp->pdev->dev,
15843 "Cannot find PCI-X capability, aborting\n");
15847 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
15848 tg3_flag_set(tp, PCIX_MODE);
15851 /* If we have an AMD 762 or VIA K8T800 chipset, write
15852 * reordering to the mailbox registers done by the host
15853 * controller can cause major troubles. We read back from
15854 * every mailbox register write to force the writes to be
15855 * posted to the chip in order.
15857 if (pci_dev_present(tg3_write_reorder_chipsets) &&
15858 !tg3_flag(tp, PCI_EXPRESS))
15859 tg3_flag_set(tp, MBOX_WRITE_REORDER);
15861 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
15862 &tp->pci_cacheline_sz);
15863 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
15864 &tp->pci_lat_timer);
15865 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
15866 tp->pci_lat_timer < 64) {
15867 tp->pci_lat_timer = 64;
15868 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
15869 tp->pci_lat_timer);
15872 /* Important! -- It is critical that the PCI-X hw workaround
15873 * situation is decided before the first MMIO register access.
15875 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
15876 /* 5700 BX chips need to have their TX producer index
15877 * mailboxes written twice to workaround a bug.
15879 tg3_flag_set(tp, TXD_MBOX_HWBUG);
15881 /* If we are in PCI-X mode, enable register write workaround.
15883 * The workaround is to use indirect register accesses
15884 * for all chip writes not to mailbox registers.
15886 if (tg3_flag(tp, PCIX_MODE)) {
15889 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
15891 /* The chip can have it's power management PCI config
15892 * space registers clobbered due to this bug.
15893 * So explicitly force the chip into D0 here.
15895 pci_read_config_dword(tp->pdev,
15896 tp->pm_cap + PCI_PM_CTRL,
15898 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
15899 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
15900 pci_write_config_dword(tp->pdev,
15901 tp->pm_cap + PCI_PM_CTRL,
15904 /* Also, force SERR#/PERR# in PCI command. */
15905 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
15906 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
15907 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
15911 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
15912 tg3_flag_set(tp, PCI_HIGH_SPEED);
15913 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
15914 tg3_flag_set(tp, PCI_32BIT);
15916 /* Chip-specific fixup from Broadcom driver */
15917 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
15918 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
15919 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
15920 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
15923 /* Default fast path register access methods */
15924 tp->read32 = tg3_read32;
15925 tp->write32 = tg3_write32;
15926 tp->read32_mbox = tg3_read32;
15927 tp->write32_mbox = tg3_write32;
15928 tp->write32_tx_mbox = tg3_write32;
15929 tp->write32_rx_mbox = tg3_write32;
15931 /* Various workaround register access methods */
15932 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
15933 tp->write32 = tg3_write_indirect_reg32;
15934 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
15935 (tg3_flag(tp, PCI_EXPRESS) &&
15936 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
15938 * Back to back register writes can cause problems on these
15939 * chips, the workaround is to read back all reg writes
15940 * except those to mailbox regs.
15942 * See tg3_write_indirect_reg32().
15944 tp->write32 = tg3_write_flush_reg32;
15947 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
15948 tp->write32_tx_mbox = tg3_write32_tx_mbox;
15949 if (tg3_flag(tp, MBOX_WRITE_REORDER))
15950 tp->write32_rx_mbox = tg3_write_flush_reg32;
15953 if (tg3_flag(tp, ICH_WORKAROUND)) {
15954 tp->read32 = tg3_read_indirect_reg32;
15955 tp->write32 = tg3_write_indirect_reg32;
15956 tp->read32_mbox = tg3_read_indirect_mbox;
15957 tp->write32_mbox = tg3_write_indirect_mbox;
15958 tp->write32_tx_mbox = tg3_write_indirect_mbox;
15959 tp->write32_rx_mbox = tg3_write_indirect_mbox;
15964 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
15965 pci_cmd &= ~PCI_COMMAND_MEMORY;
15966 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
15968 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15969 tp->read32_mbox = tg3_read32_mbox_5906;
15970 tp->write32_mbox = tg3_write32_mbox_5906;
15971 tp->write32_tx_mbox = tg3_write32_mbox_5906;
15972 tp->write32_rx_mbox = tg3_write32_mbox_5906;
15975 if (tp->write32 == tg3_write_indirect_reg32 ||
15976 (tg3_flag(tp, PCIX_MODE) &&
15977 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15978 tg3_asic_rev(tp) == ASIC_REV_5701)))
15979 tg3_flag_set(tp, SRAM_USE_CONFIG);
15981 /* The memory arbiter has to be enabled in order for SRAM accesses
15982 * to succeed. Normally on powerup the tg3 chip firmware will make
15983 * sure it is enabled, but other entities such as system netboot
15984 * code might disable it.
15986 val = tr32(MEMARB_MODE);
15987 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
15989 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
15990 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
15991 tg3_flag(tp, 5780_CLASS)) {
15992 if (tg3_flag(tp, PCIX_MODE)) {
15993 pci_read_config_dword(tp->pdev,
15994 tp->pcix_cap + PCI_X_STATUS,
15996 tp->pci_fn = val & 0x7;
15998 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15999 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16000 tg3_asic_rev(tp) == ASIC_REV_5720) {
16001 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16002 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16003 val = tr32(TG3_CPMU_STATUS);
16005 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16006 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16008 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16009 TG3_CPMU_STATUS_FSHFT_5719;
16012 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16013 tp->write32_tx_mbox = tg3_write_flush_reg32;
16014 tp->write32_rx_mbox = tg3_write_flush_reg32;
16017 /* Get eeprom hw config before calling tg3_set_power_state().
16018 * In particular, the TG3_FLAG_IS_NIC flag must be
16019 * determined before calling tg3_set_power_state() so that
16020 * we know whether or not to switch out of Vaux power.
16021 * When the flag is set, it means that GPIO1 is used for eeprom
16022 * write protect and also implies that it is a LOM where GPIOs
16023 * are not used to switch power.
16025 tg3_get_eeprom_hw_cfg(tp);
16027 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16028 tg3_flag_clear(tp, TSO_CAPABLE);
16029 tg3_flag_clear(tp, TSO_BUG);
16030 tp->fw_needed = NULL;
16033 if (tg3_flag(tp, ENABLE_APE)) {
16034 /* Allow reads and writes to the
16035 * APE register and memory space.
16037 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
16038 PCISTATE_ALLOW_APE_SHMEM_WR |
16039 PCISTATE_ALLOW_APE_PSPACE_WR;
16040 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16043 tg3_ape_lock_init(tp);
16046 /* Set up tp->grc_local_ctrl before calling
16047 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16048 * will bring 5700's external PHY out of reset.
16049 * It is also used as eeprom write protect on LOMs.
16051 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16052 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16053 tg3_flag(tp, EEPROM_WRITE_PROT))
16054 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16055 GRC_LCLCTRL_GPIO_OUTPUT1);
16056 /* Unused GPIO3 must be driven as output on 5752 because there
16057 * are no pull-up resistors on unused GPIO pins.
16059 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16060 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16062 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16063 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16064 tg3_flag(tp, 57765_CLASS))
16065 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16067 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16068 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16069 /* Turn off the debug UART. */
16070 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16071 if (tg3_flag(tp, IS_NIC))
16072 /* Keep VMain power. */
16073 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16074 GRC_LCLCTRL_GPIO_OUTPUT0;
16077 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16078 tp->grc_local_ctrl |=
16079 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16081 /* Switch out of Vaux if it is a NIC */
16082 tg3_pwrsrc_switch_to_vmain(tp);
16084 /* Derive initial jumbo mode from MTU assigned in
16085 * ether_setup() via the alloc_etherdev() call
16087 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16088 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16090 /* Determine WakeOnLan speed to use. */
16091 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16092 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16093 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16094 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16095 tg3_flag_clear(tp, WOL_SPEED_100MB);
16097 tg3_flag_set(tp, WOL_SPEED_100MB);
16100 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16101 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16103 /* A few boards don't want Ethernet@WireSpeed phy feature */
16104 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16105 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16106 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16107 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16108 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16109 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16110 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16112 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16113 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16114 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16115 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16116 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16118 if (tg3_flag(tp, 5705_PLUS) &&
16119 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16120 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16121 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16122 !tg3_flag(tp, 57765_PLUS)) {
16123 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16124 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16125 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16126 tg3_asic_rev(tp) == ASIC_REV_5761) {
16127 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16128 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16129 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16130 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16131 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16133 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16136 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16137 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16138 tp->phy_otp = tg3_read_otp_phycfg(tp);
16139 if (tp->phy_otp == 0)
16140 tp->phy_otp = TG3_OTP_DEFAULT;
16143 if (tg3_flag(tp, CPMU_PRESENT))
16144 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16146 tp->mi_mode = MAC_MI_MODE_BASE;
16148 tp->coalesce_mode = 0;
16149 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16150 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16151 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16153 /* Set these bits to enable statistics workaround. */
16154 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16155 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16156 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16157 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16158 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16161 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16162 tg3_asic_rev(tp) == ASIC_REV_57780)
16163 tg3_flag_set(tp, USE_PHYLIB);
16165 err = tg3_mdio_init(tp);
16169 /* Initialize data/descriptor byte/word swapping. */
16170 val = tr32(GRC_MODE);
16171 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16172 tg3_asic_rev(tp) == ASIC_REV_5762)
16173 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16174 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16175 GRC_MODE_B2HRX_ENABLE |
16176 GRC_MODE_HTX2B_ENABLE |
16177 GRC_MODE_HOST_STACKUP);
16179 val &= GRC_MODE_HOST_STACKUP;
16181 tw32(GRC_MODE, val | tp->grc_mode);
16183 tg3_switch_clocks(tp);
16185 /* Clear this out for sanity. */
16186 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16188 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16190 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
16191 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16192 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16193 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16194 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16195 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16196 void __iomem *sram_base;
16198 /* Write some dummy words into the SRAM status block
16199 * area, see if it reads back correctly. If the return
16200 * value is bad, force enable the PCIX workaround.
16202 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16204 writel(0x00000000, sram_base);
16205 writel(0x00000000, sram_base + 4);
16206 writel(0xffffffff, sram_base + 4);
16207 if (readl(sram_base) != 0x00000000)
16208 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16213 tg3_nvram_init(tp);
16215 /* If the device has an NVRAM, no need to load patch firmware */
16216 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16217 !tg3_flag(tp, NO_NVRAM))
16218 tp->fw_needed = NULL;
16220 grc_misc_cfg = tr32(GRC_MISC_CFG);
16221 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16223 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16224 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16225 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
16226 tg3_flag_set(tp, IS_5788);
16228 if (!tg3_flag(tp, IS_5788) &&
16229 tg3_asic_rev(tp) != ASIC_REV_5700)
16230 tg3_flag_set(tp, TAGGED_STATUS);
16231 if (tg3_flag(tp, TAGGED_STATUS)) {
16232 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16233 HOSTCC_MODE_CLRTICK_TXBD);
16235 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16236 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16237 tp->misc_host_ctrl);
16240 /* Preserve the APE MAC_MODE bits */
16241 if (tg3_flag(tp, ENABLE_APE))
16242 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16246 if (tg3_10_100_only_device(tp, ent))
16247 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16249 err = tg3_phy_probe(tp);
16251 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16252 /* ... but do not return immediately ... */
16257 tg3_read_fw_ver(tp);
16259 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16260 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16262 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16263 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16265 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16268 /* 5700 {AX,BX} chips have a broken status block link
16269 * change bit implementation, so we must use the
16270 * status register in those cases.
16272 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16273 tg3_flag_set(tp, USE_LINKCHG_REG);
16275 tg3_flag_clear(tp, USE_LINKCHG_REG);
16277 /* The led_ctrl is set during tg3_phy_probe, here we might
16278 * have to force the link status polling mechanism based
16279 * upon subsystem IDs.
16281 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16282 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16283 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16284 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16285 tg3_flag_set(tp, USE_LINKCHG_REG);
16288 /* For all SERDES we poll the MAC status register. */
16289 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16290 tg3_flag_set(tp, POLL_SERDES);
16292 tg3_flag_clear(tp, POLL_SERDES);
16294 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16295 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16296 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16297 tg3_flag(tp, PCIX_MODE)) {
16298 tp->rx_offset = NET_SKB_PAD;
16299 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16300 tp->rx_copy_thresh = ~(u16)0;
16304 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16305 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
16306 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16308 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
16310 /* Increment the rx prod index on the rx std ring by at most
16311 * 8 for these chips to workaround hw errata.
16313 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16314 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16315 tg3_asic_rev(tp) == ASIC_REV_5755)
16316 tp->rx_std_max_post = 8;
16318 if (tg3_flag(tp, ASPM_WORKAROUND))
16319 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16320 PCIE_PWR_MGMT_L1_THRESH_MSK;
16325 #ifdef CONFIG_SPARC
16326 static int tg3_get_macaddr_sparc(struct tg3 *tp)
16328 struct net_device *dev = tp->dev;
16329 struct pci_dev *pdev = tp->pdev;
16330 struct device_node *dp = pci_device_to_OF_node(pdev);
16331 const unsigned char *addr;
16334 addr = of_get_property(dp, "local-mac-address", &len);
16335 if (addr && len == 6) {
16336 memcpy(dev->dev_addr, addr, 6);
16342 static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
16344 struct net_device *dev = tp->dev;
16346 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
16351 static int tg3_get_device_address(struct tg3 *tp)
16353 struct net_device *dev = tp->dev;
16354 u32 hi, lo, mac_offset;
16358 #ifdef CONFIG_SPARC
16359 if (!tg3_get_macaddr_sparc(tp))
16363 if (tg3_flag(tp, IS_SSB_CORE)) {
16364 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16365 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16370 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16371 tg3_flag(tp, 5780_CLASS)) {
16372 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16374 if (tg3_nvram_lock(tp))
16375 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16377 tg3_nvram_unlock(tp);
16378 } else if (tg3_flag(tp, 5717_PLUS)) {
16379 if (tp->pci_fn & 1)
16381 if (tp->pci_fn > 1)
16382 mac_offset += 0x18c;
16383 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
16386 /* First try to get it from MAC address mailbox. */
16387 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16388 if ((hi >> 16) == 0x484b) {
16389 dev->dev_addr[0] = (hi >> 8) & 0xff;
16390 dev->dev_addr[1] = (hi >> 0) & 0xff;
16392 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16393 dev->dev_addr[2] = (lo >> 24) & 0xff;
16394 dev->dev_addr[3] = (lo >> 16) & 0xff;
16395 dev->dev_addr[4] = (lo >> 8) & 0xff;
16396 dev->dev_addr[5] = (lo >> 0) & 0xff;
16398 /* Some old bootcode may report a 0 MAC address in SRAM */
16399 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16402 /* Next, try NVRAM. */
16403 if (!tg3_flag(tp, NO_NVRAM) &&
16404 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
16405 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
16406 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16407 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
16409 /* Finally just fetch it out of the MAC control regs. */
16411 hi = tr32(MAC_ADDR_0_HIGH);
16412 lo = tr32(MAC_ADDR_0_LOW);
16414 dev->dev_addr[5] = lo & 0xff;
16415 dev->dev_addr[4] = (lo >> 8) & 0xff;
16416 dev->dev_addr[3] = (lo >> 16) & 0xff;
16417 dev->dev_addr[2] = (lo >> 24) & 0xff;
16418 dev->dev_addr[1] = hi & 0xff;
16419 dev->dev_addr[0] = (hi >> 8) & 0xff;
16423 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
16424 #ifdef CONFIG_SPARC
16425 if (!tg3_get_default_macaddr_sparc(tp))
16433 #define BOUNDARY_SINGLE_CACHELINE 1
16434 #define BOUNDARY_MULTI_CACHELINE 2
16436 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
16438 int cacheline_size;
16442 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16444 cacheline_size = 1024;
16446 cacheline_size = (int) byte * 4;
16448 /* On 5703 and later chips, the boundary bits have no
16451 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16452 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16453 !tg3_flag(tp, PCI_EXPRESS))
16456 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16457 goal = BOUNDARY_MULTI_CACHELINE;
16459 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16460 goal = BOUNDARY_SINGLE_CACHELINE;
16466 if (tg3_flag(tp, 57765_PLUS)) {
16467 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
16474 /* PCI controllers on most RISC systems tend to disconnect
16475 * when a device tries to burst across a cache-line boundary.
16476 * Therefore, letting tg3 do so just wastes PCI bandwidth.
16478 * Unfortunately, for PCI-E there are only limited
16479 * write-side controls for this, and thus for reads
16480 * we will still get the disconnects. We'll also waste
16481 * these PCI cycles for both read and write for chips
16482 * other than 5700 and 5701 which do not implement the
16485 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
16486 switch (cacheline_size) {
16491 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16492 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
16493 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
16495 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16496 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16501 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
16502 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
16506 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16507 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16510 } else if (tg3_flag(tp, PCI_EXPRESS)) {
16511 switch (cacheline_size) {
16515 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16516 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16517 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
16523 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16524 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
16528 switch (cacheline_size) {
16530 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16531 val |= (DMA_RWCTRL_READ_BNDRY_16 |
16532 DMA_RWCTRL_WRITE_BNDRY_16);
16537 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16538 val |= (DMA_RWCTRL_READ_BNDRY_32 |
16539 DMA_RWCTRL_WRITE_BNDRY_32);
16544 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16545 val |= (DMA_RWCTRL_READ_BNDRY_64 |
16546 DMA_RWCTRL_WRITE_BNDRY_64);
16551 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16552 val |= (DMA_RWCTRL_READ_BNDRY_128 |
16553 DMA_RWCTRL_WRITE_BNDRY_128);
16558 val |= (DMA_RWCTRL_READ_BNDRY_256 |
16559 DMA_RWCTRL_WRITE_BNDRY_256);
16562 val |= (DMA_RWCTRL_READ_BNDRY_512 |
16563 DMA_RWCTRL_WRITE_BNDRY_512);
16567 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
16568 DMA_RWCTRL_WRITE_BNDRY_1024);
16577 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
16578 int size, int to_device)
16580 struct tg3_internal_buffer_desc test_desc;
16581 u32 sram_dma_descs;
16584 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
16586 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
16587 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
16588 tw32(RDMAC_STATUS, 0);
16589 tw32(WDMAC_STATUS, 0);
16591 tw32(BUFMGR_MODE, 0);
16592 tw32(FTQ_RESET, 0);
16594 test_desc.addr_hi = ((u64) buf_dma) >> 32;
16595 test_desc.addr_lo = buf_dma & 0xffffffff;
16596 test_desc.nic_mbuf = 0x00002100;
16597 test_desc.len = size;
16600 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
16601 * the *second* time the tg3 driver was getting loaded after an
16604 * Broadcom tells me:
16605 * ...the DMA engine is connected to the GRC block and a DMA
16606 * reset may affect the GRC block in some unpredictable way...
16607 * The behavior of resets to individual blocks has not been tested.
16609 * Broadcom noted the GRC reset will also reset all sub-components.
16612 test_desc.cqid_sqid = (13 << 8) | 2;
16614 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
16617 test_desc.cqid_sqid = (16 << 8) | 7;
16619 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
16622 test_desc.flags = 0x00000005;
16624 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
16627 val = *(((u32 *)&test_desc) + i);
16628 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
16629 sram_dma_descs + (i * sizeof(u32)));
16630 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
16632 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
16635 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
16637 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
16640 for (i = 0; i < 40; i++) {
16644 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
16646 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
16647 if ((val & 0xffff) == sram_dma_descs) {
16658 #define TEST_BUFFER_SIZE 0x2000
16660 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
16661 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
16665 static int tg3_test_dma(struct tg3 *tp)
16667 dma_addr_t buf_dma;
16668 u32 *buf, saved_dma_rwctrl;
16671 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
16672 &buf_dma, GFP_KERNEL);
16678 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
16679 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
16681 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
16683 if (tg3_flag(tp, 57765_PLUS))
16686 if (tg3_flag(tp, PCI_EXPRESS)) {
16687 /* DMA read watermark not used on PCIE */
16688 tp->dma_rwctrl |= 0x00180000;
16689 } else if (!tg3_flag(tp, PCIX_MODE)) {
16690 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16691 tg3_asic_rev(tp) == ASIC_REV_5750)
16692 tp->dma_rwctrl |= 0x003f0000;
16694 tp->dma_rwctrl |= 0x003f000f;
16696 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
16697 tg3_asic_rev(tp) == ASIC_REV_5704) {
16698 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
16699 u32 read_water = 0x7;
16701 /* If the 5704 is behind the EPB bridge, we can
16702 * do the less restrictive ONE_DMA workaround for
16703 * better performance.
16705 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
16706 tg3_asic_rev(tp) == ASIC_REV_5704)
16707 tp->dma_rwctrl |= 0x8000;
16708 else if (ccval == 0x6 || ccval == 0x7)
16709 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
16711 if (tg3_asic_rev(tp) == ASIC_REV_5703)
16713 /* Set bit 23 to enable PCIX hw bug fix */
16715 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
16716 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
16718 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
16719 /* 5780 always in PCIX mode */
16720 tp->dma_rwctrl |= 0x00144000;
16721 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
16722 /* 5714 always in PCIX mode */
16723 tp->dma_rwctrl |= 0x00148000;
16725 tp->dma_rwctrl |= 0x001b000f;
16728 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
16729 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
16731 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
16732 tg3_asic_rev(tp) == ASIC_REV_5704)
16733 tp->dma_rwctrl &= 0xfffffff0;
16735 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16736 tg3_asic_rev(tp) == ASIC_REV_5701) {
16737 /* Remove this if it causes problems for some boards. */
16738 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
16740 /* On 5700/5701 chips, we need to set this bit.
16741 * Otherwise the chip will issue cacheline transactions
16742 * to streamable DMA memory with not all the byte
16743 * enables turned on. This is an error on several
16744 * RISC PCI controllers, in particular sparc64.
16746 * On 5703/5704 chips, this bit has been reassigned
16747 * a different meaning. In particular, it is used
16748 * on those chips to enable a PCI-X workaround.
16750 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
16753 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
16756 /* Unneeded, already done by tg3_get_invariants. */
16757 tg3_switch_clocks(tp);
16760 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16761 tg3_asic_rev(tp) != ASIC_REV_5701)
16764 /* It is best to perform DMA test with maximum write burst size
16765 * to expose the 5700/5701 write DMA bug.
16767 saved_dma_rwctrl = tp->dma_rwctrl;
16768 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
16769 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
16774 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
16777 /* Send the buffer to the chip. */
16778 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
16780 dev_err(&tp->pdev->dev,
16781 "%s: Buffer write failed. err = %d\n",
16787 /* validate data reached card RAM correctly. */
16788 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
16790 tg3_read_mem(tp, 0x2100 + (i*4), &val);
16791 if (le32_to_cpu(val) != p[i]) {
16792 dev_err(&tp->pdev->dev,
16793 "%s: Buffer corrupted on device! "
16794 "(%d != %d)\n", __func__, val, i);
16795 /* ret = -ENODEV here? */
16800 /* Now read it back. */
16801 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
16803 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
16804 "err = %d\n", __func__, ret);
16809 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
16813 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
16814 DMA_RWCTRL_WRITE_BNDRY_16) {
16815 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
16816 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
16817 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
16820 dev_err(&tp->pdev->dev,
16821 "%s: Buffer corrupted on read back! "
16822 "(%d != %d)\n", __func__, p[i], i);
16828 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
16834 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
16835 DMA_RWCTRL_WRITE_BNDRY_16) {
16836 /* DMA test passed without adjusting DMA boundary,
16837 * now look for chipsets that are known to expose the
16838 * DMA bug without failing the test.
16840 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
16841 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
16842 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
16844 /* Safe to use the calculated DMA boundary. */
16845 tp->dma_rwctrl = saved_dma_rwctrl;
16848 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
16852 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
16857 static void tg3_init_bufmgr_config(struct tg3 *tp)
16859 if (tg3_flag(tp, 57765_PLUS)) {
16860 tp->bufmgr_config.mbuf_read_dma_low_water =
16861 DEFAULT_MB_RDMA_LOW_WATER_5705;
16862 tp->bufmgr_config.mbuf_mac_rx_low_water =
16863 DEFAULT_MB_MACRX_LOW_WATER_57765;
16864 tp->bufmgr_config.mbuf_high_water =
16865 DEFAULT_MB_HIGH_WATER_57765;
16867 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
16868 DEFAULT_MB_RDMA_LOW_WATER_5705;
16869 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
16870 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
16871 tp->bufmgr_config.mbuf_high_water_jumbo =
16872 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
16873 } else if (tg3_flag(tp, 5705_PLUS)) {
16874 tp->bufmgr_config.mbuf_read_dma_low_water =
16875 DEFAULT_MB_RDMA_LOW_WATER_5705;
16876 tp->bufmgr_config.mbuf_mac_rx_low_water =
16877 DEFAULT_MB_MACRX_LOW_WATER_5705;
16878 tp->bufmgr_config.mbuf_high_water =
16879 DEFAULT_MB_HIGH_WATER_5705;
16880 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16881 tp->bufmgr_config.mbuf_mac_rx_low_water =
16882 DEFAULT_MB_MACRX_LOW_WATER_5906;
16883 tp->bufmgr_config.mbuf_high_water =
16884 DEFAULT_MB_HIGH_WATER_5906;
16887 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
16888 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
16889 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
16890 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
16891 tp->bufmgr_config.mbuf_high_water_jumbo =
16892 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
16894 tp->bufmgr_config.mbuf_read_dma_low_water =
16895 DEFAULT_MB_RDMA_LOW_WATER;
16896 tp->bufmgr_config.mbuf_mac_rx_low_water =
16897 DEFAULT_MB_MACRX_LOW_WATER;
16898 tp->bufmgr_config.mbuf_high_water =
16899 DEFAULT_MB_HIGH_WATER;
16901 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
16902 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
16903 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
16904 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
16905 tp->bufmgr_config.mbuf_high_water_jumbo =
16906 DEFAULT_MB_HIGH_WATER_JUMBO;
16909 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
16910 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
16913 static char *tg3_phy_string(struct tg3 *tp)
16915 switch (tp->phy_id & TG3_PHY_ID_MASK) {
16916 case TG3_PHY_ID_BCM5400: return "5400";
16917 case TG3_PHY_ID_BCM5401: return "5401";
16918 case TG3_PHY_ID_BCM5411: return "5411";
16919 case TG3_PHY_ID_BCM5701: return "5701";
16920 case TG3_PHY_ID_BCM5703: return "5703";
16921 case TG3_PHY_ID_BCM5704: return "5704";
16922 case TG3_PHY_ID_BCM5705: return "5705";
16923 case TG3_PHY_ID_BCM5750: return "5750";
16924 case TG3_PHY_ID_BCM5752: return "5752";
16925 case TG3_PHY_ID_BCM5714: return "5714";
16926 case TG3_PHY_ID_BCM5780: return "5780";
16927 case TG3_PHY_ID_BCM5755: return "5755";
16928 case TG3_PHY_ID_BCM5787: return "5787";
16929 case TG3_PHY_ID_BCM5784: return "5784";
16930 case TG3_PHY_ID_BCM5756: return "5722/5756";
16931 case TG3_PHY_ID_BCM5906: return "5906";
16932 case TG3_PHY_ID_BCM5761: return "5761";
16933 case TG3_PHY_ID_BCM5718C: return "5718C";
16934 case TG3_PHY_ID_BCM5718S: return "5718S";
16935 case TG3_PHY_ID_BCM57765: return "57765";
16936 case TG3_PHY_ID_BCM5719C: return "5719C";
16937 case TG3_PHY_ID_BCM5720C: return "5720C";
16938 case TG3_PHY_ID_BCM5762: return "5762C";
16939 case TG3_PHY_ID_BCM8002: return "8002/serdes";
16940 case 0: return "serdes";
16941 default: return "unknown";
16945 static char *tg3_bus_string(struct tg3 *tp, char *str)
16947 if (tg3_flag(tp, PCI_EXPRESS)) {
16948 strcpy(str, "PCI Express");
16950 } else if (tg3_flag(tp, PCIX_MODE)) {
16951 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
16953 strcpy(str, "PCIX:");
16955 if ((clock_ctrl == 7) ||
16956 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
16957 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
16958 strcat(str, "133MHz");
16959 else if (clock_ctrl == 0)
16960 strcat(str, "33MHz");
16961 else if (clock_ctrl == 2)
16962 strcat(str, "50MHz");
16963 else if (clock_ctrl == 4)
16964 strcat(str, "66MHz");
16965 else if (clock_ctrl == 6)
16966 strcat(str, "100MHz");
16968 strcpy(str, "PCI:");
16969 if (tg3_flag(tp, PCI_HIGH_SPEED))
16970 strcat(str, "66MHz");
16972 strcat(str, "33MHz");
16974 if (tg3_flag(tp, PCI_32BIT))
16975 strcat(str, ":32-bit");
16977 strcat(str, ":64-bit");
16981 static void tg3_init_coal(struct tg3 *tp)
16983 struct ethtool_coalesce *ec = &tp->coal;
16985 memset(ec, 0, sizeof(*ec));
16986 ec->cmd = ETHTOOL_GCOALESCE;
16987 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
16988 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
16989 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
16990 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
16991 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
16992 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
16993 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
16994 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
16995 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
16997 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
16998 HOSTCC_MODE_CLRTICK_TXBD)) {
16999 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17000 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17001 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17002 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17005 if (tg3_flag(tp, 5705_PLUS)) {
17006 ec->rx_coalesce_usecs_irq = 0;
17007 ec->tx_coalesce_usecs_irq = 0;
17008 ec->stats_block_coalesce_usecs = 0;
17012 static int tg3_init_one(struct pci_dev *pdev,
17013 const struct pci_device_id *ent)
17015 struct net_device *dev;
17017 int i, err, pm_cap;
17018 u32 sndmbx, rcvmbx, intmbx;
17020 u64 dma_mask, persist_dma_mask;
17021 netdev_features_t features = 0;
17023 printk_once(KERN_INFO "%s\n", version);
17025 err = pci_enable_device(pdev);
17027 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
17031 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17033 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
17034 goto err_out_disable_pdev;
17037 pci_set_master(pdev);
17039 /* Find power-management capability. */
17040 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
17042 dev_err(&pdev->dev,
17043 "Cannot find Power Management capability, aborting\n");
17045 goto err_out_free_res;
17048 err = pci_set_power_state(pdev, PCI_D0);
17050 dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
17051 goto err_out_free_res;
17054 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17057 goto err_out_power_down;
17060 SET_NETDEV_DEV(dev, &pdev->dev);
17062 tp = netdev_priv(dev);
17065 tp->pm_cap = pm_cap;
17066 tp->rx_mode = TG3_DEF_RX_MODE;
17067 tp->tx_mode = TG3_DEF_TX_MODE;
17071 tp->msg_enable = tg3_debug;
17073 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17075 if (pdev_is_ssb_gige_core(pdev)) {
17076 tg3_flag_set(tp, IS_SSB_CORE);
17077 if (ssb_gige_must_flush_posted_writes(pdev))
17078 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17079 if (ssb_gige_one_dma_at_once(pdev))
17080 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17081 if (ssb_gige_have_roboswitch(pdev))
17082 tg3_flag_set(tp, ROBOSWITCH);
17083 if (ssb_gige_is_rgmii(pdev))
17084 tg3_flag_set(tp, RGMII_MODE);
17087 /* The word/byte swap controls here control register access byte
17088 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17091 tp->misc_host_ctrl =
17092 MISC_HOST_CTRL_MASK_PCI_INT |
17093 MISC_HOST_CTRL_WORD_SWAP |
17094 MISC_HOST_CTRL_INDIR_ACCESS |
17095 MISC_HOST_CTRL_PCISTATE_RW;
17097 /* The NONFRM (non-frame) byte/word swap controls take effect
17098 * on descriptor entries, anything which isn't packet data.
17100 * The StrongARM chips on the board (one for tx, one for rx)
17101 * are running in big-endian mode.
17103 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17104 GRC_MODE_WSWAP_NONFRM_DATA);
17105 #ifdef __BIG_ENDIAN
17106 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17108 spin_lock_init(&tp->lock);
17109 spin_lock_init(&tp->indirect_lock);
17110 INIT_WORK(&tp->reset_task, tg3_reset_task);
17112 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17114 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
17116 goto err_out_free_dev;
17119 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17120 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17121 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17122 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17123 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17124 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17125 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17126 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17127 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17128 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17129 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17130 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727) {
17131 tg3_flag_set(tp, ENABLE_APE);
17132 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17133 if (!tp->aperegs) {
17134 dev_err(&pdev->dev,
17135 "Cannot map APE registers, aborting\n");
17137 goto err_out_iounmap;
17141 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17142 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17144 dev->ethtool_ops = &tg3_ethtool_ops;
17145 dev->watchdog_timeo = TG3_TX_TIMEOUT;
17146 dev->netdev_ops = &tg3_netdev_ops;
17147 dev->irq = pdev->irq;
17149 err = tg3_get_invariants(tp, ent);
17151 dev_err(&pdev->dev,
17152 "Problem fetching invariants of chip, aborting\n");
17153 goto err_out_apeunmap;
17156 /* The EPB bridge inside 5714, 5715, and 5780 and any
17157 * device behind the EPB cannot support DMA addresses > 40-bit.
17158 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17159 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17160 * do DMA address check in tg3_start_xmit().
17162 if (tg3_flag(tp, IS_5788))
17163 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
17164 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17165 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
17166 #ifdef CONFIG_HIGHMEM
17167 dma_mask = DMA_BIT_MASK(64);
17170 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
17172 /* Configure DMA attributes. */
17173 if (dma_mask > DMA_BIT_MASK(32)) {
17174 err = pci_set_dma_mask(pdev, dma_mask);
17176 features |= NETIF_F_HIGHDMA;
17177 err = pci_set_consistent_dma_mask(pdev,
17180 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17181 "DMA for consistent allocations\n");
17182 goto err_out_apeunmap;
17186 if (err || dma_mask == DMA_BIT_MASK(32)) {
17187 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
17189 dev_err(&pdev->dev,
17190 "No usable DMA configuration, aborting\n");
17191 goto err_out_apeunmap;
17195 tg3_init_bufmgr_config(tp);
17197 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
17199 /* 5700 B0 chips do not support checksumming correctly due
17200 * to hardware bugs.
17202 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17203 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17205 if (tg3_flag(tp, 5755_PLUS))
17206 features |= NETIF_F_IPV6_CSUM;
17209 /* TSO is on by default on chips that support hardware TSO.
17210 * Firmware TSO on older chips gives lower performance, so it
17211 * is off by default, but can be enabled using ethtool.
17213 if ((tg3_flag(tp, HW_TSO_1) ||
17214 tg3_flag(tp, HW_TSO_2) ||
17215 tg3_flag(tp, HW_TSO_3)) &&
17216 (features & NETIF_F_IP_CSUM))
17217 features |= NETIF_F_TSO;
17218 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17219 if (features & NETIF_F_IPV6_CSUM)
17220 features |= NETIF_F_TSO6;
17221 if (tg3_flag(tp, HW_TSO_3) ||
17222 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17223 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17224 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17225 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17226 tg3_asic_rev(tp) == ASIC_REV_57780)
17227 features |= NETIF_F_TSO_ECN;
17230 dev->features |= features;
17231 dev->vlan_features |= features;
17234 * Add loopback capability only for a subset of devices that support
17235 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17236 * loopback for the remaining devices.
17238 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17239 !tg3_flag(tp, CPMU_PRESENT))
17240 /* Add the loopback capability */
17241 features |= NETIF_F_LOOPBACK;
17243 dev->hw_features |= features;
17245 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17246 !tg3_flag(tp, TSO_CAPABLE) &&
17247 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17248 tg3_flag_set(tp, MAX_RXPEND_64);
17249 tp->rx_pending = 63;
17252 err = tg3_get_device_address(tp);
17254 dev_err(&pdev->dev,
17255 "Could not obtain valid ethernet address, aborting\n");
17256 goto err_out_apeunmap;
17260 * Reset chip in case UNDI or EFI driver did not shutdown
17261 * DMA self test will enable WDMAC and we'll see (spurious)
17262 * pending DMA on the PCI bus at that point.
17264 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17265 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
17266 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
17267 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17270 err = tg3_test_dma(tp);
17272 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
17273 goto err_out_apeunmap;
17276 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17277 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17278 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
17279 for (i = 0; i < tp->irq_max; i++) {
17280 struct tg3_napi *tnapi = &tp->napi[i];
17283 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17285 tnapi->int_mbox = intmbx;
17291 tnapi->consmbox = rcvmbx;
17292 tnapi->prodmbox = sndmbx;
17295 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
17297 tnapi->coal_now = HOSTCC_MODE_NOW;
17299 if (!tg3_flag(tp, SUPPORT_MSIX))
17303 * If we support MSIX, we'll be using RSS. If we're using
17304 * RSS, the first vector only handles link interrupts and the
17305 * remaining vectors handle rx and tx interrupts. Reuse the
17306 * mailbox values for the next iteration. The values we setup
17307 * above are still useful for the single vectored mode.
17322 pci_set_drvdata(pdev, dev);
17324 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17325 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17326 tg3_asic_rev(tp) == ASIC_REV_5762)
17327 tg3_flag_set(tp, PTP_CAPABLE);
17329 if (tg3_flag(tp, 5717_PLUS)) {
17330 /* Resume a low-power mode */
17331 tg3_frob_aux_power(tp, false);
17334 tg3_timer_init(tp);
17336 tg3_carrier_off(tp);
17338 err = register_netdev(dev);
17340 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
17341 goto err_out_apeunmap;
17344 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17345 tp->board_part_number,
17346 tg3_chip_rev_id(tp),
17347 tg3_bus_string(tp, str),
17350 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
17351 struct phy_device *phydev;
17352 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
17354 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
17355 phydev->drv->name, dev_name(&phydev->dev));
17359 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17360 ethtype = "10/100Base-TX";
17361 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17362 ethtype = "1000Base-SX";
17364 ethtype = "10/100/1000Base-T";
17366 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
17367 "(WireSpeed[%d], EEE[%d])\n",
17368 tg3_phy_string(tp), ethtype,
17369 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17370 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
17373 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
17374 (dev->features & NETIF_F_RXCSUM) != 0,
17375 tg3_flag(tp, USE_LINKCHG_REG) != 0,
17376 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
17377 tg3_flag(tp, ENABLE_ASF) != 0,
17378 tg3_flag(tp, TSO_CAPABLE) != 0);
17379 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17381 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17382 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
17384 pci_save_state(pdev);
17390 iounmap(tp->aperegs);
17391 tp->aperegs = NULL;
17403 err_out_power_down:
17404 pci_set_power_state(pdev, PCI_D3hot);
17407 pci_release_regions(pdev);
17409 err_out_disable_pdev:
17410 pci_disable_device(pdev);
17411 pci_set_drvdata(pdev, NULL);
17415 static void tg3_remove_one(struct pci_dev *pdev)
17417 struct net_device *dev = pci_get_drvdata(pdev);
17420 struct tg3 *tp = netdev_priv(dev);
17422 release_firmware(tp->fw);
17424 tg3_reset_task_cancel(tp);
17426 if (tg3_flag(tp, USE_PHYLIB)) {
17431 unregister_netdev(dev);
17433 iounmap(tp->aperegs);
17434 tp->aperegs = NULL;
17441 pci_release_regions(pdev);
17442 pci_disable_device(pdev);
17443 pci_set_drvdata(pdev, NULL);
17447 #ifdef CONFIG_PM_SLEEP
17448 static int tg3_suspend(struct device *device)
17450 struct pci_dev *pdev = to_pci_dev(device);
17451 struct net_device *dev = pci_get_drvdata(pdev);
17452 struct tg3 *tp = netdev_priv(dev);
17455 if (!netif_running(dev))
17458 tg3_reset_task_cancel(tp);
17460 tg3_netif_stop(tp);
17462 tg3_timer_stop(tp);
17464 tg3_full_lock(tp, 1);
17465 tg3_disable_ints(tp);
17466 tg3_full_unlock(tp);
17468 netif_device_detach(dev);
17470 tg3_full_lock(tp, 0);
17471 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17472 tg3_flag_clear(tp, INIT_COMPLETE);
17473 tg3_full_unlock(tp);
17475 err = tg3_power_down_prepare(tp);
17479 tg3_full_lock(tp, 0);
17481 tg3_flag_set(tp, INIT_COMPLETE);
17482 err2 = tg3_restart_hw(tp, 1);
17486 tg3_timer_start(tp);
17488 netif_device_attach(dev);
17489 tg3_netif_start(tp);
17492 tg3_full_unlock(tp);
17501 static int tg3_resume(struct device *device)
17503 struct pci_dev *pdev = to_pci_dev(device);
17504 struct net_device *dev = pci_get_drvdata(pdev);
17505 struct tg3 *tp = netdev_priv(dev);
17508 if (!netif_running(dev))
17511 netif_device_attach(dev);
17513 tg3_full_lock(tp, 0);
17515 tg3_flag_set(tp, INIT_COMPLETE);
17516 err = tg3_restart_hw(tp,
17517 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
17521 tg3_timer_start(tp);
17523 tg3_netif_start(tp);
17526 tg3_full_unlock(tp);
17534 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
17535 #define TG3_PM_OPS (&tg3_pm_ops)
17539 #define TG3_PM_OPS NULL
17541 #endif /* CONFIG_PM_SLEEP */
17544 * tg3_io_error_detected - called when PCI error is detected
17545 * @pdev: Pointer to PCI device
17546 * @state: The current pci connection state
17548 * This function is called after a PCI bus error affecting
17549 * this device has been detected.
17551 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
17552 pci_channel_state_t state)
17554 struct net_device *netdev = pci_get_drvdata(pdev);
17555 struct tg3 *tp = netdev_priv(netdev);
17556 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
17558 netdev_info(netdev, "PCI I/O error detected\n");
17562 if (!netif_running(netdev))
17567 tg3_netif_stop(tp);
17569 tg3_timer_stop(tp);
17571 /* Want to make sure that the reset task doesn't run */
17572 tg3_reset_task_cancel(tp);
17574 netif_device_detach(netdev);
17576 /* Clean up software state, even if MMIO is blocked */
17577 tg3_full_lock(tp, 0);
17578 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
17579 tg3_full_unlock(tp);
17582 if (state == pci_channel_io_perm_failure)
17583 err = PCI_ERS_RESULT_DISCONNECT;
17585 pci_disable_device(pdev);
17593 * tg3_io_slot_reset - called after the pci bus has been reset.
17594 * @pdev: Pointer to PCI device
17596 * Restart the card from scratch, as if from a cold-boot.
17597 * At this point, the card has exprienced a hard reset,
17598 * followed by fixups by BIOS, and has its config space
17599 * set up identically to what it was at cold boot.
17601 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
17603 struct net_device *netdev = pci_get_drvdata(pdev);
17604 struct tg3 *tp = netdev_priv(netdev);
17605 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
17610 if (pci_enable_device(pdev)) {
17611 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
17615 pci_set_master(pdev);
17616 pci_restore_state(pdev);
17617 pci_save_state(pdev);
17619 if (!netif_running(netdev)) {
17620 rc = PCI_ERS_RESULT_RECOVERED;
17624 err = tg3_power_up(tp);
17628 rc = PCI_ERS_RESULT_RECOVERED;
17637 * tg3_io_resume - called when traffic can start flowing again.
17638 * @pdev: Pointer to PCI device
17640 * This callback is called when the error recovery driver tells
17641 * us that its OK to resume normal operation.
17643 static void tg3_io_resume(struct pci_dev *pdev)
17645 struct net_device *netdev = pci_get_drvdata(pdev);
17646 struct tg3 *tp = netdev_priv(netdev);
17651 if (!netif_running(netdev))
17654 tg3_full_lock(tp, 0);
17655 tg3_flag_set(tp, INIT_COMPLETE);
17656 err = tg3_restart_hw(tp, 1);
17658 tg3_full_unlock(tp);
17659 netdev_err(netdev, "Cannot restart hardware after reset.\n");
17663 netif_device_attach(netdev);
17665 tg3_timer_start(tp);
17667 tg3_netif_start(tp);
17669 tg3_full_unlock(tp);
17677 static const struct pci_error_handlers tg3_err_handler = {
17678 .error_detected = tg3_io_error_detected,
17679 .slot_reset = tg3_io_slot_reset,
17680 .resume = tg3_io_resume
17683 static struct pci_driver tg3_driver = {
17684 .name = DRV_MODULE_NAME,
17685 .id_table = tg3_pci_tbl,
17686 .probe = tg3_init_one,
17687 .remove = tg3_remove_one,
17688 .err_handler = &tg3_err_handler,
17689 .driver.pm = TG3_PM_OPS,
17692 static int __init tg3_init(void)
17694 return pci_register_driver(&tg3_driver);
17697 static void __exit tg3_cleanup(void)
17699 pci_unregister_driver(&tg3_driver);
17702 module_init(tg3_init);
17703 module_exit(tg3_cleanup);