drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c

   1 /*
   2  * Linux network driver for Brocade Converged Network Adapter.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License (GPL) Version 2 as
   6  * published by the Free Software Foundation
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  */
  13 /*
  14  * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
  15  * All rights reserved
  16  * www.brocade.com
  17  */
  18
  19 #include "bfa_ioc.h"
  20 #include "cna.h"
  21 #include "bfi.h"
  22 #include "bfi_reg.h"
  23 #include "bfa_defs.h"
  24
  25 #define bfa_ioc_ct_sync_pos(__ioc)      \
  26                 ((u32) (1 << bfa_ioc_pcifn(__ioc)))
  27 #define BFA_IOC_SYNC_REQD_SH            16
  28 #define bfa_ioc_ct_get_sync_ackd(__val) (__val & 0x0000ffff)
  29 #define bfa_ioc_ct_clear_sync_ackd(__val) (__val & 0xffff0000)
  30 #define bfa_ioc_ct_get_sync_reqd(__val) (__val >> BFA_IOC_SYNC_REQD_SH)
  31 #define bfa_ioc_ct_sync_reqd_pos(__ioc) \
  32                 (bfa_ioc_ct_sync_pos(__ioc) << BFA_IOC_SYNC_REQD_SH)
  33
  34 /*
  35  * forward declarations
  36  */
  37 static bool bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc);
  38 static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc);
  39 static void bfa_ioc_ct_reg_init(struct bfa_ioc *ioc);
  40 static void bfa_ioc_ct_map_port(struct bfa_ioc *ioc);
  41 static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix);
  42 static void bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc);
  43 static void bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc);
  44 static bool bfa_ioc_ct_sync_start(struct bfa_ioc *ioc);
  45 static void bfa_ioc_ct_sync_join(struct bfa_ioc *ioc);
  46 static void bfa_ioc_ct_sync_leave(struct bfa_ioc *ioc);
  47 static void bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc);
  48 static bool bfa_ioc_ct_sync_complete(struct bfa_ioc *ioc);
  49 static enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb,
  50                                 enum bfi_asic_mode asic_mode);
  51
  52 static struct bfa_ioc_hwif nw_hwif_ct;
  53
  54 static void
  55 bfa_ioc_set_ctx_hwif(struct bfa_ioc *ioc, struct bfa_ioc_hwif *hwif)
  56 {
  57         hwif->ioc_firmware_lock = bfa_ioc_ct_firmware_lock;
  58         hwif->ioc_firmware_unlock = bfa_ioc_ct_firmware_unlock;
  59         hwif->ioc_notify_fail = bfa_ioc_ct_notify_fail;
  60         hwif->ioc_ownership_reset = bfa_ioc_ct_ownership_reset;
  61         hwif->ioc_sync_start = bfa_ioc_ct_sync_start;
  62         hwif->ioc_sync_join = bfa_ioc_ct_sync_join;
  63         hwif->ioc_sync_leave = bfa_ioc_ct_sync_leave;
  64         hwif->ioc_sync_ack = bfa_ioc_ct_sync_ack;
  65         hwif->ioc_sync_complete = bfa_ioc_ct_sync_complete;
  66 }
  67
  68 /**
  69  * Called from bfa_ioc_attach() to map asic specific calls.
  70  */
  71 void
  72 bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc)
  73 {
  74         bfa_ioc_set_ctx_hwif(ioc, &nw_hwif_ct);
  75
  76         nw_hwif_ct.ioc_pll_init = bfa_ioc_ct_pll_init;
  77         nw_hwif_ct.ioc_reg_init = bfa_ioc_ct_reg_init;
  78         nw_hwif_ct.ioc_map_port = bfa_ioc_ct_map_port;
  79         nw_hwif_ct.ioc_isr_mode_set = bfa_ioc_ct_isr_mode_set;
  80         ioc->ioc_hwif = &nw_hwif_ct;
  81 }
  82
  83 /**
  84  * Return true if firmware of current driver matches the running firmware.
  85  */
  86 static bool
  87 bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc)
  88 {
  89         enum bfi_ioc_state ioc_fwstate;
  90         u32 usecnt;
  91         struct bfi_ioc_image_hdr fwhdr;
  92
  93         /**
  94          * If bios boot (flash based) -- do not increment usage count
  95          */
  96         if (bfa_cb_image_get_size(bfa_ioc_asic_gen(ioc)) <
  97                                                 BFA_IOC_FWIMG_MINSZ)
  98                 return true;
  99
 100         bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
 101         usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
 102
 103         /**
 104          * If usage count is 0, always return TRUE.
 105          */
 106         if (usecnt == 0) {
 107                 writel(1, ioc->ioc_regs.ioc_usage_reg);
 108                 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
 109                 writel(0, ioc->ioc_regs.ioc_fail_sync);
 110                 return true;
 111         }
 112
 113         ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate);
 114
 115         /**
 116          * Use count cannot be non-zero and chip in uninitialized state.
 117          */
 118         BUG_ON(!(ioc_fwstate != BFI_IOC_UNINIT));
 119
 120         /**
 121          * Check if another driver with a different firmware is active
 122          */
 123         bfa_nw_ioc_fwver_get(ioc, &fwhdr);
 124         if (!bfa_nw_ioc_fwver_cmp(ioc, &fwhdr)) {
 125                 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
 126                 return false;
 127         }
 128
 129         /**
 130          * Same firmware version. Increment the reference count.
 131          */
 132         usecnt++;
 133         writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
 134         bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
 135         return true;
 136 }
 137
 138 static void
 139 bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc)
 140 {
 141         u32 usecnt;
 142
 143         /**
 144          * If bios boot (flash based) -- do not decrement usage count
 145          */
 146         if (bfa_cb_image_get_size(bfa_ioc_asic_gen(ioc)) <
 147                                                 BFA_IOC_FWIMG_MINSZ)
 148                 return;
 149
 150         /**
 151          * decrement usage count
 152          */
 153         bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
 154         usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
 155         BUG_ON(!(usecnt > 0));
 156
 157         usecnt--;
 158         writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
 159
 160         bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
 161 }
 162
 163 /**
 164  * Notify other functions on HB failure.
 165  */
 166 static void
 167 bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc)
 168 {
 169         writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt);
 170         writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt);
 171         /* Wait for halt to take effect */
 172         readl(ioc->ioc_regs.ll_halt);
 173         readl(ioc->ioc_regs.alt_ll_halt);
 174 }
 175
 176 /**
 177  * Host to LPU mailbox message addresses
 178  */
 179 static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } ct_fnreg[] = {
 180         { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
 181         { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 },
 182         { HOSTFN2_LPU_MBOX0_0, LPU_HOSTFN2_MBOX0_0, HOST_PAGE_NUM_FN2 },
 183         { HOSTFN3_LPU_MBOX0_8, LPU_HOSTFN3_MBOX0_8, HOST_PAGE_NUM_FN3 }
 184 };
 185
 186 /**
 187  * Host <-> LPU mailbox command/status registers - port 0
 188  */
 189 static struct { u32 hfn, lpu; } ct_p0reg[] = {
 190         { HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT },
 191         { HOSTFN1_LPU0_CMD_STAT, LPU0_HOSTFN1_CMD_STAT },
 192         { HOSTFN2_LPU0_CMD_STAT, LPU0_HOSTFN2_CMD_STAT },
 193         { HOSTFN3_LPU0_CMD_STAT, LPU0_HOSTFN3_CMD_STAT }
 194 };
 195
 196 /**
 197  * Host <-> LPU mailbox command/status registers - port 1
 198  */
 199 static struct { u32 hfn, lpu; } ct_p1reg[] = {
 200         { HOSTFN0_LPU1_CMD_STAT, LPU1_HOSTFN0_CMD_STAT },
 201         { HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT },
 202         { HOSTFN2_LPU1_CMD_STAT, LPU1_HOSTFN2_CMD_STAT },
 203         { HOSTFN3_LPU1_CMD_STAT, LPU1_HOSTFN3_CMD_STAT }
 204 };
 205
 206 static void
 207 bfa_ioc_ct_reg_init(struct bfa_ioc *ioc)
 208 {
 209         void __iomem *rb;
 210         int             pcifn = bfa_ioc_pcifn(ioc);
 211
 212         rb = bfa_ioc_bar0(ioc);
 213
 214         ioc->ioc_regs.hfn_mbox = rb + ct_fnreg[pcifn].hfn_mbox;
 215         ioc->ioc_regs.lpu_mbox = rb + ct_fnreg[pcifn].lpu_mbox;
 216         ioc->ioc_regs.host_page_num_fn = rb + ct_fnreg[pcifn].hfn_pgn;
 217
 218         if (ioc->port_id == 0) {
 219                 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
 220                 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
 221                 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
 222                 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p0reg[pcifn].hfn;
 223                 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p0reg[pcifn].lpu;
 224                 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
 225                 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;
 226         } else {
 227                 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
 228                 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
 229                 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG;
 230                 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p1reg[pcifn].hfn;
 231                 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p1reg[pcifn].lpu;
 232                 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
 233                 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0;
 234         }
 235
 236         /*
 237          * PSS control registers
 238          */
 239         ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
 240         ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
 241         ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG);
 242         ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG);
 243
 244         /*
 245          * IOC semaphore registers and serialization
 246          */
 247         ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
 248         ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG);
 249         ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
 250         ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT);
 251         ioc->ioc_regs.ioc_fail_sync = (rb + BFA_IOC_FAIL_SYNC);
 252
 253         /**
 254          * sram memory access
 255          */
 256         ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
 257         ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT;
 258
 259         /*
 260          * err set reg : for notification of hb failure in fcmode
 261          */
 262         ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
 263 }
 264
 265 /**
 266  * Initialize IOC to port mapping.
 267  */
 268
 269 #define FNC_PERS_FN_SHIFT(__fn) ((__fn) * 8)
 270 static void
 271 bfa_ioc_ct_map_port(struct bfa_ioc *ioc)
 272 {
 273         void __iomem *rb = ioc->pcidev.pci_bar_kva;
 274         u32     r32;
 275
 276         /**
 277          * For catapult, base port id on personality register and IOC type
 278          */
 279         r32 = readl(rb + FNC_PERS_REG);
 280         r32 >>= FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc));
 281         ioc->port_id = (r32 & __F0_PORT_MAP_MK) >> __F0_PORT_MAP_SH;
 282
 283 }
 284
 285 /**
 286  * Set interrupt mode for a function: INTX or MSIX
 287  */
 288 static void
 289 bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix)
 290 {
 291         void __iomem *rb = ioc->pcidev.pci_bar_kva;
 292         u32     r32, mode;
 293
 294         r32 = readl(rb + FNC_PERS_REG);
 295
 296         mode = (r32 >> FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))) &
 297                 __F0_INTX_STATUS;
 298
 299         /**
 300          * If already in desired mode, do not change anything
 301          */
 302         if ((!msix && mode) || (msix && !mode))
 303                 return;
 304
 305         if (msix)
 306                 mode = __F0_INTX_STATUS_MSIX;
 307         else
 308                 mode = __F0_INTX_STATUS_INTA;
 309
 310         r32 &= ~(__F0_INTX_STATUS << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
 311         r32 |= (mode << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
 312
 313         writel(r32, rb + FNC_PERS_REG);
 314 }
 315
 316 /**
 317  * Cleanup hw semaphore and usecnt registers
 318  */
 319 static void
 320 bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc)
 321 {
 322         bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
 323         writel(0, ioc->ioc_regs.ioc_usage_reg);
 324         bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
 325
 326         /*
 327          * Read the hw sem reg to make sure that it is locked
 328          * before we clear it. If it is not locked, writing 1
 329          * will lock it instead of clearing it.
 330          */
 331         readl(ioc->ioc_regs.ioc_sem_reg);
 332         bfa_nw_ioc_hw_sem_release(ioc);
 333 }
 334
 335 /**
 336  * Synchronized IOC failure processing routines
 337  */
 338 static bool
 339 bfa_ioc_ct_sync_start(struct bfa_ioc *ioc)
 340 {
 341         u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
 342         u32 sync_reqd = bfa_ioc_ct_get_sync_reqd(r32);
 343
 344         /*
 345          * Driver load time.  If the sync required bit for this PCI fn
 346          * is set, it is due to an unclean exit by the driver for this
 347          * PCI fn in the previous incarnation. Whoever comes here first
 348          * should clean it up, no matter which PCI fn.
 349          */
 350
 351         if (sync_reqd & bfa_ioc_ct_sync_pos(ioc)) {
 352                 writel(0, ioc->ioc_regs.ioc_fail_sync);
 353                 writel(1, ioc->ioc_regs.ioc_usage_reg);
 354                 writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate);
 355                 writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate);
 356                 return true;
 357         }
 358
 359         return bfa_ioc_ct_sync_complete(ioc);
 360 }
 361 /**
 362  * Synchronized IOC failure processing routines
 363  */
 364 static void
 365 bfa_ioc_ct_sync_join(struct bfa_ioc *ioc)
 366 {
 367         u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
 368         u32 sync_pos = bfa_ioc_ct_sync_reqd_pos(ioc);
 369
 370         writel((r32 | sync_pos), ioc->ioc_regs.ioc_fail_sync);
 371 }
 372
 373 static void
 374 bfa_ioc_ct_sync_leave(struct bfa_ioc *ioc)
 375 {
 376         u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
 377         u32 sync_msk = bfa_ioc_ct_sync_reqd_pos(ioc) |
 378                                         bfa_ioc_ct_sync_pos(ioc);
 379
 380         writel((r32 & ~sync_msk), ioc->ioc_regs.ioc_fail_sync);
 381 }
 382
 383 static void
 384 bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc)
 385 {
 386         u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
 387
 388         writel((r32 | bfa_ioc_ct_sync_pos(ioc)), ioc->ioc_regs.ioc_fail_sync);
 389 }
 390
 391 static bool
 392 bfa_ioc_ct_sync_complete(struct bfa_ioc *ioc)
 393 {
 394         u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
 395         u32 sync_reqd = bfa_ioc_ct_get_sync_reqd(r32);
 396         u32 sync_ackd = bfa_ioc_ct_get_sync_ackd(r32);
 397         u32 tmp_ackd;
 398
 399         if (sync_ackd == 0)
 400                 return true;
 401
 402         /**
 403          * The check below is to see whether any other PCI fn
 404          * has reinitialized the ASIC (reset sync_ackd bits)
 405          * and failed again while this IOC was waiting for hw
 406          * semaphore (in bfa_iocpf_sm_semwait()).
 407          */
 408         tmp_ackd = sync_ackd;
 409         if ((sync_reqd &  bfa_ioc_ct_sync_pos(ioc)) &&
 410                         !(sync_ackd & bfa_ioc_ct_sync_pos(ioc)))
 411                 sync_ackd |= bfa_ioc_ct_sync_pos(ioc);
 412
 413         if (sync_reqd == sync_ackd) {
 414                 writel(bfa_ioc_ct_clear_sync_ackd(r32),
 415                                 ioc->ioc_regs.ioc_fail_sync);
 416                 writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate);
 417                 writel(BFI_IOC_FAIL, ioc->ioc_regs.alt_ioc_fwstate);
 418                 return true;
 419         }
 420
 421         /**
 422          * If another PCI fn reinitialized and failed again while
 423          * this IOC was waiting for hw sem, the sync_ackd bit for
 424          * this IOC need to be set again to allow reinitialization.
 425          */
 426         if (tmp_ackd != sync_ackd)
 427                 writel((r32 | sync_ackd), ioc->ioc_regs.ioc_fail_sync);
 428
 429         return false;
 430 }
 431
 432 static enum bfa_status
 433 bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode)
 434 {
 435         u32     pll_sclk, pll_fclk, r32;
 436         bool fcmode = (asic_mode == BFI_ASIC_MODE_FC);
 437
 438         pll_sclk = __APP_PLL_SCLK_LRESETN | __APP_PLL_SCLK_ENARST |
 439                 __APP_PLL_SCLK_RSEL200500 | __APP_PLL_SCLK_P0_1(3U) |
 440                 __APP_PLL_SCLK_JITLMT0_1(3U) |
 441                 __APP_PLL_SCLK_CNTLMT0_1(1U);
 442         pll_fclk = __APP_PLL_LCLK_LRESETN | __APP_PLL_LCLK_ENARST |
 443                 __APP_PLL_LCLK_RSEL200500 | __APP_PLL_LCLK_P0_1(3U) |
 444                 __APP_PLL_LCLK_JITLMT0_1(3U) |
 445                 __APP_PLL_LCLK_CNTLMT0_1(1U);
 446
 447         if (fcmode) {
 448                 writel(0, (rb + OP_MODE));
 449                 writel(__APP_EMS_CMLCKSEL |
 450                                 __APP_EMS_REFCKBUFEN2 |
 451                                 __APP_EMS_CHANNEL_SEL,
 452                                 (rb + ETH_MAC_SER_REG));
 453         } else {
 454                 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE));
 455                 writel(__APP_EMS_REFCKBUFEN1,
 456                                 (rb + ETH_MAC_SER_REG));
 457         }
 458         writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
 459         writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
 460         writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
 461         writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
 462         writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
 463         writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
 464         writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
 465         writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
 466         writel(pll_sclk |
 467                 __APP_PLL_SCLK_LOGIC_SOFT_RESET,
 468                 rb + APP_PLL_SCLK_CTL_REG);
 469         writel(pll_fclk |
 470                 __APP_PLL_LCLK_LOGIC_SOFT_RESET,
 471                 rb + APP_PLL_LCLK_CTL_REG);
 472         writel(pll_sclk |
 473                 __APP_PLL_SCLK_LOGIC_SOFT_RESET | __APP_PLL_SCLK_ENABLE,
 474                 rb + APP_PLL_SCLK_CTL_REG);
 475         writel(pll_fclk |
 476                 __APP_PLL_LCLK_LOGIC_SOFT_RESET | __APP_PLL_LCLK_ENABLE,
 477                 rb + APP_PLL_LCLK_CTL_REG);
 478         readl(rb + HOSTFN0_INT_MSK);
 479         udelay(2000);
 480         writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
 481         writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
 482         writel(pll_sclk |
 483                 __APP_PLL_SCLK_ENABLE,
 484                 rb + APP_PLL_SCLK_CTL_REG);
 485         writel(pll_fclk |
 486                 __APP_PLL_LCLK_ENABLE,
 487                 rb + APP_PLL_LCLK_CTL_REG);
 488
 489         if (!fcmode) {
 490                 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0));
 491                 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1));
 492         }
 493         r32 = readl((rb + PSS_CTL_REG));
 494         r32 &= ~__PSS_LMEM_RESET;
 495         writel(r32, (rb + PSS_CTL_REG));
 496         udelay(1000);
 497         if (!fcmode) {
 498                 writel(0, (rb + PMM_1T_RESET_REG_P0));
 499                 writel(0, (rb + PMM_1T_RESET_REG_P1));
 500         }
 501
 502         writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG));
 503         udelay(1000);
 504         r32 = readl((rb + MBIST_STAT_REG));
 505         writel(0, (rb + MBIST_CTL_REG));
 506         return BFA_STATUS_OK;
 507 }