drivers/net/ethernet/brocade/bna/bna_types.h

   1 /*
   2  * Linux network driver for Brocade Converged Network Adapter.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License (GPL) Version 2 as
   6  * published by the Free Software Foundation
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  */
  13 /*
  14  * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
  15  * All rights reserved
  16  * www.brocade.com
  17  */
  18 #ifndef __BNA_TYPES_H__
  19 #define __BNA_TYPES_H__
  20
  21 #include "cna.h"
  22 #include "bna_hw_defs.h"
  23 #include "bfa_cee.h"
  24 #include "bfi_enet.h"
  25 #include "bfa_msgq.h"
  26
  27 /**
  28  *
  29  * Forward declarations
  30  *
  31  */
  32
  33 struct bna_mcam_handle;
  34 struct bna_txq;
  35 struct bna_tx;
  36 struct bna_rxq;
  37 struct bna_cq;
  38 struct bna_rx;
  39 struct bna_rxf;
  40 struct bna_port;
  41 struct bna_enet;
  42 struct bna;
  43 struct bnad;
  44
  45 /**
  46  *
  47  * Enums, primitive data types
  48  *
  49  */
  50
  51 enum bna_status {
  52         BNA_STATUS_T_DISABLED   = 0,
  53         BNA_STATUS_T_ENABLED    = 1
  54 };
  55
  56 enum bna_cleanup_type {
  57         BNA_HARD_CLEANUP        = 0,
  58         BNA_SOFT_CLEANUP        = 1
  59 };
  60
  61 enum bna_cb_status {
  62         BNA_CB_SUCCESS          = 0,
  63         BNA_CB_FAIL             = 1,
  64         BNA_CB_INTERRUPT        = 2,
  65         BNA_CB_BUSY             = 3,
  66         BNA_CB_INVALID_MAC      = 4,
  67         BNA_CB_MCAST_LIST_FULL  = 5,
  68         BNA_CB_UCAST_CAM_FULL   = 6,
  69         BNA_CB_WAITING          = 7,
  70         BNA_CB_NOT_EXEC         = 8
  71 };
  72
  73 enum bna_res_type {
  74         BNA_RES_T_MEM           = 1,
  75         BNA_RES_T_INTR          = 2
  76 };
  77
  78 enum bna_mem_type {
  79         BNA_MEM_T_KVA           = 1,
  80         BNA_MEM_T_DMA           = 2
  81 };
  82
  83 enum bna_intr_type {
  84         BNA_INTR_T_INTX         = 1,
  85         BNA_INTR_T_MSIX         = 2
  86 };
  87
  88 enum bna_res_req_type {
  89         BNA_RES_MEM_T_COM               = 0,
  90         BNA_RES_MEM_T_ATTR              = 1,
  91         BNA_RES_MEM_T_FWTRC             = 2,
  92         BNA_RES_MEM_T_STATS             = 3,
  93         BNA_RES_MEM_T_SWSTATS           = 4,
  94         BNA_RES_MEM_T_IBIDX             = 5,
  95         BNA_RES_MEM_T_IB_ARRAY          = 6,
  96         BNA_RES_MEM_T_INTR_ARRAY        = 7,
  97         BNA_RES_MEM_T_IDXSEG_ARRAY      = 8,
  98         BNA_RES_MEM_T_TX_ARRAY          = 9,
  99         BNA_RES_MEM_T_TXQ_ARRAY         = 10,
 100         BNA_RES_MEM_T_RX_ARRAY          = 11,
 101         BNA_RES_MEM_T_RXP_ARRAY         = 12,
 102         BNA_RES_MEM_T_RXQ_ARRAY         = 13,
 103         BNA_RES_MEM_T_UCMAC_ARRAY       = 14,
 104         BNA_RES_MEM_T_MCMAC_ARRAY       = 15,
 105         BNA_RES_MEM_T_RIT_ENTRY         = 16,
 106         BNA_RES_MEM_T_RIT_SEGMENT       = 17,
 107         BNA_RES_INTR_T_MBOX             = 18,
 108         BNA_RES_T_MAX
 109 };
 110
 111 enum bna_mod_res_req_type {
 112         BNA_MOD_RES_MEM_T_TX_ARRAY      = 0,
 113         BNA_MOD_RES_MEM_T_TXQ_ARRAY     = 1,
 114         BNA_MOD_RES_MEM_T_RX_ARRAY      = 2,
 115         BNA_MOD_RES_MEM_T_RXP_ARRAY     = 3,
 116         BNA_MOD_RES_MEM_T_RXQ_ARRAY     = 4,
 117         BNA_MOD_RES_MEM_T_UCMAC_ARRAY   = 5,
 118         BNA_MOD_RES_MEM_T_MCMAC_ARRAY   = 6,
 119         BNA_MOD_RES_MEM_T_MCHANDLE_ARRAY = 7,
 120         BNA_MOD_RES_T_MAX
 121 };
 122
 123 enum bna_tx_res_req_type {
 124         BNA_TX_RES_MEM_T_TCB    = 0,
 125         BNA_TX_RES_MEM_T_UNMAPQ = 1,
 126         BNA_TX_RES_MEM_T_QPT    = 2,
 127         BNA_TX_RES_MEM_T_SWQPT  = 3,
 128         BNA_TX_RES_MEM_T_PAGE   = 4,
 129         BNA_TX_RES_MEM_T_IBIDX  = 5,
 130         BNA_TX_RES_INTR_T_TXCMPL = 6,
 131         BNA_TX_RES_T_MAX,
 132 };
 133
 134 enum bna_rx_mem_type {
 135         BNA_RX_RES_MEM_T_CCB            = 0,    /* CQ context */
 136         BNA_RX_RES_MEM_T_RCB            = 1,    /* CQ context */
 137         BNA_RX_RES_MEM_T_UNMAPQ         = 2,    /* UnmapQ for RxQs */
 138         BNA_RX_RES_MEM_T_CQPT           = 3,    /* CQ QPT */
 139         BNA_RX_RES_MEM_T_CSWQPT         = 4,    /* S/W QPT */
 140         BNA_RX_RES_MEM_T_CQPT_PAGE      = 5,    /* CQPT page */
 141         BNA_RX_RES_MEM_T_HQPT           = 6,    /* RX QPT */
 142         BNA_RX_RES_MEM_T_DQPT           = 7,    /* RX QPT */
 143         BNA_RX_RES_MEM_T_HSWQPT         = 8,    /* RX s/w QPT */
 144         BNA_RX_RES_MEM_T_DSWQPT         = 9,    /* RX s/w QPT */
 145         BNA_RX_RES_MEM_T_DPAGE          = 10,   /* RX s/w QPT */
 146         BNA_RX_RES_MEM_T_HPAGE          = 11,   /* RX s/w QPT */
 147         BNA_RX_RES_MEM_T_IBIDX          = 12,
 148         BNA_RX_RES_MEM_T_RIT            = 13,
 149         BNA_RX_RES_T_INTR               = 14,   /* Rx interrupts */
 150         BNA_RX_RES_T_MAX                = 15
 151 };
 152
 153 enum bna_mbox_state {
 154         BNA_MBOX_FREE           = 0,
 155         BNA_MBOX_POSTED         = 1
 156 };
 157
 158 enum bna_tx_type {
 159         BNA_TX_T_REGULAR        = 0,
 160         BNA_TX_T_LOOPBACK       = 1,
 161 };
 162
 163 enum bna_tx_flags {
 164         BNA_TX_F_ENET_STARTED   = 1,
 165         BNA_TX_F_ENABLED        = 2,
 166         BNA_TX_F_PRIO_CHANGED   = 4,
 167         BNA_TX_F_BW_UPDATED     = 8,
 168 };
 169
 170 enum bna_tx_mod_flags {
 171         BNA_TX_MOD_F_ENET_STARTED       = 1,
 172         BNA_TX_MOD_F_ENET_LOOPBACK      = 2,
 173 };
 174
 175 enum bna_rx_type {
 176         BNA_RX_T_REGULAR        = 0,
 177         BNA_RX_T_LOOPBACK       = 1,
 178 };
 179
 180 enum bna_rxp_type {
 181         BNA_RXP_SINGLE          = 1,
 182         BNA_RXP_SLR             = 2,
 183         BNA_RXP_HDS             = 3
 184 };
 185
 186 enum bna_rxmode {
 187         BNA_RXMODE_PROMISC      = 1,
 188         BNA_RXMODE_DEFAULT      = 2,
 189         BNA_RXMODE_ALLMULTI     = 4
 190 };
 191
 192 enum bna_rx_event {
 193         RX_E_START                      = 1,
 194         RX_E_STOP                       = 2,
 195         RX_E_FAIL                       = 3,
 196         RX_E_STARTED                    = 4,
 197         RX_E_STOPPED                    = 5,
 198         RX_E_RXF_STARTED                = 6,
 199         RX_E_RXF_STOPPED                = 7,
 200         RX_E_CLEANUP_DONE               = 8,
 201 };
 202
 203 enum bna_rx_state {
 204         BNA_RX_STOPPED                  = 1,
 205         BNA_RX_RXF_START_WAIT           = 2,
 206         BNA_RX_STARTED                  = 3,
 207         BNA_RX_RXF_STOP_WAIT            = 4,
 208         BNA_RX_RXQ_STOP_WAIT            = 5,
 209 };
 210
 211 enum bna_rx_flags {
 212         BNA_RX_F_ENET_STARTED   = 1,
 213         BNA_RX_F_ENABLED        = 2,
 214 };
 215
 216 enum bna_rx_mod_flags {
 217         BNA_RX_MOD_F_ENET_STARTED       = 1,
 218         BNA_RX_MOD_F_ENET_LOOPBACK      = 2,
 219 };
 220
 221 enum bna_rxf_oper_state {
 222         BNA_RXF_OPER_STATE_RUNNING      = 0x01, /* rxf operational */
 223         BNA_RXF_OPER_STATE_PAUSED       = 0x02, /* rxf in PAUSED state */
 224 };
 225
 226 enum bna_rxf_flags {
 227         BNA_RXF_F_PAUSED                = 1,
 228 };
 229
 230 enum bna_rxf_event {
 231         RXF_E_START                     = 1,
 232         RXF_E_STOP                      = 2,
 233         RXF_E_FAIL                      = 3,
 234         RXF_E_CONFIG                    = 4,
 235         RXF_E_PAUSE                     = 5,
 236         RXF_E_RESUME                    = 6,
 237         RXF_E_FW_RESP                   = 7,
 238 };
 239
 240 enum bna_rxf_state {
 241         BNA_RXF_STOPPED                 = 1,
 242         BNA_RXF_START_WAIT              = 2,
 243         BNA_RXF_CAM_FLTR_MOD_WAIT       = 3,
 244         BNA_RXF_STARTED                 = 4,
 245         BNA_RXF_CAM_FLTR_CLR_WAIT       = 5,
 246         BNA_RXF_STOP_WAIT               = 6,
 247         BNA_RXF_PAUSE_WAIT              = 7,
 248         BNA_RXF_RESUME_WAIT             = 8,
 249         BNA_RXF_STAT_CLR_WAIT           = 9,
 250 };
 251
 252 enum bna_port_type {
 253         BNA_PORT_T_REGULAR              = 0,
 254         BNA_PORT_T_LOOPBACK_INTERNAL    = 1,
 255         BNA_PORT_T_LOOPBACK_EXTERNAL    = 2,
 256 };
 257
 258 enum bna_enet_type {
 259         BNA_ENET_T_REGULAR              = 0,
 260         BNA_ENET_T_LOOPBACK_INTERNAL    = 1,
 261         BNA_ENET_T_LOOPBACK_EXTERNAL    = 2,
 262 };
 263
 264 enum bna_link_status {
 265         BNA_LINK_DOWN           = 0,
 266         BNA_LINK_UP             = 1,
 267         BNA_CEE_UP              = 2
 268 };
 269
 270 enum bna_llport_flags {
 271         BNA_LLPORT_F_ADMIN_UP           = 1,
 272         BNA_LLPORT_F_PORT_ENABLED       = 2,
 273         BNA_LLPORT_F_RX_STARTED         = 4
 274 };
 275
 276 enum bna_ethport_flags {
 277         BNA_ETHPORT_F_ADMIN_UP          = 1,
 278         BNA_ETHPORT_F_PORT_ENABLED      = 2,
 279         BNA_ETHPORT_F_RX_STARTED        = 4,
 280 };
 281
 282 enum bna_port_flags {
 283         BNA_PORT_F_DEVICE_READY = 1,
 284         BNA_PORT_F_ENABLED      = 2,
 285         BNA_PORT_F_PAUSE_CHANGED = 4,
 286         BNA_PORT_F_MTU_CHANGED  = 8
 287 };
 288
 289 enum bna_enet_flags {
 290         BNA_ENET_F_IOCETH_READY         = 1,
 291         BNA_ENET_F_ENABLED              = 2,
 292         BNA_ENET_F_PAUSE_CHANGED        = 4,
 293         BNA_ENET_F_MTU_CHANGED          = 8
 294 };
 295
 296 enum bna_rss_flags {
 297         BNA_RSS_F_RIT_PENDING           = 1,
 298         BNA_RSS_F_CFG_PENDING           = 2,
 299         BNA_RSS_F_STATUS_PENDING        = 4,
 300 };
 301
 302 enum bna_mod_flags {
 303         BNA_MOD_F_INIT_DONE             = 1,
 304 };
 305
 306 enum bna_pkt_rates {
 307         BNA_PKT_RATE_10K                = 10000,
 308         BNA_PKT_RATE_20K                = 20000,
 309         BNA_PKT_RATE_30K                = 30000,
 310         BNA_PKT_RATE_40K                = 40000,
 311         BNA_PKT_RATE_50K                = 50000,
 312         BNA_PKT_RATE_60K                = 60000,
 313         BNA_PKT_RATE_70K                = 70000,
 314         BNA_PKT_RATE_80K                = 80000,
 315 };
 316
 317 enum bna_dim_load_types {
 318         BNA_LOAD_T_HIGH_4               = 0, /* 80K <= r */
 319         BNA_LOAD_T_HIGH_3               = 1, /* 60K <= r < 80K */
 320         BNA_LOAD_T_HIGH_2               = 2, /* 50K <= r < 60K */
 321         BNA_LOAD_T_HIGH_1               = 3, /* 40K <= r < 50K */
 322         BNA_LOAD_T_LOW_1                = 4, /* 30K <= r < 40K */
 323         BNA_LOAD_T_LOW_2                = 5, /* 20K <= r < 30K */
 324         BNA_LOAD_T_LOW_3                = 6, /* 10K <= r < 20K */
 325         BNA_LOAD_T_LOW_4                = 7, /* r < 10K */
 326         BNA_LOAD_T_MAX                  = 8
 327 };
 328
 329 enum bna_dim_bias_types {
 330         BNA_BIAS_T_SMALL                = 0, /* small pkts > (large pkts * 2) */
 331         BNA_BIAS_T_LARGE                = 1, /* Not BNA_BIAS_T_SMALL */
 332         BNA_BIAS_T_MAX                  = 2
 333 };
 334
 335 #define BNA_MAX_NAME_SIZE       64
 336 struct bna_ident {
 337         int                     id;
 338         char                    name[BNA_MAX_NAME_SIZE];
 339 };
 340
 341 struct bna_mac {
 342         /* This should be the first one */
 343         struct list_head                        qe;
 344         u8                      addr[ETH_ALEN];
 345         struct bna_mcam_handle *handle;
 346 };
 347
 348 struct bna_mem_descr {
 349         u32             len;
 350         void            *kva;
 351         struct bna_dma_addr dma;
 352 };
 353
 354 struct bna_mem_info {
 355         enum bna_mem_type mem_type;
 356         u32             len;
 357         u32             num;
 358         u32             align_sz; /* 0/1 = no alignment */
 359         struct bna_mem_descr *mdl;
 360         void                    *cookie; /* For bnad to unmap dma later */
 361 };
 362
 363 struct bna_intr_descr {
 364         int                     vector;
 365 };
 366
 367 struct bna_intr_info {
 368         enum bna_intr_type intr_type;
 369         int                     num;
 370         struct bna_intr_descr *idl;
 371 };
 372
 373 union bna_res_u {
 374         struct bna_mem_info mem_info;
 375         struct bna_intr_info intr_info;
 376 };
 377
 378 struct bna_res_info {
 379         enum bna_res_type res_type;
 380         union bna_res_u         res_u;
 381 };
 382
 383 /* HW QPT */
 384 struct bna_qpt {
 385         struct bna_dma_addr hw_qpt_ptr;
 386         void            *kv_qpt_ptr;
 387         u32             page_count;
 388         u32             page_size;
 389 };
 390
 391 struct bna_attr {
 392         int                     num_txq;
 393         int                     num_rxp;
 394         int                     num_ucmac;
 395         int                     num_mcmac;
 396         int                     max_rit_size;
 397 };
 398
 399 /**
 400  *
 401  * IOCEth
 402  *
 403  */
 404
 405 struct bna_ioceth {
 406         bfa_fsm_t               fsm;
 407         struct bfa_ioc ioc;
 408
 409         struct bna_attr attr;
 410         struct bfa_msgq_cmd_entry msgq_cmd;
 411         struct bfi_enet_attr_req attr_req;
 412
 413         void (*stop_cbfn)(struct bnad *bnad);
 414         struct bnad *stop_cbarg;
 415
 416         struct bna *bna;
 417 };
 418
 419 /**
 420  *
 421  * Mail box
 422  *
 423  */
 424
 425 struct bna_mbox_qe {
 426         /* This should be the first one */
 427         struct list_head                        qe;
 428
 429         struct bfa_mbox_cmd cmd;
 430         u32             cmd_len;
 431         /* Callback for port, tx, rx, rxf */
 432         void (*cbfn)(void *arg, int status);
 433         void                    *cbarg;
 434 };
 435
 436 struct bna_mbox_mod {
 437         enum bna_mbox_state state;
 438         struct list_head                        posted_q;
 439         u32             msg_pending;
 440         u32             msg_ctr;
 441         struct bna *bna;
 442 };
 443
 444 /**
 445  *
 446  * Port
 447  *
 448  */
 449
 450 /* Pause configuration */
 451 struct bna_pause_config {
 452         enum bna_status tx_pause;
 453         enum bna_status rx_pause;
 454 };
 455
 456 struct bna_llport {
 457         bfa_fsm_t               fsm;
 458         enum bna_llport_flags flags;
 459
 460         enum bna_port_type type;
 461
 462         enum bna_link_status link_status;
 463
 464         int                     rx_started_count;
 465
 466         void (*stop_cbfn)(struct bna_port *, enum bna_cb_status);
 467
 468         struct bna_mbox_qe mbox_qe;
 469
 470         struct bna *bna;
 471 };
 472
 473 struct bna_port {
 474         bfa_fsm_t               fsm;
 475         enum bna_port_flags flags;
 476
 477         enum bna_port_type type;
 478
 479         struct bna_llport llport;
 480
 481         struct bna_pause_config pause_config;
 482         u8                      priority;
 483         int                     mtu;
 484
 485         /* Callback for bna_port_disable(), port_stop() */
 486         void (*stop_cbfn)(void *, enum bna_cb_status);
 487         void                    *stop_cbarg;
 488
 489         /* Callback for bna_port_pause_config() */
 490         void (*pause_cbfn)(struct bnad *, enum bna_cb_status);
 491
 492         /* Callback for bna_port_mtu_set() */
 493         void (*mtu_cbfn)(struct bnad *, enum bna_cb_status);
 494
 495         void (*link_cbfn)(struct bnad *, enum bna_link_status);
 496
 497         struct bfa_wc           chld_stop_wc;
 498
 499         struct bna_mbox_qe mbox_qe;
 500
 501         struct bna *bna;
 502 };
 503
 504 /**
 505  *
 506  * Enet
 507  *
 508  */
 509
 510 struct bna_enet {
 511         bfa_fsm_t               fsm;
 512         enum bna_enet_flags flags;
 513
 514         enum bna_enet_type type;
 515
 516         struct bna_pause_config pause_config;
 517         int                     mtu;
 518
 519         /* Callback for bna_enet_disable(), enet_stop() */
 520         void (*stop_cbfn)(void *);
 521         void                    *stop_cbarg;
 522
 523         /* Callback for bna_enet_pause_config() */
 524         void (*pause_cbfn)(struct bnad *);
 525
 526         /* Callback for bna_enet_mtu_set() */
 527         void (*mtu_cbfn)(struct bnad *);
 528
 529         struct bfa_wc           chld_stop_wc;
 530
 531         struct bfa_msgq_cmd_entry msgq_cmd;
 532         struct bfi_enet_set_pause_req pause_req;
 533
 534         struct bna *bna;
 535 };
 536
 537 /**
 538  *
 539  * Ethport
 540  *
 541  */
 542
 543 struct bna_ethport {
 544         bfa_fsm_t               fsm;
 545         enum bna_ethport_flags flags;
 546
 547         enum bna_link_status link_status;
 548
 549         int                     rx_started_count;
 550
 551         void (*stop_cbfn)(struct bna_enet *);
 552
 553         void (*adminup_cbfn)(struct bnad *, enum bna_cb_status);
 554
 555         void (*link_cbfn)(struct bnad *, enum bna_link_status);
 556
 557         struct bfa_msgq_cmd_entry msgq_cmd;
 558         union {
 559                 struct bfi_enet_enable_req admin_req;
 560                 struct bfi_enet_diag_lb_req lpbk_req;
 561         } bfi_enet_cmd;
 562
 563         struct bna *bna;
 564 };
 565
 566 /**
 567  *
 568  * Interrupt Block
 569  *
 570  */
 571
 572 /* IB index segment structure */
 573 struct bna_ibidx_seg {
 574         /* This should be the first one */
 575         struct list_head                        qe;
 576
 577         u8                      ib_seg_size;
 578         u8                      ib_idx_tbl_offset;
 579 };
 580
 581 /* Interrupt structure */
 582 struct bna_intr {
 583         /* This should be the first one */
 584         struct list_head                        qe;
 585         int                     ref_count;
 586
 587         enum bna_intr_type intr_type;
 588         int                     vector;
 589
 590         struct bna_ib *ib;
 591 };
 592
 593 /* Doorbell structure */
 594 struct bna_ib_dbell {
 595         void *__iomem doorbell_addr;
 596         u32             doorbell_ack;
 597 };
 598
 599 /* IB structure */
 600 struct bna_ib {
 601         struct bna_dma_addr ib_seg_host_addr;
 602         void            *ib_seg_host_addr_kva;
 603
 604         struct bna_ib_dbell door_bell;
 605
 606         enum bna_intr_type      intr_type;
 607         int                     intr_vector;
 608
 609         u8                      coalescing_timeo;    /* Unit is 5usec. */
 610
 611         int                     interpkt_count;
 612         int                     interpkt_timeo;
 613 };
 614
 615 /**
 616  *
 617  * Tx object
 618  *
 619  */
 620
 621 /* Tx datapath control structure */
 622 #define BNA_Q_NAME_SIZE         16
 623 struct bna_tcb {
 624         /* Fast path */
 625         void                    **sw_qpt;
 626         void                    *unmap_q;
 627         u32             producer_index;
 628         u32             consumer_index;
 629         volatile u32    *hw_consumer_index;
 630         u32             q_depth;
 631         void *__iomem q_dbell;
 632         struct bna_ib_dbell *i_dbell;
 633         int                     page_idx;
 634         int                     page_count;
 635         /* Control path */
 636         struct bna_txq *txq;
 637         struct bnad *bnad;
 638         void                    *priv; /* BNAD's cookie */
 639         enum bna_intr_type intr_type;
 640         int                     intr_vector;
 641         u8                      priority; /* Current priority */
 642         unsigned long           flags; /* Used by bnad as required */
 643         int                     id;
 644         char                    name[BNA_Q_NAME_SIZE];
 645 };
 646
 647 /* TxQ QPT and configuration */
 648 struct bna_txq {
 649         /* This should be the first one */
 650         struct list_head                        qe;
 651
 652         u8                      priority;
 653
 654         struct bna_qpt qpt;
 655         struct bna_tcb *tcb;
 656         struct bna_ib ib;
 657
 658         struct bna_tx *tx;
 659
 660         int                     hw_id;
 661
 662         u64             tx_packets;
 663         u64             tx_bytes;
 664 };
 665
 666 /* Tx object */
 667 struct bna_tx {
 668         /* This should be the first one */
 669         struct list_head                        qe;
 670         int                     rid;
 671         int                     hw_id;
 672
 673         bfa_fsm_t               fsm;
 674         enum bna_tx_flags flags;
 675
 676         enum bna_tx_type type;
 677         int                     num_txq;
 678
 679         struct list_head                        txq_q;
 680         u16                     txf_vlan_id;
 681
 682         /* Tx event handlers */
 683         void (*tcb_setup_cbfn)(struct bnad *, struct bna_tcb *);
 684         void (*tcb_destroy_cbfn)(struct bnad *, struct bna_tcb *);
 685         void (*tx_stall_cbfn)(struct bnad *, struct bna_tx *);
 686         void (*tx_resume_cbfn)(struct bnad *, struct bna_tx *);
 687         void (*tx_cleanup_cbfn)(struct bnad *, struct bna_tx *);
 688
 689         /* callback for bna_tx_disable(), bna_tx_stop() */
 690         void (*stop_cbfn)(void *arg, struct bna_tx *tx);
 691         void                    *stop_cbarg;
 692
 693         /* callback for bna_tx_prio_set() */
 694         void (*prio_change_cbfn)(struct bnad *bnad, struct bna_tx *tx);
 695
 696         struct bfa_msgq_cmd_entry msgq_cmd;
 697         union {
 698                 struct bfi_enet_tx_cfg_req      cfg_req;
 699                 struct bfi_enet_req             req;
 700                 struct bfi_enet_tx_cfg_rsp      cfg_rsp;
 701         } bfi_enet_cmd;
 702
 703         struct bna *bna;
 704         void                    *priv;  /* bnad's cookie */
 705 };
 706
 707 /* Tx object configuration used during creation */
 708 struct bna_tx_config {
 709         int                     num_txq;
 710         int                     txq_depth;
 711         int                     coalescing_timeo;
 712         enum bna_tx_type tx_type;
 713 };
 714
 715 struct bna_tx_event_cbfn {
 716         /* Optional */
 717         void (*tcb_setup_cbfn)(struct bnad *, struct bna_tcb *);
 718         void (*tcb_destroy_cbfn)(struct bnad *, struct bna_tcb *);
 719         /* Mandatory */
 720         void (*tx_stall_cbfn)(struct bnad *, struct bna_tx *);
 721         void (*tx_resume_cbfn)(struct bnad *, struct bna_tx *);
 722         void (*tx_cleanup_cbfn)(struct bnad *, struct bna_tx *);
 723 };
 724
 725 /* Tx module - keeps track of free, active tx objects */
 726 struct bna_tx_mod {
 727         struct bna_tx *tx;              /* BFI_MAX_TXQ entries */
 728         struct bna_txq *txq;            /* BFI_MAX_TXQ entries */
 729
 730         struct list_head                        tx_free_q;
 731         struct list_head                        tx_active_q;
 732
 733         struct list_head                        txq_free_q;
 734
 735         /* callback for bna_tx_mod_stop() */
 736         void (*stop_cbfn)(struct bna_enet *enet);
 737
 738         struct bfa_wc           tx_stop_wc;
 739
 740         enum bna_tx_mod_flags flags;
 741
 742         u8                      prio_map;
 743         int                     default_prio;
 744         int                     iscsi_over_cee;
 745         int                     iscsi_prio;
 746         int                     prio_reconfigured;
 747
 748         u32                     rid_mask;
 749
 750         struct bna *bna;
 751 };
 752
 753 /**
 754  *
 755  * Receive Indirection Table
 756  *
 757  */
 758
 759 /* One row of RIT table */
 760 struct bna_rit_entry {
 761         u8 large_rxq_id;        /* used for either large or data buffers */
 762         u8 small_rxq_id;        /* used for either small or header buffers */
 763 };
 764
 765 /* RIT segment */
 766 struct bna_rit_segment {
 767         struct list_head                        qe;
 768
 769         u32             rit_offset;
 770         u32             rit_size;
 771         /**
 772          * max_rit_size: Varies per RIT segment depending on how RIT is
 773          * partitioned
 774          */
 775         u32             max_rit_size;
 776
 777         struct bna_rit_entry *rit;
 778 };
 779
 780 /**
 781  *
 782  * Rx object
 783  *
 784  */
 785
 786 /* Rx datapath control structure */
 787 struct bna_rcb {
 788         /* Fast path */
 789         void                    **sw_qpt;
 790         void                    *unmap_q;
 791         u32             producer_index;
 792         u32             consumer_index;
 793         u32             q_depth;
 794         void *__iomem q_dbell;
 795         int                     page_idx;
 796         int                     page_count;
 797         /* Control path */
 798         struct bna_rxq *rxq;
 799         struct bna_ccb *ccb;
 800         struct bnad *bnad;
 801         void                    *priv; /* BNAD's cookie */
 802         unsigned long           flags;
 803         int                     id;
 804 };
 805
 806 /* RxQ structure - QPT, configuration */
 807 struct bna_rxq {
 808         struct list_head                        qe;
 809
 810         int                     buffer_size;
 811         int                     q_depth;
 812
 813         struct bna_qpt qpt;
 814         struct bna_rcb *rcb;
 815
 816         struct bna_rxp *rxp;
 817         struct bna_rx *rx;
 818
 819         int                     hw_id;
 820
 821         u64             rx_packets;
 822         u64             rx_bytes;
 823         u64             rx_packets_with_error;
 824         u64             rxbuf_alloc_failed;
 825 };
 826
 827 /* RxQ pair */
 828 union bna_rxq_u {
 829         struct {
 830                 struct bna_rxq *hdr;
 831                 struct bna_rxq *data;
 832         } hds;
 833         struct {
 834                 struct bna_rxq *small;
 835                 struct bna_rxq *large;
 836         } slr;
 837         struct {
 838                 struct bna_rxq *only;
 839                 struct bna_rxq *reserved;
 840         } single;
 841 };
 842
 843 /* Packet rate for Dynamic Interrupt Moderation */
 844 struct bna_pkt_rate {
 845         u32             small_pkt_cnt;
 846         u32             large_pkt_cnt;
 847 };
 848
 849 /* Completion control structure */
 850 struct bna_ccb {
 851         /* Fast path */
 852         void                    **sw_qpt;
 853         u32             producer_index;
 854         volatile u32    *hw_producer_index;
 855         u32             q_depth;
 856         struct bna_ib_dbell *i_dbell;
 857         struct bna_rcb *rcb[2];
 858         void                    *ctrl; /* For bnad */
 859         struct bna_pkt_rate pkt_rate;
 860         int                     page_idx;
 861         int                     page_count;
 862
 863         /* Control path */
 864         struct bna_cq *cq;
 865         struct bnad *bnad;
 866         void                    *priv; /* BNAD's cookie */
 867         enum bna_intr_type intr_type;
 868         int                     intr_vector;
 869         u8                      rx_coalescing_timeo; /* For NAPI */
 870         int                     id;
 871         char                    name[BNA_Q_NAME_SIZE];
 872 };
 873
 874 /* CQ QPT, configuration  */
 875 struct bna_cq {
 876         struct bna_qpt qpt;
 877         struct bna_ccb *ccb;
 878
 879         struct bna_ib ib;
 880
 881         struct bna_rx *rx;
 882 };
 883
 884 struct bna_rss_config {
 885         enum bfi_enet_rss_type  hash_type;
 886         u8                      hash_mask;
 887         u32             toeplitz_hash_key[BFI_ENET_RSS_KEY_LEN];
 888 };
 889
 890 struct bna_hds_config {
 891         enum bfi_enet_hds_type  hdr_type;
 892         int                     forced_offset;
 893 };
 894
 895 /* Rx object configuration used during creation */
 896 struct bna_rx_config {
 897         enum bna_rx_type rx_type;
 898         int                     num_paths;
 899         enum bna_rxp_type rxp_type;
 900         int                     paused;
 901         int                     q_depth;
 902         int                     coalescing_timeo;
 903         /*
 904          * Small/Large (or Header/Data) buffer size to be configured
 905          * for SLR and HDS queue type. Large buffer size comes from
 906          * enet->mtu.
 907          */
 908         int                     small_buff_size;
 909
 910         enum bna_status rss_status;
 911         struct bna_rss_config rss_config;
 912
 913         struct bna_hds_config hds_config;
 914
 915         enum bna_status vlan_strip_status;
 916 };
 917
 918 /* Rx Path structure - one per MSIX vector/CPU */
 919 struct bna_rxp {
 920         /* This should be the first one */
 921         struct list_head                        qe;
 922
 923         enum bna_rxp_type type;
 924         union   bna_rxq_u       rxq;
 925         struct bna_cq cq;
 926
 927         struct bna_rx *rx;
 928
 929         /* MSI-x vector number for configuring RSS */
 930         int                     vector;
 931         int                     hw_id;
 932 };
 933
 934 /* RxF structure (hardware Rx Function) */
 935 struct bna_rxf {
 936         bfa_fsm_t               fsm;
 937         enum bna_rxf_flags flags;
 938
 939         struct bfa_msgq_cmd_entry msgq_cmd;
 940         union {
 941                 struct bfi_enet_enable_req req;
 942                 struct bfi_enet_rss_cfg_req rss_req;
 943                 struct bfi_enet_rit_req rit_req;
 944                 struct bfi_enet_rx_vlan_req vlan_req;
 945                 struct bfi_enet_mcast_add_req mcast_add_req;
 946                 struct bfi_enet_mcast_del_req mcast_del_req;
 947                 struct bfi_enet_ucast_req ucast_req;
 948         } bfi_enet_cmd;
 949
 950         /* callback for bna_rxf_start() */
 951         void (*start_cbfn) (struct bna_rx *rx);
 952         struct bna_rx *start_cbarg;
 953
 954         /* callback for bna_rxf_stop() */
 955         void (*stop_cbfn) (struct bna_rx *rx);
 956         struct bna_rx *stop_cbarg;
 957
 958         /* callback for bna_rx_receive_pause() / bna_rx_receive_resume() */
 959         void (*oper_state_cbfn) (struct bnad *bnad, struct bna_rx *rx);
 960         struct bnad *oper_state_cbarg;
 961
 962         /**
 963          * callback for:
 964          *      bna_rxf_ucast_set()
 965          *      bna_rxf_{ucast/mcast}_add(),
 966          *      bna_rxf_{ucast/mcast}_del(),
 967          *      bna_rxf_mode_set()
 968          */
 969         void (*cam_fltr_cbfn)(struct bnad *bnad, struct bna_rx *rx);
 970         struct bnad *cam_fltr_cbarg;
 971
 972         /* List of unicast addresses yet to be applied to h/w */
 973         struct list_head                        ucast_pending_add_q;
 974         struct list_head                        ucast_pending_del_q;
 975         struct bna_mac *ucast_pending_mac;
 976         int                     ucast_pending_set;
 977         /* ucast addresses applied to the h/w */
 978         struct list_head                        ucast_active_q;
 979         struct bna_mac ucast_active_mac;
 980         int                     ucast_active_set;
 981
 982         /* List of multicast addresses yet to be applied to h/w */
 983         struct list_head                        mcast_pending_add_q;
 984         struct list_head                        mcast_pending_del_q;
 985         /* multicast addresses applied to the h/w */
 986         struct list_head                        mcast_active_q;
 987         struct list_head                        mcast_handle_q;
 988
 989         /* Rx modes yet to be applied to h/w */
 990         enum bna_rxmode rxmode_pending;
 991         enum bna_rxmode rxmode_pending_bitmask;
 992         /* Rx modes applied to h/w */
 993         enum bna_rxmode rxmode_active;
 994
 995         u8                      vlan_pending_bitmask;
 996         enum bna_status vlan_filter_status;
 997         u32     vlan_filter_table[(BFI_ENET_VLAN_ID_MAX) / 32];
 998         bool                    vlan_strip_pending;
 999         enum bna_status         vlan_strip_status;
1000
1001         enum bna_rss_flags      rss_pending;
1002         enum bna_status         rss_status;
1003         struct bna_rss_config   rss_cfg;
1004         u8                      *rit;
1005         int                     rit_size;
1006
1007         struct bna_rx           *rx;
1008 };
1009
1010 /* Rx object */
1011 struct bna_rx {
1012         /* This should be the first one */
1013         struct list_head                        qe;
1014         int                     rid;
1015         int                     hw_id;
1016
1017         bfa_fsm_t               fsm;
1018
1019         enum bna_rx_type type;
1020
1021         int                     num_paths;
1022         struct list_head                        rxp_q;
1023
1024         struct bna_hds_config   hds_cfg;
1025
1026         struct bna_rxf rxf;
1027
1028         enum bna_rx_flags rx_flags;
1029
1030         struct bfa_msgq_cmd_entry msgq_cmd;
1031         union {
1032                 struct bfi_enet_rx_cfg_req      cfg_req;
1033                 struct bfi_enet_req             req;
1034                 struct bfi_enet_rx_cfg_rsp      cfg_rsp;
1035         } bfi_enet_cmd;
1036
1037         /* Rx event handlers */
1038         void (*rcb_setup_cbfn)(struct bnad *, struct bna_rcb *);
1039         void (*rcb_destroy_cbfn)(struct bnad *, struct bna_rcb *);
1040         void (*ccb_setup_cbfn)(struct bnad *, struct bna_ccb *);
1041         void (*ccb_destroy_cbfn)(struct bnad *, struct bna_ccb *);
1042         void (*rx_cleanup_cbfn)(struct bnad *, struct bna_rx *);
1043         void (*rx_post_cbfn)(struct bnad *, struct bna_rx *);
1044
1045         /* callback for bna_rx_disable(), bna_rx_stop() */
1046         void (*stop_cbfn)(void *arg, struct bna_rx *rx);
1047         void                    *stop_cbarg;
1048
1049         struct bna *bna;
1050         void                    *priv; /* bnad's cookie */
1051 };
1052
1053 struct bna_rx_event_cbfn {
1054         /* Optional */
1055         void (*rcb_setup_cbfn)(struct bnad *, struct bna_rcb *);
1056         void (*rcb_destroy_cbfn)(struct bnad *, struct bna_rcb *);
1057         void (*ccb_setup_cbfn)(struct bnad *, struct bna_ccb *);
1058         void (*ccb_destroy_cbfn)(struct bnad *, struct bna_ccb *);
1059         /* Mandatory */
1060         void (*rx_cleanup_cbfn)(struct bnad *, struct bna_rx *);
1061         void (*rx_post_cbfn)(struct bnad *, struct bna_rx *);
1062 };
1063
1064 /* Rx module - keeps track of free, active rx objects */
1065 struct bna_rx_mod {
1066         struct bna *bna;                /* back pointer to parent */
1067         struct bna_rx *rx;              /* BFI_MAX_RXQ entries */
1068         struct bna_rxp *rxp;            /* BFI_MAX_RXQ entries */
1069         struct bna_rxq *rxq;            /* BFI_MAX_RXQ entries */
1070
1071         struct list_head                        rx_free_q;
1072         struct list_head                        rx_active_q;
1073         int                     rx_free_count;
1074
1075         struct list_head                        rxp_free_q;
1076         int                     rxp_free_count;
1077
1078         struct list_head                        rxq_free_q;
1079         int                     rxq_free_count;
1080
1081         enum bna_rx_mod_flags flags;
1082
1083         /* callback for bna_rx_mod_stop() */
1084         void (*stop_cbfn)(struct bna_enet *enet);
1085
1086         struct bfa_wc           rx_stop_wc;
1087         u32             dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX];
1088         u32             rid_mask;
1089 };
1090
1091 /**
1092  *
1093  * CAM
1094  *
1095  */
1096
1097 struct bna_ucam_mod {
1098         struct bna_mac *ucmac;          /* BFI_MAX_UCMAC entries */
1099         struct list_head                        free_q;
1100
1101         struct bna *bna;
1102 };
1103
1104 struct bna_mcam_handle {
1105         /* This should be the first one */
1106         struct list_head                        qe;
1107         int                     handle;
1108         int                     refcnt;
1109 };
1110
1111 struct bna_mcam_mod {
1112         struct bna_mac *mcmac;          /* BFI_MAX_MCMAC entries */
1113         struct bna_mcam_handle *mchandle;       /* BFI_MAX_MCMAC entries */
1114         struct list_head                        free_q;
1115         struct list_head                        free_handle_q;
1116
1117         struct bna *bna;
1118 };
1119
1120 /**
1121  *
1122  * Statistics
1123  *
1124  */
1125
1126 struct bna_tx_stats {
1127         int                     tx_state;
1128         int                     tx_flags;
1129         int                     num_txqs;
1130         u32             txq_bmap[2];
1131         int                     txf_id;
1132 };
1133
1134 struct bna_rx_stats {
1135         int                     rx_state;
1136         int                     rx_flags;
1137         int                     num_rxps;
1138         int                     num_rxqs;
1139         u32             rxq_bmap[2];
1140         u32             cq_bmap[2];
1141         int                     rxf_id;
1142         int                     rxf_state;
1143         int                     rxf_oper_state;
1144         int                     num_active_ucast;
1145         int                     num_active_mcast;
1146         int                     rxmode_active;
1147         int                     vlan_filter_status;
1148         int                     rss_status;
1149         int                     hds_status;
1150 };
1151
1152 struct bna_sw_stats {
1153         int                     device_state;
1154         int                     port_state;
1155         int                     port_flags;
1156         int                     llport_state;
1157         int                     priority;
1158         int                     num_active_tx;
1159         int                     num_active_rx;
1160 };
1161
1162 struct bna_stats {
1163         struct bna_dma_addr     hw_stats_dma;
1164         struct bfi_enet_stats   *hw_stats_kva;
1165         struct bfi_enet_stats   hw_stats;
1166 };
1167
1168 struct bna_stats_mod {
1169         bool            ioc_ready;
1170         bool            stats_get_busy;
1171         bool            stats_clr_busy;
1172         struct bfa_msgq_cmd_entry stats_get_cmd;
1173         struct bfa_msgq_cmd_entry stats_clr_cmd;
1174         struct bfi_enet_stats_req stats_get;
1175         struct bfi_enet_stats_req stats_clr;
1176 };
1177
1178 /**
1179  *
1180  * BNA
1181  *
1182  */
1183
1184 struct bna {
1185         struct bna_ident ident;
1186         struct bfa_pcidev pcidev;
1187
1188         struct bna_reg regs;
1189         struct bna_bit_defn bits;
1190
1191         struct bna_stats stats;
1192
1193         struct bna_ioceth ioceth;
1194         struct bfa_cee cee;
1195         struct bfa_msgq msgq;
1196
1197         struct bna_ethport ethport;
1198         struct bna_enet enet;
1199         struct bna_stats_mod stats_mod;
1200
1201         struct bna_tx_mod tx_mod;
1202         struct bna_rx_mod rx_mod;
1203         struct bna_ucam_mod ucam_mod;
1204         struct bna_mcam_mod mcam_mod;
1205
1206         enum bna_mod_flags mod_flags;
1207
1208         int                     default_mode_rid;
1209         int                     promisc_rid;
1210
1211         struct bnad *bnad;
1212 };
1213 #endif  /* __BNA_TYPES_H__ */