2 * Linux network driver for Brocade Converged Network Adapter.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
18 #include <linux/bitops.h>
19 #include <linux/netdevice.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_vlan.h>
25 #include <linux/if_ether.h>
27 #include <linux/prefetch.h>
28 #include <linux/module.h>
34 static DEFINE_MUTEX(bnad_fwimg_mutex);
39 static uint bnad_msix_disable;
40 module_param(bnad_msix_disable, uint, 0444);
41 MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode");
43 static uint bnad_ioc_auto_recover = 1;
44 module_param(bnad_ioc_auto_recover, uint, 0444);
45 MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery");
47 static uint bna_debugfs_enable = 1;
48 module_param(bna_debugfs_enable, uint, S_IRUGO | S_IWUSR);
49 MODULE_PARM_DESC(bna_debugfs_enable, "Enables debugfs feature, default=1,"
50 " Range[false:0|true:1]");
55 static u32 bnad_rxqs_per_cq = 2;
57 static struct mutex bnad_list_mutex;
58 static LIST_HEAD(bnad_list);
59 static const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
64 #define BNAD_GET_MBOX_IRQ(_bnad) \
65 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
66 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
67 ((_bnad)->pcidev->irq))
69 #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _size) \
71 (_res_info)->res_type = BNA_RES_T_MEM; \
72 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
73 (_res_info)->res_u.mem_info.num = (_num); \
74 (_res_info)->res_u.mem_info.len = (_size); \
78 bnad_add_to_list(struct bnad *bnad)
80 mutex_lock(&bnad_list_mutex);
81 list_add_tail(&bnad->list_entry, &bnad_list);
83 mutex_unlock(&bnad_list_mutex);
87 bnad_remove_from_list(struct bnad *bnad)
89 mutex_lock(&bnad_list_mutex);
90 list_del(&bnad->list_entry);
91 mutex_unlock(&bnad_list_mutex);
95 * Reinitialize completions in CQ, once Rx is taken down
98 bnad_cq_cleanup(struct bnad *bnad, struct bna_ccb *ccb)
100 struct bna_cq_entry *cmpl;
103 for (i = 0; i < ccb->q_depth; i++) {
104 cmpl = &((struct bna_cq_entry *)ccb->sw_q)[i];
109 /* Tx Datapath functions */
112 /* Caller should ensure that the entry at unmap_q[index] is valid */
114 bnad_tx_buff_unmap(struct bnad *bnad,
115 struct bnad_tx_unmap *unmap_q,
116 u32 q_depth, u32 index)
118 struct bnad_tx_unmap *unmap;
122 unmap = &unmap_q[index];
123 nvecs = unmap->nvecs;
128 dma_unmap_single(&bnad->pcidev->dev,
129 dma_unmap_addr(&unmap->vectors[0], dma_addr),
130 skb_headlen(skb), DMA_TO_DEVICE);
131 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, 0);
137 if (vector == BFI_TX_MAX_VECTORS_PER_WI) {
139 BNA_QE_INDX_INC(index, q_depth);
140 unmap = &unmap_q[index];
143 dma_unmap_page(&bnad->pcidev->dev,
144 dma_unmap_addr(&unmap->vectors[vector], dma_addr),
145 skb_shinfo(skb)->frags[nvecs].size, DMA_TO_DEVICE);
146 dma_unmap_addr_set(&unmap->vectors[vector], dma_addr, 0);
150 BNA_QE_INDX_INC(index, q_depth);
156 * Frees all pending Tx Bufs
157 * At this point no activity is expected on the Q,
158 * so DMA unmap & freeing is fine.
161 bnad_txq_cleanup(struct bnad *bnad, struct bna_tcb *tcb)
163 struct bnad_tx_unmap *unmap_q = tcb->unmap_q;
167 for (i = 0; i < tcb->q_depth; i++) {
168 skb = unmap_q[i].skb;
171 bnad_tx_buff_unmap(bnad, unmap_q, tcb->q_depth, i);
173 dev_kfree_skb_any(skb);
178 * bnad_txcmpl_process : Frees the Tx bufs on Tx completion
179 * Can be called in a) Interrupt context
183 bnad_txcmpl_process(struct bnad *bnad, struct bna_tcb *tcb)
185 u32 sent_packets = 0, sent_bytes = 0;
186 u32 wis, unmap_wis, hw_cons, cons, q_depth;
187 struct bnad_tx_unmap *unmap_q = tcb->unmap_q;
188 struct bnad_tx_unmap *unmap;
191 /* Just return if TX is stopped */
192 if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
195 hw_cons = *(tcb->hw_consumer_index);
196 cons = tcb->consumer_index;
197 q_depth = tcb->q_depth;
199 wis = BNA_Q_INDEX_CHANGE(cons, hw_cons, q_depth);
200 BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth)));
203 unmap = &unmap_q[cons];
208 sent_bytes += skb->len;
210 unmap_wis = BNA_TXQ_WI_NEEDED(unmap->nvecs);
213 cons = bnad_tx_buff_unmap(bnad, unmap_q, q_depth, cons);
214 dev_kfree_skb_any(skb);
217 /* Update consumer pointers. */
218 tcb->consumer_index = hw_cons;
220 tcb->txq->tx_packets += sent_packets;
221 tcb->txq->tx_bytes += sent_bytes;
227 bnad_tx_complete(struct bnad *bnad, struct bna_tcb *tcb)
229 struct net_device *netdev = bnad->netdev;
232 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
235 sent = bnad_txcmpl_process(bnad, tcb);
237 if (netif_queue_stopped(netdev) &&
238 netif_carrier_ok(netdev) &&
239 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
240 BNAD_NETIF_WAKE_THRESHOLD) {
241 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
242 netif_wake_queue(netdev);
243 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
248 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
249 bna_ib_ack(tcb->i_dbell, sent);
251 smp_mb__before_clear_bit();
252 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
257 /* MSIX Tx Completion Handler */
259 bnad_msix_tx(int irq, void *data)
261 struct bna_tcb *tcb = (struct bna_tcb *)data;
262 struct bnad *bnad = tcb->bnad;
264 bnad_tx_complete(bnad, tcb);
270 bnad_rxq_alloc_uninit(struct bnad *bnad, struct bna_rcb *rcb)
272 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
274 unmap_q->reuse_pi = -1;
275 unmap_q->alloc_order = -1;
276 unmap_q->map_size = 0;
277 unmap_q->type = BNAD_RXBUF_NONE;
280 /* Default is page-based allocation. Multi-buffer support - TBD */
282 bnad_rxq_alloc_init(struct bnad *bnad, struct bna_rcb *rcb)
284 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
287 bnad_rxq_alloc_uninit(bnad, rcb);
289 order = get_order(rcb->rxq->buffer_size);
291 unmap_q->type = BNAD_RXBUF_PAGE;
293 if (bna_is_small_rxq(rcb->id)) {
294 unmap_q->alloc_order = 0;
295 unmap_q->map_size = rcb->rxq->buffer_size;
297 if (rcb->rxq->multi_buffer) {
298 unmap_q->alloc_order = 0;
299 unmap_q->map_size = rcb->rxq->buffer_size;
300 unmap_q->type = BNAD_RXBUF_MULTI_BUFF;
302 unmap_q->alloc_order = order;
304 (rcb->rxq->buffer_size > 2048) ?
305 PAGE_SIZE << order : 2048;
309 BUG_ON(((PAGE_SIZE << order) % unmap_q->map_size));
315 bnad_rxq_cleanup_page(struct bnad *bnad, struct bnad_rx_unmap *unmap)
320 dma_unmap_page(&bnad->pcidev->dev,
321 dma_unmap_addr(&unmap->vector, dma_addr),
322 unmap->vector.len, DMA_FROM_DEVICE);
323 put_page(unmap->page);
325 dma_unmap_addr_set(&unmap->vector, dma_addr, 0);
326 unmap->vector.len = 0;
330 bnad_rxq_cleanup_skb(struct bnad *bnad, struct bnad_rx_unmap *unmap)
335 dma_unmap_single(&bnad->pcidev->dev,
336 dma_unmap_addr(&unmap->vector, dma_addr),
337 unmap->vector.len, DMA_FROM_DEVICE);
338 dev_kfree_skb_any(unmap->skb);
340 dma_unmap_addr_set(&unmap->vector, dma_addr, 0);
341 unmap->vector.len = 0;
345 bnad_rxq_cleanup(struct bnad *bnad, struct bna_rcb *rcb)
347 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
350 for (i = 0; i < rcb->q_depth; i++) {
351 struct bnad_rx_unmap *unmap = &unmap_q->unmap[i];
353 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
354 bnad_rxq_cleanup_skb(bnad, unmap);
356 bnad_rxq_cleanup_page(bnad, unmap);
358 bnad_rxq_alloc_uninit(bnad, rcb);
362 bnad_rxq_refill_page(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc)
364 u32 alloced, prod, q_depth;
365 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
366 struct bnad_rx_unmap *unmap, *prev;
367 struct bna_rxq_entry *rxent;
369 u32 page_offset, alloc_size;
372 prod = rcb->producer_index;
373 q_depth = rcb->q_depth;
375 alloc_size = PAGE_SIZE << unmap_q->alloc_order;
379 unmap = &unmap_q->unmap[prod];
381 if (unmap_q->reuse_pi < 0) {
382 page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
383 unmap_q->alloc_order);
386 prev = &unmap_q->unmap[unmap_q->reuse_pi];
388 page_offset = prev->page_offset + unmap_q->map_size;
392 if (unlikely(!page)) {
393 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
394 rcb->rxq->rxbuf_alloc_failed++;
398 dma_addr = dma_map_page(&bnad->pcidev->dev, page, page_offset,
399 unmap_q->map_size, DMA_FROM_DEVICE);
402 unmap->page_offset = page_offset;
403 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr);
404 unmap->vector.len = unmap_q->map_size;
405 page_offset += unmap_q->map_size;
407 if (page_offset < alloc_size)
408 unmap_q->reuse_pi = prod;
410 unmap_q->reuse_pi = -1;
412 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod];
413 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
414 BNA_QE_INDX_INC(prod, q_depth);
419 if (likely(alloced)) {
420 rcb->producer_index = prod;
422 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags)))
423 bna_rxq_prod_indx_doorbell(rcb);
430 bnad_rxq_refill_skb(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc)
432 u32 alloced, prod, q_depth, buff_sz;
433 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
434 struct bnad_rx_unmap *unmap;
435 struct bna_rxq_entry *rxent;
439 buff_sz = rcb->rxq->buffer_size;
440 prod = rcb->producer_index;
441 q_depth = rcb->q_depth;
445 unmap = &unmap_q->unmap[prod];
447 skb = netdev_alloc_skb_ip_align(bnad->netdev, buff_sz);
449 if (unlikely(!skb)) {
450 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
451 rcb->rxq->rxbuf_alloc_failed++;
454 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
455 buff_sz, DMA_FROM_DEVICE);
458 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr);
459 unmap->vector.len = buff_sz;
461 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod];
462 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
463 BNA_QE_INDX_INC(prod, q_depth);
468 if (likely(alloced)) {
469 rcb->producer_index = prod;
471 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags)))
472 bna_rxq_prod_indx_doorbell(rcb);
479 bnad_rxq_post(struct bnad *bnad, struct bna_rcb *rcb)
481 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
484 to_alloc = BNA_QE_FREE_CNT(rcb, rcb->q_depth);
485 if (!(to_alloc >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT))
488 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
489 bnad_rxq_refill_skb(bnad, rcb, to_alloc);
491 bnad_rxq_refill_page(bnad, rcb, to_alloc);
494 #define flags_cksum_prot_mask (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
496 BNA_CQ_EF_TCP | BNA_CQ_EF_UDP | \
497 BNA_CQ_EF_L4_CKSUM_OK)
499 #define flags_tcp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
500 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
501 #define flags_tcp6 (BNA_CQ_EF_IPV6 | \
502 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
503 #define flags_udp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
504 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
505 #define flags_udp6 (BNA_CQ_EF_IPV6 | \
506 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
509 bnad_cq_drop_packet(struct bnad *bnad, struct bna_rcb *rcb,
510 u32 sop_ci, u32 nvecs)
512 struct bnad_rx_unmap_q *unmap_q;
513 struct bnad_rx_unmap *unmap;
516 unmap_q = rcb->unmap_q;
517 for (vec = 0, ci = sop_ci; vec < nvecs; vec++) {
518 unmap = &unmap_q->unmap[ci];
519 BNA_QE_INDX_INC(ci, rcb->q_depth);
521 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
522 bnad_rxq_cleanup_skb(bnad, unmap);
524 bnad_rxq_cleanup_page(bnad, unmap);
529 bnad_cq_setup_skb_frags(struct bna_rcb *rcb, struct sk_buff *skb,
530 u32 sop_ci, u32 nvecs, u32 last_fraglen)
533 u32 ci, vec, len, totlen = 0;
534 struct bnad_rx_unmap_q *unmap_q;
535 struct bnad_rx_unmap *unmap;
537 unmap_q = rcb->unmap_q;
540 /* prefetch header */
541 prefetch(page_address(unmap_q->unmap[sop_ci].page) +
542 unmap_q->unmap[sop_ci].page_offset);
544 for (vec = 1, ci = sop_ci; vec <= nvecs; vec++) {
545 unmap = &unmap_q->unmap[ci];
546 BNA_QE_INDX_INC(ci, rcb->q_depth);
548 dma_unmap_page(&bnad->pcidev->dev,
549 dma_unmap_addr(&unmap->vector, dma_addr),
550 unmap->vector.len, DMA_FROM_DEVICE);
552 len = (vec == nvecs) ?
553 last_fraglen : unmap->vector.len;
556 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
557 unmap->page, unmap->page_offset, len);
560 unmap->vector.len = 0;
564 skb->data_len += totlen;
565 skb->truesize += totlen;
569 bnad_cq_setup_skb(struct bnad *bnad, struct sk_buff *skb,
570 struct bnad_rx_unmap *unmap, u32 len)
574 dma_unmap_single(&bnad->pcidev->dev,
575 dma_unmap_addr(&unmap->vector, dma_addr),
576 unmap->vector.len, DMA_FROM_DEVICE);
579 skb->protocol = eth_type_trans(skb, bnad->netdev);
582 unmap->vector.len = 0;
586 bnad_cq_process(struct bnad *bnad, struct bna_ccb *ccb, int budget)
588 struct bna_cq_entry *cq, *cmpl, *next_cmpl;
589 struct bna_rcb *rcb = NULL;
590 struct bnad_rx_unmap_q *unmap_q;
591 struct bnad_rx_unmap *unmap = NULL;
592 struct sk_buff *skb = NULL;
593 struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
594 struct bnad_rx_ctrl *rx_ctrl = ccb->ctrl;
595 u32 packets = 0, len = 0, totlen = 0;
596 u32 pi, vec, sop_ci = 0, nvecs = 0;
597 u32 flags, masked_flags;
599 prefetch(bnad->netdev);
602 cmpl = &cq[ccb->producer_index];
604 while (cmpl->valid && (packets < budget)) {
605 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
607 if (bna_is_small_rxq(cmpl->rxq_id))
612 unmap_q = rcb->unmap_q;
614 /* start of packet ci */
615 sop_ci = rcb->consumer_index;
617 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) {
618 unmap = &unmap_q->unmap[sop_ci];
621 skb = napi_get_frags(&rx_ctrl->napi);
627 flags = ntohl(cmpl->flags);
628 len = ntohs(cmpl->length);
632 /* Check all the completions for this frame.
633 * busy-wait doesn't help much, break here.
635 if (BNAD_RXBUF_IS_MULTI_BUFF(unmap_q->type) &&
636 (flags & BNA_CQ_EF_EOP) == 0) {
637 pi = ccb->producer_index;
639 BNA_QE_INDX_INC(pi, ccb->q_depth);
642 if (!next_cmpl->valid)
645 len = ntohs(next_cmpl->length);
646 flags = ntohl(next_cmpl->flags);
650 } while ((flags & BNA_CQ_EF_EOP) == 0);
652 if (!next_cmpl->valid)
656 /* TODO: BNA_CQ_EF_LOCAL ? */
657 if (unlikely(flags & (BNA_CQ_EF_MAC_ERROR |
658 BNA_CQ_EF_FCS_ERROR |
659 BNA_CQ_EF_TOO_LONG))) {
660 bnad_cq_drop_packet(bnad, rcb, sop_ci, nvecs);
661 rcb->rxq->rx_packets_with_error++;
666 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
667 bnad_cq_setup_skb(bnad, skb, unmap, len);
669 bnad_cq_setup_skb_frags(rcb, skb, sop_ci, nvecs, len);
672 rcb->rxq->rx_packets++;
673 rcb->rxq->rx_bytes += totlen;
674 ccb->bytes_per_intr += totlen;
676 masked_flags = flags & flags_cksum_prot_mask;
679 ((bnad->netdev->features & NETIF_F_RXCSUM) &&
680 ((masked_flags == flags_tcp4) ||
681 (masked_flags == flags_udp4) ||
682 (masked_flags == flags_tcp6) ||
683 (masked_flags == flags_udp6))))
684 skb->ip_summed = CHECKSUM_UNNECESSARY;
686 skb_checksum_none_assert(skb);
688 if (flags & BNA_CQ_EF_VLAN)
689 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(cmpl->vlan_tag));
691 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
692 netif_receive_skb(skb);
694 napi_gro_frags(&rx_ctrl->napi);
697 BNA_QE_INDX_ADD(rcb->consumer_index, nvecs, rcb->q_depth);
698 for (vec = 0; vec < nvecs; vec++) {
699 cmpl = &cq[ccb->producer_index];
701 BNA_QE_INDX_INC(ccb->producer_index, ccb->q_depth);
703 cmpl = &cq[ccb->producer_index];
706 napi_gro_flush(&rx_ctrl->napi, false);
707 if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
708 bna_ib_ack_disable_irq(ccb->i_dbell, packets);
710 bnad_rxq_post(bnad, ccb->rcb[0]);
712 bnad_rxq_post(bnad, ccb->rcb[1]);
718 bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
720 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
721 struct napi_struct *napi = &rx_ctrl->napi;
723 if (likely(napi_schedule_prep(napi))) {
724 __napi_schedule(napi);
725 rx_ctrl->rx_schedule++;
729 /* MSIX Rx Path Handler */
731 bnad_msix_rx(int irq, void *data)
733 struct bna_ccb *ccb = (struct bna_ccb *)data;
736 ((struct bnad_rx_ctrl *)(ccb->ctrl))->rx_intr_ctr++;
737 bnad_netif_rx_schedule_poll(ccb->bnad, ccb);
743 /* Interrupt handlers */
745 /* Mbox Interrupt Handlers */
747 bnad_msix_mbox_handler(int irq, void *data)
751 struct bnad *bnad = (struct bnad *)data;
753 spin_lock_irqsave(&bnad->bna_lock, flags);
754 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
755 spin_unlock_irqrestore(&bnad->bna_lock, flags);
759 bna_intr_status_get(&bnad->bna, intr_status);
761 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
762 bna_mbox_handler(&bnad->bna, intr_status);
764 spin_unlock_irqrestore(&bnad->bna_lock, flags);
770 bnad_isr(int irq, void *data)
775 struct bnad *bnad = (struct bnad *)data;
776 struct bnad_rx_info *rx_info;
777 struct bnad_rx_ctrl *rx_ctrl;
778 struct bna_tcb *tcb = NULL;
780 spin_lock_irqsave(&bnad->bna_lock, flags);
781 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
782 spin_unlock_irqrestore(&bnad->bna_lock, flags);
786 bna_intr_status_get(&bnad->bna, intr_status);
788 if (unlikely(!intr_status)) {
789 spin_unlock_irqrestore(&bnad->bna_lock, flags);
793 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
794 bna_mbox_handler(&bnad->bna, intr_status);
796 spin_unlock_irqrestore(&bnad->bna_lock, flags);
798 if (!BNA_IS_INTX_DATA_INTR(intr_status))
801 /* Process data interrupts */
803 for (i = 0; i < bnad->num_tx; i++) {
804 for (j = 0; j < bnad->num_txq_per_tx; j++) {
805 tcb = bnad->tx_info[i].tcb[j];
806 if (tcb && test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
807 bnad_tx_complete(bnad, bnad->tx_info[i].tcb[j]);
811 for (i = 0; i < bnad->num_rx; i++) {
812 rx_info = &bnad->rx_info[i];
815 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
816 rx_ctrl = &rx_info->rx_ctrl[j];
818 bnad_netif_rx_schedule_poll(bnad,
826 * Called in interrupt / callback context
827 * with bna_lock held, so cfg_flags access is OK
830 bnad_enable_mbox_irq(struct bnad *bnad)
832 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
834 BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
838 * Called with bnad->bna_lock held b'cos of
839 * bnad->cfg_flags access.
842 bnad_disable_mbox_irq(struct bnad *bnad)
844 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
846 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
850 bnad_set_netdev_perm_addr(struct bnad *bnad)
852 struct net_device *netdev = bnad->netdev;
854 memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len);
855 if (is_zero_ether_addr(netdev->dev_addr))
856 memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len);
859 /* Control Path Handlers */
863 bnad_cb_mbox_intr_enable(struct bnad *bnad)
865 bnad_enable_mbox_irq(bnad);
869 bnad_cb_mbox_intr_disable(struct bnad *bnad)
871 bnad_disable_mbox_irq(bnad);
875 bnad_cb_ioceth_ready(struct bnad *bnad)
877 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
878 complete(&bnad->bnad_completions.ioc_comp);
882 bnad_cb_ioceth_failed(struct bnad *bnad)
884 bnad->bnad_completions.ioc_comp_status = BNA_CB_FAIL;
885 complete(&bnad->bnad_completions.ioc_comp);
889 bnad_cb_ioceth_disabled(struct bnad *bnad)
891 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
892 complete(&bnad->bnad_completions.ioc_comp);
896 bnad_cb_enet_disabled(void *arg)
898 struct bnad *bnad = (struct bnad *)arg;
900 netif_carrier_off(bnad->netdev);
901 complete(&bnad->bnad_completions.enet_comp);
905 bnad_cb_ethport_link_status(struct bnad *bnad,
906 enum bna_link_status link_status)
908 bool link_up = false;
910 link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP);
912 if (link_status == BNA_CEE_UP) {
913 if (!test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
914 BNAD_UPDATE_CTR(bnad, cee_toggle);
915 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
917 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
918 BNAD_UPDATE_CTR(bnad, cee_toggle);
919 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
923 if (!netif_carrier_ok(bnad->netdev)) {
925 printk(KERN_WARNING "bna: %s link up\n",
927 netif_carrier_on(bnad->netdev);
928 BNAD_UPDATE_CTR(bnad, link_toggle);
929 for (tx_id = 0; tx_id < bnad->num_tx; tx_id++) {
930 for (tcb_id = 0; tcb_id < bnad->num_txq_per_tx;
932 struct bna_tcb *tcb =
933 bnad->tx_info[tx_id].tcb[tcb_id];
940 if (test_bit(BNAD_TXQ_TX_STARTED,
944 * Transmit Schedule */
945 printk(KERN_INFO "bna: %s %d "
952 BNAD_UPDATE_CTR(bnad,
958 BNAD_UPDATE_CTR(bnad,
965 if (netif_carrier_ok(bnad->netdev)) {
966 printk(KERN_WARNING "bna: %s link down\n",
968 netif_carrier_off(bnad->netdev);
969 BNAD_UPDATE_CTR(bnad, link_toggle);
975 bnad_cb_tx_disabled(void *arg, struct bna_tx *tx)
977 struct bnad *bnad = (struct bnad *)arg;
979 complete(&bnad->bnad_completions.tx_comp);
983 bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb)
985 struct bnad_tx_info *tx_info =
986 (struct bnad_tx_info *)tcb->txq->tx->priv;
989 tx_info->tcb[tcb->id] = tcb;
993 bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
995 struct bnad_tx_info *tx_info =
996 (struct bnad_tx_info *)tcb->txq->tx->priv;
998 tx_info->tcb[tcb->id] = NULL;
1003 bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
1005 struct bnad_rx_info *rx_info =
1006 (struct bnad_rx_info *)ccb->cq->rx->priv;
1008 rx_info->rx_ctrl[ccb->id].ccb = ccb;
1009 ccb->ctrl = &rx_info->rx_ctrl[ccb->id];
1013 bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb)
1015 struct bnad_rx_info *rx_info =
1016 (struct bnad_rx_info *)ccb->cq->rx->priv;
1018 rx_info->rx_ctrl[ccb->id].ccb = NULL;
1022 bnad_cb_tx_stall(struct bnad *bnad, struct bna_tx *tx)
1024 struct bnad_tx_info *tx_info =
1025 (struct bnad_tx_info *)tx->priv;
1026 struct bna_tcb *tcb;
1030 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1031 tcb = tx_info->tcb[i];
1035 clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
1036 netif_stop_subqueue(bnad->netdev, txq_id);
1037 printk(KERN_INFO "bna: %s %d TXQ_STOPPED\n",
1038 bnad->netdev->name, txq_id);
1043 bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx)
1045 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
1046 struct bna_tcb *tcb;
1050 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1051 tcb = tx_info->tcb[i];
1056 BUG_ON(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags));
1057 set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
1058 BUG_ON(*(tcb->hw_consumer_index) != 0);
1060 if (netif_carrier_ok(bnad->netdev)) {
1061 printk(KERN_INFO "bna: %s %d TXQ_STARTED\n",
1062 bnad->netdev->name, txq_id);
1063 netif_wake_subqueue(bnad->netdev, txq_id);
1064 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
1069 * Workaround for first ioceth enable failure & we
1070 * get a 0 MAC address. We try to get the MAC address
1073 if (is_zero_ether_addr(&bnad->perm_addr.mac[0])) {
1074 bna_enet_perm_mac_get(&bnad->bna.enet, &bnad->perm_addr);
1075 bnad_set_netdev_perm_addr(bnad);
1080 * Free all TxQs buffers and then notify TX_E_CLEANUP_DONE to Tx fsm.
1083 bnad_tx_cleanup(struct delayed_work *work)
1085 struct bnad_tx_info *tx_info =
1086 container_of(work, struct bnad_tx_info, tx_cleanup_work);
1087 struct bnad *bnad = NULL;
1088 struct bna_tcb *tcb;
1089 unsigned long flags;
1092 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1093 tcb = tx_info->tcb[i];
1099 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
1104 bnad_txq_cleanup(bnad, tcb);
1106 smp_mb__before_clear_bit();
1107 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
1111 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work,
1112 msecs_to_jiffies(1));
1116 spin_lock_irqsave(&bnad->bna_lock, flags);
1117 bna_tx_cleanup_complete(tx_info->tx);
1118 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1122 bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tx *tx)
1124 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
1125 struct bna_tcb *tcb;
1128 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1129 tcb = tx_info->tcb[i];
1134 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 0);
1138 bnad_cb_rx_stall(struct bnad *bnad, struct bna_rx *rx)
1140 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1141 struct bna_ccb *ccb;
1142 struct bnad_rx_ctrl *rx_ctrl;
1145 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1146 rx_ctrl = &rx_info->rx_ctrl[i];
1151 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[0]->flags);
1154 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[1]->flags);
1159 * Free all RxQs buffers and then notify RX_E_CLEANUP_DONE to Rx fsm.
1162 bnad_rx_cleanup(void *work)
1164 struct bnad_rx_info *rx_info =
1165 container_of(work, struct bnad_rx_info, rx_cleanup_work);
1166 struct bnad_rx_ctrl *rx_ctrl;
1167 struct bnad *bnad = NULL;
1168 unsigned long flags;
1171 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1172 rx_ctrl = &rx_info->rx_ctrl[i];
1177 bnad = rx_ctrl->ccb->bnad;
1180 * Wait till the poll handler has exited
1181 * and nothing can be scheduled anymore
1183 napi_disable(&rx_ctrl->napi);
1185 bnad_cq_cleanup(bnad, rx_ctrl->ccb);
1186 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[0]);
1187 if (rx_ctrl->ccb->rcb[1])
1188 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[1]);
1191 spin_lock_irqsave(&bnad->bna_lock, flags);
1192 bna_rx_cleanup_complete(rx_info->rx);
1193 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1197 bnad_cb_rx_cleanup(struct bnad *bnad, struct bna_rx *rx)
1199 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1200 struct bna_ccb *ccb;
1201 struct bnad_rx_ctrl *rx_ctrl;
1204 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1205 rx_ctrl = &rx_info->rx_ctrl[i];
1210 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
1213 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
1216 queue_work(bnad->work_q, &rx_info->rx_cleanup_work);
1220 bnad_cb_rx_post(struct bnad *bnad, struct bna_rx *rx)
1222 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1223 struct bna_ccb *ccb;
1224 struct bna_rcb *rcb;
1225 struct bnad_rx_ctrl *rx_ctrl;
1228 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1229 rx_ctrl = &rx_info->rx_ctrl[i];
1234 napi_enable(&rx_ctrl->napi);
1236 for (j = 0; j < BNAD_MAX_RXQ_PER_RXP; j++) {
1241 bnad_rxq_alloc_init(bnad, rcb);
1242 set_bit(BNAD_RXQ_STARTED, &rcb->flags);
1243 set_bit(BNAD_RXQ_POST_OK, &rcb->flags);
1244 bnad_rxq_post(bnad, rcb);
1250 bnad_cb_rx_disabled(void *arg, struct bna_rx *rx)
1252 struct bnad *bnad = (struct bnad *)arg;
1254 complete(&bnad->bnad_completions.rx_comp);
1258 bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx)
1260 bnad->bnad_completions.mcast_comp_status = BNA_CB_SUCCESS;
1261 complete(&bnad->bnad_completions.mcast_comp);
1265 bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
1266 struct bna_stats *stats)
1268 if (status == BNA_CB_SUCCESS)
1269 BNAD_UPDATE_CTR(bnad, hw_stats_updates);
1271 if (!netif_running(bnad->netdev) ||
1272 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1275 mod_timer(&bnad->stats_timer,
1276 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1280 bnad_cb_enet_mtu_set(struct bnad *bnad)
1282 bnad->bnad_completions.mtu_comp_status = BNA_CB_SUCCESS;
1283 complete(&bnad->bnad_completions.mtu_comp);
1287 bnad_cb_completion(void *arg, enum bfa_status status)
1289 struct bnad_iocmd_comp *iocmd_comp =
1290 (struct bnad_iocmd_comp *)arg;
1292 iocmd_comp->comp_status = (u32) status;
1293 complete(&iocmd_comp->comp);
1296 /* Resource allocation, free functions */
1299 bnad_mem_free(struct bnad *bnad,
1300 struct bna_mem_info *mem_info)
1305 if (mem_info->mdl == NULL)
1308 for (i = 0; i < mem_info->num; i++) {
1309 if (mem_info->mdl[i].kva != NULL) {
1310 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1311 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma),
1313 dma_free_coherent(&bnad->pcidev->dev,
1314 mem_info->mdl[i].len,
1315 mem_info->mdl[i].kva, dma_pa);
1317 kfree(mem_info->mdl[i].kva);
1320 kfree(mem_info->mdl);
1321 mem_info->mdl = NULL;
1325 bnad_mem_alloc(struct bnad *bnad,
1326 struct bna_mem_info *mem_info)
1331 if ((mem_info->num == 0) || (mem_info->len == 0)) {
1332 mem_info->mdl = NULL;
1336 mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr),
1338 if (mem_info->mdl == NULL)
1341 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1342 for (i = 0; i < mem_info->num; i++) {
1343 mem_info->mdl[i].len = mem_info->len;
1344 mem_info->mdl[i].kva =
1345 dma_alloc_coherent(&bnad->pcidev->dev,
1346 mem_info->len, &dma_pa,
1348 if (mem_info->mdl[i].kva == NULL)
1351 BNA_SET_DMA_ADDR(dma_pa,
1352 &(mem_info->mdl[i].dma));
1355 for (i = 0; i < mem_info->num; i++) {
1356 mem_info->mdl[i].len = mem_info->len;
1357 mem_info->mdl[i].kva = kzalloc(mem_info->len,
1359 if (mem_info->mdl[i].kva == NULL)
1367 bnad_mem_free(bnad, mem_info);
1371 /* Free IRQ for Mailbox */
1373 bnad_mbox_irq_free(struct bnad *bnad)
1376 unsigned long flags;
1378 spin_lock_irqsave(&bnad->bna_lock, flags);
1379 bnad_disable_mbox_irq(bnad);
1380 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1382 irq = BNAD_GET_MBOX_IRQ(bnad);
1383 free_irq(irq, bnad);
1387 * Allocates IRQ for Mailbox, but keep it disabled
1388 * This will be enabled once we get the mbox enable callback
1392 bnad_mbox_irq_alloc(struct bnad *bnad)
1395 unsigned long irq_flags, flags;
1397 irq_handler_t irq_handler;
1399 spin_lock_irqsave(&bnad->bna_lock, flags);
1400 if (bnad->cfg_flags & BNAD_CF_MSIX) {
1401 irq_handler = (irq_handler_t)bnad_msix_mbox_handler;
1402 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
1405 irq_handler = (irq_handler_t)bnad_isr;
1406 irq = bnad->pcidev->irq;
1407 irq_flags = IRQF_SHARED;
1410 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1411 sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME);
1414 * Set the Mbox IRQ disable flag, so that the IRQ handler
1415 * called from request_irq() for SHARED IRQs do not execute
1417 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
1419 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
1421 err = request_irq(irq, irq_handler, irq_flags,
1422 bnad->mbox_irq_name, bnad);
1428 bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info)
1430 kfree(intr_info->idl);
1431 intr_info->idl = NULL;
1434 /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1436 bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src,
1437 u32 txrx_id, struct bna_intr_info *intr_info)
1439 int i, vector_start = 0;
1441 unsigned long flags;
1443 spin_lock_irqsave(&bnad->bna_lock, flags);
1444 cfg_flags = bnad->cfg_flags;
1445 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1447 if (cfg_flags & BNAD_CF_MSIX) {
1448 intr_info->intr_type = BNA_INTR_T_MSIX;
1449 intr_info->idl = kcalloc(intr_info->num,
1450 sizeof(struct bna_intr_descr),
1452 if (!intr_info->idl)
1457 vector_start = BNAD_MAILBOX_MSIX_VECTORS + txrx_id;
1461 vector_start = BNAD_MAILBOX_MSIX_VECTORS +
1462 (bnad->num_tx * bnad->num_txq_per_tx) +
1470 for (i = 0; i < intr_info->num; i++)
1471 intr_info->idl[i].vector = vector_start + i;
1473 intr_info->intr_type = BNA_INTR_T_INTX;
1475 intr_info->idl = kcalloc(intr_info->num,
1476 sizeof(struct bna_intr_descr),
1478 if (!intr_info->idl)
1483 intr_info->idl[0].vector = BNAD_INTX_TX_IB_BITMASK;
1487 intr_info->idl[0].vector = BNAD_INTX_RX_IB_BITMASK;
1494 /* NOTE: Should be called for MSIX only
1495 * Unregisters Tx MSIX vector(s) from the kernel
1498 bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info,
1504 for (i = 0; i < num_txqs; i++) {
1505 if (tx_info->tcb[i] == NULL)
1508 vector_num = tx_info->tcb[i]->intr_vector;
1509 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]);
1513 /* NOTE: Should be called for MSIX only
1514 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1517 bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info,
1518 u32 tx_id, int num_txqs)
1524 for (i = 0; i < num_txqs; i++) {
1525 vector_num = tx_info->tcb[i]->intr_vector;
1526 sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name,
1527 tx_id + tx_info->tcb[i]->id);
1528 err = request_irq(bnad->msix_table[vector_num].vector,
1529 (irq_handler_t)bnad_msix_tx, 0,
1530 tx_info->tcb[i]->name,
1540 bnad_tx_msix_unregister(bnad, tx_info, (i - 1));
1544 /* NOTE: Should be called for MSIX only
1545 * Unregisters Rx MSIX vector(s) from the kernel
1548 bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info,
1554 for (i = 0; i < num_rxps; i++) {
1555 if (rx_info->rx_ctrl[i].ccb == NULL)
1558 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1559 free_irq(bnad->msix_table[vector_num].vector,
1560 rx_info->rx_ctrl[i].ccb);
1564 /* NOTE: Should be called for MSIX only
1565 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1568 bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info,
1569 u32 rx_id, int num_rxps)
1575 for (i = 0; i < num_rxps; i++) {
1576 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1577 sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d",
1579 rx_id + rx_info->rx_ctrl[i].ccb->id);
1580 err = request_irq(bnad->msix_table[vector_num].vector,
1581 (irq_handler_t)bnad_msix_rx, 0,
1582 rx_info->rx_ctrl[i].ccb->name,
1583 rx_info->rx_ctrl[i].ccb);
1592 bnad_rx_msix_unregister(bnad, rx_info, (i - 1));
1596 /* Free Tx object Resources */
1598 bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1602 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1603 if (res_info[i].res_type == BNA_RES_T_MEM)
1604 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1605 else if (res_info[i].res_type == BNA_RES_T_INTR)
1606 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1610 /* Allocates memory and interrupt resources for Tx object */
1612 bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1617 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1618 if (res_info[i].res_type == BNA_RES_T_MEM)
1619 err = bnad_mem_alloc(bnad,
1620 &res_info[i].res_u.mem_info);
1621 else if (res_info[i].res_type == BNA_RES_T_INTR)
1622 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id,
1623 &res_info[i].res_u.intr_info);
1630 bnad_tx_res_free(bnad, res_info);
1634 /* Free Rx object Resources */
1636 bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1640 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1641 if (res_info[i].res_type == BNA_RES_T_MEM)
1642 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1643 else if (res_info[i].res_type == BNA_RES_T_INTR)
1644 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1648 /* Allocates memory and interrupt resources for Rx object */
1650 bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1655 /* All memory needs to be allocated before setup_ccbs */
1656 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1657 if (res_info[i].res_type == BNA_RES_T_MEM)
1658 err = bnad_mem_alloc(bnad,
1659 &res_info[i].res_u.mem_info);
1660 else if (res_info[i].res_type == BNA_RES_T_INTR)
1661 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id,
1662 &res_info[i].res_u.intr_info);
1669 bnad_rx_res_free(bnad, res_info);
1673 /* Timer callbacks */
1676 bnad_ioc_timeout(unsigned long data)
1678 struct bnad *bnad = (struct bnad *)data;
1679 unsigned long flags;
1681 spin_lock_irqsave(&bnad->bna_lock, flags);
1682 bfa_nw_ioc_timeout((void *) &bnad->bna.ioceth.ioc);
1683 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1687 bnad_ioc_hb_check(unsigned long data)
1689 struct bnad *bnad = (struct bnad *)data;
1690 unsigned long flags;
1692 spin_lock_irqsave(&bnad->bna_lock, flags);
1693 bfa_nw_ioc_hb_check((void *) &bnad->bna.ioceth.ioc);
1694 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1698 bnad_iocpf_timeout(unsigned long data)
1700 struct bnad *bnad = (struct bnad *)data;
1701 unsigned long flags;
1703 spin_lock_irqsave(&bnad->bna_lock, flags);
1704 bfa_nw_iocpf_timeout((void *) &bnad->bna.ioceth.ioc);
1705 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1709 bnad_iocpf_sem_timeout(unsigned long data)
1711 struct bnad *bnad = (struct bnad *)data;
1712 unsigned long flags;
1714 spin_lock_irqsave(&bnad->bna_lock, flags);
1715 bfa_nw_iocpf_sem_timeout((void *) &bnad->bna.ioceth.ioc);
1716 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1720 * All timer routines use bnad->bna_lock to protect against
1721 * the following race, which may occur in case of no locking:
1729 /* b) Dynamic Interrupt Moderation Timer */
1731 bnad_dim_timeout(unsigned long data)
1733 struct bnad *bnad = (struct bnad *)data;
1734 struct bnad_rx_info *rx_info;
1735 struct bnad_rx_ctrl *rx_ctrl;
1737 unsigned long flags;
1739 if (!netif_carrier_ok(bnad->netdev))
1742 spin_lock_irqsave(&bnad->bna_lock, flags);
1743 for (i = 0; i < bnad->num_rx; i++) {
1744 rx_info = &bnad->rx_info[i];
1747 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1748 rx_ctrl = &rx_info->rx_ctrl[j];
1751 bna_rx_dim_update(rx_ctrl->ccb);
1755 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1756 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags))
1757 mod_timer(&bnad->dim_timer,
1758 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1759 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1762 /* c) Statistics Timer */
1764 bnad_stats_timeout(unsigned long data)
1766 struct bnad *bnad = (struct bnad *)data;
1767 unsigned long flags;
1769 if (!netif_running(bnad->netdev) ||
1770 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1773 spin_lock_irqsave(&bnad->bna_lock, flags);
1774 bna_hw_stats_get(&bnad->bna);
1775 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1779 * Set up timer for DIM
1780 * Called with bnad->bna_lock held
1783 bnad_dim_timer_start(struct bnad *bnad)
1785 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
1786 !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
1787 setup_timer(&bnad->dim_timer, bnad_dim_timeout,
1788 (unsigned long)bnad);
1789 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1790 mod_timer(&bnad->dim_timer,
1791 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1796 * Set up timer for statistics
1797 * Called with mutex_lock(&bnad->conf_mutex) held
1800 bnad_stats_timer_start(struct bnad *bnad)
1802 unsigned long flags;
1804 spin_lock_irqsave(&bnad->bna_lock, flags);
1805 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) {
1806 setup_timer(&bnad->stats_timer, bnad_stats_timeout,
1807 (unsigned long)bnad);
1808 mod_timer(&bnad->stats_timer,
1809 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1811 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1815 * Stops the stats timer
1816 * Called with mutex_lock(&bnad->conf_mutex) held
1819 bnad_stats_timer_stop(struct bnad *bnad)
1822 unsigned long flags;
1824 spin_lock_irqsave(&bnad->bna_lock, flags);
1825 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1827 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1829 del_timer_sync(&bnad->stats_timer);
1835 bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
1837 int i = 1; /* Index 0 has broadcast address */
1838 struct netdev_hw_addr *mc_addr;
1840 netdev_for_each_mc_addr(mc_addr, netdev) {
1841 memcpy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0],
1848 bnad_napi_poll_rx(struct napi_struct *napi, int budget)
1850 struct bnad_rx_ctrl *rx_ctrl =
1851 container_of(napi, struct bnad_rx_ctrl, napi);
1852 struct bnad *bnad = rx_ctrl->bnad;
1855 rx_ctrl->rx_poll_ctr++;
1857 if (!netif_carrier_ok(bnad->netdev))
1860 rcvd = bnad_cq_process(bnad, rx_ctrl->ccb, budget);
1865 napi_complete(napi);
1867 rx_ctrl->rx_complete++;
1870 bnad_enable_rx_irq_unsafe(rx_ctrl->ccb);
1875 #define BNAD_NAPI_POLL_QUOTA 64
1877 bnad_napi_add(struct bnad *bnad, u32 rx_id)
1879 struct bnad_rx_ctrl *rx_ctrl;
1882 /* Initialize & enable NAPI */
1883 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1884 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
1885 netif_napi_add(bnad->netdev, &rx_ctrl->napi,
1886 bnad_napi_poll_rx, BNAD_NAPI_POLL_QUOTA);
1891 bnad_napi_delete(struct bnad *bnad, u32 rx_id)
1895 /* First disable and then clean up */
1896 for (i = 0; i < bnad->num_rxp_per_rx; i++)
1897 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
1900 /* Should be held with conf_lock held */
1902 bnad_destroy_tx(struct bnad *bnad, u32 tx_id)
1904 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1905 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1906 unsigned long flags;
1911 init_completion(&bnad->bnad_completions.tx_comp);
1912 spin_lock_irqsave(&bnad->bna_lock, flags);
1913 bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled);
1914 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1915 wait_for_completion(&bnad->bnad_completions.tx_comp);
1917 if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
1918 bnad_tx_msix_unregister(bnad, tx_info,
1919 bnad->num_txq_per_tx);
1921 spin_lock_irqsave(&bnad->bna_lock, flags);
1922 bna_tx_destroy(tx_info->tx);
1923 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1928 bnad_tx_res_free(bnad, res_info);
1931 /* Should be held with conf_lock held */
1933 bnad_setup_tx(struct bnad *bnad, u32 tx_id)
1936 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1937 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1938 struct bna_intr_info *intr_info =
1939 &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
1940 struct bna_tx_config *tx_config = &bnad->tx_config[tx_id];
1941 static const struct bna_tx_event_cbfn tx_cbfn = {
1942 .tcb_setup_cbfn = bnad_cb_tcb_setup,
1943 .tcb_destroy_cbfn = bnad_cb_tcb_destroy,
1944 .tx_stall_cbfn = bnad_cb_tx_stall,
1945 .tx_resume_cbfn = bnad_cb_tx_resume,
1946 .tx_cleanup_cbfn = bnad_cb_tx_cleanup,
1950 unsigned long flags;
1952 tx_info->tx_id = tx_id;
1954 /* Initialize the Tx object configuration */
1955 tx_config->num_txq = bnad->num_txq_per_tx;
1956 tx_config->txq_depth = bnad->txq_depth;
1957 tx_config->tx_type = BNA_TX_T_REGULAR;
1958 tx_config->coalescing_timeo = bnad->tx_coalescing_timeo;
1960 /* Get BNA's resource requirement for one tx object */
1961 spin_lock_irqsave(&bnad->bna_lock, flags);
1962 bna_tx_res_req(bnad->num_txq_per_tx,
1963 bnad->txq_depth, res_info);
1964 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1966 /* Fill Unmap Q memory requirements */
1967 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_TX_RES_MEM_T_UNMAPQ],
1968 bnad->num_txq_per_tx, (sizeof(struct bnad_tx_unmap) *
1971 /* Allocate resources */
1972 err = bnad_tx_res_alloc(bnad, res_info, tx_id);
1976 /* Ask BNA to create one Tx object, supplying required resources */
1977 spin_lock_irqsave(&bnad->bna_lock, flags);
1978 tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info,
1980 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1985 INIT_DELAYED_WORK(&tx_info->tx_cleanup_work,
1986 (work_func_t)bnad_tx_cleanup);
1988 /* Register ISR for the Tx object */
1989 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
1990 err = bnad_tx_msix_register(bnad, tx_info,
1991 tx_id, bnad->num_txq_per_tx);
1996 spin_lock_irqsave(&bnad->bna_lock, flags);
1998 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2003 bnad_tx_res_free(bnad, res_info);
2007 /* Setup the rx config for bna_rx_create */
2008 /* bnad decides the configuration */
2010 bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config)
2012 memset(rx_config, 0, sizeof(*rx_config));
2013 rx_config->rx_type = BNA_RX_T_REGULAR;
2014 rx_config->num_paths = bnad->num_rxp_per_rx;
2015 rx_config->coalescing_timeo = bnad->rx_coalescing_timeo;
2017 if (bnad->num_rxp_per_rx > 1) {
2018 rx_config->rss_status = BNA_STATUS_T_ENABLED;
2019 rx_config->rss_config.hash_type =
2020 (BFI_ENET_RSS_IPV6 |
2021 BFI_ENET_RSS_IPV6_TCP |
2023 BFI_ENET_RSS_IPV4_TCP);
2024 rx_config->rss_config.hash_mask =
2025 bnad->num_rxp_per_rx - 1;
2026 get_random_bytes(rx_config->rss_config.toeplitz_hash_key,
2027 sizeof(rx_config->rss_config.toeplitz_hash_key));
2029 rx_config->rss_status = BNA_STATUS_T_DISABLED;
2030 memset(&rx_config->rss_config, 0,
2031 sizeof(rx_config->rss_config));
2034 rx_config->frame_size = BNAD_FRAME_SIZE(bnad->netdev->mtu);
2035 rx_config->q0_multi_buf = BNA_STATUS_T_DISABLED;
2037 /* BNA_RXP_SINGLE - one data-buffer queue
2038 * BNA_RXP_SLR - one small-buffer and one large-buffer queues
2039 * BNA_RXP_HDS - one header-buffer and one data-buffer queues
2041 /* TODO: configurable param for queue type */
2042 rx_config->rxp_type = BNA_RXP_SLR;
2044 if (BNAD_PCI_DEV_IS_CAT2(bnad) &&
2045 rx_config->frame_size > 4096) {
2046 /* though size_routing_enable is set in SLR,
2047 * small packets may get routed to same rxq.
2048 * set buf_size to 2048 instead of PAGE_SIZE.
2050 rx_config->q0_buf_size = 2048;
2051 /* this should be in multiples of 2 */
2052 rx_config->q0_num_vecs = 4;
2053 rx_config->q0_depth = bnad->rxq_depth * rx_config->q0_num_vecs;
2054 rx_config->q0_multi_buf = BNA_STATUS_T_ENABLED;
2056 rx_config->q0_buf_size = rx_config->frame_size;
2057 rx_config->q0_num_vecs = 1;
2058 rx_config->q0_depth = bnad->rxq_depth;
2061 /* initialize for q1 for BNA_RXP_SLR/BNA_RXP_HDS */
2062 if (rx_config->rxp_type == BNA_RXP_SLR) {
2063 rx_config->q1_depth = bnad->rxq_depth;
2064 rx_config->q1_buf_size = BFI_SMALL_RXBUF_SIZE;
2067 rx_config->vlan_strip_status = BNA_STATUS_T_ENABLED;
2071 bnad_rx_ctrl_init(struct bnad *bnad, u32 rx_id)
2073 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2076 for (i = 0; i < bnad->num_rxp_per_rx; i++)
2077 rx_info->rx_ctrl[i].bnad = bnad;
2080 /* Called with mutex_lock(&bnad->conf_mutex) held */
2082 bnad_reinit_rx(struct bnad *bnad)
2084 struct net_device *netdev = bnad->netdev;
2085 u32 err = 0, current_err = 0;
2086 u32 rx_id = 0, count = 0;
2087 unsigned long flags;
2089 /* destroy and create new rx objects */
2090 for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) {
2091 if (!bnad->rx_info[rx_id].rx)
2093 bnad_destroy_rx(bnad, rx_id);
2096 spin_lock_irqsave(&bnad->bna_lock, flags);
2097 bna_enet_mtu_set(&bnad->bna.enet,
2098 BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL);
2099 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2101 for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) {
2103 current_err = bnad_setup_rx(bnad, rx_id);
2104 if (current_err && !err) {
2106 pr_err("RXQ:%u setup failed\n", rx_id);
2110 /* restore rx configuration */
2111 if (bnad->rx_info[0].rx && !err) {
2112 bnad_restore_vlans(bnad, 0);
2113 bnad_enable_default_bcast(bnad);
2114 spin_lock_irqsave(&bnad->bna_lock, flags);
2115 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2116 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2117 bnad_set_rx_mode(netdev);
2123 /* Called with bnad_conf_lock() held */
2125 bnad_destroy_rx(struct bnad *bnad, u32 rx_id)
2127 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2128 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
2129 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
2130 unsigned long flags;
2137 spin_lock_irqsave(&bnad->bna_lock, flags);
2138 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
2139 test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
2140 clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
2143 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2145 del_timer_sync(&bnad->dim_timer);
2148 init_completion(&bnad->bnad_completions.rx_comp);
2149 spin_lock_irqsave(&bnad->bna_lock, flags);
2150 bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled);
2151 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2152 wait_for_completion(&bnad->bnad_completions.rx_comp);
2154 if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
2155 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
2157 bnad_napi_delete(bnad, rx_id);
2159 spin_lock_irqsave(&bnad->bna_lock, flags);
2160 bna_rx_destroy(rx_info->rx);
2164 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2166 bnad_rx_res_free(bnad, res_info);
2169 /* Called with mutex_lock(&bnad->conf_mutex) held */
2171 bnad_setup_rx(struct bnad *bnad, u32 rx_id)
2174 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2175 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
2176 struct bna_intr_info *intr_info =
2177 &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
2178 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
2179 static const struct bna_rx_event_cbfn rx_cbfn = {
2180 .rcb_setup_cbfn = NULL,
2181 .rcb_destroy_cbfn = NULL,
2182 .ccb_setup_cbfn = bnad_cb_ccb_setup,
2183 .ccb_destroy_cbfn = bnad_cb_ccb_destroy,
2184 .rx_stall_cbfn = bnad_cb_rx_stall,
2185 .rx_cleanup_cbfn = bnad_cb_rx_cleanup,
2186 .rx_post_cbfn = bnad_cb_rx_post,
2189 unsigned long flags;
2191 rx_info->rx_id = rx_id;
2193 /* Initialize the Rx object configuration */
2194 bnad_init_rx_config(bnad, rx_config);
2196 /* Get BNA's resource requirement for one Rx object */
2197 spin_lock_irqsave(&bnad->bna_lock, flags);
2198 bna_rx_res_req(rx_config, res_info);
2199 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2201 /* Fill Unmap Q memory requirements */
2202 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPDQ],
2203 rx_config->num_paths,
2204 (rx_config->q0_depth *
2205 sizeof(struct bnad_rx_unmap)) +
2206 sizeof(struct bnad_rx_unmap_q));
2208 if (rx_config->rxp_type != BNA_RXP_SINGLE) {
2209 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPHQ],
2210 rx_config->num_paths,
2211 (rx_config->q1_depth *
2212 sizeof(struct bnad_rx_unmap) +
2213 sizeof(struct bnad_rx_unmap_q)));
2215 /* Allocate resource */
2216 err = bnad_rx_res_alloc(bnad, res_info, rx_id);
2220 bnad_rx_ctrl_init(bnad, rx_id);
2222 /* Ask BNA to create one Rx object, supplying required resources */
2223 spin_lock_irqsave(&bnad->bna_lock, flags);
2224 rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info,
2228 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2232 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2234 INIT_WORK(&rx_info->rx_cleanup_work,
2235 (work_func_t)(bnad_rx_cleanup));
2238 * Init NAPI, so that state is set to NAPI_STATE_SCHED,
2239 * so that IRQ handler cannot schedule NAPI at this point.
2241 bnad_napi_add(bnad, rx_id);
2243 /* Register ISR for the Rx object */
2244 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
2245 err = bnad_rx_msix_register(bnad, rx_info, rx_id,
2246 rx_config->num_paths);
2251 spin_lock_irqsave(&bnad->bna_lock, flags);
2253 /* Set up Dynamic Interrupt Moderation Vector */
2254 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED)
2255 bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector);
2257 /* Enable VLAN filtering only on the default Rx */
2258 bna_rx_vlanfilter_enable(rx);
2260 /* Start the DIM timer */
2261 bnad_dim_timer_start(bnad);
2265 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2270 bnad_destroy_rx(bnad, rx_id);
2274 /* Called with conf_lock & bnad->bna_lock held */
2276 bnad_tx_coalescing_timeo_set(struct bnad *bnad)
2278 struct bnad_tx_info *tx_info;
2280 tx_info = &bnad->tx_info[0];
2284 bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo);
2287 /* Called with conf_lock & bnad->bna_lock held */
2289 bnad_rx_coalescing_timeo_set(struct bnad *bnad)
2291 struct bnad_rx_info *rx_info;
2294 for (i = 0; i < bnad->num_rx; i++) {
2295 rx_info = &bnad->rx_info[i];
2298 bna_rx_coalescing_timeo_set(rx_info->rx,
2299 bnad->rx_coalescing_timeo);
2304 * Called with bnad->bna_lock held
2307 bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr)
2311 if (!is_valid_ether_addr(mac_addr))
2312 return -EADDRNOTAVAIL;
2314 /* If datapath is down, pretend everything went through */
2315 if (!bnad->rx_info[0].rx)
2318 ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr, NULL);
2319 if (ret != BNA_CB_SUCCESS)
2320 return -EADDRNOTAVAIL;
2325 /* Should be called with conf_lock held */
2327 bnad_enable_default_bcast(struct bnad *bnad)
2329 struct bnad_rx_info *rx_info = &bnad->rx_info[0];
2331 unsigned long flags;
2333 init_completion(&bnad->bnad_completions.mcast_comp);
2335 spin_lock_irqsave(&bnad->bna_lock, flags);
2336 ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr,
2337 bnad_cb_rx_mcast_add);
2338 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2340 if (ret == BNA_CB_SUCCESS)
2341 wait_for_completion(&bnad->bnad_completions.mcast_comp);
2345 if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS)
2351 /* Called with mutex_lock(&bnad->conf_mutex) held */
2353 bnad_restore_vlans(struct bnad *bnad, u32 rx_id)
2356 unsigned long flags;
2358 for_each_set_bit(vid, bnad->active_vlans, VLAN_N_VID) {
2359 spin_lock_irqsave(&bnad->bna_lock, flags);
2360 bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vid);
2361 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2365 /* Statistics utilities */
2367 bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
2371 for (i = 0; i < bnad->num_rx; i++) {
2372 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
2373 if (bnad->rx_info[i].rx_ctrl[j].ccb) {
2374 stats->rx_packets += bnad->rx_info[i].
2375 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets;
2376 stats->rx_bytes += bnad->rx_info[i].
2377 rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes;
2378 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
2379 bnad->rx_info[i].rx_ctrl[j].ccb->
2381 stats->rx_packets +=
2382 bnad->rx_info[i].rx_ctrl[j].
2383 ccb->rcb[1]->rxq->rx_packets;
2385 bnad->rx_info[i].rx_ctrl[j].
2386 ccb->rcb[1]->rxq->rx_bytes;
2391 for (i = 0; i < bnad->num_tx; i++) {
2392 for (j = 0; j < bnad->num_txq_per_tx; j++) {
2393 if (bnad->tx_info[i].tcb[j]) {
2394 stats->tx_packets +=
2395 bnad->tx_info[i].tcb[j]->txq->tx_packets;
2397 bnad->tx_info[i].tcb[j]->txq->tx_bytes;
2404 * Must be called with the bna_lock held.
2407 bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
2409 struct bfi_enet_stats_mac *mac_stats;
2413 mac_stats = &bnad->stats.bna_stats->hw_stats.mac_stats;
2415 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error +
2416 mac_stats->rx_frame_length_error + mac_stats->rx_code_error +
2417 mac_stats->rx_undersize;
2418 stats->tx_errors = mac_stats->tx_fcs_error +
2419 mac_stats->tx_undersize;
2420 stats->rx_dropped = mac_stats->rx_drop;
2421 stats->tx_dropped = mac_stats->tx_drop;
2422 stats->multicast = mac_stats->rx_multicast;
2423 stats->collisions = mac_stats->tx_total_collision;
2425 stats->rx_length_errors = mac_stats->rx_frame_length_error;
2427 /* receive ring buffer overflow ?? */
2429 stats->rx_crc_errors = mac_stats->rx_fcs_error;
2430 stats->rx_frame_errors = mac_stats->rx_alignment_error;
2431 /* recv'r fifo overrun */
2432 bmap = bna_rx_rid_mask(&bnad->bna);
2433 for (i = 0; bmap; i++) {
2435 stats->rx_fifo_errors +=
2436 bnad->stats.bna_stats->
2437 hw_stats.rxf_stats[i].frame_drops;
2445 bnad_mbox_irq_sync(struct bnad *bnad)
2448 unsigned long flags;
2450 spin_lock_irqsave(&bnad->bna_lock, flags);
2451 if (bnad->cfg_flags & BNAD_CF_MSIX)
2452 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
2454 irq = bnad->pcidev->irq;
2455 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2457 synchronize_irq(irq);
2460 /* Utility used by bnad_start_xmit, for doing TSO */
2462 bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
2466 if (skb_header_cloned(skb)) {
2467 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2469 BNAD_UPDATE_CTR(bnad, tso_err);
2475 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2476 * excluding the length field.
2478 if (skb->protocol == htons(ETH_P_IP)) {
2479 struct iphdr *iph = ip_hdr(skb);
2481 /* Do we really need these? */
2485 tcp_hdr(skb)->check =
2486 ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
2488 BNAD_UPDATE_CTR(bnad, tso4);
2490 struct ipv6hdr *ipv6h = ipv6_hdr(skb);
2492 ipv6h->payload_len = 0;
2493 tcp_hdr(skb)->check =
2494 ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
2496 BNAD_UPDATE_CTR(bnad, tso6);
2503 * Initialize Q numbers depending on Rx Paths
2504 * Called with bnad->bna_lock held, because of cfg_flags
2508 bnad_q_num_init(struct bnad *bnad)
2512 rxps = min((uint)num_online_cpus(),
2513 (uint)(BNAD_MAX_RX * BNAD_MAX_RXP_PER_RX));
2515 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
2516 rxps = 1; /* INTx */
2520 bnad->num_rxp_per_rx = rxps;
2521 bnad->num_txq_per_tx = BNAD_TXQ_NUM;
2525 * Adjusts the Q numbers, given a number of msix vectors
2526 * Give preference to RSS as opposed to Tx priority Queues,
2527 * in such a case, just use 1 Tx Q
2528 * Called with bnad->bna_lock held b'cos of cfg_flags access
2531 bnad_q_num_adjust(struct bnad *bnad, int msix_vectors, int temp)
2533 bnad->num_txq_per_tx = 1;
2534 if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) +
2535 bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) &&
2536 (bnad->cfg_flags & BNAD_CF_MSIX)) {
2537 bnad->num_rxp_per_rx = msix_vectors -
2538 (bnad->num_tx * bnad->num_txq_per_tx) -
2539 BNAD_MAILBOX_MSIX_VECTORS;
2541 bnad->num_rxp_per_rx = 1;
2544 /* Enable / disable ioceth */
2546 bnad_ioceth_disable(struct bnad *bnad)
2548 unsigned long flags;
2551 spin_lock_irqsave(&bnad->bna_lock, flags);
2552 init_completion(&bnad->bnad_completions.ioc_comp);
2553 bna_ioceth_disable(&bnad->bna.ioceth, BNA_HARD_CLEANUP);
2554 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2556 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2557 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
2559 err = bnad->bnad_completions.ioc_comp_status;
2564 bnad_ioceth_enable(struct bnad *bnad)
2567 unsigned long flags;
2569 spin_lock_irqsave(&bnad->bna_lock, flags);
2570 init_completion(&bnad->bnad_completions.ioc_comp);
2571 bnad->bnad_completions.ioc_comp_status = BNA_CB_WAITING;
2572 bna_ioceth_enable(&bnad->bna.ioceth);
2573 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2575 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2576 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
2578 err = bnad->bnad_completions.ioc_comp_status;
2583 /* Free BNA resources */
2585 bnad_res_free(struct bnad *bnad, struct bna_res_info *res_info,
2590 for (i = 0; i < res_val_max; i++)
2591 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
2594 /* Allocates memory and interrupt resources for BNA */
2596 bnad_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
2601 for (i = 0; i < res_val_max; i++) {
2602 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info);
2609 bnad_res_free(bnad, res_info, res_val_max);
2613 /* Interrupt enable / disable */
2615 bnad_enable_msix(struct bnad *bnad)
2618 unsigned long flags;
2620 spin_lock_irqsave(&bnad->bna_lock, flags);
2621 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2622 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2625 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2627 if (bnad->msix_table)
2631 kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL);
2633 if (!bnad->msix_table)
2636 for (i = 0; i < bnad->msix_num; i++)
2637 bnad->msix_table[i].entry = i;
2639 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, bnad->msix_num);
2641 /* Not enough MSI-X vectors. */
2642 pr_warn("BNA: %d MSI-X vectors allocated < %d requested\n",
2643 ret, bnad->msix_num);
2645 spin_lock_irqsave(&bnad->bna_lock, flags);
2646 /* ret = #of vectors that we got */
2647 bnad_q_num_adjust(bnad, (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2,
2648 (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2);
2649 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2651 bnad->msix_num = BNAD_NUM_TXQ + BNAD_NUM_RXP +
2652 BNAD_MAILBOX_MSIX_VECTORS;
2654 if (bnad->msix_num > ret)
2657 /* Try once more with adjusted numbers */
2658 /* If this fails, fall back to INTx */
2659 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table,
2667 pci_intx(bnad->pcidev, 0);
2672 pr_warn("BNA: MSI-X enable failed - operating in INTx mode\n");
2674 kfree(bnad->msix_table);
2675 bnad->msix_table = NULL;
2677 spin_lock_irqsave(&bnad->bna_lock, flags);
2678 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2679 bnad_q_num_init(bnad);
2680 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2684 bnad_disable_msix(struct bnad *bnad)
2687 unsigned long flags;
2689 spin_lock_irqsave(&bnad->bna_lock, flags);
2690 cfg_flags = bnad->cfg_flags;
2691 if (bnad->cfg_flags & BNAD_CF_MSIX)
2692 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2693 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2695 if (cfg_flags & BNAD_CF_MSIX) {
2696 pci_disable_msix(bnad->pcidev);
2697 kfree(bnad->msix_table);
2698 bnad->msix_table = NULL;
2702 /* Netdev entry points */
2704 bnad_open(struct net_device *netdev)
2707 struct bnad *bnad = netdev_priv(netdev);
2708 struct bna_pause_config pause_config;
2709 unsigned long flags;
2711 mutex_lock(&bnad->conf_mutex);
2714 err = bnad_setup_tx(bnad, 0);
2719 err = bnad_setup_rx(bnad, 0);
2724 pause_config.tx_pause = 0;
2725 pause_config.rx_pause = 0;
2727 spin_lock_irqsave(&bnad->bna_lock, flags);
2728 bna_enet_mtu_set(&bnad->bna.enet,
2729 BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL);
2730 bna_enet_pause_config(&bnad->bna.enet, &pause_config, NULL);
2731 bna_enet_enable(&bnad->bna.enet);
2732 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2734 /* Enable broadcast */
2735 bnad_enable_default_bcast(bnad);
2737 /* Restore VLANs, if any */
2738 bnad_restore_vlans(bnad, 0);
2740 /* Set the UCAST address */
2741 spin_lock_irqsave(&bnad->bna_lock, flags);
2742 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2743 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2745 /* Start the stats timer */
2746 bnad_stats_timer_start(bnad);
2748 mutex_unlock(&bnad->conf_mutex);
2753 bnad_destroy_tx(bnad, 0);
2756 mutex_unlock(&bnad->conf_mutex);
2761 bnad_stop(struct net_device *netdev)
2763 struct bnad *bnad = netdev_priv(netdev);
2764 unsigned long flags;
2766 mutex_lock(&bnad->conf_mutex);
2768 /* Stop the stats timer */
2769 bnad_stats_timer_stop(bnad);
2771 init_completion(&bnad->bnad_completions.enet_comp);
2773 spin_lock_irqsave(&bnad->bna_lock, flags);
2774 bna_enet_disable(&bnad->bna.enet, BNA_HARD_CLEANUP,
2775 bnad_cb_enet_disabled);
2776 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2778 wait_for_completion(&bnad->bnad_completions.enet_comp);
2780 bnad_destroy_tx(bnad, 0);
2781 bnad_destroy_rx(bnad, 0);
2783 /* Synchronize mailbox IRQ */
2784 bnad_mbox_irq_sync(bnad);
2786 mutex_unlock(&bnad->conf_mutex);
2792 /* Returns 0 for success */
2794 bnad_txq_wi_prepare(struct bnad *bnad, struct bna_tcb *tcb,
2795 struct sk_buff *skb, struct bna_txq_entry *txqent)
2801 if (vlan_tx_tag_present(skb)) {
2802 vlan_tag = (u16)vlan_tx_tag_get(skb);
2803 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2805 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) {
2806 vlan_tag = ((tcb->priority & 0x7) << VLAN_PRIO_SHIFT)
2807 | (vlan_tag & 0x1fff);
2808 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2810 txqent->hdr.wi.vlan_tag = htons(vlan_tag);
2812 if (skb_is_gso(skb)) {
2813 gso_size = skb_shinfo(skb)->gso_size;
2814 if (unlikely(gso_size > bnad->netdev->mtu)) {
2815 BNAD_UPDATE_CTR(bnad, tx_skb_mss_too_long);
2818 if (unlikely((gso_size + skb_transport_offset(skb) +
2819 tcp_hdrlen(skb)) >= skb->len)) {
2820 txqent->hdr.wi.opcode =
2821 __constant_htons(BNA_TXQ_WI_SEND);
2822 txqent->hdr.wi.lso_mss = 0;
2823 BNAD_UPDATE_CTR(bnad, tx_skb_tso_too_short);
2825 txqent->hdr.wi.opcode =
2826 __constant_htons(BNA_TXQ_WI_SEND_LSO);
2827 txqent->hdr.wi.lso_mss = htons(gso_size);
2830 if (bnad_tso_prepare(bnad, skb)) {
2831 BNAD_UPDATE_CTR(bnad, tx_skb_tso_prepare);
2835 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
2836 txqent->hdr.wi.l4_hdr_size_n_offset =
2837 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET(
2838 tcp_hdrlen(skb) >> 2, skb_transport_offset(skb)));
2840 txqent->hdr.wi.opcode = __constant_htons(BNA_TXQ_WI_SEND);
2841 txqent->hdr.wi.lso_mss = 0;
2843 if (unlikely(skb->len > (bnad->netdev->mtu + ETH_HLEN))) {
2844 BNAD_UPDATE_CTR(bnad, tx_skb_non_tso_too_long);
2848 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2851 if (skb->protocol == __constant_htons(ETH_P_IP))
2852 proto = ip_hdr(skb)->protocol;
2853 #ifdef NETIF_F_IPV6_CSUM
2854 else if (skb->protocol ==
2855 __constant_htons(ETH_P_IPV6)) {
2856 /* nexthdr may not be TCP immediately. */
2857 proto = ipv6_hdr(skb)->nexthdr;
2860 if (proto == IPPROTO_TCP) {
2861 flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
2862 txqent->hdr.wi.l4_hdr_size_n_offset =
2863 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2864 (0, skb_transport_offset(skb)));
2866 BNAD_UPDATE_CTR(bnad, tcpcsum_offload);
2868 if (unlikely(skb_headlen(skb) <
2869 skb_transport_offset(skb) +
2871 BNAD_UPDATE_CTR(bnad, tx_skb_tcp_hdr);
2874 } else if (proto == IPPROTO_UDP) {
2875 flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
2876 txqent->hdr.wi.l4_hdr_size_n_offset =
2877 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2878 (0, skb_transport_offset(skb)));
2880 BNAD_UPDATE_CTR(bnad, udpcsum_offload);
2881 if (unlikely(skb_headlen(skb) <
2882 skb_transport_offset(skb) +
2883 sizeof(struct udphdr))) {
2884 BNAD_UPDATE_CTR(bnad, tx_skb_udp_hdr);
2889 BNAD_UPDATE_CTR(bnad, tx_skb_csum_err);
2893 txqent->hdr.wi.l4_hdr_size_n_offset = 0;
2896 txqent->hdr.wi.flags = htons(flags);
2897 txqent->hdr.wi.frame_length = htonl(skb->len);
2903 * bnad_start_xmit : Netdev entry point for Transmit
2904 * Called under lock held by net_device
2907 bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2909 struct bnad *bnad = netdev_priv(netdev);
2911 struct bna_tcb *tcb = NULL;
2912 struct bnad_tx_unmap *unmap_q, *unmap, *head_unmap;
2913 u32 prod, q_depth, vect_id;
2914 u32 wis, vectors, len;
2916 dma_addr_t dma_addr;
2917 struct bna_txq_entry *txqent;
2919 len = skb_headlen(skb);
2921 /* Sanity checks for the skb */
2923 if (unlikely(skb->len <= ETH_HLEN)) {
2925 BNAD_UPDATE_CTR(bnad, tx_skb_too_short);
2926 return NETDEV_TX_OK;
2928 if (unlikely(len > BFI_TX_MAX_DATA_PER_VECTOR)) {
2930 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero);
2931 return NETDEV_TX_OK;
2933 if (unlikely(len == 0)) {
2935 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero);
2936 return NETDEV_TX_OK;
2939 tcb = bnad->tx_info[0].tcb[txq_id];
2940 q_depth = tcb->q_depth;
2941 prod = tcb->producer_index;
2943 unmap_q = tcb->unmap_q;
2946 * Takes care of the Tx that is scheduled between clearing the flag
2947 * and the netif_tx_stop_all_queues() call.
2949 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) {
2951 BNAD_UPDATE_CTR(bnad, tx_skb_stopping);
2952 return NETDEV_TX_OK;
2955 vectors = 1 + skb_shinfo(skb)->nr_frags;
2956 wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */
2958 if (unlikely(vectors > BFI_TX_MAX_VECTORS_PER_PKT)) {
2960 BNAD_UPDATE_CTR(bnad, tx_skb_max_vectors);
2961 return NETDEV_TX_OK;
2964 /* Check for available TxQ resources */
2965 if (unlikely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) {
2966 if ((*tcb->hw_consumer_index != tcb->consumer_index) &&
2967 !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
2969 sent = bnad_txcmpl_process(bnad, tcb);
2970 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
2971 bna_ib_ack(tcb->i_dbell, sent);
2972 smp_mb__before_clear_bit();
2973 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
2975 netif_stop_queue(netdev);
2976 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2981 * Check again to deal with race condition between
2982 * netif_stop_queue here, and netif_wake_queue in
2983 * interrupt handler which is not inside netif tx lock.
2985 if (likely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) {
2986 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2987 return NETDEV_TX_BUSY;
2989 netif_wake_queue(netdev);
2990 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
2994 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod];
2995 head_unmap = &unmap_q[prod];
2997 /* Program the opcode, flags, frame_len, num_vectors in WI */
2998 if (bnad_txq_wi_prepare(bnad, tcb, skb, txqent)) {
3000 return NETDEV_TX_OK;
3002 txqent->hdr.wi.reserved = 0;
3003 txqent->hdr.wi.num_vectors = vectors;
3005 head_unmap->skb = skb;
3006 head_unmap->nvecs = 0;
3008 /* Program the vectors */
3010 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
3011 len, DMA_TO_DEVICE);
3012 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[0].host_addr);
3013 txqent->vector[0].length = htons(len);
3014 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, dma_addr);
3015 head_unmap->nvecs++;
3017 for (i = 0, vect_id = 0; i < vectors - 1; i++) {
3018 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
3019 u16 size = skb_frag_size(frag);
3021 if (unlikely(size == 0)) {
3022 /* Undo the changes starting at tcb->producer_index */
3023 bnad_tx_buff_unmap(bnad, unmap_q, q_depth,
3024 tcb->producer_index);
3026 BNAD_UPDATE_CTR(bnad, tx_skb_frag_zero);
3027 return NETDEV_TX_OK;
3033 if (vect_id == BFI_TX_MAX_VECTORS_PER_WI) {
3035 BNA_QE_INDX_INC(prod, q_depth);
3036 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod];
3037 txqent->hdr.wi_ext.opcode =
3038 __constant_htons(BNA_TXQ_WI_EXTENSION);
3039 unmap = &unmap_q[prod];
3042 dma_addr = skb_frag_dma_map(&bnad->pcidev->dev, frag,
3043 0, size, DMA_TO_DEVICE);
3044 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
3045 txqent->vector[vect_id].length = htons(size);
3046 dma_unmap_addr_set(&unmap->vectors[vect_id], dma_addr,
3048 head_unmap->nvecs++;
3051 if (unlikely(len != skb->len)) {
3052 /* Undo the changes starting at tcb->producer_index */
3053 bnad_tx_buff_unmap(bnad, unmap_q, q_depth, tcb->producer_index);
3055 BNAD_UPDATE_CTR(bnad, tx_skb_len_mismatch);
3056 return NETDEV_TX_OK;
3059 BNA_QE_INDX_INC(prod, q_depth);
3060 tcb->producer_index = prod;
3064 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
3065 return NETDEV_TX_OK;
3067 skb_tx_timestamp(skb);
3069 bna_txq_prod_indx_doorbell(tcb);
3072 return NETDEV_TX_OK;
3076 * Used spin_lock to synchronize reading of stats structures, which
3077 * is written by BNA under the same lock.
3079 static struct rtnl_link_stats64 *
3080 bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)
3082 struct bnad *bnad = netdev_priv(netdev);
3083 unsigned long flags;
3085 spin_lock_irqsave(&bnad->bna_lock, flags);
3087 bnad_netdev_qstats_fill(bnad, stats);
3088 bnad_netdev_hwstats_fill(bnad, stats);
3090 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3096 bnad_set_rx_ucast_fltr(struct bnad *bnad)
3098 struct net_device *netdev = bnad->netdev;
3099 int uc_count = netdev_uc_count(netdev);
3100 enum bna_cb_status ret;
3102 struct netdev_hw_addr *ha;
3105 if (netdev_uc_empty(bnad->netdev)) {
3106 bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL, NULL);
3110 if (uc_count > bna_attr(&bnad->bna)->num_ucmac)
3113 mac_list = kzalloc(uc_count * ETH_ALEN, GFP_ATOMIC);
3114 if (mac_list == NULL)
3118 netdev_for_each_uc_addr(ha, netdev) {
3119 memcpy(&mac_list[entry * ETH_ALEN],
3120 &ha->addr[0], ETH_ALEN);
3124 ret = bna_rx_ucast_listset(bnad->rx_info[0].rx, entry,
3128 if (ret != BNA_CB_SUCCESS)
3133 /* ucast packets not in UCAM are routed to default function */
3135 bnad->cfg_flags |= BNAD_CF_DEFAULT;
3136 bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL, NULL);
3140 bnad_set_rx_mcast_fltr(struct bnad *bnad)
3142 struct net_device *netdev = bnad->netdev;
3143 int mc_count = netdev_mc_count(netdev);
3144 enum bna_cb_status ret;
3147 if (netdev->flags & IFF_ALLMULTI)
3150 if (netdev_mc_empty(netdev))
3153 if (mc_count > bna_attr(&bnad->bna)->num_mcmac)
3156 mac_list = kzalloc((mc_count + 1) * ETH_ALEN, GFP_ATOMIC);
3158 if (mac_list == NULL)
3161 memcpy(&mac_list[0], &bnad_bcast_addr[0], ETH_ALEN);
3163 /* copy rest of the MCAST addresses */
3164 bnad_netdev_mc_list_get(netdev, mac_list);
3165 ret = bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1,
3169 if (ret != BNA_CB_SUCCESS)
3175 bnad->cfg_flags |= BNAD_CF_ALLMULTI;
3176 bna_rx_mcast_delall(bnad->rx_info[0].rx, NULL);
3180 bnad_set_rx_mode(struct net_device *netdev)
3182 struct bnad *bnad = netdev_priv(netdev);
3183 enum bna_rxmode new_mode, mode_mask;
3184 unsigned long flags;
3186 spin_lock_irqsave(&bnad->bna_lock, flags);
3188 if (bnad->rx_info[0].rx == NULL) {
3189 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3193 /* clear bnad flags to update it with new settings */
3194 bnad->cfg_flags &= ~(BNAD_CF_PROMISC | BNAD_CF_DEFAULT |
3198 if (netdev->flags & IFF_PROMISC) {
3199 new_mode |= BNAD_RXMODE_PROMISC_DEFAULT;
3200 bnad->cfg_flags |= BNAD_CF_PROMISC;
3202 bnad_set_rx_mcast_fltr(bnad);
3204 if (bnad->cfg_flags & BNAD_CF_ALLMULTI)
3205 new_mode |= BNA_RXMODE_ALLMULTI;
3207 bnad_set_rx_ucast_fltr(bnad);
3209 if (bnad->cfg_flags & BNAD_CF_DEFAULT)
3210 new_mode |= BNA_RXMODE_DEFAULT;
3213 mode_mask = BNA_RXMODE_PROMISC | BNA_RXMODE_DEFAULT |
3214 BNA_RXMODE_ALLMULTI;
3215 bna_rx_mode_set(bnad->rx_info[0].rx, new_mode, mode_mask, NULL);
3217 if (bnad->cfg_flags & BNAD_CF_PROMISC)
3218 bna_rx_vlan_strip_disable(bnad->rx_info[0].rx);
3220 bna_rx_vlan_strip_enable(bnad->rx_info[0].rx);
3222 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3226 * bna_lock is used to sync writes to netdev->addr
3227 * conf_lock cannot be used since this call may be made
3228 * in a non-blocking context.
3231 bnad_set_mac_address(struct net_device *netdev, void *mac_addr)
3234 struct bnad *bnad = netdev_priv(netdev);
3235 struct sockaddr *sa = (struct sockaddr *)mac_addr;
3236 unsigned long flags;
3238 spin_lock_irqsave(&bnad->bna_lock, flags);
3240 err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
3243 memcpy(netdev->dev_addr, sa->sa_data, netdev->addr_len);
3245 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3251 bnad_mtu_set(struct bnad *bnad, int frame_size)
3253 unsigned long flags;
3255 init_completion(&bnad->bnad_completions.mtu_comp);
3257 spin_lock_irqsave(&bnad->bna_lock, flags);
3258 bna_enet_mtu_set(&bnad->bna.enet, frame_size, bnad_cb_enet_mtu_set);
3259 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3261 wait_for_completion(&bnad->bnad_completions.mtu_comp);
3263 return bnad->bnad_completions.mtu_comp_status;
3267 bnad_change_mtu(struct net_device *netdev, int new_mtu)
3270 struct bnad *bnad = netdev_priv(netdev);
3271 u32 rx_count = 0, frame, new_frame;
3273 if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
3276 mutex_lock(&bnad->conf_mutex);
3279 netdev->mtu = new_mtu;
3281 frame = BNAD_FRAME_SIZE(mtu);
3282 new_frame = BNAD_FRAME_SIZE(new_mtu);
3284 /* check if multi-buffer needs to be enabled */
3285 if (BNAD_PCI_DEV_IS_CAT2(bnad) &&
3286 netif_running(bnad->netdev)) {
3287 /* only when transition is over 4K */
3288 if ((frame <= 4096 && new_frame > 4096) ||
3289 (frame > 4096 && new_frame <= 4096))
3290 rx_count = bnad_reinit_rx(bnad);
3293 /* rx_count > 0 - new rx created
3294 * - Linux set err = 0 and return
3296 err = bnad_mtu_set(bnad, new_frame);
3300 mutex_unlock(&bnad->conf_mutex);
3305 bnad_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
3307 struct bnad *bnad = netdev_priv(netdev);
3308 unsigned long flags;
3310 if (!bnad->rx_info[0].rx)
3313 mutex_lock(&bnad->conf_mutex);
3315 spin_lock_irqsave(&bnad->bna_lock, flags);
3316 bna_rx_vlan_add(bnad->rx_info[0].rx, vid);
3317 set_bit(vid, bnad->active_vlans);
3318 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3320 mutex_unlock(&bnad->conf_mutex);
3326 bnad_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
3328 struct bnad *bnad = netdev_priv(netdev);
3329 unsigned long flags;
3331 if (!bnad->rx_info[0].rx)
3334 mutex_lock(&bnad->conf_mutex);
3336 spin_lock_irqsave(&bnad->bna_lock, flags);
3337 clear_bit(vid, bnad->active_vlans);
3338 bna_rx_vlan_del(bnad->rx_info[0].rx, vid);
3339 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3341 mutex_unlock(&bnad->conf_mutex);
3346 #ifdef CONFIG_NET_POLL_CONTROLLER
3348 bnad_netpoll(struct net_device *netdev)
3350 struct bnad *bnad = netdev_priv(netdev);
3351 struct bnad_rx_info *rx_info;
3352 struct bnad_rx_ctrl *rx_ctrl;
3356 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
3357 bna_intx_disable(&bnad->bna, curr_mask);
3358 bnad_isr(bnad->pcidev->irq, netdev);
3359 bna_intx_enable(&bnad->bna, curr_mask);
3362 * Tx processing may happen in sending context, so no need
3363 * to explicitly process completions here
3367 for (i = 0; i < bnad->num_rx; i++) {
3368 rx_info = &bnad->rx_info[i];
3371 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
3372 rx_ctrl = &rx_info->rx_ctrl[j];
3374 bnad_netif_rx_schedule_poll(bnad,
3382 static const struct net_device_ops bnad_netdev_ops = {
3383 .ndo_open = bnad_open,
3384 .ndo_stop = bnad_stop,
3385 .ndo_start_xmit = bnad_start_xmit,
3386 .ndo_get_stats64 = bnad_get_stats64,
3387 .ndo_set_rx_mode = bnad_set_rx_mode,
3388 .ndo_validate_addr = eth_validate_addr,
3389 .ndo_set_mac_address = bnad_set_mac_address,
3390 .ndo_change_mtu = bnad_change_mtu,
3391 .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid,
3392 .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid,
3393 #ifdef CONFIG_NET_POLL_CONTROLLER
3394 .ndo_poll_controller = bnad_netpoll
3399 bnad_netdev_init(struct bnad *bnad, bool using_dac)
3401 struct net_device *netdev = bnad->netdev;
3403 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
3404 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3405 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_TX;
3407 netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA |
3408 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3409 NETIF_F_TSO | NETIF_F_TSO6;
3411 netdev->features |= netdev->hw_features |
3412 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER;
3415 netdev->features |= NETIF_F_HIGHDMA;
3417 netdev->mem_start = bnad->mmio_start;
3418 netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1;
3420 netdev->netdev_ops = &bnad_netdev_ops;
3421 bnad_set_ethtool_ops(netdev);
3425 * 1. Initialize the bnad structure
3426 * 2. Setup netdev pointer in pci_dev
3427 * 3. Initialize no. of TxQ & CQs & MSIX vectors
3428 * 4. Initialize work queue.
3431 bnad_init(struct bnad *bnad,
3432 struct pci_dev *pdev, struct net_device *netdev)
3434 unsigned long flags;
3436 SET_NETDEV_DEV(netdev, &pdev->dev);
3437 pci_set_drvdata(pdev, netdev);
3439 bnad->netdev = netdev;
3440 bnad->pcidev = pdev;
3441 bnad->mmio_start = pci_resource_start(pdev, 0);
3442 bnad->mmio_len = pci_resource_len(pdev, 0);
3443 bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len);
3445 dev_err(&pdev->dev, "ioremap for bar0 failed\n");
3448 pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0,
3449 (unsigned long long) bnad->mmio_len);
3451 spin_lock_irqsave(&bnad->bna_lock, flags);
3452 if (!bnad_msix_disable)
3453 bnad->cfg_flags = BNAD_CF_MSIX;
3455 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
3457 bnad_q_num_init(bnad);
3458 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3460 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) +
3461 (bnad->num_rx * bnad->num_rxp_per_rx) +
3462 BNAD_MAILBOX_MSIX_VECTORS;
3464 bnad->txq_depth = BNAD_TXQ_DEPTH;
3465 bnad->rxq_depth = BNAD_RXQ_DEPTH;
3467 bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
3468 bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
3470 sprintf(bnad->wq_name, "%s_wq_%d", BNAD_NAME, bnad->id);
3471 bnad->work_q = create_singlethread_workqueue(bnad->wq_name);
3472 if (!bnad->work_q) {
3473 iounmap(bnad->bar0);
3481 * Must be called after bnad_pci_uninit()
3482 * so that iounmap() and pci_set_drvdata(NULL)
3483 * happens only after PCI uninitialization.
3486 bnad_uninit(struct bnad *bnad)
3489 flush_workqueue(bnad->work_q);
3490 destroy_workqueue(bnad->work_q);
3491 bnad->work_q = NULL;
3495 iounmap(bnad->bar0);
3500 a) Per ioceth mutes used for serializing configuration
3501 changes from OS interface
3502 b) spin lock used to protect bna state machine
3505 bnad_lock_init(struct bnad *bnad)
3507 spin_lock_init(&bnad->bna_lock);
3508 mutex_init(&bnad->conf_mutex);
3509 mutex_init(&bnad_list_mutex);
3513 bnad_lock_uninit(struct bnad *bnad)
3515 mutex_destroy(&bnad->conf_mutex);
3516 mutex_destroy(&bnad_list_mutex);
3519 /* PCI Initialization */
3521 bnad_pci_init(struct bnad *bnad,
3522 struct pci_dev *pdev, bool *using_dac)
3526 err = pci_enable_device(pdev);
3529 err = pci_request_regions(pdev, BNAD_NAME);
3531 goto disable_device;
3532 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
3535 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3537 goto release_regions;
3540 pci_set_master(pdev);
3544 pci_release_regions(pdev);
3546 pci_disable_device(pdev);
3552 bnad_pci_uninit(struct pci_dev *pdev)
3554 pci_release_regions(pdev);
3555 pci_disable_device(pdev);
3559 bnad_pci_probe(struct pci_dev *pdev,
3560 const struct pci_device_id *pcidev_id)
3566 struct net_device *netdev;
3567 struct bfa_pcidev pcidev_info;
3568 unsigned long flags;
3570 pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
3571 pdev, pcidev_id, PCI_FUNC(pdev->devfn));
3573 mutex_lock(&bnad_fwimg_mutex);
3574 if (!cna_get_firmware_buf(pdev)) {
3575 mutex_unlock(&bnad_fwimg_mutex);
3576 pr_warn("Failed to load Firmware Image!\n");
3579 mutex_unlock(&bnad_fwimg_mutex);
3582 * Allocates sizeof(struct net_device + struct bnad)
3583 * bnad = netdev->priv
3585 netdev = alloc_etherdev(sizeof(struct bnad));
3590 bnad = netdev_priv(netdev);
3591 bnad_lock_init(bnad);
3592 bnad_add_to_list(bnad);
3594 mutex_lock(&bnad->conf_mutex);
3596 * PCI initialization
3597 * Output : using_dac = 1 for 64 bit DMA
3598 * = 0 for 32 bit DMA
3601 err = bnad_pci_init(bnad, pdev, &using_dac);
3606 * Initialize bnad structure
3607 * Setup relation between pci_dev & netdev
3609 err = bnad_init(bnad, pdev, netdev);
3613 /* Initialize netdev structure, set up ethtool ops */
3614 bnad_netdev_init(bnad, using_dac);
3616 /* Set link to down state */
3617 netif_carrier_off(netdev);
3619 /* Setup the debugfs node for this bfad */
3620 if (bna_debugfs_enable)
3621 bnad_debugfs_init(bnad);
3623 /* Get resource requirement form bna */
3624 spin_lock_irqsave(&bnad->bna_lock, flags);
3625 bna_res_req(&bnad->res_info[0]);
3626 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3628 /* Allocate resources from bna */
3629 err = bnad_res_alloc(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3635 /* Setup pcidev_info for bna_init() */
3636 pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
3637 pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
3638 pcidev_info.device_id = bnad->pcidev->device;
3639 pcidev_info.pci_bar_kva = bnad->bar0;
3641 spin_lock_irqsave(&bnad->bna_lock, flags);
3642 bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]);
3643 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3645 bnad->stats.bna_stats = &bna->stats;
3647 bnad_enable_msix(bnad);
3648 err = bnad_mbox_irq_alloc(bnad);
3653 setup_timer(&bnad->bna.ioceth.ioc.ioc_timer, bnad_ioc_timeout,
3654 ((unsigned long)bnad));
3655 setup_timer(&bnad->bna.ioceth.ioc.hb_timer, bnad_ioc_hb_check,
3656 ((unsigned long)bnad));
3657 setup_timer(&bnad->bna.ioceth.ioc.iocpf_timer, bnad_iocpf_timeout,
3658 ((unsigned long)bnad));
3659 setup_timer(&bnad->bna.ioceth.ioc.sem_timer, bnad_iocpf_sem_timeout,
3660 ((unsigned long)bnad));
3662 /* Now start the timer before calling IOC */
3663 mod_timer(&bnad->bna.ioceth.ioc.iocpf_timer,
3664 jiffies + msecs_to_jiffies(BNA_IOC_TIMER_FREQ));
3668 * If the call back comes with error, we bail out.
3669 * This is a catastrophic error.
3671 err = bnad_ioceth_enable(bnad);
3673 pr_err("BNA: Initialization failed err=%d\n",
3678 spin_lock_irqsave(&bnad->bna_lock, flags);
3679 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3680 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) {
3681 bnad_q_num_adjust(bnad, bna_attr(bna)->num_txq - 1,
3682 bna_attr(bna)->num_rxp - 1);
3683 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3684 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1))
3687 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3689 goto disable_ioceth;
3691 spin_lock_irqsave(&bnad->bna_lock, flags);
3692 bna_mod_res_req(&bnad->bna, &bnad->mod_res_info[0]);
3693 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3695 err = bnad_res_alloc(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3698 goto disable_ioceth;
3701 spin_lock_irqsave(&bnad->bna_lock, flags);
3702 bna_mod_init(&bnad->bna, &bnad->mod_res_info[0]);
3703 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3705 /* Get the burnt-in mac */
3706 spin_lock_irqsave(&bnad->bna_lock, flags);
3707 bna_enet_perm_mac_get(&bna->enet, &bnad->perm_addr);
3708 bnad_set_netdev_perm_addr(bnad);
3709 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3711 mutex_unlock(&bnad->conf_mutex);
3713 /* Finally, reguister with net_device layer */
3714 err = register_netdev(netdev);
3716 pr_err("BNA : Registering with netdev failed\n");
3719 set_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags);
3724 mutex_unlock(&bnad->conf_mutex);
3728 mutex_lock(&bnad->conf_mutex);
3729 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3731 bnad_ioceth_disable(bnad);
3732 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3733 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3734 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
3735 spin_lock_irqsave(&bnad->bna_lock, flags);
3737 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3738 bnad_mbox_irq_free(bnad);
3739 bnad_disable_msix(bnad);
3741 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3743 /* Remove the debugfs node for this bnad */
3744 kfree(bnad->regdata);
3745 bnad_debugfs_uninit(bnad);
3748 bnad_pci_uninit(pdev);
3750 mutex_unlock(&bnad->conf_mutex);
3751 bnad_remove_from_list(bnad);
3752 bnad_lock_uninit(bnad);
3753 free_netdev(netdev);
3758 bnad_pci_remove(struct pci_dev *pdev)
3760 struct net_device *netdev = pci_get_drvdata(pdev);
3763 unsigned long flags;
3768 pr_info("%s bnad_pci_remove\n", netdev->name);
3769 bnad = netdev_priv(netdev);
3772 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags))
3773 unregister_netdev(netdev);
3775 mutex_lock(&bnad->conf_mutex);
3776 bnad_ioceth_disable(bnad);
3777 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3778 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3779 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
3780 spin_lock_irqsave(&bnad->bna_lock, flags);
3782 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3784 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3785 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3786 bnad_mbox_irq_free(bnad);
3787 bnad_disable_msix(bnad);
3788 bnad_pci_uninit(pdev);
3789 mutex_unlock(&bnad->conf_mutex);
3790 bnad_remove_from_list(bnad);
3791 bnad_lock_uninit(bnad);
3792 /* Remove the debugfs node for this bnad */
3793 kfree(bnad->regdata);
3794 bnad_debugfs_uninit(bnad);
3796 free_netdev(netdev);
3799 static DEFINE_PCI_DEVICE_TABLE(bnad_pci_id_table) = {
3801 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3802 PCI_DEVICE_ID_BROCADE_CT),
3803 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3804 .class_mask = 0xffff00
3807 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3808 BFA_PCI_DEVICE_ID_CT2),
3809 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3810 .class_mask = 0xffff00
3815 MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
3817 static struct pci_driver bnad_pci_driver = {
3819 .id_table = bnad_pci_id_table,
3820 .probe = bnad_pci_probe,
3821 .remove = bnad_pci_remove,
3825 bnad_module_init(void)
3829 pr_info("Brocade 10G Ethernet driver - version: %s\n",
3832 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover);
3834 err = pci_register_driver(&bnad_pci_driver);
3836 pr_err("bna : PCI registration failed in module init "
3845 bnad_module_exit(void)
3847 pci_unregister_driver(&bnad_pci_driver);
3848 release_firmware(bfi_fw);
3851 module_init(bnad_module_init);
3852 module_exit(bnad_module_exit);
3854 MODULE_AUTHOR("Brocade");
3855 MODULE_LICENSE("GPL");
3856 MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver");
3857 MODULE_VERSION(BNAD_VERSION);
3858 MODULE_FIRMWARE(CNA_FW_FILE_CT);
3859 MODULE_FIRMWARE(CNA_FW_FILE_CT2);