2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/macb.h>
27 #include <linux/platform_device.h>
28 #include <linux/phy.h>
30 #include <linux/of_device.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
33 #include <linux/pinctrl/consumer.h>
37 #define MACB_RX_BUFFER_SIZE 128
38 #define RX_BUFFER_MULTIPLE 64 /* bytes */
39 #define RX_RING_SIZE 512 /* must be power of 2 */
40 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
42 #define TX_RING_SIZE 128 /* must be power of 2 */
43 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
45 /* level of occupied TX descriptors under which we wake up TX process */
46 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
48 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
50 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
53 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
56 * Graceful stop timeouts in us. We should allow up to
57 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
59 #define MACB_HALT_TIMEOUT 1230
61 /* Ring buffer accessors */
62 static unsigned int macb_tx_ring_wrap(unsigned int index)
64 return index & (TX_RING_SIZE - 1);
67 static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
69 return &bp->tx_ring[macb_tx_ring_wrap(index)];
72 static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
74 return &bp->tx_skb[macb_tx_ring_wrap(index)];
77 static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
81 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
83 return bp->tx_ring_dma + offset;
86 static unsigned int macb_rx_ring_wrap(unsigned int index)
88 return index & (RX_RING_SIZE - 1);
91 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
93 return &bp->rx_ring[macb_rx_ring_wrap(index)];
96 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
98 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
101 void macb_set_hwaddr(struct macb *bp)
106 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
107 macb_or_gem_writel(bp, SA1B, bottom);
108 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
109 macb_or_gem_writel(bp, SA1T, top);
111 /* Clear unused address register sets */
112 macb_or_gem_writel(bp, SA2B, 0);
113 macb_or_gem_writel(bp, SA2T, 0);
114 macb_or_gem_writel(bp, SA3B, 0);
115 macb_or_gem_writel(bp, SA3T, 0);
116 macb_or_gem_writel(bp, SA4B, 0);
117 macb_or_gem_writel(bp, SA4T, 0);
119 EXPORT_SYMBOL_GPL(macb_set_hwaddr);
121 void macb_get_hwaddr(struct macb *bp)
123 struct macb_platform_data *pdata;
129 pdata = dev_get_platdata(&bp->pdev->dev);
131 /* Check all 4 address register for vaild address */
132 for (i = 0; i < 4; i++) {
133 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
134 top = macb_or_gem_readl(bp, SA1T + i * 8);
136 if (pdata && pdata->rev_eth_addr) {
137 addr[5] = bottom & 0xff;
138 addr[4] = (bottom >> 8) & 0xff;
139 addr[3] = (bottom >> 16) & 0xff;
140 addr[2] = (bottom >> 24) & 0xff;
141 addr[1] = top & 0xff;
142 addr[0] = (top & 0xff00) >> 8;
144 addr[0] = bottom & 0xff;
145 addr[1] = (bottom >> 8) & 0xff;
146 addr[2] = (bottom >> 16) & 0xff;
147 addr[3] = (bottom >> 24) & 0xff;
148 addr[4] = top & 0xff;
149 addr[5] = (top >> 8) & 0xff;
152 if (is_valid_ether_addr(addr)) {
153 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
158 netdev_info(bp->dev, "invalid hw address, using random\n");
159 eth_hw_addr_random(bp->dev);
161 EXPORT_SYMBOL_GPL(macb_get_hwaddr);
163 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
165 struct macb *bp = bus->priv;
168 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
169 | MACB_BF(RW, MACB_MAN_READ)
170 | MACB_BF(PHYA, mii_id)
171 | MACB_BF(REGA, regnum)
172 | MACB_BF(CODE, MACB_MAN_CODE)));
174 /* wait for end of transfer */
175 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
178 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
183 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
186 struct macb *bp = bus->priv;
188 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
189 | MACB_BF(RW, MACB_MAN_WRITE)
190 | MACB_BF(PHYA, mii_id)
191 | MACB_BF(REGA, regnum)
192 | MACB_BF(CODE, MACB_MAN_CODE)
193 | MACB_BF(DATA, value)));
195 /* wait for end of transfer */
196 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
202 static int macb_mdio_reset(struct mii_bus *bus)
207 static void macb_handle_link_change(struct net_device *dev)
209 struct macb *bp = netdev_priv(dev);
210 struct phy_device *phydev = bp->phy_dev;
213 int status_change = 0;
215 spin_lock_irqsave(&bp->lock, flags);
218 if ((bp->speed != phydev->speed) ||
219 (bp->duplex != phydev->duplex)) {
222 reg = macb_readl(bp, NCFGR);
223 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
225 reg &= ~GEM_BIT(GBE);
229 if (phydev->speed == SPEED_100)
230 reg |= MACB_BIT(SPD);
231 if (phydev->speed == SPEED_1000)
234 macb_or_gem_writel(bp, NCFGR, reg);
236 bp->speed = phydev->speed;
237 bp->duplex = phydev->duplex;
242 if (phydev->link != bp->link) {
247 bp->link = phydev->link;
252 spin_unlock_irqrestore(&bp->lock, flags);
256 netif_carrier_on(dev);
257 netdev_info(dev, "link up (%d/%s)\n",
259 phydev->duplex == DUPLEX_FULL ?
262 netif_carrier_off(dev);
263 netdev_info(dev, "link down\n");
268 /* based on au1000_eth. c*/
269 static int macb_mii_probe(struct net_device *dev)
271 struct macb *bp = netdev_priv(dev);
272 struct macb_platform_data *pdata;
273 struct phy_device *phydev;
277 phydev = phy_find_first(bp->mii_bus);
279 netdev_err(dev, "no PHY found\n");
283 pdata = dev_get_platdata(&bp->pdev->dev);
284 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
285 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
287 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
288 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
292 /* attach the mac to the phy */
293 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
296 netdev_err(dev, "Could not attach to PHY\n");
300 /* mask with MAC supported features */
302 phydev->supported &= PHY_GBIT_FEATURES;
304 phydev->supported &= PHY_BASIC_FEATURES;
306 phydev->advertising = phydev->supported;
311 bp->phy_dev = phydev;
316 int macb_mii_init(struct macb *bp)
318 struct macb_platform_data *pdata;
319 struct device_node *np;
322 /* Enable management port */
323 macb_writel(bp, NCR, MACB_BIT(MPE));
325 bp->mii_bus = mdiobus_alloc();
326 if (bp->mii_bus == NULL) {
331 bp->mii_bus->name = "MACB_mii_bus";
332 bp->mii_bus->read = &macb_mdio_read;
333 bp->mii_bus->write = &macb_mdio_write;
334 bp->mii_bus->reset = &macb_mdio_reset;
335 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
336 bp->pdev->name, bp->pdev->id);
337 bp->mii_bus->priv = bp;
338 bp->mii_bus->parent = &bp->dev->dev;
339 pdata = dev_get_platdata(&bp->pdev->dev);
341 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
342 if (!bp->mii_bus->irq) {
344 goto err_out_free_mdiobus;
347 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
349 np = bp->pdev->dev.of_node;
351 /* try dt phy registration */
352 err = of_mdiobus_register(bp->mii_bus, np);
354 /* fallback to standard phy registration if no phy were
355 found during dt phy registration */
356 if (!err && !phy_find_first(bp->mii_bus)) {
357 for (i = 0; i < PHY_MAX_ADDR; i++) {
358 struct phy_device *phydev;
360 phydev = mdiobus_scan(bp->mii_bus, i);
361 if (IS_ERR(phydev)) {
362 err = PTR_ERR(phydev);
368 goto err_out_unregister_bus;
371 for (i = 0; i < PHY_MAX_ADDR; i++)
372 bp->mii_bus->irq[i] = PHY_POLL;
375 bp->mii_bus->phy_mask = pdata->phy_mask;
377 err = mdiobus_register(bp->mii_bus);
381 goto err_out_free_mdio_irq;
383 err = macb_mii_probe(bp->dev);
385 goto err_out_unregister_bus;
389 err_out_unregister_bus:
390 mdiobus_unregister(bp->mii_bus);
391 err_out_free_mdio_irq:
392 kfree(bp->mii_bus->irq);
393 err_out_free_mdiobus:
394 mdiobus_free(bp->mii_bus);
398 EXPORT_SYMBOL_GPL(macb_mii_init);
400 static void macb_update_stats(struct macb *bp)
402 u32 __iomem *reg = bp->regs + MACB_PFR;
403 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
404 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
406 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
408 for(; p < end; p++, reg++)
409 *p += __raw_readl(reg);
412 static int macb_halt_tx(struct macb *bp)
414 unsigned long halt_time, timeout;
417 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
419 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
422 status = macb_readl(bp, TSR);
423 if (!(status & MACB_BIT(TGO)))
426 usleep_range(10, 250);
427 } while (time_before(halt_time, timeout));
432 static void macb_tx_error_task(struct work_struct *work)
434 struct macb *bp = container_of(work, struct macb, tx_error_task);
435 struct macb_tx_skb *tx_skb;
439 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n",
440 bp->tx_tail, bp->tx_head);
442 /* Make sure nobody is trying to queue up new packets */
443 netif_stop_queue(bp->dev);
446 * Stop transmission now
447 * (in case we have just queued new packets)
449 if (macb_halt_tx(bp))
450 /* Just complain for now, reinitializing TX path can be good */
451 netdev_err(bp->dev, "BUG: halt tx timed out\n");
453 /* No need for the lock here as nobody will interrupt us anymore */
456 * Treat frames in TX queue including the ones that caused the error.
457 * Free transmit buffers in upper layer.
459 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) {
460 struct macb_dma_desc *desc;
463 desc = macb_tx_desc(bp, tail);
465 tx_skb = macb_tx_skb(bp, tail);
468 if (ctrl & MACB_BIT(TX_USED)) {
469 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
470 macb_tx_ring_wrap(tail), skb->data);
471 bp->stats.tx_packets++;
472 bp->stats.tx_bytes += skb->len;
475 * "Buffers exhausted mid-frame" errors may only happen
476 * if the driver is buggy, so complain loudly about those.
477 * Statistics are updated by hardware.
479 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
481 "BUG: TX buffers exhausted mid-frame\n");
483 desc->ctrl = ctrl | MACB_BIT(TX_USED);
486 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
492 /* Make descriptor updates visible to hardware */
495 /* Reinitialize the TX desc queue */
496 macb_writel(bp, TBQP, bp->tx_ring_dma);
497 /* Make TX ring reflect state of hardware */
498 bp->tx_head = bp->tx_tail = 0;
500 /* Now we are ready to start transmission again */
501 netif_wake_queue(bp->dev);
503 /* Housework before enabling TX IRQ */
504 macb_writel(bp, TSR, macb_readl(bp, TSR));
505 macb_writel(bp, IER, MACB_TX_INT_FLAGS);
508 static void macb_tx_interrupt(struct macb *bp)
514 status = macb_readl(bp, TSR);
515 macb_writel(bp, TSR, status);
517 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
518 macb_writel(bp, ISR, MACB_BIT(TCOMP));
520 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
521 (unsigned long)status);
524 for (tail = bp->tx_tail; tail != head; tail++) {
525 struct macb_tx_skb *tx_skb;
527 struct macb_dma_desc *desc;
530 desc = macb_tx_desc(bp, tail);
532 /* Make hw descriptor updates visible to CPU */
537 if (!(ctrl & MACB_BIT(TX_USED)))
540 tx_skb = macb_tx_skb(bp, tail);
543 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
544 macb_tx_ring_wrap(tail), skb->data);
545 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
547 bp->stats.tx_packets++;
548 bp->stats.tx_bytes += skb->len;
550 dev_kfree_skb_irq(skb);
554 if (netif_queue_stopped(bp->dev)
555 && CIRC_CNT(bp->tx_head, bp->tx_tail,
556 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
557 netif_wake_queue(bp->dev);
560 static void gem_rx_refill(struct macb *bp)
564 struct macb_dma_desc *desc;
567 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
570 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
571 desc = &bp->rx_ring[entry];
573 /* Make hw descriptor updates visible to CPU */
578 bp->rx_prepared_head++;
580 if ((addr & MACB_BIT(RX_USED)))
583 if (bp->rx_skbuff[entry] == NULL) {
584 /* allocate sk_buff for this free entry in ring */
585 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
586 if (unlikely(skb == NULL)) {
588 "Unable to allocate sk_buff\n");
591 bp->rx_skbuff[entry] = skb;
593 /* now fill corresponding descriptor entry */
594 paddr = dma_map_single(&bp->pdev->dev, skb->data,
595 bp->rx_buffer_size, DMA_FROM_DEVICE);
597 if (entry == RX_RING_SIZE - 1)
598 paddr |= MACB_BIT(RX_WRAP);
599 bp->rx_ring[entry].addr = paddr;
600 bp->rx_ring[entry].ctrl = 0;
602 /* properly align Ethernet header */
603 skb_reserve(skb, NET_IP_ALIGN);
607 /* Make descriptor updates visible to hardware */
610 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
611 bp->rx_prepared_head, bp->rx_tail);
614 /* Mark DMA descriptors from begin up to and not including end as unused */
615 static void discard_partial_frame(struct macb *bp, unsigned int begin,
620 for (frag = begin; frag != end; frag++) {
621 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
622 desc->addr &= ~MACB_BIT(RX_USED);
625 /* Make descriptor updates visible to hardware */
629 * When this happens, the hardware stats registers for
630 * whatever caused this is updated, so we don't have to record
635 static int gem_rx(struct macb *bp, int budget)
640 struct macb_dma_desc *desc;
643 while (count < budget) {
646 entry = macb_rx_ring_wrap(bp->rx_tail);
647 desc = &bp->rx_ring[entry];
649 /* Make hw descriptor updates visible to CPU */
655 if (!(addr & MACB_BIT(RX_USED)))
658 desc->addr &= ~MACB_BIT(RX_USED);
662 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
664 "not whole frame pointed by descriptor\n");
665 bp->stats.rx_dropped++;
668 skb = bp->rx_skbuff[entry];
669 if (unlikely(!skb)) {
671 "inconsistent Rx descriptor chain\n");
672 bp->stats.rx_dropped++;
675 /* now everything is ready for receiving packet */
676 bp->rx_skbuff[entry] = NULL;
677 len = MACB_BFEXT(RX_FRMLEN, ctrl);
679 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
682 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
683 dma_unmap_single(&bp->pdev->dev, addr,
684 len, DMA_FROM_DEVICE);
686 skb->protocol = eth_type_trans(skb, bp->dev);
687 skb_checksum_none_assert(skb);
689 bp->stats.rx_packets++;
690 bp->stats.rx_bytes += skb->len;
692 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
693 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
694 skb->len, skb->csum);
695 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
696 skb->mac_header, 16, true);
697 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
698 skb->data, 32, true);
701 netif_receive_skb(skb);
709 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
710 unsigned int last_frag)
716 struct macb_dma_desc *desc;
718 desc = macb_rx_desc(bp, last_frag);
719 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
721 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
722 macb_rx_ring_wrap(first_frag),
723 macb_rx_ring_wrap(last_frag), len);
726 * The ethernet header starts NET_IP_ALIGN bytes into the
727 * first buffer. Since the header is 14 bytes, this makes the
728 * payload word-aligned.
730 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
731 * the two padding bytes into the skb so that we avoid hitting
732 * the slowpath in memcpy(), and pull them off afterwards.
734 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
736 bp->stats.rx_dropped++;
737 for (frag = first_frag; ; frag++) {
738 desc = macb_rx_desc(bp, frag);
739 desc->addr &= ~MACB_BIT(RX_USED);
740 if (frag == last_frag)
744 /* Make descriptor updates visible to hardware */
752 skb_checksum_none_assert(skb);
755 for (frag = first_frag; ; frag++) {
756 unsigned int frag_len = bp->rx_buffer_size;
758 if (offset + frag_len > len) {
759 BUG_ON(frag != last_frag);
760 frag_len = len - offset;
762 skb_copy_to_linear_data_offset(skb, offset,
763 macb_rx_buffer(bp, frag), frag_len);
764 offset += bp->rx_buffer_size;
765 desc = macb_rx_desc(bp, frag);
766 desc->addr &= ~MACB_BIT(RX_USED);
768 if (frag == last_frag)
772 /* Make descriptor updates visible to hardware */
775 __skb_pull(skb, NET_IP_ALIGN);
776 skb->protocol = eth_type_trans(skb, bp->dev);
778 bp->stats.rx_packets++;
779 bp->stats.rx_bytes += skb->len;
780 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
781 skb->len, skb->csum);
782 netif_receive_skb(skb);
787 static int macb_rx(struct macb *bp, int budget)
793 for (tail = bp->rx_tail; budget > 0; tail++) {
794 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
797 /* Make hw descriptor updates visible to CPU */
803 if (!(addr & MACB_BIT(RX_USED)))
806 if (ctrl & MACB_BIT(RX_SOF)) {
807 if (first_frag != -1)
808 discard_partial_frame(bp, first_frag, tail);
812 if (ctrl & MACB_BIT(RX_EOF)) {
814 BUG_ON(first_frag == -1);
816 dropped = macb_rx_frame(bp, first_frag, tail);
825 if (first_frag != -1)
826 bp->rx_tail = first_frag;
833 static int macb_poll(struct napi_struct *napi, int budget)
835 struct macb *bp = container_of(napi, struct macb, napi);
839 status = macb_readl(bp, RSR);
840 macb_writel(bp, RSR, status);
844 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
845 (unsigned long)status, budget);
847 work_done = bp->macbgem_ops.mog_rx(bp, budget);
848 if (work_done < budget) {
852 * We've done what we can to clean the buffers. Make sure we
853 * get notified when new packets arrive.
855 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
857 /* Packets received while interrupts were disabled */
858 status = macb_readl(bp, RSR);
859 if (unlikely(status))
860 napi_reschedule(napi);
863 /* TODO: Handle errors */
868 static irqreturn_t macb_interrupt(int irq, void *dev_id)
870 struct net_device *dev = dev_id;
871 struct macb *bp = netdev_priv(dev);
874 status = macb_readl(bp, ISR);
876 if (unlikely(!status))
879 spin_lock(&bp->lock);
882 /* close possible race with dev_close */
883 if (unlikely(!netif_running(dev))) {
884 macb_writel(bp, IDR, -1);
888 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
890 if (status & MACB_RX_INT_FLAGS) {
892 * There's no point taking any more interrupts
893 * until we have processed the buffers. The
894 * scheduling call may fail if the poll routine
895 * is already scheduled, so disable interrupts
898 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
899 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
900 macb_writel(bp, ISR, MACB_BIT(RCOMP));
902 if (napi_schedule_prep(&bp->napi)) {
903 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
904 __napi_schedule(&bp->napi);
908 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
909 macb_writel(bp, IDR, MACB_TX_INT_FLAGS);
910 schedule_work(&bp->tx_error_task);
914 if (status & MACB_BIT(TCOMP))
915 macb_tx_interrupt(bp);
918 * Link change detection isn't possible with RMII, so we'll
919 * add that if/when we get our hands on a full-blown MII PHY.
922 if (status & MACB_BIT(ISR_ROVR)) {
923 /* We missed at least one packet */
925 bp->hw_stats.gem.rx_overruns++;
927 bp->hw_stats.macb.rx_overruns++;
930 if (status & MACB_BIT(HRESP)) {
932 * TODO: Reset the hardware, and maybe move the
933 * netdev_err to a lower-priority context as well
936 netdev_err(dev, "DMA bus error: HRESP not OK\n");
939 status = macb_readl(bp, ISR);
942 spin_unlock(&bp->lock);
947 #ifdef CONFIG_NET_POLL_CONTROLLER
949 * Polling receive - used by netconsole and other diagnostic tools
950 * to allow network i/o with interrupts disabled.
952 static void macb_poll_controller(struct net_device *dev)
956 local_irq_save(flags);
957 macb_interrupt(dev->irq, dev);
958 local_irq_restore(flags);
962 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
964 struct macb *bp = netdev_priv(dev);
966 unsigned int len, entry;
967 struct macb_dma_desc *desc;
968 struct macb_tx_skb *tx_skb;
972 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
974 "start_xmit: len %u head %p data %p tail %p end %p\n",
975 skb->len, skb->head, skb->data,
976 skb_tail_pointer(skb), skb_end_pointer(skb));
977 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
978 skb->data, 16, true);
982 spin_lock_irqsave(&bp->lock, flags);
984 /* This is a hard error, log it. */
985 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1) {
986 netif_stop_queue(dev);
987 spin_unlock_irqrestore(&bp->lock, flags);
988 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
989 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
990 bp->tx_head, bp->tx_tail);
991 return NETDEV_TX_BUSY;
994 entry = macb_tx_ring_wrap(bp->tx_head);
996 netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
997 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1000 tx_skb = &bp->tx_skb[entry];
1002 tx_skb->mapping = mapping;
1003 netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
1004 skb->data, (unsigned long)mapping);
1006 ctrl = MACB_BF(TX_FRMLEN, len);
1007 ctrl |= MACB_BIT(TX_LAST);
1008 if (entry == (TX_RING_SIZE - 1))
1009 ctrl |= MACB_BIT(TX_WRAP);
1011 desc = &bp->tx_ring[entry];
1012 desc->addr = mapping;
1015 /* Make newly initialized descriptor visible to hardware */
1018 skb_tx_timestamp(skb);
1020 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1022 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1)
1023 netif_stop_queue(dev);
1025 spin_unlock_irqrestore(&bp->lock, flags);
1027 return NETDEV_TX_OK;
1030 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1032 if (!macb_is_gem(bp)) {
1033 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1035 bp->rx_buffer_size = size;
1037 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1039 "RX buffer must be multiple of %d bytes, expanding\n",
1040 RX_BUFFER_MULTIPLE);
1041 bp->rx_buffer_size =
1042 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1046 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1047 bp->dev->mtu, bp->rx_buffer_size);
1050 static void gem_free_rx_buffers(struct macb *bp)
1052 struct sk_buff *skb;
1053 struct macb_dma_desc *desc;
1060 for (i = 0; i < RX_RING_SIZE; i++) {
1061 skb = bp->rx_skbuff[i];
1066 desc = &bp->rx_ring[i];
1067 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1068 dma_unmap_single(&bp->pdev->dev, addr, skb->len,
1070 dev_kfree_skb_any(skb);
1074 kfree(bp->rx_skbuff);
1075 bp->rx_skbuff = NULL;
1078 static void macb_free_rx_buffers(struct macb *bp)
1080 if (bp->rx_buffers) {
1081 dma_free_coherent(&bp->pdev->dev,
1082 RX_RING_SIZE * bp->rx_buffer_size,
1083 bp->rx_buffers, bp->rx_buffers_dma);
1084 bp->rx_buffers = NULL;
1088 static void macb_free_consistent(struct macb *bp)
1094 bp->macbgem_ops.mog_free_rx_buffers(bp);
1096 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1097 bp->rx_ring, bp->rx_ring_dma);
1101 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1102 bp->tx_ring, bp->tx_ring_dma);
1107 static int gem_alloc_rx_buffers(struct macb *bp)
1111 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1112 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1117 "Allocated %d RX struct sk_buff entries at %p\n",
1118 RX_RING_SIZE, bp->rx_skbuff);
1122 static int macb_alloc_rx_buffers(struct macb *bp)
1126 size = RX_RING_SIZE * bp->rx_buffer_size;
1127 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1128 &bp->rx_buffers_dma, GFP_KERNEL);
1129 if (!bp->rx_buffers)
1133 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1134 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1138 static int macb_alloc_consistent(struct macb *bp)
1142 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1143 bp->tx_skb = kmalloc(size, GFP_KERNEL);
1147 size = RX_RING_BYTES;
1148 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1149 &bp->rx_ring_dma, GFP_KERNEL);
1153 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1154 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1156 size = TX_RING_BYTES;
1157 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1158 &bp->tx_ring_dma, GFP_KERNEL);
1162 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
1163 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
1165 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1171 macb_free_consistent(bp);
1175 static void gem_init_rings(struct macb *bp)
1179 for (i = 0; i < TX_RING_SIZE; i++) {
1180 bp->tx_ring[i].addr = 0;
1181 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1183 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1185 bp->rx_tail = bp->rx_prepared_head = bp->tx_head = bp->tx_tail = 0;
1190 static void macb_init_rings(struct macb *bp)
1195 addr = bp->rx_buffers_dma;
1196 for (i = 0; i < RX_RING_SIZE; i++) {
1197 bp->rx_ring[i].addr = addr;
1198 bp->rx_ring[i].ctrl = 0;
1199 addr += bp->rx_buffer_size;
1201 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1203 for (i = 0; i < TX_RING_SIZE; i++) {
1204 bp->tx_ring[i].addr = 0;
1205 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1207 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1209 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
1212 static void macb_reset_hw(struct macb *bp)
1215 * Disable RX and TX (XXX: Should we halt the transmission
1218 macb_writel(bp, NCR, 0);
1220 /* Clear the stats registers (XXX: Update stats first?) */
1221 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1223 /* Clear all status flags */
1224 macb_writel(bp, TSR, -1);
1225 macb_writel(bp, RSR, -1);
1227 /* Disable all interrupts */
1228 macb_writel(bp, IDR, -1);
1229 macb_readl(bp, ISR);
1232 static u32 gem_mdc_clk_div(struct macb *bp)
1235 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1237 if (pclk_hz <= 20000000)
1238 config = GEM_BF(CLK, GEM_CLK_DIV8);
1239 else if (pclk_hz <= 40000000)
1240 config = GEM_BF(CLK, GEM_CLK_DIV16);
1241 else if (pclk_hz <= 80000000)
1242 config = GEM_BF(CLK, GEM_CLK_DIV32);
1243 else if (pclk_hz <= 120000000)
1244 config = GEM_BF(CLK, GEM_CLK_DIV48);
1245 else if (pclk_hz <= 160000000)
1246 config = GEM_BF(CLK, GEM_CLK_DIV64);
1248 config = GEM_BF(CLK, GEM_CLK_DIV96);
1253 static u32 macb_mdc_clk_div(struct macb *bp)
1256 unsigned long pclk_hz;
1258 if (macb_is_gem(bp))
1259 return gem_mdc_clk_div(bp);
1261 pclk_hz = clk_get_rate(bp->pclk);
1262 if (pclk_hz <= 20000000)
1263 config = MACB_BF(CLK, MACB_CLK_DIV8);
1264 else if (pclk_hz <= 40000000)
1265 config = MACB_BF(CLK, MACB_CLK_DIV16);
1266 else if (pclk_hz <= 80000000)
1267 config = MACB_BF(CLK, MACB_CLK_DIV32);
1269 config = MACB_BF(CLK, MACB_CLK_DIV64);
1275 * Get the DMA bus width field of the network configuration register that we
1276 * should program. We find the width from decoding the design configuration
1277 * register to find the maximum supported data bus width.
1279 static u32 macb_dbw(struct macb *bp)
1281 if (!macb_is_gem(bp))
1284 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1286 return GEM_BF(DBW, GEM_DBW128);
1288 return GEM_BF(DBW, GEM_DBW64);
1291 return GEM_BF(DBW, GEM_DBW32);
1296 * Configure the receive DMA engine
1297 * - use the correct receive buffer size
1298 * - set the possibility to use INCR16 bursts
1299 * (if not supported by FIFO, it will fallback to default)
1300 * - set both rx/tx packet buffers to full memory size
1301 * These are configurable parameters for GEM.
1303 static void macb_configure_dma(struct macb *bp)
1307 if (macb_is_gem(bp)) {
1308 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1309 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1310 dmacfg |= GEM_BF(FBLDO, 16);
1311 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1312 dmacfg &= ~GEM_BIT(ENDIA);
1313 gem_writel(bp, DMACFG, dmacfg);
1318 * Configure peripheral capacities according to integration options used
1320 static void macb_configure_caps(struct macb *bp)
1322 if (macb_is_gem(bp)) {
1323 if (GEM_BFEXT(IRQCOR, gem_readl(bp, DCFG1)) == 0)
1324 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
1328 static void macb_init_hw(struct macb *bp)
1333 macb_set_hwaddr(bp);
1335 config = macb_mdc_clk_div(bp);
1336 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1337 config |= MACB_BIT(PAE); /* PAuse Enable */
1338 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1339 config |= MACB_BIT(BIG); /* Receive oversized frames */
1340 if (bp->dev->flags & IFF_PROMISC)
1341 config |= MACB_BIT(CAF); /* Copy All Frames */
1342 if (!(bp->dev->flags & IFF_BROADCAST))
1343 config |= MACB_BIT(NBC); /* No BroadCast */
1344 config |= macb_dbw(bp);
1345 macb_writel(bp, NCFGR, config);
1346 bp->speed = SPEED_10;
1347 bp->duplex = DUPLEX_HALF;
1349 macb_configure_dma(bp);
1350 macb_configure_caps(bp);
1352 /* Initialize TX and RX buffers */
1353 macb_writel(bp, RBQP, bp->rx_ring_dma);
1354 macb_writel(bp, TBQP, bp->tx_ring_dma);
1356 /* Enable TX and RX */
1357 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1359 /* Enable interrupts */
1360 macb_writel(bp, IER, (MACB_RX_INT_FLAGS
1362 | MACB_BIT(HRESP)));
1367 * The hash address register is 64 bits long and takes up two
1368 * locations in the memory map. The least significant bits are stored
1369 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1371 * The unicast hash enable and the multicast hash enable bits in the
1372 * network configuration register enable the reception of hash matched
1373 * frames. The destination address is reduced to a 6 bit index into
1374 * the 64 bit hash register using the following hash function. The
1375 * hash function is an exclusive or of every sixth bit of the
1376 * destination address.
1378 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1379 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1380 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1381 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1382 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1383 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1385 * da[0] represents the least significant bit of the first byte
1386 * received, that is, the multicast/unicast indicator, and da[47]
1387 * represents the most significant bit of the last byte received. If
1388 * the hash index, hi[n], points to a bit that is set in the hash
1389 * register then the frame will be matched according to whether the
1390 * frame is multicast or unicast. A multicast match will be signalled
1391 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1392 * index points to a bit set in the hash register. A unicast match
1393 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1394 * and the hash index points to a bit set in the hash register. To
1395 * receive all multicast frames, the hash register should be set with
1396 * all ones and the multicast hash enable bit should be set in the
1397 * network configuration register.
1400 static inline int hash_bit_value(int bitnr, __u8 *addr)
1402 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1408 * Return the hash index value for the specified address.
1410 static int hash_get_index(__u8 *addr)
1415 for (j = 0; j < 6; j++) {
1416 for (i = 0, bitval = 0; i < 8; i++)
1417 bitval ^= hash_bit_value(i*6 + j, addr);
1419 hash_index |= (bitval << j);
1426 * Add multicast addresses to the internal multicast-hash table.
1428 static void macb_sethashtable(struct net_device *dev)
1430 struct netdev_hw_addr *ha;
1431 unsigned long mc_filter[2];
1433 struct macb *bp = netdev_priv(dev);
1435 mc_filter[0] = mc_filter[1] = 0;
1437 netdev_for_each_mc_addr(ha, dev) {
1438 bitnr = hash_get_index(ha->addr);
1439 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1442 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1443 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1447 * Enable/Disable promiscuous and multicast modes.
1449 void macb_set_rx_mode(struct net_device *dev)
1452 struct macb *bp = netdev_priv(dev);
1454 cfg = macb_readl(bp, NCFGR);
1456 if (dev->flags & IFF_PROMISC)
1457 /* Enable promiscuous mode */
1458 cfg |= MACB_BIT(CAF);
1459 else if (dev->flags & (~IFF_PROMISC))
1460 /* Disable promiscuous mode */
1461 cfg &= ~MACB_BIT(CAF);
1463 if (dev->flags & IFF_ALLMULTI) {
1464 /* Enable all multicast mode */
1465 macb_or_gem_writel(bp, HRB, -1);
1466 macb_or_gem_writel(bp, HRT, -1);
1467 cfg |= MACB_BIT(NCFGR_MTI);
1468 } else if (!netdev_mc_empty(dev)) {
1469 /* Enable specific multicasts */
1470 macb_sethashtable(dev);
1471 cfg |= MACB_BIT(NCFGR_MTI);
1472 } else if (dev->flags & (~IFF_ALLMULTI)) {
1473 /* Disable all multicast mode */
1474 macb_or_gem_writel(bp, HRB, 0);
1475 macb_or_gem_writel(bp, HRT, 0);
1476 cfg &= ~MACB_BIT(NCFGR_MTI);
1479 macb_writel(bp, NCFGR, cfg);
1481 EXPORT_SYMBOL_GPL(macb_set_rx_mode);
1483 static int macb_open(struct net_device *dev)
1485 struct macb *bp = netdev_priv(dev);
1486 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1489 netdev_dbg(bp->dev, "open\n");
1491 /* carrier starts down */
1492 netif_carrier_off(dev);
1494 /* if the phy is not yet register, retry later*/
1498 /* RX buffers initialization */
1499 macb_init_rx_buffer_size(bp, bufsz);
1501 err = macb_alloc_consistent(bp);
1503 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1508 napi_enable(&bp->napi);
1510 bp->macbgem_ops.mog_init_rings(bp);
1513 /* schedule a link state check */
1514 phy_start(bp->phy_dev);
1516 netif_start_queue(dev);
1521 static int macb_close(struct net_device *dev)
1523 struct macb *bp = netdev_priv(dev);
1524 unsigned long flags;
1526 netif_stop_queue(dev);
1527 napi_disable(&bp->napi);
1530 phy_stop(bp->phy_dev);
1532 spin_lock_irqsave(&bp->lock, flags);
1534 netif_carrier_off(dev);
1535 spin_unlock_irqrestore(&bp->lock, flags);
1537 macb_free_consistent(bp);
1542 static void gem_update_stats(struct macb *bp)
1544 u32 __iomem *reg = bp->regs + GEM_OTX;
1545 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1546 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1548 for (; p < end; p++, reg++)
1549 *p += __raw_readl(reg);
1552 static struct net_device_stats *gem_get_stats(struct macb *bp)
1554 struct gem_stats *hwstat = &bp->hw_stats.gem;
1555 struct net_device_stats *nstat = &bp->stats;
1557 gem_update_stats(bp);
1559 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1560 hwstat->rx_alignment_errors +
1561 hwstat->rx_resource_errors +
1562 hwstat->rx_overruns +
1563 hwstat->rx_oversize_frames +
1564 hwstat->rx_jabbers +
1565 hwstat->rx_undersized_frames +
1566 hwstat->rx_length_field_frame_errors);
1567 nstat->tx_errors = (hwstat->tx_late_collisions +
1568 hwstat->tx_excessive_collisions +
1569 hwstat->tx_underrun +
1570 hwstat->tx_carrier_sense_errors);
1571 nstat->multicast = hwstat->rx_multicast_frames;
1572 nstat->collisions = (hwstat->tx_single_collision_frames +
1573 hwstat->tx_multiple_collision_frames +
1574 hwstat->tx_excessive_collisions);
1575 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1576 hwstat->rx_jabbers +
1577 hwstat->rx_undersized_frames +
1578 hwstat->rx_length_field_frame_errors);
1579 nstat->rx_over_errors = hwstat->rx_resource_errors;
1580 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1581 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1582 nstat->rx_fifo_errors = hwstat->rx_overruns;
1583 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1584 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1585 nstat->tx_fifo_errors = hwstat->tx_underrun;
1590 struct net_device_stats *macb_get_stats(struct net_device *dev)
1592 struct macb *bp = netdev_priv(dev);
1593 struct net_device_stats *nstat = &bp->stats;
1594 struct macb_stats *hwstat = &bp->hw_stats.macb;
1596 if (macb_is_gem(bp))
1597 return gem_get_stats(bp);
1599 /* read stats from hardware */
1600 macb_update_stats(bp);
1602 /* Convert HW stats into netdevice stats */
1603 nstat->rx_errors = (hwstat->rx_fcs_errors +
1604 hwstat->rx_align_errors +
1605 hwstat->rx_resource_errors +
1606 hwstat->rx_overruns +
1607 hwstat->rx_oversize_pkts +
1608 hwstat->rx_jabbers +
1609 hwstat->rx_undersize_pkts +
1610 hwstat->sqe_test_errors +
1611 hwstat->rx_length_mismatch);
1612 nstat->tx_errors = (hwstat->tx_late_cols +
1613 hwstat->tx_excessive_cols +
1614 hwstat->tx_underruns +
1615 hwstat->tx_carrier_errors);
1616 nstat->collisions = (hwstat->tx_single_cols +
1617 hwstat->tx_multiple_cols +
1618 hwstat->tx_excessive_cols);
1619 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1620 hwstat->rx_jabbers +
1621 hwstat->rx_undersize_pkts +
1622 hwstat->rx_length_mismatch);
1623 nstat->rx_over_errors = hwstat->rx_resource_errors +
1624 hwstat->rx_overruns;
1625 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1626 nstat->rx_frame_errors = hwstat->rx_align_errors;
1627 nstat->rx_fifo_errors = hwstat->rx_overruns;
1628 /* XXX: What does "missed" mean? */
1629 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1630 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1631 nstat->tx_fifo_errors = hwstat->tx_underruns;
1632 /* Don't know about heartbeat or window errors... */
1636 EXPORT_SYMBOL_GPL(macb_get_stats);
1638 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1640 struct macb *bp = netdev_priv(dev);
1641 struct phy_device *phydev = bp->phy_dev;
1646 return phy_ethtool_gset(phydev, cmd);
1649 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1651 struct macb *bp = netdev_priv(dev);
1652 struct phy_device *phydev = bp->phy_dev;
1657 return phy_ethtool_sset(phydev, cmd);
1660 static int macb_get_regs_len(struct net_device *netdev)
1662 return MACB_GREGS_NBR * sizeof(u32);
1665 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1668 struct macb *bp = netdev_priv(dev);
1669 unsigned int tail, head;
1672 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1673 | MACB_GREGS_VERSION;
1675 tail = macb_tx_ring_wrap(bp->tx_tail);
1676 head = macb_tx_ring_wrap(bp->tx_head);
1678 regs_buff[0] = macb_readl(bp, NCR);
1679 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1680 regs_buff[2] = macb_readl(bp, NSR);
1681 regs_buff[3] = macb_readl(bp, TSR);
1682 regs_buff[4] = macb_readl(bp, RBQP);
1683 regs_buff[5] = macb_readl(bp, TBQP);
1684 regs_buff[6] = macb_readl(bp, RSR);
1685 regs_buff[7] = macb_readl(bp, IMR);
1687 regs_buff[8] = tail;
1688 regs_buff[9] = head;
1689 regs_buff[10] = macb_tx_dma(bp, tail);
1690 regs_buff[11] = macb_tx_dma(bp, head);
1692 if (macb_is_gem(bp)) {
1693 regs_buff[12] = gem_readl(bp, USRIO);
1694 regs_buff[13] = gem_readl(bp, DMACFG);
1698 const struct ethtool_ops macb_ethtool_ops = {
1699 .get_settings = macb_get_settings,
1700 .set_settings = macb_set_settings,
1701 .get_regs_len = macb_get_regs_len,
1702 .get_regs = macb_get_regs,
1703 .get_link = ethtool_op_get_link,
1704 .get_ts_info = ethtool_op_get_ts_info,
1706 EXPORT_SYMBOL_GPL(macb_ethtool_ops);
1708 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1710 struct macb *bp = netdev_priv(dev);
1711 struct phy_device *phydev = bp->phy_dev;
1713 if (!netif_running(dev))
1719 return phy_mii_ioctl(phydev, rq, cmd);
1721 EXPORT_SYMBOL_GPL(macb_ioctl);
1723 static const struct net_device_ops macb_netdev_ops = {
1724 .ndo_open = macb_open,
1725 .ndo_stop = macb_close,
1726 .ndo_start_xmit = macb_start_xmit,
1727 .ndo_set_rx_mode = macb_set_rx_mode,
1728 .ndo_get_stats = macb_get_stats,
1729 .ndo_do_ioctl = macb_ioctl,
1730 .ndo_validate_addr = eth_validate_addr,
1731 .ndo_change_mtu = eth_change_mtu,
1732 .ndo_set_mac_address = eth_mac_addr,
1733 #ifdef CONFIG_NET_POLL_CONTROLLER
1734 .ndo_poll_controller = macb_poll_controller,
1738 #if defined(CONFIG_OF)
1739 static const struct of_device_id macb_dt_ids[] = {
1740 { .compatible = "cdns,at32ap7000-macb" },
1741 { .compatible = "cdns,at91sam9260-macb" },
1742 { .compatible = "cdns,macb" },
1743 { .compatible = "cdns,pc302-gem" },
1744 { .compatible = "cdns,gem" },
1747 MODULE_DEVICE_TABLE(of, macb_dt_ids);
1750 static int __init macb_probe(struct platform_device *pdev)
1752 struct macb_platform_data *pdata;
1753 struct resource *regs;
1754 struct net_device *dev;
1756 struct phy_device *phydev;
1759 struct pinctrl *pinctrl;
1762 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1764 dev_err(&pdev->dev, "no mmio resource defined\n");
1768 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1769 if (IS_ERR(pinctrl)) {
1770 err = PTR_ERR(pinctrl);
1771 if (err == -EPROBE_DEFER)
1774 dev_warn(&pdev->dev, "No pinctrl provided\n");
1778 dev = alloc_etherdev(sizeof(*bp));
1782 SET_NETDEV_DEV(dev, &pdev->dev);
1784 /* TODO: Actually, we have some interesting features... */
1787 bp = netdev_priv(dev);
1791 spin_lock_init(&bp->lock);
1792 INIT_WORK(&bp->tx_error_task, macb_tx_error_task);
1794 bp->pclk = devm_clk_get(&pdev->dev, "pclk");
1795 if (IS_ERR(bp->pclk)) {
1796 err = PTR_ERR(bp->pclk);
1797 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
1798 goto err_out_free_dev;
1801 bp->hclk = devm_clk_get(&pdev->dev, "hclk");
1802 if (IS_ERR(bp->hclk)) {
1803 err = PTR_ERR(bp->hclk);
1804 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
1805 goto err_out_free_dev;
1808 err = clk_prepare_enable(bp->pclk);
1810 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
1811 goto err_out_free_dev;
1814 err = clk_prepare_enable(bp->hclk);
1816 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
1817 goto err_out_disable_pclk;
1820 bp->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
1822 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1824 goto err_out_disable_clocks;
1827 dev->irq = platform_get_irq(pdev, 0);
1828 err = devm_request_irq(&pdev->dev, dev->irq, macb_interrupt, 0,
1831 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1833 goto err_out_disable_clocks;
1836 dev->netdev_ops = &macb_netdev_ops;
1837 netif_napi_add(dev, &bp->napi, macb_poll, 64);
1838 dev->ethtool_ops = &macb_ethtool_ops;
1840 dev->base_addr = regs->start;
1842 /* setup appropriated routines according to adapter type */
1843 if (macb_is_gem(bp)) {
1844 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
1845 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
1846 bp->macbgem_ops.mog_init_rings = gem_init_rings;
1847 bp->macbgem_ops.mog_rx = gem_rx;
1849 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
1850 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
1851 bp->macbgem_ops.mog_init_rings = macb_init_rings;
1852 bp->macbgem_ops.mog_rx = macb_rx;
1855 /* Set MII management clock divider */
1856 config = macb_mdc_clk_div(bp);
1857 config |= macb_dbw(bp);
1858 macb_writel(bp, NCFGR, config);
1860 mac = of_get_mac_address(pdev->dev.of_node);
1862 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1864 macb_get_hwaddr(bp);
1866 err = of_get_phy_mode(pdev->dev.of_node);
1868 pdata = dev_get_platdata(&pdev->dev);
1869 if (pdata && pdata->is_rmii)
1870 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1872 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1874 bp->phy_interface = err;
1877 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
1878 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
1879 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
1880 #if defined(CONFIG_ARCH_AT91)
1881 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1884 macb_or_gem_writel(bp, USRIO, 0);
1887 #if defined(CONFIG_ARCH_AT91)
1888 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
1890 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
1893 err = register_netdev(dev);
1895 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1896 goto err_out_disable_clocks;
1899 err = macb_mii_init(bp);
1901 goto err_out_unregister_netdev;
1903 platform_set_drvdata(pdev, dev);
1905 netif_carrier_off(dev);
1907 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1908 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1909 dev->irq, dev->dev_addr);
1911 phydev = bp->phy_dev;
1912 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1913 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1917 err_out_unregister_netdev:
1918 unregister_netdev(dev);
1919 err_out_disable_clocks:
1920 clk_disable_unprepare(bp->hclk);
1921 err_out_disable_pclk:
1922 clk_disable_unprepare(bp->pclk);
1929 static int __exit macb_remove(struct platform_device *pdev)
1931 struct net_device *dev;
1934 dev = platform_get_drvdata(pdev);
1937 bp = netdev_priv(dev);
1939 phy_disconnect(bp->phy_dev);
1940 mdiobus_unregister(bp->mii_bus);
1941 kfree(bp->mii_bus->irq);
1942 mdiobus_free(bp->mii_bus);
1943 unregister_netdev(dev);
1944 clk_disable_unprepare(bp->hclk);
1945 clk_disable_unprepare(bp->pclk);
1953 static int macb_suspend(struct device *dev)
1955 struct platform_device *pdev = to_platform_device(dev);
1956 struct net_device *netdev = platform_get_drvdata(pdev);
1957 struct macb *bp = netdev_priv(netdev);
1959 netif_carrier_off(netdev);
1960 netif_device_detach(netdev);
1962 clk_disable_unprepare(bp->hclk);
1963 clk_disable_unprepare(bp->pclk);
1968 static int macb_resume(struct device *dev)
1970 struct platform_device *pdev = to_platform_device(dev);
1971 struct net_device *netdev = platform_get_drvdata(pdev);
1972 struct macb *bp = netdev_priv(netdev);
1974 clk_prepare_enable(bp->pclk);
1975 clk_prepare_enable(bp->hclk);
1977 netif_device_attach(netdev);
1983 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
1985 static struct platform_driver macb_driver = {
1986 .remove = __exit_p(macb_remove),
1989 .owner = THIS_MODULE,
1990 .of_match_table = of_match_ptr(macb_dt_ids),
1995 module_platform_driver_probe(macb_driver, macb_probe);
1997 MODULE_LICENSE("GPL");
1998 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
1999 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2000 MODULE_ALIAS("platform:macb");