2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
20 #include <linux/gpio.h>
21 #include <linux/interrupt.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_data/macb.h>
26 #include <linux/platform_device.h>
27 #include <linux/phy.h>
29 #include <linux/of_device.h>
30 #include <linux/of_net.h>
31 #include <linux/pinctrl/consumer.h>
35 #define MACB_RX_BUFFER_SIZE 128
36 #define GEM_RX_BUFFER_SIZE 2048
37 #define RX_BUFFER_MULTIPLE 64 /* bytes */
38 #define RX_RING_SIZE 512 /* must be power of 2 */
39 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
41 #define TX_RING_SIZE 128 /* must be power of 2 */
42 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
44 /* level of occupied TX descriptors under which we wake up TX process */
45 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
47 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
49 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
52 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
55 * Graceful stop timeouts in us. We should allow up to
56 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
58 #define MACB_HALT_TIMEOUT 1230
60 /* Ring buffer accessors */
61 static unsigned int macb_tx_ring_wrap(unsigned int index)
63 return index & (TX_RING_SIZE - 1);
66 static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
68 return &bp->tx_ring[macb_tx_ring_wrap(index)];
71 static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
73 return &bp->tx_skb[macb_tx_ring_wrap(index)];
76 static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
80 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
82 return bp->tx_ring_dma + offset;
85 static unsigned int macb_rx_ring_wrap(unsigned int index)
87 return index & (RX_RING_SIZE - 1);
90 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
92 return &bp->rx_ring[macb_rx_ring_wrap(index)];
95 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
97 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
100 void macb_set_hwaddr(struct macb *bp)
105 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
106 macb_or_gem_writel(bp, SA1B, bottom);
107 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
108 macb_or_gem_writel(bp, SA1T, top);
110 /* Clear unused address register sets */
111 macb_or_gem_writel(bp, SA2B, 0);
112 macb_or_gem_writel(bp, SA2T, 0);
113 macb_or_gem_writel(bp, SA3B, 0);
114 macb_or_gem_writel(bp, SA3T, 0);
115 macb_or_gem_writel(bp, SA4B, 0);
116 macb_or_gem_writel(bp, SA4T, 0);
118 EXPORT_SYMBOL_GPL(macb_set_hwaddr);
120 void macb_get_hwaddr(struct macb *bp)
122 struct macb_platform_data *pdata;
128 pdata = bp->pdev->dev.platform_data;
130 /* Check all 4 address register for vaild address */
131 for (i = 0; i < 4; i++) {
132 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
133 top = macb_or_gem_readl(bp, SA1T + i * 8);
135 if (pdata && pdata->rev_eth_addr) {
136 addr[5] = bottom & 0xff;
137 addr[4] = (bottom >> 8) & 0xff;
138 addr[3] = (bottom >> 16) & 0xff;
139 addr[2] = (bottom >> 24) & 0xff;
140 addr[1] = top & 0xff;
141 addr[0] = (top & 0xff00) >> 8;
143 addr[0] = bottom & 0xff;
144 addr[1] = (bottom >> 8) & 0xff;
145 addr[2] = (bottom >> 16) & 0xff;
146 addr[3] = (bottom >> 24) & 0xff;
147 addr[4] = top & 0xff;
148 addr[5] = (top >> 8) & 0xff;
151 if (is_valid_ether_addr(addr)) {
152 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
157 netdev_info(bp->dev, "invalid hw address, using random\n");
158 eth_hw_addr_random(bp->dev);
160 EXPORT_SYMBOL_GPL(macb_get_hwaddr);
162 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
164 struct macb *bp = bus->priv;
167 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
168 | MACB_BF(RW, MACB_MAN_READ)
169 | MACB_BF(PHYA, mii_id)
170 | MACB_BF(REGA, regnum)
171 | MACB_BF(CODE, MACB_MAN_CODE)));
173 /* wait for end of transfer */
174 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
177 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
182 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
185 struct macb *bp = bus->priv;
187 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
188 | MACB_BF(RW, MACB_MAN_WRITE)
189 | MACB_BF(PHYA, mii_id)
190 | MACB_BF(REGA, regnum)
191 | MACB_BF(CODE, MACB_MAN_CODE)
192 | MACB_BF(DATA, value)));
194 /* wait for end of transfer */
195 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
201 static int macb_mdio_reset(struct mii_bus *bus)
206 static void macb_handle_link_change(struct net_device *dev)
208 struct macb *bp = netdev_priv(dev);
209 struct phy_device *phydev = bp->phy_dev;
212 int status_change = 0;
214 spin_lock_irqsave(&bp->lock, flags);
217 if ((bp->speed != phydev->speed) ||
218 (bp->duplex != phydev->duplex)) {
221 reg = macb_readl(bp, NCFGR);
222 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
224 reg &= ~GEM_BIT(GBE);
228 if (phydev->speed == SPEED_100)
229 reg |= MACB_BIT(SPD);
230 if (phydev->speed == SPEED_1000)
233 macb_or_gem_writel(bp, NCFGR, reg);
235 bp->speed = phydev->speed;
236 bp->duplex = phydev->duplex;
241 if (phydev->link != bp->link) {
246 bp->link = phydev->link;
251 spin_unlock_irqrestore(&bp->lock, flags);
255 netif_carrier_on(dev);
256 netdev_info(dev, "link up (%d/%s)\n",
258 phydev->duplex == DUPLEX_FULL ?
261 netif_carrier_off(dev);
262 netdev_info(dev, "link down\n");
267 /* based on au1000_eth. c*/
268 static int macb_mii_probe(struct net_device *dev)
270 struct macb *bp = netdev_priv(dev);
271 struct macb_platform_data *pdata;
272 struct phy_device *phydev;
276 phydev = phy_find_first(bp->mii_bus);
278 netdev_err(dev, "no PHY found\n");
282 pdata = dev_get_platdata(&bp->pdev->dev);
283 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
284 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
286 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
287 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
291 /* attach the mac to the phy */
292 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
295 netdev_err(dev, "Could not attach to PHY\n");
299 /* mask with MAC supported features */
301 phydev->supported &= PHY_GBIT_FEATURES;
303 phydev->supported &= PHY_BASIC_FEATURES;
305 phydev->advertising = phydev->supported;
310 bp->phy_dev = phydev;
315 int macb_mii_init(struct macb *bp)
317 struct macb_platform_data *pdata;
320 /* Enable management port */
321 macb_writel(bp, NCR, MACB_BIT(MPE));
323 bp->mii_bus = mdiobus_alloc();
324 if (bp->mii_bus == NULL) {
329 bp->mii_bus->name = "MACB_mii_bus";
330 bp->mii_bus->read = &macb_mdio_read;
331 bp->mii_bus->write = &macb_mdio_write;
332 bp->mii_bus->reset = &macb_mdio_reset;
333 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
334 bp->pdev->name, bp->pdev->id);
335 bp->mii_bus->priv = bp;
336 bp->mii_bus->parent = &bp->dev->dev;
337 pdata = bp->pdev->dev.platform_data;
340 bp->mii_bus->phy_mask = pdata->phy_mask;
342 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
343 if (!bp->mii_bus->irq) {
345 goto err_out_free_mdiobus;
348 for (i = 0; i < PHY_MAX_ADDR; i++)
349 bp->mii_bus->irq[i] = PHY_POLL;
351 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
353 if (mdiobus_register(bp->mii_bus))
354 goto err_out_free_mdio_irq;
356 if (macb_mii_probe(bp->dev) != 0) {
357 goto err_out_unregister_bus;
362 err_out_unregister_bus:
363 mdiobus_unregister(bp->mii_bus);
364 err_out_free_mdio_irq:
365 kfree(bp->mii_bus->irq);
366 err_out_free_mdiobus:
367 mdiobus_free(bp->mii_bus);
371 EXPORT_SYMBOL_GPL(macb_mii_init);
373 static void macb_update_stats(struct macb *bp)
375 u32 __iomem *reg = bp->regs + MACB_PFR;
376 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
377 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
379 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
381 for(; p < end; p++, reg++)
382 *p += __raw_readl(reg);
385 static int macb_halt_tx(struct macb *bp)
387 unsigned long halt_time, timeout;
390 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
392 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
395 status = macb_readl(bp, TSR);
396 if (!(status & MACB_BIT(TGO)))
399 usleep_range(10, 250);
400 } while (time_before(halt_time, timeout));
405 static void macb_tx_error_task(struct work_struct *work)
407 struct macb *bp = container_of(work, struct macb, tx_error_task);
408 struct macb_tx_skb *tx_skb;
412 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n",
413 bp->tx_tail, bp->tx_head);
415 /* Make sure nobody is trying to queue up new packets */
416 netif_stop_queue(bp->dev);
419 * Stop transmission now
420 * (in case we have just queued new packets)
422 if (macb_halt_tx(bp))
423 /* Just complain for now, reinitializing TX path can be good */
424 netdev_err(bp->dev, "BUG: halt tx timed out\n");
426 /* No need for the lock here as nobody will interrupt us anymore */
429 * Treat frames in TX queue including the ones that caused the error.
430 * Free transmit buffers in upper layer.
432 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) {
433 struct macb_dma_desc *desc;
436 desc = macb_tx_desc(bp, tail);
438 tx_skb = macb_tx_skb(bp, tail);
441 if (ctrl & MACB_BIT(TX_USED)) {
442 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
443 macb_tx_ring_wrap(tail), skb->data);
444 bp->stats.tx_packets++;
445 bp->stats.tx_bytes += skb->len;
448 * "Buffers exhausted mid-frame" errors may only happen
449 * if the driver is buggy, so complain loudly about those.
450 * Statistics are updated by hardware.
452 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
454 "BUG: TX buffers exhausted mid-frame\n");
456 desc->ctrl = ctrl | MACB_BIT(TX_USED);
459 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
465 /* Make descriptor updates visible to hardware */
468 /* Reinitialize the TX desc queue */
469 macb_writel(bp, TBQP, bp->tx_ring_dma);
470 /* Make TX ring reflect state of hardware */
471 bp->tx_head = bp->tx_tail = 0;
473 /* Now we are ready to start transmission again */
474 netif_wake_queue(bp->dev);
476 /* Housework before enabling TX IRQ */
477 macb_writel(bp, TSR, macb_readl(bp, TSR));
478 macb_writel(bp, IER, MACB_TX_INT_FLAGS);
481 static void macb_tx_interrupt(struct macb *bp)
487 status = macb_readl(bp, TSR);
488 macb_writel(bp, TSR, status);
490 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
491 macb_writel(bp, ISR, MACB_BIT(TCOMP));
493 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
494 (unsigned long)status);
497 for (tail = bp->tx_tail; tail != head; tail++) {
498 struct macb_tx_skb *tx_skb;
500 struct macb_dma_desc *desc;
503 desc = macb_tx_desc(bp, tail);
505 /* Make hw descriptor updates visible to CPU */
510 if (!(ctrl & MACB_BIT(TX_USED)))
513 tx_skb = macb_tx_skb(bp, tail);
516 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
517 macb_tx_ring_wrap(tail), skb->data);
518 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
520 bp->stats.tx_packets++;
521 bp->stats.tx_bytes += skb->len;
523 dev_kfree_skb_irq(skb);
527 if (netif_queue_stopped(bp->dev)
528 && CIRC_CNT(bp->tx_head, bp->tx_tail,
529 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
530 netif_wake_queue(bp->dev);
533 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
534 unsigned int last_frag)
540 struct macb_dma_desc *desc;
542 desc = macb_rx_desc(bp, last_frag);
543 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
545 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
546 macb_rx_ring_wrap(first_frag),
547 macb_rx_ring_wrap(last_frag), len);
550 * The ethernet header starts NET_IP_ALIGN bytes into the
551 * first buffer. Since the header is 14 bytes, this makes the
552 * payload word-aligned.
554 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
555 * the two padding bytes into the skb so that we avoid hitting
556 * the slowpath in memcpy(), and pull them off afterwards.
558 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
560 bp->stats.rx_dropped++;
561 for (frag = first_frag; ; frag++) {
562 desc = macb_rx_desc(bp, frag);
563 desc->addr &= ~MACB_BIT(RX_USED);
564 if (frag == last_frag)
568 /* Make descriptor updates visible to hardware */
576 skb_checksum_none_assert(skb);
579 for (frag = first_frag; ; frag++) {
580 unsigned int frag_len = bp->rx_buffer_size;
582 if (offset + frag_len > len) {
583 BUG_ON(frag != last_frag);
584 frag_len = len - offset;
586 skb_copy_to_linear_data_offset(skb, offset,
587 macb_rx_buffer(bp, frag), frag_len);
588 offset += bp->rx_buffer_size;
589 desc = macb_rx_desc(bp, frag);
590 desc->addr &= ~MACB_BIT(RX_USED);
592 if (frag == last_frag)
596 /* Make descriptor updates visible to hardware */
599 __skb_pull(skb, NET_IP_ALIGN);
600 skb->protocol = eth_type_trans(skb, bp->dev);
602 bp->stats.rx_packets++;
603 bp->stats.rx_bytes += skb->len;
604 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
605 skb->len, skb->csum);
606 netif_receive_skb(skb);
611 /* Mark DMA descriptors from begin up to and not including end as unused */
612 static void discard_partial_frame(struct macb *bp, unsigned int begin,
617 for (frag = begin; frag != end; frag++) {
618 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
619 desc->addr &= ~MACB_BIT(RX_USED);
622 /* Make descriptor updates visible to hardware */
626 * When this happens, the hardware stats registers for
627 * whatever caused this is updated, so we don't have to record
632 static int macb_rx(struct macb *bp, int budget)
638 for (tail = bp->rx_tail; budget > 0; tail++) {
639 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
642 /* Make hw descriptor updates visible to CPU */
648 if (!(addr & MACB_BIT(RX_USED)))
651 if (ctrl & MACB_BIT(RX_SOF)) {
652 if (first_frag != -1)
653 discard_partial_frame(bp, first_frag, tail);
657 if (ctrl & MACB_BIT(RX_EOF)) {
659 BUG_ON(first_frag == -1);
661 dropped = macb_rx_frame(bp, first_frag, tail);
670 if (first_frag != -1)
671 bp->rx_tail = first_frag;
678 static int macb_poll(struct napi_struct *napi, int budget)
680 struct macb *bp = container_of(napi, struct macb, napi);
684 status = macb_readl(bp, RSR);
685 macb_writel(bp, RSR, status);
689 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
690 (unsigned long)status, budget);
692 work_done = macb_rx(bp, budget);
693 if (work_done < budget) {
697 * We've done what we can to clean the buffers. Make sure we
698 * get notified when new packets arrive.
700 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
702 /* Packets received while interrupts were disabled */
703 status = macb_readl(bp, RSR);
704 if (unlikely(status))
705 napi_reschedule(napi);
708 /* TODO: Handle errors */
713 static irqreturn_t macb_interrupt(int irq, void *dev_id)
715 struct net_device *dev = dev_id;
716 struct macb *bp = netdev_priv(dev);
719 status = macb_readl(bp, ISR);
721 if (unlikely(!status))
724 spin_lock(&bp->lock);
727 /* close possible race with dev_close */
728 if (unlikely(!netif_running(dev))) {
729 macb_writel(bp, IDR, -1);
733 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
735 if (status & MACB_RX_INT_FLAGS) {
737 * There's no point taking any more interrupts
738 * until we have processed the buffers. The
739 * scheduling call may fail if the poll routine
740 * is already scheduled, so disable interrupts
743 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
744 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
745 macb_writel(bp, ISR, MACB_BIT(RCOMP));
747 if (napi_schedule_prep(&bp->napi)) {
748 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
749 __napi_schedule(&bp->napi);
753 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
754 macb_writel(bp, IDR, MACB_TX_INT_FLAGS);
755 schedule_work(&bp->tx_error_task);
759 if (status & MACB_BIT(TCOMP))
760 macb_tx_interrupt(bp);
763 * Link change detection isn't possible with RMII, so we'll
764 * add that if/when we get our hands on a full-blown MII PHY.
767 if (status & MACB_BIT(ISR_ROVR)) {
768 /* We missed at least one packet */
770 bp->hw_stats.gem.rx_overruns++;
772 bp->hw_stats.macb.rx_overruns++;
775 if (status & MACB_BIT(HRESP)) {
777 * TODO: Reset the hardware, and maybe move the
778 * netdev_err to a lower-priority context as well
781 netdev_err(dev, "DMA bus error: HRESP not OK\n");
784 status = macb_readl(bp, ISR);
787 spin_unlock(&bp->lock);
792 #ifdef CONFIG_NET_POLL_CONTROLLER
794 * Polling receive - used by netconsole and other diagnostic tools
795 * to allow network i/o with interrupts disabled.
797 static void macb_poll_controller(struct net_device *dev)
801 local_irq_save(flags);
802 macb_interrupt(dev->irq, dev);
803 local_irq_restore(flags);
807 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
809 struct macb *bp = netdev_priv(dev);
811 unsigned int len, entry;
812 struct macb_dma_desc *desc;
813 struct macb_tx_skb *tx_skb;
817 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
819 "start_xmit: len %u head %p data %p tail %p end %p\n",
820 skb->len, skb->head, skb->data,
821 skb_tail_pointer(skb), skb_end_pointer(skb));
822 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
823 skb->data, 16, true);
827 spin_lock_irqsave(&bp->lock, flags);
829 /* This is a hard error, log it. */
830 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1) {
831 netif_stop_queue(dev);
832 spin_unlock_irqrestore(&bp->lock, flags);
833 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
834 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
835 bp->tx_head, bp->tx_tail);
836 return NETDEV_TX_BUSY;
839 entry = macb_tx_ring_wrap(bp->tx_head);
841 netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
842 mapping = dma_map_single(&bp->pdev->dev, skb->data,
845 tx_skb = &bp->tx_skb[entry];
847 tx_skb->mapping = mapping;
848 netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
849 skb->data, (unsigned long)mapping);
851 ctrl = MACB_BF(TX_FRMLEN, len);
852 ctrl |= MACB_BIT(TX_LAST);
853 if (entry == (TX_RING_SIZE - 1))
854 ctrl |= MACB_BIT(TX_WRAP);
856 desc = &bp->tx_ring[entry];
857 desc->addr = mapping;
860 /* Make newly initialized descriptor visible to hardware */
863 skb_tx_timestamp(skb);
865 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
867 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1)
868 netif_stop_queue(dev);
870 spin_unlock_irqrestore(&bp->lock, flags);
875 static void macb_init_rx_buffer_size(struct macb *bp)
877 if (!macb_is_gem(bp)) {
878 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
880 bp->rx_buffer_size = GEM_RX_BUFFER_SIZE;
882 if (bp->rx_buffer_size > PAGE_SIZE) {
884 "RX buffer cannot be bigger than PAGE_SIZE, shrinking\n");
885 bp->rx_buffer_size = PAGE_SIZE;
887 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
889 "RX buffer must be multiple of %d bytes, shrinking\n",
892 rounddown(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
894 bp->rx_buffer_size = max(RX_BUFFER_MULTIPLE, GEM_RX_BUFFER_SIZE);
899 static void macb_free_consistent(struct macb *bp)
906 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
907 bp->rx_ring, bp->rx_ring_dma);
911 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
912 bp->tx_ring, bp->tx_ring_dma);
915 if (bp->rx_buffers) {
916 dma_free_coherent(&bp->pdev->dev,
917 RX_RING_SIZE * bp->rx_buffer_size,
918 bp->rx_buffers, bp->rx_buffers_dma);
919 bp->rx_buffers = NULL;
923 static int macb_alloc_consistent(struct macb *bp)
927 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
928 bp->tx_skb = kmalloc(size, GFP_KERNEL);
932 size = RX_RING_BYTES;
933 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
934 &bp->rx_ring_dma, GFP_KERNEL);
938 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
939 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
941 size = TX_RING_BYTES;
942 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
943 &bp->tx_ring_dma, GFP_KERNEL);
947 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
948 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
950 size = RX_RING_SIZE * bp->rx_buffer_size;
951 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
952 &bp->rx_buffers_dma, GFP_KERNEL);
956 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
957 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
962 macb_free_consistent(bp);
966 static void macb_init_rings(struct macb *bp)
971 addr = bp->rx_buffers_dma;
972 for (i = 0; i < RX_RING_SIZE; i++) {
973 bp->rx_ring[i].addr = addr;
974 bp->rx_ring[i].ctrl = 0;
975 addr += bp->rx_buffer_size;
977 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
979 for (i = 0; i < TX_RING_SIZE; i++) {
980 bp->tx_ring[i].addr = 0;
981 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
983 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
985 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
988 static void macb_reset_hw(struct macb *bp)
991 * Disable RX and TX (XXX: Should we halt the transmission
994 macb_writel(bp, NCR, 0);
996 /* Clear the stats registers (XXX: Update stats first?) */
997 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
999 /* Clear all status flags */
1000 macb_writel(bp, TSR, -1);
1001 macb_writel(bp, RSR, -1);
1003 /* Disable all interrupts */
1004 macb_writel(bp, IDR, -1);
1005 macb_readl(bp, ISR);
1008 static u32 gem_mdc_clk_div(struct macb *bp)
1011 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1013 if (pclk_hz <= 20000000)
1014 config = GEM_BF(CLK, GEM_CLK_DIV8);
1015 else if (pclk_hz <= 40000000)
1016 config = GEM_BF(CLK, GEM_CLK_DIV16);
1017 else if (pclk_hz <= 80000000)
1018 config = GEM_BF(CLK, GEM_CLK_DIV32);
1019 else if (pclk_hz <= 120000000)
1020 config = GEM_BF(CLK, GEM_CLK_DIV48);
1021 else if (pclk_hz <= 160000000)
1022 config = GEM_BF(CLK, GEM_CLK_DIV64);
1024 config = GEM_BF(CLK, GEM_CLK_DIV96);
1029 static u32 macb_mdc_clk_div(struct macb *bp)
1032 unsigned long pclk_hz;
1034 if (macb_is_gem(bp))
1035 return gem_mdc_clk_div(bp);
1037 pclk_hz = clk_get_rate(bp->pclk);
1038 if (pclk_hz <= 20000000)
1039 config = MACB_BF(CLK, MACB_CLK_DIV8);
1040 else if (pclk_hz <= 40000000)
1041 config = MACB_BF(CLK, MACB_CLK_DIV16);
1042 else if (pclk_hz <= 80000000)
1043 config = MACB_BF(CLK, MACB_CLK_DIV32);
1045 config = MACB_BF(CLK, MACB_CLK_DIV64);
1051 * Get the DMA bus width field of the network configuration register that we
1052 * should program. We find the width from decoding the design configuration
1053 * register to find the maximum supported data bus width.
1055 static u32 macb_dbw(struct macb *bp)
1057 if (!macb_is_gem(bp))
1060 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1062 return GEM_BF(DBW, GEM_DBW128);
1064 return GEM_BF(DBW, GEM_DBW64);
1067 return GEM_BF(DBW, GEM_DBW32);
1072 * Configure the receive DMA engine
1073 * - use the correct receive buffer size
1074 * - set the possibility to use INCR16 bursts
1075 * (if not supported by FIFO, it will fallback to default)
1076 * - set both rx/tx packet buffers to full memory size
1077 * These are configurable parameters for GEM.
1079 static void macb_configure_dma(struct macb *bp)
1083 if (macb_is_gem(bp)) {
1084 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1085 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1086 dmacfg |= GEM_BF(FBLDO, 16);
1087 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1088 dmacfg &= ~GEM_BIT(ENDIA);
1089 gem_writel(bp, DMACFG, dmacfg);
1094 * Configure peripheral capacities according to integration options used
1096 static void macb_configure_caps(struct macb *bp)
1098 if (macb_is_gem(bp)) {
1099 if (GEM_BF(IRQCOR, gem_readl(bp, DCFG1)) == 0)
1100 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
1104 static void macb_init_hw(struct macb *bp)
1109 macb_set_hwaddr(bp);
1111 config = macb_mdc_clk_div(bp);
1112 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1113 config |= MACB_BIT(PAE); /* PAuse Enable */
1114 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1115 config |= MACB_BIT(BIG); /* Receive oversized frames */
1116 if (bp->dev->flags & IFF_PROMISC)
1117 config |= MACB_BIT(CAF); /* Copy All Frames */
1118 if (!(bp->dev->flags & IFF_BROADCAST))
1119 config |= MACB_BIT(NBC); /* No BroadCast */
1120 config |= macb_dbw(bp);
1121 macb_writel(bp, NCFGR, config);
1122 bp->speed = SPEED_10;
1123 bp->duplex = DUPLEX_HALF;
1125 macb_configure_dma(bp);
1126 macb_configure_caps(bp);
1128 /* Initialize TX and RX buffers */
1129 macb_writel(bp, RBQP, bp->rx_ring_dma);
1130 macb_writel(bp, TBQP, bp->tx_ring_dma);
1132 /* Enable TX and RX */
1133 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1135 /* Enable interrupts */
1136 macb_writel(bp, IER, (MACB_RX_INT_FLAGS
1138 | MACB_BIT(HRESP)));
1143 * The hash address register is 64 bits long and takes up two
1144 * locations in the memory map. The least significant bits are stored
1145 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1147 * The unicast hash enable and the multicast hash enable bits in the
1148 * network configuration register enable the reception of hash matched
1149 * frames. The destination address is reduced to a 6 bit index into
1150 * the 64 bit hash register using the following hash function. The
1151 * hash function is an exclusive or of every sixth bit of the
1152 * destination address.
1154 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1155 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1156 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1157 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1158 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1159 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1161 * da[0] represents the least significant bit of the first byte
1162 * received, that is, the multicast/unicast indicator, and da[47]
1163 * represents the most significant bit of the last byte received. If
1164 * the hash index, hi[n], points to a bit that is set in the hash
1165 * register then the frame will be matched according to whether the
1166 * frame is multicast or unicast. A multicast match will be signalled
1167 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1168 * index points to a bit set in the hash register. A unicast match
1169 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1170 * and the hash index points to a bit set in the hash register. To
1171 * receive all multicast frames, the hash register should be set with
1172 * all ones and the multicast hash enable bit should be set in the
1173 * network configuration register.
1176 static inline int hash_bit_value(int bitnr, __u8 *addr)
1178 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1184 * Return the hash index value for the specified address.
1186 static int hash_get_index(__u8 *addr)
1191 for (j = 0; j < 6; j++) {
1192 for (i = 0, bitval = 0; i < 8; i++)
1193 bitval ^= hash_bit_value(i*6 + j, addr);
1195 hash_index |= (bitval << j);
1202 * Add multicast addresses to the internal multicast-hash table.
1204 static void macb_sethashtable(struct net_device *dev)
1206 struct netdev_hw_addr *ha;
1207 unsigned long mc_filter[2];
1209 struct macb *bp = netdev_priv(dev);
1211 mc_filter[0] = mc_filter[1] = 0;
1213 netdev_for_each_mc_addr(ha, dev) {
1214 bitnr = hash_get_index(ha->addr);
1215 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1218 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1219 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1223 * Enable/Disable promiscuous and multicast modes.
1225 void macb_set_rx_mode(struct net_device *dev)
1228 struct macb *bp = netdev_priv(dev);
1230 cfg = macb_readl(bp, NCFGR);
1232 if (dev->flags & IFF_PROMISC)
1233 /* Enable promiscuous mode */
1234 cfg |= MACB_BIT(CAF);
1235 else if (dev->flags & (~IFF_PROMISC))
1236 /* Disable promiscuous mode */
1237 cfg &= ~MACB_BIT(CAF);
1239 if (dev->flags & IFF_ALLMULTI) {
1240 /* Enable all multicast mode */
1241 macb_or_gem_writel(bp, HRB, -1);
1242 macb_or_gem_writel(bp, HRT, -1);
1243 cfg |= MACB_BIT(NCFGR_MTI);
1244 } else if (!netdev_mc_empty(dev)) {
1245 /* Enable specific multicasts */
1246 macb_sethashtable(dev);
1247 cfg |= MACB_BIT(NCFGR_MTI);
1248 } else if (dev->flags & (~IFF_ALLMULTI)) {
1249 /* Disable all multicast mode */
1250 macb_or_gem_writel(bp, HRB, 0);
1251 macb_or_gem_writel(bp, HRT, 0);
1252 cfg &= ~MACB_BIT(NCFGR_MTI);
1255 macb_writel(bp, NCFGR, cfg);
1257 EXPORT_SYMBOL_GPL(macb_set_rx_mode);
1259 static int macb_open(struct net_device *dev)
1261 struct macb *bp = netdev_priv(dev);
1264 netdev_dbg(bp->dev, "open\n");
1266 /* carrier starts down */
1267 netif_carrier_off(dev);
1269 /* if the phy is not yet register, retry later*/
1273 /* RX buffers initialization */
1274 macb_init_rx_buffer_size(bp);
1276 err = macb_alloc_consistent(bp);
1278 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1283 napi_enable(&bp->napi);
1285 macb_init_rings(bp);
1288 /* schedule a link state check */
1289 phy_start(bp->phy_dev);
1291 netif_start_queue(dev);
1296 static int macb_close(struct net_device *dev)
1298 struct macb *bp = netdev_priv(dev);
1299 unsigned long flags;
1301 netif_stop_queue(dev);
1302 napi_disable(&bp->napi);
1305 phy_stop(bp->phy_dev);
1307 spin_lock_irqsave(&bp->lock, flags);
1309 netif_carrier_off(dev);
1310 spin_unlock_irqrestore(&bp->lock, flags);
1312 macb_free_consistent(bp);
1317 static void gem_update_stats(struct macb *bp)
1319 u32 __iomem *reg = bp->regs + GEM_OTX;
1320 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1321 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1323 for (; p < end; p++, reg++)
1324 *p += __raw_readl(reg);
1327 static struct net_device_stats *gem_get_stats(struct macb *bp)
1329 struct gem_stats *hwstat = &bp->hw_stats.gem;
1330 struct net_device_stats *nstat = &bp->stats;
1332 gem_update_stats(bp);
1334 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1335 hwstat->rx_alignment_errors +
1336 hwstat->rx_resource_errors +
1337 hwstat->rx_overruns +
1338 hwstat->rx_oversize_frames +
1339 hwstat->rx_jabbers +
1340 hwstat->rx_undersized_frames +
1341 hwstat->rx_length_field_frame_errors);
1342 nstat->tx_errors = (hwstat->tx_late_collisions +
1343 hwstat->tx_excessive_collisions +
1344 hwstat->tx_underrun +
1345 hwstat->tx_carrier_sense_errors);
1346 nstat->multicast = hwstat->rx_multicast_frames;
1347 nstat->collisions = (hwstat->tx_single_collision_frames +
1348 hwstat->tx_multiple_collision_frames +
1349 hwstat->tx_excessive_collisions);
1350 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1351 hwstat->rx_jabbers +
1352 hwstat->rx_undersized_frames +
1353 hwstat->rx_length_field_frame_errors);
1354 nstat->rx_over_errors = hwstat->rx_resource_errors;
1355 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1356 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1357 nstat->rx_fifo_errors = hwstat->rx_overruns;
1358 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1359 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1360 nstat->tx_fifo_errors = hwstat->tx_underrun;
1365 struct net_device_stats *macb_get_stats(struct net_device *dev)
1367 struct macb *bp = netdev_priv(dev);
1368 struct net_device_stats *nstat = &bp->stats;
1369 struct macb_stats *hwstat = &bp->hw_stats.macb;
1371 if (macb_is_gem(bp))
1372 return gem_get_stats(bp);
1374 /* read stats from hardware */
1375 macb_update_stats(bp);
1377 /* Convert HW stats into netdevice stats */
1378 nstat->rx_errors = (hwstat->rx_fcs_errors +
1379 hwstat->rx_align_errors +
1380 hwstat->rx_resource_errors +
1381 hwstat->rx_overruns +
1382 hwstat->rx_oversize_pkts +
1383 hwstat->rx_jabbers +
1384 hwstat->rx_undersize_pkts +
1385 hwstat->sqe_test_errors +
1386 hwstat->rx_length_mismatch);
1387 nstat->tx_errors = (hwstat->tx_late_cols +
1388 hwstat->tx_excessive_cols +
1389 hwstat->tx_underruns +
1390 hwstat->tx_carrier_errors);
1391 nstat->collisions = (hwstat->tx_single_cols +
1392 hwstat->tx_multiple_cols +
1393 hwstat->tx_excessive_cols);
1394 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1395 hwstat->rx_jabbers +
1396 hwstat->rx_undersize_pkts +
1397 hwstat->rx_length_mismatch);
1398 nstat->rx_over_errors = hwstat->rx_resource_errors +
1399 hwstat->rx_overruns;
1400 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1401 nstat->rx_frame_errors = hwstat->rx_align_errors;
1402 nstat->rx_fifo_errors = hwstat->rx_overruns;
1403 /* XXX: What does "missed" mean? */
1404 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1405 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1406 nstat->tx_fifo_errors = hwstat->tx_underruns;
1407 /* Don't know about heartbeat or window errors... */
1411 EXPORT_SYMBOL_GPL(macb_get_stats);
1413 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1415 struct macb *bp = netdev_priv(dev);
1416 struct phy_device *phydev = bp->phy_dev;
1421 return phy_ethtool_gset(phydev, cmd);
1424 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1426 struct macb *bp = netdev_priv(dev);
1427 struct phy_device *phydev = bp->phy_dev;
1432 return phy_ethtool_sset(phydev, cmd);
1435 static int macb_get_regs_len(struct net_device *netdev)
1437 return MACB_GREGS_NBR * sizeof(u32);
1440 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1443 struct macb *bp = netdev_priv(dev);
1444 unsigned int tail, head;
1447 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1448 | MACB_GREGS_VERSION;
1450 tail = macb_tx_ring_wrap(bp->tx_tail);
1451 head = macb_tx_ring_wrap(bp->tx_head);
1453 regs_buff[0] = macb_readl(bp, NCR);
1454 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1455 regs_buff[2] = macb_readl(bp, NSR);
1456 regs_buff[3] = macb_readl(bp, TSR);
1457 regs_buff[4] = macb_readl(bp, RBQP);
1458 regs_buff[5] = macb_readl(bp, TBQP);
1459 regs_buff[6] = macb_readl(bp, RSR);
1460 regs_buff[7] = macb_readl(bp, IMR);
1462 regs_buff[8] = tail;
1463 regs_buff[9] = head;
1464 regs_buff[10] = macb_tx_dma(bp, tail);
1465 regs_buff[11] = macb_tx_dma(bp, head);
1467 if (macb_is_gem(bp)) {
1468 regs_buff[12] = gem_readl(bp, USRIO);
1469 regs_buff[13] = gem_readl(bp, DMACFG);
1473 const struct ethtool_ops macb_ethtool_ops = {
1474 .get_settings = macb_get_settings,
1475 .set_settings = macb_set_settings,
1476 .get_regs_len = macb_get_regs_len,
1477 .get_regs = macb_get_regs,
1478 .get_link = ethtool_op_get_link,
1479 .get_ts_info = ethtool_op_get_ts_info,
1481 EXPORT_SYMBOL_GPL(macb_ethtool_ops);
1483 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1485 struct macb *bp = netdev_priv(dev);
1486 struct phy_device *phydev = bp->phy_dev;
1488 if (!netif_running(dev))
1494 return phy_mii_ioctl(phydev, rq, cmd);
1496 EXPORT_SYMBOL_GPL(macb_ioctl);
1498 static const struct net_device_ops macb_netdev_ops = {
1499 .ndo_open = macb_open,
1500 .ndo_stop = macb_close,
1501 .ndo_start_xmit = macb_start_xmit,
1502 .ndo_set_rx_mode = macb_set_rx_mode,
1503 .ndo_get_stats = macb_get_stats,
1504 .ndo_do_ioctl = macb_ioctl,
1505 .ndo_validate_addr = eth_validate_addr,
1506 .ndo_change_mtu = eth_change_mtu,
1507 .ndo_set_mac_address = eth_mac_addr,
1508 #ifdef CONFIG_NET_POLL_CONTROLLER
1509 .ndo_poll_controller = macb_poll_controller,
1513 #if defined(CONFIG_OF)
1514 static const struct of_device_id macb_dt_ids[] = {
1515 { .compatible = "cdns,at32ap7000-macb" },
1516 { .compatible = "cdns,at91sam9260-macb" },
1517 { .compatible = "cdns,macb" },
1518 { .compatible = "cdns,pc302-gem" },
1519 { .compatible = "cdns,gem" },
1522 MODULE_DEVICE_TABLE(of, macb_dt_ids);
1525 static int __init macb_probe(struct platform_device *pdev)
1527 struct macb_platform_data *pdata;
1528 struct resource *regs;
1529 struct net_device *dev;
1531 struct phy_device *phydev;
1534 struct pinctrl *pinctrl;
1537 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1539 dev_err(&pdev->dev, "no mmio resource defined\n");
1543 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1544 if (IS_ERR(pinctrl)) {
1545 err = PTR_ERR(pinctrl);
1546 if (err == -EPROBE_DEFER)
1549 dev_warn(&pdev->dev, "No pinctrl provided\n");
1553 dev = alloc_etherdev(sizeof(*bp));
1557 SET_NETDEV_DEV(dev, &pdev->dev);
1559 /* TODO: Actually, we have some interesting features... */
1562 bp = netdev_priv(dev);
1566 spin_lock_init(&bp->lock);
1567 INIT_WORK(&bp->tx_error_task, macb_tx_error_task);
1569 bp->pclk = clk_get(&pdev->dev, "pclk");
1570 if (IS_ERR(bp->pclk)) {
1571 dev_err(&pdev->dev, "failed to get macb_clk\n");
1572 goto err_out_free_dev;
1574 clk_prepare_enable(bp->pclk);
1576 bp->hclk = clk_get(&pdev->dev, "hclk");
1577 if (IS_ERR(bp->hclk)) {
1578 dev_err(&pdev->dev, "failed to get hclk\n");
1579 goto err_out_put_pclk;
1581 clk_prepare_enable(bp->hclk);
1583 bp->regs = ioremap(regs->start, resource_size(regs));
1585 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1587 goto err_out_disable_clocks;
1590 dev->irq = platform_get_irq(pdev, 0);
1591 err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev);
1593 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1595 goto err_out_iounmap;
1598 dev->netdev_ops = &macb_netdev_ops;
1599 netif_napi_add(dev, &bp->napi, macb_poll, 64);
1600 dev->ethtool_ops = &macb_ethtool_ops;
1602 dev->base_addr = regs->start;
1604 /* Set MII management clock divider */
1605 config = macb_mdc_clk_div(bp);
1606 config |= macb_dbw(bp);
1607 macb_writel(bp, NCFGR, config);
1609 mac = of_get_mac_address(pdev->dev.of_node);
1611 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1613 macb_get_hwaddr(bp);
1615 err = of_get_phy_mode(pdev->dev.of_node);
1617 pdata = pdev->dev.platform_data;
1618 if (pdata && pdata->is_rmii)
1619 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1621 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1623 bp->phy_interface = err;
1626 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
1627 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
1628 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
1629 #if defined(CONFIG_ARCH_AT91)
1630 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1633 macb_or_gem_writel(bp, USRIO, 0);
1636 #if defined(CONFIG_ARCH_AT91)
1637 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
1639 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
1642 err = register_netdev(dev);
1644 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1645 goto err_out_free_irq;
1648 err = macb_mii_init(bp);
1650 goto err_out_unregister_netdev;
1652 platform_set_drvdata(pdev, dev);
1654 netif_carrier_off(dev);
1656 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1657 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1658 dev->irq, dev->dev_addr);
1660 phydev = bp->phy_dev;
1661 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1662 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1666 err_out_unregister_netdev:
1667 unregister_netdev(dev);
1669 free_irq(dev->irq, dev);
1672 err_out_disable_clocks:
1673 clk_disable_unprepare(bp->hclk);
1675 clk_disable_unprepare(bp->pclk);
1684 static int __exit macb_remove(struct platform_device *pdev)
1686 struct net_device *dev;
1689 dev = platform_get_drvdata(pdev);
1692 bp = netdev_priv(dev);
1694 phy_disconnect(bp->phy_dev);
1695 mdiobus_unregister(bp->mii_bus);
1696 kfree(bp->mii_bus->irq);
1697 mdiobus_free(bp->mii_bus);
1698 unregister_netdev(dev);
1699 free_irq(dev->irq, dev);
1701 clk_disable_unprepare(bp->hclk);
1703 clk_disable_unprepare(bp->pclk);
1712 static int macb_suspend(struct platform_device *pdev, pm_message_t state)
1714 struct net_device *netdev = platform_get_drvdata(pdev);
1715 struct macb *bp = netdev_priv(netdev);
1717 netif_carrier_off(netdev);
1718 netif_device_detach(netdev);
1720 clk_disable_unprepare(bp->hclk);
1721 clk_disable_unprepare(bp->pclk);
1726 static int macb_resume(struct platform_device *pdev)
1728 struct net_device *netdev = platform_get_drvdata(pdev);
1729 struct macb *bp = netdev_priv(netdev);
1731 clk_prepare_enable(bp->pclk);
1732 clk_prepare_enable(bp->hclk);
1734 netif_device_attach(netdev);
1739 #define macb_suspend NULL
1740 #define macb_resume NULL
1743 static struct platform_driver macb_driver = {
1744 .remove = __exit_p(macb_remove),
1745 .suspend = macb_suspend,
1746 .resume = macb_resume,
1749 .owner = THIS_MODULE,
1750 .of_match_table = of_match_ptr(macb_dt_ids),
1754 module_platform_driver_probe(macb_driver, macb_probe);
1756 MODULE_LICENSE("GPL");
1757 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
1758 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1759 MODULE_ALIAS("platform:macb");