2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/macb.h>
27 #include <linux/platform_device.h>
28 #include <linux/phy.h>
30 #include <linux/of_device.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
36 #define MACB_RX_BUFFER_SIZE 128
37 #define RX_BUFFER_MULTIPLE 64 /* bytes */
38 #define RX_RING_SIZE 512 /* must be power of 2 */
39 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
41 #define TX_RING_SIZE 128 /* must be power of 2 */
42 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
44 /* level of occupied TX descriptors under which we wake up TX process */
45 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
47 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
49 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
52 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
54 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
55 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
57 #define GEM_MTU_MIN_SIZE 68
60 * Graceful stop timeouts in us. We should allow up to
61 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
63 #define MACB_HALT_TIMEOUT 1230
65 /* Ring buffer accessors */
66 static unsigned int macb_tx_ring_wrap(unsigned int index)
68 return index & (TX_RING_SIZE - 1);
71 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
74 return &queue->tx_ring[macb_tx_ring_wrap(index)];
77 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
80 return &queue->tx_skb[macb_tx_ring_wrap(index)];
83 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
87 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
89 return queue->tx_ring_dma + offset;
92 static unsigned int macb_rx_ring_wrap(unsigned int index)
94 return index & (RX_RING_SIZE - 1);
97 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
99 return &bp->rx_ring[macb_rx_ring_wrap(index)];
102 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
104 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
107 static void macb_set_hwaddr(struct macb *bp)
112 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
113 macb_or_gem_writel(bp, SA1B, bottom);
114 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
115 macb_or_gem_writel(bp, SA1T, top);
117 /* Clear unused address register sets */
118 macb_or_gem_writel(bp, SA2B, 0);
119 macb_or_gem_writel(bp, SA2T, 0);
120 macb_or_gem_writel(bp, SA3B, 0);
121 macb_or_gem_writel(bp, SA3T, 0);
122 macb_or_gem_writel(bp, SA4B, 0);
123 macb_or_gem_writel(bp, SA4T, 0);
126 static void macb_get_hwaddr(struct macb *bp)
128 struct macb_platform_data *pdata;
134 pdata = dev_get_platdata(&bp->pdev->dev);
136 /* Check all 4 address register for vaild address */
137 for (i = 0; i < 4; i++) {
138 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
139 top = macb_or_gem_readl(bp, SA1T + i * 8);
141 if (pdata && pdata->rev_eth_addr) {
142 addr[5] = bottom & 0xff;
143 addr[4] = (bottom >> 8) & 0xff;
144 addr[3] = (bottom >> 16) & 0xff;
145 addr[2] = (bottom >> 24) & 0xff;
146 addr[1] = top & 0xff;
147 addr[0] = (top & 0xff00) >> 8;
149 addr[0] = bottom & 0xff;
150 addr[1] = (bottom >> 8) & 0xff;
151 addr[2] = (bottom >> 16) & 0xff;
152 addr[3] = (bottom >> 24) & 0xff;
153 addr[4] = top & 0xff;
154 addr[5] = (top >> 8) & 0xff;
157 if (is_valid_ether_addr(addr)) {
158 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
163 netdev_info(bp->dev, "invalid hw address, using random\n");
164 eth_hw_addr_random(bp->dev);
167 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
169 struct macb *bp = bus->priv;
172 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
173 | MACB_BF(RW, MACB_MAN_READ)
174 | MACB_BF(PHYA, mii_id)
175 | MACB_BF(REGA, regnum)
176 | MACB_BF(CODE, MACB_MAN_CODE)));
178 /* wait for end of transfer */
179 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
182 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
187 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
190 struct macb *bp = bus->priv;
192 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
193 | MACB_BF(RW, MACB_MAN_WRITE)
194 | MACB_BF(PHYA, mii_id)
195 | MACB_BF(REGA, regnum)
196 | MACB_BF(CODE, MACB_MAN_CODE)
197 | MACB_BF(DATA, value)));
199 /* wait for end of transfer */
200 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
207 * macb_set_tx_clk() - Set a clock to a new frequency
208 * @clk Pointer to the clock to change
209 * @rate New frequency in Hz
210 * @dev Pointer to the struct net_device
212 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
214 long ferr, rate, rate_rounded;
233 rate_rounded = clk_round_rate(clk, rate);
234 if (rate_rounded < 0)
237 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
240 ferr = abs(rate_rounded - rate);
241 ferr = DIV_ROUND_UP(ferr, rate / 100000);
243 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
246 if (clk_set_rate(clk, rate_rounded))
247 netdev_err(dev, "adjusting tx_clk failed.\n");
250 static void macb_handle_link_change(struct net_device *dev)
252 struct macb *bp = netdev_priv(dev);
253 struct phy_device *phydev = bp->phy_dev;
256 int status_change = 0;
258 spin_lock_irqsave(&bp->lock, flags);
261 if ((bp->speed != phydev->speed) ||
262 (bp->duplex != phydev->duplex)) {
265 reg = macb_readl(bp, NCFGR);
266 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
268 reg &= ~GEM_BIT(GBE);
272 if (phydev->speed == SPEED_100)
273 reg |= MACB_BIT(SPD);
274 if (phydev->speed == SPEED_1000 &&
275 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
278 macb_or_gem_writel(bp, NCFGR, reg);
280 bp->speed = phydev->speed;
281 bp->duplex = phydev->duplex;
286 if (phydev->link != bp->link) {
291 bp->link = phydev->link;
296 spin_unlock_irqrestore(&bp->lock, flags);
300 /* Update the TX clock rate if and only if the link is
301 * up and there has been a link change.
303 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
305 netif_carrier_on(dev);
306 netdev_info(dev, "link up (%d/%s)\n",
308 phydev->duplex == DUPLEX_FULL ?
311 netif_carrier_off(dev);
312 netdev_info(dev, "link down\n");
317 /* based on au1000_eth. c*/
318 static int macb_mii_probe(struct net_device *dev)
320 struct macb *bp = netdev_priv(dev);
321 struct macb_platform_data *pdata;
322 struct phy_device *phydev;
326 phydev = phy_find_first(bp->mii_bus);
328 netdev_err(dev, "no PHY found\n");
332 pdata = dev_get_platdata(&bp->pdev->dev);
333 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
334 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
336 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
337 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
341 /* attach the mac to the phy */
342 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
345 netdev_err(dev, "Could not attach to PHY\n");
349 /* mask with MAC supported features */
350 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
351 phydev->supported &= PHY_GBIT_FEATURES;
353 phydev->supported &= PHY_BASIC_FEATURES;
355 if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
356 phydev->supported &= ~SUPPORTED_1000baseT_Half;
358 phydev->advertising = phydev->supported;
363 bp->phy_dev = phydev;
368 static int macb_mii_init(struct macb *bp)
370 struct macb_platform_data *pdata;
371 struct device_node *np;
374 /* Enable management port */
375 macb_writel(bp, NCR, MACB_BIT(MPE));
377 bp->mii_bus = mdiobus_alloc();
378 if (bp->mii_bus == NULL) {
383 bp->mii_bus->name = "MACB_mii_bus";
384 bp->mii_bus->read = &macb_mdio_read;
385 bp->mii_bus->write = &macb_mdio_write;
386 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
387 bp->pdev->name, bp->pdev->id);
388 bp->mii_bus->priv = bp;
389 bp->mii_bus->parent = &bp->dev->dev;
390 pdata = dev_get_platdata(&bp->pdev->dev);
392 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
393 if (!bp->mii_bus->irq) {
395 goto err_out_free_mdiobus;
398 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
400 np = bp->pdev->dev.of_node;
402 /* try dt phy registration */
403 err = of_mdiobus_register(bp->mii_bus, np);
405 /* fallback to standard phy registration if no phy were
406 found during dt phy registration */
407 if (!err && !phy_find_first(bp->mii_bus)) {
408 for (i = 0; i < PHY_MAX_ADDR; i++) {
409 struct phy_device *phydev;
411 phydev = mdiobus_scan(bp->mii_bus, i);
412 if (IS_ERR(phydev)) {
413 err = PTR_ERR(phydev);
419 goto err_out_unregister_bus;
422 for (i = 0; i < PHY_MAX_ADDR; i++)
423 bp->mii_bus->irq[i] = PHY_POLL;
426 bp->mii_bus->phy_mask = pdata->phy_mask;
428 err = mdiobus_register(bp->mii_bus);
432 goto err_out_free_mdio_irq;
434 err = macb_mii_probe(bp->dev);
436 goto err_out_unregister_bus;
440 err_out_unregister_bus:
441 mdiobus_unregister(bp->mii_bus);
442 err_out_free_mdio_irq:
443 kfree(bp->mii_bus->irq);
444 err_out_free_mdiobus:
445 mdiobus_free(bp->mii_bus);
450 static void macb_update_stats(struct macb *bp)
452 u32 __iomem *reg = bp->regs + MACB_PFR;
453 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
454 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
456 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
458 for(; p < end; p++, reg++)
459 *p += readl_relaxed(reg);
462 static int macb_halt_tx(struct macb *bp)
464 unsigned long halt_time, timeout;
467 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
469 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
472 status = macb_readl(bp, TSR);
473 if (!(status & MACB_BIT(TGO)))
476 usleep_range(10, 250);
477 } while (time_before(halt_time, timeout));
482 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
484 if (tx_skb->mapping) {
485 if (tx_skb->mapped_as_page)
486 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
487 tx_skb->size, DMA_TO_DEVICE);
489 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
490 tx_skb->size, DMA_TO_DEVICE);
495 dev_kfree_skb_any(tx_skb->skb);
500 static void macb_tx_error_task(struct work_struct *work)
502 struct macb_queue *queue = container_of(work, struct macb_queue,
504 struct macb *bp = queue->bp;
505 struct macb_tx_skb *tx_skb;
506 struct macb_dma_desc *desc;
511 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
512 (unsigned int)(queue - bp->queues),
513 queue->tx_tail, queue->tx_head);
515 /* Prevent the queue IRQ handlers from running: each of them may call
516 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
517 * As explained below, we have to halt the transmission before updating
518 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
519 * network engine about the macb/gem being halted.
521 spin_lock_irqsave(&bp->lock, flags);
523 /* Make sure nobody is trying to queue up new packets */
524 netif_tx_stop_all_queues(bp->dev);
527 * Stop transmission now
528 * (in case we have just queued new packets)
529 * macb/gem must be halted to write TBQP register
531 if (macb_halt_tx(bp))
532 /* Just complain for now, reinitializing TX path can be good */
533 netdev_err(bp->dev, "BUG: halt tx timed out\n");
536 * Treat frames in TX queue including the ones that caused the error.
537 * Free transmit buffers in upper layer.
539 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
542 desc = macb_tx_desc(queue, tail);
544 tx_skb = macb_tx_skb(queue, tail);
547 if (ctrl & MACB_BIT(TX_USED)) {
548 /* skb is set for the last buffer of the frame */
550 macb_tx_unmap(bp, tx_skb);
552 tx_skb = macb_tx_skb(queue, tail);
556 /* ctrl still refers to the first buffer descriptor
557 * since it's the only one written back by the hardware
559 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
560 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
561 macb_tx_ring_wrap(tail), skb->data);
562 bp->stats.tx_packets++;
563 bp->stats.tx_bytes += skb->len;
567 * "Buffers exhausted mid-frame" errors may only happen
568 * if the driver is buggy, so complain loudly about those.
569 * Statistics are updated by hardware.
571 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
573 "BUG: TX buffers exhausted mid-frame\n");
575 desc->ctrl = ctrl | MACB_BIT(TX_USED);
578 macb_tx_unmap(bp, tx_skb);
581 /* Set end of TX queue */
582 desc = macb_tx_desc(queue, 0);
584 desc->ctrl = MACB_BIT(TX_USED);
586 /* Make descriptor updates visible to hardware */
589 /* Reinitialize the TX desc queue */
590 queue_writel(queue, TBQP, queue->tx_ring_dma);
591 /* Make TX ring reflect state of hardware */
595 /* Housework before enabling TX IRQ */
596 macb_writel(bp, TSR, macb_readl(bp, TSR));
597 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
599 /* Now we are ready to start transmission again */
600 netif_tx_start_all_queues(bp->dev);
601 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
603 spin_unlock_irqrestore(&bp->lock, flags);
606 static void macb_tx_interrupt(struct macb_queue *queue)
611 struct macb *bp = queue->bp;
612 u16 queue_index = queue - bp->queues;
614 status = macb_readl(bp, TSR);
615 macb_writel(bp, TSR, status);
617 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
618 queue_writel(queue, ISR, MACB_BIT(TCOMP));
620 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
621 (unsigned long)status);
623 head = queue->tx_head;
624 for (tail = queue->tx_tail; tail != head; tail++) {
625 struct macb_tx_skb *tx_skb;
627 struct macb_dma_desc *desc;
630 desc = macb_tx_desc(queue, tail);
632 /* Make hw descriptor updates visible to CPU */
637 /* TX_USED bit is only set by hardware on the very first buffer
638 * descriptor of the transmitted frame.
640 if (!(ctrl & MACB_BIT(TX_USED)))
643 /* Process all buffers of the current transmitted frame */
645 tx_skb = macb_tx_skb(queue, tail);
648 /* First, update TX stats if needed */
650 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
651 macb_tx_ring_wrap(tail), skb->data);
652 bp->stats.tx_packets++;
653 bp->stats.tx_bytes += skb->len;
656 /* Now we can safely release resources */
657 macb_tx_unmap(bp, tx_skb);
659 /* skb is set only for the last buffer of the frame.
660 * WARNING: at this point skb has been freed by
668 queue->tx_tail = tail;
669 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
670 CIRC_CNT(queue->tx_head, queue->tx_tail,
671 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
672 netif_wake_subqueue(bp->dev, queue_index);
675 static void gem_rx_refill(struct macb *bp)
681 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
682 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
684 /* Make hw descriptor updates visible to CPU */
687 bp->rx_prepared_head++;
689 if (bp->rx_skbuff[entry] == NULL) {
690 /* allocate sk_buff for this free entry in ring */
691 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
692 if (unlikely(skb == NULL)) {
694 "Unable to allocate sk_buff\n");
698 /* now fill corresponding descriptor entry */
699 paddr = dma_map_single(&bp->pdev->dev, skb->data,
700 bp->rx_buffer_size, DMA_FROM_DEVICE);
701 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
706 bp->rx_skbuff[entry] = skb;
708 if (entry == RX_RING_SIZE - 1)
709 paddr |= MACB_BIT(RX_WRAP);
710 bp->rx_ring[entry].addr = paddr;
711 bp->rx_ring[entry].ctrl = 0;
713 /* properly align Ethernet header */
714 skb_reserve(skb, NET_IP_ALIGN);
716 bp->rx_ring[entry].addr &= ~MACB_BIT(RX_USED);
717 bp->rx_ring[entry].ctrl = 0;
721 /* Make descriptor updates visible to hardware */
724 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
725 bp->rx_prepared_head, bp->rx_tail);
728 /* Mark DMA descriptors from begin up to and not including end as unused */
729 static void discard_partial_frame(struct macb *bp, unsigned int begin,
734 for (frag = begin; frag != end; frag++) {
735 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
736 desc->addr &= ~MACB_BIT(RX_USED);
739 /* Make descriptor updates visible to hardware */
743 * When this happens, the hardware stats registers for
744 * whatever caused this is updated, so we don't have to record
749 static int gem_rx(struct macb *bp, int budget)
754 struct macb_dma_desc *desc;
757 while (count < budget) {
760 entry = macb_rx_ring_wrap(bp->rx_tail);
761 desc = &bp->rx_ring[entry];
763 /* Make hw descriptor updates visible to CPU */
769 if (!(addr & MACB_BIT(RX_USED)))
775 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
777 "not whole frame pointed by descriptor\n");
778 bp->stats.rx_dropped++;
781 skb = bp->rx_skbuff[entry];
782 if (unlikely(!skb)) {
784 "inconsistent Rx descriptor chain\n");
785 bp->stats.rx_dropped++;
788 /* now everything is ready for receiving packet */
789 bp->rx_skbuff[entry] = NULL;
790 len = ctrl & bp->rx_frm_len_mask;
792 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
795 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
796 dma_unmap_single(&bp->pdev->dev, addr,
797 bp->rx_buffer_size, DMA_FROM_DEVICE);
799 skb->protocol = eth_type_trans(skb, bp->dev);
800 skb_checksum_none_assert(skb);
801 if (bp->dev->features & NETIF_F_RXCSUM &&
802 !(bp->dev->flags & IFF_PROMISC) &&
803 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
804 skb->ip_summed = CHECKSUM_UNNECESSARY;
806 bp->stats.rx_packets++;
807 bp->stats.rx_bytes += skb->len;
809 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
810 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
811 skb->len, skb->csum);
812 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
813 skb_mac_header(skb), 16, true);
814 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
815 skb->data, 32, true);
818 netif_receive_skb(skb);
826 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
827 unsigned int last_frag)
833 struct macb_dma_desc *desc;
835 desc = macb_rx_desc(bp, last_frag);
836 len = desc->ctrl & bp->rx_frm_len_mask;
838 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
839 macb_rx_ring_wrap(first_frag),
840 macb_rx_ring_wrap(last_frag), len);
843 * The ethernet header starts NET_IP_ALIGN bytes into the
844 * first buffer. Since the header is 14 bytes, this makes the
845 * payload word-aligned.
847 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
848 * the two padding bytes into the skb so that we avoid hitting
849 * the slowpath in memcpy(), and pull them off afterwards.
851 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
853 bp->stats.rx_dropped++;
854 for (frag = first_frag; ; frag++) {
855 desc = macb_rx_desc(bp, frag);
856 desc->addr &= ~MACB_BIT(RX_USED);
857 if (frag == last_frag)
861 /* Make descriptor updates visible to hardware */
869 skb_checksum_none_assert(skb);
872 for (frag = first_frag; ; frag++) {
873 unsigned int frag_len = bp->rx_buffer_size;
875 if (offset + frag_len > len) {
876 BUG_ON(frag != last_frag);
877 frag_len = len - offset;
879 skb_copy_to_linear_data_offset(skb, offset,
880 macb_rx_buffer(bp, frag), frag_len);
881 offset += bp->rx_buffer_size;
882 desc = macb_rx_desc(bp, frag);
883 desc->addr &= ~MACB_BIT(RX_USED);
885 if (frag == last_frag)
889 /* Make descriptor updates visible to hardware */
892 __skb_pull(skb, NET_IP_ALIGN);
893 skb->protocol = eth_type_trans(skb, bp->dev);
895 bp->stats.rx_packets++;
896 bp->stats.rx_bytes += skb->len;
897 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
898 skb->len, skb->csum);
899 netif_receive_skb(skb);
904 static int macb_rx(struct macb *bp, int budget)
910 for (tail = bp->rx_tail; budget > 0; tail++) {
911 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
914 /* Make hw descriptor updates visible to CPU */
920 if (!(addr & MACB_BIT(RX_USED)))
923 if (ctrl & MACB_BIT(RX_SOF)) {
924 if (first_frag != -1)
925 discard_partial_frame(bp, first_frag, tail);
929 if (ctrl & MACB_BIT(RX_EOF)) {
931 BUG_ON(first_frag == -1);
933 dropped = macb_rx_frame(bp, first_frag, tail);
942 if (first_frag != -1)
943 bp->rx_tail = first_frag;
950 static int macb_poll(struct napi_struct *napi, int budget)
952 struct macb *bp = container_of(napi, struct macb, napi);
956 status = macb_readl(bp, RSR);
957 macb_writel(bp, RSR, status);
961 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
962 (unsigned long)status, budget);
964 work_done = bp->macbgem_ops.mog_rx(bp, budget);
965 if (work_done < budget) {
968 /* Packets received while interrupts were disabled */
969 status = macb_readl(bp, RSR);
971 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
972 macb_writel(bp, ISR, MACB_BIT(RCOMP));
973 napi_reschedule(napi);
975 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
979 /* TODO: Handle errors */
984 static irqreturn_t macb_interrupt(int irq, void *dev_id)
986 struct macb_queue *queue = dev_id;
987 struct macb *bp = queue->bp;
988 struct net_device *dev = bp->dev;
991 status = queue_readl(queue, ISR);
993 if (unlikely(!status))
996 spin_lock(&bp->lock);
999 /* close possible race with dev_close */
1000 if (unlikely(!netif_running(dev))) {
1001 queue_writel(queue, IDR, -1);
1005 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1006 (unsigned int)(queue - bp->queues),
1007 (unsigned long)status);
1009 if (status & MACB_RX_INT_FLAGS) {
1011 * There's no point taking any more interrupts
1012 * until we have processed the buffers. The
1013 * scheduling call may fail if the poll routine
1014 * is already scheduled, so disable interrupts
1017 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
1018 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1019 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1021 if (napi_schedule_prep(&bp->napi)) {
1022 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1023 __napi_schedule(&bp->napi);
1027 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1028 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1029 schedule_work(&queue->tx_error_task);
1031 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1032 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1037 if (status & MACB_BIT(TCOMP))
1038 macb_tx_interrupt(queue);
1041 * Link change detection isn't possible with RMII, so we'll
1042 * add that if/when we get our hands on a full-blown MII PHY.
1045 /* There is a hardware issue under heavy load where DMA can
1046 * stop, this causes endless "used buffer descriptor read"
1047 * interrupts but it can be cleared by re-enabling RX. See
1048 * the at91 manual, section 41.3.1 or the Zynq manual
1049 * section 16.7.4 for details.
1051 if (status & MACB_BIT(RXUBR)) {
1052 ctrl = macb_readl(bp, NCR);
1053 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1054 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1056 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1057 macb_writel(bp, ISR, MACB_BIT(RXUBR));
1060 if (status & MACB_BIT(ISR_ROVR)) {
1061 /* We missed at least one packet */
1062 if (macb_is_gem(bp))
1063 bp->hw_stats.gem.rx_overruns++;
1065 bp->hw_stats.macb.rx_overruns++;
1067 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1068 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1071 if (status & MACB_BIT(HRESP)) {
1073 * TODO: Reset the hardware, and maybe move the
1074 * netdev_err to a lower-priority context as well
1077 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1079 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1080 queue_writel(queue, ISR, MACB_BIT(HRESP));
1083 status = queue_readl(queue, ISR);
1086 spin_unlock(&bp->lock);
1091 #ifdef CONFIG_NET_POLL_CONTROLLER
1093 * Polling receive - used by netconsole and other diagnostic tools
1094 * to allow network i/o with interrupts disabled.
1096 static void macb_poll_controller(struct net_device *dev)
1098 struct macb *bp = netdev_priv(dev);
1099 struct macb_queue *queue;
1100 unsigned long flags;
1103 local_irq_save(flags);
1104 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1105 macb_interrupt(dev->irq, queue);
1106 local_irq_restore(flags);
1110 static inline unsigned int macb_count_tx_descriptors(struct macb *bp,
1113 return (len + bp->max_tx_length - 1) / bp->max_tx_length;
1116 static unsigned int macb_tx_map(struct macb *bp,
1117 struct macb_queue *queue,
1118 struct sk_buff *skb)
1121 unsigned int len, entry, i, tx_head = queue->tx_head;
1122 struct macb_tx_skb *tx_skb = NULL;
1123 struct macb_dma_desc *desc;
1124 unsigned int offset, size, count = 0;
1125 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1126 unsigned int eof = 1;
1129 /* First, map non-paged data */
1130 len = skb_headlen(skb);
1133 size = min(len, bp->max_tx_length);
1134 entry = macb_tx_ring_wrap(tx_head);
1135 tx_skb = &queue->tx_skb[entry];
1137 mapping = dma_map_single(&bp->pdev->dev,
1139 size, DMA_TO_DEVICE);
1140 if (dma_mapping_error(&bp->pdev->dev, mapping))
1143 /* Save info to properly release resources */
1145 tx_skb->mapping = mapping;
1146 tx_skb->size = size;
1147 tx_skb->mapped_as_page = false;
1155 /* Then, map paged data from fragments */
1156 for (f = 0; f < nr_frags; f++) {
1157 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1159 len = skb_frag_size(frag);
1162 size = min(len, bp->max_tx_length);
1163 entry = macb_tx_ring_wrap(tx_head);
1164 tx_skb = &queue->tx_skb[entry];
1166 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1167 offset, size, DMA_TO_DEVICE);
1168 if (dma_mapping_error(&bp->pdev->dev, mapping))
1171 /* Save info to properly release resources */
1173 tx_skb->mapping = mapping;
1174 tx_skb->size = size;
1175 tx_skb->mapped_as_page = true;
1184 /* Should never happen */
1185 if (unlikely(tx_skb == NULL)) {
1186 netdev_err(bp->dev, "BUG! empty skb!\n");
1190 /* This is the last buffer of the frame: save socket buffer */
1193 /* Update TX ring: update buffer descriptors in reverse order
1194 * to avoid race condition
1197 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1198 * to set the end of TX queue
1201 entry = macb_tx_ring_wrap(i);
1202 ctrl = MACB_BIT(TX_USED);
1203 desc = &queue->tx_ring[entry];
1208 entry = macb_tx_ring_wrap(i);
1209 tx_skb = &queue->tx_skb[entry];
1210 desc = &queue->tx_ring[entry];
1212 ctrl = (u32)tx_skb->size;
1214 ctrl |= MACB_BIT(TX_LAST);
1217 if (unlikely(entry == (TX_RING_SIZE - 1)))
1218 ctrl |= MACB_BIT(TX_WRAP);
1220 /* Set TX buffer descriptor */
1221 desc->addr = tx_skb->mapping;
1222 /* desc->addr must be visible to hardware before clearing
1223 * 'TX_USED' bit in desc->ctrl.
1227 } while (i != queue->tx_head);
1229 queue->tx_head = tx_head;
1234 netdev_err(bp->dev, "TX DMA map failed\n");
1236 for (i = queue->tx_head; i != tx_head; i++) {
1237 tx_skb = macb_tx_skb(queue, i);
1239 macb_tx_unmap(bp, tx_skb);
1245 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1247 u16 queue_index = skb_get_queue_mapping(skb);
1248 struct macb *bp = netdev_priv(dev);
1249 struct macb_queue *queue = &bp->queues[queue_index];
1250 unsigned long flags;
1251 unsigned int count, nr_frags, frag_size, f;
1253 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1254 netdev_vdbg(bp->dev,
1255 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1256 queue_index, skb->len, skb->head, skb->data,
1257 skb_tail_pointer(skb), skb_end_pointer(skb));
1258 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1259 skb->data, 16, true);
1262 /* Count how many TX buffer descriptors are needed to send this
1263 * socket buffer: skb fragments of jumbo frames may need to be
1264 * splitted into many buffer descriptors.
1266 count = macb_count_tx_descriptors(bp, skb_headlen(skb));
1267 nr_frags = skb_shinfo(skb)->nr_frags;
1268 for (f = 0; f < nr_frags; f++) {
1269 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1270 count += macb_count_tx_descriptors(bp, frag_size);
1273 spin_lock_irqsave(&bp->lock, flags);
1275 /* This is a hard error, log it. */
1276 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < count) {
1277 netif_stop_subqueue(dev, queue_index);
1278 spin_unlock_irqrestore(&bp->lock, flags);
1279 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1280 queue->tx_head, queue->tx_tail);
1281 return NETDEV_TX_BUSY;
1284 /* Map socket buffer for DMA transfer */
1285 if (!macb_tx_map(bp, queue, skb)) {
1286 dev_kfree_skb_any(skb);
1290 /* Make newly initialized descriptor visible to hardware */
1293 skb_tx_timestamp(skb);
1295 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1297 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < 1)
1298 netif_stop_subqueue(dev, queue_index);
1301 spin_unlock_irqrestore(&bp->lock, flags);
1303 return NETDEV_TX_OK;
1306 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1308 if (!macb_is_gem(bp)) {
1309 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1311 bp->rx_buffer_size = size;
1313 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1315 "RX buffer must be multiple of %d bytes, expanding\n",
1316 RX_BUFFER_MULTIPLE);
1317 bp->rx_buffer_size =
1318 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1322 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1323 bp->dev->mtu, bp->rx_buffer_size);
1326 static void gem_free_rx_buffers(struct macb *bp)
1328 struct sk_buff *skb;
1329 struct macb_dma_desc *desc;
1336 for (i = 0; i < RX_RING_SIZE; i++) {
1337 skb = bp->rx_skbuff[i];
1342 desc = &bp->rx_ring[i];
1343 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1344 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1346 dev_kfree_skb_any(skb);
1350 kfree(bp->rx_skbuff);
1351 bp->rx_skbuff = NULL;
1354 static void macb_free_rx_buffers(struct macb *bp)
1356 if (bp->rx_buffers) {
1357 dma_free_coherent(&bp->pdev->dev,
1358 RX_RING_SIZE * bp->rx_buffer_size,
1359 bp->rx_buffers, bp->rx_buffers_dma);
1360 bp->rx_buffers = NULL;
1364 static void macb_free_consistent(struct macb *bp)
1366 struct macb_queue *queue;
1369 bp->macbgem_ops.mog_free_rx_buffers(bp);
1371 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1372 bp->rx_ring, bp->rx_ring_dma);
1376 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1377 kfree(queue->tx_skb);
1378 queue->tx_skb = NULL;
1379 if (queue->tx_ring) {
1380 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1381 queue->tx_ring, queue->tx_ring_dma);
1382 queue->tx_ring = NULL;
1387 static int gem_alloc_rx_buffers(struct macb *bp)
1391 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1392 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1397 "Allocated %d RX struct sk_buff entries at %p\n",
1398 RX_RING_SIZE, bp->rx_skbuff);
1402 static int macb_alloc_rx_buffers(struct macb *bp)
1406 size = RX_RING_SIZE * bp->rx_buffer_size;
1407 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1408 &bp->rx_buffers_dma, GFP_KERNEL);
1409 if (!bp->rx_buffers)
1413 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1414 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1418 static int macb_alloc_consistent(struct macb *bp)
1420 struct macb_queue *queue;
1424 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1425 size = TX_RING_BYTES;
1426 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1427 &queue->tx_ring_dma,
1429 if (!queue->tx_ring)
1432 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1433 q, size, (unsigned long)queue->tx_ring_dma,
1436 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1437 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1442 size = RX_RING_BYTES;
1443 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1444 &bp->rx_ring_dma, GFP_KERNEL);
1448 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1449 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1451 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1457 macb_free_consistent(bp);
1461 static void gem_init_rings(struct macb *bp)
1463 struct macb_queue *queue;
1467 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1468 for (i = 0; i < TX_RING_SIZE; i++) {
1469 queue->tx_ring[i].addr = 0;
1470 queue->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1472 queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1478 bp->rx_prepared_head = 0;
1483 static void macb_init_rings(struct macb *bp)
1488 addr = bp->rx_buffers_dma;
1489 for (i = 0; i < RX_RING_SIZE; i++) {
1490 bp->rx_ring[i].addr = addr;
1491 bp->rx_ring[i].ctrl = 0;
1492 addr += bp->rx_buffer_size;
1494 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1496 for (i = 0; i < TX_RING_SIZE; i++) {
1497 bp->queues[0].tx_ring[i].addr = 0;
1498 bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED);
1500 bp->queues[0].tx_head = 0;
1501 bp->queues[0].tx_tail = 0;
1502 bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1507 static void macb_reset_hw(struct macb *bp)
1509 struct macb_queue *queue;
1513 * Disable RX and TX (XXX: Should we halt the transmission
1516 macb_writel(bp, NCR, 0);
1518 /* Clear the stats registers (XXX: Update stats first?) */
1519 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1521 /* Clear all status flags */
1522 macb_writel(bp, TSR, -1);
1523 macb_writel(bp, RSR, -1);
1525 /* Disable all interrupts */
1526 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1527 queue_writel(queue, IDR, -1);
1528 queue_readl(queue, ISR);
1532 static u32 gem_mdc_clk_div(struct macb *bp)
1535 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1537 if (pclk_hz <= 20000000)
1538 config = GEM_BF(CLK, GEM_CLK_DIV8);
1539 else if (pclk_hz <= 40000000)
1540 config = GEM_BF(CLK, GEM_CLK_DIV16);
1541 else if (pclk_hz <= 80000000)
1542 config = GEM_BF(CLK, GEM_CLK_DIV32);
1543 else if (pclk_hz <= 120000000)
1544 config = GEM_BF(CLK, GEM_CLK_DIV48);
1545 else if (pclk_hz <= 160000000)
1546 config = GEM_BF(CLK, GEM_CLK_DIV64);
1548 config = GEM_BF(CLK, GEM_CLK_DIV96);
1553 static u32 macb_mdc_clk_div(struct macb *bp)
1556 unsigned long pclk_hz;
1558 if (macb_is_gem(bp))
1559 return gem_mdc_clk_div(bp);
1561 pclk_hz = clk_get_rate(bp->pclk);
1562 if (pclk_hz <= 20000000)
1563 config = MACB_BF(CLK, MACB_CLK_DIV8);
1564 else if (pclk_hz <= 40000000)
1565 config = MACB_BF(CLK, MACB_CLK_DIV16);
1566 else if (pclk_hz <= 80000000)
1567 config = MACB_BF(CLK, MACB_CLK_DIV32);
1569 config = MACB_BF(CLK, MACB_CLK_DIV64);
1575 * Get the DMA bus width field of the network configuration register that we
1576 * should program. We find the width from decoding the design configuration
1577 * register to find the maximum supported data bus width.
1579 static u32 macb_dbw(struct macb *bp)
1581 if (!macb_is_gem(bp))
1584 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1586 return GEM_BF(DBW, GEM_DBW128);
1588 return GEM_BF(DBW, GEM_DBW64);
1591 return GEM_BF(DBW, GEM_DBW32);
1596 * Configure the receive DMA engine
1597 * - use the correct receive buffer size
1598 * - set best burst length for DMA operations
1599 * (if not supported by FIFO, it will fallback to default)
1600 * - set both rx/tx packet buffers to full memory size
1601 * These are configurable parameters for GEM.
1603 static void macb_configure_dma(struct macb *bp)
1608 if (macb_is_gem(bp)) {
1609 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1610 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1611 if (bp->dma_burst_length)
1612 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
1613 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1614 dmacfg &= ~GEM_BIT(ENDIA_PKT);
1616 /* Find the CPU endianness by using the loopback bit of net_ctrl
1617 * register. save it first. When the CPU is in big endian we
1618 * need to program swaped mode for management descriptor access.
1620 ncr = macb_readl(bp, NCR);
1621 __raw_writel(MACB_BIT(LLB), bp->regs + MACB_NCR);
1622 tmp = __raw_readl(bp->regs + MACB_NCR);
1624 if (tmp == MACB_BIT(LLB))
1625 dmacfg &= ~GEM_BIT(ENDIA_DESC);
1627 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
1629 /* Restore net_ctrl */
1630 macb_writel(bp, NCR, ncr);
1632 if (bp->dev->features & NETIF_F_HW_CSUM)
1633 dmacfg |= GEM_BIT(TXCOEN);
1635 dmacfg &= ~GEM_BIT(TXCOEN);
1636 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1638 gem_writel(bp, DMACFG, dmacfg);
1642 static void macb_init_hw(struct macb *bp)
1644 struct macb_queue *queue;
1650 macb_set_hwaddr(bp);
1652 config = macb_mdc_clk_div(bp);
1653 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1654 config |= MACB_BIT(PAE); /* PAuse Enable */
1655 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1656 if (bp->caps & MACB_CAPS_JUMBO)
1657 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
1659 config |= MACB_BIT(BIG); /* Receive oversized frames */
1660 if (bp->dev->flags & IFF_PROMISC)
1661 config |= MACB_BIT(CAF); /* Copy All Frames */
1662 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
1663 config |= GEM_BIT(RXCOEN);
1664 if (!(bp->dev->flags & IFF_BROADCAST))
1665 config |= MACB_BIT(NBC); /* No BroadCast */
1666 config |= macb_dbw(bp);
1667 macb_writel(bp, NCFGR, config);
1668 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
1669 gem_writel(bp, JML, bp->jumbo_max_len);
1670 bp->speed = SPEED_10;
1671 bp->duplex = DUPLEX_HALF;
1672 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
1673 if (bp->caps & MACB_CAPS_JUMBO)
1674 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
1676 macb_configure_dma(bp);
1678 /* Initialize TX and RX buffers */
1679 macb_writel(bp, RBQP, bp->rx_ring_dma);
1680 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1681 queue_writel(queue, TBQP, queue->tx_ring_dma);
1683 /* Enable interrupts */
1684 queue_writel(queue, IER,
1690 /* Enable TX and RX */
1691 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1695 * The hash address register is 64 bits long and takes up two
1696 * locations in the memory map. The least significant bits are stored
1697 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1699 * The unicast hash enable and the multicast hash enable bits in the
1700 * network configuration register enable the reception of hash matched
1701 * frames. The destination address is reduced to a 6 bit index into
1702 * the 64 bit hash register using the following hash function. The
1703 * hash function is an exclusive or of every sixth bit of the
1704 * destination address.
1706 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1707 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1708 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1709 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1710 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1711 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1713 * da[0] represents the least significant bit of the first byte
1714 * received, that is, the multicast/unicast indicator, and da[47]
1715 * represents the most significant bit of the last byte received. If
1716 * the hash index, hi[n], points to a bit that is set in the hash
1717 * register then the frame will be matched according to whether the
1718 * frame is multicast or unicast. A multicast match will be signalled
1719 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1720 * index points to a bit set in the hash register. A unicast match
1721 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1722 * and the hash index points to a bit set in the hash register. To
1723 * receive all multicast frames, the hash register should be set with
1724 * all ones and the multicast hash enable bit should be set in the
1725 * network configuration register.
1728 static inline int hash_bit_value(int bitnr, __u8 *addr)
1730 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1736 * Return the hash index value for the specified address.
1738 static int hash_get_index(__u8 *addr)
1743 for (j = 0; j < 6; j++) {
1744 for (i = 0, bitval = 0; i < 8; i++)
1745 bitval ^= hash_bit_value(i * 6 + j, addr);
1747 hash_index |= (bitval << j);
1754 * Add multicast addresses to the internal multicast-hash table.
1756 static void macb_sethashtable(struct net_device *dev)
1758 struct netdev_hw_addr *ha;
1759 unsigned long mc_filter[2];
1761 struct macb *bp = netdev_priv(dev);
1763 mc_filter[0] = mc_filter[1] = 0;
1765 netdev_for_each_mc_addr(ha, dev) {
1766 bitnr = hash_get_index(ha->addr);
1767 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1770 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1771 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1775 * Enable/Disable promiscuous and multicast modes.
1777 static void macb_set_rx_mode(struct net_device *dev)
1780 struct macb *bp = netdev_priv(dev);
1782 cfg = macb_readl(bp, NCFGR);
1784 if (dev->flags & IFF_PROMISC) {
1785 /* Enable promiscuous mode */
1786 cfg |= MACB_BIT(CAF);
1788 /* Disable RX checksum offload */
1789 if (macb_is_gem(bp))
1790 cfg &= ~GEM_BIT(RXCOEN);
1792 /* Disable promiscuous mode */
1793 cfg &= ~MACB_BIT(CAF);
1795 /* Enable RX checksum offload only if requested */
1796 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
1797 cfg |= GEM_BIT(RXCOEN);
1800 if (dev->flags & IFF_ALLMULTI) {
1801 /* Enable all multicast mode */
1802 macb_or_gem_writel(bp, HRB, -1);
1803 macb_or_gem_writel(bp, HRT, -1);
1804 cfg |= MACB_BIT(NCFGR_MTI);
1805 } else if (!netdev_mc_empty(dev)) {
1806 /* Enable specific multicasts */
1807 macb_sethashtable(dev);
1808 cfg |= MACB_BIT(NCFGR_MTI);
1809 } else if (dev->flags & (~IFF_ALLMULTI)) {
1810 /* Disable all multicast mode */
1811 macb_or_gem_writel(bp, HRB, 0);
1812 macb_or_gem_writel(bp, HRT, 0);
1813 cfg &= ~MACB_BIT(NCFGR_MTI);
1816 macb_writel(bp, NCFGR, cfg);
1819 static int macb_open(struct net_device *dev)
1821 struct macb *bp = netdev_priv(dev);
1822 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1825 netdev_dbg(bp->dev, "open\n");
1827 /* carrier starts down */
1828 netif_carrier_off(dev);
1830 /* if the phy is not yet register, retry later*/
1834 /* RX buffers initialization */
1835 macb_init_rx_buffer_size(bp, bufsz);
1837 err = macb_alloc_consistent(bp);
1839 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1844 napi_enable(&bp->napi);
1846 bp->macbgem_ops.mog_init_rings(bp);
1849 /* schedule a link state check */
1850 phy_start(bp->phy_dev);
1852 netif_tx_start_all_queues(dev);
1857 static int macb_close(struct net_device *dev)
1859 struct macb *bp = netdev_priv(dev);
1860 unsigned long flags;
1862 netif_tx_stop_all_queues(dev);
1863 napi_disable(&bp->napi);
1866 phy_stop(bp->phy_dev);
1868 spin_lock_irqsave(&bp->lock, flags);
1870 netif_carrier_off(dev);
1871 spin_unlock_irqrestore(&bp->lock, flags);
1873 macb_free_consistent(bp);
1878 static int macb_change_mtu(struct net_device *dev, int new_mtu)
1880 struct macb *bp = netdev_priv(dev);
1883 if (netif_running(dev))
1886 max_mtu = ETH_DATA_LEN;
1887 if (bp->caps & MACB_CAPS_JUMBO)
1888 max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
1890 if ((new_mtu > max_mtu) || (new_mtu < GEM_MTU_MIN_SIZE))
1898 static void gem_update_stats(struct macb *bp)
1901 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1903 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
1904 u32 offset = gem_statistics[i].offset;
1905 u64 val = readl_relaxed(bp->regs + offset);
1907 bp->ethtool_stats[i] += val;
1910 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
1911 /* Add GEM_OCTTXH, GEM_OCTRXH */
1912 val = readl_relaxed(bp->regs + offset + 4);
1913 bp->ethtool_stats[i] += ((u64)val) << 32;
1919 static struct net_device_stats *gem_get_stats(struct macb *bp)
1921 struct gem_stats *hwstat = &bp->hw_stats.gem;
1922 struct net_device_stats *nstat = &bp->stats;
1924 gem_update_stats(bp);
1926 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1927 hwstat->rx_alignment_errors +
1928 hwstat->rx_resource_errors +
1929 hwstat->rx_overruns +
1930 hwstat->rx_oversize_frames +
1931 hwstat->rx_jabbers +
1932 hwstat->rx_undersized_frames +
1933 hwstat->rx_length_field_frame_errors);
1934 nstat->tx_errors = (hwstat->tx_late_collisions +
1935 hwstat->tx_excessive_collisions +
1936 hwstat->tx_underrun +
1937 hwstat->tx_carrier_sense_errors);
1938 nstat->multicast = hwstat->rx_multicast_frames;
1939 nstat->collisions = (hwstat->tx_single_collision_frames +
1940 hwstat->tx_multiple_collision_frames +
1941 hwstat->tx_excessive_collisions);
1942 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1943 hwstat->rx_jabbers +
1944 hwstat->rx_undersized_frames +
1945 hwstat->rx_length_field_frame_errors);
1946 nstat->rx_over_errors = hwstat->rx_resource_errors;
1947 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1948 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1949 nstat->rx_fifo_errors = hwstat->rx_overruns;
1950 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1951 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1952 nstat->tx_fifo_errors = hwstat->tx_underrun;
1957 static void gem_get_ethtool_stats(struct net_device *dev,
1958 struct ethtool_stats *stats, u64 *data)
1962 bp = netdev_priv(dev);
1963 gem_update_stats(bp);
1964 memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
1967 static int gem_get_sset_count(struct net_device *dev, int sset)
1971 return GEM_STATS_LEN;
1977 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
1983 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
1984 memcpy(p, gem_statistics[i].stat_string,
1990 static struct net_device_stats *macb_get_stats(struct net_device *dev)
1992 struct macb *bp = netdev_priv(dev);
1993 struct net_device_stats *nstat = &bp->stats;
1994 struct macb_stats *hwstat = &bp->hw_stats.macb;
1996 if (macb_is_gem(bp))
1997 return gem_get_stats(bp);
1999 /* read stats from hardware */
2000 macb_update_stats(bp);
2002 /* Convert HW stats into netdevice stats */
2003 nstat->rx_errors = (hwstat->rx_fcs_errors +
2004 hwstat->rx_align_errors +
2005 hwstat->rx_resource_errors +
2006 hwstat->rx_overruns +
2007 hwstat->rx_oversize_pkts +
2008 hwstat->rx_jabbers +
2009 hwstat->rx_undersize_pkts +
2010 hwstat->rx_length_mismatch);
2011 nstat->tx_errors = (hwstat->tx_late_cols +
2012 hwstat->tx_excessive_cols +
2013 hwstat->tx_underruns +
2014 hwstat->tx_carrier_errors +
2015 hwstat->sqe_test_errors);
2016 nstat->collisions = (hwstat->tx_single_cols +
2017 hwstat->tx_multiple_cols +
2018 hwstat->tx_excessive_cols);
2019 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2020 hwstat->rx_jabbers +
2021 hwstat->rx_undersize_pkts +
2022 hwstat->rx_length_mismatch);
2023 nstat->rx_over_errors = hwstat->rx_resource_errors +
2024 hwstat->rx_overruns;
2025 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2026 nstat->rx_frame_errors = hwstat->rx_align_errors;
2027 nstat->rx_fifo_errors = hwstat->rx_overruns;
2028 /* XXX: What does "missed" mean? */
2029 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2030 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2031 nstat->tx_fifo_errors = hwstat->tx_underruns;
2032 /* Don't know about heartbeat or window errors... */
2037 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2039 struct macb *bp = netdev_priv(dev);
2040 struct phy_device *phydev = bp->phy_dev;
2045 return phy_ethtool_gset(phydev, cmd);
2048 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2050 struct macb *bp = netdev_priv(dev);
2051 struct phy_device *phydev = bp->phy_dev;
2056 return phy_ethtool_sset(phydev, cmd);
2059 static int macb_get_regs_len(struct net_device *netdev)
2061 return MACB_GREGS_NBR * sizeof(u32);
2064 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2067 struct macb *bp = netdev_priv(dev);
2068 unsigned int tail, head;
2071 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2072 | MACB_GREGS_VERSION;
2074 tail = macb_tx_ring_wrap(bp->queues[0].tx_tail);
2075 head = macb_tx_ring_wrap(bp->queues[0].tx_head);
2077 regs_buff[0] = macb_readl(bp, NCR);
2078 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2079 regs_buff[2] = macb_readl(bp, NSR);
2080 regs_buff[3] = macb_readl(bp, TSR);
2081 regs_buff[4] = macb_readl(bp, RBQP);
2082 regs_buff[5] = macb_readl(bp, TBQP);
2083 regs_buff[6] = macb_readl(bp, RSR);
2084 regs_buff[7] = macb_readl(bp, IMR);
2086 regs_buff[8] = tail;
2087 regs_buff[9] = head;
2088 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2089 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2091 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2092 if (macb_is_gem(bp)) {
2093 regs_buff[13] = gem_readl(bp, DMACFG);
2097 static const struct ethtool_ops macb_ethtool_ops = {
2098 .get_settings = macb_get_settings,
2099 .set_settings = macb_set_settings,
2100 .get_regs_len = macb_get_regs_len,
2101 .get_regs = macb_get_regs,
2102 .get_link = ethtool_op_get_link,
2103 .get_ts_info = ethtool_op_get_ts_info,
2106 static const struct ethtool_ops gem_ethtool_ops = {
2107 .get_settings = macb_get_settings,
2108 .set_settings = macb_set_settings,
2109 .get_regs_len = macb_get_regs_len,
2110 .get_regs = macb_get_regs,
2111 .get_link = ethtool_op_get_link,
2112 .get_ts_info = ethtool_op_get_ts_info,
2113 .get_ethtool_stats = gem_get_ethtool_stats,
2114 .get_strings = gem_get_ethtool_strings,
2115 .get_sset_count = gem_get_sset_count,
2118 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2120 struct macb *bp = netdev_priv(dev);
2121 struct phy_device *phydev = bp->phy_dev;
2123 if (!netif_running(dev))
2129 return phy_mii_ioctl(phydev, rq, cmd);
2132 static int macb_set_features(struct net_device *netdev,
2133 netdev_features_t features)
2135 struct macb *bp = netdev_priv(netdev);
2136 netdev_features_t changed = features ^ netdev->features;
2138 /* TX checksum offload */
2139 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
2142 dmacfg = gem_readl(bp, DMACFG);
2143 if (features & NETIF_F_HW_CSUM)
2144 dmacfg |= GEM_BIT(TXCOEN);
2146 dmacfg &= ~GEM_BIT(TXCOEN);
2147 gem_writel(bp, DMACFG, dmacfg);
2150 /* RX checksum offload */
2151 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
2154 netcfg = gem_readl(bp, NCFGR);
2155 if (features & NETIF_F_RXCSUM &&
2156 !(netdev->flags & IFF_PROMISC))
2157 netcfg |= GEM_BIT(RXCOEN);
2159 netcfg &= ~GEM_BIT(RXCOEN);
2160 gem_writel(bp, NCFGR, netcfg);
2166 static const struct net_device_ops macb_netdev_ops = {
2167 .ndo_open = macb_open,
2168 .ndo_stop = macb_close,
2169 .ndo_start_xmit = macb_start_xmit,
2170 .ndo_set_rx_mode = macb_set_rx_mode,
2171 .ndo_get_stats = macb_get_stats,
2172 .ndo_do_ioctl = macb_ioctl,
2173 .ndo_validate_addr = eth_validate_addr,
2174 .ndo_change_mtu = macb_change_mtu,
2175 .ndo_set_mac_address = eth_mac_addr,
2176 #ifdef CONFIG_NET_POLL_CONTROLLER
2177 .ndo_poll_controller = macb_poll_controller,
2179 .ndo_set_features = macb_set_features,
2183 * Configure peripheral capabilities according to device tree
2184 * and integration options used
2186 static void macb_configure_caps(struct macb *bp, const struct macb_config *dt_conf)
2191 bp->caps = dt_conf->caps;
2193 if (macb_is_gem_hw(bp->regs)) {
2194 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2196 dcfg = gem_readl(bp, DCFG1);
2197 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2198 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2199 dcfg = gem_readl(bp, DCFG2);
2200 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2201 bp->caps |= MACB_CAPS_FIFO_MODE;
2204 netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps);
2207 static void macb_probe_queues(void __iomem *mem,
2208 unsigned int *queue_mask,
2209 unsigned int *num_queues)
2216 /* is it macb or gem ?
2218 * We need to read directly from the hardware here because
2219 * we are early in the probe process and don't have the
2220 * MACB_CAPS_MACB_IS_GEM flag positioned
2222 if (!macb_is_gem_hw(mem))
2225 /* bit 0 is never set but queue 0 always exists */
2226 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
2230 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
2231 if (*queue_mask & (1 << hw_q))
2235 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
2236 struct clk **hclk, struct clk **tx_clk)
2240 *pclk = devm_clk_get(&pdev->dev, "pclk");
2241 if (IS_ERR(*pclk)) {
2242 err = PTR_ERR(*pclk);
2243 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
2247 *hclk = devm_clk_get(&pdev->dev, "hclk");
2248 if (IS_ERR(*hclk)) {
2249 err = PTR_ERR(*hclk);
2250 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
2254 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2255 if (IS_ERR(*tx_clk))
2258 err = clk_prepare_enable(*pclk);
2260 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2264 err = clk_prepare_enable(*hclk);
2266 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
2267 goto err_disable_pclk;
2270 err = clk_prepare_enable(*tx_clk);
2272 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
2273 goto err_disable_hclk;
2279 clk_disable_unprepare(*hclk);
2282 clk_disable_unprepare(*pclk);
2287 static int macb_init(struct platform_device *pdev)
2289 struct net_device *dev = platform_get_drvdata(pdev);
2290 unsigned int hw_q, q;
2291 struct macb *bp = netdev_priv(dev);
2292 struct macb_queue *queue;
2296 /* set the queue register mapping once for all: queue0 has a special
2297 * register mapping but we don't want to test the queue index then
2298 * compute the corresponding register offset at run time.
2300 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
2301 if (!(bp->queue_mask & (1 << hw_q)))
2304 queue = &bp->queues[q];
2307 queue->ISR = GEM_ISR(hw_q - 1);
2308 queue->IER = GEM_IER(hw_q - 1);
2309 queue->IDR = GEM_IDR(hw_q - 1);
2310 queue->IMR = GEM_IMR(hw_q - 1);
2311 queue->TBQP = GEM_TBQP(hw_q - 1);
2313 /* queue0 uses legacy registers */
2314 queue->ISR = MACB_ISR;
2315 queue->IER = MACB_IER;
2316 queue->IDR = MACB_IDR;
2317 queue->IMR = MACB_IMR;
2318 queue->TBQP = MACB_TBQP;
2321 /* get irq: here we use the linux queue index, not the hardware
2322 * queue index. the queue irq definitions in the device tree
2323 * must remove the optional gaps that could exist in the
2324 * hardware queue mask.
2326 queue->irq = platform_get_irq(pdev, q);
2327 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
2328 IRQF_SHARED, dev->name, queue);
2331 "Unable to request IRQ %d (error %d)\n",
2336 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
2340 dev->netdev_ops = &macb_netdev_ops;
2341 netif_napi_add(dev, &bp->napi, macb_poll, 64);
2343 /* setup appropriated routines according to adapter type */
2344 if (macb_is_gem(bp)) {
2345 bp->max_tx_length = GEM_MAX_TX_LEN;
2346 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2347 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2348 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2349 bp->macbgem_ops.mog_rx = gem_rx;
2350 dev->ethtool_ops = &gem_ethtool_ops;
2352 bp->max_tx_length = MACB_MAX_TX_LEN;
2353 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2354 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2355 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2356 bp->macbgem_ops.mog_rx = macb_rx;
2357 dev->ethtool_ops = &macb_ethtool_ops;
2361 dev->hw_features = NETIF_F_SG;
2362 /* Checksum offload is only available on gem with packet buffer */
2363 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
2364 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2365 if (bp->caps & MACB_CAPS_SG_DISABLED)
2366 dev->hw_features &= ~NETIF_F_SG;
2367 dev->features = dev->hw_features;
2370 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2371 val = GEM_BIT(RGMII);
2372 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
2373 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2374 val = MACB_BIT(RMII);
2375 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2376 val = MACB_BIT(MII);
2378 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
2379 val |= MACB_BIT(CLKEN);
2381 macb_or_gem_writel(bp, USRIO, val);
2383 /* Set MII management clock divider */
2384 val = macb_mdc_clk_div(bp);
2385 val |= macb_dbw(bp);
2386 macb_writel(bp, NCFGR, val);
2391 #if defined(CONFIG_OF)
2392 /* 1518 rounded up */
2393 #define AT91ETHER_MAX_RBUFF_SZ 0x600
2394 /* max number of receive buffers */
2395 #define AT91ETHER_MAX_RX_DESCR 9
2397 /* Initialize and start the Receiver and Transmit subsystems */
2398 static int at91ether_start(struct net_device *dev)
2400 struct macb *lp = netdev_priv(dev);
2405 lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
2406 (AT91ETHER_MAX_RX_DESCR *
2407 sizeof(struct macb_dma_desc)),
2408 &lp->rx_ring_dma, GFP_KERNEL);
2412 lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
2413 AT91ETHER_MAX_RX_DESCR *
2414 AT91ETHER_MAX_RBUFF_SZ,
2415 &lp->rx_buffers_dma, GFP_KERNEL);
2416 if (!lp->rx_buffers) {
2417 dma_free_coherent(&lp->pdev->dev,
2418 AT91ETHER_MAX_RX_DESCR *
2419 sizeof(struct macb_dma_desc),
2420 lp->rx_ring, lp->rx_ring_dma);
2425 addr = lp->rx_buffers_dma;
2426 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
2427 lp->rx_ring[i].addr = addr;
2428 lp->rx_ring[i].ctrl = 0;
2429 addr += AT91ETHER_MAX_RBUFF_SZ;
2432 /* Set the Wrap bit on the last descriptor */
2433 lp->rx_ring[AT91ETHER_MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP);
2435 /* Reset buffer index */
2438 /* Program address of descriptor list in Rx Buffer Queue register */
2439 macb_writel(lp, RBQP, lp->rx_ring_dma);
2441 /* Enable Receive and Transmit */
2442 ctl = macb_readl(lp, NCR);
2443 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
2448 /* Open the ethernet interface */
2449 static int at91ether_open(struct net_device *dev)
2451 struct macb *lp = netdev_priv(dev);
2455 /* Clear internal statistics */
2456 ctl = macb_readl(lp, NCR);
2457 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
2459 macb_set_hwaddr(lp);
2461 ret = at91ether_start(dev);
2465 /* Enable MAC interrupts */
2466 macb_writel(lp, IER, MACB_BIT(RCOMP) |
2468 MACB_BIT(ISR_TUND) |
2471 MACB_BIT(ISR_ROVR) |
2474 /* schedule a link state check */
2475 phy_start(lp->phy_dev);
2477 netif_start_queue(dev);
2482 /* Close the interface */
2483 static int at91ether_close(struct net_device *dev)
2485 struct macb *lp = netdev_priv(dev);
2488 /* Disable Receiver and Transmitter */
2489 ctl = macb_readl(lp, NCR);
2490 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
2492 /* Disable MAC interrupts */
2493 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
2495 MACB_BIT(ISR_TUND) |
2498 MACB_BIT(ISR_ROVR) |
2501 netif_stop_queue(dev);
2503 dma_free_coherent(&lp->pdev->dev,
2504 AT91ETHER_MAX_RX_DESCR *
2505 sizeof(struct macb_dma_desc),
2506 lp->rx_ring, lp->rx_ring_dma);
2509 dma_free_coherent(&lp->pdev->dev,
2510 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
2511 lp->rx_buffers, lp->rx_buffers_dma);
2512 lp->rx_buffers = NULL;
2517 /* Transmit packet */
2518 static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
2520 struct macb *lp = netdev_priv(dev);
2522 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
2523 netif_stop_queue(dev);
2525 /* Store packet information (to free when Tx completed) */
2527 lp->skb_length = skb->len;
2528 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
2531 /* Set address of the data in the Transmit Address register */
2532 macb_writel(lp, TAR, lp->skb_physaddr);
2533 /* Set length of the packet in the Transmit Control register */
2534 macb_writel(lp, TCR, skb->len);
2537 netdev_err(dev, "%s called, but device is busy!\n", __func__);
2538 return NETDEV_TX_BUSY;
2541 return NETDEV_TX_OK;
2544 /* Extract received frame from buffer descriptors and sent to upper layers.
2545 * (Called from interrupt context)
2547 static void at91ether_rx(struct net_device *dev)
2549 struct macb *lp = netdev_priv(dev);
2550 unsigned char *p_recv;
2551 struct sk_buff *skb;
2552 unsigned int pktlen;
2554 while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) {
2555 p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
2556 pktlen = MACB_BF(RX_FRMLEN, lp->rx_ring[lp->rx_tail].ctrl);
2557 skb = netdev_alloc_skb(dev, pktlen + 2);
2559 skb_reserve(skb, 2);
2560 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
2562 skb->protocol = eth_type_trans(skb, dev);
2563 lp->stats.rx_packets++;
2564 lp->stats.rx_bytes += pktlen;
2567 lp->stats.rx_dropped++;
2570 if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH))
2571 lp->stats.multicast++;
2573 /* reset ownership bit */
2574 lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED);
2576 /* wrap after last buffer */
2577 if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
2584 /* MAC interrupt handler */
2585 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
2587 struct net_device *dev = dev_id;
2588 struct macb *lp = netdev_priv(dev);
2591 /* MAC Interrupt Status register indicates what interrupts are pending.
2592 * It is automatically cleared once read.
2594 intstatus = macb_readl(lp, ISR);
2596 /* Receive complete */
2597 if (intstatus & MACB_BIT(RCOMP))
2600 /* Transmit complete */
2601 if (intstatus & MACB_BIT(TCOMP)) {
2602 /* The TCOM bit is set even if the transmission failed */
2603 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
2604 lp->stats.tx_errors++;
2607 dev_kfree_skb_irq(lp->skb);
2609 dma_unmap_single(NULL, lp->skb_physaddr,
2610 lp->skb_length, DMA_TO_DEVICE);
2611 lp->stats.tx_packets++;
2612 lp->stats.tx_bytes += lp->skb_length;
2614 netif_wake_queue(dev);
2617 /* Work-around for EMAC Errata section 41.3.1 */
2618 if (intstatus & MACB_BIT(RXUBR)) {
2619 ctl = macb_readl(lp, NCR);
2620 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
2621 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
2624 if (intstatus & MACB_BIT(ISR_ROVR))
2625 netdev_err(dev, "ROVR error\n");
2630 #ifdef CONFIG_NET_POLL_CONTROLLER
2631 static void at91ether_poll_controller(struct net_device *dev)
2633 unsigned long flags;
2635 local_irq_save(flags);
2636 at91ether_interrupt(dev->irq, dev);
2637 local_irq_restore(flags);
2641 static const struct net_device_ops at91ether_netdev_ops = {
2642 .ndo_open = at91ether_open,
2643 .ndo_stop = at91ether_close,
2644 .ndo_start_xmit = at91ether_start_xmit,
2645 .ndo_get_stats = macb_get_stats,
2646 .ndo_set_rx_mode = macb_set_rx_mode,
2647 .ndo_set_mac_address = eth_mac_addr,
2648 .ndo_do_ioctl = macb_ioctl,
2649 .ndo_validate_addr = eth_validate_addr,
2650 .ndo_change_mtu = eth_change_mtu,
2651 #ifdef CONFIG_NET_POLL_CONTROLLER
2652 .ndo_poll_controller = at91ether_poll_controller,
2656 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
2657 struct clk **hclk, struct clk **tx_clk)
2664 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
2666 return PTR_ERR(*pclk);
2668 err = clk_prepare_enable(*pclk);
2670 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2677 static int at91ether_init(struct platform_device *pdev)
2679 struct net_device *dev = platform_get_drvdata(pdev);
2680 struct macb *bp = netdev_priv(dev);
2684 dev->netdev_ops = &at91ether_netdev_ops;
2685 dev->ethtool_ops = &macb_ethtool_ops;
2687 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
2692 macb_writel(bp, NCR, 0);
2694 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
2695 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
2696 reg |= MACB_BIT(RM9200_RMII);
2698 macb_writel(bp, NCFGR, reg);
2703 static const struct macb_config at91sam9260_config = {
2704 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII,
2705 .clk_init = macb_clk_init,
2709 static const struct macb_config pc302gem_config = {
2710 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2711 .dma_burst_length = 16,
2712 .clk_init = macb_clk_init,
2716 static const struct macb_config sama5d2_config = {
2718 .dma_burst_length = 16,
2719 .clk_init = macb_clk_init,
2723 static const struct macb_config sama5d3_config = {
2724 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2725 .dma_burst_length = 16,
2726 .clk_init = macb_clk_init,
2730 static const struct macb_config sama5d4_config = {
2732 .dma_burst_length = 4,
2733 .clk_init = macb_clk_init,
2737 static const struct macb_config emac_config = {
2738 .clk_init = at91ether_clk_init,
2739 .init = at91ether_init,
2743 static const struct macb_config zynqmp_config = {
2744 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
2746 .dma_burst_length = 16,
2747 .clk_init = macb_clk_init,
2749 .jumbo_max_len = 10240,
2752 static const struct macb_config zynq_config = {
2753 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
2754 MACB_CAPS_NO_GIGABIT_HALF,
2755 .dma_burst_length = 16,
2756 .clk_init = macb_clk_init,
2760 static const struct of_device_id macb_dt_ids[] = {
2761 { .compatible = "cdns,at32ap7000-macb" },
2762 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
2763 { .compatible = "cdns,macb" },
2764 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
2765 { .compatible = "cdns,gem", .data = &pc302gem_config },
2766 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
2767 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
2768 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
2769 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
2770 { .compatible = "cdns,emac", .data = &emac_config },
2771 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
2772 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
2775 MODULE_DEVICE_TABLE(of, macb_dt_ids);
2776 #endif /* CONFIG_OF */
2778 static int macb_probe(struct platform_device *pdev)
2780 int (*clk_init)(struct platform_device *, struct clk **,
2781 struct clk **, struct clk **)
2783 int (*init)(struct platform_device *) = macb_init;
2784 struct device_node *np = pdev->dev.of_node;
2785 const struct macb_config *macb_config = NULL;
2786 struct clk *pclk, *hclk, *tx_clk;
2787 unsigned int queue_mask, num_queues;
2788 struct macb_platform_data *pdata;
2789 struct phy_device *phydev;
2790 struct net_device *dev;
2791 struct resource *regs;
2798 const struct of_device_id *match;
2800 match = of_match_node(macb_dt_ids, np);
2801 if (match && match->data) {
2802 macb_config = match->data;
2803 clk_init = macb_config->clk_init;
2804 init = macb_config->init;
2808 err = clk_init(pdev, &pclk, &hclk, &tx_clk);
2812 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2813 mem = devm_ioremap_resource(&pdev->dev, regs);
2816 goto err_disable_clocks;
2819 macb_probe_queues(mem, &queue_mask, &num_queues);
2820 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
2823 goto err_disable_clocks;
2826 dev->base_addr = regs->start;
2828 SET_NETDEV_DEV(dev, &pdev->dev);
2830 bp = netdev_priv(dev);
2834 bp->num_queues = num_queues;
2835 bp->queue_mask = queue_mask;
2837 bp->dma_burst_length = macb_config->dma_burst_length;
2840 bp->tx_clk = tx_clk;
2841 if (macb_config->jumbo_max_len) {
2842 bp->jumbo_max_len = macb_config->jumbo_max_len;
2845 spin_lock_init(&bp->lock);
2847 /* setup capabilities */
2848 macb_configure_caps(bp, macb_config);
2850 platform_set_drvdata(pdev, dev);
2852 dev->irq = platform_get_irq(pdev, 0);
2855 goto err_disable_clocks;
2858 mac = of_get_mac_address(np);
2860 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
2862 macb_get_hwaddr(bp);
2864 err = of_get_phy_mode(np);
2866 pdata = dev_get_platdata(&pdev->dev);
2867 if (pdata && pdata->is_rmii)
2868 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
2870 bp->phy_interface = PHY_INTERFACE_MODE_MII;
2872 bp->phy_interface = err;
2875 /* IP specific init */
2878 goto err_out_free_netdev;
2880 err = register_netdev(dev);
2882 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
2883 goto err_out_unregister_netdev;
2886 err = macb_mii_init(bp);
2888 goto err_out_unregister_netdev;
2890 netif_carrier_off(dev);
2892 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
2893 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
2894 dev->base_addr, dev->irq, dev->dev_addr);
2896 phydev = bp->phy_dev;
2897 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2898 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
2902 err_out_unregister_netdev:
2903 unregister_netdev(dev);
2905 err_out_free_netdev:
2909 clk_disable_unprepare(tx_clk);
2910 clk_disable_unprepare(hclk);
2911 clk_disable_unprepare(pclk);
2916 static int macb_remove(struct platform_device *pdev)
2918 struct net_device *dev;
2921 dev = platform_get_drvdata(pdev);
2924 bp = netdev_priv(dev);
2926 phy_disconnect(bp->phy_dev);
2927 mdiobus_unregister(bp->mii_bus);
2928 kfree(bp->mii_bus->irq);
2929 mdiobus_free(bp->mii_bus);
2930 unregister_netdev(dev);
2931 clk_disable_unprepare(bp->tx_clk);
2932 clk_disable_unprepare(bp->hclk);
2933 clk_disable_unprepare(bp->pclk);
2940 static int __maybe_unused macb_suspend(struct device *dev)
2942 struct platform_device *pdev = to_platform_device(dev);
2943 struct net_device *netdev = platform_get_drvdata(pdev);
2944 struct macb *bp = netdev_priv(netdev);
2946 netif_carrier_off(netdev);
2947 netif_device_detach(netdev);
2949 clk_disable_unprepare(bp->tx_clk);
2950 clk_disable_unprepare(bp->hclk);
2951 clk_disable_unprepare(bp->pclk);
2956 static int __maybe_unused macb_resume(struct device *dev)
2958 struct platform_device *pdev = to_platform_device(dev);
2959 struct net_device *netdev = platform_get_drvdata(pdev);
2960 struct macb *bp = netdev_priv(netdev);
2962 clk_prepare_enable(bp->pclk);
2963 clk_prepare_enable(bp->hclk);
2964 clk_prepare_enable(bp->tx_clk);
2966 netif_device_attach(netdev);
2971 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
2973 static struct platform_driver macb_driver = {
2974 .probe = macb_probe,
2975 .remove = macb_remove,
2978 .of_match_table = of_match_ptr(macb_dt_ids),
2983 module_platform_driver(macb_driver);
2985 MODULE_LICENSE("GPL");
2986 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
2987 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2988 MODULE_ALIAS("platform:macb");