drivers/net/ethernet/cadence/macb.h

   1 /*
   2  * Atmel MACB Ethernet Controller driver
   3  *
   4  * Copyright (C) 2004-2006 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef _MACB_H
  11 #define _MACB_H
  12
  13 #define MACB_GREGS_NBR 16
  14 #define MACB_GREGS_VERSION 1
  15 #define MACB_MAX_QUEUES 8
  16
  17 /* MACB register offsets */
  18 #define MACB_NCR                                0x0000 /* Network Control */
  19 #define MACB_NCFGR                              0x0004 /* Network Config */
  20 #define MACB_NSR                                0x0008 /* Network Status */
  21 #define MACB_TAR                                0x000c /* AT91RM9200 only */
  22 #define MACB_TCR                                0x0010 /* AT91RM9200 only */
  23 #define MACB_TSR                                0x0014 /* Transmit Status */
  24 #define MACB_RBQP                               0x0018 /* RX Q Base Address */
  25 #define MACB_TBQP                               0x001c /* TX Q Base Address */
  26 #define MACB_RSR                                0x0020 /* Receive Status */
  27 #define MACB_ISR                                0x0024 /* Interrupt Status */
  28 #define MACB_IER                                0x0028 /* Interrupt Enable */
  29 #define MACB_IDR                                0x002c /* Interrupt Disable */
  30 #define MACB_IMR                                0x0030 /* Interrupt Mask */
  31 #define MACB_MAN                                0x0034 /* PHY Maintenance */
  32 #define MACB_PTR                                0x0038
  33 #define MACB_PFR                                0x003c
  34 #define MACB_FTO                                0x0040
  35 #define MACB_SCF                                0x0044
  36 #define MACB_MCF                                0x0048
  37 #define MACB_FRO                                0x004c
  38 #define MACB_FCSE                               0x0050
  39 #define MACB_ALE                                0x0054
  40 #define MACB_DTF                                0x0058
  41 #define MACB_LCOL                               0x005c
  42 #define MACB_EXCOL                              0x0060
  43 #define MACB_TUND                               0x0064
  44 #define MACB_CSE                                0x0068
  45 #define MACB_RRE                                0x006c
  46 #define MACB_ROVR                               0x0070
  47 #define MACB_RSE                                0x0074
  48 #define MACB_ELE                                0x0078
  49 #define MACB_RJA                                0x007c
  50 #define MACB_USF                                0x0080
  51 #define MACB_STE                                0x0084
  52 #define MACB_RLE                                0x0088
  53 #define MACB_TPF                                0x008c
  54 #define MACB_HRB                                0x0090
  55 #define MACB_HRT                                0x0094
  56 #define MACB_SA1B                               0x0098
  57 #define MACB_SA1T                               0x009c
  58 #define MACB_SA2B                               0x00a0
  59 #define MACB_SA2T                               0x00a4
  60 #define MACB_SA3B                               0x00a8
  61 #define MACB_SA3T                               0x00ac
  62 #define MACB_SA4B                               0x00b0
  63 #define MACB_SA4T                               0x00b4
  64 #define MACB_TID                                0x00b8
  65 #define MACB_TPQ                                0x00bc
  66 #define MACB_USRIO                              0x00c0
  67 #define MACB_WOL                                0x00c4
  68 #define MACB_MID                                0x00fc
  69
  70 /* GEM register offsets. */
  71 #define GEM_NCFGR                               0x0004 /* Network Config */
  72 #define GEM_USRIO                               0x000c /* User IO */
  73 #define GEM_DMACFG                              0x0010 /* DMA Configuration */
  74 #define GEM_HRB                                 0x0080 /* Hash Bottom */
  75 #define GEM_HRT                                 0x0084 /* Hash Top */
  76 #define GEM_SA1B                                0x0088 /* Specific1 Bottom */
  77 #define GEM_SA1T                                0x008C /* Specific1 Top */
  78 #define GEM_SA2B                                0x0090 /* Specific2 Bottom */
  79 #define GEM_SA2T                                0x0094 /* Specific2 Top */
  80 #define GEM_SA3B                                0x0098 /* Specific3 Bottom */
  81 #define GEM_SA3T                                0x009C /* Specific3 Top */
  82 #define GEM_SA4B                                0x00A0 /* Specific4 Bottom */
  83 #define GEM_SA4T                                0x00A4 /* Specific4 Top */
  84 #define GEM_OTX                                 0x0100 /* Octets transmitted */
  85 #define GEM_OCTTXL                              0x0100 /* Octets transmitted
  86                                                         * [31:0]
  87                                                         */
  88 #define GEM_OCTTXH                              0x0104 /* Octets transmitted
  89                                                         * [47:32]
  90                                                         */
  91 #define GEM_TXCNT                               0x0108 /* Error-free Frames
  92                                                         * Transmitted counter
  93                                                         */
  94 #define GEM_TXBCCNT                             0x010c /* Error-free Broadcast
  95                                                         * Frames counter
  96                                                         */
  97 #define GEM_TXMCCNT                             0x0110 /* Error-free Multicast
  98                                                         * Frames counter
  99                                                         */
 100 #define GEM_TXPAUSECNT                          0x0114 /* Pause Frames
 101                                                         * Transmitted Counter
 102                                                         */
 103 #define GEM_TX64CNT                             0x0118 /* Error-free 64 byte
 104                                                         * Frames Transmitted
 105                                                         * counter
 106                                                         */
 107 #define GEM_TX65CNT                             0x011c /* Error-free 65-127 byte
 108                                                         * Frames Transmitted
 109                                                         * counter
 110                                                         */
 111 #define GEM_TX128CNT                            0x0120 /* Error-free 128-255
 112                                                         * byte Frames
 113                                                         * Transmitted counter
 114                                                         */
 115 #define GEM_TX256CNT                            0x0124 /* Error-free 256-511
 116                                                         * byte Frames
 117                                                         * transmitted counter
 118                                                         */
 119 #define GEM_TX512CNT                            0x0128 /* Error-free 512-1023
 120                                                         * byte Frames
 121                                                         * transmitted counter
 122                                                         */
 123 #define GEM_TX1024CNT                           0x012c /* Error-free 1024-1518
 124                                                         * byte Frames
 125                                                         * transmitted counter
 126                                                         */
 127 #define GEM_TX1519CNT                           0x0130 /* Error-free larger than
 128                                                         * 1519 byte Frames
 129                                                         * tranmitted counter
 130                                                         */
 131 #define GEM_TXURUNCNT                           0x0134 /* TX under run error
 132                                                         * counter
 133                                                         */
 134 #define GEM_SNGLCOLLCNT                         0x0138 /* Single Collision Frame
 135                                                         * Counter
 136                                                         */
 137 #define GEM_MULTICOLLCNT                        0x013c /* Multiple Collision
 138                                                         * Frame Counter
 139                                                         */
 140 #define GEM_EXCESSCOLLCNT                       0x0140 /* Excessive Collision
 141                                                         * Frame Counter
 142                                                         */
 143 #define GEM_LATECOLLCNT                         0x0144 /* Late Collision Frame
 144                                                         * Counter
 145                                                         */
 146 #define GEM_TXDEFERCNT                          0x0148 /* Deferred Transmission
 147                                                         * Frame Counter
 148                                                         */
 149 #define GEM_TXCSENSECNT                         0x014c /* Carrier Sense Error
 150                                                         * Counter
 151                                                         */
 152 #define GEM_ORX                                 0x0150 /* Octets received */
 153 #define GEM_OCTRXL                              0x0150 /* Octets received
 154                                                         * [31:0]
 155                                                         */
 156 #define GEM_OCTRXH                              0x0154 /* Octets received
 157                                                         * [47:32]
 158                                                         */
 159 #define GEM_RXCNT                               0x0158 /* Error-free Frames
 160                                                         * Received Counter
 161                                                         */
 162 #define GEM_RXBROADCNT                          0x015c /* Error-free Broadcast
 163                                                         * Frames Received
 164                                                         * Counter
 165                                                         */
 166 #define GEM_RXMULTICNT                          0x0160 /* Error-free Multicast
 167                                                         * Frames Received
 168                                                         * Counter
 169                                                         */
 170 #define GEM_RXPAUSECNT                          0x0164 /* Error-free Pause
 171                                                         * Frames Received
 172                                                         * Counter
 173                                                         */
 174 #define GEM_RX64CNT                             0x0168 /* Error-free 64 byte
 175                                                         * Frames Received
 176                                                         * Counter
 177                                                         */
 178 #define GEM_RX65CNT                             0x016c /* Error-free 65-127 byte
 179                                                         * Frames Received
 180                                                         * Counter
 181                                                         */
 182 #define GEM_RX128CNT                            0x0170 /* Error-free 128-255
 183                                                         * byte Frames Received
 184                                                         * Counter
 185                                                         */
 186 #define GEM_RX256CNT                            0x0174 /* Error-free 256-511
 187                                                         * byte Frames Received
 188                                                         * Counter
 189                                                         */
 190 #define GEM_RX512CNT                            0x0178 /* Error-free 512-1023
 191                                                         * byte Frames Received
 192                                                         * Counter
 193                                                         */
 194 #define GEM_RX1024CNT                           0x017c /* Error-free 1024-1518
 195                                                         * byte Frames Received
 196                                                         * Counter
 197                                                         */
 198 #define GEM_RX1519CNT                           0x0180 /* Error-free larger than
 199                                                         * 1519 Frames Received
 200                                                         * Counter
 201                                                         */
 202 #define GEM_RXUNDRCNT                           0x0184 /* Undersize Frames
 203                                                         * Received Counter
 204                                                         */
 205 #define GEM_RXOVRCNT                            0x0188 /* Oversize Frames
 206                                                         * Received Counter
 207                                                         */
 208 #define GEM_RXJABCNT                            0x018c /* Jabbers Received
 209                                                         * Counter
 210                                                         */
 211 #define GEM_RXFCSCNT                            0x0190 /* Frame Check Sequence
 212                                                         * Error Counter
 213                                                         */
 214 #define GEM_RXLENGTHCNT                         0x0194 /* Length Field Error
 215                                                         * Counter
 216                                                         */
 217 #define GEM_RXSYMBCNT                           0x0198 /* Symbol Error
 218                                                         * Counter
 219                                                         */
 220 #define GEM_RXALIGNCNT                          0x019c /* Alignment Error
 221                                                         * Counter
 222                                                         */
 223 #define GEM_RXRESERRCNT                         0x01a0 /* Receive Resource Error
 224                                                         * Counter
 225                                                         */
 226 #define GEM_RXORCNT                             0x01a4 /* Receive Overrun
 227                                                         * Counter
 228                                                         */
 229 #define GEM_RXIPCCNT                            0x01a8 /* IP header Checksum
 230                                                         * Error Counter
 231                                                         */
 232 #define GEM_RXTCPCCNT                           0x01ac /* TCP Checksum Error
 233                                                         * Counter
 234                                                         */
 235 #define GEM_RXUDPCCNT                           0x01b0 /* UDP Checksum Error
 236                                                         * Counter
 237                                                         */
 238 #define GEM_DCFG1                               0x0280 /* Design Config 1 */
 239 #define GEM_DCFG2                               0x0284 /* Design Config 2 */
 240 #define GEM_DCFG3                               0x0288 /* Design Config 3 */
 241 #define GEM_DCFG4                               0x028c /* Design Config 4 */
 242 #define GEM_DCFG5                               0x0290 /* Design Config 5 */
 243 #define GEM_DCFG6                               0x0294 /* Design Config 6 */
 244 #define GEM_DCFG7                               0x0298 /* Design Config 7 */
 245
 246 #define GEM_ISR(hw_q)                           (0x0400 + ((hw_q) << 2))
 247 #define GEM_TBQP(hw_q)                          (0x0440 + ((hw_q) << 2))
 248 #define GEM_RBQP(hw_q)                          (0x0480 + ((hw_q) << 2))
 249 #define GEM_IER(hw_q)                           (0x0600 + ((hw_q) << 2))
 250 #define GEM_IDR(hw_q)                           (0x0620 + ((hw_q) << 2))
 251 #define GEM_IMR(hw_q)                           (0x0640 + ((hw_q) << 2))
 252
 253 /* Bitfields in NCR */
 254 #define MACB_LB_OFFSET                          0 /* reserved */
 255 #define MACB_LB_SIZE                            1
 256 #define MACB_LLB_OFFSET                         1 /* Loop back local */
 257 #define MACB_LLB_SIZE                           1
 258 #define MACB_RE_OFFSET                          2 /* Receive enable */
 259 #define MACB_RE_SIZE                            1
 260 #define MACB_TE_OFFSET                          3 /* Transmit enable */
 261 #define MACB_TE_SIZE                            1
 262 #define MACB_MPE_OFFSET                         4 /* Management port enable */
 263 #define MACB_MPE_SIZE                           1
 264 #define MACB_CLRSTAT_OFFSET                     5 /* Clear stats regs */
 265 #define MACB_CLRSTAT_SIZE                       1
 266 #define MACB_INCSTAT_OFFSET                     6 /* Incremental stats regs */
 267 #define MACB_INCSTAT_SIZE                       1
 268 #define MACB_WESTAT_OFFSET                      7 /* Write enable stats regs */
 269 #define MACB_WESTAT_SIZE                        1
 270 #define MACB_BP_OFFSET                          8 /* Back pressure */
 271 #define MACB_BP_SIZE                            1
 272 #define MACB_TSTART_OFFSET                      9 /* Start transmission */
 273 #define MACB_TSTART_SIZE                        1
 274 #define MACB_THALT_OFFSET                       10 /* Transmit halt */
 275 #define MACB_THALT_SIZE                         1
 276 #define MACB_NCR_TPF_OFFSET                     11 /* Transmit pause frame */
 277 #define MACB_NCR_TPF_SIZE                       1
 278 #define MACB_TZQ_OFFSET                         12 /* Transmit zero quantum
 279                                                     * pause frame
 280                                                     */
 281 #define MACB_TZQ_SIZE                           1
 282
 283 /* Bitfields in NCFGR */
 284 #define MACB_SPD_OFFSET                         0 /* Speed */
 285 #define MACB_SPD_SIZE                           1
 286 #define MACB_FD_OFFSET                          1 /* Full duplex */
 287 #define MACB_FD_SIZE                            1
 288 #define MACB_BIT_RATE_OFFSET                    2 /* Discard non-VLAN frames */
 289 #define MACB_BIT_RATE_SIZE                      1
 290 #define MACB_JFRAME_OFFSET                      3 /* reserved */
 291 #define MACB_JFRAME_SIZE                        1
 292 #define MACB_CAF_OFFSET                         4 /* Copy all frames */
 293 #define MACB_CAF_SIZE                           1
 294 #define MACB_NBC_OFFSET                         5 /* No broadcast */
 295 #define MACB_NBC_SIZE                           1
 296 #define MACB_NCFGR_MTI_OFFSET                   6 /* Multicast hash enable */
 297 #define MACB_NCFGR_MTI_SIZE                     1
 298 #define MACB_UNI_OFFSET                         7 /* Unicast hash enable */
 299 #define MACB_UNI_SIZE                           1
 300 #define MACB_BIG_OFFSET                         8 /* Receive 1536 byte frames */
 301 #define MACB_BIG_SIZE                           1
 302 #define MACB_EAE_OFFSET                         9 /* External address match
 303                                                    * enable
 304                                                    */
 305 #define MACB_EAE_SIZE                           1
 306 #define MACB_CLK_OFFSET                         10
 307 #define MACB_CLK_SIZE                           2
 308 #define MACB_RTY_OFFSET                         12 /* Retry test */
 309 #define MACB_RTY_SIZE                           1
 310 #define MACB_PAE_OFFSET                         13 /* Pause enable */
 311 #define MACB_PAE_SIZE                           1
 312 #define MACB_RM9200_RMII_OFFSET                 13 /* AT91RM9200 only */
 313 #define MACB_RM9200_RMII_SIZE                   1  /* AT91RM9200 only */
 314 #define MACB_RBOF_OFFSET                        14 /* Receive buffer offset */
 315 #define MACB_RBOF_SIZE                          2
 316 #define MACB_RLCE_OFFSET                        16 /* Length field error frame
 317                                                     * discard
 318                                                     */
 319 #define MACB_RLCE_SIZE                          1
 320 #define MACB_DRFCS_OFFSET                       17 /* FCS remove */
 321 #define MACB_DRFCS_SIZE                         1
 322 #define MACB_EFRHD_OFFSET                       18
 323 #define MACB_EFRHD_SIZE                         1
 324 #define MACB_IRXFCS_OFFSET                      19
 325 #define MACB_IRXFCS_SIZE                        1
 326
 327 /* GEM specific NCFGR bitfields. */
 328 #define GEM_GBE_OFFSET                          10 /* Gigabit mode enable */
 329 #define GEM_GBE_SIZE                            1
 330 #define GEM_CLK_OFFSET                          18 /* MDC clock division */
 331 #define GEM_CLK_SIZE                            3
 332 #define GEM_DBW_OFFSET                          21 /* Data bus width */
 333 #define GEM_DBW_SIZE                            2
 334 #define GEM_RXCOEN_OFFSET                       24
 335 #define GEM_RXCOEN_SIZE                         1
 336
 337 /* Constants for data bus width. */
 338 #define GEM_DBW32                               0 /* 32 bit AMBA AHB data bus
 339                                                    * width
 340                                                    */
 341 #define GEM_DBW64                               1 /* 64 bit AMBA AHB data bus
 342                                                    * width
 343                                                    */
 344 #define GEM_DBW128                              2 /* 128 bit AMBA AHB data bus
 345                                                    * width
 346                                                    */
 347
 348 /* Bitfields in DMACFG. */
 349 #define GEM_FBLDO_OFFSET                        0 /* AHB fixed burst length for
 350                                                    * DMA data operations
 351                                                    */
 352 #define GEM_FBLDO_SIZE                          5
 353 #define GEM_ENDIA_OFFSET                        7 /* AHB endian swap mode enable
 354                                                    * for packet data accesses
 355                                                    */
 356 #define GEM_ENDIA_SIZE                          1
 357 #define GEM_RXBMS_OFFSET                        8 /* Receiver packet buffer
 358                                                    * memory size select
 359                                                    */
 360 #define GEM_RXBMS_SIZE                          2
 361 #define GEM_TXPBMS_OFFSET                       10 /* Transmitter packet buffer
 362                                                     * memory size select
 363                                                     */
 364 #define GEM_TXPBMS_SIZE                         1
 365 #define GEM_TXCOEN_OFFSET                       11 /* Transmitter IP, TCP and
 366                                                     * UDP checksum generation
 367                                                     * offload enable
 368                                                     */
 369 #define GEM_TXCOEN_SIZE                         1
 370 #define GEM_RXBS_OFFSET                         16 /* DMA receive buffer size in
 371                                                     * AHB system memory
 372                                                     */
 373 #define GEM_RXBS_SIZE                           8
 374 #define GEM_DDRP_OFFSET                         24 /* disc_when_no_ahb */
 375 #define GEM_DDRP_SIZE                           1
 376
 377
 378 /* Bitfields in NSR */
 379 #define MACB_NSR_LINK_OFFSET                    0 /* pcs_link_state */
 380 #define MACB_NSR_LINK_SIZE                      1
 381 #define MACB_MDIO_OFFSET                        1 /* status of the mdio_in
 382                                                    * pin
 383                                                    */
 384 #define MACB_MDIO_SIZE                          1
 385 #define MACB_IDLE_OFFSET                        2 /* The PHY management logic is
 386                                                    * idle (i.e. has completed)
 387                                                    */
 388 #define MACB_IDLE_SIZE                          1
 389
 390 /* Bitfields in TSR */
 391 #define MACB_UBR_OFFSET                         0 /* Used bit read */
 392 #define MACB_UBR_SIZE                           1
 393 #define MACB_COL_OFFSET                         1 /* Collision occurred */
 394 #define MACB_COL_SIZE                           1
 395 #define MACB_TSR_RLE_OFFSET                     2 /* Retry limit exceeded */
 396 #define MACB_TSR_RLE_SIZE                       1
 397 #define MACB_TGO_OFFSET                         3 /* Transmit go */
 398 #define MACB_TGO_SIZE                           1
 399 #define MACB_BEX_OFFSET                         4 /* Transmit frame corruption
 400                                                    * due to AHB error
 401                                                    */
 402 #define MACB_BEX_SIZE                           1
 403 #define MACB_RM9200_BNQ_OFFSET                  4 /* AT91RM9200 only */
 404 #define MACB_RM9200_BNQ_SIZE                    1 /* AT91RM9200 only */
 405 #define MACB_COMP_OFFSET                        5 /* Trnasmit complete */
 406 #define MACB_COMP_SIZE                          1
 407 #define MACB_UND_OFFSET                         6 /* Trnasmit under run */
 408 #define MACB_UND_SIZE                           1
 409
 410 /* Bitfields in RSR */
 411 #define MACB_BNA_OFFSET                         0 /* Buffer not available */
 412 #define MACB_BNA_SIZE                           1
 413 #define MACB_REC_OFFSET                         1 /* Frame received */
 414 #define MACB_REC_SIZE                           1
 415 #define MACB_OVR_OFFSET                         2 /* Receive overrun */
 416 #define MACB_OVR_SIZE                           1
 417
 418 /* Bitfields in ISR/IER/IDR/IMR */
 419 #define MACB_MFD_OFFSET                         0 /* Management frame sent */
 420 #define MACB_MFD_SIZE                           1
 421 #define MACB_RCOMP_OFFSET                       1 /* Receive complete */
 422 #define MACB_RCOMP_SIZE                         1
 423 #define MACB_RXUBR_OFFSET                       2 /* RX used bit read */
 424 #define MACB_RXUBR_SIZE                         1
 425 #define MACB_TXUBR_OFFSET                       3 /* TX used bit read */
 426 #define MACB_TXUBR_SIZE                         1
 427 #define MACB_ISR_TUND_OFFSET                    4 /* Enable trnasmit buffer
 428                                                    * under run interrupt
 429                                                    */
 430 #define MACB_ISR_TUND_SIZE                      1
 431 #define MACB_ISR_RLE_OFFSET                     5 /* Enable retry limit exceeded
 432                                                    * or late collision interrupt
 433                                                    */
 434 #define MACB_ISR_RLE_SIZE                       1
 435 #define MACB_TXERR_OFFSET                       6 /* Enable transmit frame
 436                                                    * corruption due to AHB error
 437                                                    * interrupt
 438                                                    */
 439 #define MACB_TXERR_SIZE                         1
 440 #define MACB_TCOMP_OFFSET                       7 /* Enable transmit complete
 441                                                    * interrupt
 442                                                    */
 443 #define MACB_TCOMP_SIZE                         1
 444 #define MACB_ISR_LINK_OFFSET                    9 /* Enable link change
 445                                                    * interrupt
 446                                                    */
 447 #define MACB_ISR_LINK_SIZE                      1
 448 #define MACB_ISR_ROVR_OFFSET                    10 /* Enable receive overrun
 449                                                     * interrupt
 450                                                     */
 451 #define MACB_ISR_ROVR_SIZE                      1
 452 #define MACB_HRESP_OFFSET                       11 /* Enable hrsep not OK
 453                                                     * interrupt
 454                                                     */
 455 #define MACB_HRESP_SIZE                         1
 456 #define MACB_PFR_OFFSET                         12 /* Enable pause frame with
 457                                                     * non-zero pause quantum
 458                                                     * interrupt
 459                                                     */
 460 #define MACB_PFR_SIZE                           1
 461 #define MACB_PTZ_OFFSET                         13 /* Enable pause time zero
 462                                                     * interrupt
 463                                                     */
 464 #define MACB_PTZ_SIZE                           1
 465
 466 /* Bitfields in MAN */
 467 #define MACB_DATA_OFFSET                        0 /* data */
 468 #define MACB_DATA_SIZE                          16
 469 #define MACB_CODE_OFFSET                        16 /* Must be written to 10 */
 470 #define MACB_CODE_SIZE                          2
 471 #define MACB_REGA_OFFSET                        18 /* Register address */
 472 #define MACB_REGA_SIZE                          5
 473 #define MACB_PHYA_OFFSET                        23 /* PHY address */
 474 #define MACB_PHYA_SIZE                          5
 475 #define MACB_RW_OFFSET                          28 /* Operation. 10 is read. 01
 476                                                     * is write.
 477                                                     */
 478 #define MACB_RW_SIZE                            2
 479 #define MACB_SOF_OFFSET                         30 /* Must be written to 1 for
 480                                                     * Clause 22 operation
 481                                                     */
 482 #define MACB_SOF_SIZE                           2
 483
 484 /* Bitfields in USRIO (AVR32) */
 485 #define MACB_MII_OFFSET                         0
 486 #define MACB_MII_SIZE                           1
 487 #define MACB_EAM_OFFSET                         1
 488 #define MACB_EAM_SIZE                           1
 489 #define MACB_TX_PAUSE_OFFSET                    2
 490 #define MACB_TX_PAUSE_SIZE                      1
 491 #define MACB_TX_PAUSE_ZERO_OFFSET               3
 492 #define MACB_TX_PAUSE_ZERO_SIZE                 1
 493
 494 /* Bitfields in USRIO (AT91) */
 495 #define MACB_RMII_OFFSET                        0
 496 #define MACB_RMII_SIZE                          1
 497 #define GEM_RGMII_OFFSET                        0 /* GEM gigabit mode */
 498 #define GEM_RGMII_SIZE                          1
 499 #define MACB_CLKEN_OFFSET                       1
 500 #define MACB_CLKEN_SIZE                         1
 501
 502 /* Bitfields in WOL */
 503 #define MACB_IP_OFFSET                          0
 504 #define MACB_IP_SIZE                            16
 505 #define MACB_MAG_OFFSET                         16
 506 #define MACB_MAG_SIZE                           1
 507 #define MACB_ARP_OFFSET                         17
 508 #define MACB_ARP_SIZE                           1
 509 #define MACB_SA1_OFFSET                         18
 510 #define MACB_SA1_SIZE                           1
 511 #define MACB_WOL_MTI_OFFSET                     19
 512 #define MACB_WOL_MTI_SIZE                       1
 513
 514 /* Bitfields in MID */
 515 #define MACB_IDNUM_OFFSET                       16
 516 #define MACB_IDNUM_SIZE                         16
 517 #define MACB_REV_OFFSET                         0
 518 #define MACB_REV_SIZE                           16
 519
 520 /* Bitfields in DCFG1. */
 521 #define GEM_IRQCOR_OFFSET                       23
 522 #define GEM_IRQCOR_SIZE                         1
 523 #define GEM_DBWDEF_OFFSET                       25
 524 #define GEM_DBWDEF_SIZE                         3
 525
 526 /* Bitfields in DCFG2. */
 527 #define GEM_RX_PKT_BUFF_OFFSET                  20
 528 #define GEM_RX_PKT_BUFF_SIZE                    1
 529 #define GEM_TX_PKT_BUFF_OFFSET                  21
 530 #define GEM_TX_PKT_BUFF_SIZE                    1
 531
 532 /* Constants for CLK */
 533 #define MACB_CLK_DIV8                           0
 534 #define MACB_CLK_DIV16                          1
 535 #define MACB_CLK_DIV32                          2
 536 #define MACB_CLK_DIV64                          3
 537
 538 /* GEM specific constants for CLK. */
 539 #define GEM_CLK_DIV8                            0
 540 #define GEM_CLK_DIV16                           1
 541 #define GEM_CLK_DIV32                           2
 542 #define GEM_CLK_DIV48                           3
 543 #define GEM_CLK_DIV64                           4
 544 #define GEM_CLK_DIV96                           5
 545
 546 /* Constants for MAN register */
 547 #define MACB_MAN_SOF                            1
 548 #define MACB_MAN_WRITE                          1
 549 #define MACB_MAN_READ                           2
 550 #define MACB_MAN_CODE                           2
 551
 552 /* Capability mask bits */
 553 #define MACB_CAPS_ISR_CLEAR_ON_WRITE            0x00000001
 554 #define MACB_CAPS_FIFO_MODE                     0x10000000
 555 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE        0x20000000
 556 #define MACB_CAPS_SG_DISABLED                   0x40000000
 557 #define MACB_CAPS_MACB_IS_GEM                   0x80000000
 558
 559 /* Bit manipulation macros */
 560 #define MACB_BIT(name)                                  \
 561         (1 << MACB_##name##_OFFSET)
 562 #define MACB_BF(name,value)                             \
 563         (((value) & ((1 << MACB_##name##_SIZE) - 1))    \
 564          << MACB_##name##_OFFSET)
 565 #define MACB_BFEXT(name,value)\
 566         (((value) >> MACB_##name##_OFFSET)              \
 567          & ((1 << MACB_##name##_SIZE) - 1))
 568 #define MACB_BFINS(name,value,old)                      \
 569         (((old) & ~(((1 << MACB_##name##_SIZE) - 1)     \
 570                     << MACB_##name##_OFFSET))           \
 571          | MACB_BF(name,value))
 572
 573 #define GEM_BIT(name)                                   \
 574         (1 << GEM_##name##_OFFSET)
 575 #define GEM_BF(name, value)                             \
 576         (((value) & ((1 << GEM_##name##_SIZE) - 1))     \
 577          << GEM_##name##_OFFSET)
 578 #define GEM_BFEXT(name, value)\
 579         (((value) >> GEM_##name##_OFFSET)               \
 580          & ((1 << GEM_##name##_SIZE) - 1))
 581 #define GEM_BFINS(name, value, old)                     \
 582         (((old) & ~(((1 << GEM_##name##_SIZE) - 1)      \
 583                     << GEM_##name##_OFFSET))            \
 584          | GEM_BF(name, value))
 585
 586 /* Register access macros */
 587 #define macb_readl(port,reg)                            \
 588         __raw_readl((port)->regs + MACB_##reg)
 589 #define macb_writel(port,reg,value)                     \
 590         __raw_writel((value), (port)->regs + MACB_##reg)
 591 #define gem_readl(port, reg)                            \
 592         __raw_readl((port)->regs + GEM_##reg)
 593 #define gem_writel(port, reg, value)                    \
 594         __raw_writel((value), (port)->regs + GEM_##reg)
 595 #define queue_readl(queue, reg)                         \
 596         __raw_readl((queue)->bp->regs + (queue)->reg)
 597 #define queue_writel(queue, reg, value)                 \
 598         __raw_writel((value), (queue)->bp->regs + (queue)->reg)
 599
 600 /*
 601  * Conditional GEM/MACB macros.  These perform the operation to the correct
 602  * register dependent on whether the device is a GEM or a MACB.  For registers
 603  * and bitfields that are common across both devices, use macb_{read,write}l
 604  * to avoid the cost of the conditional.
 605  */
 606 #define macb_or_gem_writel(__bp, __reg, __value) \
 607         ({ \
 608                 if (macb_is_gem((__bp))) \
 609                         gem_writel((__bp), __reg, __value); \
 610                 else \
 611                         macb_writel((__bp), __reg, __value); \
 612         })
 613
 614 #define macb_or_gem_readl(__bp, __reg) \
 615         ({ \
 616                 u32 __v; \
 617                 if (macb_is_gem((__bp))) \
 618                         __v = gem_readl((__bp), __reg); \
 619                 else \
 620                         __v = macb_readl((__bp), __reg); \
 621                 __v; \
 622         })
 623
 624 /**
 625  * struct macb_dma_desc - Hardware DMA descriptor
 626  * @addr: DMA address of data buffer
 627  * @ctrl: Control and status bits
 628  */
 629 struct macb_dma_desc {
 630         u32     addr;
 631         u32     ctrl;
 632 };
 633
 634 /* DMA descriptor bitfields */
 635 #define MACB_RX_USED_OFFSET                     0
 636 #define MACB_RX_USED_SIZE                       1
 637 #define MACB_RX_WRAP_OFFSET                     1
 638 #define MACB_RX_WRAP_SIZE                       1
 639 #define MACB_RX_WADDR_OFFSET                    2
 640 #define MACB_RX_WADDR_SIZE                      30
 641
 642 #define MACB_RX_FRMLEN_OFFSET                   0
 643 #define MACB_RX_FRMLEN_SIZE                     12
 644 #define MACB_RX_OFFSET_OFFSET                   12
 645 #define MACB_RX_OFFSET_SIZE                     2
 646 #define MACB_RX_SOF_OFFSET                      14
 647 #define MACB_RX_SOF_SIZE                        1
 648 #define MACB_RX_EOF_OFFSET                      15
 649 #define MACB_RX_EOF_SIZE                        1
 650 #define MACB_RX_CFI_OFFSET                      16
 651 #define MACB_RX_CFI_SIZE                        1
 652 #define MACB_RX_VLAN_PRI_OFFSET                 17
 653 #define MACB_RX_VLAN_PRI_SIZE                   3
 654 #define MACB_RX_PRI_TAG_OFFSET                  20
 655 #define MACB_RX_PRI_TAG_SIZE                    1
 656 #define MACB_RX_VLAN_TAG_OFFSET                 21
 657 #define MACB_RX_VLAN_TAG_SIZE                   1
 658 #define MACB_RX_TYPEID_MATCH_OFFSET             22
 659 #define MACB_RX_TYPEID_MATCH_SIZE               1
 660 #define MACB_RX_SA4_MATCH_OFFSET                23
 661 #define MACB_RX_SA4_MATCH_SIZE                  1
 662 #define MACB_RX_SA3_MATCH_OFFSET                24
 663 #define MACB_RX_SA3_MATCH_SIZE                  1
 664 #define MACB_RX_SA2_MATCH_OFFSET                25
 665 #define MACB_RX_SA2_MATCH_SIZE                  1
 666 #define MACB_RX_SA1_MATCH_OFFSET                26
 667 #define MACB_RX_SA1_MATCH_SIZE                  1
 668 #define MACB_RX_EXT_MATCH_OFFSET                28
 669 #define MACB_RX_EXT_MATCH_SIZE                  1
 670 #define MACB_RX_UHASH_MATCH_OFFSET              29
 671 #define MACB_RX_UHASH_MATCH_SIZE                1
 672 #define MACB_RX_MHASH_MATCH_OFFSET              30
 673 #define MACB_RX_MHASH_MATCH_SIZE                1
 674 #define MACB_RX_BROADCAST_OFFSET                31
 675 #define MACB_RX_BROADCAST_SIZE                  1
 676
 677 /* RX checksum offload disabled: bit 24 clear in NCFGR */
 678 #define GEM_RX_TYPEID_MATCH_OFFSET              22
 679 #define GEM_RX_TYPEID_MATCH_SIZE                2
 680
 681 /* RX checksum offload enabled: bit 24 set in NCFGR */
 682 #define GEM_RX_CSUM_OFFSET                      22
 683 #define GEM_RX_CSUM_SIZE                        2
 684
 685 #define MACB_TX_FRMLEN_OFFSET                   0
 686 #define MACB_TX_FRMLEN_SIZE                     11
 687 #define MACB_TX_LAST_OFFSET                     15
 688 #define MACB_TX_LAST_SIZE                       1
 689 #define MACB_TX_NOCRC_OFFSET                    16
 690 #define MACB_TX_NOCRC_SIZE                      1
 691 #define MACB_TX_BUF_EXHAUSTED_OFFSET            27
 692 #define MACB_TX_BUF_EXHAUSTED_SIZE              1
 693 #define MACB_TX_UNDERRUN_OFFSET                 28
 694 #define MACB_TX_UNDERRUN_SIZE                   1
 695 #define MACB_TX_ERROR_OFFSET                    29
 696 #define MACB_TX_ERROR_SIZE                      1
 697 #define MACB_TX_WRAP_OFFSET                     30
 698 #define MACB_TX_WRAP_SIZE                       1
 699 #define MACB_TX_USED_OFFSET                     31
 700 #define MACB_TX_USED_SIZE                       1
 701
 702 #define GEM_TX_FRMLEN_OFFSET                    0
 703 #define GEM_TX_FRMLEN_SIZE                      14
 704
 705 /* Buffer descriptor constants */
 706 #define GEM_RX_CSUM_NONE                        0
 707 #define GEM_RX_CSUM_IP_ONLY                     1
 708 #define GEM_RX_CSUM_IP_TCP                      2
 709 #define GEM_RX_CSUM_IP_UDP                      3
 710
 711 /* limit RX checksum offload to TCP and UDP packets */
 712 #define GEM_RX_CSUM_CHECKED_MASK                2
 713
 714 /**
 715  * struct macb_tx_skb - data about an skb which is being transmitted
 716  * @skb: skb currently being transmitted, only set for the last buffer
 717  *       of the frame
 718  * @mapping: DMA address of the skb's fragment buffer
 719  * @size: size of the DMA mapped buffer
 720  * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
 721  *                  false when buffer was mapped with dma_map_single()
 722  */
 723 struct macb_tx_skb {
 724         struct sk_buff          *skb;
 725         dma_addr_t              mapping;
 726         size_t                  size;
 727         bool                    mapped_as_page;
 728 };
 729
 730 /*
 731  * Hardware-collected statistics. Used when updating the network
 732  * device stats by a periodic timer.
 733  */
 734 struct macb_stats {
 735         u32     rx_pause_frames;
 736         u32     tx_ok;
 737         u32     tx_single_cols;
 738         u32     tx_multiple_cols;
 739         u32     rx_ok;
 740         u32     rx_fcs_errors;
 741         u32     rx_align_errors;
 742         u32     tx_deferred;
 743         u32     tx_late_cols;
 744         u32     tx_excessive_cols;
 745         u32     tx_underruns;
 746         u32     tx_carrier_errors;
 747         u32     rx_resource_errors;
 748         u32     rx_overruns;
 749         u32     rx_symbol_errors;
 750         u32     rx_oversize_pkts;
 751         u32     rx_jabbers;
 752         u32     rx_undersize_pkts;
 753         u32     sqe_test_errors;
 754         u32     rx_length_mismatch;
 755         u32     tx_pause_frames;
 756 };
 757
 758 struct gem_stats {
 759         u32     tx_octets_31_0;
 760         u32     tx_octets_47_32;
 761         u32     tx_frames;
 762         u32     tx_broadcast_frames;
 763         u32     tx_multicast_frames;
 764         u32     tx_pause_frames;
 765         u32     tx_64_byte_frames;
 766         u32     tx_65_127_byte_frames;
 767         u32     tx_128_255_byte_frames;
 768         u32     tx_256_511_byte_frames;
 769         u32     tx_512_1023_byte_frames;
 770         u32     tx_1024_1518_byte_frames;
 771         u32     tx_greater_than_1518_byte_frames;
 772         u32     tx_underrun;
 773         u32     tx_single_collision_frames;
 774         u32     tx_multiple_collision_frames;
 775         u32     tx_excessive_collisions;
 776         u32     tx_late_collisions;
 777         u32     tx_deferred_frames;
 778         u32     tx_carrier_sense_errors;
 779         u32     rx_octets_31_0;
 780         u32     rx_octets_47_32;
 781         u32     rx_frames;
 782         u32     rx_broadcast_frames;
 783         u32     rx_multicast_frames;
 784         u32     rx_pause_frames;
 785         u32     rx_64_byte_frames;
 786         u32     rx_65_127_byte_frames;
 787         u32     rx_128_255_byte_frames;
 788         u32     rx_256_511_byte_frames;
 789         u32     rx_512_1023_byte_frames;
 790         u32     rx_1024_1518_byte_frames;
 791         u32     rx_greater_than_1518_byte_frames;
 792         u32     rx_undersized_frames;
 793         u32     rx_oversize_frames;
 794         u32     rx_jabbers;
 795         u32     rx_frame_check_sequence_errors;
 796         u32     rx_length_field_frame_errors;
 797         u32     rx_symbol_errors;
 798         u32     rx_alignment_errors;
 799         u32     rx_resource_errors;
 800         u32     rx_overruns;
 801         u32     rx_ip_header_checksum_errors;
 802         u32     rx_tcp_checksum_errors;
 803         u32     rx_udp_checksum_errors;
 804 };
 805
 806 /* Describes the name and offset of an individual statistic register, as
 807  * returned by `ethtool -S`. Also describes which net_device_stats statistics
 808  * this register should contribute to.
 809  */
 810 struct gem_statistic {
 811         char stat_string[ETH_GSTRING_LEN];
 812         int offset;
 813         u32 stat_bits;
 814 };
 815
 816 /* Bitfield defs for net_device_stat statistics */
 817 #define GEM_NDS_RXERR_OFFSET            0
 818 #define GEM_NDS_RXLENERR_OFFSET         1
 819 #define GEM_NDS_RXOVERERR_OFFSET        2
 820 #define GEM_NDS_RXCRCERR_OFFSET         3
 821 #define GEM_NDS_RXFRAMEERR_OFFSET       4
 822 #define GEM_NDS_RXFIFOERR_OFFSET        5
 823 #define GEM_NDS_TXERR_OFFSET            6
 824 #define GEM_NDS_TXABORTEDERR_OFFSET     7
 825 #define GEM_NDS_TXCARRIERERR_OFFSET     8
 826 #define GEM_NDS_TXFIFOERR_OFFSET        9
 827 #define GEM_NDS_COLLISIONS_OFFSET       10
 828
 829 #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
 830 #define GEM_STAT_TITLE_BITS(name, title, bits) {        \
 831         .stat_string = title,                           \
 832         .offset = GEM_##name,                           \
 833         .stat_bits = bits                               \
 834 }
 835
 836 /* list of gem statistic registers. The names MUST match the
 837  * corresponding GEM_* definitions.
 838  */
 839 static const struct gem_statistic gem_statistics[] = {
 840         GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
 841         GEM_STAT_TITLE(TXCNT, "tx_frames"),
 842         GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
 843         GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
 844         GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
 845         GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
 846         GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
 847         GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
 848         GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
 849         GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
 850         GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
 851         GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
 852         GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
 853                             GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
 854         GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
 855                             GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
 856         GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
 857                             GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
 858         GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
 859                             GEM_BIT(NDS_TXERR)|
 860                             GEM_BIT(NDS_TXABORTEDERR)|
 861                             GEM_BIT(NDS_COLLISIONS)),
 862         GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
 863                             GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
 864         GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
 865         GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
 866                             GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
 867         GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
 868         GEM_STAT_TITLE(RXCNT, "rx_frames"),
 869         GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
 870         GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
 871         GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
 872         GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
 873         GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
 874         GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
 875         GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
 876         GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
 877         GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
 878         GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
 879         GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
 880                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
 881         GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
 882                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
 883         GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
 884                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
 885         GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
 886                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
 887         GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
 888                             GEM_BIT(NDS_RXERR)),
 889         GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
 890                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
 891         GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
 892                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
 893         GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
 894                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
 895         GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
 896                             GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
 897         GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
 898                             GEM_BIT(NDS_RXERR)),
 899         GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
 900                             GEM_BIT(NDS_RXERR)),
 901         GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
 902                             GEM_BIT(NDS_RXERR)),
 903 };
 904
 905 #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
 906
 907 struct macb;
 908
 909 struct macb_or_gem_ops {
 910         int     (*mog_alloc_rx_buffers)(struct macb *bp);
 911         void    (*mog_free_rx_buffers)(struct macb *bp);
 912         void    (*mog_init_rings)(struct macb *bp);
 913         int     (*mog_rx)(struct macb *bp, int budget);
 914 };
 915
 916 struct macb_config {
 917         u32                     caps;
 918         unsigned int            dma_burst_length;
 919 };
 920
 921 struct macb_queue {
 922         struct macb             *bp;
 923         int                     irq;
 924
 925         unsigned int            ISR;
 926         unsigned int            IER;
 927         unsigned int            IDR;
 928         unsigned int            IMR;
 929         unsigned int            TBQP;
 930
 931         unsigned int            tx_head, tx_tail;
 932         struct macb_dma_desc    *tx_ring;
 933         struct macb_tx_skb      *tx_skb;
 934         dma_addr_t              tx_ring_dma;
 935         struct work_struct      tx_error_task;
 936 };
 937
 938 struct macb {
 939         void __iomem            *regs;
 940
 941         unsigned int            rx_tail;
 942         unsigned int            rx_prepared_head;
 943         struct macb_dma_desc    *rx_ring;
 944         struct sk_buff          **rx_skbuff;
 945         void                    *rx_buffers;
 946         size_t                  rx_buffer_size;
 947
 948         unsigned int            num_queues;
 949         struct macb_queue       queues[MACB_MAX_QUEUES];
 950
 951         spinlock_t              lock;
 952         struct platform_device  *pdev;
 953         struct clk              *pclk;
 954         struct clk              *hclk;
 955         struct clk              *tx_clk;
 956         struct net_device       *dev;
 957         struct napi_struct      napi;
 958         struct net_device_stats stats;
 959         union {
 960                 struct macb_stats       macb;
 961                 struct gem_stats        gem;
 962         }                       hw_stats;
 963
 964         dma_addr_t              rx_ring_dma;
 965         dma_addr_t              rx_buffers_dma;
 966
 967         struct macb_or_gem_ops  macbgem_ops;
 968
 969         struct mii_bus          *mii_bus;
 970         struct phy_device       *phy_dev;
 971         unsigned int            link;
 972         unsigned int            speed;
 973         unsigned int            duplex;
 974
 975         u32                     caps;
 976         unsigned int            dma_burst_length;
 977
 978         phy_interface_t         phy_interface;
 979
 980         /* AT91RM9200 transmit */
 981         struct sk_buff *skb;                    /* holds skb until xmit interrupt completes */
 982         dma_addr_t skb_physaddr;                /* phys addr from pci_map_single */
 983         int skb_length;                         /* saved skb length for pci_unmap_single */
 984         unsigned int            max_tx_length;
 985
 986         u64                     ethtool_stats[GEM_STATS_LEN];
 987 };
 988
 989 extern const struct ethtool_ops macb_ethtool_ops;
 990
 991 int macb_mii_init(struct macb *bp);
 992 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 993 struct net_device_stats *macb_get_stats(struct net_device *dev);
 994 void macb_set_rx_mode(struct net_device *dev);
 995 void macb_set_hwaddr(struct macb *bp);
 996 void macb_get_hwaddr(struct macb *bp);
 997
 998 static inline bool macb_is_gem(struct macb *bp)
 999 {
1000         return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
1001 }
1002
1003 #endif /* _MACB_H */