2 * Atmel MACB Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
13 #define MACB_GREGS_NBR 16
14 #define MACB_GREGS_VERSION 1
16 /* MACB register offsets */
17 #define MACB_NCR 0x0000
18 #define MACB_NCFGR 0x0004
19 #define MACB_NSR 0x0008
20 #define MACB_TAR 0x000c /* AT91RM9200 only */
21 #define MACB_TCR 0x0010 /* AT91RM9200 only */
22 #define MACB_TSR 0x0014
23 #define MACB_RBQP 0x0018
24 #define MACB_TBQP 0x001c
25 #define MACB_RSR 0x0020
26 #define MACB_ISR 0x0024
27 #define MACB_IER 0x0028
28 #define MACB_IDR 0x002c
29 #define MACB_IMR 0x0030
30 #define MACB_MAN 0x0034
31 #define MACB_PTR 0x0038
32 #define MACB_PFR 0x003c
33 #define MACB_FTO 0x0040
34 #define MACB_SCF 0x0044
35 #define MACB_MCF 0x0048
36 #define MACB_FRO 0x004c
37 #define MACB_FCSE 0x0050
38 #define MACB_ALE 0x0054
39 #define MACB_DTF 0x0058
40 #define MACB_LCOL 0x005c
41 #define MACB_EXCOL 0x0060
42 #define MACB_TUND 0x0064
43 #define MACB_CSE 0x0068
44 #define MACB_RRE 0x006c
45 #define MACB_ROVR 0x0070
46 #define MACB_RSE 0x0074
47 #define MACB_ELE 0x0078
48 #define MACB_RJA 0x007c
49 #define MACB_USF 0x0080
50 #define MACB_STE 0x0084
51 #define MACB_RLE 0x0088
52 #define MACB_TPF 0x008c
53 #define MACB_HRB 0x0090
54 #define MACB_HRT 0x0094
55 #define MACB_SA1B 0x0098
56 #define MACB_SA1T 0x009c
57 #define MACB_SA2B 0x00a0
58 #define MACB_SA2T 0x00a4
59 #define MACB_SA3B 0x00a8
60 #define MACB_SA3T 0x00ac
61 #define MACB_SA4B 0x00b0
62 #define MACB_SA4T 0x00b4
63 #define MACB_TID 0x00b8
64 #define MACB_TPQ 0x00bc
65 #define MACB_USRIO 0x00c0
66 #define MACB_WOL 0x00c4
67 #define MACB_MID 0x00fc
69 /* GEM register offsets. */
70 #define GEM_NCFGR 0x0004
71 #define GEM_USRIO 0x000c
72 #define GEM_DMACFG 0x0010
73 #define GEM_HRB 0x0080
74 #define GEM_HRT 0x0084
75 #define GEM_SA1B 0x0088
76 #define GEM_SA1T 0x008C
77 #define GEM_SA2B 0x0090
78 #define GEM_SA2T 0x0094
79 #define GEM_SA3B 0x0098
80 #define GEM_SA3T 0x009C
81 #define GEM_SA4B 0x00A0
82 #define GEM_SA4T 0x00A4
83 #define GEM_OTX 0x0100
84 #define GEM_DCFG1 0x0280
85 #define GEM_DCFG2 0x0284
86 #define GEM_DCFG3 0x0288
87 #define GEM_DCFG4 0x028c
88 #define GEM_DCFG5 0x0290
89 #define GEM_DCFG6 0x0294
90 #define GEM_DCFG7 0x0298
92 /* Bitfields in NCR */
93 #define MACB_LB_OFFSET 0
94 #define MACB_LB_SIZE 1
95 #define MACB_LLB_OFFSET 1
96 #define MACB_LLB_SIZE 1
97 #define MACB_RE_OFFSET 2
98 #define MACB_RE_SIZE 1
99 #define MACB_TE_OFFSET 3
100 #define MACB_TE_SIZE 1
101 #define MACB_MPE_OFFSET 4
102 #define MACB_MPE_SIZE 1
103 #define MACB_CLRSTAT_OFFSET 5
104 #define MACB_CLRSTAT_SIZE 1
105 #define MACB_INCSTAT_OFFSET 6
106 #define MACB_INCSTAT_SIZE 1
107 #define MACB_WESTAT_OFFSET 7
108 #define MACB_WESTAT_SIZE 1
109 #define MACB_BP_OFFSET 8
110 #define MACB_BP_SIZE 1
111 #define MACB_TSTART_OFFSET 9
112 #define MACB_TSTART_SIZE 1
113 #define MACB_THALT_OFFSET 10
114 #define MACB_THALT_SIZE 1
115 #define MACB_NCR_TPF_OFFSET 11
116 #define MACB_NCR_TPF_SIZE 1
117 #define MACB_TZQ_OFFSET 12
118 #define MACB_TZQ_SIZE 1
120 /* Bitfields in NCFGR */
121 #define MACB_SPD_OFFSET 0
122 #define MACB_SPD_SIZE 1
123 #define MACB_FD_OFFSET 1
124 #define MACB_FD_SIZE 1
125 #define MACB_BIT_RATE_OFFSET 2
126 #define MACB_BIT_RATE_SIZE 1
127 #define MACB_JFRAME_OFFSET 3
128 #define MACB_JFRAME_SIZE 1
129 #define MACB_CAF_OFFSET 4
130 #define MACB_CAF_SIZE 1
131 #define MACB_NBC_OFFSET 5
132 #define MACB_NBC_SIZE 1
133 #define MACB_NCFGR_MTI_OFFSET 6
134 #define MACB_NCFGR_MTI_SIZE 1
135 #define MACB_UNI_OFFSET 7
136 #define MACB_UNI_SIZE 1
137 #define MACB_BIG_OFFSET 8
138 #define MACB_BIG_SIZE 1
139 #define MACB_EAE_OFFSET 9
140 #define MACB_EAE_SIZE 1
141 #define MACB_CLK_OFFSET 10
142 #define MACB_CLK_SIZE 2
143 #define MACB_RTY_OFFSET 12
144 #define MACB_RTY_SIZE 1
145 #define MACB_PAE_OFFSET 13
146 #define MACB_PAE_SIZE 1
147 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
148 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
149 #define MACB_RBOF_OFFSET 14
150 #define MACB_RBOF_SIZE 2
151 #define MACB_RLCE_OFFSET 16
152 #define MACB_RLCE_SIZE 1
153 #define MACB_DRFCS_OFFSET 17
154 #define MACB_DRFCS_SIZE 1
155 #define MACB_EFRHD_OFFSET 18
156 #define MACB_EFRHD_SIZE 1
157 #define MACB_IRXFCS_OFFSET 19
158 #define MACB_IRXFCS_SIZE 1
160 /* GEM specific NCFGR bitfields. */
161 #define GEM_GBE_OFFSET 10
162 #define GEM_GBE_SIZE 1
163 #define GEM_CLK_OFFSET 18
164 #define GEM_CLK_SIZE 3
165 #define GEM_DBW_OFFSET 21
166 #define GEM_DBW_SIZE 2
168 /* Constants for data bus width. */
173 /* Bitfields in DMACFG. */
174 #define GEM_RXBS_OFFSET 16
175 #define GEM_RXBS_SIZE 8
177 /* Bitfields in NSR */
178 #define MACB_NSR_LINK_OFFSET 0
179 #define MACB_NSR_LINK_SIZE 1
180 #define MACB_MDIO_OFFSET 1
181 #define MACB_MDIO_SIZE 1
182 #define MACB_IDLE_OFFSET 2
183 #define MACB_IDLE_SIZE 1
185 /* Bitfields in TSR */
186 #define MACB_UBR_OFFSET 0
187 #define MACB_UBR_SIZE 1
188 #define MACB_COL_OFFSET 1
189 #define MACB_COL_SIZE 1
190 #define MACB_TSR_RLE_OFFSET 2
191 #define MACB_TSR_RLE_SIZE 1
192 #define MACB_TGO_OFFSET 3
193 #define MACB_TGO_SIZE 1
194 #define MACB_BEX_OFFSET 4
195 #define MACB_BEX_SIZE 1
196 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
197 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
198 #define MACB_COMP_OFFSET 5
199 #define MACB_COMP_SIZE 1
200 #define MACB_UND_OFFSET 6
201 #define MACB_UND_SIZE 1
203 /* Bitfields in RSR */
204 #define MACB_BNA_OFFSET 0
205 #define MACB_BNA_SIZE 1
206 #define MACB_REC_OFFSET 1
207 #define MACB_REC_SIZE 1
208 #define MACB_OVR_OFFSET 2
209 #define MACB_OVR_SIZE 1
211 /* Bitfields in ISR/IER/IDR/IMR */
212 #define MACB_MFD_OFFSET 0
213 #define MACB_MFD_SIZE 1
214 #define MACB_RCOMP_OFFSET 1
215 #define MACB_RCOMP_SIZE 1
216 #define MACB_RXUBR_OFFSET 2
217 #define MACB_RXUBR_SIZE 1
218 #define MACB_TXUBR_OFFSET 3
219 #define MACB_TXUBR_SIZE 1
220 #define MACB_ISR_TUND_OFFSET 4
221 #define MACB_ISR_TUND_SIZE 1
222 #define MACB_ISR_RLE_OFFSET 5
223 #define MACB_ISR_RLE_SIZE 1
224 #define MACB_TXERR_OFFSET 6
225 #define MACB_TXERR_SIZE 1
226 #define MACB_TCOMP_OFFSET 7
227 #define MACB_TCOMP_SIZE 1
228 #define MACB_ISR_LINK_OFFSET 9
229 #define MACB_ISR_LINK_SIZE 1
230 #define MACB_ISR_ROVR_OFFSET 10
231 #define MACB_ISR_ROVR_SIZE 1
232 #define MACB_HRESP_OFFSET 11
233 #define MACB_HRESP_SIZE 1
234 #define MACB_PFR_OFFSET 12
235 #define MACB_PFR_SIZE 1
236 #define MACB_PTZ_OFFSET 13
237 #define MACB_PTZ_SIZE 1
239 /* Bitfields in MAN */
240 #define MACB_DATA_OFFSET 0
241 #define MACB_DATA_SIZE 16
242 #define MACB_CODE_OFFSET 16
243 #define MACB_CODE_SIZE 2
244 #define MACB_REGA_OFFSET 18
245 #define MACB_REGA_SIZE 5
246 #define MACB_PHYA_OFFSET 23
247 #define MACB_PHYA_SIZE 5
248 #define MACB_RW_OFFSET 28
249 #define MACB_RW_SIZE 2
250 #define MACB_SOF_OFFSET 30
251 #define MACB_SOF_SIZE 2
253 /* Bitfields in USRIO (AVR32) */
254 #define MACB_MII_OFFSET 0
255 #define MACB_MII_SIZE 1
256 #define MACB_EAM_OFFSET 1
257 #define MACB_EAM_SIZE 1
258 #define MACB_TX_PAUSE_OFFSET 2
259 #define MACB_TX_PAUSE_SIZE 1
260 #define MACB_TX_PAUSE_ZERO_OFFSET 3
261 #define MACB_TX_PAUSE_ZERO_SIZE 1
263 /* Bitfields in USRIO (AT91) */
264 #define MACB_RMII_OFFSET 0
265 #define MACB_RMII_SIZE 1
266 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
267 #define GEM_RGMII_SIZE 1
268 #define MACB_CLKEN_OFFSET 1
269 #define MACB_CLKEN_SIZE 1
271 /* Bitfields in WOL */
272 #define MACB_IP_OFFSET 0
273 #define MACB_IP_SIZE 16
274 #define MACB_MAG_OFFSET 16
275 #define MACB_MAG_SIZE 1
276 #define MACB_ARP_OFFSET 17
277 #define MACB_ARP_SIZE 1
278 #define MACB_SA1_OFFSET 18
279 #define MACB_SA1_SIZE 1
280 #define MACB_WOL_MTI_OFFSET 19
281 #define MACB_WOL_MTI_SIZE 1
283 /* Bitfields in MID */
284 #define MACB_IDNUM_OFFSET 16
285 #define MACB_IDNUM_SIZE 16
286 #define MACB_REV_OFFSET 0
287 #define MACB_REV_SIZE 16
289 /* Bitfields in DCFG1. */
290 #define GEM_DBWDEF_OFFSET 25
291 #define GEM_DBWDEF_SIZE 3
293 /* Constants for CLK */
294 #define MACB_CLK_DIV8 0
295 #define MACB_CLK_DIV16 1
296 #define MACB_CLK_DIV32 2
297 #define MACB_CLK_DIV64 3
299 /* GEM specific constants for CLK. */
300 #define GEM_CLK_DIV8 0
301 #define GEM_CLK_DIV16 1
302 #define GEM_CLK_DIV32 2
303 #define GEM_CLK_DIV48 3
304 #define GEM_CLK_DIV64 4
305 #define GEM_CLK_DIV96 5
307 /* Constants for MAN register */
308 #define MACB_MAN_SOF 1
309 #define MACB_MAN_WRITE 1
310 #define MACB_MAN_READ 2
311 #define MACB_MAN_CODE 2
313 /* Bit manipulation macros */
314 #define MACB_BIT(name) \
315 (1 << MACB_##name##_OFFSET)
316 #define MACB_BF(name,value) \
317 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
318 << MACB_##name##_OFFSET)
319 #define MACB_BFEXT(name,value)\
320 (((value) >> MACB_##name##_OFFSET) \
321 & ((1 << MACB_##name##_SIZE) - 1))
322 #define MACB_BFINS(name,value,old) \
323 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
324 << MACB_##name##_OFFSET)) \
325 | MACB_BF(name,value))
327 #define GEM_BIT(name) \
328 (1 << GEM_##name##_OFFSET)
329 #define GEM_BF(name, value) \
330 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
331 << GEM_##name##_OFFSET)
332 #define GEM_BFEXT(name, value)\
333 (((value) >> GEM_##name##_OFFSET) \
334 & ((1 << GEM_##name##_SIZE) - 1))
335 #define GEM_BFINS(name, value, old) \
336 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
337 << GEM_##name##_OFFSET)) \
338 | GEM_BF(name, value))
340 /* Register access macros */
341 #define macb_readl(port,reg) \
342 __raw_readl((port)->regs + MACB_##reg)
343 #define macb_writel(port,reg,value) \
344 __raw_writel((value), (port)->regs + MACB_##reg)
345 #define gem_readl(port, reg) \
346 __raw_readl((port)->regs + GEM_##reg)
347 #define gem_writel(port, reg, value) \
348 __raw_writel((value), (port)->regs + GEM_##reg)
351 * Conditional GEM/MACB macros. These perform the operation to the correct
352 * register dependent on whether the device is a GEM or a MACB. For registers
353 * and bitfields that are common across both devices, use macb_{read,write}l
354 * to avoid the cost of the conditional.
356 #define macb_or_gem_writel(__bp, __reg, __value) \
358 if (macb_is_gem((__bp))) \
359 gem_writel((__bp), __reg, __value); \
361 macb_writel((__bp), __reg, __value); \
364 #define macb_or_gem_readl(__bp, __reg) \
367 if (macb_is_gem((__bp))) \
368 __v = gem_readl((__bp), __reg); \
370 __v = macb_readl((__bp), __reg); \
375 * struct macb_dma_desc - Hardware DMA descriptor
376 * @addr: DMA address of data buffer
377 * @ctrl: Control and status bits
379 struct macb_dma_desc {
384 /* DMA descriptor bitfields */
385 #define MACB_RX_USED_OFFSET 0
386 #define MACB_RX_USED_SIZE 1
387 #define MACB_RX_WRAP_OFFSET 1
388 #define MACB_RX_WRAP_SIZE 1
389 #define MACB_RX_WADDR_OFFSET 2
390 #define MACB_RX_WADDR_SIZE 30
392 #define MACB_RX_FRMLEN_OFFSET 0
393 #define MACB_RX_FRMLEN_SIZE 12
394 #define MACB_RX_OFFSET_OFFSET 12
395 #define MACB_RX_OFFSET_SIZE 2
396 #define MACB_RX_SOF_OFFSET 14
397 #define MACB_RX_SOF_SIZE 1
398 #define MACB_RX_EOF_OFFSET 15
399 #define MACB_RX_EOF_SIZE 1
400 #define MACB_RX_CFI_OFFSET 16
401 #define MACB_RX_CFI_SIZE 1
402 #define MACB_RX_VLAN_PRI_OFFSET 17
403 #define MACB_RX_VLAN_PRI_SIZE 3
404 #define MACB_RX_PRI_TAG_OFFSET 20
405 #define MACB_RX_PRI_TAG_SIZE 1
406 #define MACB_RX_VLAN_TAG_OFFSET 21
407 #define MACB_RX_VLAN_TAG_SIZE 1
408 #define MACB_RX_TYPEID_MATCH_OFFSET 22
409 #define MACB_RX_TYPEID_MATCH_SIZE 1
410 #define MACB_RX_SA4_MATCH_OFFSET 23
411 #define MACB_RX_SA4_MATCH_SIZE 1
412 #define MACB_RX_SA3_MATCH_OFFSET 24
413 #define MACB_RX_SA3_MATCH_SIZE 1
414 #define MACB_RX_SA2_MATCH_OFFSET 25
415 #define MACB_RX_SA2_MATCH_SIZE 1
416 #define MACB_RX_SA1_MATCH_OFFSET 26
417 #define MACB_RX_SA1_MATCH_SIZE 1
418 #define MACB_RX_EXT_MATCH_OFFSET 28
419 #define MACB_RX_EXT_MATCH_SIZE 1
420 #define MACB_RX_UHASH_MATCH_OFFSET 29
421 #define MACB_RX_UHASH_MATCH_SIZE 1
422 #define MACB_RX_MHASH_MATCH_OFFSET 30
423 #define MACB_RX_MHASH_MATCH_SIZE 1
424 #define MACB_RX_BROADCAST_OFFSET 31
425 #define MACB_RX_BROADCAST_SIZE 1
427 #define MACB_TX_FRMLEN_OFFSET 0
428 #define MACB_TX_FRMLEN_SIZE 11
429 #define MACB_TX_LAST_OFFSET 15
430 #define MACB_TX_LAST_SIZE 1
431 #define MACB_TX_NOCRC_OFFSET 16
432 #define MACB_TX_NOCRC_SIZE 1
433 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27
434 #define MACB_TX_BUF_EXHAUSTED_SIZE 1
435 #define MACB_TX_UNDERRUN_OFFSET 28
436 #define MACB_TX_UNDERRUN_SIZE 1
437 #define MACB_TX_ERROR_OFFSET 29
438 #define MACB_TX_ERROR_SIZE 1
439 #define MACB_TX_WRAP_OFFSET 30
440 #define MACB_TX_WRAP_SIZE 1
441 #define MACB_TX_USED_OFFSET 31
442 #define MACB_TX_USED_SIZE 1
445 * struct macb_tx_skb - data about an skb which is being transmitted
446 * @skb: skb currently being transmitted
447 * @mapping: DMA address of the skb's data buffer
455 * Hardware-collected statistics. Used when updating the network
456 * device stats by a periodic timer.
462 u32 tx_multiple_cols;
468 u32 tx_excessive_cols;
470 u32 tx_carrier_errors;
471 u32 rx_resource_errors;
473 u32 rx_symbol_errors;
474 u32 rx_oversize_pkts;
476 u32 rx_undersize_pkts;
478 u32 rx_length_mismatch;
486 u32 tx_broadcast_frames;
487 u32 tx_multicast_frames;
489 u32 tx_64_byte_frames;
490 u32 tx_65_127_byte_frames;
491 u32 tx_128_255_byte_frames;
492 u32 tx_256_511_byte_frames;
493 u32 tx_512_1023_byte_frames;
494 u32 tx_1024_1518_byte_frames;
495 u32 tx_greater_than_1518_byte_frames;
497 u32 tx_single_collision_frames;
498 u32 tx_multiple_collision_frames;
499 u32 tx_excessive_collisions;
500 u32 tx_late_collisions;
501 u32 tx_deferred_frames;
502 u32 tx_carrier_sense_errors;
506 u32 rx_broadcast_frames;
507 u32 rx_multicast_frames;
509 u32 rx_64_byte_frames;
510 u32 rx_65_127_byte_frames;
511 u32 rx_128_255_byte_frames;
512 u32 rx_256_511_byte_frames;
513 u32 rx_512_1023_byte_frames;
514 u32 rx_1024_1518_byte_frames;
515 u32 rx_greater_than_1518_byte_frames;
516 u32 rx_undersized_frames;
517 u32 rx_oversize_frames;
519 u32 rx_frame_check_sequence_errors;
520 u32 rx_length_field_frame_errors;
521 u32 rx_symbol_errors;
522 u32 rx_alignment_errors;
523 u32 rx_resource_errors;
525 u32 rx_ip_header_checksum_errors;
526 u32 rx_tcp_checksum_errors;
527 u32 rx_udp_checksum_errors;
533 unsigned int rx_tail;
534 struct macb_dma_desc *rx_ring;
537 unsigned int tx_head, tx_tail;
538 struct macb_dma_desc *tx_ring;
539 struct macb_tx_skb *tx_skb;
542 struct platform_device *pdev;
545 struct net_device *dev;
546 struct napi_struct napi;
547 struct work_struct tx_error_task;
548 struct net_device_stats stats;
550 struct macb_stats macb;
551 struct gem_stats gem;
554 dma_addr_t rx_ring_dma;
555 dma_addr_t tx_ring_dma;
556 dma_addr_t rx_buffers_dma;
558 struct mii_bus *mii_bus;
559 struct phy_device *phy_dev;
564 phy_interface_t phy_interface;
566 /* AT91RM9200 transmit */
567 struct sk_buff *skb; /* holds skb until xmit interrupt completes */
568 dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
569 int skb_length; /* saved skb length for pci_unmap_single */
572 extern const struct ethtool_ops macb_ethtool_ops;
574 int macb_mii_init(struct macb *bp);
575 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
576 struct net_device_stats *macb_get_stats(struct net_device *dev);
577 void macb_set_rx_mode(struct net_device *dev);
578 void macb_set_hwaddr(struct macb *bp);
579 void macb_get_hwaddr(struct macb *bp);
581 static inline bool macb_is_gem(struct macb *bp)
583 return MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2;