2 * Atmel MACB Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
13 #define MACB_GREGS_NBR 16
14 #define MACB_GREGS_VERSION 1
16 /* MACB register offsets */
17 #define MACB_NCR 0x0000
18 #define MACB_NCFGR 0x0004
19 #define MACB_NSR 0x0008
20 #define MACB_TAR 0x000c /* AT91RM9200 only */
21 #define MACB_TCR 0x0010 /* AT91RM9200 only */
22 #define MACB_TSR 0x0014
23 #define MACB_RBQP 0x0018
24 #define MACB_TBQP 0x001c
25 #define MACB_RSR 0x0020
26 #define MACB_ISR 0x0024
27 #define MACB_IER 0x0028
28 #define MACB_IDR 0x002c
29 #define MACB_IMR 0x0030
30 #define MACB_MAN 0x0034
31 #define MACB_PTR 0x0038
32 #define MACB_PFR 0x003c
33 #define MACB_FTO 0x0040
34 #define MACB_SCF 0x0044
35 #define MACB_MCF 0x0048
36 #define MACB_FRO 0x004c
37 #define MACB_FCSE 0x0050
38 #define MACB_ALE 0x0054
39 #define MACB_DTF 0x0058
40 #define MACB_LCOL 0x005c
41 #define MACB_EXCOL 0x0060
42 #define MACB_TUND 0x0064
43 #define MACB_CSE 0x0068
44 #define MACB_RRE 0x006c
45 #define MACB_ROVR 0x0070
46 #define MACB_RSE 0x0074
47 #define MACB_ELE 0x0078
48 #define MACB_RJA 0x007c
49 #define MACB_USF 0x0080
50 #define MACB_STE 0x0084
51 #define MACB_RLE 0x0088
52 #define MACB_TPF 0x008c
53 #define MACB_HRB 0x0090
54 #define MACB_HRT 0x0094
55 #define MACB_SA1B 0x0098
56 #define MACB_SA1T 0x009c
57 #define MACB_SA2B 0x00a0
58 #define MACB_SA2T 0x00a4
59 #define MACB_SA3B 0x00a8
60 #define MACB_SA3T 0x00ac
61 #define MACB_SA4B 0x00b0
62 #define MACB_SA4T 0x00b4
63 #define MACB_TID 0x00b8
64 #define MACB_TPQ 0x00bc
65 #define MACB_USRIO 0x00c0
66 #define MACB_WOL 0x00c4
67 #define MACB_MID 0x00fc
69 /* GEM register offsets. */
70 #define GEM_NCFGR 0x0004
71 #define GEM_USRIO 0x000c
72 #define GEM_DMACFG 0x0010
73 #define GEM_HRB 0x0080
74 #define GEM_HRT 0x0084
75 #define GEM_SA1B 0x0088
76 #define GEM_SA1T 0x008C
77 #define GEM_OTX 0x0100
78 #define GEM_DCFG1 0x0280
79 #define GEM_DCFG2 0x0284
80 #define GEM_DCFG3 0x0288
81 #define GEM_DCFG4 0x028c
82 #define GEM_DCFG5 0x0290
83 #define GEM_DCFG6 0x0294
84 #define GEM_DCFG7 0x0298
86 /* Bitfields in NCR */
87 #define MACB_LB_OFFSET 0
88 #define MACB_LB_SIZE 1
89 #define MACB_LLB_OFFSET 1
90 #define MACB_LLB_SIZE 1
91 #define MACB_RE_OFFSET 2
92 #define MACB_RE_SIZE 1
93 #define MACB_TE_OFFSET 3
94 #define MACB_TE_SIZE 1
95 #define MACB_MPE_OFFSET 4
96 #define MACB_MPE_SIZE 1
97 #define MACB_CLRSTAT_OFFSET 5
98 #define MACB_CLRSTAT_SIZE 1
99 #define MACB_INCSTAT_OFFSET 6
100 #define MACB_INCSTAT_SIZE 1
101 #define MACB_WESTAT_OFFSET 7
102 #define MACB_WESTAT_SIZE 1
103 #define MACB_BP_OFFSET 8
104 #define MACB_BP_SIZE 1
105 #define MACB_TSTART_OFFSET 9
106 #define MACB_TSTART_SIZE 1
107 #define MACB_THALT_OFFSET 10
108 #define MACB_THALT_SIZE 1
109 #define MACB_NCR_TPF_OFFSET 11
110 #define MACB_NCR_TPF_SIZE 1
111 #define MACB_TZQ_OFFSET 12
112 #define MACB_TZQ_SIZE 1
114 /* Bitfields in NCFGR */
115 #define MACB_SPD_OFFSET 0
116 #define MACB_SPD_SIZE 1
117 #define MACB_FD_OFFSET 1
118 #define MACB_FD_SIZE 1
119 #define MACB_BIT_RATE_OFFSET 2
120 #define MACB_BIT_RATE_SIZE 1
121 #define MACB_JFRAME_OFFSET 3
122 #define MACB_JFRAME_SIZE 1
123 #define MACB_CAF_OFFSET 4
124 #define MACB_CAF_SIZE 1
125 #define MACB_NBC_OFFSET 5
126 #define MACB_NBC_SIZE 1
127 #define MACB_NCFGR_MTI_OFFSET 6
128 #define MACB_NCFGR_MTI_SIZE 1
129 #define MACB_UNI_OFFSET 7
130 #define MACB_UNI_SIZE 1
131 #define MACB_BIG_OFFSET 8
132 #define MACB_BIG_SIZE 1
133 #define MACB_EAE_OFFSET 9
134 #define MACB_EAE_SIZE 1
135 #define MACB_CLK_OFFSET 10
136 #define MACB_CLK_SIZE 2
137 #define MACB_RTY_OFFSET 12
138 #define MACB_RTY_SIZE 1
139 #define MACB_PAE_OFFSET 13
140 #define MACB_PAE_SIZE 1
141 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
142 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
143 #define MACB_RBOF_OFFSET 14
144 #define MACB_RBOF_SIZE 2
145 #define MACB_RLCE_OFFSET 16
146 #define MACB_RLCE_SIZE 1
147 #define MACB_DRFCS_OFFSET 17
148 #define MACB_DRFCS_SIZE 1
149 #define MACB_EFRHD_OFFSET 18
150 #define MACB_EFRHD_SIZE 1
151 #define MACB_IRXFCS_OFFSET 19
152 #define MACB_IRXFCS_SIZE 1
154 /* GEM specific NCFGR bitfields. */
155 #define GEM_GBE_OFFSET 10
156 #define GEM_GBE_SIZE 1
157 #define GEM_CLK_OFFSET 18
158 #define GEM_CLK_SIZE 3
159 #define GEM_DBW_OFFSET 21
160 #define GEM_DBW_SIZE 2
162 /* Constants for data bus width. */
167 /* Bitfields in DMACFG. */
168 #define GEM_RXBS_OFFSET 16
169 #define GEM_RXBS_SIZE 8
171 /* Bitfields in NSR */
172 #define MACB_NSR_LINK_OFFSET 0
173 #define MACB_NSR_LINK_SIZE 1
174 #define MACB_MDIO_OFFSET 1
175 #define MACB_MDIO_SIZE 1
176 #define MACB_IDLE_OFFSET 2
177 #define MACB_IDLE_SIZE 1
179 /* Bitfields in TSR */
180 #define MACB_UBR_OFFSET 0
181 #define MACB_UBR_SIZE 1
182 #define MACB_COL_OFFSET 1
183 #define MACB_COL_SIZE 1
184 #define MACB_TSR_RLE_OFFSET 2
185 #define MACB_TSR_RLE_SIZE 1
186 #define MACB_TGO_OFFSET 3
187 #define MACB_TGO_SIZE 1
188 #define MACB_BEX_OFFSET 4
189 #define MACB_BEX_SIZE 1
190 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
191 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
192 #define MACB_COMP_OFFSET 5
193 #define MACB_COMP_SIZE 1
194 #define MACB_UND_OFFSET 6
195 #define MACB_UND_SIZE 1
197 /* Bitfields in RSR */
198 #define MACB_BNA_OFFSET 0
199 #define MACB_BNA_SIZE 1
200 #define MACB_REC_OFFSET 1
201 #define MACB_REC_SIZE 1
202 #define MACB_OVR_OFFSET 2
203 #define MACB_OVR_SIZE 1
205 /* Bitfields in ISR/IER/IDR/IMR */
206 #define MACB_MFD_OFFSET 0
207 #define MACB_MFD_SIZE 1
208 #define MACB_RCOMP_OFFSET 1
209 #define MACB_RCOMP_SIZE 1
210 #define MACB_RXUBR_OFFSET 2
211 #define MACB_RXUBR_SIZE 1
212 #define MACB_TXUBR_OFFSET 3
213 #define MACB_TXUBR_SIZE 1
214 #define MACB_ISR_TUND_OFFSET 4
215 #define MACB_ISR_TUND_SIZE 1
216 #define MACB_ISR_RLE_OFFSET 5
217 #define MACB_ISR_RLE_SIZE 1
218 #define MACB_TXERR_OFFSET 6
219 #define MACB_TXERR_SIZE 1
220 #define MACB_TCOMP_OFFSET 7
221 #define MACB_TCOMP_SIZE 1
222 #define MACB_ISR_LINK_OFFSET 9
223 #define MACB_ISR_LINK_SIZE 1
224 #define MACB_ISR_ROVR_OFFSET 10
225 #define MACB_ISR_ROVR_SIZE 1
226 #define MACB_HRESP_OFFSET 11
227 #define MACB_HRESP_SIZE 1
228 #define MACB_PFR_OFFSET 12
229 #define MACB_PFR_SIZE 1
230 #define MACB_PTZ_OFFSET 13
231 #define MACB_PTZ_SIZE 1
233 /* Bitfields in MAN */
234 #define MACB_DATA_OFFSET 0
235 #define MACB_DATA_SIZE 16
236 #define MACB_CODE_OFFSET 16
237 #define MACB_CODE_SIZE 2
238 #define MACB_REGA_OFFSET 18
239 #define MACB_REGA_SIZE 5
240 #define MACB_PHYA_OFFSET 23
241 #define MACB_PHYA_SIZE 5
242 #define MACB_RW_OFFSET 28
243 #define MACB_RW_SIZE 2
244 #define MACB_SOF_OFFSET 30
245 #define MACB_SOF_SIZE 2
247 /* Bitfields in USRIO (AVR32) */
248 #define MACB_MII_OFFSET 0
249 #define MACB_MII_SIZE 1
250 #define MACB_EAM_OFFSET 1
251 #define MACB_EAM_SIZE 1
252 #define MACB_TX_PAUSE_OFFSET 2
253 #define MACB_TX_PAUSE_SIZE 1
254 #define MACB_TX_PAUSE_ZERO_OFFSET 3
255 #define MACB_TX_PAUSE_ZERO_SIZE 1
257 /* Bitfields in USRIO (AT91) */
258 #define MACB_RMII_OFFSET 0
259 #define MACB_RMII_SIZE 1
260 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
261 #define GEM_RGMII_SIZE 1
262 #define MACB_CLKEN_OFFSET 1
263 #define MACB_CLKEN_SIZE 1
265 /* Bitfields in WOL */
266 #define MACB_IP_OFFSET 0
267 #define MACB_IP_SIZE 16
268 #define MACB_MAG_OFFSET 16
269 #define MACB_MAG_SIZE 1
270 #define MACB_ARP_OFFSET 17
271 #define MACB_ARP_SIZE 1
272 #define MACB_SA1_OFFSET 18
273 #define MACB_SA1_SIZE 1
274 #define MACB_WOL_MTI_OFFSET 19
275 #define MACB_WOL_MTI_SIZE 1
277 /* Bitfields in MID */
278 #define MACB_IDNUM_OFFSET 16
279 #define MACB_IDNUM_SIZE 16
280 #define MACB_REV_OFFSET 0
281 #define MACB_REV_SIZE 16
283 /* Bitfields in DCFG1. */
284 #define GEM_DBWDEF_OFFSET 25
285 #define GEM_DBWDEF_SIZE 3
287 /* Constants for CLK */
288 #define MACB_CLK_DIV8 0
289 #define MACB_CLK_DIV16 1
290 #define MACB_CLK_DIV32 2
291 #define MACB_CLK_DIV64 3
293 /* GEM specific constants for CLK. */
294 #define GEM_CLK_DIV8 0
295 #define GEM_CLK_DIV16 1
296 #define GEM_CLK_DIV32 2
297 #define GEM_CLK_DIV48 3
298 #define GEM_CLK_DIV64 4
299 #define GEM_CLK_DIV96 5
301 /* Constants for MAN register */
302 #define MACB_MAN_SOF 1
303 #define MACB_MAN_WRITE 1
304 #define MACB_MAN_READ 2
305 #define MACB_MAN_CODE 2
307 /* Bit manipulation macros */
308 #define MACB_BIT(name) \
309 (1 << MACB_##name##_OFFSET)
310 #define MACB_BF(name,value) \
311 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
312 << MACB_##name##_OFFSET)
313 #define MACB_BFEXT(name,value)\
314 (((value) >> MACB_##name##_OFFSET) \
315 & ((1 << MACB_##name##_SIZE) - 1))
316 #define MACB_BFINS(name,value,old) \
317 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
318 << MACB_##name##_OFFSET)) \
319 | MACB_BF(name,value))
321 #define GEM_BIT(name) \
322 (1 << GEM_##name##_OFFSET)
323 #define GEM_BF(name, value) \
324 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
325 << GEM_##name##_OFFSET)
326 #define GEM_BFEXT(name, value)\
327 (((value) >> GEM_##name##_OFFSET) \
328 & ((1 << GEM_##name##_SIZE) - 1))
329 #define GEM_BFINS(name, value, old) \
330 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
331 << GEM_##name##_OFFSET)) \
332 | GEM_BF(name, value))
334 /* Register access macros */
335 #define macb_readl(port,reg) \
336 __raw_readl((port)->regs + MACB_##reg)
337 #define macb_writel(port,reg,value) \
338 __raw_writel((value), (port)->regs + MACB_##reg)
339 #define gem_readl(port, reg) \
340 __raw_readl((port)->regs + GEM_##reg)
341 #define gem_writel(port, reg, value) \
342 __raw_writel((value), (port)->regs + GEM_##reg)
345 * Conditional GEM/MACB macros. These perform the operation to the correct
346 * register dependent on whether the device is a GEM or a MACB. For registers
347 * and bitfields that are common across both devices, use macb_{read,write}l
348 * to avoid the cost of the conditional.
350 #define macb_or_gem_writel(__bp, __reg, __value) \
352 if (macb_is_gem((__bp))) \
353 gem_writel((__bp), __reg, __value); \
355 macb_writel((__bp), __reg, __value); \
358 #define macb_or_gem_readl(__bp, __reg) \
361 if (macb_is_gem((__bp))) \
362 __v = gem_readl((__bp), __reg); \
364 __v = macb_readl((__bp), __reg); \
369 * struct macb_dma_desc - Hardware DMA descriptor
370 * @addr: DMA address of data buffer
371 * @ctrl: Control and status bits
373 struct macb_dma_desc {
378 /* DMA descriptor bitfields */
379 #define MACB_RX_USED_OFFSET 0
380 #define MACB_RX_USED_SIZE 1
381 #define MACB_RX_WRAP_OFFSET 1
382 #define MACB_RX_WRAP_SIZE 1
383 #define MACB_RX_WADDR_OFFSET 2
384 #define MACB_RX_WADDR_SIZE 30
386 #define MACB_RX_FRMLEN_OFFSET 0
387 #define MACB_RX_FRMLEN_SIZE 12
388 #define MACB_RX_OFFSET_OFFSET 12
389 #define MACB_RX_OFFSET_SIZE 2
390 #define MACB_RX_SOF_OFFSET 14
391 #define MACB_RX_SOF_SIZE 1
392 #define MACB_RX_EOF_OFFSET 15
393 #define MACB_RX_EOF_SIZE 1
394 #define MACB_RX_CFI_OFFSET 16
395 #define MACB_RX_CFI_SIZE 1
396 #define MACB_RX_VLAN_PRI_OFFSET 17
397 #define MACB_RX_VLAN_PRI_SIZE 3
398 #define MACB_RX_PRI_TAG_OFFSET 20
399 #define MACB_RX_PRI_TAG_SIZE 1
400 #define MACB_RX_VLAN_TAG_OFFSET 21
401 #define MACB_RX_VLAN_TAG_SIZE 1
402 #define MACB_RX_TYPEID_MATCH_OFFSET 22
403 #define MACB_RX_TYPEID_MATCH_SIZE 1
404 #define MACB_RX_SA4_MATCH_OFFSET 23
405 #define MACB_RX_SA4_MATCH_SIZE 1
406 #define MACB_RX_SA3_MATCH_OFFSET 24
407 #define MACB_RX_SA3_MATCH_SIZE 1
408 #define MACB_RX_SA2_MATCH_OFFSET 25
409 #define MACB_RX_SA2_MATCH_SIZE 1
410 #define MACB_RX_SA1_MATCH_OFFSET 26
411 #define MACB_RX_SA1_MATCH_SIZE 1
412 #define MACB_RX_EXT_MATCH_OFFSET 28
413 #define MACB_RX_EXT_MATCH_SIZE 1
414 #define MACB_RX_UHASH_MATCH_OFFSET 29
415 #define MACB_RX_UHASH_MATCH_SIZE 1
416 #define MACB_RX_MHASH_MATCH_OFFSET 30
417 #define MACB_RX_MHASH_MATCH_SIZE 1
418 #define MACB_RX_BROADCAST_OFFSET 31
419 #define MACB_RX_BROADCAST_SIZE 1
421 #define MACB_TX_FRMLEN_OFFSET 0
422 #define MACB_TX_FRMLEN_SIZE 11
423 #define MACB_TX_LAST_OFFSET 15
424 #define MACB_TX_LAST_SIZE 1
425 #define MACB_TX_NOCRC_OFFSET 16
426 #define MACB_TX_NOCRC_SIZE 1
427 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27
428 #define MACB_TX_BUF_EXHAUSTED_SIZE 1
429 #define MACB_TX_UNDERRUN_OFFSET 28
430 #define MACB_TX_UNDERRUN_SIZE 1
431 #define MACB_TX_ERROR_OFFSET 29
432 #define MACB_TX_ERROR_SIZE 1
433 #define MACB_TX_WRAP_OFFSET 30
434 #define MACB_TX_WRAP_SIZE 1
435 #define MACB_TX_USED_OFFSET 31
436 #define MACB_TX_USED_SIZE 1
439 * struct macb_tx_skb - data about an skb which is being transmitted
440 * @skb: skb currently being transmitted
441 * @mapping: DMA address of the skb's data buffer
449 * Hardware-collected statistics. Used when updating the network
450 * device stats by a periodic timer.
456 u32 tx_multiple_cols;
462 u32 tx_excessive_cols;
464 u32 tx_carrier_errors;
465 u32 rx_resource_errors;
467 u32 rx_symbol_errors;
468 u32 rx_oversize_pkts;
470 u32 rx_undersize_pkts;
472 u32 rx_length_mismatch;
480 u32 tx_broadcast_frames;
481 u32 tx_multicast_frames;
483 u32 tx_64_byte_frames;
484 u32 tx_65_127_byte_frames;
485 u32 tx_128_255_byte_frames;
486 u32 tx_256_511_byte_frames;
487 u32 tx_512_1023_byte_frames;
488 u32 tx_1024_1518_byte_frames;
489 u32 tx_greater_than_1518_byte_frames;
491 u32 tx_single_collision_frames;
492 u32 tx_multiple_collision_frames;
493 u32 tx_excessive_collisions;
494 u32 tx_late_collisions;
495 u32 tx_deferred_frames;
496 u32 tx_carrier_sense_errors;
500 u32 rx_broadcast_frames;
501 u32 rx_multicast_frames;
503 u32 rx_64_byte_frames;
504 u32 rx_65_127_byte_frames;
505 u32 rx_128_255_byte_frames;
506 u32 rx_256_511_byte_frames;
507 u32 rx_512_1023_byte_frames;
508 u32 rx_1024_1518_byte_frames;
509 u32 rx_greater_than_1518_byte_frames;
510 u32 rx_undersized_frames;
511 u32 rx_oversize_frames;
513 u32 rx_frame_check_sequence_errors;
514 u32 rx_length_field_frame_errors;
515 u32 rx_symbol_errors;
516 u32 rx_alignment_errors;
517 u32 rx_resource_errors;
519 u32 rx_ip_header_checksum_errors;
520 u32 rx_tcp_checksum_errors;
521 u32 rx_udp_checksum_errors;
527 unsigned int rx_tail;
528 struct macb_dma_desc *rx_ring;
531 unsigned int tx_head, tx_tail;
532 struct macb_dma_desc *tx_ring;
533 struct macb_tx_skb *tx_skb;
536 struct platform_device *pdev;
539 struct net_device *dev;
540 struct napi_struct napi;
541 struct work_struct tx_error_task;
542 struct net_device_stats stats;
544 struct macb_stats macb;
545 struct gem_stats gem;
548 dma_addr_t rx_ring_dma;
549 dma_addr_t tx_ring_dma;
550 dma_addr_t rx_buffers_dma;
552 struct mii_bus *mii_bus;
553 struct phy_device *phy_dev;
558 phy_interface_t phy_interface;
561 struct macb_platform_data board_data; /* board-specific
562 * configuration (shared with
563 * macb for common data */
566 struct sk_buff *skb; /* holds skb until xmit interrupt completes */
567 dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
568 int skb_length; /* saved skb length for pci_unmap_single */
571 extern const struct ethtool_ops macb_ethtool_ops;
573 int macb_mii_init(struct macb *bp);
574 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
575 void macb_set_rx_mode(struct net_device *dev);
576 void macb_set_hwaddr(struct macb *bp);
577 void macb_get_hwaddr(struct macb *bp);
579 static inline bool macb_is_gem(struct macb *bp)
581 return MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2;