2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <asm/uaccess.h>
71 #define DRV_VERSION "1.3.0-ko"
72 #define DRV_DESC "Chelsio T4 Network Driver"
75 * Max interrupt hold-off timer value in us. Queues fall back to this value
76 * under extreme memory pressure so it's largish to give the system time to
79 #define MAX_SGE_TIMERVAL 200U
83 * Physical Function provisioning constants.
85 PFRES_NVI = 4, /* # of Virtual Interfaces */
86 PFRES_NETHCTRL = 128, /* # of EQs used for ETH or CTRL Qs */
87 PFRES_NIQFLINT = 128, /* # of ingress Qs/w Free List(s)/intr
89 PFRES_NEQ = 256, /* # of egress queues */
90 PFRES_NIQ = 0, /* # of ingress queues */
91 PFRES_TC = 0, /* PCI-E traffic class */
92 PFRES_NEXACTF = 128, /* # of exact MPS filters */
94 PFRES_R_CAPS = FW_CMD_CAP_PF,
95 PFRES_WX_CAPS = FW_CMD_CAP_PF,
99 * Virtual Function provisioning constants. We need two extra Ingress
100 * Queues with Interrupt capability to serve as the VF's Firmware
101 * Event Queue and Forwarded Interrupt Queue (when using MSI mode) --
102 * neither will have Free Lists associated with them). For each
103 * Ethernet/Control Egress Queue and for each Free List, we need an
106 VFRES_NPORTS = 1, /* # of "ports" per VF */
107 VFRES_NQSETS = 2, /* # of "Queue Sets" per VF */
109 VFRES_NVI = VFRES_NPORTS, /* # of Virtual Interfaces */
110 VFRES_NETHCTRL = VFRES_NQSETS, /* # of EQs used for ETH or CTRL Qs */
111 VFRES_NIQFLINT = VFRES_NQSETS+2,/* # of ingress Qs/w Free List(s)/intr */
112 VFRES_NEQ = VFRES_NQSETS*2, /* # of egress queues */
113 VFRES_NIQ = 0, /* # of non-fl/int ingress queues */
114 VFRES_TC = 0, /* PCI-E traffic class */
115 VFRES_NEXACTF = 16, /* # of exact MPS filters */
117 VFRES_R_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF|FW_CMD_CAP_PORT,
118 VFRES_WX_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF,
123 * Provide a Port Access Rights Mask for the specified PF/VF. This is very
124 * static and likely not to be useful in the long run. We really need to
125 * implement some form of persistent configuration which the firmware
128 static unsigned int pfvfres_pmask(struct adapter *adapter,
129 unsigned int pf, unsigned int vf)
131 unsigned int portn, portvec;
134 * Give PF's access to all of the ports.
137 return FW_PFVF_CMD_PMASK_MASK;
140 * For VFs, we'll assign them access to the ports based purely on the
141 * PF. We assign active ports in order, wrapping around if there are
142 * fewer active ports than PFs: e.g. active port[pf % nports].
143 * Unfortunately the adapter's port_info structs haven't been
144 * initialized yet so we have to compute this.
146 if (adapter->params.nports == 0)
149 portn = pf % adapter->params.nports;
150 portvec = adapter->params.portvec;
153 * Isolate the lowest set bit in the port vector. If we're at
154 * the port number that we want, return that as the pmask.
155 * otherwise mask that bit out of the port vector and
156 * decrement our port number ...
158 unsigned int pmask = portvec ^ (portvec & (portvec-1));
168 MAX_TXQ_ENTRIES = 16384,
169 MAX_CTRL_TXQ_ENTRIES = 1024,
170 MAX_RSPQ_ENTRIES = 16384,
171 MAX_RX_BUFFERS = 16384,
172 MIN_TXQ_ENTRIES = 32,
173 MIN_CTRL_TXQ_ENTRIES = 32,
174 MIN_RSPQ_ENTRIES = 128,
178 /* Host shadow copy of ingress filter entry. This is in host native format
179 * and doesn't match the ordering or bit order, etc. of the hardware of the
180 * firmware command. The use of bit-field structure elements is purely to
181 * remind ourselves of the field size limitations and save memory in the case
182 * where the filter table is large.
184 struct filter_entry {
185 /* Administrative fields for filter.
187 u32 valid:1; /* filter allocated and valid */
188 u32 locked:1; /* filter is administratively locked */
190 u32 pending:1; /* filter action is pending firmware reply */
191 u32 smtidx:8; /* Source MAC Table index for smac */
192 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
194 /* The filter itself. Most of this is a straight copy of information
195 * provided by the extended ioctl(). Some fields are translated to
196 * internal forms -- for instance the Ingress Queue ID passed in from
197 * the ioctl() is translated into the Absolute Ingress Queue ID.
199 struct ch_filter_specification fs;
202 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
203 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
204 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
206 #define CH_DEVICE(devid, data) { PCI_VDEVICE(CHELSIO, devid), (data) }
208 static DEFINE_PCI_DEVICE_TABLE(cxgb4_pci_tbl) = {
209 CH_DEVICE(0xa000, 0), /* PE10K */
210 CH_DEVICE(0x4001, -1),
211 CH_DEVICE(0x4002, -1),
212 CH_DEVICE(0x4003, -1),
213 CH_DEVICE(0x4004, -1),
214 CH_DEVICE(0x4005, -1),
215 CH_DEVICE(0x4006, -1),
216 CH_DEVICE(0x4007, -1),
217 CH_DEVICE(0x4008, -1),
218 CH_DEVICE(0x4009, -1),
219 CH_DEVICE(0x400a, -1),
220 CH_DEVICE(0x4401, 4),
221 CH_DEVICE(0x4402, 4),
222 CH_DEVICE(0x4403, 4),
223 CH_DEVICE(0x4404, 4),
224 CH_DEVICE(0x4405, 4),
225 CH_DEVICE(0x4406, 4),
226 CH_DEVICE(0x4407, 4),
227 CH_DEVICE(0x4408, 4),
228 CH_DEVICE(0x4409, 4),
229 CH_DEVICE(0x440a, 4),
230 CH_DEVICE(0x440d, 4),
231 CH_DEVICE(0x440e, 4),
235 #define FW_FNAME "cxgb4/t4fw.bin"
236 #define FW_CFNAME "cxgb4/t4-config.txt"
238 MODULE_DESCRIPTION(DRV_DESC);
239 MODULE_AUTHOR("Chelsio Communications");
240 MODULE_LICENSE("Dual BSD/GPL");
241 MODULE_VERSION(DRV_VERSION);
242 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
243 MODULE_FIRMWARE(FW_FNAME);
246 * Normally we're willing to become the firmware's Master PF but will be happy
247 * if another PF has already become the Master and initialized the adapter.
248 * Setting "force_init" will cause this driver to forcibly establish itself as
249 * the Master PF and initialize the adapter.
251 static uint force_init;
253 module_param(force_init, uint, 0644);
254 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
257 * Normally if the firmware we connect to has Configuration File support, we
258 * use that and only fall back to the old Driver-based initialization if the
259 * Configuration File fails for some reason. If force_old_init is set, then
260 * we'll always use the old Driver-based initialization sequence.
262 static uint force_old_init;
264 module_param(force_old_init, uint, 0644);
265 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence");
267 static int dflt_msg_enable = DFLT_MSG_ENABLE;
269 module_param(dflt_msg_enable, int, 0644);
270 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
273 * The driver uses the best interrupt scheme available on a platform in the
274 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
275 * of these schemes the driver may consider as follows:
277 * msi = 2: choose from among all three options
278 * msi = 1: only consider MSI and INTx interrupts
279 * msi = 0: force INTx interrupts
283 module_param(msi, int, 0644);
284 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
287 * Queue interrupt hold-off timer values. Queues default to the first of these
290 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
292 module_param_array(intr_holdoff, uint, NULL, 0644);
293 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
294 "0..4 in microseconds");
296 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
298 module_param_array(intr_cnt, uint, NULL, 0644);
299 MODULE_PARM_DESC(intr_cnt,
300 "thresholds 1..3 for queue interrupt packet counters");
303 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
304 * offset by 2 bytes in order to have the IP headers line up on 4-byte
305 * boundaries. This is a requirement for many architectures which will throw
306 * a machine check fault if an attempt is made to access one of the 4-byte IP
307 * header fields on a non-4-byte boundary. And it's a major performance issue
308 * even on some architectures which allow it like some implementations of the
309 * x86 ISA. However, some architectures don't mind this and for some very
310 * edge-case performance sensitive applications (like forwarding large volumes
311 * of small packets), setting this DMA offset to 0 will decrease the number of
312 * PCI-E Bus transfers enough to measurably affect performance.
314 static int rx_dma_offset = 2;
318 #ifdef CONFIG_PCI_IOV
319 module_param(vf_acls, bool, 0644);
320 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
322 static unsigned int num_vf[4];
324 module_param_array(num_vf, uint, NULL, 0644);
325 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
329 * The filter TCAM has a fixed portion and a variable portion. The fixed
330 * portion can match on source/destination IP IPv4/IPv6 addresses and TCP/UDP
331 * ports. The variable portion is 36 bits which can include things like Exact
332 * Match MAC Index (9 bits), Ether Type (16 bits), IP Protocol (8 bits),
333 * [Inner] VLAN Tag (17 bits), etc. which, if all were somehow selected, would
334 * far exceed the 36-bit budget for this "compressed" header portion of the
335 * filter. Thus, we have a scarce resource which must be carefully managed.
337 * By default we set this up to mostly match the set of filter matching
338 * capabilities of T3 but with accommodations for some of T4's more
339 * interesting features:
341 * { IP Fragment (1), MPS Match Type (3), IP Protocol (8),
342 * [Inner] VLAN (17), Port (3), FCoE (1) }
345 TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
346 TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT,
347 TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT,
350 static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
352 module_param(tp_vlan_pri_map, uint, 0644);
353 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration");
355 static struct dentry *cxgb4_debugfs_root;
357 static LIST_HEAD(adapter_list);
358 static DEFINE_MUTEX(uld_mutex);
359 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
360 static const char *uld_str[] = { "RDMA", "iSCSI" };
362 static void link_report(struct net_device *dev)
364 if (!netif_carrier_ok(dev))
365 netdev_info(dev, "link down\n");
367 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
369 const char *s = "10Mbps";
370 const struct port_info *p = netdev_priv(dev);
372 switch (p->link_cfg.speed) {
384 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
389 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
391 struct net_device *dev = adapter->port[port_id];
393 /* Skip changes from disabled ports. */
394 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
396 netif_carrier_on(dev);
398 netif_carrier_off(dev);
404 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
406 static const char *mod_str[] = {
407 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
410 const struct net_device *dev = adap->port[port_id];
411 const struct port_info *pi = netdev_priv(dev);
413 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
414 netdev_info(dev, "port module unplugged\n");
415 else if (pi->mod_type < ARRAY_SIZE(mod_str))
416 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
420 * Configure the exact and hash address filters to handle a port's multicast
421 * and secondary unicast MAC addresses.
423 static int set_addr_filters(const struct net_device *dev, bool sleep)
431 const struct netdev_hw_addr *ha;
432 int uc_cnt = netdev_uc_count(dev);
433 int mc_cnt = netdev_mc_count(dev);
434 const struct port_info *pi = netdev_priv(dev);
435 unsigned int mb = pi->adapter->fn;
437 /* first do the secondary unicast addresses */
438 netdev_for_each_uc_addr(ha, dev) {
439 addr[naddr++] = ha->addr;
440 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
441 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
442 naddr, addr, filt_idx, &uhash, sleep);
451 /* next set up the multicast addresses */
452 netdev_for_each_mc_addr(ha, dev) {
453 addr[naddr++] = ha->addr;
454 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
455 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
456 naddr, addr, filt_idx, &mhash, sleep);
465 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
466 uhash | mhash, sleep);
469 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
470 module_param(dbfifo_int_thresh, int, 0644);
471 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
474 * usecs to sleep while draining the dbfifo
476 static int dbfifo_drain_delay = 1000;
477 module_param(dbfifo_drain_delay, int, 0644);
478 MODULE_PARM_DESC(dbfifo_drain_delay,
479 "usecs to sleep while draining the dbfifo");
482 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
483 * If @mtu is -1 it is left unchanged.
485 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
488 struct port_info *pi = netdev_priv(dev);
490 ret = set_addr_filters(dev, sleep_ok);
492 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
493 (dev->flags & IFF_PROMISC) ? 1 : 0,
494 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
499 static struct workqueue_struct *workq;
502 * link_start - enable a port
503 * @dev: the port to enable
505 * Performs the MAC and PHY actions needed to enable a port.
507 static int link_start(struct net_device *dev)
510 struct port_info *pi = netdev_priv(dev);
511 unsigned int mb = pi->adapter->fn;
514 * We do not set address filters and promiscuity here, the stack does
515 * that step explicitly.
517 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
518 !!(dev->features & NETIF_F_HW_VLAN_RX), true);
520 ret = t4_change_mac(pi->adapter, mb, pi->viid,
521 pi->xact_addr_filt, dev->dev_addr, true,
524 pi->xact_addr_filt = ret;
529 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
532 ret = t4_enable_vi(pi->adapter, mb, pi->viid, true, true);
536 /* Clear a filter and release any of its resources that we own. This also
537 * clears the filter's "pending" status.
539 static void clear_filter(struct adapter *adap, struct filter_entry *f)
541 /* If the new or old filter have loopback rewriteing rules then we'll
542 * need to free any existing Layer Two Table (L2T) entries of the old
543 * filter rule. The firmware will handle freeing up any Source MAC
544 * Table (SMT) entries used for rewriting Source MAC Addresses in
548 cxgb4_l2t_release(f->l2t);
550 /* The zeroing of the filter rule below clears the filter valid,
551 * pending, locked flags, l2t pointer, etc. so it's all we need for
554 memset(f, 0, sizeof(*f));
557 /* Handle a filter write/deletion reply.
559 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
561 unsigned int idx = GET_TID(rpl);
562 unsigned int nidx = idx - adap->tids.ftid_base;
564 struct filter_entry *f;
566 if (idx >= adap->tids.ftid_base && nidx <
567 (adap->tids.nftids + adap->tids.nsftids)) {
569 ret = GET_TCB_COOKIE(rpl->cookie);
570 f = &adap->tids.ftid_tab[idx];
572 if (ret == FW_FILTER_WR_FLT_DELETED) {
573 /* Clear the filter when we get confirmation from the
574 * hardware that the filter has been deleted.
576 clear_filter(adap, f);
577 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
578 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
580 clear_filter(adap, f);
581 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
582 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
583 f->pending = 0; /* asynchronous setup completed */
586 /* Something went wrong. Issue a warning about the
587 * problem and clear everything out.
589 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
591 clear_filter(adap, f);
596 /* Response queue handler for the FW event queue.
598 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
599 const struct pkt_gl *gl)
601 u8 opcode = ((const struct rss_header *)rsp)->opcode;
603 rsp++; /* skip RSS header */
604 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
605 const struct cpl_sge_egr_update *p = (void *)rsp;
606 unsigned int qid = EGR_QID(ntohl(p->opcode_qid));
609 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
611 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
612 struct sge_eth_txq *eq;
614 eq = container_of(txq, struct sge_eth_txq, q);
615 netif_tx_wake_queue(eq->txq);
617 struct sge_ofld_txq *oq;
619 oq = container_of(txq, struct sge_ofld_txq, q);
620 tasklet_schedule(&oq->qresume_tsk);
622 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
623 const struct cpl_fw6_msg *p = (void *)rsp;
626 t4_handle_fw_rpl(q->adap, p->data);
627 } else if (opcode == CPL_L2T_WRITE_RPL) {
628 const struct cpl_l2t_write_rpl *p = (void *)rsp;
630 do_l2t_write_rpl(q->adap, p);
631 } else if (opcode == CPL_SET_TCB_RPL) {
632 const struct cpl_set_tcb_rpl *p = (void *)rsp;
634 filter_rpl(q->adap, p);
636 dev_err(q->adap->pdev_dev,
637 "unexpected CPL %#x on FW event queue\n", opcode);
642 * uldrx_handler - response queue handler for ULD queues
643 * @q: the response queue that received the packet
644 * @rsp: the response queue descriptor holding the offload message
645 * @gl: the gather list of packet fragments
647 * Deliver an ingress offload packet to a ULD. All processing is done by
648 * the ULD, we just maintain statistics.
650 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
651 const struct pkt_gl *gl)
653 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
655 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
661 else if (gl == CXGB4_MSG_AN)
668 static void disable_msi(struct adapter *adapter)
670 if (adapter->flags & USING_MSIX) {
671 pci_disable_msix(adapter->pdev);
672 adapter->flags &= ~USING_MSIX;
673 } else if (adapter->flags & USING_MSI) {
674 pci_disable_msi(adapter->pdev);
675 adapter->flags &= ~USING_MSI;
680 * Interrupt handler for non-data events used with MSI-X.
682 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
684 struct adapter *adap = cookie;
686 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
689 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
691 t4_slow_intr_handler(adap);
696 * Name the MSI-X interrupts.
698 static void name_msix_vecs(struct adapter *adap)
700 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
702 /* non-data interrupts */
703 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
706 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
707 adap->port[0]->name);
709 /* Ethernet queues */
710 for_each_port(adap, j) {
711 struct net_device *d = adap->port[j];
712 const struct port_info *pi = netdev_priv(d);
714 for (i = 0; i < pi->nqsets; i++, msi_idx++)
715 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
720 for_each_ofldrxq(&adap->sge, i)
721 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
722 adap->port[0]->name, i);
724 for_each_rdmarxq(&adap->sge, i)
725 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
726 adap->port[0]->name, i);
729 static int request_msix_queue_irqs(struct adapter *adap)
731 struct sge *s = &adap->sge;
732 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, msi_index = 2;
734 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
735 adap->msix_info[1].desc, &s->fw_evtq);
739 for_each_ethrxq(s, ethqidx) {
740 err = request_irq(adap->msix_info[msi_index].vec,
742 adap->msix_info[msi_index].desc,
743 &s->ethrxq[ethqidx].rspq);
748 for_each_ofldrxq(s, ofldqidx) {
749 err = request_irq(adap->msix_info[msi_index].vec,
751 adap->msix_info[msi_index].desc,
752 &s->ofldrxq[ofldqidx].rspq);
757 for_each_rdmarxq(s, rdmaqidx) {
758 err = request_irq(adap->msix_info[msi_index].vec,
760 adap->msix_info[msi_index].desc,
761 &s->rdmarxq[rdmaqidx].rspq);
769 while (--rdmaqidx >= 0)
770 free_irq(adap->msix_info[--msi_index].vec,
771 &s->rdmarxq[rdmaqidx].rspq);
772 while (--ofldqidx >= 0)
773 free_irq(adap->msix_info[--msi_index].vec,
774 &s->ofldrxq[ofldqidx].rspq);
775 while (--ethqidx >= 0)
776 free_irq(adap->msix_info[--msi_index].vec,
777 &s->ethrxq[ethqidx].rspq);
778 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
782 static void free_msix_queue_irqs(struct adapter *adap)
784 int i, msi_index = 2;
785 struct sge *s = &adap->sge;
787 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
788 for_each_ethrxq(s, i)
789 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
790 for_each_ofldrxq(s, i)
791 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
792 for_each_rdmarxq(s, i)
793 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
797 * write_rss - write the RSS table for a given port
799 * @queues: array of queue indices for RSS
801 * Sets up the portion of the HW RSS table for the port's VI to distribute
802 * packets to the Rx queues in @queues.
804 static int write_rss(const struct port_info *pi, const u16 *queues)
808 const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
810 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
814 /* map the queue indices to queue ids */
815 for (i = 0; i < pi->rss_size; i++, queues++)
816 rss[i] = q[*queues].rspq.abs_id;
818 err = t4_config_rss_range(pi->adapter, pi->adapter->fn, pi->viid, 0,
819 pi->rss_size, rss, pi->rss_size);
825 * setup_rss - configure RSS
828 * Sets up RSS for each port.
830 static int setup_rss(struct adapter *adap)
834 for_each_port(adap, i) {
835 const struct port_info *pi = adap2pinfo(adap, i);
837 err = write_rss(pi, pi->rss);
845 * Return the channel of the ingress queue with the given qid.
847 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
849 qid -= p->ingr_start;
850 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
854 * Wait until all NAPI handlers are descheduled.
856 static void quiesce_rx(struct adapter *adap)
860 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
861 struct sge_rspq *q = adap->sge.ingr_map[i];
864 napi_disable(&q->napi);
869 * Enable NAPI scheduling and interrupt generation for all Rx queues.
871 static void enable_rx(struct adapter *adap)
875 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
876 struct sge_rspq *q = adap->sge.ingr_map[i];
881 napi_enable(&q->napi);
882 /* 0-increment GTS to start the timer and enable interrupts */
883 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
884 SEINTARM(q->intr_params) |
885 INGRESSQID(q->cntxt_id));
890 * setup_sge_queues - configure SGE Tx/Rx/response queues
893 * Determines how many sets of SGE queues to use and initializes them.
894 * We support multiple queue sets per port if we have MSI-X, otherwise
895 * just one queue set per port.
897 static int setup_sge_queues(struct adapter *adap)
899 int err, msi_idx, i, j;
900 struct sge *s = &adap->sge;
902 bitmap_zero(s->starving_fl, MAX_EGRQ);
903 bitmap_zero(s->txq_maperr, MAX_EGRQ);
905 if (adap->flags & USING_MSIX)
906 msi_idx = 1; /* vector 0 is for non-queue interrupts */
908 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
912 msi_idx = -((int)s->intrq.abs_id + 1);
915 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
916 msi_idx, NULL, fwevtq_handler);
918 freeout: t4_free_sge_resources(adap);
922 for_each_port(adap, i) {
923 struct net_device *dev = adap->port[i];
924 struct port_info *pi = netdev_priv(dev);
925 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
926 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
928 for (j = 0; j < pi->nqsets; j++, q++) {
931 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
937 memset(&q->stats, 0, sizeof(q->stats));
939 for (j = 0; j < pi->nqsets; j++, t++) {
940 err = t4_sge_alloc_eth_txq(adap, t, dev,
941 netdev_get_tx_queue(dev, j),
942 s->fw_evtq.cntxt_id);
948 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
949 for_each_ofldrxq(s, i) {
950 struct sge_ofld_rxq *q = &s->ofldrxq[i];
951 struct net_device *dev = adap->port[i / j];
955 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, msi_idx,
956 &q->fl, uldrx_handler);
959 memset(&q->stats, 0, sizeof(q->stats));
960 s->ofld_rxq[i] = q->rspq.abs_id;
961 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], dev,
962 s->fw_evtq.cntxt_id);
967 for_each_rdmarxq(s, i) {
968 struct sge_ofld_rxq *q = &s->rdmarxq[i];
972 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
973 msi_idx, &q->fl, uldrx_handler);
976 memset(&q->stats, 0, sizeof(q->stats));
977 s->rdma_rxq[i] = q->rspq.abs_id;
980 for_each_port(adap, i) {
982 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
983 * have RDMA queues, and that's the right value.
985 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
987 s->rdmarxq[i].rspq.cntxt_id);
992 t4_write_reg(adap, MPS_TRC_RSS_CONTROL,
993 RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
994 QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
999 * Returns 0 if new FW was successfully loaded, a positive errno if a load was
1000 * started but failed, and a negative errno if flash load couldn't start.
1002 static int upgrade_fw(struct adapter *adap)
1006 const struct fw_hdr *hdr;
1007 const struct firmware *fw;
1008 struct device *dev = adap->pdev_dev;
1010 ret = request_firmware(&fw, FW_FNAME, dev);
1012 dev_err(dev, "unable to load firmware image " FW_FNAME
1013 ", error %d\n", ret);
1017 hdr = (const struct fw_hdr *)fw->data;
1018 vers = ntohl(hdr->fw_ver);
1019 if (FW_HDR_FW_VER_MAJOR_GET(vers) != FW_VERSION_MAJOR) {
1020 ret = -EINVAL; /* wrong major version, won't do */
1025 * If the flash FW is unusable or we found something newer, load it.
1027 if (FW_HDR_FW_VER_MAJOR_GET(adap->params.fw_vers) != FW_VERSION_MAJOR ||
1028 vers > adap->params.fw_vers) {
1029 dev_info(dev, "upgrading firmware ...\n");
1030 ret = t4_fw_upgrade(adap, adap->mbox, fw->data, fw->size,
1033 dev_info(dev, "firmware successfully upgraded to "
1034 FW_FNAME " (%d.%d.%d.%d)\n",
1035 FW_HDR_FW_VER_MAJOR_GET(vers),
1036 FW_HDR_FW_VER_MINOR_GET(vers),
1037 FW_HDR_FW_VER_MICRO_GET(vers),
1038 FW_HDR_FW_VER_BUILD_GET(vers));
1040 dev_err(dev, "firmware upgrade failed! err=%d\n", -ret);
1043 * Tell our caller that we didn't upgrade the firmware.
1048 out: release_firmware(fw);
1053 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1054 * The allocated memory is cleared.
1056 void *t4_alloc_mem(size_t size)
1058 void *p = kzalloc(size, GFP_KERNEL);
1066 * Free memory allocated through alloc_mem().
1068 static void t4_free_mem(void *addr)
1070 if (is_vmalloc_addr(addr))
1076 /* Send a Work Request to write the filter at a specified index. We construct
1077 * a Firmware Filter Work Request to have the work done and put the indicated
1078 * filter into "pending" mode which will prevent any further actions against
1079 * it till we get a reply from the firmware on the completion status of the
1082 static int set_filter_wr(struct adapter *adapter, int fidx)
1084 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1085 struct sk_buff *skb;
1086 struct fw_filter_wr *fwr;
1089 /* If the new filter requires loopback Destination MAC and/or VLAN
1090 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1093 if (f->fs.newdmac || f->fs.newvlan) {
1094 /* allocate L2T entry for new filter */
1095 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1098 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1099 f->fs.eport, f->fs.dmac)) {
1100 cxgb4_l2t_release(f->l2t);
1106 ftid = adapter->tids.ftid_base + fidx;
1108 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL | __GFP_NOFAIL);
1109 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1110 memset(fwr, 0, sizeof(*fwr));
1112 /* It would be nice to put most of the following in t4_hw.c but most
1113 * of the work is translating the cxgbtool ch_filter_specification
1114 * into the Work Request and the definition of that structure is
1115 * currently in cxgbtool.h which isn't appropriate to pull into the
1116 * common code. We may eventually try to come up with a more neutral
1117 * filter specification structure but for now it's easiest to simply
1118 * put this fairly direct code in line ...
1120 fwr->op_pkd = htonl(FW_WR_OP(FW_FILTER_WR));
1121 fwr->len16_pkd = htonl(FW_WR_LEN16(sizeof(*fwr)/16));
1123 htonl(V_FW_FILTER_WR_TID(ftid) |
1124 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
1125 V_FW_FILTER_WR_NOREPLY(0) |
1126 V_FW_FILTER_WR_IQ(f->fs.iq));
1127 fwr->del_filter_to_l2tix =
1128 htonl(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
1129 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
1130 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
1131 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
1132 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
1133 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
1134 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
1135 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
1136 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
1137 f->fs.newvlan == VLAN_REWRITE) |
1138 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
1139 f->fs.newvlan == VLAN_REWRITE) |
1140 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
1141 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
1142 V_FW_FILTER_WR_PRIO(f->fs.prio) |
1143 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
1144 fwr->ethtype = htons(f->fs.val.ethtype);
1145 fwr->ethtypem = htons(f->fs.mask.ethtype);
1146 fwr->frag_to_ovlan_vldm =
1147 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
1148 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
1149 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
1150 V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
1151 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
1152 V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
1154 fwr->rx_chan_rx_rpl_iq =
1155 htons(V_FW_FILTER_WR_RX_CHAN(0) |
1156 V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id));
1157 fwr->maci_to_matchtypem =
1158 htonl(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
1159 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
1160 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
1161 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
1162 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
1163 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
1164 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
1165 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
1166 fwr->ptcl = f->fs.val.proto;
1167 fwr->ptclm = f->fs.mask.proto;
1168 fwr->ttyp = f->fs.val.tos;
1169 fwr->ttypm = f->fs.mask.tos;
1170 fwr->ivlan = htons(f->fs.val.ivlan);
1171 fwr->ivlanm = htons(f->fs.mask.ivlan);
1172 fwr->ovlan = htons(f->fs.val.ovlan);
1173 fwr->ovlanm = htons(f->fs.mask.ovlan);
1174 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1175 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1176 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1177 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1178 fwr->lp = htons(f->fs.val.lport);
1179 fwr->lpm = htons(f->fs.mask.lport);
1180 fwr->fp = htons(f->fs.val.fport);
1181 fwr->fpm = htons(f->fs.mask.fport);
1183 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1185 /* Mark the filter as "pending" and ship off the Filter Work Request.
1186 * When we get the Work Request Reply we'll clear the pending status.
1189 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1190 t4_ofld_send(adapter, skb);
1194 /* Delete the filter at a specified index.
1196 static int del_filter_wr(struct adapter *adapter, int fidx)
1198 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1199 struct sk_buff *skb;
1200 struct fw_filter_wr *fwr;
1201 unsigned int len, ftid;
1204 ftid = adapter->tids.ftid_base + fidx;
1206 skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL);
1207 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1208 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1210 /* Mark the filter as "pending" and ship off the Filter Work Request.
1211 * When we get the Work Request Reply we'll clear the pending status.
1214 t4_mgmt_tx(adapter, skb);
1218 static inline int is_offload(const struct adapter *adap)
1220 return adap->params.offload;
1224 * Implementation of ethtool operations.
1227 static u32 get_msglevel(struct net_device *dev)
1229 return netdev2adap(dev)->msg_enable;
1232 static void set_msglevel(struct net_device *dev, u32 val)
1234 netdev2adap(dev)->msg_enable = val;
1237 static char stats_strings[][ETH_GSTRING_LEN] = {
1240 "TxBroadcastFrames ",
1241 "TxMulticastFrames ",
1247 "TxFrames128To255 ",
1248 "TxFrames256To511 ",
1249 "TxFrames512To1023 ",
1250 "TxFrames1024To1518 ",
1251 "TxFrames1519ToMax ",
1266 "RxBroadcastFrames ",
1267 "RxMulticastFrames ",
1279 "RxFrames128To255 ",
1280 "RxFrames256To511 ",
1281 "RxFrames512To1023 ",
1282 "RxFrames1024To1518 ",
1283 "RxFrames1519ToMax ",
1295 "RxBG0FramesDropped ",
1296 "RxBG1FramesDropped ",
1297 "RxBG2FramesDropped ",
1298 "RxBG3FramesDropped ",
1299 "RxBG0FramesTrunc ",
1300 "RxBG1FramesTrunc ",
1301 "RxBG2FramesTrunc ",
1302 "RxBG3FramesTrunc ",
1313 static int get_sset_count(struct net_device *dev, int sset)
1317 return ARRAY_SIZE(stats_strings);
1323 #define T4_REGMAP_SIZE (160 * 1024)
1325 static int get_regs_len(struct net_device *dev)
1327 return T4_REGMAP_SIZE;
1330 static int get_eeprom_len(struct net_device *dev)
1335 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1337 struct adapter *adapter = netdev2adap(dev);
1339 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1340 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1341 strlcpy(info->bus_info, pci_name(adapter->pdev),
1342 sizeof(info->bus_info));
1344 if (adapter->params.fw_vers)
1345 snprintf(info->fw_version, sizeof(info->fw_version),
1346 "%u.%u.%u.%u, TP %u.%u.%u.%u",
1347 FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers),
1348 FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers),
1349 FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers),
1350 FW_HDR_FW_VER_BUILD_GET(adapter->params.fw_vers),
1351 FW_HDR_FW_VER_MAJOR_GET(adapter->params.tp_vers),
1352 FW_HDR_FW_VER_MINOR_GET(adapter->params.tp_vers),
1353 FW_HDR_FW_VER_MICRO_GET(adapter->params.tp_vers),
1354 FW_HDR_FW_VER_BUILD_GET(adapter->params.tp_vers));
1357 static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
1359 if (stringset == ETH_SS_STATS)
1360 memcpy(data, stats_strings, sizeof(stats_strings));
1364 * port stats maintained per queue of the port. They should be in the same
1365 * order as in stats_strings above.
1367 struct queue_port_stats {
1377 static void collect_sge_port_stats(const struct adapter *adap,
1378 const struct port_info *p, struct queue_port_stats *s)
1381 const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
1382 const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
1384 memset(s, 0, sizeof(*s));
1385 for (i = 0; i < p->nqsets; i++, rx++, tx++) {
1387 s->tx_csum += tx->tx_cso;
1388 s->rx_csum += rx->stats.rx_cso;
1389 s->vlan_ex += rx->stats.vlan_ex;
1390 s->vlan_ins += tx->vlan_ins;
1391 s->gro_pkts += rx->stats.lro_pkts;
1392 s->gro_merged += rx->stats.lro_merged;
1396 static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1399 struct port_info *pi = netdev_priv(dev);
1400 struct adapter *adapter = pi->adapter;
1402 t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data);
1404 data += sizeof(struct port_stats) / sizeof(u64);
1405 collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
1409 * Return a version number to identify the type of adapter. The scheme is:
1410 * - bits 0..9: chip version
1411 * - bits 10..15: chip revision
1412 * - bits 16..23: register dump version
1414 static inline unsigned int mk_adap_vers(const struct adapter *ap)
1416 return 4 | (ap->params.rev << 10) | (1 << 16);
1419 static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
1422 u32 *p = buf + start;
1424 for ( ; start <= end; start += sizeof(u32))
1425 *p++ = t4_read_reg(ap, start);
1428 static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1431 static const unsigned int reg_ranges[] = {
1652 struct adapter *ap = netdev2adap(dev);
1654 regs->version = mk_adap_vers(ap);
1656 memset(buf, 0, T4_REGMAP_SIZE);
1657 for (i = 0; i < ARRAY_SIZE(reg_ranges); i += 2)
1658 reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]);
1661 static int restart_autoneg(struct net_device *dev)
1663 struct port_info *p = netdev_priv(dev);
1665 if (!netif_running(dev))
1667 if (p->link_cfg.autoneg != AUTONEG_ENABLE)
1669 t4_restart_aneg(p->adapter, p->adapter->fn, p->tx_chan);
1673 static int identify_port(struct net_device *dev,
1674 enum ethtool_phys_id_state state)
1677 struct adapter *adap = netdev2adap(dev);
1679 if (state == ETHTOOL_ID_ACTIVE)
1681 else if (state == ETHTOOL_ID_INACTIVE)
1686 return t4_identify_port(adap, adap->fn, netdev2pinfo(dev)->viid, val);
1689 static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
1693 if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XFI ||
1694 type == FW_PORT_TYPE_BT_XAUI) {
1696 if (caps & FW_PORT_CAP_SPEED_100M)
1697 v |= SUPPORTED_100baseT_Full;
1698 if (caps & FW_PORT_CAP_SPEED_1G)
1699 v |= SUPPORTED_1000baseT_Full;
1700 if (caps & FW_PORT_CAP_SPEED_10G)
1701 v |= SUPPORTED_10000baseT_Full;
1702 } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
1703 v |= SUPPORTED_Backplane;
1704 if (caps & FW_PORT_CAP_SPEED_1G)
1705 v |= SUPPORTED_1000baseKX_Full;
1706 if (caps & FW_PORT_CAP_SPEED_10G)
1707 v |= SUPPORTED_10000baseKX4_Full;
1708 } else if (type == FW_PORT_TYPE_KR)
1709 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
1710 else if (type == FW_PORT_TYPE_BP_AP)
1711 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
1712 SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full;
1713 else if (type == FW_PORT_TYPE_BP4_AP)
1714 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
1715 SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full |
1716 SUPPORTED_10000baseKX4_Full;
1717 else if (type == FW_PORT_TYPE_FIBER_XFI ||
1718 type == FW_PORT_TYPE_FIBER_XAUI || type == FW_PORT_TYPE_SFP)
1719 v |= SUPPORTED_FIBRE;
1721 if (caps & FW_PORT_CAP_ANEG)
1722 v |= SUPPORTED_Autoneg;
1726 static unsigned int to_fw_linkcaps(unsigned int caps)
1730 if (caps & ADVERTISED_100baseT_Full)
1731 v |= FW_PORT_CAP_SPEED_100M;
1732 if (caps & ADVERTISED_1000baseT_Full)
1733 v |= FW_PORT_CAP_SPEED_1G;
1734 if (caps & ADVERTISED_10000baseT_Full)
1735 v |= FW_PORT_CAP_SPEED_10G;
1739 static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1741 const struct port_info *p = netdev_priv(dev);
1743 if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
1744 p->port_type == FW_PORT_TYPE_BT_XFI ||
1745 p->port_type == FW_PORT_TYPE_BT_XAUI)
1746 cmd->port = PORT_TP;
1747 else if (p->port_type == FW_PORT_TYPE_FIBER_XFI ||
1748 p->port_type == FW_PORT_TYPE_FIBER_XAUI)
1749 cmd->port = PORT_FIBRE;
1750 else if (p->port_type == FW_PORT_TYPE_SFP) {
1751 if (p->mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
1752 p->mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
1753 cmd->port = PORT_DA;
1755 cmd->port = PORT_FIBRE;
1757 cmd->port = PORT_OTHER;
1759 if (p->mdio_addr >= 0) {
1760 cmd->phy_address = p->mdio_addr;
1761 cmd->transceiver = XCVR_EXTERNAL;
1762 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
1763 MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
1765 cmd->phy_address = 0; /* not really, but no better option */
1766 cmd->transceiver = XCVR_INTERNAL;
1767 cmd->mdio_support = 0;
1770 cmd->supported = from_fw_linkcaps(p->port_type, p->link_cfg.supported);
1771 cmd->advertising = from_fw_linkcaps(p->port_type,
1772 p->link_cfg.advertising);
1773 ethtool_cmd_speed_set(cmd,
1774 netif_carrier_ok(dev) ? p->link_cfg.speed : 0);
1775 cmd->duplex = DUPLEX_FULL;
1776 cmd->autoneg = p->link_cfg.autoneg;
1782 static unsigned int speed_to_caps(int speed)
1784 if (speed == SPEED_100)
1785 return FW_PORT_CAP_SPEED_100M;
1786 if (speed == SPEED_1000)
1787 return FW_PORT_CAP_SPEED_1G;
1788 if (speed == SPEED_10000)
1789 return FW_PORT_CAP_SPEED_10G;
1793 static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1796 struct port_info *p = netdev_priv(dev);
1797 struct link_config *lc = &p->link_cfg;
1798 u32 speed = ethtool_cmd_speed(cmd);
1800 if (cmd->duplex != DUPLEX_FULL) /* only full-duplex supported */
1803 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
1805 * PHY offers a single speed. See if that's what's
1808 if (cmd->autoneg == AUTONEG_DISABLE &&
1809 (lc->supported & speed_to_caps(speed)))
1814 if (cmd->autoneg == AUTONEG_DISABLE) {
1815 cap = speed_to_caps(speed);
1817 if (!(lc->supported & cap) || (speed == SPEED_1000) ||
1818 (speed == SPEED_10000))
1820 lc->requested_speed = cap;
1821 lc->advertising = 0;
1823 cap = to_fw_linkcaps(cmd->advertising);
1824 if (!(lc->supported & cap))
1826 lc->requested_speed = 0;
1827 lc->advertising = cap | FW_PORT_CAP_ANEG;
1829 lc->autoneg = cmd->autoneg;
1831 if (netif_running(dev))
1832 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
1837 static void get_pauseparam(struct net_device *dev,
1838 struct ethtool_pauseparam *epause)
1840 struct port_info *p = netdev_priv(dev);
1842 epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
1843 epause->rx_pause = (p->link_cfg.fc & PAUSE_RX) != 0;
1844 epause->tx_pause = (p->link_cfg.fc & PAUSE_TX) != 0;
1847 static int set_pauseparam(struct net_device *dev,
1848 struct ethtool_pauseparam *epause)
1850 struct port_info *p = netdev_priv(dev);
1851 struct link_config *lc = &p->link_cfg;
1853 if (epause->autoneg == AUTONEG_DISABLE)
1854 lc->requested_fc = 0;
1855 else if (lc->supported & FW_PORT_CAP_ANEG)
1856 lc->requested_fc = PAUSE_AUTONEG;
1860 if (epause->rx_pause)
1861 lc->requested_fc |= PAUSE_RX;
1862 if (epause->tx_pause)
1863 lc->requested_fc |= PAUSE_TX;
1864 if (netif_running(dev))
1865 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
1870 static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1872 const struct port_info *pi = netdev_priv(dev);
1873 const struct sge *s = &pi->adapter->sge;
1875 e->rx_max_pending = MAX_RX_BUFFERS;
1876 e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
1877 e->rx_jumbo_max_pending = 0;
1878 e->tx_max_pending = MAX_TXQ_ENTRIES;
1880 e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
1881 e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
1882 e->rx_jumbo_pending = 0;
1883 e->tx_pending = s->ethtxq[pi->first_qset].q.size;
1886 static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1889 const struct port_info *pi = netdev_priv(dev);
1890 struct adapter *adapter = pi->adapter;
1891 struct sge *s = &adapter->sge;
1893 if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
1894 e->tx_pending > MAX_TXQ_ENTRIES ||
1895 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
1896 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
1897 e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
1900 if (adapter->flags & FULL_INIT_DONE)
1903 for (i = 0; i < pi->nqsets; ++i) {
1904 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
1905 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
1906 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
1911 static int closest_timer(const struct sge *s, int time)
1913 int i, delta, match = 0, min_delta = INT_MAX;
1915 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1916 delta = time - s->timer_val[i];
1919 if (delta < min_delta) {
1927 static int closest_thres(const struct sge *s, int thres)
1929 int i, delta, match = 0, min_delta = INT_MAX;
1931 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1932 delta = thres - s->counter_val[i];
1935 if (delta < min_delta) {
1944 * Return a queue's interrupt hold-off time in us. 0 means no timer.
1946 static unsigned int qtimer_val(const struct adapter *adap,
1947 const struct sge_rspq *q)
1949 unsigned int idx = q->intr_params >> 1;
1951 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1955 * set_rxq_intr_params - set a queue's interrupt holdoff parameters
1956 * @adap: the adapter
1958 * @us: the hold-off time in us, or 0 to disable timer
1959 * @cnt: the hold-off packet count, or 0 to disable counter
1961 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1962 * one of the two needs to be enabled for the queue to generate interrupts.
1964 static int set_rxq_intr_params(struct adapter *adap, struct sge_rspq *q,
1965 unsigned int us, unsigned int cnt)
1967 if ((us | cnt) == 0)
1974 new_idx = closest_thres(&adap->sge, cnt);
1975 if (q->desc && q->pktcnt_idx != new_idx) {
1976 /* the queue has already been created, update it */
1977 v = FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
1978 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1979 FW_PARAMS_PARAM_YZ(q->cntxt_id);
1980 err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
1985 q->pktcnt_idx = new_idx;
1988 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1989 q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
1993 static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1995 const struct port_info *pi = netdev_priv(dev);
1996 struct adapter *adap = pi->adapter;
2001 for (i = pi->first_qset; i < pi->first_qset + pi->nqsets; i++) {
2002 q = &adap->sge.ethrxq[i].rspq;
2003 r = set_rxq_intr_params(adap, q, c->rx_coalesce_usecs,
2004 c->rx_max_coalesced_frames);
2006 dev_err(&dev->dev, "failed to set coalesce %d\n", r);
2013 static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2015 const struct port_info *pi = netdev_priv(dev);
2016 const struct adapter *adap = pi->adapter;
2017 const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
2019 c->rx_coalesce_usecs = qtimer_val(adap, rq);
2020 c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN) ?
2021 adap->sge.counter_val[rq->pktcnt_idx] : 0;
2026 * eeprom_ptov - translate a physical EEPROM address to virtual
2027 * @phys_addr: the physical EEPROM address
2028 * @fn: the PCI function number
2029 * @sz: size of function-specific area
2031 * Translate a physical EEPROM address to virtual. The first 1K is
2032 * accessed through virtual addresses starting at 31K, the rest is
2033 * accessed through virtual addresses starting at 0.
2035 * The mapping is as follows:
2036 * [0..1K) -> [31K..32K)
2037 * [1K..1K+A) -> [31K-A..31K)
2038 * [1K+A..ES) -> [0..ES-A-1K)
2040 * where A = @fn * @sz, and ES = EEPROM size.
2042 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2045 if (phys_addr < 1024)
2046 return phys_addr + (31 << 10);
2047 if (phys_addr < 1024 + fn)
2048 return 31744 - fn + phys_addr - 1024;
2049 if (phys_addr < EEPROMSIZE)
2050 return phys_addr - 1024 - fn;
2055 * The next two routines implement eeprom read/write from physical addresses.
2057 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
2059 int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2062 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
2063 return vaddr < 0 ? vaddr : 0;
2066 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
2068 int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2071 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
2072 return vaddr < 0 ? vaddr : 0;
2075 #define EEPROM_MAGIC 0x38E2F10C
2077 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2081 struct adapter *adapter = netdev2adap(dev);
2083 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2087 e->magic = EEPROM_MAGIC;
2088 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
2089 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
2092 memcpy(data, buf + e->offset, e->len);
2097 static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2102 u32 aligned_offset, aligned_len, *p;
2103 struct adapter *adapter = netdev2adap(dev);
2105 if (eeprom->magic != EEPROM_MAGIC)
2108 aligned_offset = eeprom->offset & ~3;
2109 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2111 if (adapter->fn > 0) {
2112 u32 start = 1024 + adapter->fn * EEPROMPFSIZE;
2114 if (aligned_offset < start ||
2115 aligned_offset + aligned_len > start + EEPROMPFSIZE)
2119 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2121 * RMW possibly needed for first or last words.
2123 buf = kmalloc(aligned_len, GFP_KERNEL);
2126 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
2127 if (!err && aligned_len > 4)
2128 err = eeprom_rd_phys(adapter,
2129 aligned_offset + aligned_len - 4,
2130 (u32 *)&buf[aligned_len - 4]);
2133 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2137 err = t4_seeprom_wp(adapter, false);
2141 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
2142 err = eeprom_wr_phys(adapter, aligned_offset, *p);
2143 aligned_offset += 4;
2147 err = t4_seeprom_wp(adapter, true);
2154 static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
2157 const struct firmware *fw;
2158 struct adapter *adap = netdev2adap(netdev);
2160 ef->data[sizeof(ef->data) - 1] = '\0';
2161 ret = request_firmware(&fw, ef->data, adap->pdev_dev);
2165 ret = t4_load_fw(adap, fw->data, fw->size);
2166 release_firmware(fw);
2168 dev_info(adap->pdev_dev, "loaded firmware %s\n", ef->data);
2172 #define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
2173 #define BCAST_CRC 0xa0ccc1a6
2175 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2177 wol->supported = WAKE_BCAST | WAKE_MAGIC;
2178 wol->wolopts = netdev2adap(dev)->wol;
2179 memset(&wol->sopass, 0, sizeof(wol->sopass));
2182 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2185 struct port_info *pi = netdev_priv(dev);
2187 if (wol->wolopts & ~WOL_SUPPORTED)
2189 t4_wol_magic_enable(pi->adapter, pi->tx_chan,
2190 (wol->wolopts & WAKE_MAGIC) ? dev->dev_addr : NULL);
2191 if (wol->wolopts & WAKE_BCAST) {
2192 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0xfe, ~0ULL,
2195 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 1,
2196 ~6ULL, ~0ULL, BCAST_CRC, true);
2198 t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0, 0, 0, 0, false);
2202 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
2204 const struct port_info *pi = netdev_priv(dev);
2205 netdev_features_t changed = dev->features ^ features;
2208 if (!(changed & NETIF_F_HW_VLAN_RX))
2211 err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
2213 !!(features & NETIF_F_HW_VLAN_RX), true);
2215 dev->features = features ^ NETIF_F_HW_VLAN_RX;
2219 static u32 get_rss_table_size(struct net_device *dev)
2221 const struct port_info *pi = netdev_priv(dev);
2223 return pi->rss_size;
2226 static int get_rss_table(struct net_device *dev, u32 *p)
2228 const struct port_info *pi = netdev_priv(dev);
2229 unsigned int n = pi->rss_size;
2236 static int set_rss_table(struct net_device *dev, const u32 *p)
2239 struct port_info *pi = netdev_priv(dev);
2241 for (i = 0; i < pi->rss_size; i++)
2243 if (pi->adapter->flags & FULL_INIT_DONE)
2244 return write_rss(pi, pi->rss);
2248 static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2251 const struct port_info *pi = netdev_priv(dev);
2253 switch (info->cmd) {
2254 case ETHTOOL_GRXFH: {
2255 unsigned int v = pi->rss_mode;
2258 switch (info->flow_type) {
2260 if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2261 info->data = RXH_IP_SRC | RXH_IP_DST |
2262 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2263 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2264 info->data = RXH_IP_SRC | RXH_IP_DST;
2267 if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) &&
2268 (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
2269 info->data = RXH_IP_SRC | RXH_IP_DST |
2270 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2271 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2272 info->data = RXH_IP_SRC | RXH_IP_DST;
2275 case AH_ESP_V4_FLOW:
2277 if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2278 info->data = RXH_IP_SRC | RXH_IP_DST;
2281 if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2282 info->data = RXH_IP_SRC | RXH_IP_DST |
2283 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2284 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2285 info->data = RXH_IP_SRC | RXH_IP_DST;
2288 if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) &&
2289 (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
2290 info->data = RXH_IP_SRC | RXH_IP_DST |
2291 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2292 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2293 info->data = RXH_IP_SRC | RXH_IP_DST;
2296 case AH_ESP_V6_FLOW:
2298 if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2299 info->data = RXH_IP_SRC | RXH_IP_DST;
2304 case ETHTOOL_GRXRINGS:
2305 info->data = pi->nqsets;
2311 static const struct ethtool_ops cxgb_ethtool_ops = {
2312 .get_settings = get_settings,
2313 .set_settings = set_settings,
2314 .get_drvinfo = get_drvinfo,
2315 .get_msglevel = get_msglevel,
2316 .set_msglevel = set_msglevel,
2317 .get_ringparam = get_sge_param,
2318 .set_ringparam = set_sge_param,
2319 .get_coalesce = get_coalesce,
2320 .set_coalesce = set_coalesce,
2321 .get_eeprom_len = get_eeprom_len,
2322 .get_eeprom = get_eeprom,
2323 .set_eeprom = set_eeprom,
2324 .get_pauseparam = get_pauseparam,
2325 .set_pauseparam = set_pauseparam,
2326 .get_link = ethtool_op_get_link,
2327 .get_strings = get_strings,
2328 .set_phys_id = identify_port,
2329 .nway_reset = restart_autoneg,
2330 .get_sset_count = get_sset_count,
2331 .get_ethtool_stats = get_stats,
2332 .get_regs_len = get_regs_len,
2333 .get_regs = get_regs,
2336 .get_rxnfc = get_rxnfc,
2337 .get_rxfh_indir_size = get_rss_table_size,
2338 .get_rxfh_indir = get_rss_table,
2339 .set_rxfh_indir = set_rss_table,
2340 .flash_device = set_flash,
2346 static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
2350 loff_t avail = file_inode(file)->i_size;
2351 unsigned int mem = (uintptr_t)file->private_data & 3;
2352 struct adapter *adap = file->private_data - mem;
2358 if (count > avail - pos)
2359 count = avail - pos;
2367 ret = t4_mc_read(adap, pos, data, NULL);
2369 ret = t4_edc_read(adap, mem, pos, data, NULL);
2373 ofst = pos % sizeof(data);
2374 len = min(count, sizeof(data) - ofst);
2375 if (copy_to_user(buf, (u8 *)data + ofst, len))
2382 count = pos - *ppos;
2387 static const struct file_operations mem_debugfs_fops = {
2388 .owner = THIS_MODULE,
2389 .open = simple_open,
2391 .llseek = default_llseek,
2394 static void add_debugfs_mem(struct adapter *adap, const char *name,
2395 unsigned int idx, unsigned int size_mb)
2399 de = debugfs_create_file(name, S_IRUSR, adap->debugfs_root,
2400 (void *)adap + idx, &mem_debugfs_fops);
2401 if (de && de->d_inode)
2402 de->d_inode->i_size = size_mb << 20;
2405 static int setup_debugfs(struct adapter *adap)
2409 if (IS_ERR_OR_NULL(adap->debugfs_root))
2412 i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE);
2413 if (i & EDRAM0_ENABLE)
2414 add_debugfs_mem(adap, "edc0", MEM_EDC0, 5);
2415 if (i & EDRAM1_ENABLE)
2416 add_debugfs_mem(adap, "edc1", MEM_EDC1, 5);
2417 if (i & EXT_MEM_ENABLE)
2418 add_debugfs_mem(adap, "mc", MEM_MC,
2419 EXT_MEM_SIZE_GET(t4_read_reg(adap, MA_EXT_MEMORY_BAR)));
2421 debugfs_create_file("l2t", S_IRUSR, adap->debugfs_root, adap,
2427 * upper-layer driver support
2431 * Allocate an active-open TID and set it to the supplied value.
2433 int cxgb4_alloc_atid(struct tid_info *t, void *data)
2437 spin_lock_bh(&t->atid_lock);
2439 union aopen_entry *p = t->afree;
2441 atid = (p - t->atid_tab) + t->atid_base;
2446 spin_unlock_bh(&t->atid_lock);
2449 EXPORT_SYMBOL(cxgb4_alloc_atid);
2452 * Release an active-open TID.
2454 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
2456 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
2458 spin_lock_bh(&t->atid_lock);
2462 spin_unlock_bh(&t->atid_lock);
2464 EXPORT_SYMBOL(cxgb4_free_atid);
2467 * Allocate a server TID and set it to the supplied value.
2469 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
2473 spin_lock_bh(&t->stid_lock);
2474 if (family == PF_INET) {
2475 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
2476 if (stid < t->nstids)
2477 __set_bit(stid, t->stid_bmap);
2481 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
2486 t->stid_tab[stid].data = data;
2487 stid += t->stid_base;
2490 spin_unlock_bh(&t->stid_lock);
2493 EXPORT_SYMBOL(cxgb4_alloc_stid);
2495 /* Allocate a server filter TID and set it to the supplied value.
2497 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
2501 spin_lock_bh(&t->stid_lock);
2502 if (family == PF_INET) {
2503 stid = find_next_zero_bit(t->stid_bmap,
2504 t->nstids + t->nsftids, t->nstids);
2505 if (stid < (t->nstids + t->nsftids))
2506 __set_bit(stid, t->stid_bmap);
2513 t->stid_tab[stid].data = data;
2514 stid += t->stid_base;
2517 spin_unlock_bh(&t->stid_lock);
2520 EXPORT_SYMBOL(cxgb4_alloc_sftid);
2522 /* Release a server TID.
2524 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
2526 stid -= t->stid_base;
2527 spin_lock_bh(&t->stid_lock);
2528 if (family == PF_INET)
2529 __clear_bit(stid, t->stid_bmap);
2531 bitmap_release_region(t->stid_bmap, stid, 2);
2532 t->stid_tab[stid].data = NULL;
2534 spin_unlock_bh(&t->stid_lock);
2536 EXPORT_SYMBOL(cxgb4_free_stid);
2539 * Populate a TID_RELEASE WR. Caller must properly size the skb.
2541 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
2544 struct cpl_tid_release *req;
2546 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
2547 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
2548 INIT_TP_WR(req, tid);
2549 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
2553 * Queue a TID release request and if necessary schedule a work queue to
2556 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
2559 void **p = &t->tid_tab[tid];
2560 struct adapter *adap = container_of(t, struct adapter, tids);
2562 spin_lock_bh(&adap->tid_release_lock);
2563 *p = adap->tid_release_head;
2564 /* Low 2 bits encode the Tx channel number */
2565 adap->tid_release_head = (void **)((uintptr_t)p | chan);
2566 if (!adap->tid_release_task_busy) {
2567 adap->tid_release_task_busy = true;
2568 queue_work(workq, &adap->tid_release_task);
2570 spin_unlock_bh(&adap->tid_release_lock);
2574 * Process the list of pending TID release requests.
2576 static void process_tid_release_list(struct work_struct *work)
2578 struct sk_buff *skb;
2579 struct adapter *adap;
2581 adap = container_of(work, struct adapter, tid_release_task);
2583 spin_lock_bh(&adap->tid_release_lock);
2584 while (adap->tid_release_head) {
2585 void **p = adap->tid_release_head;
2586 unsigned int chan = (uintptr_t)p & 3;
2587 p = (void *)p - chan;
2589 adap->tid_release_head = *p;
2591 spin_unlock_bh(&adap->tid_release_lock);
2593 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
2595 schedule_timeout_uninterruptible(1);
2597 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
2598 t4_ofld_send(adap, skb);
2599 spin_lock_bh(&adap->tid_release_lock);
2601 adap->tid_release_task_busy = false;
2602 spin_unlock_bh(&adap->tid_release_lock);
2606 * Release a TID and inform HW. If we are unable to allocate the release
2607 * message we defer to a work queue.
2609 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
2612 struct sk_buff *skb;
2613 struct adapter *adap = container_of(t, struct adapter, tids);
2615 old = t->tid_tab[tid];
2616 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
2618 t->tid_tab[tid] = NULL;
2619 mk_tid_release(skb, chan, tid);
2620 t4_ofld_send(adap, skb);
2622 cxgb4_queue_tid_release(t, chan, tid);
2624 atomic_dec(&t->tids_in_use);
2626 EXPORT_SYMBOL(cxgb4_remove_tid);
2629 * Allocate and initialize the TID tables. Returns 0 on success.
2631 static int tid_init(struct tid_info *t)
2634 unsigned int stid_bmap_size;
2635 unsigned int natids = t->natids;
2637 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
2638 size = t->ntids * sizeof(*t->tid_tab) +
2639 natids * sizeof(*t->atid_tab) +
2640 t->nstids * sizeof(*t->stid_tab) +
2641 t->nsftids * sizeof(*t->stid_tab) +
2642 stid_bmap_size * sizeof(long) +
2643 t->nftids * sizeof(*t->ftid_tab) +
2644 t->nsftids * sizeof(*t->ftid_tab);
2646 t->tid_tab = t4_alloc_mem(size);
2650 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
2651 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
2652 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
2653 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
2654 spin_lock_init(&t->stid_lock);
2655 spin_lock_init(&t->atid_lock);
2657 t->stids_in_use = 0;
2659 t->atids_in_use = 0;
2660 atomic_set(&t->tids_in_use, 0);
2662 /* Setup the free list for atid_tab and clear the stid bitmap. */
2665 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
2666 t->afree = t->atid_tab;
2668 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
2673 * cxgb4_create_server - create an IP server
2675 * @stid: the server TID
2676 * @sip: local IP address to bind server to
2677 * @sport: the server's TCP port
2678 * @queue: queue to direct messages from this server to
2680 * Create an IP server for the given port and address.
2681 * Returns <0 on error and one of the %NET_XMIT_* values on success.
2683 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
2684 __be32 sip, __be16 sport, __be16 vlan,
2688 struct sk_buff *skb;
2689 struct adapter *adap;
2690 struct cpl_pass_open_req *req;
2692 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
2696 adap = netdev2adap(dev);
2697 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
2699 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
2700 req->local_port = sport;
2701 req->peer_port = htons(0);
2702 req->local_ip = sip;
2703 req->peer_ip = htonl(0);
2704 chan = rxq_to_chan(&adap->sge, queue);
2705 req->opt0 = cpu_to_be64(TX_CHAN(chan));
2706 req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
2707 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
2708 return t4_mgmt_tx(adap, skb);
2710 EXPORT_SYMBOL(cxgb4_create_server);
2713 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
2714 * @mtus: the HW MTU table
2715 * @mtu: the target MTU
2716 * @idx: index of selected entry in the MTU table
2718 * Returns the index and the value in the HW MTU table that is closest to
2719 * but does not exceed @mtu, unless @mtu is smaller than any value in the
2720 * table, in which case that smallest available value is selected.
2722 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
2727 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
2733 EXPORT_SYMBOL(cxgb4_best_mtu);
2736 * cxgb4_port_chan - get the HW channel of a port
2737 * @dev: the net device for the port
2739 * Return the HW Tx channel of the given port.
2741 unsigned int cxgb4_port_chan(const struct net_device *dev)
2743 return netdev2pinfo(dev)->tx_chan;
2745 EXPORT_SYMBOL(cxgb4_port_chan);
2747 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
2749 struct adapter *adap = netdev2adap(dev);
2752 v = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
2753 return lpfifo ? G_LP_COUNT(v) : G_HP_COUNT(v);
2755 EXPORT_SYMBOL(cxgb4_dbfifo_count);
2758 * cxgb4_port_viid - get the VI id of a port
2759 * @dev: the net device for the port
2761 * Return the VI id of the given port.
2763 unsigned int cxgb4_port_viid(const struct net_device *dev)
2765 return netdev2pinfo(dev)->viid;
2767 EXPORT_SYMBOL(cxgb4_port_viid);
2770 * cxgb4_port_idx - get the index of a port
2771 * @dev: the net device for the port
2773 * Return the index of the given port.
2775 unsigned int cxgb4_port_idx(const struct net_device *dev)
2777 return netdev2pinfo(dev)->port_id;
2779 EXPORT_SYMBOL(cxgb4_port_idx);
2781 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
2782 struct tp_tcp_stats *v6)
2784 struct adapter *adap = pci_get_drvdata(pdev);
2786 spin_lock(&adap->stats_lock);
2787 t4_tp_get_tcp_stats(adap, v4, v6);
2788 spin_unlock(&adap->stats_lock);
2790 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
2792 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
2793 const unsigned int *pgsz_order)
2795 struct adapter *adap = netdev2adap(dev);
2797 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask);
2798 t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) |
2799 HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) |
2800 HPZ3(pgsz_order[3]));
2802 EXPORT_SYMBOL(cxgb4_iscsi_init);
2804 int cxgb4_flush_eq_cache(struct net_device *dev)
2806 struct adapter *adap = netdev2adap(dev);
2809 ret = t4_fwaddrspace_write(adap, adap->mbox,
2810 0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
2813 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
2815 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
2817 u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
2821 ret = t4_mem_win_read_len(adap, addr, (__be32 *)&indices, 8);
2823 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
2824 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
2829 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
2832 struct adapter *adap = netdev2adap(dev);
2833 u16 hw_pidx, hw_cidx;
2836 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
2840 if (pidx != hw_pidx) {
2843 if (pidx >= hw_pidx)
2844 delta = pidx - hw_pidx;
2846 delta = size - hw_pidx + pidx;
2848 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
2849 QID(qid) | PIDX(delta));
2854 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
2856 static struct pci_driver cxgb4_driver;
2858 static void check_neigh_update(struct neighbour *neigh)
2860 const struct device *parent;
2861 const struct net_device *netdev = neigh->dev;
2863 if (netdev->priv_flags & IFF_802_1Q_VLAN)
2864 netdev = vlan_dev_real_dev(netdev);
2865 parent = netdev->dev.parent;
2866 if (parent && parent->driver == &cxgb4_driver.driver)
2867 t4_l2t_update(dev_get_drvdata(parent), neigh);
2870 static int netevent_cb(struct notifier_block *nb, unsigned long event,
2874 case NETEVENT_NEIGH_UPDATE:
2875 check_neigh_update(data);
2877 case NETEVENT_REDIRECT:
2884 static bool netevent_registered;
2885 static struct notifier_block cxgb4_netevent_nb = {
2886 .notifier_call = netevent_cb
2889 static void drain_db_fifo(struct adapter *adap, int usecs)
2894 set_current_state(TASK_UNINTERRUPTIBLE);
2895 schedule_timeout(usecs_to_jiffies(usecs));
2896 v = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
2897 if (G_LP_COUNT(v) == 0 && G_HP_COUNT(v) == 0)
2902 static void disable_txq_db(struct sge_txq *q)
2904 spin_lock_irq(&q->db_lock);
2906 spin_unlock_irq(&q->db_lock);
2909 static void enable_txq_db(struct sge_txq *q)
2911 spin_lock_irq(&q->db_lock);
2913 spin_unlock_irq(&q->db_lock);
2916 static void disable_dbs(struct adapter *adap)
2920 for_each_ethrxq(&adap->sge, i)
2921 disable_txq_db(&adap->sge.ethtxq[i].q);
2922 for_each_ofldrxq(&adap->sge, i)
2923 disable_txq_db(&adap->sge.ofldtxq[i].q);
2924 for_each_port(adap, i)
2925 disable_txq_db(&adap->sge.ctrlq[i].q);
2928 static void enable_dbs(struct adapter *adap)
2932 for_each_ethrxq(&adap->sge, i)
2933 enable_txq_db(&adap->sge.ethtxq[i].q);
2934 for_each_ofldrxq(&adap->sge, i)
2935 enable_txq_db(&adap->sge.ofldtxq[i].q);
2936 for_each_port(adap, i)
2937 enable_txq_db(&adap->sge.ctrlq[i].q);
2940 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2942 u16 hw_pidx, hw_cidx;
2945 spin_lock_bh(&q->db_lock);
2946 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2949 if (q->db_pidx != hw_pidx) {
2952 if (q->db_pidx >= hw_pidx)
2953 delta = q->db_pidx - hw_pidx;
2955 delta = q->size - hw_pidx + q->db_pidx;
2957 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
2958 QID(q->cntxt_id) | PIDX(delta));
2962 spin_unlock_bh(&q->db_lock);
2964 CH_WARN(adap, "DB drop recovery failed.\n");
2966 static void recover_all_queues(struct adapter *adap)
2970 for_each_ethrxq(&adap->sge, i)
2971 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2972 for_each_ofldrxq(&adap->sge, i)
2973 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
2974 for_each_port(adap, i)
2975 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2978 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2980 mutex_lock(&uld_mutex);
2981 if (adap->uld_handle[CXGB4_ULD_RDMA])
2982 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
2984 mutex_unlock(&uld_mutex);
2987 static void process_db_full(struct work_struct *work)
2989 struct adapter *adap;
2991 adap = container_of(work, struct adapter, db_full_task);
2993 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2994 drain_db_fifo(adap, dbfifo_drain_delay);
2995 t4_set_reg_field(adap, SGE_INT_ENABLE3,
2996 DBFIFO_HP_INT | DBFIFO_LP_INT,
2997 DBFIFO_HP_INT | DBFIFO_LP_INT);
2998 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3001 static void process_db_drop(struct work_struct *work)
3003 struct adapter *adap;
3005 adap = container_of(work, struct adapter, db_drop_task);
3007 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
3009 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
3010 drain_db_fifo(adap, 1);
3011 recover_all_queues(adap);
3015 void t4_db_full(struct adapter *adap)
3017 t4_set_reg_field(adap, SGE_INT_ENABLE3,
3018 DBFIFO_HP_INT | DBFIFO_LP_INT, 0);
3019 queue_work(workq, &adap->db_full_task);
3022 void t4_db_dropped(struct adapter *adap)
3024 queue_work(workq, &adap->db_drop_task);
3027 static void uld_attach(struct adapter *adap, unsigned int uld)
3030 struct cxgb4_lld_info lli;
3033 lli.pdev = adap->pdev;
3034 lli.l2t = adap->l2t;
3035 lli.tids = &adap->tids;
3036 lli.ports = adap->port;
3037 lli.vr = &adap->vres;
3038 lli.mtus = adap->params.mtus;
3039 if (uld == CXGB4_ULD_RDMA) {
3040 lli.rxq_ids = adap->sge.rdma_rxq;
3041 lli.nrxq = adap->sge.rdmaqs;
3042 } else if (uld == CXGB4_ULD_ISCSI) {
3043 lli.rxq_ids = adap->sge.ofld_rxq;
3044 lli.nrxq = adap->sge.ofldqsets;
3046 lli.ntxq = adap->sge.ofldqsets;
3047 lli.nchan = adap->params.nports;
3048 lli.nports = adap->params.nports;
3049 lli.wr_cred = adap->params.ofldq_wr_cred;
3050 lli.adapter_type = adap->params.rev;
3051 lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
3052 lli.udb_density = 1 << QUEUESPERPAGEPF0_GET(
3053 t4_read_reg(adap, SGE_EGRESS_QUEUES_PER_PAGE_PF) >>
3055 lli.ucq_density = 1 << QUEUESPERPAGEPF0_GET(
3056 t4_read_reg(adap, SGE_INGRESS_QUEUES_PER_PAGE_PF) >>
3058 lli.filt_mode = adap->filter_mode;
3059 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
3060 for (i = 0; i < NCHAN; i++)
3062 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
3063 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
3064 lli.fw_vers = adap->params.fw_vers;
3065 lli.dbfifo_int_thresh = dbfifo_int_thresh;
3066 lli.sge_pktshift = adap->sge.pktshift;
3067 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
3069 handle = ulds[uld].add(&lli);
3070 if (IS_ERR(handle)) {
3071 dev_warn(adap->pdev_dev,
3072 "could not attach to the %s driver, error %ld\n",
3073 uld_str[uld], PTR_ERR(handle));
3077 adap->uld_handle[uld] = handle;
3079 if (!netevent_registered) {
3080 register_netevent_notifier(&cxgb4_netevent_nb);
3081 netevent_registered = true;
3084 if (adap->flags & FULL_INIT_DONE)
3085 ulds[uld].state_change(handle, CXGB4_STATE_UP);
3088 static void attach_ulds(struct adapter *adap)
3092 mutex_lock(&uld_mutex);
3093 list_add_tail(&adap->list_node, &adapter_list);
3094 for (i = 0; i < CXGB4_ULD_MAX; i++)
3096 uld_attach(adap, i);
3097 mutex_unlock(&uld_mutex);
3100 static void detach_ulds(struct adapter *adap)
3104 mutex_lock(&uld_mutex);
3105 list_del(&adap->list_node);
3106 for (i = 0; i < CXGB4_ULD_MAX; i++)
3107 if (adap->uld_handle[i]) {
3108 ulds[i].state_change(adap->uld_handle[i],
3109 CXGB4_STATE_DETACH);
3110 adap->uld_handle[i] = NULL;
3112 if (netevent_registered && list_empty(&adapter_list)) {
3113 unregister_netevent_notifier(&cxgb4_netevent_nb);
3114 netevent_registered = false;
3116 mutex_unlock(&uld_mutex);
3119 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
3123 mutex_lock(&uld_mutex);
3124 for (i = 0; i < CXGB4_ULD_MAX; i++)
3125 if (adap->uld_handle[i])
3126 ulds[i].state_change(adap->uld_handle[i], new_state);
3127 mutex_unlock(&uld_mutex);
3131 * cxgb4_register_uld - register an upper-layer driver
3132 * @type: the ULD type
3133 * @p: the ULD methods
3135 * Registers an upper-layer driver with this driver and notifies the ULD
3136 * about any presently available devices that support its type. Returns
3137 * %-EBUSY if a ULD of the same type is already registered.
3139 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
3142 struct adapter *adap;
3144 if (type >= CXGB4_ULD_MAX)
3146 mutex_lock(&uld_mutex);
3147 if (ulds[type].add) {
3152 list_for_each_entry(adap, &adapter_list, list_node)
3153 uld_attach(adap, type);
3154 out: mutex_unlock(&uld_mutex);
3157 EXPORT_SYMBOL(cxgb4_register_uld);
3160 * cxgb4_unregister_uld - unregister an upper-layer driver
3161 * @type: the ULD type
3163 * Unregisters an existing upper-layer driver.
3165 int cxgb4_unregister_uld(enum cxgb4_uld type)
3167 struct adapter *adap;
3169 if (type >= CXGB4_ULD_MAX)
3171 mutex_lock(&uld_mutex);
3172 list_for_each_entry(adap, &adapter_list, list_node)
3173 adap->uld_handle[type] = NULL;
3174 ulds[type].add = NULL;
3175 mutex_unlock(&uld_mutex);
3178 EXPORT_SYMBOL(cxgb4_unregister_uld);
3181 * cxgb_up - enable the adapter
3182 * @adap: adapter being enabled
3184 * Called when the first port is enabled, this function performs the
3185 * actions necessary to make an adapter operational, such as completing
3186 * the initialization of HW modules, and enabling interrupts.
3188 * Must be called with the rtnl lock held.
3190 static int cxgb_up(struct adapter *adap)
3194 err = setup_sge_queues(adap);
3197 err = setup_rss(adap);
3201 if (adap->flags & USING_MSIX) {
3202 name_msix_vecs(adap);
3203 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
3204 adap->msix_info[0].desc, adap);
3208 err = request_msix_queue_irqs(adap);
3210 free_irq(adap->msix_info[0].vec, adap);
3214 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
3215 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
3216 adap->port[0]->name, adap);
3222 t4_intr_enable(adap);
3223 adap->flags |= FULL_INIT_DONE;
3224 notify_ulds(adap, CXGB4_STATE_UP);
3228 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
3230 t4_free_sge_resources(adap);
3234 static void cxgb_down(struct adapter *adapter)
3236 t4_intr_disable(adapter);
3237 cancel_work_sync(&adapter->tid_release_task);
3238 cancel_work_sync(&adapter->db_full_task);
3239 cancel_work_sync(&adapter->db_drop_task);
3240 adapter->tid_release_task_busy = false;
3241 adapter->tid_release_head = NULL;
3243 if (adapter->flags & USING_MSIX) {
3244 free_msix_queue_irqs(adapter);
3245 free_irq(adapter->msix_info[0].vec, adapter);
3247 free_irq(adapter->pdev->irq, adapter);
3248 quiesce_rx(adapter);
3249 t4_sge_stop(adapter);
3250 t4_free_sge_resources(adapter);
3251 adapter->flags &= ~FULL_INIT_DONE;
3255 * net_device operations
3257 static int cxgb_open(struct net_device *dev)
3260 struct port_info *pi = netdev_priv(dev);
3261 struct adapter *adapter = pi->adapter;
3263 netif_carrier_off(dev);
3265 if (!(adapter->flags & FULL_INIT_DONE)) {
3266 err = cxgb_up(adapter);
3271 err = link_start(dev);
3273 netif_tx_start_all_queues(dev);
3277 static int cxgb_close(struct net_device *dev)
3279 struct port_info *pi = netdev_priv(dev);
3280 struct adapter *adapter = pi->adapter;
3282 netif_tx_stop_all_queues(dev);
3283 netif_carrier_off(dev);
3284 return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
3287 /* Return an error number if the indicated filter isn't writable ...
3289 static int writable_filter(struct filter_entry *f)
3299 /* Delete the filter at the specified index (if valid). The checks for all
3300 * the common problems with doing this like the filter being locked, currently
3301 * pending in another operation, etc.
3303 static int delete_filter(struct adapter *adapter, unsigned int fidx)
3305 struct filter_entry *f;
3308 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
3311 f = &adapter->tids.ftid_tab[fidx];
3312 ret = writable_filter(f);
3316 return del_filter_wr(adapter, fidx);
3321 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
3322 __be32 sip, __be16 sport, __be16 vlan,
3323 unsigned int queue, unsigned char port, unsigned char mask)
3326 struct filter_entry *f;
3327 struct adapter *adap;
3331 adap = netdev2adap(dev);
3333 /* Adjust stid to correct filter index */
3334 stid -= adap->tids.nstids;
3335 stid += adap->tids.nftids;
3337 /* Check to make sure the filter requested is writable ...
3339 f = &adap->tids.ftid_tab[stid];
3340 ret = writable_filter(f);
3344 /* Clear out any old resources being used by the filter before
3345 * we start constructing the new filter.
3348 clear_filter(adap, f);
3350 /* Clear out filter specifications */
3351 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
3352 f->fs.val.lport = cpu_to_be16(sport);
3353 f->fs.mask.lport = ~0;
3355 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
3356 for (i = 0; i < 4; i++) {
3357 f->fs.val.lip[i] = val[i];
3358 f->fs.mask.lip[i] = ~0;
3360 if (adap->filter_mode & F_PORT) {
3361 f->fs.val.iport = port;
3362 f->fs.mask.iport = mask;
3368 /* Mark filter as locked */
3372 ret = set_filter_wr(adap, stid);
3374 clear_filter(adap, f);
3380 EXPORT_SYMBOL(cxgb4_create_server_filter);
3382 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
3383 unsigned int queue, bool ipv6)
3386 struct filter_entry *f;
3387 struct adapter *adap;
3389 adap = netdev2adap(dev);
3391 /* Adjust stid to correct filter index */
3392 stid -= adap->tids.nstids;
3393 stid += adap->tids.nftids;
3395 f = &adap->tids.ftid_tab[stid];
3396 /* Unlock the filter */
3399 ret = delete_filter(adap, stid);
3405 EXPORT_SYMBOL(cxgb4_remove_server_filter);
3407 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
3408 struct rtnl_link_stats64 *ns)
3410 struct port_stats stats;
3411 struct port_info *p = netdev_priv(dev);
3412 struct adapter *adapter = p->adapter;
3414 spin_lock(&adapter->stats_lock);
3415 t4_get_port_stats(adapter, p->tx_chan, &stats);
3416 spin_unlock(&adapter->stats_lock);
3418 ns->tx_bytes = stats.tx_octets;
3419 ns->tx_packets = stats.tx_frames;
3420 ns->rx_bytes = stats.rx_octets;
3421 ns->rx_packets = stats.rx_frames;
3422 ns->multicast = stats.rx_mcast_frames;
3424 /* detailed rx_errors */
3425 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
3427 ns->rx_over_errors = 0;
3428 ns->rx_crc_errors = stats.rx_fcs_err;
3429 ns->rx_frame_errors = stats.rx_symbol_err;
3430 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
3431 stats.rx_ovflow2 + stats.rx_ovflow3 +
3432 stats.rx_trunc0 + stats.rx_trunc1 +
3433 stats.rx_trunc2 + stats.rx_trunc3;
3434 ns->rx_missed_errors = 0;
3436 /* detailed tx_errors */
3437 ns->tx_aborted_errors = 0;
3438 ns->tx_carrier_errors = 0;
3439 ns->tx_fifo_errors = 0;
3440 ns->tx_heartbeat_errors = 0;
3441 ns->tx_window_errors = 0;
3443 ns->tx_errors = stats.tx_error_frames;
3444 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
3445 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
3449 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
3452 int ret = 0, prtad, devad;
3453 struct port_info *pi = netdev_priv(dev);
3454 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
3458 if (pi->mdio_addr < 0)
3460 data->phy_id = pi->mdio_addr;
3464 if (mdio_phy_id_is_c45(data->phy_id)) {
3465 prtad = mdio_phy_id_prtad(data->phy_id);
3466 devad = mdio_phy_id_devad(data->phy_id);
3467 } else if (data->phy_id < 32) {
3468 prtad = data->phy_id;
3470 data->reg_num &= 0x1f;
3474 mbox = pi->adapter->fn;
3475 if (cmd == SIOCGMIIREG)
3476 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
3477 data->reg_num, &data->val_out);
3479 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
3480 data->reg_num, data->val_in);
3488 static void cxgb_set_rxmode(struct net_device *dev)
3490 /* unfortunately we can't return errors to the stack */
3491 set_rxmode(dev, -1, false);
3494 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
3497 struct port_info *pi = netdev_priv(dev);
3499 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
3501 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
3508 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
3511 struct sockaddr *addr = p;
3512 struct port_info *pi = netdev_priv(dev);
3514 if (!is_valid_ether_addr(addr->sa_data))
3515 return -EADDRNOTAVAIL;
3517 ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
3518 pi->xact_addr_filt, addr->sa_data, true, true);
3522 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3523 pi->xact_addr_filt = ret;
3527 #ifdef CONFIG_NET_POLL_CONTROLLER
3528 static void cxgb_netpoll(struct net_device *dev)
3530 struct port_info *pi = netdev_priv(dev);
3531 struct adapter *adap = pi->adapter;
3533 if (adap->flags & USING_MSIX) {
3535 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3537 for (i = pi->nqsets; i; i--, rx++)
3538 t4_sge_intr_msix(0, &rx->rspq);
3540 t4_intr_handler(adap)(0, adap);
3544 static const struct net_device_ops cxgb4_netdev_ops = {
3545 .ndo_open = cxgb_open,
3546 .ndo_stop = cxgb_close,
3547 .ndo_start_xmit = t4_eth_xmit,
3548 .ndo_get_stats64 = cxgb_get_stats,
3549 .ndo_set_rx_mode = cxgb_set_rxmode,
3550 .ndo_set_mac_address = cxgb_set_mac_addr,
3551 .ndo_set_features = cxgb_set_features,
3552 .ndo_validate_addr = eth_validate_addr,
3553 .ndo_do_ioctl = cxgb_ioctl,
3554 .ndo_change_mtu = cxgb_change_mtu,
3555 #ifdef CONFIG_NET_POLL_CONTROLLER
3556 .ndo_poll_controller = cxgb_netpoll,
3560 void t4_fatal_err(struct adapter *adap)
3562 t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);
3563 t4_intr_disable(adap);
3564 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3567 static void setup_memwin(struct adapter *adap)
3571 bar0 = pci_resource_start(adap->pdev, 0); /* truncation intentional */
3572 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
3573 (bar0 + MEMWIN0_BASE) | BIR(0) |
3574 WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
3575 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
3576 (bar0 + MEMWIN1_BASE) | BIR(0) |
3577 WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
3578 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
3579 (bar0 + MEMWIN2_BASE) | BIR(0) |
3580 WINDOW(ilog2(MEMWIN2_APERTURE) - 10));
3583 static void setup_memwin_rdma(struct adapter *adap)
3585 if (adap->vres.ocq.size) {
3586 unsigned int start, sz_kb;
3588 start = pci_resource_start(adap->pdev, 2) +
3589 OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3590 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3592 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
3593 start | BIR(1) | WINDOW(ilog2(sz_kb)));
3595 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
3596 adap->vres.ocq.start);
3598 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
3602 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3607 /* get device capabilities */
3608 memset(c, 0, sizeof(*c));
3609 c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3610 FW_CMD_REQUEST | FW_CMD_READ);
3611 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3612 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
3616 /* select capabilities we'll be using */
3617 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
3619 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
3621 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
3622 } else if (vf_acls) {
3623 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
3626 c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3627 FW_CMD_REQUEST | FW_CMD_WRITE);
3628 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
3632 ret = t4_config_glbl_rss(adap, adap->fn,
3633 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3634 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
3635 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP);
3639 ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, MAX_EGRQ, 64, MAX_INGQ,
3640 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, FW_CMD_CAP_PF);
3646 /* tweak some settings */
3647 t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
3648 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
3649 t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
3650 v = t4_read_reg(adap, TP_PIO_DATA);
3651 t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
3653 /* first 4 Tx modulation queues point to consecutive Tx channels */
3654 adap->params.tp.tx_modq_map = 0xE4;
3655 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
3656 V_TX_MOD_QUEUE_REQ_MAP(adap->params.tp.tx_modq_map));
3658 /* associate each Tx modulation queue with consecutive Tx channels */
3660 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
3661 &v, 1, A_TP_TX_SCHED_HDR);
3662 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
3663 &v, 1, A_TP_TX_SCHED_FIFO);
3664 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
3665 &v, 1, A_TP_TX_SCHED_PCMD);
3667 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3668 if (is_offload(adap)) {
3669 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0,
3670 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3671 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3672 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3673 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3674 t4_write_reg(adap, A_TP_TX_MOD_CHANNEL_WEIGHT,
3675 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3676 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3677 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3678 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3681 /* get basic stuff going */
3682 return t4_early_init(adap, adap->fn);
3686 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3688 #define MAX_ATIDS 8192U
3691 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3693 * If the firmware we're dealing with has Configuration File support, then
3694 * we use that to perform all configuration
3698 * Tweak configuration based on module parameters, etc. Most of these have
3699 * defaults assigned to them by Firmware Configuration Files (if we're using
3700 * them) but need to be explicitly set if we're using hard-coded
3701 * initialization. But even in the case of using Firmware Configuration
3702 * Files, we'd like to expose the ability to change these via module
3703 * parameters so these are essentially common tweaks/settings for
3704 * Configuration Files and hard-coded initialization ...
3706 static int adap_init0_tweaks(struct adapter *adapter)
3709 * Fix up various Host-Dependent Parameters like Page Size, Cache
3710 * Line Size, etc. The firmware default is for a 4KB Page Size and
3711 * 64B Cache Line Size ...
3713 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3716 * Process module parameters which affect early initialization.
3718 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3719 dev_err(&adapter->pdev->dev,
3720 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3724 t4_set_reg_field(adapter, SGE_CONTROL,
3726 PKTSHIFT(rx_dma_offset));
3729 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3730 * adds the pseudo header itself.
3732 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG,
3733 CSUM_HAS_PSEUDO_HDR, 0);
3739 * Attempt to initialize the adapter via a Firmware Configuration File.
3741 static int adap_init0_config(struct adapter *adapter, int reset)
3743 struct fw_caps_config_cmd caps_cmd;
3744 const struct firmware *cf;
3745 unsigned long mtype = 0, maddr = 0;
3746 u32 finiver, finicsum, cfcsum;
3747 int ret, using_flash;
3750 * Reset device if necessary.
3753 ret = t4_fw_reset(adapter, adapter->mbox,
3754 PIORSTMODE | PIORST);
3760 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3761 * then use that. Otherwise, use the configuration file stored
3762 * in the adapter flash ...
3764 ret = request_firmware(&cf, FW_CFNAME, adapter->pdev_dev);
3767 mtype = FW_MEMTYPE_CF_FLASH;
3768 maddr = t4_flash_cfg_addr(adapter);
3770 u32 params[7], val[7];
3773 if (cf->size >= FLASH_CFG_MAX_SIZE)
3776 params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3777 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
3778 ret = t4_query_params(adapter, adapter->mbox,
3779 adapter->fn, 0, 1, params, val);
3782 * For t4_memory_write() below addresses and
3783 * sizes have to be in terms of multiples of 4
3784 * bytes. So, if the Configuration File isn't
3785 * a multiple of 4 bytes in length we'll have
3786 * to write that out separately since we can't
3787 * guarantee that the bytes following the
3788 * residual byte in the buffer returned by
3789 * request_firmware() are zeroed out ...
3791 size_t resid = cf->size & 0x3;
3792 size_t size = cf->size & ~0x3;
3793 __be32 *data = (__be32 *)cf->data;
3795 mtype = FW_PARAMS_PARAM_Y_GET(val[0]);
3796 maddr = FW_PARAMS_PARAM_Z_GET(val[0]) << 16;
3798 ret = t4_memory_write(adapter, mtype, maddr,
3800 if (ret == 0 && resid != 0) {
3807 last.word = data[size >> 2];
3808 for (i = resid; i < 4; i++)
3810 ret = t4_memory_write(adapter, mtype,
3817 release_firmware(cf);
3823 * Issue a Capability Configuration command to the firmware to get it
3824 * to parse the Configuration File. We don't use t4_fw_config_file()
3825 * because we want the ability to modify various features after we've
3826 * processed the configuration file ...
3828 memset(&caps_cmd, 0, sizeof(caps_cmd));
3829 caps_cmd.op_to_write =
3830 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3833 caps_cmd.cfvalid_to_len16 =
3834 htonl(FW_CAPS_CONFIG_CMD_CFVALID |
3835 FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3836 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
3837 FW_LEN16(caps_cmd));
3838 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3843 finiver = ntohl(caps_cmd.finiver);
3844 finicsum = ntohl(caps_cmd.finicsum);
3845 cfcsum = ntohl(caps_cmd.cfcsum);
3846 if (finicsum != cfcsum)
3847 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3848 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3852 * And now tell the firmware to use the configuration we just loaded.
3854 caps_cmd.op_to_write =
3855 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3858 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3859 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3865 * Tweak configuration based on system architecture, module
3868 ret = adap_init0_tweaks(adapter);
3873 * And finally tell the firmware to initialize itself using the
3874 * parameters from the Configuration File.
3876 ret = t4_fw_initialize(adapter, adapter->mbox);
3881 * Return successfully and note that we're operating with parameters
3882 * not supplied by the driver, rather than from hard-wired
3883 * initialization constants burried in the driver.
3885 adapter->flags |= USING_SOFT_PARAMS;
3886 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
3887 "Configuration File %s, version %#x, computed checksum %#x\n",
3890 : "/lib/firmware/" FW_CFNAME),
3895 * Something bad happened. Return the error ... (If the "error"
3896 * is that there's no Configuration File on the adapter we don't
3897 * want to issue a warning since this is fairly common.)
3901 dev_warn(adapter->pdev_dev, "Configuration file error %d\n",
3907 * Attempt to initialize the adapter via hard-coded, driver supplied
3910 static int adap_init0_no_config(struct adapter *adapter, int reset)
3912 struct sge *s = &adapter->sge;
3913 struct fw_caps_config_cmd caps_cmd;
3918 * Reset device if necessary
3921 ret = t4_fw_reset(adapter, adapter->mbox,
3922 PIORSTMODE | PIORST);
3928 * Get device capabilities and select which we'll be using.
3930 memset(&caps_cmd, 0, sizeof(caps_cmd));
3931 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3932 FW_CMD_REQUEST | FW_CMD_READ);
3933 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3934 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3939 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
3941 caps_cmd.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
3943 caps_cmd.niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
3944 } else if (vf_acls) {
3945 dev_err(adapter->pdev_dev, "virtualization ACLs not supported");
3948 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3949 FW_CMD_REQUEST | FW_CMD_WRITE);
3950 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3956 * Tweak configuration based on system architecture, module
3959 ret = adap_init0_tweaks(adapter);
3964 * Select RSS Global Mode we want to use. We use "Basic Virtual"
3965 * mode which maps each Virtual Interface to its own section of
3966 * the RSS Table and we turn on all map and hash enables ...
3968 adapter->flags |= RSS_TNLALLLOOKUP;
3969 ret = t4_config_glbl_rss(adapter, adapter->mbox,
3970 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3971 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
3972 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ |
3973 ((adapter->flags & RSS_TNLALLLOOKUP) ?
3974 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP : 0));
3979 * Set up our own fundamental resource provisioning ...
3981 ret = t4_cfg_pfvf(adapter, adapter->mbox, adapter->fn, 0,
3982 PFRES_NEQ, PFRES_NETHCTRL,
3983 PFRES_NIQFLINT, PFRES_NIQ,
3984 PFRES_TC, PFRES_NVI,
3985 FW_PFVF_CMD_CMASK_MASK,
3986 pfvfres_pmask(adapter, adapter->fn, 0),
3988 PFRES_R_CAPS, PFRES_WX_CAPS);
3993 * Perform low level SGE initialization. We need to do this before we
3994 * send the firmware the INITIALIZE command because that will cause
3995 * any other PF Drivers which are waiting for the Master
3996 * Initialization to proceed forward.
3998 for (i = 0; i < SGE_NTIMERS - 1; i++)
3999 s->timer_val[i] = min(intr_holdoff[i], MAX_SGE_TIMERVAL);
4000 s->timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;
4001 s->counter_val[0] = 1;
4002 for (i = 1; i < SGE_NCOUNTERS; i++)
4003 s->counter_val[i] = min(intr_cnt[i - 1],
4004 THRESHOLD_0_GET(THRESHOLD_0_MASK));
4005 t4_sge_init(adapter);
4007 #ifdef CONFIG_PCI_IOV
4009 * Provision resource limits for Virtual Functions. We currently
4010 * grant them all the same static resource limits except for the Port
4011 * Access Rights Mask which we're assigning based on the PF. All of
4012 * the static provisioning stuff for both the PF and VF really needs
4013 * to be managed in a persistent manner for each device which the
4014 * firmware controls.
4019 for (pf = 0; pf < ARRAY_SIZE(num_vf); pf++) {
4020 if (num_vf[pf] <= 0)
4023 /* VF numbering starts at 1! */
4024 for (vf = 1; vf <= num_vf[pf]; vf++) {
4025 ret = t4_cfg_pfvf(adapter, adapter->mbox,
4027 VFRES_NEQ, VFRES_NETHCTRL,
4028 VFRES_NIQFLINT, VFRES_NIQ,
4029 VFRES_TC, VFRES_NVI,
4030 FW_PFVF_CMD_CMASK_MASK,
4034 VFRES_R_CAPS, VFRES_WX_CAPS);
4036 dev_warn(adapter->pdev_dev,
4038 "provision pf/vf=%d/%d; "
4039 "err=%d\n", pf, vf, ret);
4046 * Set up the default filter mode. Later we'll want to implement this
4047 * via a firmware command, etc. ... This needs to be done before the
4048 * firmare initialization command ... If the selected set of fields
4049 * isn't equal to the default value, we'll need to make sure that the
4050 * field selections will fit in the 36-bit budget.
4052 if (tp_vlan_pri_map != TP_VLAN_PRI_MAP_DEFAULT) {
4055 for (j = TP_VLAN_PRI_MAP_FIRST; j <= TP_VLAN_PRI_MAP_LAST; j++)
4056 switch (tp_vlan_pri_map & (1 << j)) {
4058 /* compressed filter field not enabled */
4078 case ETHERTYPE_MASK:
4084 case MPSHITTYPE_MASK:
4087 case FRAGMENTATION_MASK:
4093 dev_err(adapter->pdev_dev,
4094 "tp_vlan_pri_map=%#x needs %d bits > 36;"\
4095 " using %#x\n", tp_vlan_pri_map, bits,
4096 TP_VLAN_PRI_MAP_DEFAULT);
4097 tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
4100 v = tp_vlan_pri_map;
4101 t4_write_indirect(adapter, TP_PIO_ADDR, TP_PIO_DATA,
4102 &v, 1, TP_VLAN_PRI_MAP);
4105 * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
4106 * to support any of the compressed filter fields above. Newer
4107 * versions of the firmware do this automatically but it doesn't hurt
4108 * to set it here. Meanwhile, we do _not_ need to set Lookup Every
4109 * Packet in TP_INGRESS_CONFIG to support matching non-TCP packets
4110 * since the firmware automatically turns this on and off when we have
4111 * a non-zero number of filters active (since it does have a
4112 * performance impact).
4114 if (tp_vlan_pri_map)
4115 t4_set_reg_field(adapter, TP_GLOBAL_CONFIG,
4116 FIVETUPLELOOKUP_MASK,
4117 FIVETUPLELOOKUP_MASK);
4120 * Tweak some settings.
4122 t4_write_reg(adapter, TP_SHIFT_CNT, SYNSHIFTMAX(6) |
4123 RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
4124 PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
4125 KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
4128 * Get basic stuff going by issuing the Firmware Initialize command.
4129 * Note that this _must_ be after all PFVF commands ...
4131 ret = t4_fw_initialize(adapter, adapter->mbox);
4136 * Return successfully!
4138 dev_info(adapter->pdev_dev, "Successfully configured using built-in "\
4139 "driver parameters\n");
4143 * Something bad happened. Return the error ...
4150 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4152 static int adap_init0(struct adapter *adap)
4156 enum dev_state state;
4157 u32 params[7], val[7];
4158 struct fw_caps_config_cmd caps_cmd;
4162 * Contact FW, advertising Master capability (and potentially forcing
4163 * ourselves as the Master PF if our module parameter force_init is
4166 ret = t4_fw_hello(adap, adap->mbox, adap->fn,
4167 force_init ? MASTER_MUST : MASTER_MAY,
4170 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
4174 if (ret == adap->mbox)
4175 adap->flags |= MASTER_PF;
4176 if (force_init && state == DEV_STATE_INIT)
4177 state = DEV_STATE_UNINIT;
4180 * If we're the Master PF Driver and the device is uninitialized,
4181 * then let's consider upgrading the firmware ... (We always want
4182 * to check the firmware version number in order to A. get it for
4183 * later reporting and B. to warn if the currently loaded firmware
4184 * is excessively mismatched relative to the driver.)
4186 ret = t4_check_fw_version(adap);
4187 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
4188 if (ret == -EINVAL || ret > 0) {
4189 if (upgrade_fw(adap) >= 0) {
4191 * Note that the chip was reset as part of the
4192 * firmware upgrade so we don't reset it again
4193 * below and grab the new firmware version.
4196 ret = t4_check_fw_version(adap);
4204 * Grab VPD parameters. This should be done after we establish a
4205 * connection to the firmware since some of the VPD parameters
4206 * (notably the Core Clock frequency) are retrieved via requests to
4207 * the firmware. On the other hand, we need these fairly early on
4208 * so we do this right after getting ahold of the firmware.
4210 ret = get_vpd_params(adap, &adap->params.vpd);
4215 * Find out what ports are available to us. Note that we need to do
4216 * this before calling adap_init0_no_config() since it needs nports
4220 FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
4221 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
4222 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
4226 adap->params.nports = hweight32(port_vec);
4227 adap->params.portvec = port_vec;
4230 * If the firmware is initialized already (and we're not forcing a
4231 * master initialization), note that we're living with existing
4232 * adapter parameters. Otherwise, it's time to try initializing the
4235 if (state == DEV_STATE_INIT) {
4236 dev_info(adap->pdev_dev, "Coming up as %s: "\
4237 "Adapter already initialized\n",
4238 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
4239 adap->flags |= USING_SOFT_PARAMS;
4241 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
4242 "Initializing adapter\n");
4245 * If the firmware doesn't support Configuration
4246 * Files warn user and exit,
4249 dev_warn(adap->pdev_dev, "Firmware doesn't support "
4250 "configuration file.\n");
4252 ret = adap_init0_no_config(adap, reset);
4255 * Find out whether we're dealing with a version of
4256 * the firmware which has configuration file support.
4258 params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
4259 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
4260 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
4264 * If the firmware doesn't support Configuration
4265 * Files, use the old Driver-based, hard-wired
4266 * initialization. Otherwise, try using the
4267 * Configuration File support and fall back to the
4268 * Driver-based initialization if there's no
4269 * Configuration File found.
4272 ret = adap_init0_no_config(adap, reset);
4275 * The firmware provides us with a memory
4276 * buffer where we can load a Configuration
4277 * File from the host if we want to override
4278 * the Configuration File in flash.
4281 ret = adap_init0_config(adap, reset);
4282 if (ret == -ENOENT) {
4283 dev_info(adap->pdev_dev,
4284 "No Configuration File present "
4285 "on adapter. Using hard-wired "
4286 "configuration parameters.\n");
4287 ret = adap_init0_no_config(adap, reset);
4292 dev_err(adap->pdev_dev,
4293 "could not initialize adapter, error %d\n",
4300 * If we're living with non-hard-coded parameters (either from a
4301 * Firmware Configuration File or values programmed by a different PF
4302 * Driver), give the SGE code a chance to pull in anything that it
4303 * needs ... Note that this must be called after we retrieve our VPD
4304 * parameters in order to know how to convert core ticks to seconds.
4306 if (adap->flags & USING_SOFT_PARAMS) {
4307 ret = t4_sge_init(adap);
4312 if (is_bypass_device(adap->pdev->device))
4313 adap->params.bypass = 1;
4316 * Grab some of our basic fundamental operating parameters.
4318 #define FW_PARAM_DEV(param) \
4319 (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
4320 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
4322 #define FW_PARAM_PFVF(param) \
4323 FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
4324 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)| \
4325 FW_PARAMS_PARAM_Y(0) | \
4326 FW_PARAMS_PARAM_Z(0)
4328 params[0] = FW_PARAM_PFVF(EQ_START);
4329 params[1] = FW_PARAM_PFVF(L2T_START);
4330 params[2] = FW_PARAM_PFVF(L2T_END);
4331 params[3] = FW_PARAM_PFVF(FILTER_START);
4332 params[4] = FW_PARAM_PFVF(FILTER_END);
4333 params[5] = FW_PARAM_PFVF(IQFLINT_START);
4334 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
4337 adap->sge.egr_start = val[0];
4338 adap->l2t_start = val[1];
4339 adap->l2t_end = val[2];
4340 adap->tids.ftid_base = val[3];
4341 adap->tids.nftids = val[4] - val[3] + 1;
4342 adap->sge.ingr_start = val[5];
4344 /* query params related to active filter region */
4345 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
4346 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
4347 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
4348 /* If Active filter size is set we enable establishing
4349 * offload connection through firmware work request
4351 if ((val[0] != val[1]) && (ret >= 0)) {
4352 adap->flags |= FW_OFLD_CONN;
4353 adap->tids.aftid_base = val[0];
4354 adap->tids.aftid_end = val[1];
4358 * Get device capabilities so we can determine what resources we need
4361 memset(&caps_cmd, 0, sizeof(caps_cmd));
4362 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4363 FW_CMD_REQUEST | FW_CMD_READ);
4364 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4365 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
4370 if (caps_cmd.ofldcaps) {
4371 /* query offload-related parameters */
4372 params[0] = FW_PARAM_DEV(NTID);
4373 params[1] = FW_PARAM_PFVF(SERVER_START);
4374 params[2] = FW_PARAM_PFVF(SERVER_END);
4375 params[3] = FW_PARAM_PFVF(TDDP_START);
4376 params[4] = FW_PARAM_PFVF(TDDP_END);
4377 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4378 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
4382 adap->tids.ntids = val[0];
4383 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
4384 adap->tids.stid_base = val[1];
4385 adap->tids.nstids = val[2] - val[1] + 1;
4387 * Setup server filter region. Divide the availble filter
4388 * region into two parts. Regular filters get 1/3rd and server
4389 * filters get 2/3rd part. This is only enabled if workarond
4391 * 1. For regular filters.
4392 * 2. Server filter: This are special filters which are used
4393 * to redirect SYN packets to offload queue.
4395 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
4396 adap->tids.sftid_base = adap->tids.ftid_base +
4397 DIV_ROUND_UP(adap->tids.nftids, 3);
4398 adap->tids.nsftids = adap->tids.nftids -
4399 DIV_ROUND_UP(adap->tids.nftids, 3);
4400 adap->tids.nftids = adap->tids.sftid_base -
4401 adap->tids.ftid_base;
4403 adap->vres.ddp.start = val[3];
4404 adap->vres.ddp.size = val[4] - val[3] + 1;
4405 adap->params.ofldq_wr_cred = val[5];
4407 adap->params.offload = 1;
4409 if (caps_cmd.rdmacaps) {
4410 params[0] = FW_PARAM_PFVF(STAG_START);
4411 params[1] = FW_PARAM_PFVF(STAG_END);
4412 params[2] = FW_PARAM_PFVF(RQ_START);
4413 params[3] = FW_PARAM_PFVF(RQ_END);
4414 params[4] = FW_PARAM_PFVF(PBL_START);
4415 params[5] = FW_PARAM_PFVF(PBL_END);
4416 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
4420 adap->vres.stag.start = val[0];
4421 adap->vres.stag.size = val[1] - val[0] + 1;
4422 adap->vres.rq.start = val[2];
4423 adap->vres.rq.size = val[3] - val[2] + 1;
4424 adap->vres.pbl.start = val[4];
4425 adap->vres.pbl.size = val[5] - val[4] + 1;
4427 params[0] = FW_PARAM_PFVF(SQRQ_START);
4428 params[1] = FW_PARAM_PFVF(SQRQ_END);
4429 params[2] = FW_PARAM_PFVF(CQ_START);
4430 params[3] = FW_PARAM_PFVF(CQ_END);
4431 params[4] = FW_PARAM_PFVF(OCQ_START);
4432 params[5] = FW_PARAM_PFVF(OCQ_END);
4433 ret = t4_query_params(adap, 0, 0, 0, 6, params, val);
4436 adap->vres.qp.start = val[0];
4437 adap->vres.qp.size = val[1] - val[0] + 1;
4438 adap->vres.cq.start = val[2];
4439 adap->vres.cq.size = val[3] - val[2] + 1;
4440 adap->vres.ocq.start = val[4];
4441 adap->vres.ocq.size = val[5] - val[4] + 1;
4443 if (caps_cmd.iscsicaps) {
4444 params[0] = FW_PARAM_PFVF(ISCSI_START);
4445 params[1] = FW_PARAM_PFVF(ISCSI_END);
4446 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
4450 adap->vres.iscsi.start = val[0];
4451 adap->vres.iscsi.size = val[1] - val[0] + 1;
4453 #undef FW_PARAM_PFVF
4457 * These are finalized by FW initialization, load their values now.
4459 v = t4_read_reg(adap, TP_TIMER_RESOLUTION);
4460 adap->params.tp.tre = TIMERRESOLUTION_GET(v);
4461 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_GET(v);
4462 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
4463 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4464 adap->params.b_wnd);
4466 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4467 for (j = 0; j < NCHAN; j++)
4468 adap->params.tp.tx_modq[j] = j;
4470 t4_read_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4471 &adap->filter_mode, 1,
4474 adap->flags |= FW_OK;
4478 * Something bad happened. If a command timed out or failed with EIO
4479 * FW does not operate within its spec or something catastrophic
4480 * happened to HW/FW, stop issuing commands.
4483 if (ret != -ETIMEDOUT && ret != -EIO)
4484 t4_fw_bye(adap, adap->mbox);
4490 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4491 pci_channel_state_t state)
4494 struct adapter *adap = pci_get_drvdata(pdev);
4500 adap->flags &= ~FW_OK;
4501 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
4502 for_each_port(adap, i) {
4503 struct net_device *dev = adap->port[i];
4505 netif_device_detach(dev);
4506 netif_carrier_off(dev);
4508 if (adap->flags & FULL_INIT_DONE)
4511 pci_disable_device(pdev);
4512 out: return state == pci_channel_io_perm_failure ?
4513 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4516 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4519 struct fw_caps_config_cmd c;
4520 struct adapter *adap = pci_get_drvdata(pdev);
4523 pci_restore_state(pdev);
4524 pci_save_state(pdev);
4525 return PCI_ERS_RESULT_RECOVERED;
4528 if (pci_enable_device(pdev)) {
4529 dev_err(&pdev->dev, "cannot reenable PCI device after reset\n");
4530 return PCI_ERS_RESULT_DISCONNECT;
4533 pci_set_master(pdev);
4534 pci_restore_state(pdev);
4535 pci_save_state(pdev);
4536 pci_cleanup_aer_uncorrect_error_status(pdev);
4538 if (t4_wait_dev_ready(adap) < 0)
4539 return PCI_ERS_RESULT_DISCONNECT;
4540 if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL))
4541 return PCI_ERS_RESULT_DISCONNECT;
4542 adap->flags |= FW_OK;
4543 if (adap_init1(adap, &c))
4544 return PCI_ERS_RESULT_DISCONNECT;
4546 for_each_port(adap, i) {
4547 struct port_info *p = adap2pinfo(adap, i);
4549 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
4552 return PCI_ERS_RESULT_DISCONNECT;
4554 p->xact_addr_filt = -1;
4557 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4558 adap->params.b_wnd);
4561 return PCI_ERS_RESULT_DISCONNECT;
4562 return PCI_ERS_RESULT_RECOVERED;
4565 static void eeh_resume(struct pci_dev *pdev)
4568 struct adapter *adap = pci_get_drvdata(pdev);
4574 for_each_port(adap, i) {
4575 struct net_device *dev = adap->port[i];
4577 if (netif_running(dev)) {
4579 cxgb_set_rxmode(dev);
4581 netif_device_attach(dev);
4586 static const struct pci_error_handlers cxgb4_eeh = {
4587 .error_detected = eeh_err_detected,
4588 .slot_reset = eeh_slot_reset,
4589 .resume = eeh_resume,
4592 static inline bool is_10g_port(const struct link_config *lc)
4594 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0;
4597 static inline void init_rspq(struct sge_rspq *q, u8 timer_idx, u8 pkt_cnt_idx,
4598 unsigned int size, unsigned int iqe_size)
4600 q->intr_params = QINTR_TIMER_IDX(timer_idx) |
4601 (pkt_cnt_idx < SGE_NCOUNTERS ? QINTR_CNT_EN : 0);
4602 q->pktcnt_idx = pkt_cnt_idx < SGE_NCOUNTERS ? pkt_cnt_idx : 0;
4603 q->iqe_len = iqe_size;
4608 * Perform default configuration of DMA queues depending on the number and type
4609 * of ports we found and the number of available CPUs. Most settings can be
4610 * modified by the admin prior to actual use.
4612 static void cfg_queues(struct adapter *adap)
4614 struct sge *s = &adap->sge;
4615 int i, q10g = 0, n10g = 0, qidx = 0;
4617 for_each_port(adap, i)
4618 n10g += is_10g_port(&adap2pinfo(adap, i)->link_cfg);
4621 * We default to 1 queue per non-10G port and up to # of cores queues
4625 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
4626 if (q10g > netif_get_num_default_rss_queues())
4627 q10g = netif_get_num_default_rss_queues();
4629 for_each_port(adap, i) {
4630 struct port_info *pi = adap2pinfo(adap, i);
4632 pi->first_qset = qidx;
4633 pi->nqsets = is_10g_port(&pi->link_cfg) ? q10g : 1;
4638 s->max_ethqsets = qidx; /* MSI-X may lower it later */
4640 if (is_offload(adap)) {
4642 * For offload we use 1 queue/channel if all ports are up to 1G,
4643 * otherwise we divide all available queues amongst the channels
4644 * capped by the number of available cores.
4647 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
4649 s->ofldqsets = roundup(i, adap->params.nports);
4651 s->ofldqsets = adap->params.nports;
4652 /* For RDMA one Rx queue per channel suffices */
4653 s->rdmaqs = adap->params.nports;
4656 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4657 struct sge_eth_rxq *r = &s->ethrxq[i];
4659 init_rspq(&r->rspq, 0, 0, 1024, 64);
4663 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4664 s->ethtxq[i].q.size = 1024;
4666 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4667 s->ctrlq[i].q.size = 512;
4669 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
4670 s->ofldtxq[i].q.size = 1024;
4672 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
4673 struct sge_ofld_rxq *r = &s->ofldrxq[i];
4675 init_rspq(&r->rspq, 0, 0, 1024, 64);
4676 r->rspq.uld = CXGB4_ULD_ISCSI;
4680 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
4681 struct sge_ofld_rxq *r = &s->rdmarxq[i];
4683 init_rspq(&r->rspq, 0, 0, 511, 64);
4684 r->rspq.uld = CXGB4_ULD_RDMA;
4688 init_rspq(&s->fw_evtq, 6, 0, 512, 64);
4689 init_rspq(&s->intrq, 6, 0, 2 * MAX_INGQ, 64);
4693 * Reduce the number of Ethernet queues across all ports to at most n.
4694 * n provides at least one queue per port.
4696 static void reduce_ethqs(struct adapter *adap, int n)
4699 struct port_info *pi;
4701 while (n < adap->sge.ethqsets)
4702 for_each_port(adap, i) {
4703 pi = adap2pinfo(adap, i);
4704 if (pi->nqsets > 1) {
4706 adap->sge.ethqsets--;
4707 if (adap->sge.ethqsets <= n)
4713 for_each_port(adap, i) {
4714 pi = adap2pinfo(adap, i);
4720 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4721 #define EXTRA_VECS 2
4723 static int enable_msix(struct adapter *adap)
4726 int i, err, want, need;
4727 struct sge *s = &adap->sge;
4728 unsigned int nchan = adap->params.nports;
4729 struct msix_entry entries[MAX_INGQ + 1];
4731 for (i = 0; i < ARRAY_SIZE(entries); ++i)
4732 entries[i].entry = i;
4734 want = s->max_ethqsets + EXTRA_VECS;
4735 if (is_offload(adap)) {
4736 want += s->rdmaqs + s->ofldqsets;
4737 /* need nchan for each possible ULD */
4738 ofld_need = 2 * nchan;
4740 need = adap->params.nports + EXTRA_VECS + ofld_need;
4742 while ((err = pci_enable_msix(adap->pdev, entries, want)) >= need)
4747 * Distribute available vectors to the various queue groups.
4748 * Every group gets its minimum requirement and NIC gets top
4749 * priority for leftovers.
4751 i = want - EXTRA_VECS - ofld_need;
4752 if (i < s->max_ethqsets) {
4753 s->max_ethqsets = i;
4754 if (i < s->ethqsets)
4755 reduce_ethqs(adap, i);
4757 if (is_offload(adap)) {
4758 i = want - EXTRA_VECS - s->max_ethqsets;
4759 i -= ofld_need - nchan;
4760 s->ofldqsets = (i / nchan) * nchan; /* round down */
4762 for (i = 0; i < want; ++i)
4763 adap->msix_info[i].vec = entries[i].vector;
4765 dev_info(adap->pdev_dev,
4766 "only %d MSI-X vectors left, not using MSI-X\n", err);
4772 static int init_rss(struct adapter *adap)
4776 for_each_port(adap, i) {
4777 struct port_info *pi = adap2pinfo(adap, i);
4779 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4782 for (j = 0; j < pi->rss_size; j++)
4783 pi->rss[j] = ethtool_rxfh_indir_default(j, pi->nqsets);
4788 static void print_port_info(const struct net_device *dev)
4790 static const char *base[] = {
4791 "R XFI", "R XAUI", "T SGMII", "T XFI", "T XAUI", "KX4", "CX4",
4792 "KX", "KR", "R SFP+", "KR/KX", "KR/KX/KX4"
4797 const char *spd = "";
4798 const struct port_info *pi = netdev_priv(dev);
4799 const struct adapter *adap = pi->adapter;
4801 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4803 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4806 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
4807 bufp += sprintf(bufp, "100/");
4808 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
4809 bufp += sprintf(bufp, "1000/");
4810 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
4811 bufp += sprintf(bufp, "10G/");
4814 sprintf(bufp, "BASE-%s", base[pi->port_type]);
4816 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
4817 adap->params.vpd.id, adap->params.rev, buf,
4818 is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
4819 (adap->flags & USING_MSIX) ? " MSI-X" :
4820 (adap->flags & USING_MSI) ? " MSI" : "");
4821 netdev_info(dev, "S/N: %s, E/C: %s\n",
4822 adap->params.vpd.sn, adap->params.vpd.ec);
4825 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
4827 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
4831 * Free the following resources:
4832 * - memory used for tables
4835 * - resources FW is holding for us
4837 static void free_some_resources(struct adapter *adapter)
4841 t4_free_mem(adapter->l2t);
4842 t4_free_mem(adapter->tids.tid_tab);
4843 disable_msi(adapter);
4845 for_each_port(adapter, i)
4846 if (adapter->port[i]) {
4847 kfree(adap2pinfo(adapter, i)->rss);
4848 free_netdev(adapter->port[i]);
4850 if (adapter->flags & FW_OK)
4851 t4_fw_bye(adapter, adapter->fn);
4854 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
4855 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
4856 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
4858 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4861 struct port_info *pi;
4862 bool highdma = false;
4863 struct adapter *adapter = NULL;
4865 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4867 err = pci_request_regions(pdev, KBUILD_MODNAME);
4869 /* Just info, some other driver may have claimed the device. */
4870 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4874 /* We control everything through one PF */
4875 func = PCI_FUNC(pdev->devfn);
4876 if (func != ent->driver_data) {
4877 pci_save_state(pdev); /* to restore SR-IOV later */
4881 err = pci_enable_device(pdev);
4883 dev_err(&pdev->dev, "cannot enable PCI device\n");
4884 goto out_release_regions;
4887 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4889 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4891 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4892 "coherent allocations\n");
4893 goto out_disable_device;
4896 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4898 dev_err(&pdev->dev, "no usable DMA configuration\n");
4899 goto out_disable_device;
4903 pci_enable_pcie_error_reporting(pdev);
4904 enable_pcie_relaxed_ordering(pdev);
4905 pci_set_master(pdev);
4906 pci_save_state(pdev);
4908 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4911 goto out_disable_device;
4914 adapter->regs = pci_ioremap_bar(pdev, 0);
4915 if (!adapter->regs) {
4916 dev_err(&pdev->dev, "cannot map device registers\n");
4918 goto out_free_adapter;
4921 adapter->pdev = pdev;
4922 adapter->pdev_dev = &pdev->dev;
4923 adapter->mbox = func;
4925 adapter->msg_enable = dflt_msg_enable;
4926 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4928 spin_lock_init(&adapter->stats_lock);
4929 spin_lock_init(&adapter->tid_release_lock);
4931 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
4932 INIT_WORK(&adapter->db_full_task, process_db_full);
4933 INIT_WORK(&adapter->db_drop_task, process_db_drop);
4935 err = t4_prep_adapter(adapter);
4938 setup_memwin(adapter);
4939 err = adap_init0(adapter);
4940 setup_memwin_rdma(adapter);
4944 for_each_port(adapter, i) {
4945 struct net_device *netdev;
4947 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4954 SET_NETDEV_DEV(netdev, &pdev->dev);
4956 adapter->port[i] = netdev;
4957 pi = netdev_priv(netdev);
4958 pi->adapter = adapter;
4959 pi->xact_addr_filt = -1;
4961 netdev->irq = pdev->irq;
4963 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
4964 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4965 NETIF_F_RXCSUM | NETIF_F_RXHASH |
4966 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4968 netdev->hw_features |= NETIF_F_HIGHDMA;
4969 netdev->features |= netdev->hw_features;
4970 netdev->vlan_features = netdev->features & VLAN_FEAT;
4972 netdev->priv_flags |= IFF_UNICAST_FLT;
4974 netdev->netdev_ops = &cxgb4_netdev_ops;
4975 SET_ETHTOOL_OPS(netdev, &cxgb_ethtool_ops);
4978 pci_set_drvdata(pdev, adapter);
4980 if (adapter->flags & FW_OK) {
4981 err = t4_port_init(adapter, func, func, 0);
4987 * Configure queues and allocate tables now, they can be needed as
4988 * soon as the first register_netdev completes.
4990 cfg_queues(adapter);
4992 adapter->l2t = t4_init_l2t();
4993 if (!adapter->l2t) {
4994 /* We tolerate a lack of L2T, giving up some functionality */
4995 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
4996 adapter->params.offload = 0;
4999 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
5000 dev_warn(&pdev->dev, "could not allocate TID table, "
5002 adapter->params.offload = 0;
5005 /* See what interrupts we'll be using */
5006 if (msi > 1 && enable_msix(adapter) == 0)
5007 adapter->flags |= USING_MSIX;
5008 else if (msi > 0 && pci_enable_msi(pdev) == 0)
5009 adapter->flags |= USING_MSI;
5011 err = init_rss(adapter);
5016 * The card is now ready to go. If any errors occur during device
5017 * registration we do not fail the whole card but rather proceed only
5018 * with the ports we manage to register successfully. However we must
5019 * register at least one net device.
5021 for_each_port(adapter, i) {
5022 pi = adap2pinfo(adapter, i);
5023 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
5024 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
5026 err = register_netdev(adapter->port[i]);
5029 adapter->chan_map[pi->tx_chan] = i;
5030 print_port_info(adapter->port[i]);
5033 dev_err(&pdev->dev, "could not register any net devices\n");
5037 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
5041 if (cxgb4_debugfs_root) {
5042 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
5043 cxgb4_debugfs_root);
5044 setup_debugfs(adapter);
5047 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
5048 pdev->needs_freset = 1;
5050 if (is_offload(adapter))
5051 attach_ulds(adapter);
5054 #ifdef CONFIG_PCI_IOV
5055 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
5056 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
5057 dev_info(&pdev->dev,
5058 "instantiated %u virtual functions\n",
5064 free_some_resources(adapter);
5066 iounmap(adapter->regs);
5070 pci_disable_pcie_error_reporting(pdev);
5071 pci_disable_device(pdev);
5072 out_release_regions:
5073 pci_release_regions(pdev);
5074 pci_set_drvdata(pdev, NULL);
5078 static void remove_one(struct pci_dev *pdev)
5080 struct adapter *adapter = pci_get_drvdata(pdev);
5082 #ifdef CONFIG_PCI_IOV
5083 pci_disable_sriov(pdev);
5090 if (is_offload(adapter))
5091 detach_ulds(adapter);
5093 for_each_port(adapter, i)
5094 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5095 unregister_netdev(adapter->port[i]);
5097 if (adapter->debugfs_root)
5098 debugfs_remove_recursive(adapter->debugfs_root);
5100 /* If we allocated filters, free up state associated with any
5103 if (adapter->tids.ftid_tab) {
5104 struct filter_entry *f = &adapter->tids.ftid_tab[0];
5105 for (i = 0; i < (adapter->tids.nftids +
5106 adapter->tids.nsftids); i++, f++)
5108 clear_filter(adapter, f);
5111 if (adapter->flags & FULL_INIT_DONE)
5114 free_some_resources(adapter);
5115 iounmap(adapter->regs);
5117 pci_disable_pcie_error_reporting(pdev);
5118 pci_disable_device(pdev);
5119 pci_release_regions(pdev);
5120 pci_set_drvdata(pdev, NULL);
5122 pci_release_regions(pdev);
5125 static struct pci_driver cxgb4_driver = {
5126 .name = KBUILD_MODNAME,
5127 .id_table = cxgb4_pci_tbl,
5129 .remove = remove_one,
5130 .err_handler = &cxgb4_eeh,
5133 static int __init cxgb4_init_module(void)
5137 workq = create_singlethread_workqueue("cxgb4");
5141 /* Debugfs support is optional, just warn if this fails */
5142 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
5143 if (!cxgb4_debugfs_root)
5144 pr_warn("could not create debugfs entry, continuing\n");
5146 ret = pci_register_driver(&cxgb4_driver);
5148 debugfs_remove(cxgb4_debugfs_root);
5152 static void __exit cxgb4_cleanup_module(void)
5154 pci_unregister_driver(&cxgb4_driver);
5155 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
5156 flush_workqueue(workq);
5157 destroy_workqueue(workq);
5160 module_init(cxgb4_init_module);
5161 module_exit(cxgb4_cleanup_module);