2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
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13 * without modification, are permitted provided that the following
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17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/skbuff.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/if_vlan.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/jiffies.h>
42 #include <linux/prefetch.h>
43 #include <linux/export.h>
52 * Rx buffer size. We use largish buffers if possible but settle for single
53 * pages under memory shortage.
56 # define FL_PG_ORDER 0
58 # define FL_PG_ORDER (16 - PAGE_SHIFT)
61 /* RX_PULL_LEN should be <= RX_COPY_THRES */
62 #define RX_COPY_THRES 256
63 #define RX_PULL_LEN 128
66 * Main body length for sk_buffs used for Rx Ethernet packets with fragments.
67 * Should be >= RX_PULL_LEN but possibly bigger to give pskb_may_pull some room.
69 #define RX_PKT_SKB_LEN 512
72 * Max number of Tx descriptors we clean up at a time. Should be modest as
73 * freeing skbs isn't cheap and it happens while holding locks. We just need
74 * to free packets faster than they arrive, we eventually catch up and keep
75 * the amortized cost reasonable. Must be >= 2 * TXQ_STOP_THRES.
77 #define MAX_TX_RECLAIM 16
80 * Max number of Rx buffers we replenish at a time. Again keep this modest,
81 * allocating buffers isn't cheap either.
83 #define MAX_RX_REFILL 16U
86 * Period of the Rx queue check timer. This timer is infrequent as it has
87 * something to do only when the system experiences severe memory shortage.
89 #define RX_QCHECK_PERIOD (HZ / 2)
92 * Period of the Tx queue check timer.
94 #define TX_QCHECK_PERIOD (HZ / 2)
96 /* SGE Hung Ingress DMA Threshold Warning time (in Hz) and Warning Repeat Rate
97 * (in RX_QCHECK_PERIOD multiples). If we find one of the SGE Ingress DMA
98 * State Machines in the same state for this amount of time (in HZ) then we'll
99 * issue a warning about a potential hang. We'll repeat the warning as the
100 * SGE Ingress DMA Channel appears to be hung every N RX_QCHECK_PERIODs till
101 * the situation clears. If the situation clears, we'll note that as well.
103 #define SGE_IDMA_WARN_THRESH (1 * HZ)
104 #define SGE_IDMA_WARN_REPEAT (20 * RX_QCHECK_PERIOD)
107 * Max number of Tx descriptors to be reclaimed by the Tx timer.
109 #define MAX_TIMER_TX_RECLAIM 100
112 * Timer index used when backing off due to memory shortage.
114 #define NOMEM_TMR_IDX (SGE_NTIMERS - 1)
117 * An FL with <= FL_STARVE_THRES buffers is starving and a periodic timer will
118 * attempt to refill it.
120 #define FL_STARVE_THRES 4
123 * Suspend an Ethernet Tx queue with fewer available descriptors than this.
124 * This is the same as calc_tx_descs() for a TSO packet with
125 * nr_frags == MAX_SKB_FRAGS.
127 #define ETHTXQ_STOP_THRES \
128 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
131 * Suspension threshold for non-Ethernet Tx queues. We require enough room
132 * for a full sized WR.
134 #define TXQ_STOP_THRES (SGE_MAX_WR_LEN / sizeof(struct tx_desc))
137 * Max Tx descriptor space we allow for an Ethernet packet to be inlined
140 #define MAX_IMM_TX_PKT_LEN 128
143 * Max size of a WR sent through a control Tx queue.
145 #define MAX_CTRL_WR_LEN SGE_MAX_WR_LEN
147 struct tx_sw_desc { /* SW state per Tx descriptor */
149 struct ulptx_sgl *sgl;
152 struct rx_sw_desc { /* SW state per Rx descriptor */
158 * Rx buffer sizes for "useskbs" Free List buffers (one ingress packet pe skb
159 * buffer). We currently only support two sizes for 1500- and 9000-byte MTUs.
160 * We could easily support more but there doesn't seem to be much need for
163 #define FL_MTU_SMALL 1500
164 #define FL_MTU_LARGE 9000
166 static inline unsigned int fl_mtu_bufsize(struct adapter *adapter,
169 struct sge *s = &adapter->sge;
171 return ALIGN(s->pktshift + ETH_HLEN + VLAN_HLEN + mtu, s->fl_align);
174 #define FL_MTU_SMALL_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_SMALL)
175 #define FL_MTU_LARGE_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_LARGE)
178 * Bits 0..3 of rx_sw_desc.dma_addr have special meaning. The hardware uses
179 * these to specify the buffer size as an index into the SGE Free List Buffer
180 * Size register array. We also use bit 4, when the buffer has been unmapped
181 * for DMA, but this is of course never sent to the hardware and is only used
182 * to prevent double unmappings. All of the above requires that the Free List
183 * Buffers which we allocate have the bottom 5 bits free (0) -- i.e. are
184 * 32-byte or or a power of 2 greater in alignment. Since the SGE's minimal
185 * Free List Buffer alignment is 32 bytes, this works out for us ...
188 RX_BUF_FLAGS = 0x1f, /* bottom five bits are special */
189 RX_BUF_SIZE = 0x0f, /* bottom three bits are for buf sizes */
190 RX_UNMAPPED_BUF = 0x10, /* buffer is not mapped */
193 * XXX We shouldn't depend on being able to use these indices.
194 * XXX Especially when some other Master PF has initialized the
195 * XXX adapter or we use the Firmware Configuration File. We
196 * XXX should really search through the Host Buffer Size register
197 * XXX array for the appropriately sized buffer indices.
199 RX_SMALL_PG_BUF = 0x0, /* small (PAGE_SIZE) page buffer */
200 RX_LARGE_PG_BUF = 0x1, /* buffer large (FL_PG_ORDER) page buffer */
202 RX_SMALL_MTU_BUF = 0x2, /* small MTU buffer */
203 RX_LARGE_MTU_BUF = 0x3, /* large MTU buffer */
206 static inline dma_addr_t get_buf_addr(const struct rx_sw_desc *d)
208 return d->dma_addr & ~(dma_addr_t)RX_BUF_FLAGS;
211 static inline bool is_buf_mapped(const struct rx_sw_desc *d)
213 return !(d->dma_addr & RX_UNMAPPED_BUF);
217 * txq_avail - return the number of available slots in a Tx queue
220 * Returns the number of descriptors in a Tx queue available to write new
223 static inline unsigned int txq_avail(const struct sge_txq *q)
225 return q->size - 1 - q->in_use;
229 * fl_cap - return the capacity of a free-buffer list
232 * Returns the capacity of a free-buffer list. The capacity is less than
233 * the size because one descriptor needs to be left unpopulated, otherwise
234 * HW will think the FL is empty.
236 static inline unsigned int fl_cap(const struct sge_fl *fl)
238 return fl->size - 8; /* 1 descriptor = 8 buffers */
241 static inline bool fl_starving(const struct sge_fl *fl)
243 return fl->avail - fl->pend_cred <= FL_STARVE_THRES;
246 static int map_skb(struct device *dev, const struct sk_buff *skb,
249 const skb_frag_t *fp, *end;
250 const struct skb_shared_info *si;
252 *addr = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
253 if (dma_mapping_error(dev, *addr))
256 si = skb_shinfo(skb);
257 end = &si->frags[si->nr_frags];
259 for (fp = si->frags; fp < end; fp++) {
260 *++addr = skb_frag_dma_map(dev, fp, 0, skb_frag_size(fp),
262 if (dma_mapping_error(dev, *addr))
268 while (fp-- > si->frags)
269 dma_unmap_page(dev, *--addr, skb_frag_size(fp), DMA_TO_DEVICE);
271 dma_unmap_single(dev, addr[-1], skb_headlen(skb), DMA_TO_DEVICE);
276 #ifdef CONFIG_NEED_DMA_MAP_STATE
277 static void unmap_skb(struct device *dev, const struct sk_buff *skb,
278 const dma_addr_t *addr)
280 const skb_frag_t *fp, *end;
281 const struct skb_shared_info *si;
283 dma_unmap_single(dev, *addr++, skb_headlen(skb), DMA_TO_DEVICE);
285 si = skb_shinfo(skb);
286 end = &si->frags[si->nr_frags];
287 for (fp = si->frags; fp < end; fp++)
288 dma_unmap_page(dev, *addr++, skb_frag_size(fp), DMA_TO_DEVICE);
292 * deferred_unmap_destructor - unmap a packet when it is freed
295 * This is the packet destructor used for Tx packets that need to remain
296 * mapped until they are freed rather than until their Tx descriptors are
299 static void deferred_unmap_destructor(struct sk_buff *skb)
301 unmap_skb(skb->dev->dev.parent, skb, (dma_addr_t *)skb->head);
305 static void unmap_sgl(struct device *dev, const struct sk_buff *skb,
306 const struct ulptx_sgl *sgl, const struct sge_txq *q)
308 const struct ulptx_sge_pair *p;
309 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
311 if (likely(skb_headlen(skb)))
312 dma_unmap_single(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0),
315 dma_unmap_page(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0),
321 * the complexity below is because of the possibility of a wrap-around
322 * in the middle of an SGL
324 for (p = sgl->sge; nfrags >= 2; nfrags -= 2) {
325 if (likely((u8 *)(p + 1) <= (u8 *)q->stat)) {
326 unmap: dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
327 ntohl(p->len[0]), DMA_TO_DEVICE);
328 dma_unmap_page(dev, be64_to_cpu(p->addr[1]),
329 ntohl(p->len[1]), DMA_TO_DEVICE);
331 } else if ((u8 *)p == (u8 *)q->stat) {
332 p = (const struct ulptx_sge_pair *)q->desc;
334 } else if ((u8 *)p + 8 == (u8 *)q->stat) {
335 const __be64 *addr = (const __be64 *)q->desc;
337 dma_unmap_page(dev, be64_to_cpu(addr[0]),
338 ntohl(p->len[0]), DMA_TO_DEVICE);
339 dma_unmap_page(dev, be64_to_cpu(addr[1]),
340 ntohl(p->len[1]), DMA_TO_DEVICE);
341 p = (const struct ulptx_sge_pair *)&addr[2];
343 const __be64 *addr = (const __be64 *)q->desc;
345 dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
346 ntohl(p->len[0]), DMA_TO_DEVICE);
347 dma_unmap_page(dev, be64_to_cpu(addr[0]),
348 ntohl(p->len[1]), DMA_TO_DEVICE);
349 p = (const struct ulptx_sge_pair *)&addr[1];
355 if ((u8 *)p == (u8 *)q->stat)
356 p = (const struct ulptx_sge_pair *)q->desc;
357 addr = (u8 *)p + 16 <= (u8 *)q->stat ? p->addr[0] :
358 *(const __be64 *)q->desc;
359 dma_unmap_page(dev, be64_to_cpu(addr), ntohl(p->len[0]),
365 * free_tx_desc - reclaims Tx descriptors and their buffers
366 * @adapter: the adapter
367 * @q: the Tx queue to reclaim descriptors from
368 * @n: the number of descriptors to reclaim
369 * @unmap: whether the buffers should be unmapped for DMA
371 * Reclaims Tx descriptors from an SGE Tx queue and frees the associated
372 * Tx buffers. Called with the Tx queue lock held.
374 static void free_tx_desc(struct adapter *adap, struct sge_txq *q,
375 unsigned int n, bool unmap)
377 struct tx_sw_desc *d;
378 unsigned int cidx = q->cidx;
379 struct device *dev = adap->pdev_dev;
383 if (d->skb) { /* an SGL is present */
385 unmap_sgl(dev, d->skb, d->sgl, q);
390 if (++cidx == q->size) {
399 * Return the number of reclaimable descriptors in a Tx queue.
401 static inline int reclaimable(const struct sge_txq *q)
403 int hw_cidx = ntohs(q->stat->cidx);
405 return hw_cidx < 0 ? hw_cidx + q->size : hw_cidx;
409 * reclaim_completed_tx - reclaims completed Tx descriptors
411 * @q: the Tx queue to reclaim completed descriptors from
412 * @unmap: whether the buffers should be unmapped for DMA
414 * Reclaims Tx descriptors that the SGE has indicated it has processed,
415 * and frees the associated buffers if possible. Called with the Tx
418 static inline void reclaim_completed_tx(struct adapter *adap, struct sge_txq *q,
421 int avail = reclaimable(q);
425 * Limit the amount of clean up work we do at a time to keep
426 * the Tx lock hold time O(1).
428 if (avail > MAX_TX_RECLAIM)
429 avail = MAX_TX_RECLAIM;
431 free_tx_desc(adap, q, avail, unmap);
436 static inline int get_buf_size(struct adapter *adapter,
437 const struct rx_sw_desc *d)
439 struct sge *s = &adapter->sge;
440 unsigned int rx_buf_size_idx = d->dma_addr & RX_BUF_SIZE;
443 switch (rx_buf_size_idx) {
444 case RX_SMALL_PG_BUF:
445 buf_size = PAGE_SIZE;
448 case RX_LARGE_PG_BUF:
449 buf_size = PAGE_SIZE << s->fl_pg_order;
452 case RX_SMALL_MTU_BUF:
453 buf_size = FL_MTU_SMALL_BUFSIZE(adapter);
456 case RX_LARGE_MTU_BUF:
457 buf_size = FL_MTU_LARGE_BUFSIZE(adapter);
468 * free_rx_bufs - free the Rx buffers on an SGE free list
470 * @q: the SGE free list to free buffers from
471 * @n: how many buffers to free
473 * Release the next @n buffers on an SGE free-buffer Rx queue. The
474 * buffers must be made inaccessible to HW before calling this function.
476 static void free_rx_bufs(struct adapter *adap, struct sge_fl *q, int n)
479 struct rx_sw_desc *d = &q->sdesc[q->cidx];
481 if (is_buf_mapped(d))
482 dma_unmap_page(adap->pdev_dev, get_buf_addr(d),
483 get_buf_size(adap, d),
487 if (++q->cidx == q->size)
494 * unmap_rx_buf - unmap the current Rx buffer on an SGE free list
496 * @q: the SGE free list
498 * Unmap the current buffer on an SGE free-buffer Rx queue. The
499 * buffer must be made inaccessible to HW before calling this function.
501 * This is similar to @free_rx_bufs above but does not free the buffer.
502 * Do note that the FL still loses any further access to the buffer.
504 static void unmap_rx_buf(struct adapter *adap, struct sge_fl *q)
506 struct rx_sw_desc *d = &q->sdesc[q->cidx];
508 if (is_buf_mapped(d))
509 dma_unmap_page(adap->pdev_dev, get_buf_addr(d),
510 get_buf_size(adap, d), PCI_DMA_FROMDEVICE);
512 if (++q->cidx == q->size)
517 static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
520 if (q->pend_cred >= 8) {
521 val = PIDX(q->pend_cred / 8);
522 if (!is_t4(adap->params.chip))
525 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), DBPRIO(1) |
526 QID(q->cntxt_id) | val);
531 static inline void set_rx_sw_desc(struct rx_sw_desc *sd, struct page *pg,
535 sd->dma_addr = mapping; /* includes size low bits */
539 * refill_fl - refill an SGE Rx buffer ring
541 * @q: the ring to refill
542 * @n: the number of new buffers to allocate
543 * @gfp: the gfp flags for the allocations
545 * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,
546 * allocated with the supplied gfp flags. The caller must assure that
547 * @n does not exceed the queue's capacity. If afterwards the queue is
548 * found critically low mark it as starving in the bitmap of starving FLs.
550 * Returns the number of buffers allocated.
552 static unsigned int refill_fl(struct adapter *adap, struct sge_fl *q, int n,
555 struct sge *s = &adap->sge;
558 unsigned int cred = q->avail;
559 __be64 *d = &q->desc[q->pidx];
560 struct rx_sw_desc *sd = &q->sdesc[q->pidx];
562 gfp |= __GFP_NOWARN | __GFP_COLD;
564 if (s->fl_pg_order == 0)
565 goto alloc_small_pages;
568 * Prefer large buffers
571 pg = alloc_pages(gfp | __GFP_COMP, s->fl_pg_order);
573 q->large_alloc_failed++;
574 break; /* fall back to single pages */
577 mapping = dma_map_page(adap->pdev_dev, pg, 0,
578 PAGE_SIZE << s->fl_pg_order,
580 if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) {
581 __free_pages(pg, s->fl_pg_order);
582 goto out; /* do not try small pages for this error */
584 mapping |= RX_LARGE_PG_BUF;
585 *d++ = cpu_to_be64(mapping);
587 set_rx_sw_desc(sd, pg, mapping);
591 if (++q->pidx == q->size) {
601 pg = __skb_alloc_page(gfp, NULL);
607 mapping = dma_map_page(adap->pdev_dev, pg, 0, PAGE_SIZE,
609 if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) {
613 *d++ = cpu_to_be64(mapping);
615 set_rx_sw_desc(sd, pg, mapping);
619 if (++q->pidx == q->size) {
626 out: cred = q->avail - cred;
627 q->pend_cred += cred;
630 if (unlikely(fl_starving(q))) {
632 set_bit(q->cntxt_id - adap->sge.egr_start,
633 adap->sge.starving_fl);
639 static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl)
641 refill_fl(adap, fl, min(MAX_RX_REFILL, fl_cap(fl) - fl->avail),
646 * alloc_ring - allocate resources for an SGE descriptor ring
647 * @dev: the PCI device's core device
648 * @nelem: the number of descriptors
649 * @elem_size: the size of each descriptor
650 * @sw_size: the size of the SW state associated with each ring element
651 * @phys: the physical address of the allocated ring
652 * @metadata: address of the array holding the SW state for the ring
653 * @stat_size: extra space in HW ring for status information
654 * @node: preferred node for memory allocations
656 * Allocates resources for an SGE descriptor ring, such as Tx queues,
657 * free buffer lists, or response queues. Each SGE ring requires
658 * space for its HW descriptors plus, optionally, space for the SW state
659 * associated with each HW entry (the metadata). The function returns
660 * three values: the virtual address for the HW ring (the return value
661 * of the function), the bus address of the HW ring, and the address
664 static void *alloc_ring(struct device *dev, size_t nelem, size_t elem_size,
665 size_t sw_size, dma_addr_t *phys, void *metadata,
666 size_t stat_size, int node)
668 size_t len = nelem * elem_size + stat_size;
670 void *p = dma_alloc_coherent(dev, len, phys, GFP_KERNEL);
675 s = kzalloc_node(nelem * sw_size, GFP_KERNEL, node);
678 dma_free_coherent(dev, len, p, *phys);
683 *(void **)metadata = s;
689 * sgl_len - calculates the size of an SGL of the given capacity
690 * @n: the number of SGL entries
692 * Calculates the number of flits needed for a scatter/gather list that
693 * can hold the given number of entries.
695 static inline unsigned int sgl_len(unsigned int n)
698 return (3 * n) / 2 + (n & 1) + 2;
702 * flits_to_desc - returns the num of Tx descriptors for the given flits
703 * @n: the number of flits
705 * Returns the number of Tx descriptors needed for the supplied number
708 static inline unsigned int flits_to_desc(unsigned int n)
710 BUG_ON(n > SGE_MAX_WR_LEN / 8);
711 return DIV_ROUND_UP(n, 8);
715 * is_eth_imm - can an Ethernet packet be sent as immediate data?
718 * Returns whether an Ethernet packet is small enough to fit as
719 * immediate data. Return value corresponds to headroom required.
721 static inline int is_eth_imm(const struct sk_buff *skb)
723 int hdrlen = skb_shinfo(skb)->gso_size ?
724 sizeof(struct cpl_tx_pkt_lso_core) : 0;
726 hdrlen += sizeof(struct cpl_tx_pkt);
727 if (skb->len <= MAX_IMM_TX_PKT_LEN - hdrlen)
733 * calc_tx_flits - calculate the number of flits for a packet Tx WR
736 * Returns the number of flits needed for a Tx WR for the given Ethernet
737 * packet, including the needed WR and CPL headers.
739 static inline unsigned int calc_tx_flits(const struct sk_buff *skb)
742 int hdrlen = is_eth_imm(skb);
745 return DIV_ROUND_UP(skb->len + hdrlen, sizeof(__be64));
747 flits = sgl_len(skb_shinfo(skb)->nr_frags + 1) + 4;
748 if (skb_shinfo(skb)->gso_size)
754 * calc_tx_descs - calculate the number of Tx descriptors for a packet
757 * Returns the number of Tx descriptors needed for the given Ethernet
758 * packet, including the needed WR and CPL headers.
760 static inline unsigned int calc_tx_descs(const struct sk_buff *skb)
762 return flits_to_desc(calc_tx_flits(skb));
766 * write_sgl - populate a scatter/gather list for a packet
768 * @q: the Tx queue we are writing into
769 * @sgl: starting location for writing the SGL
770 * @end: points right after the end of the SGL
771 * @start: start offset into skb main-body data to include in the SGL
772 * @addr: the list of bus addresses for the SGL elements
774 * Generates a gather list for the buffers that make up a packet.
775 * The caller must provide adequate space for the SGL that will be written.
776 * The SGL includes all of the packet's page fragments and the data in its
777 * main body except for the first @start bytes. @sgl must be 16-byte
778 * aligned and within a Tx descriptor with available space. @end points
779 * right after the end of the SGL but does not account for any potential
780 * wrap around, i.e., @end > @sgl.
782 static void write_sgl(const struct sk_buff *skb, struct sge_txq *q,
783 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
784 const dma_addr_t *addr)
787 struct ulptx_sge_pair *to;
788 const struct skb_shared_info *si = skb_shinfo(skb);
789 unsigned int nfrags = si->nr_frags;
790 struct ulptx_sge_pair buf[MAX_SKB_FRAGS / 2 + 1];
792 len = skb_headlen(skb) - start;
794 sgl->len0 = htonl(len);
795 sgl->addr0 = cpu_to_be64(addr[0] + start);
798 sgl->len0 = htonl(skb_frag_size(&si->frags[0]));
799 sgl->addr0 = cpu_to_be64(addr[1]);
802 sgl->cmd_nsge = htonl(ULPTX_CMD(ULP_TX_SC_DSGL) | ULPTX_NSGE(nfrags));
803 if (likely(--nfrags == 0))
806 * Most of the complexity below deals with the possibility we hit the
807 * end of the queue in the middle of writing the SGL. For this case
808 * only we create the SGL in a temporary buffer and then copy it.
810 to = (u8 *)end > (u8 *)q->stat ? buf : sgl->sge;
812 for (i = (nfrags != si->nr_frags); nfrags >= 2; nfrags -= 2, to++) {
813 to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i]));
814 to->len[1] = cpu_to_be32(skb_frag_size(&si->frags[++i]));
815 to->addr[0] = cpu_to_be64(addr[i]);
816 to->addr[1] = cpu_to_be64(addr[++i]);
819 to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i]));
820 to->len[1] = cpu_to_be32(0);
821 to->addr[0] = cpu_to_be64(addr[i + 1]);
823 if (unlikely((u8 *)end > (u8 *)q->stat)) {
824 unsigned int part0 = (u8 *)q->stat - (u8 *)sgl->sge, part1;
827 memcpy(sgl->sge, buf, part0);
828 part1 = (u8 *)end - (u8 *)q->stat;
829 memcpy(q->desc, (u8 *)buf + part0, part1);
830 end = (void *)q->desc + part1;
832 if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */
836 /* This function copies 64 byte coalesced work request to
837 * memory mapped BAR2 space(user space writes).
838 * For coalesced WR SGE, fetches data from the FIFO instead of from Host.
840 static void cxgb_pio_copy(u64 __iomem *dst, u64 *src)
853 * ring_tx_db - check and potentially ring a Tx queue's doorbell
856 * @n: number of new descriptors to give to HW
858 * Ring the doorbel for a Tx queue.
860 static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
862 unsigned int *wr, index;
864 wmb(); /* write descriptors before telling HW */
865 spin_lock(&q->db_lock);
866 if (!q->db_disabled) {
867 if (is_t4(adap->params.chip)) {
868 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
869 QID(q->cntxt_id) | PIDX(n));
872 index = q->pidx ? (q->pidx - 1) : (q->size - 1);
873 wr = (unsigned int *)&q->desc[index];
874 cxgb_pio_copy((u64 __iomem *)
875 (adap->bar2 + q->udb + 64),
878 writel(n, adap->bar2 + q->udb + 8);
882 q->db_pidx = q->pidx;
883 spin_unlock(&q->db_lock);
887 * inline_tx_skb - inline a packet's data into Tx descriptors
889 * @q: the Tx queue where the packet will be inlined
890 * @pos: starting position in the Tx queue where to inline the packet
892 * Inline a packet's contents directly into Tx descriptors, starting at
893 * the given position within the Tx DMA ring.
894 * Most of the complexity of this operation is dealing with wrap arounds
895 * in the middle of the packet we want to inline.
897 static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
901 int left = (void *)q->stat - pos;
903 if (likely(skb->len <= left)) {
904 if (likely(!skb->data_len))
905 skb_copy_from_linear_data(skb, pos, skb->len);
907 skb_copy_bits(skb, 0, pos, skb->len);
910 skb_copy_bits(skb, 0, pos, left);
911 skb_copy_bits(skb, left, q->desc, skb->len - left);
912 pos = (void *)q->desc + (skb->len - left);
915 /* 0-pad to multiple of 16 */
916 p = PTR_ALIGN(pos, 8);
917 if ((uintptr_t)p & 8)
922 * Figure out what HW csum a packet wants and return the appropriate control
925 static u64 hwcsum(const struct sk_buff *skb)
928 const struct iphdr *iph = ip_hdr(skb);
930 if (iph->version == 4) {
931 if (iph->protocol == IPPROTO_TCP)
932 csum_type = TX_CSUM_TCPIP;
933 else if (iph->protocol == IPPROTO_UDP)
934 csum_type = TX_CSUM_UDPIP;
937 * unknown protocol, disable HW csum
938 * and hope a bad packet is detected
940 return TXPKT_L4CSUM_DIS;
944 * this doesn't work with extension headers
946 const struct ipv6hdr *ip6h = (const struct ipv6hdr *)iph;
948 if (ip6h->nexthdr == IPPROTO_TCP)
949 csum_type = TX_CSUM_TCPIP6;
950 else if (ip6h->nexthdr == IPPROTO_UDP)
951 csum_type = TX_CSUM_UDPIP6;
956 if (likely(csum_type >= TX_CSUM_TCPIP))
957 return TXPKT_CSUM_TYPE(csum_type) |
958 TXPKT_IPHDR_LEN(skb_network_header_len(skb)) |
959 TXPKT_ETHHDR_LEN(skb_network_offset(skb) - ETH_HLEN);
961 int start = skb_transport_offset(skb);
963 return TXPKT_CSUM_TYPE(csum_type) | TXPKT_CSUM_START(start) |
964 TXPKT_CSUM_LOC(start + skb->csum_offset);
968 static void eth_txq_stop(struct sge_eth_txq *q)
970 netif_tx_stop_queue(q->txq);
974 static inline void txq_advance(struct sge_txq *q, unsigned int n)
978 if (q->pidx >= q->size)
983 * t4_eth_xmit - add a packet to an Ethernet Tx queue
985 * @dev: the egress net device
987 * Add a packet to an SGE Ethernet Tx queue. Runs with softirqs disabled.
989 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev)
995 unsigned int flits, ndesc;
996 struct adapter *adap;
997 struct sge_eth_txq *q;
998 const struct port_info *pi;
999 struct fw_eth_tx_pkt_wr *wr;
1000 struct cpl_tx_pkt_core *cpl;
1001 const struct skb_shared_info *ssi;
1002 dma_addr_t addr[MAX_SKB_FRAGS + 1];
1003 bool immediate = false;
1006 * The chip min packet length is 10 octets but play safe and reject
1007 * anything shorter than an Ethernet header.
1009 if (unlikely(skb->len < ETH_HLEN)) {
1010 out_free: dev_kfree_skb(skb);
1011 return NETDEV_TX_OK;
1014 pi = netdev_priv(dev);
1016 qidx = skb_get_queue_mapping(skb);
1017 q = &adap->sge.ethtxq[qidx + pi->first_qset];
1019 reclaim_completed_tx(adap, &q->q, true);
1021 flits = calc_tx_flits(skb);
1022 ndesc = flits_to_desc(flits);
1023 credits = txq_avail(&q->q) - ndesc;
1025 if (unlikely(credits < 0)) {
1027 dev_err(adap->pdev_dev,
1028 "%s: Tx ring %u full while queue awake!\n",
1030 return NETDEV_TX_BUSY;
1033 if (is_eth_imm(skb))
1037 unlikely(map_skb(adap->pdev_dev, skb, addr) < 0)) {
1042 wr_mid = FW_WR_LEN16(DIV_ROUND_UP(flits, 2));
1043 if (unlikely(credits < ETHTXQ_STOP_THRES)) {
1045 wr_mid |= FW_WR_EQUEQ | FW_WR_EQUIQ;
1048 wr = (void *)&q->q.desc[q->q.pidx];
1049 wr->equiq_to_len16 = htonl(wr_mid);
1050 wr->r3 = cpu_to_be64(0);
1051 end = (u64 *)wr + flits;
1053 len = immediate ? skb->len : 0;
1054 ssi = skb_shinfo(skb);
1055 if (ssi->gso_size) {
1056 struct cpl_tx_pkt_lso *lso = (void *)wr;
1057 bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0;
1058 int l3hdr_len = skb_network_header_len(skb);
1059 int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN;
1061 len += sizeof(*lso);
1062 wr->op_immdlen = htonl(FW_WR_OP(FW_ETH_TX_PKT_WR) |
1063 FW_WR_IMMDLEN(len));
1064 lso->c.lso_ctrl = htonl(LSO_OPCODE(CPL_TX_PKT_LSO) |
1065 LSO_FIRST_SLICE | LSO_LAST_SLICE |
1067 LSO_ETHHDR_LEN(eth_xtra_len / 4) |
1068 LSO_IPHDR_LEN(l3hdr_len / 4) |
1069 LSO_TCPHDR_LEN(tcp_hdr(skb)->doff));
1070 lso->c.ipid_ofst = htons(0);
1071 lso->c.mss = htons(ssi->gso_size);
1072 lso->c.seqno_offset = htonl(0);
1073 lso->c.len = htonl(skb->len);
1074 cpl = (void *)(lso + 1);
1075 cntrl = TXPKT_CSUM_TYPE(v6 ? TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
1076 TXPKT_IPHDR_LEN(l3hdr_len) |
1077 TXPKT_ETHHDR_LEN(eth_xtra_len);
1079 q->tx_cso += ssi->gso_segs;
1081 len += sizeof(*cpl);
1082 wr->op_immdlen = htonl(FW_WR_OP(FW_ETH_TX_PKT_WR) |
1083 FW_WR_IMMDLEN(len));
1084 cpl = (void *)(wr + 1);
1085 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1086 cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS;
1089 cntrl = TXPKT_L4CSUM_DIS | TXPKT_IPCSUM_DIS;
1092 if (vlan_tx_tag_present(skb)) {
1094 cntrl |= TXPKT_VLAN_VLD | TXPKT_VLAN(vlan_tx_tag_get(skb));
1097 cpl->ctrl0 = htonl(TXPKT_OPCODE(CPL_TX_PKT_XT) |
1098 TXPKT_INTF(pi->tx_chan) | TXPKT_PF(adap->fn));
1099 cpl->pack = htons(0);
1100 cpl->len = htons(skb->len);
1101 cpl->ctrl1 = cpu_to_be64(cntrl);
1104 inline_tx_skb(skb, &q->q, cpl + 1);
1109 write_sgl(skb, &q->q, (struct ulptx_sgl *)(cpl + 1), end, 0,
1113 last_desc = q->q.pidx + ndesc - 1;
1114 if (last_desc >= q->q.size)
1115 last_desc -= q->q.size;
1116 q->q.sdesc[last_desc].skb = skb;
1117 q->q.sdesc[last_desc].sgl = (struct ulptx_sgl *)(cpl + 1);
1120 txq_advance(&q->q, ndesc);
1122 ring_tx_db(adap, &q->q, ndesc);
1123 return NETDEV_TX_OK;
1127 * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs
1128 * @q: the SGE control Tx queue
1130 * This is a variant of reclaim_completed_tx() that is used for Tx queues
1131 * that send only immediate data (presently just the control queues) and
1132 * thus do not have any sk_buffs to release.
1134 static inline void reclaim_completed_tx_imm(struct sge_txq *q)
1136 int hw_cidx = ntohs(q->stat->cidx);
1137 int reclaim = hw_cidx - q->cidx;
1142 q->in_use -= reclaim;
1147 * is_imm - check whether a packet can be sent as immediate data
1150 * Returns true if a packet can be sent as a WR with immediate data.
1152 static inline int is_imm(const struct sk_buff *skb)
1154 return skb->len <= MAX_CTRL_WR_LEN;
1158 * ctrlq_check_stop - check if a control queue is full and should stop
1160 * @wr: most recent WR written to the queue
1162 * Check if a control queue has become full and should be stopped.
1163 * We clean up control queue descriptors very lazily, only when we are out.
1164 * If the queue is still full after reclaiming any completed descriptors
1165 * we suspend it and have the last WR wake it up.
1167 static void ctrlq_check_stop(struct sge_ctrl_txq *q, struct fw_wr_hdr *wr)
1169 reclaim_completed_tx_imm(&q->q);
1170 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) {
1171 wr->lo |= htonl(FW_WR_EQUEQ | FW_WR_EQUIQ);
1178 * ctrl_xmit - send a packet through an SGE control Tx queue
1179 * @q: the control queue
1182 * Send a packet through an SGE control Tx queue. Packets sent through
1183 * a control queue must fit entirely as immediate data.
1185 static int ctrl_xmit(struct sge_ctrl_txq *q, struct sk_buff *skb)
1188 struct fw_wr_hdr *wr;
1190 if (unlikely(!is_imm(skb))) {
1193 return NET_XMIT_DROP;
1196 ndesc = DIV_ROUND_UP(skb->len, sizeof(struct tx_desc));
1197 spin_lock(&q->sendq.lock);
1199 if (unlikely(q->full)) {
1200 skb->priority = ndesc; /* save for restart */
1201 __skb_queue_tail(&q->sendq, skb);
1202 spin_unlock(&q->sendq.lock);
1206 wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx];
1207 inline_tx_skb(skb, &q->q, wr);
1209 txq_advance(&q->q, ndesc);
1210 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES))
1211 ctrlq_check_stop(q, wr);
1213 ring_tx_db(q->adap, &q->q, ndesc);
1214 spin_unlock(&q->sendq.lock);
1217 return NET_XMIT_SUCCESS;
1221 * restart_ctrlq - restart a suspended control queue
1222 * @data: the control queue to restart
1224 * Resumes transmission on a suspended Tx control queue.
1226 static void restart_ctrlq(unsigned long data)
1228 struct sk_buff *skb;
1229 unsigned int written = 0;
1230 struct sge_ctrl_txq *q = (struct sge_ctrl_txq *)data;
1232 spin_lock(&q->sendq.lock);
1233 reclaim_completed_tx_imm(&q->q);
1234 BUG_ON(txq_avail(&q->q) < TXQ_STOP_THRES); /* q should be empty */
1236 while ((skb = __skb_dequeue(&q->sendq)) != NULL) {
1237 struct fw_wr_hdr *wr;
1238 unsigned int ndesc = skb->priority; /* previously saved */
1241 * Write descriptors and free skbs outside the lock to limit
1242 * wait times. q->full is still set so new skbs will be queued.
1244 spin_unlock(&q->sendq.lock);
1246 wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx];
1247 inline_tx_skb(skb, &q->q, wr);
1251 txq_advance(&q->q, ndesc);
1252 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) {
1253 unsigned long old = q->q.stops;
1255 ctrlq_check_stop(q, wr);
1256 if (q->q.stops != old) { /* suspended anew */
1257 spin_lock(&q->sendq.lock);
1262 ring_tx_db(q->adap, &q->q, written);
1265 spin_lock(&q->sendq.lock);
1268 ringdb: if (written)
1269 ring_tx_db(q->adap, &q->q, written);
1270 spin_unlock(&q->sendq.lock);
1274 * t4_mgmt_tx - send a management message
1275 * @adap: the adapter
1276 * @skb: the packet containing the management message
1278 * Send a management message through control queue 0.
1280 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb)
1285 ret = ctrl_xmit(&adap->sge.ctrlq[0], skb);
1291 * is_ofld_imm - check whether a packet can be sent as immediate data
1294 * Returns true if a packet can be sent as an offload WR with immediate
1295 * data. We currently use the same limit as for Ethernet packets.
1297 static inline int is_ofld_imm(const struct sk_buff *skb)
1299 return skb->len <= MAX_IMM_TX_PKT_LEN;
1303 * calc_tx_flits_ofld - calculate # of flits for an offload packet
1306 * Returns the number of flits needed for the given offload packet.
1307 * These packets are already fully constructed and no additional headers
1310 static inline unsigned int calc_tx_flits_ofld(const struct sk_buff *skb)
1312 unsigned int flits, cnt;
1314 if (is_ofld_imm(skb))
1315 return DIV_ROUND_UP(skb->len, 8);
1317 flits = skb_transport_offset(skb) / 8U; /* headers */
1318 cnt = skb_shinfo(skb)->nr_frags;
1319 if (skb_tail_pointer(skb) != skb_transport_header(skb))
1321 return flits + sgl_len(cnt);
1325 * txq_stop_maperr - stop a Tx queue due to I/O MMU exhaustion
1326 * @adap: the adapter
1327 * @q: the queue to stop
1329 * Mark a Tx queue stopped due to I/O MMU exhaustion and resulting
1330 * inability to map packets. A periodic timer attempts to restart
1333 static void txq_stop_maperr(struct sge_ofld_txq *q)
1337 set_bit(q->q.cntxt_id - q->adap->sge.egr_start,
1338 q->adap->sge.txq_maperr);
1342 * ofldtxq_stop - stop an offload Tx queue that has become full
1343 * @q: the queue to stop
1344 * @skb: the packet causing the queue to become full
1346 * Stops an offload Tx queue that has become full and modifies the packet
1347 * being written to request a wakeup.
1349 static void ofldtxq_stop(struct sge_ofld_txq *q, struct sk_buff *skb)
1351 struct fw_wr_hdr *wr = (struct fw_wr_hdr *)skb->data;
1353 wr->lo |= htonl(FW_WR_EQUEQ | FW_WR_EQUIQ);
1359 * service_ofldq - restart a suspended offload queue
1360 * @q: the offload queue
1362 * Services an offload Tx queue by moving packets from its packet queue
1363 * to the HW Tx ring. The function starts and ends with the queue locked.
1365 static void service_ofldq(struct sge_ofld_txq *q)
1369 struct sk_buff *skb;
1370 unsigned int written = 0;
1371 unsigned int flits, ndesc;
1373 while ((skb = skb_peek(&q->sendq)) != NULL && !q->full) {
1375 * We drop the lock but leave skb on sendq, thus retaining
1376 * exclusive access to the state of the queue.
1378 spin_unlock(&q->sendq.lock);
1380 reclaim_completed_tx(q->adap, &q->q, false);
1382 flits = skb->priority; /* previously saved */
1383 ndesc = flits_to_desc(flits);
1384 credits = txq_avail(&q->q) - ndesc;
1385 BUG_ON(credits < 0);
1386 if (unlikely(credits < TXQ_STOP_THRES))
1387 ofldtxq_stop(q, skb);
1389 pos = (u64 *)&q->q.desc[q->q.pidx];
1390 if (is_ofld_imm(skb))
1391 inline_tx_skb(skb, &q->q, pos);
1392 else if (map_skb(q->adap->pdev_dev, skb,
1393 (dma_addr_t *)skb->head)) {
1395 spin_lock(&q->sendq.lock);
1398 int last_desc, hdr_len = skb_transport_offset(skb);
1400 memcpy(pos, skb->data, hdr_len);
1401 write_sgl(skb, &q->q, (void *)pos + hdr_len,
1402 pos + flits, hdr_len,
1403 (dma_addr_t *)skb->head);
1404 #ifdef CONFIG_NEED_DMA_MAP_STATE
1405 skb->dev = q->adap->port[0];
1406 skb->destructor = deferred_unmap_destructor;
1408 last_desc = q->q.pidx + ndesc - 1;
1409 if (last_desc >= q->q.size)
1410 last_desc -= q->q.size;
1411 q->q.sdesc[last_desc].skb = skb;
1414 txq_advance(&q->q, ndesc);
1416 if (unlikely(written > 32)) {
1417 ring_tx_db(q->adap, &q->q, written);
1421 spin_lock(&q->sendq.lock);
1422 __skb_unlink(skb, &q->sendq);
1423 if (is_ofld_imm(skb))
1426 if (likely(written))
1427 ring_tx_db(q->adap, &q->q, written);
1431 * ofld_xmit - send a packet through an offload queue
1432 * @q: the Tx offload queue
1435 * Send an offload packet through an SGE offload queue.
1437 static int ofld_xmit(struct sge_ofld_txq *q, struct sk_buff *skb)
1439 skb->priority = calc_tx_flits_ofld(skb); /* save for restart */
1440 spin_lock(&q->sendq.lock);
1441 __skb_queue_tail(&q->sendq, skb);
1442 if (q->sendq.qlen == 1)
1444 spin_unlock(&q->sendq.lock);
1445 return NET_XMIT_SUCCESS;
1449 * restart_ofldq - restart a suspended offload queue
1450 * @data: the offload queue to restart
1452 * Resumes transmission on a suspended Tx offload queue.
1454 static void restart_ofldq(unsigned long data)
1456 struct sge_ofld_txq *q = (struct sge_ofld_txq *)data;
1458 spin_lock(&q->sendq.lock);
1459 q->full = 0; /* the queue actually is completely empty now */
1461 spin_unlock(&q->sendq.lock);
1465 * skb_txq - return the Tx queue an offload packet should use
1468 * Returns the Tx queue an offload packet should use as indicated by bits
1469 * 1-15 in the packet's queue_mapping.
1471 static inline unsigned int skb_txq(const struct sk_buff *skb)
1473 return skb->queue_mapping >> 1;
1477 * is_ctrl_pkt - return whether an offload packet is a control packet
1480 * Returns whether an offload packet should use an OFLD or a CTRL
1481 * Tx queue as indicated by bit 0 in the packet's queue_mapping.
1483 static inline unsigned int is_ctrl_pkt(const struct sk_buff *skb)
1485 return skb->queue_mapping & 1;
1488 static inline int ofld_send(struct adapter *adap, struct sk_buff *skb)
1490 unsigned int idx = skb_txq(skb);
1492 if (unlikely(is_ctrl_pkt(skb))) {
1493 /* Single ctrl queue is a requirement for LE workaround path */
1494 if (adap->tids.nsftids)
1496 return ctrl_xmit(&adap->sge.ctrlq[idx], skb);
1498 return ofld_xmit(&adap->sge.ofldtxq[idx], skb);
1502 * t4_ofld_send - send an offload packet
1503 * @adap: the adapter
1506 * Sends an offload packet. We use the packet queue_mapping to select the
1507 * appropriate Tx queue as follows: bit 0 indicates whether the packet
1508 * should be sent as regular or control, bits 1-15 select the queue.
1510 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb)
1515 ret = ofld_send(adap, skb);
1521 * cxgb4_ofld_send - send an offload packet
1522 * @dev: the net device
1525 * Sends an offload packet. This is an exported version of @t4_ofld_send,
1526 * intended for ULDs.
1528 int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb)
1530 return t4_ofld_send(netdev2adap(dev), skb);
1532 EXPORT_SYMBOL(cxgb4_ofld_send);
1534 static inline void copy_frags(struct sk_buff *skb,
1535 const struct pkt_gl *gl, unsigned int offset)
1539 /* usually there's just one frag */
1540 __skb_fill_page_desc(skb, 0, gl->frags[0].page,
1541 gl->frags[0].offset + offset,
1542 gl->frags[0].size - offset);
1543 skb_shinfo(skb)->nr_frags = gl->nfrags;
1544 for (i = 1; i < gl->nfrags; i++)
1545 __skb_fill_page_desc(skb, i, gl->frags[i].page,
1546 gl->frags[i].offset,
1549 /* get a reference to the last page, we don't own it */
1550 get_page(gl->frags[gl->nfrags - 1].page);
1554 * cxgb4_pktgl_to_skb - build an sk_buff from a packet gather list
1555 * @gl: the gather list
1556 * @skb_len: size of sk_buff main body if it carries fragments
1557 * @pull_len: amount of data to move to the sk_buff's main body
1559 * Builds an sk_buff from the given packet gather list. Returns the
1560 * sk_buff or %NULL if sk_buff allocation failed.
1562 struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl,
1563 unsigned int skb_len, unsigned int pull_len)
1565 struct sk_buff *skb;
1568 * Below we rely on RX_COPY_THRES being less than the smallest Rx buffer
1569 * size, which is expected since buffers are at least PAGE_SIZEd.
1570 * In this case packets up to RX_COPY_THRES have only one fragment.
1572 if (gl->tot_len <= RX_COPY_THRES) {
1573 skb = dev_alloc_skb(gl->tot_len);
1576 __skb_put(skb, gl->tot_len);
1577 skb_copy_to_linear_data(skb, gl->va, gl->tot_len);
1579 skb = dev_alloc_skb(skb_len);
1582 __skb_put(skb, pull_len);
1583 skb_copy_to_linear_data(skb, gl->va, pull_len);
1585 copy_frags(skb, gl, pull_len);
1586 skb->len = gl->tot_len;
1587 skb->data_len = skb->len - pull_len;
1588 skb->truesize += skb->data_len;
1592 EXPORT_SYMBOL(cxgb4_pktgl_to_skb);
1595 * t4_pktgl_free - free a packet gather list
1596 * @gl: the gather list
1598 * Releases the pages of a packet gather list. We do not own the last
1599 * page on the list and do not free it.
1601 static void t4_pktgl_free(const struct pkt_gl *gl)
1604 const struct page_frag *p;
1606 for (p = gl->frags, n = gl->nfrags - 1; n--; p++)
1611 * Process an MPS trace packet. Give it an unused protocol number so it won't
1612 * be delivered to anyone and send it to the stack for capture.
1614 static noinline int handle_trace_pkt(struct adapter *adap,
1615 const struct pkt_gl *gl)
1617 struct sk_buff *skb;
1619 skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN);
1620 if (unlikely(!skb)) {
1625 if (is_t4(adap->params.chip))
1626 __skb_pull(skb, sizeof(struct cpl_trace_pkt));
1628 __skb_pull(skb, sizeof(struct cpl_t5_trace_pkt));
1630 skb_reset_mac_header(skb);
1631 skb->protocol = htons(0xffff);
1632 skb->dev = adap->port[0];
1633 netif_receive_skb(skb);
1637 static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl,
1638 const struct cpl_rx_pkt *pkt)
1640 struct adapter *adapter = rxq->rspq.adap;
1641 struct sge *s = &adapter->sge;
1643 struct sk_buff *skb;
1645 skb = napi_get_frags(&rxq->rspq.napi);
1646 if (unlikely(!skb)) {
1648 rxq->stats.rx_drops++;
1652 copy_frags(skb, gl, s->pktshift);
1653 skb->len = gl->tot_len - s->pktshift;
1654 skb->data_len = skb->len;
1655 skb->truesize += skb->data_len;
1656 skb->ip_summed = CHECKSUM_UNNECESSARY;
1657 skb_record_rx_queue(skb, rxq->rspq.idx);
1658 if (rxq->rspq.netdev->features & NETIF_F_RXHASH)
1659 skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val,
1662 if (unlikely(pkt->vlan_ex)) {
1663 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan));
1664 rxq->stats.vlan_ex++;
1666 ret = napi_gro_frags(&rxq->rspq.napi);
1667 if (ret == GRO_HELD)
1668 rxq->stats.lro_pkts++;
1669 else if (ret == GRO_MERGED || ret == GRO_MERGED_FREE)
1670 rxq->stats.lro_merged++;
1672 rxq->stats.rx_cso++;
1676 * t4_ethrx_handler - process an ingress ethernet packet
1677 * @q: the response queue that received the packet
1678 * @rsp: the response queue descriptor holding the RX_PKT message
1679 * @si: the gather list of packet fragments
1681 * Process an ingress ethernet packet and deliver it to the stack.
1683 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1684 const struct pkt_gl *si)
1687 struct sk_buff *skb;
1688 const struct cpl_rx_pkt *pkt;
1689 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
1690 struct sge *s = &q->adap->sge;
1691 int cpl_trace_pkt = is_t4(q->adap->params.chip) ?
1692 CPL_TRACE_PKT : CPL_TRACE_PKT_T5;
1694 if (unlikely(*(u8 *)rsp == cpl_trace_pkt))
1695 return handle_trace_pkt(q->adap, si);
1697 pkt = (const struct cpl_rx_pkt *)rsp;
1698 csum_ok = pkt->csum_calc && !pkt->err_vec;
1699 if ((pkt->l2info & htonl(RXF_TCP)) &&
1700 (q->netdev->features & NETIF_F_GRO) && csum_ok && !pkt->ip_frag) {
1701 do_gro(rxq, si, pkt);
1705 skb = cxgb4_pktgl_to_skb(si, RX_PKT_SKB_LEN, RX_PULL_LEN);
1706 if (unlikely(!skb)) {
1708 rxq->stats.rx_drops++;
1712 __skb_pull(skb, s->pktshift); /* remove ethernet header padding */
1713 skb->protocol = eth_type_trans(skb, q->netdev);
1714 skb_record_rx_queue(skb, q->idx);
1715 if (skb->dev->features & NETIF_F_RXHASH)
1716 skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val,
1721 if (csum_ok && (q->netdev->features & NETIF_F_RXCSUM) &&
1722 (pkt->l2info & htonl(RXF_UDP | RXF_TCP))) {
1723 if (!pkt->ip_frag) {
1724 skb->ip_summed = CHECKSUM_UNNECESSARY;
1725 rxq->stats.rx_cso++;
1726 } else if (pkt->l2info & htonl(RXF_IP)) {
1727 __sum16 c = (__force __sum16)pkt->csum;
1728 skb->csum = csum_unfold(c);
1729 skb->ip_summed = CHECKSUM_COMPLETE;
1730 rxq->stats.rx_cso++;
1733 skb_checksum_none_assert(skb);
1735 if (unlikely(pkt->vlan_ex)) {
1736 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan));
1737 rxq->stats.vlan_ex++;
1739 netif_receive_skb(skb);
1744 * restore_rx_bufs - put back a packet's Rx buffers
1745 * @si: the packet gather list
1746 * @q: the SGE free list
1747 * @frags: number of FL buffers to restore
1749 * Puts back on an FL the Rx buffers associated with @si. The buffers
1750 * have already been unmapped and are left unmapped, we mark them so to
1751 * prevent further unmapping attempts.
1753 * This function undoes a series of @unmap_rx_buf calls when we find out
1754 * that the current packet can't be processed right away afterall and we
1755 * need to come back to it later. This is a very rare event and there's
1756 * no effort to make this particularly efficient.
1758 static void restore_rx_bufs(const struct pkt_gl *si, struct sge_fl *q,
1761 struct rx_sw_desc *d;
1765 q->cidx = q->size - 1;
1768 d = &q->sdesc[q->cidx];
1769 d->page = si->frags[frags].page;
1770 d->dma_addr |= RX_UNMAPPED_BUF;
1776 * is_new_response - check if a response is newly written
1777 * @r: the response descriptor
1778 * @q: the response queue
1780 * Returns true if a response descriptor contains a yet unprocessed
1783 static inline bool is_new_response(const struct rsp_ctrl *r,
1784 const struct sge_rspq *q)
1786 return RSPD_GEN(r->type_gen) == q->gen;
1790 * rspq_next - advance to the next entry in a response queue
1793 * Updates the state of a response queue to advance it to the next entry.
1795 static inline void rspq_next(struct sge_rspq *q)
1797 q->cur_desc = (void *)q->cur_desc + q->iqe_len;
1798 if (unlikely(++q->cidx == q->size)) {
1801 q->cur_desc = q->desc;
1806 * process_responses - process responses from an SGE response queue
1807 * @q: the ingress queue to process
1808 * @budget: how many responses can be processed in this round
1810 * Process responses from an SGE response queue up to the supplied budget.
1811 * Responses include received packets as well as control messages from FW
1814 * Additionally choose the interrupt holdoff time for the next interrupt
1815 * on this queue. If the system is under memory shortage use a fairly
1816 * long delay to help recovery.
1818 static int process_responses(struct sge_rspq *q, int budget)
1821 int budget_left = budget;
1822 const struct rsp_ctrl *rc;
1823 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
1824 struct adapter *adapter = q->adap;
1825 struct sge *s = &adapter->sge;
1827 while (likely(budget_left)) {
1828 rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc));
1829 if (!is_new_response(rc, q))
1833 rsp_type = RSPD_TYPE(rc->type_gen);
1834 if (likely(rsp_type == RSP_TYPE_FLBUF)) {
1835 struct page_frag *fp;
1837 const struct rx_sw_desc *rsd;
1838 u32 len = ntohl(rc->pldbuflen_qid), bufsz, frags;
1840 if (len & RSPD_NEWBUF) {
1841 if (likely(q->offset > 0)) {
1842 free_rx_bufs(q->adap, &rxq->fl, 1);
1845 len = RSPD_LEN(len);
1849 /* gather packet fragments */
1850 for (frags = 0, fp = si.frags; ; frags++, fp++) {
1851 rsd = &rxq->fl.sdesc[rxq->fl.cidx];
1852 bufsz = get_buf_size(adapter, rsd);
1853 fp->page = rsd->page;
1854 fp->offset = q->offset;
1855 fp->size = min(bufsz, len);
1859 unmap_rx_buf(q->adap, &rxq->fl);
1863 * Last buffer remains mapped so explicitly make it
1864 * coherent for CPU access.
1866 dma_sync_single_for_cpu(q->adap->pdev_dev,
1868 fp->size, DMA_FROM_DEVICE);
1870 si.va = page_address(si.frags[0].page) +
1874 si.nfrags = frags + 1;
1875 ret = q->handler(q, q->cur_desc, &si);
1876 if (likely(ret == 0))
1877 q->offset += ALIGN(fp->size, s->fl_align);
1879 restore_rx_bufs(&si, &rxq->fl, frags);
1880 } else if (likely(rsp_type == RSP_TYPE_CPL)) {
1881 ret = q->handler(q, q->cur_desc, NULL);
1883 ret = q->handler(q, (const __be64 *)rc, CXGB4_MSG_AN);
1886 if (unlikely(ret)) {
1887 /* couldn't process descriptor, back off for recovery */
1888 q->next_intr_params = QINTR_TIMER_IDX(NOMEM_TMR_IDX);
1896 if (q->offset >= 0 && rxq->fl.size - rxq->fl.avail >= 16)
1897 __refill_fl(q->adap, &rxq->fl);
1898 return budget - budget_left;
1902 * napi_rx_handler - the NAPI handler for Rx processing
1903 * @napi: the napi instance
1904 * @budget: how many packets we can process in this round
1906 * Handler for new data events when using NAPI. This does not need any
1907 * locking or protection from interrupts as data interrupts are off at
1908 * this point and other adapter interrupts do not interfere (the latter
1909 * in not a concern at all with MSI-X as non-data interrupts then have
1910 * a separate handler).
1912 static int napi_rx_handler(struct napi_struct *napi, int budget)
1914 unsigned int params;
1915 struct sge_rspq *q = container_of(napi, struct sge_rspq, napi);
1916 int work_done = process_responses(q, budget);
1918 if (likely(work_done < budget)) {
1919 napi_complete(napi);
1920 params = q->next_intr_params;
1921 q->next_intr_params = q->intr_params;
1923 params = QINTR_TIMER_IDX(7);
1925 t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS), CIDXINC(work_done) |
1926 INGRESSQID((u32)q->cntxt_id) | SEINTARM(params));
1931 * The MSI-X interrupt handler for an SGE response queue.
1933 irqreturn_t t4_sge_intr_msix(int irq, void *cookie)
1935 struct sge_rspq *q = cookie;
1937 napi_schedule(&q->napi);
1942 * Process the indirect interrupt entries in the interrupt queue and kick off
1943 * NAPI for each queue that has generated an entry.
1945 static unsigned int process_intrq(struct adapter *adap)
1947 unsigned int credits;
1948 const struct rsp_ctrl *rc;
1949 struct sge_rspq *q = &adap->sge.intrq;
1951 spin_lock(&adap->sge.intrq_lock);
1952 for (credits = 0; ; credits++) {
1953 rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc));
1954 if (!is_new_response(rc, q))
1958 if (RSPD_TYPE(rc->type_gen) == RSP_TYPE_INTR) {
1959 unsigned int qid = ntohl(rc->pldbuflen_qid);
1961 qid -= adap->sge.ingr_start;
1962 napi_schedule(&adap->sge.ingr_map[qid]->napi);
1968 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS), CIDXINC(credits) |
1969 INGRESSQID(q->cntxt_id) | SEINTARM(q->intr_params));
1970 spin_unlock(&adap->sge.intrq_lock);
1975 * The MSI interrupt handler, which handles data events from SGE response queues
1976 * as well as error and other async events as they all use the same MSI vector.
1978 static irqreturn_t t4_intr_msi(int irq, void *cookie)
1980 struct adapter *adap = cookie;
1982 t4_slow_intr_handler(adap);
1983 process_intrq(adap);
1988 * Interrupt handler for legacy INTx interrupts.
1989 * Handles data events from SGE response queues as well as error and other
1990 * async events as they all use the same interrupt line.
1992 static irqreturn_t t4_intr_intx(int irq, void *cookie)
1994 struct adapter *adap = cookie;
1996 t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI), 0);
1997 if (t4_slow_intr_handler(adap) | process_intrq(adap))
1999 return IRQ_NONE; /* probably shared interrupt */
2003 * t4_intr_handler - select the top-level interrupt handler
2004 * @adap: the adapter
2006 * Selects the top-level interrupt handler based on the type of interrupts
2007 * (MSI-X, MSI, or INTx).
2009 irq_handler_t t4_intr_handler(struct adapter *adap)
2011 if (adap->flags & USING_MSIX)
2012 return t4_sge_intr_msix;
2013 if (adap->flags & USING_MSI)
2015 return t4_intr_intx;
2018 static void sge_rx_timer_cb(unsigned long data)
2021 unsigned int i, idma_same_state_cnt[2];
2022 struct adapter *adap = (struct adapter *)data;
2023 struct sge *s = &adap->sge;
2025 for (i = 0; i < ARRAY_SIZE(s->starving_fl); i++)
2026 for (m = s->starving_fl[i]; m; m &= m - 1) {
2027 struct sge_eth_rxq *rxq;
2028 unsigned int id = __ffs(m) + i * BITS_PER_LONG;
2029 struct sge_fl *fl = s->egr_map[id];
2031 clear_bit(id, s->starving_fl);
2032 smp_mb__after_clear_bit();
2034 if (fl_starving(fl)) {
2035 rxq = container_of(fl, struct sge_eth_rxq, fl);
2036 if (napi_reschedule(&rxq->rspq.napi))
2039 set_bit(id, s->starving_fl);
2043 t4_write_reg(adap, SGE_DEBUG_INDEX, 13);
2044 idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH);
2045 idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
2047 for (i = 0; i < 2; i++) {
2048 u32 debug0, debug11;
2050 /* If the Ingress DMA Same State Counter ("timer") is less
2051 * than 1s, then we can reset our synthesized Stall Timer and
2052 * continue. If we have previously emitted warnings about a
2053 * potential stalled Ingress Queue, issue a note indicating
2054 * that the Ingress Queue has resumed forward progress.
2056 if (idma_same_state_cnt[i] < s->idma_1s_thresh) {
2057 if (s->idma_stalled[i] >= SGE_IDMA_WARN_THRESH)
2058 CH_WARN(adap, "SGE idma%d, queue%u,resumed after %d sec\n",
2060 s->idma_stalled[i]/HZ);
2061 s->idma_stalled[i] = 0;
2065 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
2066 * domain. The first time we get here it'll be because we
2067 * passed the 1s Threshold; each additional time it'll be
2068 * because the RX Timer Callback is being fired on its regular
2071 * If the stall is below our Potential Hung Ingress Queue
2072 * Warning Threshold, continue.
2074 if (s->idma_stalled[i] == 0)
2075 s->idma_stalled[i] = HZ;
2077 s->idma_stalled[i] += RX_QCHECK_PERIOD;
2079 if (s->idma_stalled[i] < SGE_IDMA_WARN_THRESH)
2082 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT Hz */
2083 if (((s->idma_stalled[i] - HZ) % SGE_IDMA_WARN_REPEAT) != 0)
2086 /* Read and save the SGE IDMA State and Queue ID information.
2087 * We do this every time in case it changes across time ...
2089 t4_write_reg(adap, SGE_DEBUG_INDEX, 0);
2090 debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
2091 s->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
2093 t4_write_reg(adap, SGE_DEBUG_INDEX, 11);
2094 debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
2095 s->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
2097 CH_WARN(adap, "SGE idma%u, queue%u, maybe stuck state%u %dsecs (debug0=%#x, debug11=%#x)\n",
2098 i, s->idma_qid[i], s->idma_state[i],
2099 s->idma_stalled[i]/HZ, debug0, debug11);
2100 t4_sge_decode_idma_state(adap, s->idma_state[i]);
2103 mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD);
2106 static void sge_tx_timer_cb(unsigned long data)
2109 unsigned int i, budget;
2110 struct adapter *adap = (struct adapter *)data;
2111 struct sge *s = &adap->sge;
2113 for (i = 0; i < ARRAY_SIZE(s->txq_maperr); i++)
2114 for (m = s->txq_maperr[i]; m; m &= m - 1) {
2115 unsigned long id = __ffs(m) + i * BITS_PER_LONG;
2116 struct sge_ofld_txq *txq = s->egr_map[id];
2118 clear_bit(id, s->txq_maperr);
2119 tasklet_schedule(&txq->qresume_tsk);
2122 budget = MAX_TIMER_TX_RECLAIM;
2123 i = s->ethtxq_rover;
2125 struct sge_eth_txq *q = &s->ethtxq[i];
2128 time_after_eq(jiffies, q->txq->trans_start + HZ / 100) &&
2129 __netif_tx_trylock(q->txq)) {
2130 int avail = reclaimable(&q->q);
2136 free_tx_desc(adap, &q->q, avail, true);
2137 q->q.in_use -= avail;
2140 __netif_tx_unlock(q->txq);
2143 if (++i >= s->ethqsets)
2145 } while (budget && i != s->ethtxq_rover);
2146 s->ethtxq_rover = i;
2147 mod_timer(&s->tx_timer, jiffies + (budget ? TX_QCHECK_PERIOD : 2));
2150 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
2151 struct net_device *dev, int intr_idx,
2152 struct sge_fl *fl, rspq_handler_t hnd)
2156 struct sge *s = &adap->sge;
2157 struct port_info *pi = netdev_priv(dev);
2159 /* Size needs to be multiple of 16, including status entry. */
2160 iq->size = roundup(iq->size, 16);
2162 iq->desc = alloc_ring(adap->pdev_dev, iq->size, iq->iqe_len, 0,
2163 &iq->phys_addr, NULL, 0, NUMA_NO_NODE);
2167 memset(&c, 0, sizeof(c));
2168 c.op_to_vfn = htonl(FW_CMD_OP(FW_IQ_CMD) | FW_CMD_REQUEST |
2169 FW_CMD_WRITE | FW_CMD_EXEC |
2170 FW_IQ_CMD_PFN(adap->fn) | FW_IQ_CMD_VFN(0));
2171 c.alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC | FW_IQ_CMD_IQSTART(1) |
2173 c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2174 FW_IQ_CMD_IQASYNCH(fwevtq) | FW_IQ_CMD_VIID(pi->viid) |
2175 FW_IQ_CMD_IQANDST(intr_idx < 0) | FW_IQ_CMD_IQANUD(1) |
2176 FW_IQ_CMD_IQANDSTINDEX(intr_idx >= 0 ? intr_idx :
2178 c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2179 FW_IQ_CMD_IQGTSMODE |
2180 FW_IQ_CMD_IQINTCNTTHRESH(iq->pktcnt_idx) |
2181 FW_IQ_CMD_IQESIZE(ilog2(iq->iqe_len) - 4));
2182 c.iqsize = htons(iq->size);
2183 c.iqaddr = cpu_to_be64(iq->phys_addr);
2186 fl->size = roundup(fl->size, 8);
2187 fl->desc = alloc_ring(adap->pdev_dev, fl->size, sizeof(__be64),
2188 sizeof(struct rx_sw_desc), &fl->addr,
2189 &fl->sdesc, s->stat_len, NUMA_NO_NODE);
2193 flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);
2194 c.iqns_to_fl0congen = htonl(FW_IQ_CMD_FL0PACKEN(1) |
2195 FW_IQ_CMD_FL0FETCHRO(1) |
2196 FW_IQ_CMD_FL0DATARO(1) |
2197 FW_IQ_CMD_FL0PADEN(1));
2198 c.fl0dcaen_to_fl0cidxfthresh = htons(FW_IQ_CMD_FL0FBMIN(2) |
2199 FW_IQ_CMD_FL0FBMAX(3));
2200 c.fl0size = htons(flsz);
2201 c.fl0addr = cpu_to_be64(fl->addr);
2204 ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c);
2208 netif_napi_add(dev, &iq->napi, napi_rx_handler, 64);
2209 iq->cur_desc = iq->desc;
2212 iq->next_intr_params = iq->intr_params;
2213 iq->cntxt_id = ntohs(c.iqid);
2214 iq->abs_id = ntohs(c.physiqid);
2215 iq->size--; /* subtract status entry */
2220 /* set offset to -1 to distinguish ingress queues without FL */
2221 iq->offset = fl ? 0 : -1;
2223 adap->sge.ingr_map[iq->cntxt_id - adap->sge.ingr_start] = iq;
2226 fl->cntxt_id = ntohs(c.fl0id);
2227 fl->avail = fl->pend_cred = 0;
2228 fl->pidx = fl->cidx = 0;
2229 fl->alloc_failed = fl->large_alloc_failed = fl->starving = 0;
2230 adap->sge.egr_map[fl->cntxt_id - adap->sge.egr_start] = fl;
2231 refill_fl(adap, fl, fl_cap(fl), GFP_KERNEL);
2239 dma_free_coherent(adap->pdev_dev, iq->size * iq->iqe_len,
2240 iq->desc, iq->phys_addr);
2243 if (fl && fl->desc) {
2246 dma_free_coherent(adap->pdev_dev, flsz * sizeof(struct tx_desc),
2247 fl->desc, fl->addr);
2253 static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id)
2256 if (!is_t4(adap->params.chip)) {
2258 unsigned short udb_density;
2259 unsigned long qpshift;
2262 s_qpp = QUEUESPERPAGEPF1 * adap->fn;
2263 udb_density = 1 << QUEUESPERPAGEPF0_GET((t4_read_reg(adap,
2264 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp));
2265 qpshift = PAGE_SHIFT - ilog2(udb_density);
2266 q->udb = q->cntxt_id << qpshift;
2267 q->udb &= PAGE_MASK;
2268 page = q->udb / PAGE_SIZE;
2269 q->udb += (q->cntxt_id - (page * udb_density)) * 128;
2273 q->cidx = q->pidx = 0;
2274 q->stops = q->restarts = 0;
2275 q->stat = (void *)&q->desc[q->size];
2276 spin_lock_init(&q->db_lock);
2277 adap->sge.egr_map[id - adap->sge.egr_start] = q;
2280 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
2281 struct net_device *dev, struct netdev_queue *netdevq,
2285 struct fw_eq_eth_cmd c;
2286 struct sge *s = &adap->sge;
2287 struct port_info *pi = netdev_priv(dev);
2289 /* Add status entries */
2290 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
2292 txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size,
2293 sizeof(struct tx_desc), sizeof(struct tx_sw_desc),
2294 &txq->q.phys_addr, &txq->q.sdesc, s->stat_len,
2295 netdev_queue_numa_node_read(netdevq));
2299 memset(&c, 0, sizeof(c));
2300 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_ETH_CMD) | FW_CMD_REQUEST |
2301 FW_CMD_WRITE | FW_CMD_EXEC |
2302 FW_EQ_ETH_CMD_PFN(adap->fn) | FW_EQ_ETH_CMD_VFN(0));
2303 c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC |
2304 FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
2305 c.viid_pkd = htonl(FW_EQ_ETH_CMD_VIID(pi->viid));
2306 c.fetchszm_to_iqid = htonl(FW_EQ_ETH_CMD_HOSTFCMODE(2) |
2307 FW_EQ_ETH_CMD_PCIECHN(pi->tx_chan) |
2308 FW_EQ_ETH_CMD_FETCHRO(1) |
2309 FW_EQ_ETH_CMD_IQID(iqid));
2310 c.dcaen_to_eqsize = htonl(FW_EQ_ETH_CMD_FBMIN(2) |
2311 FW_EQ_ETH_CMD_FBMAX(3) |
2312 FW_EQ_ETH_CMD_CIDXFTHRESH(5) |
2313 FW_EQ_ETH_CMD_EQSIZE(nentries));
2314 c.eqaddr = cpu_to_be64(txq->q.phys_addr);
2316 ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c);
2318 kfree(txq->q.sdesc);
2319 txq->q.sdesc = NULL;
2320 dma_free_coherent(adap->pdev_dev,
2321 nentries * sizeof(struct tx_desc),
2322 txq->q.desc, txq->q.phys_addr);
2327 init_txq(adap, &txq->q, FW_EQ_ETH_CMD_EQID_GET(ntohl(c.eqid_pkd)));
2329 txq->tso = txq->tx_cso = txq->vlan_ins = 0;
2330 txq->mapping_err = 0;
2334 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
2335 struct net_device *dev, unsigned int iqid,
2336 unsigned int cmplqid)
2339 struct fw_eq_ctrl_cmd c;
2340 struct sge *s = &adap->sge;
2341 struct port_info *pi = netdev_priv(dev);
2343 /* Add status entries */
2344 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
2346 txq->q.desc = alloc_ring(adap->pdev_dev, nentries,
2347 sizeof(struct tx_desc), 0, &txq->q.phys_addr,
2348 NULL, 0, NUMA_NO_NODE);
2352 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST |
2353 FW_CMD_WRITE | FW_CMD_EXEC |
2354 FW_EQ_CTRL_CMD_PFN(adap->fn) |
2355 FW_EQ_CTRL_CMD_VFN(0));
2356 c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC |
2357 FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
2358 c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_CMPLIQID(cmplqid));
2359 c.physeqid_pkd = htonl(0);
2360 c.fetchszm_to_iqid = htonl(FW_EQ_CTRL_CMD_HOSTFCMODE(2) |
2361 FW_EQ_CTRL_CMD_PCIECHN(pi->tx_chan) |
2362 FW_EQ_CTRL_CMD_FETCHRO |
2363 FW_EQ_CTRL_CMD_IQID(iqid));
2364 c.dcaen_to_eqsize = htonl(FW_EQ_CTRL_CMD_FBMIN(2) |
2365 FW_EQ_CTRL_CMD_FBMAX(3) |
2366 FW_EQ_CTRL_CMD_CIDXFTHRESH(5) |
2367 FW_EQ_CTRL_CMD_EQSIZE(nentries));
2368 c.eqaddr = cpu_to_be64(txq->q.phys_addr);
2370 ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c);
2372 dma_free_coherent(adap->pdev_dev,
2373 nentries * sizeof(struct tx_desc),
2374 txq->q.desc, txq->q.phys_addr);
2379 init_txq(adap, &txq->q, FW_EQ_CTRL_CMD_EQID_GET(ntohl(c.cmpliqid_eqid)));
2381 skb_queue_head_init(&txq->sendq);
2382 tasklet_init(&txq->qresume_tsk, restart_ctrlq, (unsigned long)txq);
2387 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
2388 struct net_device *dev, unsigned int iqid)
2391 struct fw_eq_ofld_cmd c;
2392 struct sge *s = &adap->sge;
2393 struct port_info *pi = netdev_priv(dev);
2395 /* Add status entries */
2396 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
2398 txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size,
2399 sizeof(struct tx_desc), sizeof(struct tx_sw_desc),
2400 &txq->q.phys_addr, &txq->q.sdesc, s->stat_len,
2405 memset(&c, 0, sizeof(c));
2406 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST |
2407 FW_CMD_WRITE | FW_CMD_EXEC |
2408 FW_EQ_OFLD_CMD_PFN(adap->fn) |
2409 FW_EQ_OFLD_CMD_VFN(0));
2410 c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC |
2411 FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
2412 c.fetchszm_to_iqid = htonl(FW_EQ_OFLD_CMD_HOSTFCMODE(2) |
2413 FW_EQ_OFLD_CMD_PCIECHN(pi->tx_chan) |
2414 FW_EQ_OFLD_CMD_FETCHRO(1) |
2415 FW_EQ_OFLD_CMD_IQID(iqid));
2416 c.dcaen_to_eqsize = htonl(FW_EQ_OFLD_CMD_FBMIN(2) |
2417 FW_EQ_OFLD_CMD_FBMAX(3) |
2418 FW_EQ_OFLD_CMD_CIDXFTHRESH(5) |
2419 FW_EQ_OFLD_CMD_EQSIZE(nentries));
2420 c.eqaddr = cpu_to_be64(txq->q.phys_addr);
2422 ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c);
2424 kfree(txq->q.sdesc);
2425 txq->q.sdesc = NULL;
2426 dma_free_coherent(adap->pdev_dev,
2427 nentries * sizeof(struct tx_desc),
2428 txq->q.desc, txq->q.phys_addr);
2433 init_txq(adap, &txq->q, FW_EQ_OFLD_CMD_EQID_GET(ntohl(c.eqid_pkd)));
2435 skb_queue_head_init(&txq->sendq);
2436 tasklet_init(&txq->qresume_tsk, restart_ofldq, (unsigned long)txq);
2438 txq->mapping_err = 0;
2442 static void free_txq(struct adapter *adap, struct sge_txq *q)
2444 struct sge *s = &adap->sge;
2446 dma_free_coherent(adap->pdev_dev,
2447 q->size * sizeof(struct tx_desc) + s->stat_len,
2448 q->desc, q->phys_addr);
2454 static void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq,
2457 struct sge *s = &adap->sge;
2458 unsigned int fl_id = fl ? fl->cntxt_id : 0xffff;
2460 adap->sge.ingr_map[rq->cntxt_id - adap->sge.ingr_start] = NULL;
2461 t4_iq_free(adap, adap->fn, adap->fn, 0, FW_IQ_TYPE_FL_INT_CAP,
2462 rq->cntxt_id, fl_id, 0xffff);
2463 dma_free_coherent(adap->pdev_dev, (rq->size + 1) * rq->iqe_len,
2464 rq->desc, rq->phys_addr);
2465 netif_napi_del(&rq->napi);
2467 rq->cntxt_id = rq->abs_id = 0;
2471 free_rx_bufs(adap, fl, fl->avail);
2472 dma_free_coherent(adap->pdev_dev, fl->size * 8 + s->stat_len,
2473 fl->desc, fl->addr);
2482 * t4_free_sge_resources - free SGE resources
2483 * @adap: the adapter
2485 * Frees resources used by the SGE queue sets.
2487 void t4_free_sge_resources(struct adapter *adap)
2490 struct sge_eth_rxq *eq = adap->sge.ethrxq;
2491 struct sge_eth_txq *etq = adap->sge.ethtxq;
2492 struct sge_ofld_rxq *oq = adap->sge.ofldrxq;
2494 /* clean up Ethernet Tx/Rx queues */
2495 for (i = 0; i < adap->sge.ethqsets; i++, eq++, etq++) {
2497 free_rspq_fl(adap, &eq->rspq, &eq->fl);
2499 t4_eth_eq_free(adap, adap->fn, adap->fn, 0,
2501 free_tx_desc(adap, &etq->q, etq->q.in_use, true);
2502 kfree(etq->q.sdesc);
2503 free_txq(adap, &etq->q);
2507 /* clean up RDMA and iSCSI Rx queues */
2508 for (i = 0; i < adap->sge.ofldqsets; i++, oq++) {
2510 free_rspq_fl(adap, &oq->rspq, &oq->fl);
2512 for (i = 0, oq = adap->sge.rdmarxq; i < adap->sge.rdmaqs; i++, oq++) {
2514 free_rspq_fl(adap, &oq->rspq, &oq->fl);
2517 /* clean up offload Tx queues */
2518 for (i = 0; i < ARRAY_SIZE(adap->sge.ofldtxq); i++) {
2519 struct sge_ofld_txq *q = &adap->sge.ofldtxq[i];
2522 tasklet_kill(&q->qresume_tsk);
2523 t4_ofld_eq_free(adap, adap->fn, adap->fn, 0,
2525 free_tx_desc(adap, &q->q, q->q.in_use, false);
2527 __skb_queue_purge(&q->sendq);
2528 free_txq(adap, &q->q);
2532 /* clean up control Tx queues */
2533 for (i = 0; i < ARRAY_SIZE(adap->sge.ctrlq); i++) {
2534 struct sge_ctrl_txq *cq = &adap->sge.ctrlq[i];
2537 tasklet_kill(&cq->qresume_tsk);
2538 t4_ctrl_eq_free(adap, adap->fn, adap->fn, 0,
2540 __skb_queue_purge(&cq->sendq);
2541 free_txq(adap, &cq->q);
2545 if (adap->sge.fw_evtq.desc)
2546 free_rspq_fl(adap, &adap->sge.fw_evtq, NULL);
2548 if (adap->sge.intrq.desc)
2549 free_rspq_fl(adap, &adap->sge.intrq, NULL);
2551 /* clear the reverse egress queue map */
2552 memset(adap->sge.egr_map, 0, sizeof(adap->sge.egr_map));
2555 void t4_sge_start(struct adapter *adap)
2557 adap->sge.ethtxq_rover = 0;
2558 mod_timer(&adap->sge.rx_timer, jiffies + RX_QCHECK_PERIOD);
2559 mod_timer(&adap->sge.tx_timer, jiffies + TX_QCHECK_PERIOD);
2563 * t4_sge_stop - disable SGE operation
2564 * @adap: the adapter
2566 * Stop tasklets and timers associated with the DMA engine. Note that
2567 * this is effective only if measures have been taken to disable any HW
2568 * events that may restart them.
2570 void t4_sge_stop(struct adapter *adap)
2573 struct sge *s = &adap->sge;
2575 if (in_interrupt()) /* actions below require waiting */
2578 if (s->rx_timer.function)
2579 del_timer_sync(&s->rx_timer);
2580 if (s->tx_timer.function)
2581 del_timer_sync(&s->tx_timer);
2583 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++) {
2584 struct sge_ofld_txq *q = &s->ofldtxq[i];
2587 tasklet_kill(&q->qresume_tsk);
2589 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) {
2590 struct sge_ctrl_txq *cq = &s->ctrlq[i];
2593 tasklet_kill(&cq->qresume_tsk);
2598 * t4_sge_init - initialize SGE
2599 * @adap: the adapter
2601 * Performs SGE initialization needed every time after a chip reset.
2602 * We do not initialize any of the queues here, instead the driver
2603 * top-level must request them individually.
2605 * Called in two different modes:
2607 * 1. Perform actual hardware initialization and record hard-coded
2608 * parameters which were used. This gets used when we're the
2609 * Master PF and the Firmware Configuration File support didn't
2610 * work for some reason.
2612 * 2. We're not the Master PF or initialization was performed with
2613 * a Firmware Configuration File. In this case we need to grab
2614 * any of the SGE operating parameters that we need to have in
2615 * order to do our job and make sure we can live with them ...
2618 static int t4_sge_init_soft(struct adapter *adap)
2620 struct sge *s = &adap->sge;
2621 u32 fl_small_pg, fl_large_pg, fl_small_mtu, fl_large_mtu;
2622 u32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5;
2623 u32 ingress_rx_threshold;
2626 * Verify that CPL messages are going to the Ingress Queue for
2627 * process_responses() and that only packet data is going to the
2630 if ((t4_read_reg(adap, SGE_CONTROL) & RXPKTCPLMODE_MASK) !=
2631 RXPKTCPLMODE(X_RXPKTCPLMODE_SPLIT)) {
2632 dev_err(adap->pdev_dev, "bad SGE CPL MODE\n");
2637 * Validate the Host Buffer Register Array indices that we want to
2640 * XXX Note that we should really read through the Host Buffer Size
2641 * XXX register array and find the indices of the Buffer Sizes which
2642 * XXX meet our needs!
2644 #define READ_FL_BUF(x) \
2645 t4_read_reg(adap, SGE_FL_BUFFER_SIZE0+(x)*sizeof(u32))
2647 fl_small_pg = READ_FL_BUF(RX_SMALL_PG_BUF);
2648 fl_large_pg = READ_FL_BUF(RX_LARGE_PG_BUF);
2649 fl_small_mtu = READ_FL_BUF(RX_SMALL_MTU_BUF);
2650 fl_large_mtu = READ_FL_BUF(RX_LARGE_MTU_BUF);
2652 /* We only bother using the Large Page logic if the Large Page Buffer
2653 * is larger than our Page Size Buffer.
2655 if (fl_large_pg <= fl_small_pg)
2660 /* The Page Size Buffer must be exactly equal to our Page Size and the
2661 * Large Page Size Buffer should be 0 (per above) or a power of 2.
2663 if (fl_small_pg != PAGE_SIZE ||
2664 (fl_large_pg & (fl_large_pg-1)) != 0) {
2665 dev_err(adap->pdev_dev, "bad SGE FL page buffer sizes [%d, %d]\n",
2666 fl_small_pg, fl_large_pg);
2670 s->fl_pg_order = ilog2(fl_large_pg) - PAGE_SHIFT;
2672 if (fl_small_mtu < FL_MTU_SMALL_BUFSIZE(adap) ||
2673 fl_large_mtu < FL_MTU_LARGE_BUFSIZE(adap)) {
2674 dev_err(adap->pdev_dev, "bad SGE FL MTU sizes [%d, %d]\n",
2675 fl_small_mtu, fl_large_mtu);
2680 * Retrieve our RX interrupt holdoff timer values and counter
2681 * threshold values from the SGE parameters.
2683 timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1);
2684 timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3);
2685 timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5);
2686 s->timer_val[0] = core_ticks_to_us(adap,
2687 TIMERVALUE0_GET(timer_value_0_and_1));
2688 s->timer_val[1] = core_ticks_to_us(adap,
2689 TIMERVALUE1_GET(timer_value_0_and_1));
2690 s->timer_val[2] = core_ticks_to_us(adap,
2691 TIMERVALUE2_GET(timer_value_2_and_3));
2692 s->timer_val[3] = core_ticks_to_us(adap,
2693 TIMERVALUE3_GET(timer_value_2_and_3));
2694 s->timer_val[4] = core_ticks_to_us(adap,
2695 TIMERVALUE4_GET(timer_value_4_and_5));
2696 s->timer_val[5] = core_ticks_to_us(adap,
2697 TIMERVALUE5_GET(timer_value_4_and_5));
2699 ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD);
2700 s->counter_val[0] = THRESHOLD_0_GET(ingress_rx_threshold);
2701 s->counter_val[1] = THRESHOLD_1_GET(ingress_rx_threshold);
2702 s->counter_val[2] = THRESHOLD_2_GET(ingress_rx_threshold);
2703 s->counter_val[3] = THRESHOLD_3_GET(ingress_rx_threshold);
2708 static int t4_sge_init_hard(struct adapter *adap)
2710 struct sge *s = &adap->sge;
2713 * Set up our basic SGE mode to deliver CPL messages to our Ingress
2714 * Queue and Packet Date to the Free List.
2716 t4_set_reg_field(adap, SGE_CONTROL, RXPKTCPLMODE_MASK,
2720 * Set up to drop DOORBELL writes when the DOORBELL FIFO overflows
2721 * and generate an interrupt when this occurs so we can recover.
2723 if (is_t4(adap->params.chip)) {
2724 t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS,
2725 V_HP_INT_THRESH(M_HP_INT_THRESH) |
2726 V_LP_INT_THRESH(M_LP_INT_THRESH),
2727 V_HP_INT_THRESH(dbfifo_int_thresh) |
2728 V_LP_INT_THRESH(dbfifo_int_thresh));
2730 t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS,
2731 V_LP_INT_THRESH_T5(M_LP_INT_THRESH_T5),
2732 V_LP_INT_THRESH_T5(dbfifo_int_thresh));
2733 t4_set_reg_field(adap, SGE_DBFIFO_STATUS2,
2734 V_HP_INT_THRESH_T5(M_HP_INT_THRESH_T5),
2735 V_HP_INT_THRESH_T5(dbfifo_int_thresh));
2737 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_ENABLE_DROP,
2741 * SGE_FL_BUFFER_SIZE0 (RX_SMALL_PG_BUF) is set up by
2742 * t4_fixup_host_params().
2744 s->fl_pg_order = FL_PG_ORDER;
2747 SGE_FL_BUFFER_SIZE0+RX_LARGE_PG_BUF*sizeof(u32),
2748 PAGE_SIZE << FL_PG_ORDER);
2749 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0+RX_SMALL_MTU_BUF*sizeof(u32),
2750 FL_MTU_SMALL_BUFSIZE(adap));
2751 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0+RX_LARGE_MTU_BUF*sizeof(u32),
2752 FL_MTU_LARGE_BUFSIZE(adap));
2755 * Note that the SGE Ingress Packet Count Interrupt Threshold and
2756 * Timer Holdoff values must be supplied by our caller.
2758 t4_write_reg(adap, SGE_INGRESS_RX_THRESHOLD,
2759 THRESHOLD_0(s->counter_val[0]) |
2760 THRESHOLD_1(s->counter_val[1]) |
2761 THRESHOLD_2(s->counter_val[2]) |
2762 THRESHOLD_3(s->counter_val[3]));
2763 t4_write_reg(adap, SGE_TIMER_VALUE_0_AND_1,
2764 TIMERVALUE0(us_to_core_ticks(adap, s->timer_val[0])) |
2765 TIMERVALUE1(us_to_core_ticks(adap, s->timer_val[1])));
2766 t4_write_reg(adap, SGE_TIMER_VALUE_2_AND_3,
2767 TIMERVALUE2(us_to_core_ticks(adap, s->timer_val[2])) |
2768 TIMERVALUE3(us_to_core_ticks(adap, s->timer_val[3])));
2769 t4_write_reg(adap, SGE_TIMER_VALUE_4_AND_5,
2770 TIMERVALUE4(us_to_core_ticks(adap, s->timer_val[4])) |
2771 TIMERVALUE5(us_to_core_ticks(adap, s->timer_val[5])));
2776 int t4_sge_init(struct adapter *adap)
2778 struct sge *s = &adap->sge;
2779 u32 sge_control, sge_conm_ctrl;
2780 int ret, egress_threshold;
2783 * Ingress Padding Boundary and Egress Status Page Size are set up by
2784 * t4_fixup_host_params().
2786 sge_control = t4_read_reg(adap, SGE_CONTROL);
2787 s->pktshift = PKTSHIFT_GET(sge_control);
2788 s->stat_len = (sge_control & EGRSTATUSPAGESIZE_MASK) ? 128 : 64;
2789 s->fl_align = 1 << (INGPADBOUNDARY_GET(sge_control) +
2790 X_INGPADBOUNDARY_SHIFT);
2792 if (adap->flags & USING_SOFT_PARAMS)
2793 ret = t4_sge_init_soft(adap);
2795 ret = t4_sge_init_hard(adap);
2800 * A FL with <= fl_starve_thres buffers is starving and a periodic
2801 * timer will attempt to refill it. This needs to be larger than the
2802 * SGE's Egress Congestion Threshold. If it isn't, then we can get
2803 * stuck waiting for new packets while the SGE is waiting for us to
2804 * give it more Free List entries. (Note that the SGE's Egress
2805 * Congestion Threshold is in units of 2 Free List pointers.) For T4,
2806 * there was only a single field to control this. For T5 there's the
2807 * original field which now only applies to Unpacked Mode Free List
2808 * buffers and a new field which only applies to Packed Mode Free List
2811 sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL);
2812 if (is_t4(adap->params.chip))
2813 egress_threshold = EGRTHRESHOLD_GET(sge_conm_ctrl);
2815 egress_threshold = EGRTHRESHOLDPACKING_GET(sge_conm_ctrl);
2816 s->fl_starve_thres = 2*egress_threshold + 1;
2818 setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adap);
2819 setup_timer(&s->tx_timer, sge_tx_timer_cb, (unsigned long)adap);
2820 s->idma_1s_thresh = core_ticks_per_usec(adap) * 1000000; /* 1 s */
2821 s->idma_stalled[0] = 0;
2822 s->idma_stalled[1] = 0;
2823 spin_lock_init(&s->intrq_lock);