2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2009-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #ifndef _T4FW_INTERFACE_H_
36 #define _T4FW_INTERFACE_H_
39 FW_SUCCESS = 0, /* completed sucessfully */
40 FW_EPERM = 1, /* operation not permitted */
41 FW_ENOENT = 2, /* no such file or directory */
42 FW_EIO = 5, /* input/output error; hw bad */
43 FW_ENOEXEC = 8, /* exec format error; inv microcode */
44 FW_EAGAIN = 11, /* try again */
45 FW_ENOMEM = 12, /* out of memory */
46 FW_EFAULT = 14, /* bad address; fw bad */
47 FW_EBUSY = 16, /* resource busy */
48 FW_EEXIST = 17, /* file exists */
49 FW_ENODEV = 19, /* no such device */
50 FW_EINVAL = 22, /* invalid argument */
51 FW_ENOSPC = 28, /* no space left on device */
52 FW_ENOSYS = 38, /* functionality not implemented */
53 FW_ENODATA = 61, /* no data available */
54 FW_EPROTO = 71, /* protocol error */
55 FW_EADDRINUSE = 98, /* address already in use */
56 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
57 FW_ENETDOWN = 100, /* network is down */
58 FW_ENETUNREACH = 101, /* network is unreachable */
59 FW_ENOBUFS = 105, /* no buffer space available */
60 FW_ETIMEDOUT = 110, /* timeout */
61 FW_EINPROGRESS = 115, /* fw internal */
62 FW_SCSI_ABORT_REQUESTED = 128, /* */
63 FW_SCSI_ABORT_TIMEDOUT = 129, /* */
64 FW_SCSI_ABORTED = 130, /* */
65 FW_SCSI_CLOSE_REQUESTED = 131, /* */
66 FW_ERR_LINK_DOWN = 132, /* */
67 FW_RDEV_NOT_READY = 133, /* */
68 FW_ERR_RDEV_LOST = 134, /* */
69 FW_ERR_RDEV_LOGO = 135, /* */
70 FW_FCOE_NO_XCHG = 136, /* */
71 FW_SCSI_RSP_ERR = 137, /* */
72 FW_ERR_RDEV_IMPL_LOGO = 138, /* */
73 FW_SCSI_UNDER_FLOW_ERR = 139, /* */
74 FW_SCSI_OVER_FLOW_ERR = 140, /* */
75 FW_SCSI_DDP_ERR = 141, /* DDP error*/
76 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */
79 #define FW_T4VF_SGE_BASE_ADDR 0x0000
80 #define FW_T4VF_MPS_BASE_ADDR 0x0100
81 #define FW_T4VF_PL_BASE_ADDR 0x0200
82 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240
83 #define FW_T4VF_CIM_BASE_ADDR 0x0300
89 FW_ETH_TX_PKT_WR = 0x08,
90 FW_OFLD_CONNECTION_WR = 0x2f,
92 FW_OFLD_TX_DATA_WR = 0x0b,
94 FW_ETH_TX_PKT_VM_WR = 0x11,
97 FW_RI_RDMA_WRITE_WR = 0x14,
99 FW_RI_RDMA_READ_WR = 0x16,
100 FW_RI_RECV_WR = 0x17,
101 FW_RI_BIND_MW_WR = 0x18,
102 FW_RI_FR_NSMR_WR = 0x19,
103 FW_RI_INV_LSTAG_WR = 0x1a,
112 /* work request opcode (hi) */
113 #define FW_WR_OP_S 24
114 #define FW_WR_OP_M 0xff
115 #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S)
116 #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
118 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
119 #define FW_WR_ATOMIC_S 23
120 #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S)
122 /* flush flag (hi) - firmware flushes flushable work request buffered
123 * in the flow context.
125 #define FW_WR_FLUSH_S 22
126 #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S)
128 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
129 #define FW_WR_COMPL_S 21
130 #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S)
131 #define FW_WR_COMPL_F FW_WR_COMPL_V(1U)
133 /* work request immediate data length (hi) */
134 #define FW_WR_IMMDLEN_S 0
135 #define FW_WR_IMMDLEN_M 0xff
136 #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S)
138 /* egress queue status update to associated ingress queue entry (lo) */
139 #define FW_WR_EQUIQ_S 31
140 #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S)
141 #define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U)
143 /* egress queue status update to egress queue status entry (lo) */
144 #define FW_WR_EQUEQ_S 30
145 #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S)
146 #define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U)
148 /* flow context identifier (lo) */
149 #define FW_WR_FLOWID_S 8
150 #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S)
152 /* length in units of 16-bytes (lo) */
153 #define FW_WR_LEN16_S 0
154 #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S)
156 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B
157 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327
159 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
160 enum fw_filter_wr_cookie {
161 FW_FILTER_WR_SUCCESS,
162 FW_FILTER_WR_FLT_ADDED,
163 FW_FILTER_WR_FLT_DELETED,
164 FW_FILTER_WR_SMT_TBL_FULL,
168 struct fw_filter_wr {
173 __be32 del_filter_to_l2tix;
176 __u8 frag_to_ovlan_vldm;
178 __be16 rx_chan_rx_rpl_iq;
179 __be32 maci_to_matchtypem;
200 #define FW_FILTER_WR_TID_S 12
201 #define FW_FILTER_WR_TID_M 0xfffff
202 #define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S)
203 #define FW_FILTER_WR_TID_G(x) \
204 (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
206 #define FW_FILTER_WR_RQTYPE_S 11
207 #define FW_FILTER_WR_RQTYPE_M 0x1
208 #define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S)
209 #define FW_FILTER_WR_RQTYPE_G(x) \
210 (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
211 #define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U)
213 #define FW_FILTER_WR_NOREPLY_S 10
214 #define FW_FILTER_WR_NOREPLY_M 0x1
215 #define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S)
216 #define FW_FILTER_WR_NOREPLY_G(x) \
217 (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
218 #define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U)
220 #define FW_FILTER_WR_IQ_S 0
221 #define FW_FILTER_WR_IQ_M 0x3ff
222 #define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S)
223 #define FW_FILTER_WR_IQ_G(x) \
224 (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
226 #define FW_FILTER_WR_DEL_FILTER_S 31
227 #define FW_FILTER_WR_DEL_FILTER_M 0x1
228 #define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S)
229 #define FW_FILTER_WR_DEL_FILTER_G(x) \
230 (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
231 #define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U)
233 #define FW_FILTER_WR_RPTTID_S 25
234 #define FW_FILTER_WR_RPTTID_M 0x1
235 #define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S)
236 #define FW_FILTER_WR_RPTTID_G(x) \
237 (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
238 #define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U)
240 #define FW_FILTER_WR_DROP_S 24
241 #define FW_FILTER_WR_DROP_M 0x1
242 #define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S)
243 #define FW_FILTER_WR_DROP_G(x) \
244 (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
245 #define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U)
247 #define FW_FILTER_WR_DIRSTEER_S 23
248 #define FW_FILTER_WR_DIRSTEER_M 0x1
249 #define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S)
250 #define FW_FILTER_WR_DIRSTEER_G(x) \
251 (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
252 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
254 #define FW_FILTER_WR_MASKHASH_S 22
255 #define FW_FILTER_WR_MASKHASH_M 0x1
256 #define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S)
257 #define FW_FILTER_WR_MASKHASH_G(x) \
258 (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
259 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
261 #define FW_FILTER_WR_DIRSTEERHASH_S 21
262 #define FW_FILTER_WR_DIRSTEERHASH_M 0x1
263 #define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
264 #define FW_FILTER_WR_DIRSTEERHASH_G(x) \
265 (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
266 #define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U)
268 #define FW_FILTER_WR_LPBK_S 20
269 #define FW_FILTER_WR_LPBK_M 0x1
270 #define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S)
271 #define FW_FILTER_WR_LPBK_G(x) \
272 (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
273 #define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U)
275 #define FW_FILTER_WR_DMAC_S 19
276 #define FW_FILTER_WR_DMAC_M 0x1
277 #define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S)
278 #define FW_FILTER_WR_DMAC_G(x) \
279 (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
280 #define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U)
282 #define FW_FILTER_WR_SMAC_S 18
283 #define FW_FILTER_WR_SMAC_M 0x1
284 #define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S)
285 #define FW_FILTER_WR_SMAC_G(x) \
286 (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
287 #define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U)
289 #define FW_FILTER_WR_INSVLAN_S 17
290 #define FW_FILTER_WR_INSVLAN_M 0x1
291 #define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S)
292 #define FW_FILTER_WR_INSVLAN_G(x) \
293 (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
294 #define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U)
296 #define FW_FILTER_WR_RMVLAN_S 16
297 #define FW_FILTER_WR_RMVLAN_M 0x1
298 #define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S)
299 #define FW_FILTER_WR_RMVLAN_G(x) \
300 (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
301 #define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U)
303 #define FW_FILTER_WR_HITCNTS_S 15
304 #define FW_FILTER_WR_HITCNTS_M 0x1
305 #define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S)
306 #define FW_FILTER_WR_HITCNTS_G(x) \
307 (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
308 #define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U)
310 #define FW_FILTER_WR_TXCHAN_S 13
311 #define FW_FILTER_WR_TXCHAN_M 0x3
312 #define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S)
313 #define FW_FILTER_WR_TXCHAN_G(x) \
314 (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
316 #define FW_FILTER_WR_PRIO_S 12
317 #define FW_FILTER_WR_PRIO_M 0x1
318 #define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S)
319 #define FW_FILTER_WR_PRIO_G(x) \
320 (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
321 #define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U)
323 #define FW_FILTER_WR_L2TIX_S 0
324 #define FW_FILTER_WR_L2TIX_M 0xfff
325 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
326 #define FW_FILTER_WR_L2TIX_G(x) \
327 (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
329 #define FW_FILTER_WR_FRAG_S 7
330 #define FW_FILTER_WR_FRAG_M 0x1
331 #define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S)
332 #define FW_FILTER_WR_FRAG_G(x) \
333 (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
334 #define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U)
336 #define FW_FILTER_WR_FRAGM_S 6
337 #define FW_FILTER_WR_FRAGM_M 0x1
338 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
339 #define FW_FILTER_WR_FRAGM_G(x) \
340 (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
341 #define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U)
343 #define FW_FILTER_WR_IVLAN_VLD_S 5
344 #define FW_FILTER_WR_IVLAN_VLD_M 0x1
345 #define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S)
346 #define FW_FILTER_WR_IVLAN_VLD_G(x) \
347 (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
348 #define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U)
350 #define FW_FILTER_WR_OVLAN_VLD_S 4
351 #define FW_FILTER_WR_OVLAN_VLD_M 0x1
352 #define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S)
353 #define FW_FILTER_WR_OVLAN_VLD_G(x) \
354 (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
355 #define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U)
357 #define FW_FILTER_WR_IVLAN_VLDM_S 3
358 #define FW_FILTER_WR_IVLAN_VLDM_M 0x1
359 #define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
360 #define FW_FILTER_WR_IVLAN_VLDM_G(x) \
361 (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
362 #define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U)
364 #define FW_FILTER_WR_OVLAN_VLDM_S 2
365 #define FW_FILTER_WR_OVLAN_VLDM_M 0x1
366 #define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
367 #define FW_FILTER_WR_OVLAN_VLDM_G(x) \
368 (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
369 #define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U)
371 #define FW_FILTER_WR_RX_CHAN_S 15
372 #define FW_FILTER_WR_RX_CHAN_M 0x1
373 #define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S)
374 #define FW_FILTER_WR_RX_CHAN_G(x) \
375 (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
376 #define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U)
378 #define FW_FILTER_WR_RX_RPL_IQ_S 0
379 #define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff
380 #define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
381 #define FW_FILTER_WR_RX_RPL_IQ_G(x) \
382 (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
384 #define FW_FILTER_WR_MACI_S 23
385 #define FW_FILTER_WR_MACI_M 0x1ff
386 #define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S)
387 #define FW_FILTER_WR_MACI_G(x) \
388 (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
390 #define FW_FILTER_WR_MACIM_S 14
391 #define FW_FILTER_WR_MACIM_M 0x1ff
392 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
393 #define FW_FILTER_WR_MACIM_G(x) \
394 (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
396 #define FW_FILTER_WR_FCOE_S 13
397 #define FW_FILTER_WR_FCOE_M 0x1
398 #define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S)
399 #define FW_FILTER_WR_FCOE_G(x) \
400 (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
401 #define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U)
403 #define FW_FILTER_WR_FCOEM_S 12
404 #define FW_FILTER_WR_FCOEM_M 0x1
405 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
406 #define FW_FILTER_WR_FCOEM_G(x) \
407 (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
408 #define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U)
410 #define FW_FILTER_WR_PORT_S 9
411 #define FW_FILTER_WR_PORT_M 0x7
412 #define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S)
413 #define FW_FILTER_WR_PORT_G(x) \
414 (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
416 #define FW_FILTER_WR_PORTM_S 6
417 #define FW_FILTER_WR_PORTM_M 0x7
418 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
419 #define FW_FILTER_WR_PORTM_G(x) \
420 (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
422 #define FW_FILTER_WR_MATCHTYPE_S 3
423 #define FW_FILTER_WR_MATCHTYPE_M 0x7
424 #define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S)
425 #define FW_FILTER_WR_MATCHTYPE_G(x) \
426 (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
428 #define FW_FILTER_WR_MATCHTYPEM_S 0
429 #define FW_FILTER_WR_MATCHTYPEM_M 0x7
430 #define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S)
431 #define FW_FILTER_WR_MATCHTYPEM_G(x) \
432 (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
441 __be32 op_to_immdlen;
446 struct fw_eth_tx_pkt_wr {
448 __be32 equiq_to_len16;
452 struct fw_ofld_connection_wr {
458 struct fw_ofld_connection_le {
464 union fw_ofld_connection_leip {
465 struct fw_ofld_connection_le_ipv4 {
472 struct fw_ofld_connection_le_ipv6 {
480 struct fw_ofld_connection_tcb {
481 __be32 t_state_to_astid;
482 __be16 cplrxdataack_cplpassacceptrpl;
494 #define FW_OFLD_CONNECTION_WR_VERSION_S 31
495 #define FW_OFLD_CONNECTION_WR_VERSION_M 0x1
496 #define FW_OFLD_CONNECTION_WR_VERSION_V(x) \
497 ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
498 #define FW_OFLD_CONNECTION_WR_VERSION_G(x) \
499 (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
500 FW_OFLD_CONNECTION_WR_VERSION_M)
501 #define FW_OFLD_CONNECTION_WR_VERSION_F \
502 FW_OFLD_CONNECTION_WR_VERSION_V(1U)
504 #define FW_OFLD_CONNECTION_WR_CPL_S 30
505 #define FW_OFLD_CONNECTION_WR_CPL_M 0x1
506 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
507 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
508 (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
509 #define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U)
511 #define FW_OFLD_CONNECTION_WR_T_STATE_S 28
512 #define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf
513 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \
514 ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
515 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \
516 (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
517 FW_OFLD_CONNECTION_WR_T_STATE_M)
519 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24
520 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf
521 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \
522 ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
523 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \
524 (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
525 FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
527 #define FW_OFLD_CONNECTION_WR_ASTID_S 0
528 #define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff
529 #define FW_OFLD_CONNECTION_WR_ASTID_V(x) \
530 ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
531 #define FW_OFLD_CONNECTION_WR_ASTID_G(x) \
532 (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
534 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15
535 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1
536 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \
537 ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
538 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \
539 (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
540 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
541 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \
542 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
544 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14
545 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1
546 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \
547 ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
548 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \
549 (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
550 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
551 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \
552 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
555 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */
559 FW_FLOWC_MNEM_SNDNXT,
560 FW_FLOWC_MNEM_RCVNXT,
561 FW_FLOWC_MNEM_SNDBUF,
565 struct fw_flowc_mnemval {
572 __be32 op_to_nparams;
574 struct fw_flowc_mnemval mnemval[0];
577 #define FW_FLOWC_WR_NPARAMS_S 0
578 #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S)
580 struct fw_ofld_tx_data_wr {
581 __be32 op_to_immdlen;
584 __be32 tunnel_to_proxy;
587 #define FW_OFLD_TX_DATA_WR_TUNNEL_S 19
588 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
590 #define FW_OFLD_TX_DATA_WR_SAVE_S 18
591 #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
593 #define FW_OFLD_TX_DATA_WR_FLUSH_S 17
594 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
595 #define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
597 #define FW_OFLD_TX_DATA_WR_URGENT_S 16
598 #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
600 #define FW_OFLD_TX_DATA_WR_MORE_S 15
601 #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
603 #define FW_OFLD_TX_DATA_WR_SHOVE_S 14
604 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
605 #define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
607 #define FW_OFLD_TX_DATA_WR_ULPMODE_S 10
608 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
610 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6
611 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \
612 ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
616 #define FW_CMD_WR_DMA (1U << 17)
621 #define FW_CMD_WR_DMA_S 17
622 #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S)
624 struct fw_eth_tx_pkt_vm_wr {
626 __be32 equiq_to_len16;
634 #define FW_CMD_MAX_TIMEOUT 10000
637 * If a host driver does a HELLO and discovers that there's already a MASTER
638 * selected, we may have to wait for that MASTER to finish issuing RESET,
639 * configuration and INITIALIZE commands. Also, there's a possibility that
640 * our own HELLO may get lost if it happens right as the MASTER is issuign a
641 * RESET command, so we need to be willing to make a few retries of our HELLO.
643 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
644 #define FW_CMD_HELLO_RETRIES 3
647 enum fw_cmd_opcodes {
652 FW_INITIALIZE_CMD = 0x06,
653 FW_CAPS_CONFIG_CMD = 0x07,
654 FW_PARAMS_CMD = 0x08,
657 FW_EQ_MNGT_CMD = 0x11,
658 FW_EQ_ETH_CMD = 0x12,
659 FW_EQ_CTRL_CMD = 0x13,
660 FW_EQ_OFLD_CMD = 0x21,
662 FW_VI_MAC_CMD = 0x15,
663 FW_VI_RXMODE_CMD = 0x16,
664 FW_VI_ENABLE_CMD = 0x17,
665 FW_ACL_MAC_CMD = 0x18,
666 FW_ACL_VLAN_CMD = 0x19,
667 FW_VI_STATS_CMD = 0x1a,
669 FW_PORT_STATS_CMD = 0x1c,
670 FW_PORT_LB_STATS_CMD = 0x1d,
671 FW_PORT_TRACE_CMD = 0x1e,
672 FW_PORT_TRACE_MMAP_CMD = 0x1f,
673 FW_RSS_IND_TBL_CMD = 0x20,
674 FW_RSS_GLB_CONFIG_CMD = 0x22,
675 FW_RSS_VI_CONFIG_CMD = 0x23,
677 FW_LASTC2E_CMD = 0x40,
683 FW_CMD_CAP_PF = 0x01,
684 FW_CMD_CAP_DMAQ = 0x02,
685 FW_CMD_CAP_PORT = 0x04,
686 FW_CMD_CAP_PORTPROMISC = 0x08,
687 FW_CMD_CAP_PORTSTATS = 0x10,
688 FW_CMD_CAP_VF = 0x80,
692 * Generic command header flit0
699 #define FW_CMD_OP_S 24
700 #define FW_CMD_OP_M 0xff
701 #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S)
702 #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
704 #define FW_CMD_REQUEST_S 23
705 #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S)
706 #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U)
708 #define FW_CMD_READ_S 22
709 #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S)
710 #define FW_CMD_READ_F FW_CMD_READ_V(1U)
712 #define FW_CMD_WRITE_S 21
713 #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S)
714 #define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U)
716 #define FW_CMD_EXEC_S 20
717 #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S)
718 #define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U)
720 #define FW_CMD_RAMASK_S 20
721 #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S)
723 #define FW_CMD_RETVAL_S 8
724 #define FW_CMD_RETVAL_M 0xff
725 #define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S)
726 #define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
728 #define FW_CMD_LEN16_S 0
729 #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S)
731 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
733 enum fw_ldst_addrspc {
734 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
735 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
736 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
737 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
738 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
739 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
740 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
741 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
742 FW_LDST_ADDRSPC_MDIO = 0x0018,
743 FW_LDST_ADDRSPC_MPS = 0x0020,
744 FW_LDST_ADDRSPC_FUNC = 0x0028,
745 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
748 enum fw_ldst_mps_fid {
753 enum fw_ldst_func_access_ctl {
754 FW_LDST_FUNC_ACC_CTL_VIID,
755 FW_LDST_FUNC_ACC_CTL_FID
758 enum fw_ldst_func_mod_index {
763 __be32 op_to_addrspace;
764 #define FW_LDST_CMD_ADDRSPACE(x) ((x) << 0)
765 __be32 cycles_to_len16;
767 struct fw_ldst_addrval {
771 struct fw_ldst_idctxt {
783 struct fw_ldst_mdio {
799 struct fw_ldst_func {
807 struct fw_ldst_pcie {
820 #define FW_LDST_CMD_MSG(x) ((x) << 31)
821 #define FW_LDST_CMD_PADDR(x) ((x) << 8)
822 #define FW_LDST_CMD_MMD(x) ((x) << 0)
823 #define FW_LDST_CMD_FID(x) ((x) << 15)
824 #define FW_LDST_CMD_CTL(x) ((x) << 0)
825 #define FW_LDST_CMD_RPLCPF(x) ((x) << 0)
826 #define FW_LDST_CMD_LC (1U << 4)
827 #define FW_LDST_CMD_NACCESS(x) ((x) << 0)
828 #define FW_LDST_CMD_FN(x) ((x) << 0)
830 struct fw_reset_cmd {
837 #define FW_RESET_CMD_HALT_SHIFT 31
838 #define FW_RESET_CMD_HALT_MASK 0x1
839 #define FW_RESET_CMD_HALT(x) ((x) << FW_RESET_CMD_HALT_SHIFT)
840 #define FW_RESET_CMD_HALT_GET(x) \
841 (((x) >> FW_RESET_CMD_HALT_SHIFT) & FW_RESET_CMD_HALT_MASK)
844 fw_hello_cmd_stage_os = 0x0
847 struct fw_hello_cmd {
850 __be32 err_to_clearinit;
851 #define FW_HELLO_CMD_ERR (1U << 31)
852 #define FW_HELLO_CMD_INIT (1U << 30)
853 #define FW_HELLO_CMD_MASTERDIS(x) ((x) << 29)
854 #define FW_HELLO_CMD_MASTERFORCE(x) ((x) << 28)
855 #define FW_HELLO_CMD_MBMASTER_MASK 0xfU
856 #define FW_HELLO_CMD_MBMASTER_SHIFT 24
857 #define FW_HELLO_CMD_MBMASTER(x) ((x) << FW_HELLO_CMD_MBMASTER_SHIFT)
858 #define FW_HELLO_CMD_MBMASTER_GET(x) \
859 (((x) >> FW_HELLO_CMD_MBMASTER_SHIFT) & FW_HELLO_CMD_MBMASTER_MASK)
860 #define FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << 23)
861 #define FW_HELLO_CMD_MBASYNCNOT(x) ((x) << 20)
862 #define FW_HELLO_CMD_STAGE(x) ((x) << 17)
863 #define FW_HELLO_CMD_CLEARINIT (1U << 16)
873 struct fw_initialize_cmd {
879 enum fw_caps_config_hm {
880 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
881 FW_CAPS_CONFIG_HM_PL = 0x00000002,
882 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
883 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
884 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
885 FW_CAPS_CONFIG_HM_TP = 0x00000020,
886 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
887 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
888 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
889 FW_CAPS_CONFIG_HM_MC = 0x00000200,
890 FW_CAPS_CONFIG_HM_LE = 0x00000400,
891 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
892 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
893 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
894 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
895 FW_CAPS_CONFIG_HM_MI = 0x00008000,
896 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
897 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
898 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
899 FW_CAPS_CONFIG_HM_MA = 0x00080000,
900 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
901 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
902 FW_CAPS_CONFIG_HM_UART = 0x00400000,
903 FW_CAPS_CONFIG_HM_SF = 0x00800000,
906 enum fw_caps_config_nbm {
907 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
908 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
911 enum fw_caps_config_link {
912 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
913 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
914 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
917 enum fw_caps_config_switch {
918 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
919 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
922 enum fw_caps_config_nic {
923 FW_CAPS_CONFIG_NIC = 0x00000001,
924 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
927 enum fw_caps_config_ofld {
928 FW_CAPS_CONFIG_OFLD = 0x00000001,
931 enum fw_caps_config_rdma {
932 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
933 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
936 enum fw_caps_config_iscsi {
937 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
938 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
939 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
940 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
943 enum fw_caps_config_fcoe {
944 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
945 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
946 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004,
950 FW_MEMTYPE_CF_EDC0 = 0x0,
951 FW_MEMTYPE_CF_EDC1 = 0x1,
952 FW_MEMTYPE_CF_EXTMEM = 0x2,
953 FW_MEMTYPE_CF_FLASH = 0x4,
954 FW_MEMTYPE_CF_INTERNAL = 0x5,
957 struct fw_caps_config_cmd {
959 __be32 cfvalid_to_len16;
977 #define FW_CAPS_CONFIG_CMD_CFVALID (1U << 27)
978 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) ((x) << 24)
979 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) ((x) << 16)
982 * params command mnemonics
984 enum fw_params_mnem {
985 FW_PARAMS_MNEM_DEV = 1, /* device params */
986 FW_PARAMS_MNEM_PFVF = 2, /* function params */
987 FW_PARAMS_MNEM_REG = 3, /* limited register access */
988 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
995 enum fw_params_param_dev {
996 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
997 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
998 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
999 * allocated by the device's
1002 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1003 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04,
1004 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1005 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1006 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07,
1007 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1008 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1009 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1010 FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1011 FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1012 FW_PARAMS_PARAM_DEV_CF = 0x0D,
1013 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1014 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1015 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1019 * physical and virtual function parameters
1021 enum fw_params_param_pfvf {
1022 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
1023 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1024 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1025 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1026 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1027 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1028 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1029 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1030 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1031 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1032 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1033 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1034 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1035 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1036 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1037 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1038 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
1039 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1040 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
1041 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1042 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1043 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1044 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
1045 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
1046 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
1047 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1048 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
1049 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
1050 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26,
1051 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27,
1052 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28,
1053 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1054 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1055 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B,
1056 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
1057 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1058 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1059 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1060 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
1064 * dma queue parameters
1066 enum fw_params_param_dmaq {
1067 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1068 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1069 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1070 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1071 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1072 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1075 #define FW_PARAMS_MNEM(x) ((x) << 24)
1076 #define FW_PARAMS_PARAM_X(x) ((x) << 16)
1077 #define FW_PARAMS_PARAM_Y_SHIFT 8
1078 #define FW_PARAMS_PARAM_Y_MASK 0xffU
1079 #define FW_PARAMS_PARAM_Y(x) ((x) << FW_PARAMS_PARAM_Y_SHIFT)
1080 #define FW_PARAMS_PARAM_Y_GET(x) (((x) >> FW_PARAMS_PARAM_Y_SHIFT) &\
1081 FW_PARAMS_PARAM_Y_MASK)
1082 #define FW_PARAMS_PARAM_Z_SHIFT 0
1083 #define FW_PARAMS_PARAM_Z_MASK 0xffu
1084 #define FW_PARAMS_PARAM_Z(x) ((x) << FW_PARAMS_PARAM_Z_SHIFT)
1085 #define FW_PARAMS_PARAM_Z_GET(x) (((x) >> FW_PARAMS_PARAM_Z_SHIFT) &\
1086 FW_PARAMS_PARAM_Z_MASK)
1087 #define FW_PARAMS_PARAM_XYZ(x) ((x) << 0)
1088 #define FW_PARAMS_PARAM_YZ(x) ((x) << 0)
1090 struct fw_params_cmd {
1092 __be32 retval_len16;
1093 struct fw_params_param {
1099 #define FW_PARAMS_CMD_PFN(x) ((x) << 8)
1100 #define FW_PARAMS_CMD_VFN(x) ((x) << 0)
1102 struct fw_pfvf_cmd {
1104 __be32 retval_len16;
1105 __be32 niqflint_niq;
1107 __be32 tc_to_nexactf;
1108 __be32 r_caps_to_nethctrl;
1114 #define FW_PFVF_CMD_PFN(x) ((x) << 8)
1115 #define FW_PFVF_CMD_VFN(x) ((x) << 0)
1117 #define FW_PFVF_CMD_NIQFLINT(x) ((x) << 20)
1118 #define FW_PFVF_CMD_NIQFLINT_GET(x) (((x) >> 20) & 0xfff)
1120 #define FW_PFVF_CMD_NIQ(x) ((x) << 0)
1121 #define FW_PFVF_CMD_NIQ_GET(x) (((x) >> 0) & 0xfffff)
1123 #define FW_PFVF_CMD_TYPE (1 << 31)
1124 #define FW_PFVF_CMD_TYPE_GET(x) (((x) >> 31) & 0x1)
1126 #define FW_PFVF_CMD_CMASK(x) ((x) << 24)
1127 #define FW_PFVF_CMD_CMASK_MASK 0xf
1128 #define FW_PFVF_CMD_CMASK_GET(x) (((x) >> 24) & FW_PFVF_CMD_CMASK_MASK)
1130 #define FW_PFVF_CMD_PMASK(x) ((x) << 20)
1131 #define FW_PFVF_CMD_PMASK_MASK 0xf
1132 #define FW_PFVF_CMD_PMASK_GET(x) (((x) >> 20) & FW_PFVF_CMD_PMASK_MASK)
1134 #define FW_PFVF_CMD_NEQ(x) ((x) << 0)
1135 #define FW_PFVF_CMD_NEQ_GET(x) (((x) >> 0) & 0xfffff)
1137 #define FW_PFVF_CMD_TC(x) ((x) << 24)
1138 #define FW_PFVF_CMD_TC_GET(x) (((x) >> 24) & 0xff)
1140 #define FW_PFVF_CMD_NVI(x) ((x) << 16)
1141 #define FW_PFVF_CMD_NVI_GET(x) (((x) >> 16) & 0xff)
1143 #define FW_PFVF_CMD_NEXACTF(x) ((x) << 0)
1144 #define FW_PFVF_CMD_NEXACTF_GET(x) (((x) >> 0) & 0xffff)
1146 #define FW_PFVF_CMD_R_CAPS(x) ((x) << 24)
1147 #define FW_PFVF_CMD_R_CAPS_GET(x) (((x) >> 24) & 0xff)
1149 #define FW_PFVF_CMD_WX_CAPS(x) ((x) << 16)
1150 #define FW_PFVF_CMD_WX_CAPS_GET(x) (((x) >> 16) & 0xff)
1152 #define FW_PFVF_CMD_NETHCTRL(x) ((x) << 0)
1153 #define FW_PFVF_CMD_NETHCTRL_GET(x) (((x) >> 0) & 0xffff)
1156 FW_IQ_TYPE_FL_INT_CAP,
1157 FW_IQ_TYPE_NO_FL_INT_CAP
1162 __be32 alloc_to_len16;
1167 __be32 type_to_iqandstindex;
1168 __be16 iqdroprss_to_iqesize;
1171 __be32 iqns_to_fl0congen;
1172 __be16 fl0dcaen_to_fl0cidxfthresh;
1175 __be32 fl1cngchmap_to_fl1congen;
1176 __be16 fl1dcaen_to_fl1cidxfthresh;
1181 #define FW_IQ_CMD_PFN(x) ((x) << 8)
1182 #define FW_IQ_CMD_VFN(x) ((x) << 0)
1184 #define FW_IQ_CMD_ALLOC (1U << 31)
1185 #define FW_IQ_CMD_FREE (1U << 30)
1186 #define FW_IQ_CMD_MODIFY (1U << 29)
1187 #define FW_IQ_CMD_IQSTART(x) ((x) << 28)
1188 #define FW_IQ_CMD_IQSTOP(x) ((x) << 27)
1190 #define FW_IQ_CMD_TYPE(x) ((x) << 29)
1191 #define FW_IQ_CMD_IQASYNCH(x) ((x) << 28)
1192 #define FW_IQ_CMD_VIID(x) ((x) << 16)
1193 #define FW_IQ_CMD_IQANDST(x) ((x) << 15)
1194 #define FW_IQ_CMD_IQANUS(x) ((x) << 14)
1195 #define FW_IQ_CMD_IQANUD(x) ((x) << 12)
1196 #define FW_IQ_CMD_IQANDSTINDEX(x) ((x) << 0)
1198 #define FW_IQ_CMD_IQDROPRSS (1U << 15)
1199 #define FW_IQ_CMD_IQGTSMODE (1U << 14)
1200 #define FW_IQ_CMD_IQPCIECH(x) ((x) << 12)
1201 #define FW_IQ_CMD_IQDCAEN(x) ((x) << 11)
1202 #define FW_IQ_CMD_IQDCACPU(x) ((x) << 6)
1203 #define FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << 4)
1204 #define FW_IQ_CMD_IQO (1U << 3)
1205 #define FW_IQ_CMD_IQCPRIO(x) ((x) << 2)
1206 #define FW_IQ_CMD_IQESIZE(x) ((x) << 0)
1208 #define FW_IQ_CMD_IQNS(x) ((x) << 31)
1209 #define FW_IQ_CMD_IQRO(x) ((x) << 30)
1210 #define FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << 28)
1211 #define FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << 27)
1212 #define FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << 26)
1213 #define FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << 20)
1214 #define FW_IQ_CMD_FL0CACHELOCK(x) ((x) << 15)
1215 #define FW_IQ_CMD_FL0DBP(x) ((x) << 14)
1216 #define FW_IQ_CMD_FL0DATANS(x) ((x) << 13)
1217 #define FW_IQ_CMD_FL0DATARO(x) ((x) << 12)
1218 #define FW_IQ_CMD_FL0CONGCIF(x) ((x) << 11)
1219 #define FW_IQ_CMD_FL0ONCHIP(x) ((x) << 10)
1220 #define FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << 9)
1221 #define FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << 8)
1222 #define FW_IQ_CMD_FL0FETCHNS(x) ((x) << 7)
1223 #define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6)
1224 #define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4)
1225 #define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3)
1226 #define FW_IQ_CMD_FL0PADEN(x) ((x) << 2)
1227 #define FW_IQ_CMD_FL0PACKEN(x) ((x) << 1)
1228 #define FW_IQ_CMD_FL0CONGEN (1U << 0)
1230 #define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15)
1231 #define FW_IQ_CMD_FL0DCACPU(x) ((x) << 10)
1232 #define FW_IQ_CMD_FL0FBMIN(x) ((x) << 7)
1233 #define FW_IQ_CMD_FL0FBMAX(x) ((x) << 4)
1234 #define FW_IQ_CMD_FL0CIDXFTHRESHO (1U << 3)
1235 #define FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << 0)
1237 #define FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << 20)
1238 #define FW_IQ_CMD_FL1CACHELOCK(x) ((x) << 15)
1239 #define FW_IQ_CMD_FL1DBP(x) ((x) << 14)
1240 #define FW_IQ_CMD_FL1DATANS(x) ((x) << 13)
1241 #define FW_IQ_CMD_FL1DATARO(x) ((x) << 12)
1242 #define FW_IQ_CMD_FL1CONGCIF(x) ((x) << 11)
1243 #define FW_IQ_CMD_FL1ONCHIP(x) ((x) << 10)
1244 #define FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << 9)
1245 #define FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << 8)
1246 #define FW_IQ_CMD_FL1FETCHNS(x) ((x) << 7)
1247 #define FW_IQ_CMD_FL1FETCHRO(x) ((x) << 6)
1248 #define FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << 4)
1249 #define FW_IQ_CMD_FL1CPRIO(x) ((x) << 3)
1250 #define FW_IQ_CMD_FL1PADEN (1U << 2)
1251 #define FW_IQ_CMD_FL1PACKEN (1U << 1)
1252 #define FW_IQ_CMD_FL1CONGEN (1U << 0)
1254 #define FW_IQ_CMD_FL1DCAEN(x) ((x) << 15)
1255 #define FW_IQ_CMD_FL1DCACPU(x) ((x) << 10)
1256 #define FW_IQ_CMD_FL1FBMIN(x) ((x) << 7)
1257 #define FW_IQ_CMD_FL1FBMAX(x) ((x) << 4)
1258 #define FW_IQ_CMD_FL1CIDXFTHRESHO (1U << 3)
1259 #define FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << 0)
1261 struct fw_eq_eth_cmd {
1263 __be32 alloc_to_len16;
1265 __be32 physeqid_pkd;
1266 __be32 fetchszm_to_iqid;
1267 __be32 dcaen_to_eqsize;
1274 #define FW_EQ_ETH_CMD_PFN(x) ((x) << 8)
1275 #define FW_EQ_ETH_CMD_VFN(x) ((x) << 0)
1276 #define FW_EQ_ETH_CMD_ALLOC (1U << 31)
1277 #define FW_EQ_ETH_CMD_FREE (1U << 30)
1278 #define FW_EQ_ETH_CMD_MODIFY (1U << 29)
1279 #define FW_EQ_ETH_CMD_EQSTART (1U << 28)
1280 #define FW_EQ_ETH_CMD_EQSTOP (1U << 27)
1282 #define FW_EQ_ETH_CMD_EQID(x) ((x) << 0)
1283 #define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
1284 #define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0)
1285 #define FW_EQ_ETH_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
1287 #define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26)
1288 #define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25)
1289 #define FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << 24)
1290 #define FW_EQ_ETH_CMD_FETCHNS(x) ((x) << 23)
1291 #define FW_EQ_ETH_CMD_FETCHRO(x) ((x) << 22)
1292 #define FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << 20)
1293 #define FW_EQ_ETH_CMD_CPRIO(x) ((x) << 19)
1294 #define FW_EQ_ETH_CMD_ONCHIP(x) ((x) << 18)
1295 #define FW_EQ_ETH_CMD_PCIECHN(x) ((x) << 16)
1296 #define FW_EQ_ETH_CMD_IQID(x) ((x) << 0)
1298 #define FW_EQ_ETH_CMD_DCAEN(x) ((x) << 31)
1299 #define FW_EQ_ETH_CMD_DCACPU(x) ((x) << 26)
1300 #define FW_EQ_ETH_CMD_FBMIN(x) ((x) << 23)
1301 #define FW_EQ_ETH_CMD_FBMAX(x) ((x) << 20)
1302 #define FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << 19)
1303 #define FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << 16)
1304 #define FW_EQ_ETH_CMD_EQSIZE(x) ((x) << 0)
1306 #define FW_EQ_ETH_CMD_AUTOEQUEQE (1U << 30)
1307 #define FW_EQ_ETH_CMD_VIID(x) ((x) << 16)
1309 struct fw_eq_ctrl_cmd {
1311 __be32 alloc_to_len16;
1312 __be32 cmpliqid_eqid;
1313 __be32 physeqid_pkd;
1314 __be32 fetchszm_to_iqid;
1315 __be32 dcaen_to_eqsize;
1319 #define FW_EQ_CTRL_CMD_PFN(x) ((x) << 8)
1320 #define FW_EQ_CTRL_CMD_VFN(x) ((x) << 0)
1322 #define FW_EQ_CTRL_CMD_ALLOC (1U << 31)
1323 #define FW_EQ_CTRL_CMD_FREE (1U << 30)
1324 #define FW_EQ_CTRL_CMD_MODIFY (1U << 29)
1325 #define FW_EQ_CTRL_CMD_EQSTART (1U << 28)
1326 #define FW_EQ_CTRL_CMD_EQSTOP (1U << 27)
1328 #define FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << 20)
1329 #define FW_EQ_CTRL_CMD_EQID(x) ((x) << 0)
1330 #define FW_EQ_CTRL_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
1331 #define FW_EQ_CTRL_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
1333 #define FW_EQ_CTRL_CMD_FETCHSZM (1U << 26)
1334 #define FW_EQ_CTRL_CMD_STATUSPGNS (1U << 25)
1335 #define FW_EQ_CTRL_CMD_STATUSPGRO (1U << 24)
1336 #define FW_EQ_CTRL_CMD_FETCHNS (1U << 23)
1337 #define FW_EQ_CTRL_CMD_FETCHRO (1U << 22)
1338 #define FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << 20)
1339 #define FW_EQ_CTRL_CMD_CPRIO(x) ((x) << 19)
1340 #define FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << 18)
1341 #define FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << 16)
1342 #define FW_EQ_CTRL_CMD_IQID(x) ((x) << 0)
1344 #define FW_EQ_CTRL_CMD_DCAEN(x) ((x) << 31)
1345 #define FW_EQ_CTRL_CMD_DCACPU(x) ((x) << 26)
1346 #define FW_EQ_CTRL_CMD_FBMIN(x) ((x) << 23)
1347 #define FW_EQ_CTRL_CMD_FBMAX(x) ((x) << 20)
1348 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) ((x) << 19)
1349 #define FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << 16)
1350 #define FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << 0)
1352 struct fw_eq_ofld_cmd {
1354 __be32 alloc_to_len16;
1356 __be32 physeqid_pkd;
1357 __be32 fetchszm_to_iqid;
1358 __be32 dcaen_to_eqsize;
1362 #define FW_EQ_OFLD_CMD_PFN(x) ((x) << 8)
1363 #define FW_EQ_OFLD_CMD_VFN(x) ((x) << 0)
1365 #define FW_EQ_OFLD_CMD_ALLOC (1U << 31)
1366 #define FW_EQ_OFLD_CMD_FREE (1U << 30)
1367 #define FW_EQ_OFLD_CMD_MODIFY (1U << 29)
1368 #define FW_EQ_OFLD_CMD_EQSTART (1U << 28)
1369 #define FW_EQ_OFLD_CMD_EQSTOP (1U << 27)
1371 #define FW_EQ_OFLD_CMD_EQID(x) ((x) << 0)
1372 #define FW_EQ_OFLD_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
1373 #define FW_EQ_OFLD_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
1375 #define FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << 26)
1376 #define FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << 25)
1377 #define FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << 24)
1378 #define FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << 23)
1379 #define FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << 22)
1380 #define FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << 20)
1381 #define FW_EQ_OFLD_CMD_CPRIO(x) ((x) << 19)
1382 #define FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << 18)
1383 #define FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << 16)
1384 #define FW_EQ_OFLD_CMD_IQID(x) ((x) << 0)
1386 #define FW_EQ_OFLD_CMD_DCAEN(x) ((x) << 31)
1387 #define FW_EQ_OFLD_CMD_DCACPU(x) ((x) << 26)
1388 #define FW_EQ_OFLD_CMD_FBMIN(x) ((x) << 23)
1389 #define FW_EQ_OFLD_CMD_FBMAX(x) ((x) << 20)
1390 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) ((x) << 19)
1391 #define FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << 16)
1392 #define FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << 0)
1395 * Macros for VIID parsing:
1396 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1399 #define FW_VIID_PFN_S 8
1400 #define FW_VIID_PFN_M 0x7
1401 #define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
1403 #define FW_VIID_VIVLD_GET(x) (((x) >> 7) & 0x1)
1404 #define FW_VIID_VIN_GET(x) (((x) >> 0) & 0x7F)
1408 __be32 alloc_to_len16;
1424 #define FW_VI_CMD_PFN(x) ((x) << 8)
1425 #define FW_VI_CMD_VFN(x) ((x) << 0)
1426 #define FW_VI_CMD_ALLOC (1U << 31)
1427 #define FW_VI_CMD_FREE (1U << 30)
1428 #define FW_VI_CMD_VIID(x) ((x) << 0)
1429 #define FW_VI_CMD_VIID_GET(x) ((x) & 0xfff)
1430 #define FW_VI_CMD_PORTID(x) ((x) << 4)
1431 #define FW_VI_CMD_PORTID_GET(x) (((x) >> 4) & 0xf)
1432 #define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff)
1434 /* Special VI_MAC command index ids */
1435 #define FW_VI_MAC_ADD_MAC 0x3FF
1436 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1437 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD
1438 #define FW_CLS_TCAM_NUM_ENTRIES 336
1440 enum fw_vi_mac_smac {
1441 FW_VI_MAC_MPS_TCAM_ENTRY,
1442 FW_VI_MAC_MPS_TCAM_ONLY,
1444 FW_VI_MAC_SMT_AND_MPSTCAM
1447 enum fw_vi_mac_result {
1448 FW_VI_MAC_R_SUCCESS,
1449 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
1450 FW_VI_MAC_R_SMAC_FAIL,
1451 FW_VI_MAC_R_F_ACL_CHECK
1454 struct fw_vi_mac_cmd {
1456 __be32 freemacs_to_len16;
1458 struct fw_vi_mac_exact {
1459 __be16 valid_to_idx;
1462 struct fw_vi_mac_hash {
1468 #define FW_VI_MAC_CMD_VIID(x) ((x) << 0)
1469 #define FW_VI_MAC_CMD_FREEMACS(x) ((x) << 31)
1470 #define FW_VI_MAC_CMD_HASHVECEN (1U << 23)
1471 #define FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << 22)
1472 #define FW_VI_MAC_CMD_VALID (1U << 15)
1473 #define FW_VI_MAC_CMD_PRIO(x) ((x) << 12)
1474 #define FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << 10)
1475 #define FW_VI_MAC_CMD_SMAC_RESULT_GET(x) (((x) >> 10) & 0x3)
1476 #define FW_VI_MAC_CMD_IDX(x) ((x) << 0)
1477 #define FW_VI_MAC_CMD_IDX_GET(x) (((x) >> 0) & 0x3ff)
1479 #define FW_RXMODE_MTU_NO_CHG 65535
1481 struct fw_vi_rxmode_cmd {
1483 __be32 retval_len16;
1484 __be32 mtu_to_vlanexen;
1488 #define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0)
1489 #define FW_VI_RXMODE_CMD_MTU_MASK 0xffff
1490 #define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16)
1491 #define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3
1492 #define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14)
1493 #define FW_VI_RXMODE_CMD_ALLMULTIEN_MASK 0x3
1494 #define FW_VI_RXMODE_CMD_ALLMULTIEN(x) ((x) << 12)
1495 #define FW_VI_RXMODE_CMD_BROADCASTEN_MASK 0x3
1496 #define FW_VI_RXMODE_CMD_BROADCASTEN(x) ((x) << 10)
1497 #define FW_VI_RXMODE_CMD_VLANEXEN_MASK 0x3
1498 #define FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << 8)
1500 struct fw_vi_enable_cmd {
1502 __be32 ien_to_len16;
1508 #define FW_VI_ENABLE_CMD_VIID(x) ((x) << 0)
1509 #define FW_VI_ENABLE_CMD_IEN(x) ((x) << 31)
1510 #define FW_VI_ENABLE_CMD_EEN(x) ((x) << 30)
1511 #define FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << 28)
1512 #define FW_VI_ENABLE_CMD_LED (1U << 29)
1514 /* VI VF stats offset definitions */
1515 #define VI_VF_NUM_STATS 16
1516 enum fw_vi_stats_vf_index {
1517 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
1518 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
1519 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
1520 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
1521 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
1522 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
1523 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
1524 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
1525 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
1526 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
1527 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
1528 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
1529 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
1530 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
1531 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
1532 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
1535 /* VI PF stats offset definitions */
1536 #define VI_PF_NUM_STATS 17
1537 enum fw_vi_stats_pf_index {
1538 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1539 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1540 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1541 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1542 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1543 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1544 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1545 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1546 FW_VI_PF_STAT_RX_BYTES_IX,
1547 FW_VI_PF_STAT_RX_FRAMES_IX,
1548 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1549 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1550 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1551 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1552 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1553 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1554 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1557 struct fw_vi_stats_cmd {
1559 __be32 retval_len16;
1561 struct fw_vi_stats_ctl {
1572 struct fw_vi_stats_pf {
1573 __be64 tx_bcast_bytes;
1574 __be64 tx_bcast_frames;
1575 __be64 tx_mcast_bytes;
1576 __be64 tx_mcast_frames;
1577 __be64 tx_ucast_bytes;
1578 __be64 tx_ucast_frames;
1579 __be64 tx_offload_bytes;
1580 __be64 tx_offload_frames;
1582 __be64 rx_pf_frames;
1583 __be64 rx_bcast_bytes;
1584 __be64 rx_bcast_frames;
1585 __be64 rx_mcast_bytes;
1586 __be64 rx_mcast_frames;
1587 __be64 rx_ucast_bytes;
1588 __be64 rx_ucast_frames;
1589 __be64 rx_err_frames;
1591 struct fw_vi_stats_vf {
1592 __be64 tx_bcast_bytes;
1593 __be64 tx_bcast_frames;
1594 __be64 tx_mcast_bytes;
1595 __be64 tx_mcast_frames;
1596 __be64 tx_ucast_bytes;
1597 __be64 tx_ucast_frames;
1598 __be64 tx_drop_frames;
1599 __be64 tx_offload_bytes;
1600 __be64 tx_offload_frames;
1601 __be64 rx_bcast_bytes;
1602 __be64 rx_bcast_frames;
1603 __be64 rx_mcast_bytes;
1604 __be64 rx_mcast_frames;
1605 __be64 rx_ucast_bytes;
1606 __be64 rx_ucast_frames;
1607 __be64 rx_err_frames;
1612 #define FW_VI_STATS_CMD_VIID(x) ((x) << 0)
1613 #define FW_VI_STATS_CMD_NSTATS(x) ((x) << 12)
1614 #define FW_VI_STATS_CMD_IX(x) ((x) << 0)
1616 struct fw_acl_mac_cmd {
1631 #define FW_ACL_MAC_CMD_PFN(x) ((x) << 8)
1632 #define FW_ACL_MAC_CMD_VFN(x) ((x) << 0)
1633 #define FW_ACL_MAC_CMD_EN(x) ((x) << 31)
1635 struct fw_acl_vlan_cmd {
1644 #define FW_ACL_VLAN_CMD_PFN(x) ((x) << 8)
1645 #define FW_ACL_VLAN_CMD_VFN(x) ((x) << 0)
1646 #define FW_ACL_VLAN_CMD_EN(x) ((x) << 31)
1647 #define FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << 7)
1648 #define FW_ACL_VLAN_CMD_FM(x) ((x) << 6)
1651 FW_PORT_CAP_SPEED_100M = 0x0001,
1652 FW_PORT_CAP_SPEED_1G = 0x0002,
1653 FW_PORT_CAP_SPEED_2_5G = 0x0004,
1654 FW_PORT_CAP_SPEED_10G = 0x0008,
1655 FW_PORT_CAP_SPEED_40G = 0x0010,
1656 FW_PORT_CAP_SPEED_100G = 0x0020,
1657 FW_PORT_CAP_FC_RX = 0x0040,
1658 FW_PORT_CAP_FC_TX = 0x0080,
1659 FW_PORT_CAP_ANEG = 0x0100,
1660 FW_PORT_CAP_MDI_0 = 0x0200,
1661 FW_PORT_CAP_MDI_1 = 0x0400,
1662 FW_PORT_CAP_BEAN = 0x0800,
1663 FW_PORT_CAP_PMA_LPBK = 0x1000,
1664 FW_PORT_CAP_PCS_LPBK = 0x2000,
1665 FW_PORT_CAP_PHYXS_LPBK = 0x4000,
1666 FW_PORT_CAP_FAR_END_LPBK = 0x8000,
1670 FW_PORT_MDI_UNCHANGED,
1672 FW_PORT_MDI_F_STRAIGHT,
1673 FW_PORT_MDI_F_CROSSOVER
1676 #define FW_PORT_MDI(x) ((x) << 9)
1678 enum fw_port_action {
1679 FW_PORT_ACTION_L1_CFG = 0x0001,
1680 FW_PORT_ACTION_L2_CFG = 0x0002,
1681 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1682 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
1683 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
1684 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006,
1685 FW_PORT_ACTION_DCB_READ_RECV = 0x0007,
1686 FW_PORT_ACTION_DCB_READ_DET = 0x0008,
1687 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
1688 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
1689 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
1690 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
1691 FW_PORT_ACTION_L1_LPBK = 0x0021,
1692 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022,
1693 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023,
1694 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
1695 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
1696 FW_PORT_ACTION_PHY_RESET = 0x0040,
1697 FW_PORT_ACTION_PMA_RESET = 0x0041,
1698 FW_PORT_ACTION_PCS_RESET = 0x0042,
1699 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
1700 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
1701 FW_PORT_ACTION_AN_RESET = 0x0045
1704 enum fw_port_l2cfg_ctlbf {
1705 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
1706 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
1707 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
1708 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
1709 FW_PORT_L2_CTLBF_IVLAN = 0x10,
1710 FW_PORT_L2_CTLBF_TXIPG = 0x20
1713 enum fw_port_dcb_versions {
1714 FW_PORT_DCB_VER_UNKNOWN,
1715 FW_PORT_DCB_VER_CEE1D0,
1716 FW_PORT_DCB_VER_CEE1D01,
1717 FW_PORT_DCB_VER_IEEE,
1718 FW_PORT_DCB_VER_AUTO = 7
1721 enum fw_port_dcb_cfg {
1722 FW_PORT_DCB_CFG_PG = 0x01,
1723 FW_PORT_DCB_CFG_PFC = 0x02,
1724 FW_PORT_DCB_CFG_APPL = 0x04
1727 enum fw_port_dcb_cfg_rc {
1728 FW_PORT_DCB_CFG_SUCCESS = 0x0,
1729 FW_PORT_DCB_CFG_ERROR = 0x1
1732 enum fw_port_dcb_type {
1733 FW_PORT_DCB_TYPE_PGID = 0x00,
1734 FW_PORT_DCB_TYPE_PGRATE = 0x01,
1735 FW_PORT_DCB_TYPE_PRIORATE = 0x02,
1736 FW_PORT_DCB_TYPE_PFC = 0x03,
1737 FW_PORT_DCB_TYPE_APP_ID = 0x04,
1738 FW_PORT_DCB_TYPE_CONTROL = 0x05,
1741 enum fw_port_dcb_feature_state {
1742 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
1743 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
1744 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
1745 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
1748 struct fw_port_cmd {
1749 __be32 op_to_portid;
1750 __be32 action_to_len16;
1752 struct fw_port_l1cfg {
1756 struct fw_port_l2cfg {
1758 __u8 ovlan3_to_ivlan0;
1760 __be16 txipg_force_pinfo;
1771 struct fw_port_info {
1772 __be32 lstatus_to_modtype;
1782 struct fw_port_diags {
1788 struct fw_port_dcb_pgid {
1795 struct fw_port_dcb_pgrate {
1799 __u8 num_tcs_supported;
1803 struct fw_port_dcb_priorate {
1807 __u8 strict_priorate[8];
1809 struct fw_port_dcb_pfc {
1816 struct fw_port_app_priority {
1825 struct fw_port_dcb_control {
1828 __be16 dcb_version_to_app_state;
1836 #define FW_PORT_CMD_READ (1U << 22)
1838 #define FW_PORT_CMD_PORTID(x) ((x) << 0)
1839 #define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf)
1841 #define FW_PORT_CMD_ACTION(x) ((x) << 16)
1842 #define FW_PORT_CMD_ACTION_GET(x) (((x) >> 16) & 0xffff)
1844 #define FW_PORT_CMD_CTLBF(x) ((x) << 10)
1845 #define FW_PORT_CMD_OVLAN3(x) ((x) << 7)
1846 #define FW_PORT_CMD_OVLAN2(x) ((x) << 6)
1847 #define FW_PORT_CMD_OVLAN1(x) ((x) << 5)
1848 #define FW_PORT_CMD_OVLAN0(x) ((x) << 4)
1849 #define FW_PORT_CMD_IVLAN0(x) ((x) << 3)
1851 #define FW_PORT_CMD_TXIPG(x) ((x) << 19)
1853 #define FW_PORT_CMD_LSTATUS (1U << 31)
1854 #define FW_PORT_CMD_LSTATUS_GET(x) (((x) >> 31) & 0x1)
1855 #define FW_PORT_CMD_LSPEED(x) ((x) << 24)
1856 #define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f)
1857 #define FW_PORT_CMD_TXPAUSE (1U << 23)
1858 #define FW_PORT_CMD_RXPAUSE (1U << 22)
1859 #define FW_PORT_CMD_MDIOCAP (1U << 21)
1860 #define FW_PORT_CMD_MDIOADDR_GET(x) (((x) >> 16) & 0x1f)
1861 #define FW_PORT_CMD_LPTXPAUSE (1U << 15)
1862 #define FW_PORT_CMD_LPRXPAUSE (1U << 14)
1863 #define FW_PORT_CMD_PTYPE_MASK 0x1f
1864 #define FW_PORT_CMD_PTYPE_GET(x) (((x) >> 8) & FW_PORT_CMD_PTYPE_MASK)
1865 #define FW_PORT_CMD_MODTYPE_MASK 0x1f
1866 #define FW_PORT_CMD_MODTYPE_GET(x) (((x) >> 0) & FW_PORT_CMD_MODTYPE_MASK)
1868 #define FW_PORT_CMD_DCBXDIS (1U << 7)
1869 #define FW_PORT_CMD_APPLY (1U << 7)
1870 #define FW_PORT_CMD_ALL_SYNCD (1U << 7)
1871 #define FW_PORT_CMD_DCB_VERSION_GET(x) (((x) >> 8) & 0xf)
1873 #define FW_PORT_CMD_PPPEN(x) ((x) << 31)
1874 #define FW_PORT_CMD_TPSRC(x) ((x) << 28)
1875 #define FW_PORT_CMD_NCSISRC(x) ((x) << 24)
1877 #define FW_PORT_CMD_CH0(x) ((x) << 20)
1878 #define FW_PORT_CMD_CH1(x) ((x) << 16)
1879 #define FW_PORT_CMD_CH2(x) ((x) << 12)
1880 #define FW_PORT_CMD_CH3(x) ((x) << 8)
1881 #define FW_PORT_CMD_NCSICH(x) ((x) << 4)
1884 FW_PORT_TYPE_FIBER_XFI,
1885 FW_PORT_TYPE_FIBER_XAUI,
1886 FW_PORT_TYPE_BT_SGMII,
1887 FW_PORT_TYPE_BT_XFI,
1888 FW_PORT_TYPE_BT_XAUI,
1895 FW_PORT_TYPE_BP4_AP,
1896 FW_PORT_TYPE_QSFP_10G,
1898 FW_PORT_TYPE_BP40_BA,
1900 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_MASK
1903 enum fw_port_module_type {
1904 FW_PORT_MOD_TYPE_NA,
1905 FW_PORT_MOD_TYPE_LR,
1906 FW_PORT_MOD_TYPE_SR,
1907 FW_PORT_MOD_TYPE_ER,
1908 FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
1909 FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
1910 FW_PORT_MOD_TYPE_LRM,
1911 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_MASK - 3,
1912 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_MASK - 2,
1913 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_MASK - 1,
1915 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK
1918 enum fw_port_mod_sub_type {
1919 FW_PORT_MOD_SUB_TYPE_NA,
1920 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1921 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1922 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1923 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1924 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1925 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1927 /* The following will never been in the VPD. They are TWINAX cable
1928 * lengths decoded from SFP+ module i2c PROMs. These should
1929 * almost certainly go somewhere else ...
1931 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1932 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1933 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1934 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1938 #define FW_NUM_PORT_STATS 50
1939 #define FW_NUM_PORT_TX_STATS 23
1940 #define FW_NUM_PORT_RX_STATS 27
1942 enum fw_port_stats_tx_index {
1943 FW_STAT_TX_PORT_BYTES_IX,
1944 FW_STAT_TX_PORT_FRAMES_IX,
1945 FW_STAT_TX_PORT_BCAST_IX,
1946 FW_STAT_TX_PORT_MCAST_IX,
1947 FW_STAT_TX_PORT_UCAST_IX,
1948 FW_STAT_TX_PORT_ERROR_IX,
1949 FW_STAT_TX_PORT_64B_IX,
1950 FW_STAT_TX_PORT_65B_127B_IX,
1951 FW_STAT_TX_PORT_128B_255B_IX,
1952 FW_STAT_TX_PORT_256B_511B_IX,
1953 FW_STAT_TX_PORT_512B_1023B_IX,
1954 FW_STAT_TX_PORT_1024B_1518B_IX,
1955 FW_STAT_TX_PORT_1519B_MAX_IX,
1956 FW_STAT_TX_PORT_DROP_IX,
1957 FW_STAT_TX_PORT_PAUSE_IX,
1958 FW_STAT_TX_PORT_PPP0_IX,
1959 FW_STAT_TX_PORT_PPP1_IX,
1960 FW_STAT_TX_PORT_PPP2_IX,
1961 FW_STAT_TX_PORT_PPP3_IX,
1962 FW_STAT_TX_PORT_PPP4_IX,
1963 FW_STAT_TX_PORT_PPP5_IX,
1964 FW_STAT_TX_PORT_PPP6_IX,
1965 FW_STAT_TX_PORT_PPP7_IX
1968 enum fw_port_stat_rx_index {
1969 FW_STAT_RX_PORT_BYTES_IX,
1970 FW_STAT_RX_PORT_FRAMES_IX,
1971 FW_STAT_RX_PORT_BCAST_IX,
1972 FW_STAT_RX_PORT_MCAST_IX,
1973 FW_STAT_RX_PORT_UCAST_IX,
1974 FW_STAT_RX_PORT_MTU_ERROR_IX,
1975 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1976 FW_STAT_RX_PORT_CRC_ERROR_IX,
1977 FW_STAT_RX_PORT_LEN_ERROR_IX,
1978 FW_STAT_RX_PORT_SYM_ERROR_IX,
1979 FW_STAT_RX_PORT_64B_IX,
1980 FW_STAT_RX_PORT_65B_127B_IX,
1981 FW_STAT_RX_PORT_128B_255B_IX,
1982 FW_STAT_RX_PORT_256B_511B_IX,
1983 FW_STAT_RX_PORT_512B_1023B_IX,
1984 FW_STAT_RX_PORT_1024B_1518B_IX,
1985 FW_STAT_RX_PORT_1519B_MAX_IX,
1986 FW_STAT_RX_PORT_PAUSE_IX,
1987 FW_STAT_RX_PORT_PPP0_IX,
1988 FW_STAT_RX_PORT_PPP1_IX,
1989 FW_STAT_RX_PORT_PPP2_IX,
1990 FW_STAT_RX_PORT_PPP3_IX,
1991 FW_STAT_RX_PORT_PPP4_IX,
1992 FW_STAT_RX_PORT_PPP5_IX,
1993 FW_STAT_RX_PORT_PPP6_IX,
1994 FW_STAT_RX_PORT_PPP7_IX,
1995 FW_STAT_RX_PORT_LESS_64B_IX
1998 struct fw_port_stats_cmd {
1999 __be32 op_to_portid;
2000 __be32 retval_len16;
2001 union fw_port_stats {
2002 struct fw_port_stats_ctl {
2014 struct fw_port_stats_all {
2023 __be64 tx_128b_255b;
2024 __be64 tx_256b_511b;
2025 __be64 tx_512b_1023b;
2026 __be64 tx_1024b_1518b;
2027 __be64 tx_1519b_max;
2043 __be64 rx_mtu_error;
2044 __be64 rx_mtu_crc_error;
2045 __be64 rx_crc_error;
2046 __be64 rx_len_error;
2047 __be64 rx_sym_error;
2050 __be64 rx_128b_255b;
2051 __be64 rx_256b_511b;
2052 __be64 rx_512b_1023b;
2053 __be64 rx_1024b_1518b;
2054 __be64 rx_1519b_max;
2071 #define FW_PORT_STATS_CMD_NSTATS(x) ((x) << 4)
2072 #define FW_PORT_STATS_CMD_BG_BM(x) ((x) << 0)
2073 #define FW_PORT_STATS_CMD_TX(x) ((x) << 7)
2074 #define FW_PORT_STATS_CMD_IX(x) ((x) << 0)
2076 /* port loopback stats */
2077 #define FW_NUM_LB_STATS 16
2078 enum fw_port_lb_stats_index {
2079 FW_STAT_LB_PORT_BYTES_IX,
2080 FW_STAT_LB_PORT_FRAMES_IX,
2081 FW_STAT_LB_PORT_BCAST_IX,
2082 FW_STAT_LB_PORT_MCAST_IX,
2083 FW_STAT_LB_PORT_UCAST_IX,
2084 FW_STAT_LB_PORT_ERROR_IX,
2085 FW_STAT_LB_PORT_64B_IX,
2086 FW_STAT_LB_PORT_65B_127B_IX,
2087 FW_STAT_LB_PORT_128B_255B_IX,
2088 FW_STAT_LB_PORT_256B_511B_IX,
2089 FW_STAT_LB_PORT_512B_1023B_IX,
2090 FW_STAT_LB_PORT_1024B_1518B_IX,
2091 FW_STAT_LB_PORT_1519B_MAX_IX,
2092 FW_STAT_LB_PORT_DROP_FRAMES_IX
2095 struct fw_port_lb_stats_cmd {
2096 __be32 op_to_lbport;
2097 __be32 retval_len16;
2098 union fw_port_lb_stats {
2099 struct fw_port_lb_stats_ctl {
2111 struct fw_port_lb_stats_all {
2120 __be64 tx_128b_255b;
2121 __be64 tx_256b_511b;
2122 __be64 tx_512b_1023b;
2123 __be64 tx_1024b_1518b;
2124 __be64 tx_1519b_max;
2131 #define FW_PORT_LB_STATS_CMD_LBPORT(x) ((x) << 0)
2132 #define FW_PORT_LB_STATS_CMD_NSTATS(x) ((x) << 4)
2133 #define FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << 0)
2134 #define FW_PORT_LB_STATS_CMD_IX(x) ((x) << 0)
2136 struct fw_rss_ind_tbl_cmd {
2138 #define FW_RSS_IND_TBL_CMD_VIID(x) ((x) << 0)
2139 __be32 retval_len16;
2144 #define FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << 20)
2145 #define FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << 10)
2146 #define FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << 0)
2150 __be32 iq12_to_iq14;
2151 __be32 iq15_to_iq17;
2152 __be32 iq18_to_iq20;
2153 __be32 iq21_to_iq23;
2154 __be32 iq24_to_iq26;
2155 __be32 iq27_to_iq29;
2160 struct fw_rss_glb_config_cmd {
2162 __be32 retval_len16;
2163 union fw_rss_glb_config {
2164 struct fw_rss_glb_config_manual {
2170 struct fw_rss_glb_config_basicvirtual {
2172 __be32 synmapen_to_hashtoeplitz;
2173 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN (1U << 8)
2174 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 (1U << 7)
2175 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 (1U << 6)
2176 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 (1U << 5)
2177 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 (1U << 4)
2178 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN (1U << 3)
2179 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN (1U << 2)
2180 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP (1U << 1)
2181 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ (1U << 0)
2188 #define FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << 28)
2189 #define FW_RSS_GLB_CONFIG_CMD_MODE_GET(x) (((x) >> 28) & 0xf)
2191 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
2192 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2194 struct fw_rss_vi_config_cmd {
2196 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
2197 __be32 retval_len16;
2198 union fw_rss_vi_config {
2199 struct fw_rss_vi_config_manual {
2204 struct fw_rss_vi_config_basicvirtual {
2206 __be32 defaultq_to_udpen;
2207 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) ((x) << 16)
2208 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_GET(x) (((x) >> 16) & 0x3ff)
2209 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4)
2210 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN (1U << 3)
2211 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2)
2212 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN (1U << 1)
2213 #define FW_RSS_VI_CONFIG_CMD_UDPEN (1U << 0)
2220 struct fw_clip_cmd {
2222 __be32 alloc_to_len16;
2228 #define S_FW_CLIP_CMD_ALLOC 31
2229 #define M_FW_CLIP_CMD_ALLOC 0x1
2230 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
2231 #define G_FW_CLIP_CMD_ALLOC(x) \
2232 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
2233 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
2235 #define S_FW_CLIP_CMD_FREE 30
2236 #define M_FW_CLIP_CMD_FREE 0x1
2237 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
2238 #define G_FW_CLIP_CMD_FREE(x) \
2239 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
2240 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
2242 enum fw_error_type {
2243 FW_ERROR_TYPE_EXCEPTION = 0x0,
2244 FW_ERROR_TYPE_HWMODULE = 0x1,
2245 FW_ERROR_TYPE_WR = 0x2,
2246 FW_ERROR_TYPE_ACL = 0x3,
2249 struct fw_error_cmd {
2253 struct fw_error_exception {
2256 struct fw_error_hwmodule {
2260 struct fw_error_wr {
2266 struct fw_error_acl {
2277 struct fw_debug_cmd {
2279 #define FW_DEBUG_CMD_TYPE_GET(x) ((x) & 0xff)
2282 struct fw_debug_assert {
2288 u8 filename_8_15[8];
2291 struct fw_debug_prt {
2294 __be32 dprtstrparam0;
2295 __be32 dprtstrparam1;
2296 __be32 dprtstrparam2;
2297 __be32 dprtstrparam3;
2302 #define FW_PCIE_FW_ERR (1U << 31)
2303 #define FW_PCIE_FW_INIT (1U << 30)
2304 #define FW_PCIE_FW_HALT (1U << 29)
2305 #define FW_PCIE_FW_MASTER_VLD (1U << 15)
2306 #define FW_PCIE_FW_MASTER_MASK 0x7
2307 #define FW_PCIE_FW_MASTER_SHIFT 12
2308 #define FW_PCIE_FW_MASTER(x) ((x) << FW_PCIE_FW_MASTER_SHIFT)
2309 #define FW_PCIE_FW_MASTER_GET(x) (((x) >> FW_PCIE_FW_MASTER_SHIFT) & \
2310 FW_PCIE_FW_MASTER_MASK)
2311 #define FW_PCIE_FW_EVAL_MASK 0x7
2312 #define FW_PCIE_FW_EVAL_SHIFT 24
2313 #define FW_PCIE_FW_EVAL_GET(x) (((x) >> FW_PCIE_FW_EVAL_SHIFT) & \
2314 FW_PCIE_FW_EVAL_MASK)
2318 u8 chip; /* terminator chip type */
2319 __be16 len512; /* bin length in units of 512-bytes */
2320 __be32 fw_ver; /* firmware version */
2321 __be32 tp_microcode_ver;
2326 u8 intfver_iscsipdu;
2334 __be32 reserved6[23];
2342 #define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff)
2343 #define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff)
2344 #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff)
2345 #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff)
2347 enum fw_hdr_intfver {
2348 FW_HDR_INTFVER_NIC = 0x00,
2349 FW_HDR_INTFVER_VNIC = 0x00,
2350 FW_HDR_INTFVER_OFLD = 0x00,
2351 FW_HDR_INTFVER_RI = 0x00,
2352 FW_HDR_INTFVER_ISCSIPDU = 0x00,
2353 FW_HDR_INTFVER_ISCSI = 0x00,
2354 FW_HDR_INTFVER_FCOEPDU = 0x00,
2355 FW_HDR_INTFVER_FCOE = 0x00,
2359 FW_HDR_FLAGS_RESET_HALT = 0x00000001,
2362 #endif /* _T4FW_INTERFACE_H_ */