2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #ifndef _T4FW_INTERFACE_H_
36 #define _T4FW_INTERFACE_H_
38 #define FW_T4VF_SGE_BASE_ADDR 0x0000
39 #define FW_T4VF_MPS_BASE_ADDR 0x0100
40 #define FW_T4VF_PL_BASE_ADDR 0x0200
41 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240
42 #define FW_T4VF_CIM_BASE_ADDR 0x0300
48 FW_ETH_TX_PKT_WR = 0x08,
50 FW_OFLD_TX_DATA_WR = 0x0b,
52 FW_ETH_TX_PKT_VM_WR = 0x11,
55 FW_RI_RDMA_WRITE_WR = 0x14,
57 FW_RI_RDMA_READ_WR = 0x16,
59 FW_RI_BIND_MW_WR = 0x18,
60 FW_RI_FR_NSMR_WR = 0x19,
61 FW_RI_INV_LSTAG_WR = 0x1a,
70 #define FW_WR_OP(x) ((x) << 24)
71 #define FW_WR_OP_GET(x) (((x) >> 24) & 0xff)
72 #define FW_WR_ATOMIC(x) ((x) << 23)
73 #define FW_WR_FLUSH(x) ((x) << 22)
74 #define FW_WR_COMPL(x) ((x) << 21)
75 #define FW_WR_IMMDLEN_MASK 0xff
76 #define FW_WR_IMMDLEN(x) ((x) << 0)
78 #define FW_WR_EQUIQ (1U << 31)
79 #define FW_WR_EQUEQ (1U << 30)
80 #define FW_WR_FLOWID(x) ((x) << 8)
81 #define FW_WR_LEN16(x) ((x) << 0)
83 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B
97 struct fw_eth_tx_pkt_wr {
99 __be32 equiq_to_len16;
104 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */
108 FW_FLOWC_MNEM_SNDNXT,
109 FW_FLOWC_MNEM_RCVNXT,
110 FW_FLOWC_MNEM_SNDBUF,
114 struct fw_flowc_mnemval {
121 __be32 op_to_nparams;
122 #define FW_FLOWC_WR_NPARAMS(x) ((x) << 0)
124 struct fw_flowc_mnemval mnemval[0];
127 struct fw_ofld_tx_data_wr {
128 __be32 op_to_immdlen;
131 __be32 tunnel_to_proxy;
132 #define FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << 19)
133 #define FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << 18)
134 #define FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << 17)
135 #define FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << 16)
136 #define FW_OFLD_TX_DATA_WR_MORE(x) ((x) << 15)
137 #define FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << 14)
138 #define FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << 10)
139 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) ((x) << 6)
144 #define FW_CMD_WR_DMA (1U << 17)
149 struct fw_eth_tx_pkt_vm_wr {
151 __be32 equiq_to_len16;
159 #define FW_CMD_MAX_TIMEOUT 3000
162 * If a host driver does a HELLO and discovers that there's already a MASTER
163 * selected, we may have to wait for that MASTER to finish issuing RESET,
164 * configuration and INITIALIZE commands. Also, there's a possibility that
165 * our own HELLO may get lost if it happens right as the MASTER is issuign a
166 * RESET command, so we need to be willing to make a few retries of our HELLO.
168 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
169 #define FW_CMD_HELLO_RETRIES 3
172 enum fw_cmd_opcodes {
177 FW_INITIALIZE_CMD = 0x06,
178 FW_CAPS_CONFIG_CMD = 0x07,
179 FW_PARAMS_CMD = 0x08,
182 FW_EQ_MNGT_CMD = 0x11,
183 FW_EQ_ETH_CMD = 0x12,
184 FW_EQ_CTRL_CMD = 0x13,
185 FW_EQ_OFLD_CMD = 0x21,
187 FW_VI_MAC_CMD = 0x15,
188 FW_VI_RXMODE_CMD = 0x16,
189 FW_VI_ENABLE_CMD = 0x17,
190 FW_ACL_MAC_CMD = 0x18,
191 FW_ACL_VLAN_CMD = 0x19,
192 FW_VI_STATS_CMD = 0x1a,
194 FW_PORT_STATS_CMD = 0x1c,
195 FW_PORT_LB_STATS_CMD = 0x1d,
196 FW_PORT_TRACE_CMD = 0x1e,
197 FW_PORT_TRACE_MMAP_CMD = 0x1f,
198 FW_RSS_IND_TBL_CMD = 0x20,
199 FW_RSS_GLB_CONFIG_CMD = 0x22,
200 FW_RSS_VI_CONFIG_CMD = 0x23,
201 FW_LASTC2E_CMD = 0x40,
207 FW_CMD_CAP_PF = 0x01,
208 FW_CMD_CAP_DMAQ = 0x02,
209 FW_CMD_CAP_PORT = 0x04,
210 FW_CMD_CAP_PORTPROMISC = 0x08,
211 FW_CMD_CAP_PORTSTATS = 0x10,
212 FW_CMD_CAP_VF = 0x80,
216 * Generic command header flit0
223 #define FW_CMD_OP(x) ((x) << 24)
224 #define FW_CMD_OP_GET(x) (((x) >> 24) & 0xff)
225 #define FW_CMD_REQUEST (1U << 23)
226 #define FW_CMD_REQUEST_GET(x) (((x) >> 23) & 0x1)
227 #define FW_CMD_READ (1U << 22)
228 #define FW_CMD_WRITE (1U << 21)
229 #define FW_CMD_EXEC (1U << 20)
230 #define FW_CMD_RAMASK(x) ((x) << 20)
231 #define FW_CMD_RETVAL(x) ((x) << 8)
232 #define FW_CMD_RETVAL_GET(x) (((x) >> 8) & 0xff)
233 #define FW_CMD_LEN16(x) ((x) << 0)
234 #define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
236 enum fw_ldst_addrspc {
237 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
238 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
239 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
240 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
241 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
242 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
243 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
244 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
245 FW_LDST_ADDRSPC_MDIO = 0x0018,
246 FW_LDST_ADDRSPC_MPS = 0x0020,
247 FW_LDST_ADDRSPC_FUNC = 0x0028,
248 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
251 enum fw_ldst_mps_fid {
256 enum fw_ldst_func_access_ctl {
257 FW_LDST_FUNC_ACC_CTL_VIID,
258 FW_LDST_FUNC_ACC_CTL_FID
261 enum fw_ldst_func_mod_index {
266 __be32 op_to_addrspace;
267 #define FW_LDST_CMD_ADDRSPACE(x) ((x) << 0)
268 __be32 cycles_to_len16;
270 struct fw_ldst_addrval {
274 struct fw_ldst_idctxt {
286 struct fw_ldst_mdio {
302 struct fw_ldst_func {
310 struct fw_ldst_pcie {
323 #define FW_LDST_CMD_MSG(x) ((x) << 31)
324 #define FW_LDST_CMD_PADDR(x) ((x) << 8)
325 #define FW_LDST_CMD_MMD(x) ((x) << 0)
326 #define FW_LDST_CMD_FID(x) ((x) << 15)
327 #define FW_LDST_CMD_CTL(x) ((x) << 0)
328 #define FW_LDST_CMD_RPLCPF(x) ((x) << 0)
329 #define FW_LDST_CMD_LC (1U << 4)
330 #define FW_LDST_CMD_NACCESS(x) ((x) << 0)
331 #define FW_LDST_CMD_FN(x) ((x) << 0)
333 struct fw_reset_cmd {
340 #define FW_RESET_CMD_HALT_SHIFT 31
341 #define FW_RESET_CMD_HALT_MASK 0x1
342 #define FW_RESET_CMD_HALT(x) ((x) << FW_RESET_CMD_HALT_SHIFT)
343 #define FW_RESET_CMD_HALT_GET(x) \
344 (((x) >> FW_RESET_CMD_HALT_SHIFT) & FW_RESET_CMD_HALT_MASK)
347 fw_hello_cmd_stage_os = 0x0
350 struct fw_hello_cmd {
353 __be32 err_to_clearinit;
354 #define FW_HELLO_CMD_ERR (1U << 31)
355 #define FW_HELLO_CMD_INIT (1U << 30)
356 #define FW_HELLO_CMD_MASTERDIS(x) ((x) << 29)
357 #define FW_HELLO_CMD_MASTERFORCE(x) ((x) << 28)
358 #define FW_HELLO_CMD_MBMASTER_MASK 0xfU
359 #define FW_HELLO_CMD_MBMASTER_SHIFT 24
360 #define FW_HELLO_CMD_MBMASTER(x) ((x) << FW_HELLO_CMD_MBMASTER_SHIFT)
361 #define FW_HELLO_CMD_MBMASTER_GET(x) \
362 (((x) >> FW_HELLO_CMD_MBMASTER_SHIFT) & FW_HELLO_CMD_MBMASTER_MASK)
363 #define FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << 23)
364 #define FW_HELLO_CMD_MBASYNCNOT(x) ((x) << 20)
365 #define FW_HELLO_CMD_STAGE(x) ((x) << 17)
366 #define FW_HELLO_CMD_CLEARINIT (1U << 16)
376 struct fw_initialize_cmd {
382 enum fw_caps_config_hm {
383 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
384 FW_CAPS_CONFIG_HM_PL = 0x00000002,
385 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
386 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
387 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
388 FW_CAPS_CONFIG_HM_TP = 0x00000020,
389 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
390 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
391 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
392 FW_CAPS_CONFIG_HM_MC = 0x00000200,
393 FW_CAPS_CONFIG_HM_LE = 0x00000400,
394 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
395 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
396 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
397 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
398 FW_CAPS_CONFIG_HM_MI = 0x00008000,
399 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
400 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
401 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
402 FW_CAPS_CONFIG_HM_MA = 0x00080000,
403 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
404 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
405 FW_CAPS_CONFIG_HM_UART = 0x00400000,
406 FW_CAPS_CONFIG_HM_SF = 0x00800000,
409 enum fw_caps_config_nbm {
410 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
411 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
414 enum fw_caps_config_link {
415 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
416 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
417 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
420 enum fw_caps_config_switch {
421 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
422 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
425 enum fw_caps_config_nic {
426 FW_CAPS_CONFIG_NIC = 0x00000001,
427 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
430 enum fw_caps_config_ofld {
431 FW_CAPS_CONFIG_OFLD = 0x00000001,
434 enum fw_caps_config_rdma {
435 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
436 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
439 enum fw_caps_config_iscsi {
440 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
441 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
442 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
443 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
446 enum fw_caps_config_fcoe {
447 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
448 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
449 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004,
453 FW_MEMTYPE_CF_EDC0 = 0x0,
454 FW_MEMTYPE_CF_EDC1 = 0x1,
455 FW_MEMTYPE_CF_EXTMEM = 0x2,
456 FW_MEMTYPE_CF_FLASH = 0x4,
457 FW_MEMTYPE_CF_INTERNAL = 0x5,
460 struct fw_caps_config_cmd {
462 __be32 cfvalid_to_len16;
480 #define FW_CAPS_CONFIG_CMD_CFVALID (1U << 27)
481 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) ((x) << 24)
482 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) ((x) << 16)
485 * params command mnemonics
487 enum fw_params_mnem {
488 FW_PARAMS_MNEM_DEV = 1, /* device params */
489 FW_PARAMS_MNEM_PFVF = 2, /* function params */
490 FW_PARAMS_MNEM_REG = 3, /* limited register access */
491 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
498 enum fw_params_param_dev {
499 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
500 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
501 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
502 * allocated by the device's
505 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
506 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04,
507 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
508 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
509 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07,
510 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
511 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
512 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
513 FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
514 FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
515 FW_PARAMS_PARAM_DEV_CF = 0x0D,
519 * physical and virtual function parameters
521 enum fw_params_param_pfvf {
522 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
523 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
524 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
525 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
526 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
527 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
528 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
529 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
530 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
531 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
532 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
533 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
534 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
535 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
536 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
537 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
538 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
539 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
540 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
541 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
542 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
543 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
544 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
545 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
546 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
547 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
548 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
549 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
550 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26,
551 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27,
552 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28,
553 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
554 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
555 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B,
556 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
557 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
558 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E
562 * dma queue parameters
564 enum fw_params_param_dmaq {
565 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
566 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
567 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
568 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
569 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
572 #define FW_PARAMS_MNEM(x) ((x) << 24)
573 #define FW_PARAMS_PARAM_X(x) ((x) << 16)
574 #define FW_PARAMS_PARAM_Y_SHIFT 8
575 #define FW_PARAMS_PARAM_Y_MASK 0xffU
576 #define FW_PARAMS_PARAM_Y(x) ((x) << FW_PARAMS_PARAM_Y_SHIFT)
577 #define FW_PARAMS_PARAM_Y_GET(x) (((x) >> FW_PARAMS_PARAM_Y_SHIFT) &\
578 FW_PARAMS_PARAM_Y_MASK)
579 #define FW_PARAMS_PARAM_Z_SHIFT 0
580 #define FW_PARAMS_PARAM_Z_MASK 0xffu
581 #define FW_PARAMS_PARAM_Z(x) ((x) << FW_PARAMS_PARAM_Z_SHIFT)
582 #define FW_PARAMS_PARAM_Z_GET(x) (((x) >> FW_PARAMS_PARAM_Z_SHIFT) &\
583 FW_PARAMS_PARAM_Z_MASK)
584 #define FW_PARAMS_PARAM_XYZ(x) ((x) << 0)
585 #define FW_PARAMS_PARAM_YZ(x) ((x) << 0)
587 struct fw_params_cmd {
590 struct fw_params_param {
596 #define FW_PARAMS_CMD_PFN(x) ((x) << 8)
597 #define FW_PARAMS_CMD_VFN(x) ((x) << 0)
604 __be32 tc_to_nexactf;
605 __be32 r_caps_to_nethctrl;
611 #define FW_PFVF_CMD_PFN(x) ((x) << 8)
612 #define FW_PFVF_CMD_VFN(x) ((x) << 0)
614 #define FW_PFVF_CMD_NIQFLINT(x) ((x) << 20)
615 #define FW_PFVF_CMD_NIQFLINT_GET(x) (((x) >> 20) & 0xfff)
617 #define FW_PFVF_CMD_NIQ(x) ((x) << 0)
618 #define FW_PFVF_CMD_NIQ_GET(x) (((x) >> 0) & 0xfffff)
620 #define FW_PFVF_CMD_TYPE (1 << 31)
621 #define FW_PFVF_CMD_TYPE_GET(x) (((x) >> 31) & 0x1)
623 #define FW_PFVF_CMD_CMASK(x) ((x) << 24)
624 #define FW_PFVF_CMD_CMASK_MASK 0xf
625 #define FW_PFVF_CMD_CMASK_GET(x) (((x) >> 24) & FW_PFVF_CMD_CMASK_MASK)
627 #define FW_PFVF_CMD_PMASK(x) ((x) << 20)
628 #define FW_PFVF_CMD_PMASK_MASK 0xf
629 #define FW_PFVF_CMD_PMASK_GET(x) (((x) >> 20) & FW_PFVF_CMD_PMASK_MASK)
631 #define FW_PFVF_CMD_NEQ(x) ((x) << 0)
632 #define FW_PFVF_CMD_NEQ_GET(x) (((x) >> 0) & 0xfffff)
634 #define FW_PFVF_CMD_TC(x) ((x) << 24)
635 #define FW_PFVF_CMD_TC_GET(x) (((x) >> 24) & 0xff)
637 #define FW_PFVF_CMD_NVI(x) ((x) << 16)
638 #define FW_PFVF_CMD_NVI_GET(x) (((x) >> 16) & 0xff)
640 #define FW_PFVF_CMD_NEXACTF(x) ((x) << 0)
641 #define FW_PFVF_CMD_NEXACTF_GET(x) (((x) >> 0) & 0xffff)
643 #define FW_PFVF_CMD_R_CAPS(x) ((x) << 24)
644 #define FW_PFVF_CMD_R_CAPS_GET(x) (((x) >> 24) & 0xff)
646 #define FW_PFVF_CMD_WX_CAPS(x) ((x) << 16)
647 #define FW_PFVF_CMD_WX_CAPS_GET(x) (((x) >> 16) & 0xff)
649 #define FW_PFVF_CMD_NETHCTRL(x) ((x) << 0)
650 #define FW_PFVF_CMD_NETHCTRL_GET(x) (((x) >> 0) & 0xffff)
653 FW_IQ_TYPE_FL_INT_CAP,
654 FW_IQ_TYPE_NO_FL_INT_CAP
659 __be32 alloc_to_len16;
664 __be32 type_to_iqandstindex;
665 __be16 iqdroprss_to_iqesize;
668 __be32 iqns_to_fl0congen;
669 __be16 fl0dcaen_to_fl0cidxfthresh;
672 __be32 fl1cngchmap_to_fl1congen;
673 __be16 fl1dcaen_to_fl1cidxfthresh;
678 #define FW_IQ_CMD_PFN(x) ((x) << 8)
679 #define FW_IQ_CMD_VFN(x) ((x) << 0)
681 #define FW_IQ_CMD_ALLOC (1U << 31)
682 #define FW_IQ_CMD_FREE (1U << 30)
683 #define FW_IQ_CMD_MODIFY (1U << 29)
684 #define FW_IQ_CMD_IQSTART(x) ((x) << 28)
685 #define FW_IQ_CMD_IQSTOP(x) ((x) << 27)
687 #define FW_IQ_CMD_TYPE(x) ((x) << 29)
688 #define FW_IQ_CMD_IQASYNCH(x) ((x) << 28)
689 #define FW_IQ_CMD_VIID(x) ((x) << 16)
690 #define FW_IQ_CMD_IQANDST(x) ((x) << 15)
691 #define FW_IQ_CMD_IQANUS(x) ((x) << 14)
692 #define FW_IQ_CMD_IQANUD(x) ((x) << 12)
693 #define FW_IQ_CMD_IQANDSTINDEX(x) ((x) << 0)
695 #define FW_IQ_CMD_IQDROPRSS (1U << 15)
696 #define FW_IQ_CMD_IQGTSMODE (1U << 14)
697 #define FW_IQ_CMD_IQPCIECH(x) ((x) << 12)
698 #define FW_IQ_CMD_IQDCAEN(x) ((x) << 11)
699 #define FW_IQ_CMD_IQDCACPU(x) ((x) << 6)
700 #define FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << 4)
701 #define FW_IQ_CMD_IQO (1U << 3)
702 #define FW_IQ_CMD_IQCPRIO(x) ((x) << 2)
703 #define FW_IQ_CMD_IQESIZE(x) ((x) << 0)
705 #define FW_IQ_CMD_IQNS(x) ((x) << 31)
706 #define FW_IQ_CMD_IQRO(x) ((x) << 30)
707 #define FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << 28)
708 #define FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << 27)
709 #define FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << 26)
710 #define FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << 20)
711 #define FW_IQ_CMD_FL0CACHELOCK(x) ((x) << 15)
712 #define FW_IQ_CMD_FL0DBP(x) ((x) << 14)
713 #define FW_IQ_CMD_FL0DATANS(x) ((x) << 13)
714 #define FW_IQ_CMD_FL0DATARO(x) ((x) << 12)
715 #define FW_IQ_CMD_FL0CONGCIF(x) ((x) << 11)
716 #define FW_IQ_CMD_FL0ONCHIP(x) ((x) << 10)
717 #define FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << 9)
718 #define FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << 8)
719 #define FW_IQ_CMD_FL0FETCHNS(x) ((x) << 7)
720 #define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6)
721 #define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4)
722 #define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3)
723 #define FW_IQ_CMD_FL0PADEN(x) ((x) << 2)
724 #define FW_IQ_CMD_FL0PACKEN(x) ((x) << 1)
725 #define FW_IQ_CMD_FL0CONGEN (1U << 0)
727 #define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15)
728 #define FW_IQ_CMD_FL0DCACPU(x) ((x) << 10)
729 #define FW_IQ_CMD_FL0FBMIN(x) ((x) << 7)
730 #define FW_IQ_CMD_FL0FBMAX(x) ((x) << 4)
731 #define FW_IQ_CMD_FL0CIDXFTHRESHO (1U << 3)
732 #define FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << 0)
734 #define FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << 20)
735 #define FW_IQ_CMD_FL1CACHELOCK(x) ((x) << 15)
736 #define FW_IQ_CMD_FL1DBP(x) ((x) << 14)
737 #define FW_IQ_CMD_FL1DATANS(x) ((x) << 13)
738 #define FW_IQ_CMD_FL1DATARO(x) ((x) << 12)
739 #define FW_IQ_CMD_FL1CONGCIF(x) ((x) << 11)
740 #define FW_IQ_CMD_FL1ONCHIP(x) ((x) << 10)
741 #define FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << 9)
742 #define FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << 8)
743 #define FW_IQ_CMD_FL1FETCHNS(x) ((x) << 7)
744 #define FW_IQ_CMD_FL1FETCHRO(x) ((x) << 6)
745 #define FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << 4)
746 #define FW_IQ_CMD_FL1CPRIO(x) ((x) << 3)
747 #define FW_IQ_CMD_FL1PADEN (1U << 2)
748 #define FW_IQ_CMD_FL1PACKEN (1U << 1)
749 #define FW_IQ_CMD_FL1CONGEN (1U << 0)
751 #define FW_IQ_CMD_FL1DCAEN(x) ((x) << 15)
752 #define FW_IQ_CMD_FL1DCACPU(x) ((x) << 10)
753 #define FW_IQ_CMD_FL1FBMIN(x) ((x) << 7)
754 #define FW_IQ_CMD_FL1FBMAX(x) ((x) << 4)
755 #define FW_IQ_CMD_FL1CIDXFTHRESHO (1U << 3)
756 #define FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << 0)
758 struct fw_eq_eth_cmd {
760 __be32 alloc_to_len16;
763 __be32 fetchszm_to_iqid;
764 __be32 dcaen_to_eqsize;
771 #define FW_EQ_ETH_CMD_PFN(x) ((x) << 8)
772 #define FW_EQ_ETH_CMD_VFN(x) ((x) << 0)
773 #define FW_EQ_ETH_CMD_ALLOC (1U << 31)
774 #define FW_EQ_ETH_CMD_FREE (1U << 30)
775 #define FW_EQ_ETH_CMD_MODIFY (1U << 29)
776 #define FW_EQ_ETH_CMD_EQSTART (1U << 28)
777 #define FW_EQ_ETH_CMD_EQSTOP (1U << 27)
779 #define FW_EQ_ETH_CMD_EQID(x) ((x) << 0)
780 #define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
781 #define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0)
782 #define FW_EQ_ETH_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
784 #define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26)
785 #define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25)
786 #define FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << 24)
787 #define FW_EQ_ETH_CMD_FETCHNS(x) ((x) << 23)
788 #define FW_EQ_ETH_CMD_FETCHRO(x) ((x) << 22)
789 #define FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << 20)
790 #define FW_EQ_ETH_CMD_CPRIO(x) ((x) << 19)
791 #define FW_EQ_ETH_CMD_ONCHIP(x) ((x) << 18)
792 #define FW_EQ_ETH_CMD_PCIECHN(x) ((x) << 16)
793 #define FW_EQ_ETH_CMD_IQID(x) ((x) << 0)
795 #define FW_EQ_ETH_CMD_DCAEN(x) ((x) << 31)
796 #define FW_EQ_ETH_CMD_DCACPU(x) ((x) << 26)
797 #define FW_EQ_ETH_CMD_FBMIN(x) ((x) << 23)
798 #define FW_EQ_ETH_CMD_FBMAX(x) ((x) << 20)
799 #define FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << 19)
800 #define FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << 16)
801 #define FW_EQ_ETH_CMD_EQSIZE(x) ((x) << 0)
803 #define FW_EQ_ETH_CMD_VIID(x) ((x) << 16)
805 struct fw_eq_ctrl_cmd {
807 __be32 alloc_to_len16;
808 __be32 cmpliqid_eqid;
810 __be32 fetchszm_to_iqid;
811 __be32 dcaen_to_eqsize;
815 #define FW_EQ_CTRL_CMD_PFN(x) ((x) << 8)
816 #define FW_EQ_CTRL_CMD_VFN(x) ((x) << 0)
818 #define FW_EQ_CTRL_CMD_ALLOC (1U << 31)
819 #define FW_EQ_CTRL_CMD_FREE (1U << 30)
820 #define FW_EQ_CTRL_CMD_MODIFY (1U << 29)
821 #define FW_EQ_CTRL_CMD_EQSTART (1U << 28)
822 #define FW_EQ_CTRL_CMD_EQSTOP (1U << 27)
824 #define FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << 20)
825 #define FW_EQ_CTRL_CMD_EQID(x) ((x) << 0)
826 #define FW_EQ_CTRL_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
827 #define FW_EQ_CTRL_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
829 #define FW_EQ_CTRL_CMD_FETCHSZM (1U << 26)
830 #define FW_EQ_CTRL_CMD_STATUSPGNS (1U << 25)
831 #define FW_EQ_CTRL_CMD_STATUSPGRO (1U << 24)
832 #define FW_EQ_CTRL_CMD_FETCHNS (1U << 23)
833 #define FW_EQ_CTRL_CMD_FETCHRO (1U << 22)
834 #define FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << 20)
835 #define FW_EQ_CTRL_CMD_CPRIO(x) ((x) << 19)
836 #define FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << 18)
837 #define FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << 16)
838 #define FW_EQ_CTRL_CMD_IQID(x) ((x) << 0)
840 #define FW_EQ_CTRL_CMD_DCAEN(x) ((x) << 31)
841 #define FW_EQ_CTRL_CMD_DCACPU(x) ((x) << 26)
842 #define FW_EQ_CTRL_CMD_FBMIN(x) ((x) << 23)
843 #define FW_EQ_CTRL_CMD_FBMAX(x) ((x) << 20)
844 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) ((x) << 19)
845 #define FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << 16)
846 #define FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << 0)
848 struct fw_eq_ofld_cmd {
850 __be32 alloc_to_len16;
853 __be32 fetchszm_to_iqid;
854 __be32 dcaen_to_eqsize;
858 #define FW_EQ_OFLD_CMD_PFN(x) ((x) << 8)
859 #define FW_EQ_OFLD_CMD_VFN(x) ((x) << 0)
861 #define FW_EQ_OFLD_CMD_ALLOC (1U << 31)
862 #define FW_EQ_OFLD_CMD_FREE (1U << 30)
863 #define FW_EQ_OFLD_CMD_MODIFY (1U << 29)
864 #define FW_EQ_OFLD_CMD_EQSTART (1U << 28)
865 #define FW_EQ_OFLD_CMD_EQSTOP (1U << 27)
867 #define FW_EQ_OFLD_CMD_EQID(x) ((x) << 0)
868 #define FW_EQ_OFLD_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
869 #define FW_EQ_OFLD_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
871 #define FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << 26)
872 #define FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << 25)
873 #define FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << 24)
874 #define FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << 23)
875 #define FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << 22)
876 #define FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << 20)
877 #define FW_EQ_OFLD_CMD_CPRIO(x) ((x) << 19)
878 #define FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << 18)
879 #define FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << 16)
880 #define FW_EQ_OFLD_CMD_IQID(x) ((x) << 0)
882 #define FW_EQ_OFLD_CMD_DCAEN(x) ((x) << 31)
883 #define FW_EQ_OFLD_CMD_DCACPU(x) ((x) << 26)
884 #define FW_EQ_OFLD_CMD_FBMIN(x) ((x) << 23)
885 #define FW_EQ_OFLD_CMD_FBMAX(x) ((x) << 20)
886 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) ((x) << 19)
887 #define FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << 16)
888 #define FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << 0)
891 * Macros for VIID parsing:
892 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
894 #define FW_VIID_PFN_GET(x) (((x) >> 8) & 0x7)
895 #define FW_VIID_VIVLD_GET(x) (((x) >> 7) & 0x1)
896 #define FW_VIID_VIN_GET(x) (((x) >> 0) & 0x7F)
900 __be32 alloc_to_len16;
916 #define FW_VI_CMD_PFN(x) ((x) << 8)
917 #define FW_VI_CMD_VFN(x) ((x) << 0)
918 #define FW_VI_CMD_ALLOC (1U << 31)
919 #define FW_VI_CMD_FREE (1U << 30)
920 #define FW_VI_CMD_VIID(x) ((x) << 0)
921 #define FW_VI_CMD_VIID_GET(x) ((x) & 0xfff)
922 #define FW_VI_CMD_PORTID(x) ((x) << 4)
923 #define FW_VI_CMD_PORTID_GET(x) (((x) >> 4) & 0xf)
924 #define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff)
926 /* Special VI_MAC command index ids */
927 #define FW_VI_MAC_ADD_MAC 0x3FF
928 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
929 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD
930 #define FW_CLS_TCAM_NUM_ENTRIES 336
932 enum fw_vi_mac_smac {
933 FW_VI_MAC_MPS_TCAM_ENTRY,
934 FW_VI_MAC_MPS_TCAM_ONLY,
936 FW_VI_MAC_SMT_AND_MPSTCAM
939 enum fw_vi_mac_result {
941 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
942 FW_VI_MAC_R_SMAC_FAIL,
943 FW_VI_MAC_R_F_ACL_CHECK
946 struct fw_vi_mac_cmd {
948 __be32 freemacs_to_len16;
950 struct fw_vi_mac_exact {
954 struct fw_vi_mac_hash {
960 #define FW_VI_MAC_CMD_VIID(x) ((x) << 0)
961 #define FW_VI_MAC_CMD_FREEMACS(x) ((x) << 31)
962 #define FW_VI_MAC_CMD_HASHVECEN (1U << 23)
963 #define FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << 22)
964 #define FW_VI_MAC_CMD_VALID (1U << 15)
965 #define FW_VI_MAC_CMD_PRIO(x) ((x) << 12)
966 #define FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << 10)
967 #define FW_VI_MAC_CMD_SMAC_RESULT_GET(x) (((x) >> 10) & 0x3)
968 #define FW_VI_MAC_CMD_IDX(x) ((x) << 0)
969 #define FW_VI_MAC_CMD_IDX_GET(x) (((x) >> 0) & 0x3ff)
971 #define FW_RXMODE_MTU_NO_CHG 65535
973 struct fw_vi_rxmode_cmd {
976 __be32 mtu_to_vlanexen;
980 #define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0)
981 #define FW_VI_RXMODE_CMD_MTU_MASK 0xffff
982 #define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16)
983 #define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3
984 #define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14)
985 #define FW_VI_RXMODE_CMD_ALLMULTIEN_MASK 0x3
986 #define FW_VI_RXMODE_CMD_ALLMULTIEN(x) ((x) << 12)
987 #define FW_VI_RXMODE_CMD_BROADCASTEN_MASK 0x3
988 #define FW_VI_RXMODE_CMD_BROADCASTEN(x) ((x) << 10)
989 #define FW_VI_RXMODE_CMD_VLANEXEN_MASK 0x3
990 #define FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << 8)
992 struct fw_vi_enable_cmd {
1000 #define FW_VI_ENABLE_CMD_VIID(x) ((x) << 0)
1001 #define FW_VI_ENABLE_CMD_IEN(x) ((x) << 31)
1002 #define FW_VI_ENABLE_CMD_EEN(x) ((x) << 30)
1003 #define FW_VI_ENABLE_CMD_LED (1U << 29)
1005 /* VI VF stats offset definitions */
1006 #define VI_VF_NUM_STATS 16
1007 enum fw_vi_stats_vf_index {
1008 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
1009 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
1010 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
1011 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
1012 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
1013 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
1014 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
1015 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
1016 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
1017 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
1018 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
1019 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
1020 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
1021 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
1022 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
1023 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
1026 /* VI PF stats offset definitions */
1027 #define VI_PF_NUM_STATS 17
1028 enum fw_vi_stats_pf_index {
1029 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1030 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1031 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1032 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1033 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1034 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1035 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1036 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1037 FW_VI_PF_STAT_RX_BYTES_IX,
1038 FW_VI_PF_STAT_RX_FRAMES_IX,
1039 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1040 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1041 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1042 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1043 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1044 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1045 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1048 struct fw_vi_stats_cmd {
1050 __be32 retval_len16;
1052 struct fw_vi_stats_ctl {
1063 struct fw_vi_stats_pf {
1064 __be64 tx_bcast_bytes;
1065 __be64 tx_bcast_frames;
1066 __be64 tx_mcast_bytes;
1067 __be64 tx_mcast_frames;
1068 __be64 tx_ucast_bytes;
1069 __be64 tx_ucast_frames;
1070 __be64 tx_offload_bytes;
1071 __be64 tx_offload_frames;
1073 __be64 rx_pf_frames;
1074 __be64 rx_bcast_bytes;
1075 __be64 rx_bcast_frames;
1076 __be64 rx_mcast_bytes;
1077 __be64 rx_mcast_frames;
1078 __be64 rx_ucast_bytes;
1079 __be64 rx_ucast_frames;
1080 __be64 rx_err_frames;
1082 struct fw_vi_stats_vf {
1083 __be64 tx_bcast_bytes;
1084 __be64 tx_bcast_frames;
1085 __be64 tx_mcast_bytes;
1086 __be64 tx_mcast_frames;
1087 __be64 tx_ucast_bytes;
1088 __be64 tx_ucast_frames;
1089 __be64 tx_drop_frames;
1090 __be64 tx_offload_bytes;
1091 __be64 tx_offload_frames;
1092 __be64 rx_bcast_bytes;
1093 __be64 rx_bcast_frames;
1094 __be64 rx_mcast_bytes;
1095 __be64 rx_mcast_frames;
1096 __be64 rx_ucast_bytes;
1097 __be64 rx_ucast_frames;
1098 __be64 rx_err_frames;
1103 #define FW_VI_STATS_CMD_VIID(x) ((x) << 0)
1104 #define FW_VI_STATS_CMD_NSTATS(x) ((x) << 12)
1105 #define FW_VI_STATS_CMD_IX(x) ((x) << 0)
1107 struct fw_acl_mac_cmd {
1122 #define FW_ACL_MAC_CMD_PFN(x) ((x) << 8)
1123 #define FW_ACL_MAC_CMD_VFN(x) ((x) << 0)
1124 #define FW_ACL_MAC_CMD_EN(x) ((x) << 31)
1126 struct fw_acl_vlan_cmd {
1135 #define FW_ACL_VLAN_CMD_PFN(x) ((x) << 8)
1136 #define FW_ACL_VLAN_CMD_VFN(x) ((x) << 0)
1137 #define FW_ACL_VLAN_CMD_EN(x) ((x) << 31)
1138 #define FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << 7)
1139 #define FW_ACL_VLAN_CMD_FM(x) ((x) << 6)
1142 FW_PORT_CAP_SPEED_100M = 0x0001,
1143 FW_PORT_CAP_SPEED_1G = 0x0002,
1144 FW_PORT_CAP_SPEED_2_5G = 0x0004,
1145 FW_PORT_CAP_SPEED_10G = 0x0008,
1146 FW_PORT_CAP_SPEED_40G = 0x0010,
1147 FW_PORT_CAP_SPEED_100G = 0x0020,
1148 FW_PORT_CAP_FC_RX = 0x0040,
1149 FW_PORT_CAP_FC_TX = 0x0080,
1150 FW_PORT_CAP_ANEG = 0x0100,
1151 FW_PORT_CAP_MDI_0 = 0x0200,
1152 FW_PORT_CAP_MDI_1 = 0x0400,
1153 FW_PORT_CAP_BEAN = 0x0800,
1154 FW_PORT_CAP_PMA_LPBK = 0x1000,
1155 FW_PORT_CAP_PCS_LPBK = 0x2000,
1156 FW_PORT_CAP_PHYXS_LPBK = 0x4000,
1157 FW_PORT_CAP_FAR_END_LPBK = 0x8000,
1161 FW_PORT_MDI_UNCHANGED,
1163 FW_PORT_MDI_F_STRAIGHT,
1164 FW_PORT_MDI_F_CROSSOVER
1167 #define FW_PORT_MDI(x) ((x) << 9)
1169 enum fw_port_action {
1170 FW_PORT_ACTION_L1_CFG = 0x0001,
1171 FW_PORT_ACTION_L2_CFG = 0x0002,
1172 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1173 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
1174 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
1175 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
1176 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
1177 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
1178 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
1179 FW_PORT_ACTION_L1_LPBK = 0x0021,
1180 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022,
1181 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023,
1182 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
1183 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
1184 FW_PORT_ACTION_PHY_RESET = 0x0040,
1185 FW_PORT_ACTION_PMA_RESET = 0x0041,
1186 FW_PORT_ACTION_PCS_RESET = 0x0042,
1187 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
1188 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
1189 FW_PORT_ACTION_AN_RESET = 0x0045
1192 enum fw_port_l2cfg_ctlbf {
1193 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
1194 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
1195 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
1196 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
1197 FW_PORT_L2_CTLBF_IVLAN = 0x10,
1198 FW_PORT_L2_CTLBF_TXIPG = 0x20
1201 enum fw_port_dcb_cfg {
1202 FW_PORT_DCB_CFG_PG = 0x01,
1203 FW_PORT_DCB_CFG_PFC = 0x02,
1204 FW_PORT_DCB_CFG_APPL = 0x04
1207 enum fw_port_dcb_cfg_rc {
1208 FW_PORT_DCB_CFG_SUCCESS = 0x0,
1209 FW_PORT_DCB_CFG_ERROR = 0x1
1212 enum fw_port_dcb_type {
1213 FW_PORT_DCB_TYPE_PGID = 0x00,
1214 FW_PORT_DCB_TYPE_PGRATE = 0x01,
1215 FW_PORT_DCB_TYPE_PRIORATE = 0x02,
1216 FW_PORT_DCB_TYPE_PFC = 0x03,
1217 FW_PORT_DCB_TYPE_APP_ID = 0x04,
1220 struct fw_port_cmd {
1221 __be32 op_to_portid;
1222 __be32 action_to_len16;
1224 struct fw_port_l1cfg {
1228 struct fw_port_l2cfg {
1229 __be16 ctlbf_to_ivlan0;
1241 struct fw_port_info {
1242 __be32 lstatus_to_modtype;
1251 struct fw_port_ppp {
1252 __be32 pppen_to_ncsich;
1255 struct fw_port_dcb {
1262 __be32 pgid0_to_pgid7;
1269 #define FW_PORT_CMD_READ (1U << 22)
1271 #define FW_PORT_CMD_PORTID(x) ((x) << 0)
1272 #define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf)
1274 #define FW_PORT_CMD_ACTION(x) ((x) << 16)
1275 #define FW_PORT_CMD_ACTION_GET(x) (((x) >> 16) & 0xffff)
1277 #define FW_PORT_CMD_CTLBF(x) ((x) << 10)
1278 #define FW_PORT_CMD_OVLAN3(x) ((x) << 7)
1279 #define FW_PORT_CMD_OVLAN2(x) ((x) << 6)
1280 #define FW_PORT_CMD_OVLAN1(x) ((x) << 5)
1281 #define FW_PORT_CMD_OVLAN0(x) ((x) << 4)
1282 #define FW_PORT_CMD_IVLAN0(x) ((x) << 3)
1284 #define FW_PORT_CMD_TXIPG(x) ((x) << 19)
1286 #define FW_PORT_CMD_LSTATUS (1U << 31)
1287 #define FW_PORT_CMD_LSTATUS_GET(x) (((x) >> 31) & 0x1)
1288 #define FW_PORT_CMD_LSPEED(x) ((x) << 24)
1289 #define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f)
1290 #define FW_PORT_CMD_TXPAUSE (1U << 23)
1291 #define FW_PORT_CMD_RXPAUSE (1U << 22)
1292 #define FW_PORT_CMD_MDIOCAP (1U << 21)
1293 #define FW_PORT_CMD_MDIOADDR_GET(x) (((x) >> 16) & 0x1f)
1294 #define FW_PORT_CMD_LPTXPAUSE (1U << 15)
1295 #define FW_PORT_CMD_LPRXPAUSE (1U << 14)
1296 #define FW_PORT_CMD_PTYPE_MASK 0x1f
1297 #define FW_PORT_CMD_PTYPE_GET(x) (((x) >> 8) & FW_PORT_CMD_PTYPE_MASK)
1298 #define FW_PORT_CMD_MODTYPE_MASK 0x1f
1299 #define FW_PORT_CMD_MODTYPE_GET(x) (((x) >> 0) & FW_PORT_CMD_MODTYPE_MASK)
1301 #define FW_PORT_CMD_PPPEN(x) ((x) << 31)
1302 #define FW_PORT_CMD_TPSRC(x) ((x) << 28)
1303 #define FW_PORT_CMD_NCSISRC(x) ((x) << 24)
1305 #define FW_PORT_CMD_CH0(x) ((x) << 20)
1306 #define FW_PORT_CMD_CH1(x) ((x) << 16)
1307 #define FW_PORT_CMD_CH2(x) ((x) << 12)
1308 #define FW_PORT_CMD_CH3(x) ((x) << 8)
1309 #define FW_PORT_CMD_NCSICH(x) ((x) << 4)
1312 FW_PORT_TYPE_FIBER_XFI,
1313 FW_PORT_TYPE_FIBER_XAUI,
1314 FW_PORT_TYPE_BT_SGMII,
1315 FW_PORT_TYPE_BT_XFI,
1316 FW_PORT_TYPE_BT_XAUI,
1323 FW_PORT_TYPE_BP4_AP,
1325 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_MASK
1328 enum fw_port_module_type {
1329 FW_PORT_MOD_TYPE_NA,
1330 FW_PORT_MOD_TYPE_LR,
1331 FW_PORT_MOD_TYPE_SR,
1332 FW_PORT_MOD_TYPE_ER,
1333 FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
1334 FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
1335 FW_PORT_MOD_TYPE_LRM,
1336 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_MASK - 3,
1337 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_MASK - 2,
1338 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_MASK - 1,
1340 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK
1344 #define FW_NUM_PORT_STATS 50
1345 #define FW_NUM_PORT_TX_STATS 23
1346 #define FW_NUM_PORT_RX_STATS 27
1348 enum fw_port_stats_tx_index {
1349 FW_STAT_TX_PORT_BYTES_IX,
1350 FW_STAT_TX_PORT_FRAMES_IX,
1351 FW_STAT_TX_PORT_BCAST_IX,
1352 FW_STAT_TX_PORT_MCAST_IX,
1353 FW_STAT_TX_PORT_UCAST_IX,
1354 FW_STAT_TX_PORT_ERROR_IX,
1355 FW_STAT_TX_PORT_64B_IX,
1356 FW_STAT_TX_PORT_65B_127B_IX,
1357 FW_STAT_TX_PORT_128B_255B_IX,
1358 FW_STAT_TX_PORT_256B_511B_IX,
1359 FW_STAT_TX_PORT_512B_1023B_IX,
1360 FW_STAT_TX_PORT_1024B_1518B_IX,
1361 FW_STAT_TX_PORT_1519B_MAX_IX,
1362 FW_STAT_TX_PORT_DROP_IX,
1363 FW_STAT_TX_PORT_PAUSE_IX,
1364 FW_STAT_TX_PORT_PPP0_IX,
1365 FW_STAT_TX_PORT_PPP1_IX,
1366 FW_STAT_TX_PORT_PPP2_IX,
1367 FW_STAT_TX_PORT_PPP3_IX,
1368 FW_STAT_TX_PORT_PPP4_IX,
1369 FW_STAT_TX_PORT_PPP5_IX,
1370 FW_STAT_TX_PORT_PPP6_IX,
1371 FW_STAT_TX_PORT_PPP7_IX
1374 enum fw_port_stat_rx_index {
1375 FW_STAT_RX_PORT_BYTES_IX,
1376 FW_STAT_RX_PORT_FRAMES_IX,
1377 FW_STAT_RX_PORT_BCAST_IX,
1378 FW_STAT_RX_PORT_MCAST_IX,
1379 FW_STAT_RX_PORT_UCAST_IX,
1380 FW_STAT_RX_PORT_MTU_ERROR_IX,
1381 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1382 FW_STAT_RX_PORT_CRC_ERROR_IX,
1383 FW_STAT_RX_PORT_LEN_ERROR_IX,
1384 FW_STAT_RX_PORT_SYM_ERROR_IX,
1385 FW_STAT_RX_PORT_64B_IX,
1386 FW_STAT_RX_PORT_65B_127B_IX,
1387 FW_STAT_RX_PORT_128B_255B_IX,
1388 FW_STAT_RX_PORT_256B_511B_IX,
1389 FW_STAT_RX_PORT_512B_1023B_IX,
1390 FW_STAT_RX_PORT_1024B_1518B_IX,
1391 FW_STAT_RX_PORT_1519B_MAX_IX,
1392 FW_STAT_RX_PORT_PAUSE_IX,
1393 FW_STAT_RX_PORT_PPP0_IX,
1394 FW_STAT_RX_PORT_PPP1_IX,
1395 FW_STAT_RX_PORT_PPP2_IX,
1396 FW_STAT_RX_PORT_PPP3_IX,
1397 FW_STAT_RX_PORT_PPP4_IX,
1398 FW_STAT_RX_PORT_PPP5_IX,
1399 FW_STAT_RX_PORT_PPP6_IX,
1400 FW_STAT_RX_PORT_PPP7_IX,
1401 FW_STAT_RX_PORT_LESS_64B_IX
1404 struct fw_port_stats_cmd {
1405 __be32 op_to_portid;
1406 __be32 retval_len16;
1407 union fw_port_stats {
1408 struct fw_port_stats_ctl {
1420 struct fw_port_stats_all {
1429 __be64 tx_128b_255b;
1430 __be64 tx_256b_511b;
1431 __be64 tx_512b_1023b;
1432 __be64 tx_1024b_1518b;
1433 __be64 tx_1519b_max;
1449 __be64 rx_mtu_error;
1450 __be64 rx_mtu_crc_error;
1451 __be64 rx_crc_error;
1452 __be64 rx_len_error;
1453 __be64 rx_sym_error;
1456 __be64 rx_128b_255b;
1457 __be64 rx_256b_511b;
1458 __be64 rx_512b_1023b;
1459 __be64 rx_1024b_1518b;
1460 __be64 rx_1519b_max;
1477 #define FW_PORT_STATS_CMD_NSTATS(x) ((x) << 4)
1478 #define FW_PORT_STATS_CMD_BG_BM(x) ((x) << 0)
1479 #define FW_PORT_STATS_CMD_TX(x) ((x) << 7)
1480 #define FW_PORT_STATS_CMD_IX(x) ((x) << 0)
1482 /* port loopback stats */
1483 #define FW_NUM_LB_STATS 16
1484 enum fw_port_lb_stats_index {
1485 FW_STAT_LB_PORT_BYTES_IX,
1486 FW_STAT_LB_PORT_FRAMES_IX,
1487 FW_STAT_LB_PORT_BCAST_IX,
1488 FW_STAT_LB_PORT_MCAST_IX,
1489 FW_STAT_LB_PORT_UCAST_IX,
1490 FW_STAT_LB_PORT_ERROR_IX,
1491 FW_STAT_LB_PORT_64B_IX,
1492 FW_STAT_LB_PORT_65B_127B_IX,
1493 FW_STAT_LB_PORT_128B_255B_IX,
1494 FW_STAT_LB_PORT_256B_511B_IX,
1495 FW_STAT_LB_PORT_512B_1023B_IX,
1496 FW_STAT_LB_PORT_1024B_1518B_IX,
1497 FW_STAT_LB_PORT_1519B_MAX_IX,
1498 FW_STAT_LB_PORT_DROP_FRAMES_IX
1501 struct fw_port_lb_stats_cmd {
1502 __be32 op_to_lbport;
1503 __be32 retval_len16;
1504 union fw_port_lb_stats {
1505 struct fw_port_lb_stats_ctl {
1517 struct fw_port_lb_stats_all {
1526 __be64 tx_128b_255b;
1527 __be64 tx_256b_511b;
1528 __be64 tx_512b_1023b;
1529 __be64 tx_1024b_1518b;
1530 __be64 tx_1519b_max;
1537 #define FW_PORT_LB_STATS_CMD_LBPORT(x) ((x) << 0)
1538 #define FW_PORT_LB_STATS_CMD_NSTATS(x) ((x) << 4)
1539 #define FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << 0)
1540 #define FW_PORT_LB_STATS_CMD_IX(x) ((x) << 0)
1542 struct fw_rss_ind_tbl_cmd {
1544 #define FW_RSS_IND_TBL_CMD_VIID(x) ((x) << 0)
1545 __be32 retval_len16;
1550 #define FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << 20)
1551 #define FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << 10)
1552 #define FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << 0)
1556 __be32 iq12_to_iq14;
1557 __be32 iq15_to_iq17;
1558 __be32 iq18_to_iq20;
1559 __be32 iq21_to_iq23;
1560 __be32 iq24_to_iq26;
1561 __be32 iq27_to_iq29;
1566 struct fw_rss_glb_config_cmd {
1568 __be32 retval_len16;
1569 union fw_rss_glb_config {
1570 struct fw_rss_glb_config_manual {
1576 struct fw_rss_glb_config_basicvirtual {
1578 __be32 synmapen_to_hashtoeplitz;
1579 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN (1U << 8)
1580 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 (1U << 7)
1581 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 (1U << 6)
1582 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 (1U << 5)
1583 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 (1U << 4)
1584 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN (1U << 3)
1585 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN (1U << 2)
1586 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP (1U << 1)
1587 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ (1U << 0)
1594 #define FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << 28)
1595 #define FW_RSS_GLB_CONFIG_CMD_MODE_GET(x) (((x) >> 28) & 0xf)
1597 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
1598 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
1600 struct fw_rss_vi_config_cmd {
1602 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
1603 __be32 retval_len16;
1604 union fw_rss_vi_config {
1605 struct fw_rss_vi_config_manual {
1610 struct fw_rss_vi_config_basicvirtual {
1612 __be32 defaultq_to_udpen;
1613 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) ((x) << 16)
1614 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_GET(x) (((x) >> 16) & 0x3ff)
1615 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4)
1616 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN (1U << 3)
1617 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2)
1618 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN (1U << 1)
1619 #define FW_RSS_VI_CONFIG_CMD_UDPEN (1U << 0)
1626 enum fw_error_type {
1627 FW_ERROR_TYPE_EXCEPTION = 0x0,
1628 FW_ERROR_TYPE_HWMODULE = 0x1,
1629 FW_ERROR_TYPE_WR = 0x2,
1630 FW_ERROR_TYPE_ACL = 0x3,
1633 struct fw_error_cmd {
1637 struct fw_error_exception {
1640 struct fw_error_hwmodule {
1644 struct fw_error_wr {
1650 struct fw_error_acl {
1661 struct fw_debug_cmd {
1663 #define FW_DEBUG_CMD_TYPE_GET(x) ((x) & 0xff)
1666 struct fw_debug_assert {
1672 u8 filename_8_15[8];
1675 struct fw_debug_prt {
1678 __be32 dprtstrparam0;
1679 __be32 dprtstrparam1;
1680 __be32 dprtstrparam2;
1681 __be32 dprtstrparam3;
1686 #define FW_PCIE_FW_ERR (1U << 31)
1687 #define FW_PCIE_FW_INIT (1U << 30)
1688 #define FW_PCIE_FW_HALT (1U << 29)
1689 #define FW_PCIE_FW_MASTER_VLD (1U << 15)
1690 #define FW_PCIE_FW_MASTER_MASK 0x7
1691 #define FW_PCIE_FW_MASTER_SHIFT 12
1692 #define FW_PCIE_FW_MASTER(x) ((x) << FW_PCIE_FW_MASTER_SHIFT)
1693 #define FW_PCIE_FW_MASTER_GET(x) (((x) >> FW_PCIE_FW_MASTER_SHIFT) & \
1694 FW_PCIE_FW_MASTER_MASK)
1699 __be16 len512; /* bin length in units of 512-bytes */
1700 __be32 fw_ver; /* firmware version */
1701 __be32 tp_microcode_ver;
1706 u8 intfver_iscsipdu;
1714 __be32 reserved6[23];
1717 #define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff)
1718 #define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff)
1719 #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff)
1720 #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff)
1723 FW_HDR_FLAGS_RESET_HALT = 0x00000001,
1726 #endif /* _T4FW_INTERFACE_H_ */