drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2013 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static struct be_cmd_priv_map cmd_priv_map[] = {
  23         {
  24                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  25                 CMD_SUBSYSTEM_ETH,
  26                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  27                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  28         },
  29         {
  30                 OPCODE_COMMON_GET_FLOW_CONTROL,
  31                 CMD_SUBSYSTEM_COMMON,
  32                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  33                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  34         },
  35         {
  36                 OPCODE_COMMON_SET_FLOW_CONTROL,
  37                 CMD_SUBSYSTEM_COMMON,
  38                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  39                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  40         },
  41         {
  42                 OPCODE_ETH_GET_PPORT_STATS,
  43                 CMD_SUBSYSTEM_ETH,
  44                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  45                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  46         },
  47         {
  48                 OPCODE_COMMON_GET_PHY_DETAILS,
  49                 CMD_SUBSYSTEM_COMMON,
  50                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  51                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  52         }
  53 };
  54
  55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode,
  56                            u8 subsystem)
  57 {
  58         int i;
  59         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
  60         u32 cmd_privileges = adapter->cmd_privileges;
  61
  62         for (i = 0; i < num_entries; i++)
  63                 if (opcode == cmd_priv_map[i].opcode &&
  64                     subsystem == cmd_priv_map[i].subsystem)
  65                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
  66                                 return false;
  67
  68         return true;
  69 }
  70
  71 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  72 {
  73         return wrb->payload.embedded_payload;
  74 }
  75
  76 static void be_mcc_notify(struct be_adapter *adapter)
  77 {
  78         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  79         u32 val = 0;
  80
  81         if (be_error(adapter))
  82                 return;
  83
  84         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  85         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  86
  87         wmb();
  88         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  89 }
  90
  91 /* To check if valid bit is set, check the entire word as we don't know
  92  * the endianness of the data (old entry is host endian while a new entry is
  93  * little endian) */
  94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  95 {
  96         u32 flags;
  97
  98         if (compl->flags != 0) {
  99                 flags = le32_to_cpu(compl->flags);
 100                 if (flags & CQE_FLAGS_VALID_MASK) {
 101                         compl->flags = flags;
 102                         return true;
 103                 }
 104         }
 105         return false;
 106 }
 107
 108 /* Need to reset the entire word that houses the valid bit */
 109 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 110 {
 111         compl->flags = 0;
 112 }
 113
 114 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 115 {
 116         unsigned long addr;
 117
 118         addr = tag1;
 119         addr = ((addr << 16) << 16) | tag0;
 120         return (void *)addr;
 121 }
 122
 123 static int be_mcc_compl_process(struct be_adapter *adapter,
 124                                 struct be_mcc_compl *compl)
 125 {
 126         u16 compl_status, extd_status;
 127         struct be_cmd_resp_hdr *resp_hdr;
 128         u8 opcode = 0, subsystem = 0;
 129
 130         /* Just swap the status to host endian; mcc tag is opaquely copied
 131          * from mcc_wrb */
 132         be_dws_le_to_cpu(compl, 4);
 133
 134         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
 135                                 CQE_STATUS_COMPL_MASK;
 136
 137         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 138
 139         if (resp_hdr) {
 140                 opcode = resp_hdr->opcode;
 141                 subsystem = resp_hdr->subsystem;
 142         }
 143
 144         if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
 145              (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
 146             (subsystem == CMD_SUBSYSTEM_COMMON)) {
 147                 adapter->flash_status = compl_status;
 148                 complete(&adapter->flash_compl);
 149         }
 150
 151         if (compl_status == MCC_STATUS_SUCCESS) {
 152                 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
 153                      (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
 154                     (subsystem == CMD_SUBSYSTEM_ETH)) {
 155                         be_parse_stats(adapter);
 156                         adapter->stats_cmd_sent = false;
 157                 }
 158                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 159                     subsystem == CMD_SUBSYSTEM_COMMON) {
 160                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 161                                 (void *)resp_hdr;
 162                         adapter->drv_stats.be_on_die_temperature =
 163                                 resp->on_die_temperature;
 164                 }
 165         } else {
 166                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
 167                         adapter->be_get_temp_freq = 0;
 168
 169                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 170                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 171                         goto done;
 172
 173                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 174                         dev_warn(&adapter->pdev->dev,
 175                                  "VF is not privileged to issue opcode %d-%d\n",
 176                                  opcode, subsystem);
 177                 } else {
 178                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 179                                         CQE_STATUS_EXTD_MASK;
 180                         dev_err(&adapter->pdev->dev,
 181                                 "opcode %d-%d failed:status %d-%d\n",
 182                                 opcode, subsystem, compl_status, extd_status);
 183                 }
 184         }
 185 done:
 186         return compl_status;
 187 }
 188
 189 /* Link state evt is a string of bytes; no need for endian swapping */
 190 static void be_async_link_state_process(struct be_adapter *adapter,
 191                 struct be_async_event_link_state *evt)
 192 {
 193         /* When link status changes, link speed must be re-queried from FW */
 194         adapter->phy.link_speed = -1;
 195
 196         /* Ignore physical link event */
 197         if (lancer_chip(adapter) &&
 198             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 199                 return;
 200
 201         /* For the initial link status do not rely on the ASYNC event as
 202          * it may not be received in some cases.
 203          */
 204         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 205                 be_link_status_update(adapter, evt->port_link_status);
 206 }
 207
 208 /* Grp5 CoS Priority evt */
 209 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 210                 struct be_async_event_grp5_cos_priority *evt)
 211 {
 212         if (evt->valid) {
 213                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 214                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 215                 adapter->recommended_prio =
 216                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 217         }
 218 }
 219
 220 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 221 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 222                 struct be_async_event_grp5_qos_link_speed *evt)
 223 {
 224         if (adapter->phy.link_speed >= 0 &&
 225             evt->physical_port == adapter->port_num)
 226                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 227 }
 228
 229 /*Grp5 PVID evt*/
 230 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 231                 struct be_async_event_grp5_pvid_state *evt)
 232 {
 233         if (evt->enabled)
 234                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 235         else
 236                 adapter->pvid = 0;
 237 }
 238
 239 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 240                 u32 trailer, struct be_mcc_compl *evt)
 241 {
 242         u8 event_type = 0;
 243
 244         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 245                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 246
 247         switch (event_type) {
 248         case ASYNC_EVENT_COS_PRIORITY:
 249                 be_async_grp5_cos_priority_process(adapter,
 250                 (struct be_async_event_grp5_cos_priority *)evt);
 251         break;
 252         case ASYNC_EVENT_QOS_SPEED:
 253                 be_async_grp5_qos_speed_process(adapter,
 254                 (struct be_async_event_grp5_qos_link_speed *)evt);
 255         break;
 256         case ASYNC_EVENT_PVID_STATE:
 257                 be_async_grp5_pvid_state_process(adapter,
 258                 (struct be_async_event_grp5_pvid_state *)evt);
 259         break;
 260         default:
 261                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event 0x%x!\n",
 262                          event_type);
 263                 break;
 264         }
 265 }
 266
 267 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 268                 u32 trailer, struct be_mcc_compl *cmp)
 269 {
 270         u8 event_type = 0;
 271         struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp;
 272
 273         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 274                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 275
 276         switch (event_type) {
 277         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 278                 if (evt->valid)
 279                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 280                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 281         break;
 282         default:
 283                 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
 284                          event_type);
 285         break;
 286         }
 287 }
 288
 289 static inline bool is_link_state_evt(u32 trailer)
 290 {
 291         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 292                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 293                                 ASYNC_EVENT_CODE_LINK_STATE;
 294 }
 295
 296 static inline bool is_grp5_evt(u32 trailer)
 297 {
 298         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 299                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 300                                 ASYNC_EVENT_CODE_GRP_5);
 301 }
 302
 303 static inline bool is_dbg_evt(u32 trailer)
 304 {
 305         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 306                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 307                                 ASYNC_EVENT_CODE_QNQ);
 308 }
 309
 310 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 311 {
 312         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 313         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 314
 315         if (be_mcc_compl_is_new(compl)) {
 316                 queue_tail_inc(mcc_cq);
 317                 return compl;
 318         }
 319         return NULL;
 320 }
 321
 322 void be_async_mcc_enable(struct be_adapter *adapter)
 323 {
 324         spin_lock_bh(&adapter->mcc_cq_lock);
 325
 326         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 327         adapter->mcc_obj.rearm_cq = true;
 328
 329         spin_unlock_bh(&adapter->mcc_cq_lock);
 330 }
 331
 332 void be_async_mcc_disable(struct be_adapter *adapter)
 333 {
 334         spin_lock_bh(&adapter->mcc_cq_lock);
 335
 336         adapter->mcc_obj.rearm_cq = false;
 337         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 338
 339         spin_unlock_bh(&adapter->mcc_cq_lock);
 340 }
 341
 342 int be_process_mcc(struct be_adapter *adapter)
 343 {
 344         struct be_mcc_compl *compl;
 345         int num = 0, status = 0;
 346         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 347
 348         spin_lock(&adapter->mcc_cq_lock);
 349         while ((compl = be_mcc_compl_get(adapter))) {
 350                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 351                         /* Interpret flags as an async trailer */
 352                         if (is_link_state_evt(compl->flags))
 353                                 be_async_link_state_process(adapter,
 354                                 (struct be_async_event_link_state *) compl);
 355                         else if (is_grp5_evt(compl->flags))
 356                                 be_async_grp5_evt_process(adapter,
 357                                 compl->flags, compl);
 358                         else if (is_dbg_evt(compl->flags))
 359                                 be_async_dbg_evt_process(adapter,
 360                                 compl->flags, compl);
 361                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 362                                 status = be_mcc_compl_process(adapter, compl);
 363                                 atomic_dec(&mcc_obj->q.used);
 364                 }
 365                 be_mcc_compl_use(compl);
 366                 num++;
 367         }
 368
 369         if (num)
 370                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 371
 372         spin_unlock(&adapter->mcc_cq_lock);
 373         return status;
 374 }
 375
 376 /* Wait till no more pending mcc requests are present */
 377 static int be_mcc_wait_compl(struct be_adapter *adapter)
 378 {
 379 #define mcc_timeout             120000 /* 12s timeout */
 380         int i, status = 0;
 381         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 382
 383         for (i = 0; i < mcc_timeout; i++) {
 384                 if (be_error(adapter))
 385                         return -EIO;
 386
 387                 local_bh_disable();
 388                 status = be_process_mcc(adapter);
 389                 local_bh_enable();
 390
 391                 if (atomic_read(&mcc_obj->q.used) == 0)
 392                         break;
 393                 udelay(100);
 394         }
 395         if (i == mcc_timeout) {
 396                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 397                 adapter->fw_timeout = true;
 398                 return -EIO;
 399         }
 400         return status;
 401 }
 402
 403 /* Notify MCC requests and wait for completion */
 404 static int be_mcc_notify_wait(struct be_adapter *adapter)
 405 {
 406         int status;
 407         struct be_mcc_wrb *wrb;
 408         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 409         u16 index = mcc_obj->q.head;
 410         struct be_cmd_resp_hdr *resp;
 411
 412         index_dec(&index, mcc_obj->q.len);
 413         wrb = queue_index_node(&mcc_obj->q, index);
 414
 415         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 416
 417         be_mcc_notify(adapter);
 418
 419         status = be_mcc_wait_compl(adapter);
 420         if (status == -EIO)
 421                 goto out;
 422
 423         status = resp->status;
 424 out:
 425         return status;
 426 }
 427
 428 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 429 {
 430         int msecs = 0;
 431         u32 ready;
 432
 433         do {
 434                 if (be_error(adapter))
 435                         return -EIO;
 436
 437                 ready = ioread32(db);
 438                 if (ready == 0xffffffff)
 439                         return -1;
 440
 441                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 442                 if (ready)
 443                         break;
 444
 445                 if (msecs > 4000) {
 446                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 447                         adapter->fw_timeout = true;
 448                         be_detect_error(adapter);
 449                         return -1;
 450                 }
 451
 452                 msleep(1);
 453                 msecs++;
 454         } while (true);
 455
 456         return 0;
 457 }
 458
 459 /*
 460  * Insert the mailbox address into the doorbell in two steps
 461  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 462  */
 463 static int be_mbox_notify_wait(struct be_adapter *adapter)
 464 {
 465         int status;
 466         u32 val = 0;
 467         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 468         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 469         struct be_mcc_mailbox *mbox = mbox_mem->va;
 470         struct be_mcc_compl *compl = &mbox->compl;
 471
 472         /* wait for ready to be set */
 473         status = be_mbox_db_ready_wait(adapter, db);
 474         if (status != 0)
 475                 return status;
 476
 477         val |= MPU_MAILBOX_DB_HI_MASK;
 478         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 479         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 480         iowrite32(val, db);
 481
 482         /* wait for ready to be set */
 483         status = be_mbox_db_ready_wait(adapter, db);
 484         if (status != 0)
 485                 return status;
 486
 487         val = 0;
 488         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 489         val |= (u32)(mbox_mem->dma >> 4) << 2;
 490         iowrite32(val, db);
 491
 492         status = be_mbox_db_ready_wait(adapter, db);
 493         if (status != 0)
 494                 return status;
 495
 496         /* A cq entry has been made now */
 497         if (be_mcc_compl_is_new(compl)) {
 498                 status = be_mcc_compl_process(adapter, &mbox->compl);
 499                 be_mcc_compl_use(compl);
 500                 if (status)
 501                         return status;
 502         } else {
 503                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 504                 return -1;
 505         }
 506         return 0;
 507 }
 508
 509 static u16 be_POST_stage_get(struct be_adapter *adapter)
 510 {
 511         u32 sem;
 512
 513         if (BEx_chip(adapter))
 514                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 515         else
 516                 pci_read_config_dword(adapter->pdev,
 517                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 518
 519         return sem & POST_STAGE_MASK;
 520 }
 521
 522 int lancer_wait_ready(struct be_adapter *adapter)
 523 {
 524 #define SLIPORT_READY_TIMEOUT 30
 525         u32 sliport_status;
 526         int status = 0, i;
 527
 528         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 529                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 530                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 531                         break;
 532
 533                 msleep(1000);
 534         }
 535
 536         if (i == SLIPORT_READY_TIMEOUT)
 537                 status = -1;
 538
 539         return status;
 540 }
 541
 542 static bool lancer_provisioning_error(struct be_adapter *adapter)
 543 {
 544         u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
 545         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 546         if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
 547                 sliport_err1 = ioread32(adapter->db +
 548                                         SLIPORT_ERROR1_OFFSET);
 549                 sliport_err2 = ioread32(adapter->db +
 550                                         SLIPORT_ERROR2_OFFSET);
 551
 552                 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
 553                     sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
 554                         return true;
 555         }
 556         return false;
 557 }
 558
 559 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 560 {
 561         int status;
 562         u32 sliport_status, err, reset_needed;
 563         bool resource_error;
 564
 565         resource_error = lancer_provisioning_error(adapter);
 566         if (resource_error)
 567                 return -EAGAIN;
 568
 569         status = lancer_wait_ready(adapter);
 570         if (!status) {
 571                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 572                 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
 573                 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
 574                 if (err && reset_needed) {
 575                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
 576                                   adapter->db + SLIPORT_CONTROL_OFFSET);
 577
 578                         /* check adapter has corrected the error */
 579                         status = lancer_wait_ready(adapter);
 580                         sliport_status = ioread32(adapter->db +
 581                                                   SLIPORT_STATUS_OFFSET);
 582                         sliport_status &= (SLIPORT_STATUS_ERR_MASK |
 583                                                 SLIPORT_STATUS_RN_MASK);
 584                         if (status || sliport_status)
 585                                 status = -1;
 586                 } else if (err || reset_needed) {
 587                         status = -1;
 588                 }
 589         }
 590         /* Stop error recovery if error is not recoverable.
 591          * No resource error is temporary errors and will go away
 592          * when PF provisions resources.
 593          */
 594         resource_error = lancer_provisioning_error(adapter);
 595         if (resource_error)
 596                 status = -EAGAIN;
 597
 598         return status;
 599 }
 600
 601 int be_fw_wait_ready(struct be_adapter *adapter)
 602 {
 603         u16 stage;
 604         int status, timeout = 0;
 605         struct device *dev = &adapter->pdev->dev;
 606
 607         if (lancer_chip(adapter)) {
 608                 status = lancer_wait_ready(adapter);
 609                 return status;
 610         }
 611
 612         do {
 613                 stage = be_POST_stage_get(adapter);
 614                 if (stage == POST_STAGE_ARMFW_RDY)
 615                         return 0;
 616
 617                 dev_info(dev, "Waiting for POST, %ds elapsed\n",
 618                          timeout);
 619                 if (msleep_interruptible(2000)) {
 620                         dev_err(dev, "Waiting for POST aborted\n");
 621                         return -EINTR;
 622                 }
 623                 timeout += 2;
 624         } while (timeout < 60);
 625
 626         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 627         return -1;
 628 }
 629
 630
 631 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 632 {
 633         return &wrb->payload.sgl[0];
 634 }
 635
 636
 637 /* Don't touch the hdr after it's prepared */
 638 /* mem will be NULL for embedded commands */
 639 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 640                                 u8 subsystem, u8 opcode, int cmd_len,
 641                                 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
 642 {
 643         struct be_sge *sge;
 644         unsigned long addr = (unsigned long)req_hdr;
 645         u64 req_addr = addr;
 646
 647         req_hdr->opcode = opcode;
 648         req_hdr->subsystem = subsystem;
 649         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 650         req_hdr->version = 0;
 651
 652         wrb->tag0 = req_addr & 0xFFFFFFFF;
 653         wrb->tag1 = upper_32_bits(req_addr);
 654
 655         wrb->payload_length = cmd_len;
 656         if (mem) {
 657                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 658                         MCC_WRB_SGE_CNT_SHIFT;
 659                 sge = nonembedded_sgl(wrb);
 660                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 661                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 662                 sge->len = cpu_to_le32(mem->size);
 663         } else
 664                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 665         be_dws_cpu_to_le(wrb, 8);
 666 }
 667
 668 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 669                         struct be_dma_mem *mem)
 670 {
 671         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 672         u64 dma = (u64)mem->dma;
 673
 674         for (i = 0; i < buf_pages; i++) {
 675                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 676                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 677                 dma += PAGE_SIZE_4K;
 678         }
 679 }
 680
 681 /* Converts interrupt delay in microseconds to multiplier value */
 682 static u32 eq_delay_to_mult(u32 usec_delay)
 683 {
 684 #define MAX_INTR_RATE                   651042
 685         const u32 round = 10;
 686         u32 multiplier;
 687
 688         if (usec_delay == 0)
 689                 multiplier = 0;
 690         else {
 691                 u32 interrupt_rate = 1000000 / usec_delay;
 692                 /* Max delay, corresponding to the lowest interrupt rate */
 693                 if (interrupt_rate == 0)
 694                         multiplier = 1023;
 695                 else {
 696                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 697                         multiplier /= interrupt_rate;
 698                         /* Round the multiplier to the closest value.*/
 699                         multiplier = (multiplier + round/2) / round;
 700                         multiplier = min(multiplier, (u32)1023);
 701                 }
 702         }
 703         return multiplier;
 704 }
 705
 706 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 707 {
 708         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 709         struct be_mcc_wrb *wrb
 710                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 711         memset(wrb, 0, sizeof(*wrb));
 712         return wrb;
 713 }
 714
 715 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 716 {
 717         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 718         struct be_mcc_wrb *wrb;
 719
 720         if (!mccq->created)
 721                 return NULL;
 722
 723         if (atomic_read(&mccq->used) >= mccq->len)
 724                 return NULL;
 725
 726         wrb = queue_head_node(mccq);
 727         queue_head_inc(mccq);
 728         atomic_inc(&mccq->used);
 729         memset(wrb, 0, sizeof(*wrb));
 730         return wrb;
 731 }
 732
 733 /* Tell fw we're about to start firing cmds by writing a
 734  * special pattern across the wrb hdr; uses mbox
 735  */
 736 int be_cmd_fw_init(struct be_adapter *adapter)
 737 {
 738         u8 *wrb;
 739         int status;
 740
 741         if (lancer_chip(adapter))
 742                 return 0;
 743
 744         if (mutex_lock_interruptible(&adapter->mbox_lock))
 745                 return -1;
 746
 747         wrb = (u8 *)wrb_from_mbox(adapter);
 748         *wrb++ = 0xFF;
 749         *wrb++ = 0x12;
 750         *wrb++ = 0x34;
 751         *wrb++ = 0xFF;
 752         *wrb++ = 0xFF;
 753         *wrb++ = 0x56;
 754         *wrb++ = 0x78;
 755         *wrb = 0xFF;
 756
 757         status = be_mbox_notify_wait(adapter);
 758
 759         mutex_unlock(&adapter->mbox_lock);
 760         return status;
 761 }
 762
 763 /* Tell fw we're done with firing cmds by writing a
 764  * special pattern across the wrb hdr; uses mbox
 765  */
 766 int be_cmd_fw_clean(struct be_adapter *adapter)
 767 {
 768         u8 *wrb;
 769         int status;
 770
 771         if (lancer_chip(adapter))
 772                 return 0;
 773
 774         if (mutex_lock_interruptible(&adapter->mbox_lock))
 775                 return -1;
 776
 777         wrb = (u8 *)wrb_from_mbox(adapter);
 778         *wrb++ = 0xFF;
 779         *wrb++ = 0xAA;
 780         *wrb++ = 0xBB;
 781         *wrb++ = 0xFF;
 782         *wrb++ = 0xFF;
 783         *wrb++ = 0xCC;
 784         *wrb++ = 0xDD;
 785         *wrb = 0xFF;
 786
 787         status = be_mbox_notify_wait(adapter);
 788
 789         mutex_unlock(&adapter->mbox_lock);
 790         return status;
 791 }
 792
 793 int be_cmd_eq_create(struct be_adapter *adapter,
 794                 struct be_queue_info *eq, int eq_delay)
 795 {
 796         struct be_mcc_wrb *wrb;
 797         struct be_cmd_req_eq_create *req;
 798         struct be_dma_mem *q_mem = &eq->dma_mem;
 799         int status;
 800
 801         if (mutex_lock_interruptible(&adapter->mbox_lock))
 802                 return -1;
 803
 804         wrb = wrb_from_mbox(adapter);
 805         req = embedded_payload(wrb);
 806
 807         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 808                 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
 809
 810         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 811
 812         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 813         /* 4byte eqe*/
 814         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 815         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 816                         __ilog2_u32(eq->len/256));
 817         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 818                         eq_delay_to_mult(eq_delay));
 819         be_dws_cpu_to_le(req->context, sizeof(req->context));
 820
 821         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 822
 823         status = be_mbox_notify_wait(adapter);
 824         if (!status) {
 825                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 826                 eq->id = le16_to_cpu(resp->eq_id);
 827                 eq->created = true;
 828         }
 829
 830         mutex_unlock(&adapter->mbox_lock);
 831         return status;
 832 }
 833
 834 /* Use MCC */
 835 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 836                           bool permanent, u32 if_handle, u32 pmac_id)
 837 {
 838         struct be_mcc_wrb *wrb;
 839         struct be_cmd_req_mac_query *req;
 840         int status;
 841
 842         spin_lock_bh(&adapter->mcc_lock);
 843
 844         wrb = wrb_from_mccq(adapter);
 845         if (!wrb) {
 846                 status = -EBUSY;
 847                 goto err;
 848         }
 849         req = embedded_payload(wrb);
 850
 851         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 852                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
 853         req->type = MAC_ADDRESS_TYPE_NETWORK;
 854         if (permanent) {
 855                 req->permanent = 1;
 856         } else {
 857                 req->if_id = cpu_to_le16((u16) if_handle);
 858                 req->pmac_id = cpu_to_le32(pmac_id);
 859                 req->permanent = 0;
 860         }
 861
 862         status = be_mcc_notify_wait(adapter);
 863         if (!status) {
 864                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 865                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 866         }
 867
 868 err:
 869         spin_unlock_bh(&adapter->mcc_lock);
 870         return status;
 871 }
 872
 873 /* Uses synchronous MCCQ */
 874 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 875                 u32 if_id, u32 *pmac_id, u32 domain)
 876 {
 877         struct be_mcc_wrb *wrb;
 878         struct be_cmd_req_pmac_add *req;
 879         int status;
 880
 881         spin_lock_bh(&adapter->mcc_lock);
 882
 883         wrb = wrb_from_mccq(adapter);
 884         if (!wrb) {
 885                 status = -EBUSY;
 886                 goto err;
 887         }
 888         req = embedded_payload(wrb);
 889
 890         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 891                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
 892
 893         req->hdr.domain = domain;
 894         req->if_id = cpu_to_le32(if_id);
 895         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 896
 897         status = be_mcc_notify_wait(adapter);
 898         if (!status) {
 899                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 900                 *pmac_id = le32_to_cpu(resp->pmac_id);
 901         }
 902
 903 err:
 904         spin_unlock_bh(&adapter->mcc_lock);
 905
 906          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
 907                 status = -EPERM;
 908
 909         return status;
 910 }
 911
 912 /* Uses synchronous MCCQ */
 913 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
 914 {
 915         struct be_mcc_wrb *wrb;
 916         struct be_cmd_req_pmac_del *req;
 917         int status;
 918
 919         if (pmac_id == -1)
 920                 return 0;
 921
 922         spin_lock_bh(&adapter->mcc_lock);
 923
 924         wrb = wrb_from_mccq(adapter);
 925         if (!wrb) {
 926                 status = -EBUSY;
 927                 goto err;
 928         }
 929         req = embedded_payload(wrb);
 930
 931         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 932                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
 933
 934         req->hdr.domain = dom;
 935         req->if_id = cpu_to_le32(if_id);
 936         req->pmac_id = cpu_to_le32(pmac_id);
 937
 938         status = be_mcc_notify_wait(adapter);
 939
 940 err:
 941         spin_unlock_bh(&adapter->mcc_lock);
 942         return status;
 943 }
 944
 945 /* Uses Mbox */
 946 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
 947                 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
 948 {
 949         struct be_mcc_wrb *wrb;
 950         struct be_cmd_req_cq_create *req;
 951         struct be_dma_mem *q_mem = &cq->dma_mem;
 952         void *ctxt;
 953         int status;
 954
 955         if (mutex_lock_interruptible(&adapter->mbox_lock))
 956                 return -1;
 957
 958         wrb = wrb_from_mbox(adapter);
 959         req = embedded_payload(wrb);
 960         ctxt = &req->context;
 961
 962         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 963                 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
 964
 965         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 966
 967         if (BEx_chip(adapter)) {
 968                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 969                                                                 coalesce_wm);
 970                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 971                                                                 ctxt, no_delay);
 972                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 973                                                 __ilog2_u32(cq->len/256));
 974                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 975                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 976                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 977         } else {
 978                 req->hdr.version = 2;
 979                 req->page_size = 1; /* 1 for 4K */
 980                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
 981                                                                 no_delay);
 982                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
 983                                                 __ilog2_u32(cq->len/256));
 984                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
 985                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable,
 986                                                                 ctxt, 1);
 987                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid,
 988                                                                 ctxt, eq->id);
 989         }
 990
 991         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 992
 993         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 994
 995         status = be_mbox_notify_wait(adapter);
 996         if (!status) {
 997                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 998                 cq->id = le16_to_cpu(resp->cq_id);
 999                 cq->created = true;
1000         }
1001
1002         mutex_unlock(&adapter->mbox_lock);
1003
1004         return status;
1005 }
1006
1007 static u32 be_encoded_q_len(int q_len)
1008 {
1009         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1010         if (len_encoded == 16)
1011                 len_encoded = 0;
1012         return len_encoded;
1013 }
1014
1015 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1016                                 struct be_queue_info *mccq,
1017                                 struct be_queue_info *cq)
1018 {
1019         struct be_mcc_wrb *wrb;
1020         struct be_cmd_req_mcc_ext_create *req;
1021         struct be_dma_mem *q_mem = &mccq->dma_mem;
1022         void *ctxt;
1023         int status;
1024
1025         if (mutex_lock_interruptible(&adapter->mbox_lock))
1026                 return -1;
1027
1028         wrb = wrb_from_mbox(adapter);
1029         req = embedded_payload(wrb);
1030         ctxt = &req->context;
1031
1032         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1033                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
1034
1035         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1036         if (lancer_chip(adapter)) {
1037                 req->hdr.version = 1;
1038                 req->cq_id = cpu_to_le16(cq->id);
1039
1040                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
1041                                                 be_encoded_q_len(mccq->len));
1042                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
1043                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
1044                                                                 ctxt, cq->id);
1045                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
1046                                                                  ctxt, 1);
1047
1048         } else {
1049                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1050                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1051                                                 be_encoded_q_len(mccq->len));
1052                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1053         }
1054
1055         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1056         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
1057         req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
1058         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1059
1060         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1061
1062         status = be_mbox_notify_wait(adapter);
1063         if (!status) {
1064                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1065                 mccq->id = le16_to_cpu(resp->id);
1066                 mccq->created = true;
1067         }
1068         mutex_unlock(&adapter->mbox_lock);
1069
1070         return status;
1071 }
1072
1073 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1074                                 struct be_queue_info *mccq,
1075                                 struct be_queue_info *cq)
1076 {
1077         struct be_mcc_wrb *wrb;
1078         struct be_cmd_req_mcc_create *req;
1079         struct be_dma_mem *q_mem = &mccq->dma_mem;
1080         void *ctxt;
1081         int status;
1082
1083         if (mutex_lock_interruptible(&adapter->mbox_lock))
1084                 return -1;
1085
1086         wrb = wrb_from_mbox(adapter);
1087         req = embedded_payload(wrb);
1088         ctxt = &req->context;
1089
1090         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1091                         OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
1092
1093         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1094
1095         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1096         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1097                         be_encoded_q_len(mccq->len));
1098         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1099
1100         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1101
1102         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1103
1104         status = be_mbox_notify_wait(adapter);
1105         if (!status) {
1106                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1107                 mccq->id = le16_to_cpu(resp->id);
1108                 mccq->created = true;
1109         }
1110
1111         mutex_unlock(&adapter->mbox_lock);
1112         return status;
1113 }
1114
1115 int be_cmd_mccq_create(struct be_adapter *adapter,
1116                         struct be_queue_info *mccq,
1117                         struct be_queue_info *cq)
1118 {
1119         int status;
1120
1121         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1122         if (status && !lancer_chip(adapter)) {
1123                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1124                         "or newer to avoid conflicting priorities between NIC "
1125                         "and FCoE traffic");
1126                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1127         }
1128         return status;
1129 }
1130
1131 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1132 {
1133         struct be_mcc_wrb *wrb;
1134         struct be_cmd_req_eth_tx_create *req;
1135         struct be_queue_info *txq = &txo->q;
1136         struct be_queue_info *cq = &txo->cq;
1137         struct be_dma_mem *q_mem = &txq->dma_mem;
1138         int status, ver = 0;
1139
1140         spin_lock_bh(&adapter->mcc_lock);
1141
1142         wrb = wrb_from_mccq(adapter);
1143         if (!wrb) {
1144                 status = -EBUSY;
1145                 goto err;
1146         }
1147
1148         req = embedded_payload(wrb);
1149
1150         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1151                 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
1152
1153         if (lancer_chip(adapter)) {
1154                 req->hdr.version = 1;
1155                 req->if_id = cpu_to_le16(adapter->if_handle);
1156         } else if (BEx_chip(adapter)) {
1157                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1158                         req->hdr.version = 2;
1159         } else { /* For SH */
1160                 req->hdr.version = 2;
1161         }
1162
1163         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1164         req->ulp_num = BE_ULP1_NUM;
1165         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1166         req->cq_id = cpu_to_le16(cq->id);
1167         req->queue_size = be_encoded_q_len(txq->len);
1168         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1169
1170         ver = req->hdr.version;
1171
1172         status = be_mcc_notify_wait(adapter);
1173         if (!status) {
1174                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
1175                 txq->id = le16_to_cpu(resp->cid);
1176                 if (ver == 2)
1177                         txo->db_offset = le32_to_cpu(resp->db_offset);
1178                 else
1179                         txo->db_offset = DB_TXULP1_OFFSET;
1180                 txq->created = true;
1181         }
1182
1183 err:
1184         spin_unlock_bh(&adapter->mcc_lock);
1185
1186         return status;
1187 }
1188
1189 /* Uses MCC */
1190 int be_cmd_rxq_create(struct be_adapter *adapter,
1191                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1192                 u32 if_id, u32 rss, u8 *rss_id)
1193 {
1194         struct be_mcc_wrb *wrb;
1195         struct be_cmd_req_eth_rx_create *req;
1196         struct be_dma_mem *q_mem = &rxq->dma_mem;
1197         int status;
1198
1199         spin_lock_bh(&adapter->mcc_lock);
1200
1201         wrb = wrb_from_mccq(adapter);
1202         if (!wrb) {
1203                 status = -EBUSY;
1204                 goto err;
1205         }
1206         req = embedded_payload(wrb);
1207
1208         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1209                                 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1210
1211         req->cq_id = cpu_to_le16(cq_id);
1212         req->frag_size = fls(frag_size) - 1;
1213         req->num_pages = 2;
1214         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1215         req->interface_id = cpu_to_le32(if_id);
1216         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1217         req->rss_queue = cpu_to_le32(rss);
1218
1219         status = be_mcc_notify_wait(adapter);
1220         if (!status) {
1221                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1222                 rxq->id = le16_to_cpu(resp->id);
1223                 rxq->created = true;
1224                 *rss_id = resp->rss_id;
1225         }
1226
1227 err:
1228         spin_unlock_bh(&adapter->mcc_lock);
1229         return status;
1230 }
1231
1232 /* Generic destroyer function for all types of queues
1233  * Uses Mbox
1234  */
1235 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1236                 int queue_type)
1237 {
1238         struct be_mcc_wrb *wrb;
1239         struct be_cmd_req_q_destroy *req;
1240         u8 subsys = 0, opcode = 0;
1241         int status;
1242
1243         if (mutex_lock_interruptible(&adapter->mbox_lock))
1244                 return -1;
1245
1246         wrb = wrb_from_mbox(adapter);
1247         req = embedded_payload(wrb);
1248
1249         switch (queue_type) {
1250         case QTYPE_EQ:
1251                 subsys = CMD_SUBSYSTEM_COMMON;
1252                 opcode = OPCODE_COMMON_EQ_DESTROY;
1253                 break;
1254         case QTYPE_CQ:
1255                 subsys = CMD_SUBSYSTEM_COMMON;
1256                 opcode = OPCODE_COMMON_CQ_DESTROY;
1257                 break;
1258         case QTYPE_TXQ:
1259                 subsys = CMD_SUBSYSTEM_ETH;
1260                 opcode = OPCODE_ETH_TX_DESTROY;
1261                 break;
1262         case QTYPE_RXQ:
1263                 subsys = CMD_SUBSYSTEM_ETH;
1264                 opcode = OPCODE_ETH_RX_DESTROY;
1265                 break;
1266         case QTYPE_MCCQ:
1267                 subsys = CMD_SUBSYSTEM_COMMON;
1268                 opcode = OPCODE_COMMON_MCC_DESTROY;
1269                 break;
1270         default:
1271                 BUG();
1272         }
1273
1274         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1275                                 NULL);
1276         req->id = cpu_to_le16(q->id);
1277
1278         status = be_mbox_notify_wait(adapter);
1279         q->created = false;
1280
1281         mutex_unlock(&adapter->mbox_lock);
1282         return status;
1283 }
1284
1285 /* Uses MCC */
1286 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1287 {
1288         struct be_mcc_wrb *wrb;
1289         struct be_cmd_req_q_destroy *req;
1290         int status;
1291
1292         spin_lock_bh(&adapter->mcc_lock);
1293
1294         wrb = wrb_from_mccq(adapter);
1295         if (!wrb) {
1296                 status = -EBUSY;
1297                 goto err;
1298         }
1299         req = embedded_payload(wrb);
1300
1301         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1302                         OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1303         req->id = cpu_to_le16(q->id);
1304
1305         status = be_mcc_notify_wait(adapter);
1306         q->created = false;
1307
1308 err:
1309         spin_unlock_bh(&adapter->mcc_lock);
1310         return status;
1311 }
1312
1313 /* Create an rx filtering policy configuration on an i/f
1314  * Uses MCCQ
1315  */
1316 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1317                      u32 *if_handle, u32 domain)
1318 {
1319         struct be_mcc_wrb *wrb;
1320         struct be_cmd_req_if_create *req;
1321         int status;
1322
1323         spin_lock_bh(&adapter->mcc_lock);
1324
1325         wrb = wrb_from_mccq(adapter);
1326         if (!wrb) {
1327                 status = -EBUSY;
1328                 goto err;
1329         }
1330         req = embedded_payload(wrb);
1331
1332         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1333                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1334         req->hdr.domain = domain;
1335         req->capability_flags = cpu_to_le32(cap_flags);
1336         req->enable_flags = cpu_to_le32(en_flags);
1337
1338         req->pmac_invalid = true;
1339
1340         status = be_mcc_notify_wait(adapter);
1341         if (!status) {
1342                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1343                 *if_handle = le32_to_cpu(resp->interface_id);
1344
1345                 /* Hack to retrieve VF's pmac-id on BE3 */
1346                 if (BE3_chip(adapter) && !be_physfn(adapter))
1347                         adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1348         }
1349
1350 err:
1351         spin_unlock_bh(&adapter->mcc_lock);
1352         return status;
1353 }
1354
1355 /* Uses MCCQ */
1356 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1357 {
1358         struct be_mcc_wrb *wrb;
1359         struct be_cmd_req_if_destroy *req;
1360         int status;
1361
1362         if (interface_id == -1)
1363                 return 0;
1364
1365         spin_lock_bh(&adapter->mcc_lock);
1366
1367         wrb = wrb_from_mccq(adapter);
1368         if (!wrb) {
1369                 status = -EBUSY;
1370                 goto err;
1371         }
1372         req = embedded_payload(wrb);
1373
1374         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1375                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1376         req->hdr.domain = domain;
1377         req->interface_id = cpu_to_le32(interface_id);
1378
1379         status = be_mcc_notify_wait(adapter);
1380 err:
1381         spin_unlock_bh(&adapter->mcc_lock);
1382         return status;
1383 }
1384
1385 /* Get stats is a non embedded command: the request is not embedded inside
1386  * WRB but is a separate dma memory block
1387  * Uses asynchronous MCC
1388  */
1389 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1390 {
1391         struct be_mcc_wrb *wrb;
1392         struct be_cmd_req_hdr *hdr;
1393         int status = 0;
1394
1395         spin_lock_bh(&adapter->mcc_lock);
1396
1397         wrb = wrb_from_mccq(adapter);
1398         if (!wrb) {
1399                 status = -EBUSY;
1400                 goto err;
1401         }
1402         hdr = nonemb_cmd->va;
1403
1404         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1405                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1406
1407         /* version 1 of the cmd is not supported only by BE2 */
1408         if (!BE2_chip(adapter))
1409                 hdr->version = 1;
1410
1411         be_mcc_notify(adapter);
1412         adapter->stats_cmd_sent = true;
1413
1414 err:
1415         spin_unlock_bh(&adapter->mcc_lock);
1416         return status;
1417 }
1418
1419 /* Lancer Stats */
1420 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1421                                 struct be_dma_mem *nonemb_cmd)
1422 {
1423
1424         struct be_mcc_wrb *wrb;
1425         struct lancer_cmd_req_pport_stats *req;
1426         int status = 0;
1427
1428         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1429                             CMD_SUBSYSTEM_ETH))
1430                 return -EPERM;
1431
1432         spin_lock_bh(&adapter->mcc_lock);
1433
1434         wrb = wrb_from_mccq(adapter);
1435         if (!wrb) {
1436                 status = -EBUSY;
1437                 goto err;
1438         }
1439         req = nonemb_cmd->va;
1440
1441         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1442                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1443                         nonemb_cmd);
1444
1445         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1446         req->cmd_params.params.reset_stats = 0;
1447
1448         be_mcc_notify(adapter);
1449         adapter->stats_cmd_sent = true;
1450
1451 err:
1452         spin_unlock_bh(&adapter->mcc_lock);
1453         return status;
1454 }
1455
1456 static int be_mac_to_link_speed(int mac_speed)
1457 {
1458         switch (mac_speed) {
1459         case PHY_LINK_SPEED_ZERO:
1460                 return 0;
1461         case PHY_LINK_SPEED_10MBPS:
1462                 return 10;
1463         case PHY_LINK_SPEED_100MBPS:
1464                 return 100;
1465         case PHY_LINK_SPEED_1GBPS:
1466                 return 1000;
1467         case PHY_LINK_SPEED_10GBPS:
1468                 return 10000;
1469         case PHY_LINK_SPEED_20GBPS:
1470                 return 20000;
1471         case PHY_LINK_SPEED_25GBPS:
1472                 return 25000;
1473         case PHY_LINK_SPEED_40GBPS:
1474                 return 40000;
1475         }
1476         return 0;
1477 }
1478
1479 /* Uses synchronous mcc
1480  * Returns link_speed in Mbps
1481  */
1482 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1483                              u8 *link_status, u32 dom)
1484 {
1485         struct be_mcc_wrb *wrb;
1486         struct be_cmd_req_link_status *req;
1487         int status;
1488
1489         spin_lock_bh(&adapter->mcc_lock);
1490
1491         if (link_status)
1492                 *link_status = LINK_DOWN;
1493
1494         wrb = wrb_from_mccq(adapter);
1495         if (!wrb) {
1496                 status = -EBUSY;
1497                 goto err;
1498         }
1499         req = embedded_payload(wrb);
1500
1501         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1502                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1503
1504         /* version 1 of the cmd is not supported only by BE2 */
1505         if (!BE2_chip(adapter))
1506                 req->hdr.version = 1;
1507
1508         req->hdr.domain = dom;
1509
1510         status = be_mcc_notify_wait(adapter);
1511         if (!status) {
1512                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1513                 if (link_speed) {
1514                         *link_speed = resp->link_speed ?
1515                                       le16_to_cpu(resp->link_speed) * 10 :
1516                                       be_mac_to_link_speed(resp->mac_speed);
1517
1518                         if (!resp->logical_link_status)
1519                                 *link_speed = 0;
1520                 }
1521                 if (link_status)
1522                         *link_status = resp->logical_link_status;
1523         }
1524
1525 err:
1526         spin_unlock_bh(&adapter->mcc_lock);
1527         return status;
1528 }
1529
1530 /* Uses synchronous mcc */
1531 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1532 {
1533         struct be_mcc_wrb *wrb;
1534         struct be_cmd_req_get_cntl_addnl_attribs *req;
1535         int status = 0;
1536
1537         spin_lock_bh(&adapter->mcc_lock);
1538
1539         wrb = wrb_from_mccq(adapter);
1540         if (!wrb) {
1541                 status = -EBUSY;
1542                 goto err;
1543         }
1544         req = embedded_payload(wrb);
1545
1546         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1547                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1548                 wrb, NULL);
1549
1550         be_mcc_notify(adapter);
1551
1552 err:
1553         spin_unlock_bh(&adapter->mcc_lock);
1554         return status;
1555 }
1556
1557 /* Uses synchronous mcc */
1558 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1559 {
1560         struct be_mcc_wrb *wrb;
1561         struct be_cmd_req_get_fat *req;
1562         int status;
1563
1564         spin_lock_bh(&adapter->mcc_lock);
1565
1566         wrb = wrb_from_mccq(adapter);
1567         if (!wrb) {
1568                 status = -EBUSY;
1569                 goto err;
1570         }
1571         req = embedded_payload(wrb);
1572
1573         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1574                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1575         req->fat_operation = cpu_to_le32(QUERY_FAT);
1576         status = be_mcc_notify_wait(adapter);
1577         if (!status) {
1578                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1579                 if (log_size && resp->log_size)
1580                         *log_size = le32_to_cpu(resp->log_size) -
1581                                         sizeof(u32);
1582         }
1583 err:
1584         spin_unlock_bh(&adapter->mcc_lock);
1585         return status;
1586 }
1587
1588 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1589 {
1590         struct be_dma_mem get_fat_cmd;
1591         struct be_mcc_wrb *wrb;
1592         struct be_cmd_req_get_fat *req;
1593         u32 offset = 0, total_size, buf_size,
1594                                 log_offset = sizeof(u32), payload_len;
1595         int status;
1596
1597         if (buf_len == 0)
1598                 return;
1599
1600         total_size = buf_len;
1601
1602         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1603         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1604                         get_fat_cmd.size,
1605                         &get_fat_cmd.dma);
1606         if (!get_fat_cmd.va) {
1607                 status = -ENOMEM;
1608                 dev_err(&adapter->pdev->dev,
1609                 "Memory allocation failure while retrieving FAT data\n");
1610                 return;
1611         }
1612
1613         spin_lock_bh(&adapter->mcc_lock);
1614
1615         while (total_size) {
1616                 buf_size = min(total_size, (u32)60*1024);
1617                 total_size -= buf_size;
1618
1619                 wrb = wrb_from_mccq(adapter);
1620                 if (!wrb) {
1621                         status = -EBUSY;
1622                         goto err;
1623                 }
1624                 req = get_fat_cmd.va;
1625
1626                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1627                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1628                                 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1629                                 &get_fat_cmd);
1630
1631                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1632                 req->read_log_offset = cpu_to_le32(log_offset);
1633                 req->read_log_length = cpu_to_le32(buf_size);
1634                 req->data_buffer_size = cpu_to_le32(buf_size);
1635
1636                 status = be_mcc_notify_wait(adapter);
1637                 if (!status) {
1638                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1639                         memcpy(buf + offset,
1640                                 resp->data_buffer,
1641                                 le32_to_cpu(resp->read_log_length));
1642                 } else {
1643                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1644                         goto err;
1645                 }
1646                 offset += buf_size;
1647                 log_offset += buf_size;
1648         }
1649 err:
1650         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1651                         get_fat_cmd.va,
1652                         get_fat_cmd.dma);
1653         spin_unlock_bh(&adapter->mcc_lock);
1654 }
1655
1656 /* Uses synchronous mcc */
1657 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1658                         char *fw_on_flash)
1659 {
1660         struct be_mcc_wrb *wrb;
1661         struct be_cmd_req_get_fw_version *req;
1662         int status;
1663
1664         spin_lock_bh(&adapter->mcc_lock);
1665
1666         wrb = wrb_from_mccq(adapter);
1667         if (!wrb) {
1668                 status = -EBUSY;
1669                 goto err;
1670         }
1671
1672         req = embedded_payload(wrb);
1673
1674         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1675                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1676         status = be_mcc_notify_wait(adapter);
1677         if (!status) {
1678                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1679                 strcpy(fw_ver, resp->firmware_version_string);
1680                 if (fw_on_flash)
1681                         strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1682         }
1683 err:
1684         spin_unlock_bh(&adapter->mcc_lock);
1685         return status;
1686 }
1687
1688 /* set the EQ delay interval of an EQ to specified value
1689  * Uses async mcc
1690  */
1691 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1692 {
1693         struct be_mcc_wrb *wrb;
1694         struct be_cmd_req_modify_eq_delay *req;
1695         int status = 0;
1696
1697         spin_lock_bh(&adapter->mcc_lock);
1698
1699         wrb = wrb_from_mccq(adapter);
1700         if (!wrb) {
1701                 status = -EBUSY;
1702                 goto err;
1703         }
1704         req = embedded_payload(wrb);
1705
1706         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1707                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1708
1709         req->num_eq = cpu_to_le32(1);
1710         req->delay[0].eq_id = cpu_to_le32(eq_id);
1711         req->delay[0].phase = 0;
1712         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1713
1714         be_mcc_notify(adapter);
1715
1716 err:
1717         spin_unlock_bh(&adapter->mcc_lock);
1718         return status;
1719 }
1720
1721 /* Uses sycnhronous mcc */
1722 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1723                         u32 num, bool untagged, bool promiscuous)
1724 {
1725         struct be_mcc_wrb *wrb;
1726         struct be_cmd_req_vlan_config *req;
1727         int status;
1728
1729         spin_lock_bh(&adapter->mcc_lock);
1730
1731         wrb = wrb_from_mccq(adapter);
1732         if (!wrb) {
1733                 status = -EBUSY;
1734                 goto err;
1735         }
1736         req = embedded_payload(wrb);
1737
1738         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1739                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1740
1741         req->interface_id = if_id;
1742         req->promiscuous = promiscuous;
1743         req->untagged = untagged;
1744         req->num_vlan = num;
1745         if (!promiscuous) {
1746                 memcpy(req->normal_vlan, vtag_array,
1747                         req->num_vlan * sizeof(vtag_array[0]));
1748         }
1749
1750         status = be_mcc_notify_wait(adapter);
1751
1752 err:
1753         spin_unlock_bh(&adapter->mcc_lock);
1754         return status;
1755 }
1756
1757 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1758 {
1759         struct be_mcc_wrb *wrb;
1760         struct be_dma_mem *mem = &adapter->rx_filter;
1761         struct be_cmd_req_rx_filter *req = mem->va;
1762         int status;
1763
1764         spin_lock_bh(&adapter->mcc_lock);
1765
1766         wrb = wrb_from_mccq(adapter);
1767         if (!wrb) {
1768                 status = -EBUSY;
1769                 goto err;
1770         }
1771         memset(req, 0, sizeof(*req));
1772         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1773                                 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1774                                 wrb, mem);
1775
1776         req->if_id = cpu_to_le32(adapter->if_handle);
1777         if (flags & IFF_PROMISC) {
1778                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1779                                         BE_IF_FLAGS_VLAN_PROMISCUOUS |
1780                                         BE_IF_FLAGS_MCAST_PROMISCUOUS);
1781                 if (value == ON)
1782                         req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1783                                                 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1784                                                 BE_IF_FLAGS_MCAST_PROMISCUOUS);
1785         } else if (flags & IFF_ALLMULTI) {
1786                 req->if_flags_mask = req->if_flags =
1787                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1788         } else {
1789                 struct netdev_hw_addr *ha;
1790                 int i = 0;
1791
1792                 req->if_flags_mask = req->if_flags =
1793                                 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1794
1795                 /* Reset mcast promisc mode if already set by setting mask
1796                  * and not setting flags field
1797                  */
1798                 req->if_flags_mask |=
1799                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1800                                     adapter->if_cap_flags);
1801
1802                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1803                 netdev_for_each_mc_addr(ha, adapter->netdev)
1804                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1805         }
1806
1807         status = be_mcc_notify_wait(adapter);
1808 err:
1809         spin_unlock_bh(&adapter->mcc_lock);
1810         return status;
1811 }
1812
1813 /* Uses synchrounous mcc */
1814 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1815 {
1816         struct be_mcc_wrb *wrb;
1817         struct be_cmd_req_set_flow_control *req;
1818         int status;
1819
1820         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1821                             CMD_SUBSYSTEM_COMMON))
1822                 return -EPERM;
1823
1824         spin_lock_bh(&adapter->mcc_lock);
1825
1826         wrb = wrb_from_mccq(adapter);
1827         if (!wrb) {
1828                 status = -EBUSY;
1829                 goto err;
1830         }
1831         req = embedded_payload(wrb);
1832
1833         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1834                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1835
1836         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1837         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1838
1839         status = be_mcc_notify_wait(adapter);
1840
1841 err:
1842         spin_unlock_bh(&adapter->mcc_lock);
1843         return status;
1844 }
1845
1846 /* Uses sycn mcc */
1847 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1848 {
1849         struct be_mcc_wrb *wrb;
1850         struct be_cmd_req_get_flow_control *req;
1851         int status;
1852
1853         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1854                             CMD_SUBSYSTEM_COMMON))
1855                 return -EPERM;
1856
1857         spin_lock_bh(&adapter->mcc_lock);
1858
1859         wrb = wrb_from_mccq(adapter);
1860         if (!wrb) {
1861                 status = -EBUSY;
1862                 goto err;
1863         }
1864         req = embedded_payload(wrb);
1865
1866         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1867                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1868
1869         status = be_mcc_notify_wait(adapter);
1870         if (!status) {
1871                 struct be_cmd_resp_get_flow_control *resp =
1872                                                 embedded_payload(wrb);
1873                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1874                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1875         }
1876
1877 err:
1878         spin_unlock_bh(&adapter->mcc_lock);
1879         return status;
1880 }
1881
1882 /* Uses mbox */
1883 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1884                         u32 *mode, u32 *caps, u16 *asic_rev)
1885 {
1886         struct be_mcc_wrb *wrb;
1887         struct be_cmd_req_query_fw_cfg *req;
1888         int status;
1889
1890         if (mutex_lock_interruptible(&adapter->mbox_lock))
1891                 return -1;
1892
1893         wrb = wrb_from_mbox(adapter);
1894         req = embedded_payload(wrb);
1895
1896         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1897                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1898
1899         status = be_mbox_notify_wait(adapter);
1900         if (!status) {
1901                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1902                 *port_num = le32_to_cpu(resp->phys_port);
1903                 *mode = le32_to_cpu(resp->function_mode);
1904                 *caps = le32_to_cpu(resp->function_caps);
1905                 *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
1906         }
1907
1908         mutex_unlock(&adapter->mbox_lock);
1909         return status;
1910 }
1911
1912 /* Uses mbox */
1913 int be_cmd_reset_function(struct be_adapter *adapter)
1914 {
1915         struct be_mcc_wrb *wrb;
1916         struct be_cmd_req_hdr *req;
1917         int status;
1918
1919         if (lancer_chip(adapter)) {
1920                 status = lancer_wait_ready(adapter);
1921                 if (!status) {
1922                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
1923                                   adapter->db + SLIPORT_CONTROL_OFFSET);
1924                         status = lancer_test_and_set_rdy_state(adapter);
1925                 }
1926                 if (status) {
1927                         dev_err(&adapter->pdev->dev,
1928                                 "Adapter in non recoverable error\n");
1929                 }
1930                 return status;
1931         }
1932
1933         if (mutex_lock_interruptible(&adapter->mbox_lock))
1934                 return -1;
1935
1936         wrb = wrb_from_mbox(adapter);
1937         req = embedded_payload(wrb);
1938
1939         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1940                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1941
1942         status = be_mbox_notify_wait(adapter);
1943
1944         mutex_unlock(&adapter->mbox_lock);
1945         return status;
1946 }
1947
1948 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1949                         u32 rss_hash_opts, u16 table_size)
1950 {
1951         struct be_mcc_wrb *wrb;
1952         struct be_cmd_req_rss_config *req;
1953         u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1954                         0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1955                         0x3ea83c02, 0x4a110304};
1956         int status;
1957
1958         if (mutex_lock_interruptible(&adapter->mbox_lock))
1959                 return -1;
1960
1961         wrb = wrb_from_mbox(adapter);
1962         req = embedded_payload(wrb);
1963
1964         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1965                 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1966
1967         req->if_id = cpu_to_le32(adapter->if_handle);
1968         req->enable_rss = cpu_to_le16(rss_hash_opts);
1969         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1970
1971         if (lancer_chip(adapter) || skyhawk_chip(adapter))
1972                 req->hdr.version = 1;
1973
1974         memcpy(req->cpu_table, rsstable, table_size);
1975         memcpy(req->hash, myhash, sizeof(myhash));
1976         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1977
1978         status = be_mbox_notify_wait(adapter);
1979
1980         mutex_unlock(&adapter->mbox_lock);
1981         return status;
1982 }
1983
1984 /* Uses sync mcc */
1985 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1986                         u8 bcn, u8 sts, u8 state)
1987 {
1988         struct be_mcc_wrb *wrb;
1989         struct be_cmd_req_enable_disable_beacon *req;
1990         int status;
1991
1992         spin_lock_bh(&adapter->mcc_lock);
1993
1994         wrb = wrb_from_mccq(adapter);
1995         if (!wrb) {
1996                 status = -EBUSY;
1997                 goto err;
1998         }
1999         req = embedded_payload(wrb);
2000
2001         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2002                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
2003
2004         req->port_num = port_num;
2005         req->beacon_state = state;
2006         req->beacon_duration = bcn;
2007         req->status_duration = sts;
2008
2009         status = be_mcc_notify_wait(adapter);
2010
2011 err:
2012         spin_unlock_bh(&adapter->mcc_lock);
2013         return status;
2014 }
2015
2016 /* Uses sync mcc */
2017 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2018 {
2019         struct be_mcc_wrb *wrb;
2020         struct be_cmd_req_get_beacon_state *req;
2021         int status;
2022
2023         spin_lock_bh(&adapter->mcc_lock);
2024
2025         wrb = wrb_from_mccq(adapter);
2026         if (!wrb) {
2027                 status = -EBUSY;
2028                 goto err;
2029         }
2030         req = embedded_payload(wrb);
2031
2032         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2033                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
2034
2035         req->port_num = port_num;
2036
2037         status = be_mcc_notify_wait(adapter);
2038         if (!status) {
2039                 struct be_cmd_resp_get_beacon_state *resp =
2040                                                 embedded_payload(wrb);
2041                 *state = resp->beacon_state;
2042         }
2043
2044 err:
2045         spin_unlock_bh(&adapter->mcc_lock);
2046         return status;
2047 }
2048
2049 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2050                             u32 data_size, u32 data_offset,
2051                             const char *obj_name, u32 *data_written,
2052                             u8 *change_status, u8 *addn_status)
2053 {
2054         struct be_mcc_wrb *wrb;
2055         struct lancer_cmd_req_write_object *req;
2056         struct lancer_cmd_resp_write_object *resp;
2057         void *ctxt = NULL;
2058         int status;
2059
2060         spin_lock_bh(&adapter->mcc_lock);
2061         adapter->flash_status = 0;
2062
2063         wrb = wrb_from_mccq(adapter);
2064         if (!wrb) {
2065                 status = -EBUSY;
2066                 goto err_unlock;
2067         }
2068
2069         req = embedded_payload(wrb);
2070
2071         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2072                                 OPCODE_COMMON_WRITE_OBJECT,
2073                                 sizeof(struct lancer_cmd_req_write_object), wrb,
2074                                 NULL);
2075
2076         ctxt = &req->context;
2077         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2078                         write_length, ctxt, data_size);
2079
2080         if (data_size == 0)
2081                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2082                                 eof, ctxt, 1);
2083         else
2084                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2085                                 eof, ctxt, 0);
2086
2087         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2088         req->write_offset = cpu_to_le32(data_offset);
2089         strcpy(req->object_name, obj_name);
2090         req->descriptor_count = cpu_to_le32(1);
2091         req->buf_len = cpu_to_le32(data_size);
2092         req->addr_low = cpu_to_le32((cmd->dma +
2093                                 sizeof(struct lancer_cmd_req_write_object))
2094                                 & 0xFFFFFFFF);
2095         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2096                                 sizeof(struct lancer_cmd_req_write_object)));
2097
2098         be_mcc_notify(adapter);
2099         spin_unlock_bh(&adapter->mcc_lock);
2100
2101         if (!wait_for_completion_timeout(&adapter->flash_compl,
2102                                          msecs_to_jiffies(60000)))
2103                 status = -1;
2104         else
2105                 status = adapter->flash_status;
2106
2107         resp = embedded_payload(wrb);
2108         if (!status) {
2109                 *data_written = le32_to_cpu(resp->actual_write_len);
2110                 *change_status = resp->change_status;
2111         } else {
2112                 *addn_status = resp->additional_status;
2113         }
2114
2115         return status;
2116
2117 err_unlock:
2118         spin_unlock_bh(&adapter->mcc_lock);
2119         return status;
2120 }
2121
2122 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2123                 u32 data_size, u32 data_offset, const char *obj_name,
2124                 u32 *data_read, u32 *eof, u8 *addn_status)
2125 {
2126         struct be_mcc_wrb *wrb;
2127         struct lancer_cmd_req_read_object *req;
2128         struct lancer_cmd_resp_read_object *resp;
2129         int status;
2130
2131         spin_lock_bh(&adapter->mcc_lock);
2132
2133         wrb = wrb_from_mccq(adapter);
2134         if (!wrb) {
2135                 status = -EBUSY;
2136                 goto err_unlock;
2137         }
2138
2139         req = embedded_payload(wrb);
2140
2141         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2142                         OPCODE_COMMON_READ_OBJECT,
2143                         sizeof(struct lancer_cmd_req_read_object), wrb,
2144                         NULL);
2145
2146         req->desired_read_len = cpu_to_le32(data_size);
2147         req->read_offset = cpu_to_le32(data_offset);
2148         strcpy(req->object_name, obj_name);
2149         req->descriptor_count = cpu_to_le32(1);
2150         req->buf_len = cpu_to_le32(data_size);
2151         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2152         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2153
2154         status = be_mcc_notify_wait(adapter);
2155
2156         resp = embedded_payload(wrb);
2157         if (!status) {
2158                 *data_read = le32_to_cpu(resp->actual_read_len);
2159                 *eof = le32_to_cpu(resp->eof);
2160         } else {
2161                 *addn_status = resp->additional_status;
2162         }
2163
2164 err_unlock:
2165         spin_unlock_bh(&adapter->mcc_lock);
2166         return status;
2167 }
2168
2169 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2170                         u32 flash_type, u32 flash_opcode, u32 buf_size)
2171 {
2172         struct be_mcc_wrb *wrb;
2173         struct be_cmd_write_flashrom *req;
2174         int status;
2175
2176         spin_lock_bh(&adapter->mcc_lock);
2177         adapter->flash_status = 0;
2178
2179         wrb = wrb_from_mccq(adapter);
2180         if (!wrb) {
2181                 status = -EBUSY;
2182                 goto err_unlock;
2183         }
2184         req = cmd->va;
2185
2186         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2187                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
2188
2189         req->params.op_type = cpu_to_le32(flash_type);
2190         req->params.op_code = cpu_to_le32(flash_opcode);
2191         req->params.data_buf_size = cpu_to_le32(buf_size);
2192
2193         be_mcc_notify(adapter);
2194         spin_unlock_bh(&adapter->mcc_lock);
2195
2196         if (!wait_for_completion_timeout(&adapter->flash_compl,
2197                         msecs_to_jiffies(40000)))
2198                 status = -1;
2199         else
2200                 status = adapter->flash_status;
2201
2202         return status;
2203
2204 err_unlock:
2205         spin_unlock_bh(&adapter->mcc_lock);
2206         return status;
2207 }
2208
2209 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2210                          int offset)
2211 {
2212         struct be_mcc_wrb *wrb;
2213         struct be_cmd_read_flash_crc *req;
2214         int status;
2215
2216         spin_lock_bh(&adapter->mcc_lock);
2217
2218         wrb = wrb_from_mccq(adapter);
2219         if (!wrb) {
2220                 status = -EBUSY;
2221                 goto err;
2222         }
2223         req = embedded_payload(wrb);
2224
2225         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2226                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2227                                wrb, NULL);
2228
2229         req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2230         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2231         req->params.offset = cpu_to_le32(offset);
2232         req->params.data_buf_size = cpu_to_le32(0x4);
2233
2234         status = be_mcc_notify_wait(adapter);
2235         if (!status)
2236                 memcpy(flashed_crc, req->crc, 4);
2237
2238 err:
2239         spin_unlock_bh(&adapter->mcc_lock);
2240         return status;
2241 }
2242
2243 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2244                                 struct be_dma_mem *nonemb_cmd)
2245 {
2246         struct be_mcc_wrb *wrb;
2247         struct be_cmd_req_acpi_wol_magic_config *req;
2248         int status;
2249
2250         spin_lock_bh(&adapter->mcc_lock);
2251
2252         wrb = wrb_from_mccq(adapter);
2253         if (!wrb) {
2254                 status = -EBUSY;
2255                 goto err;
2256         }
2257         req = nonemb_cmd->va;
2258
2259         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2260                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2261                 nonemb_cmd);
2262         memcpy(req->magic_mac, mac, ETH_ALEN);
2263
2264         status = be_mcc_notify_wait(adapter);
2265
2266 err:
2267         spin_unlock_bh(&adapter->mcc_lock);
2268         return status;
2269 }
2270
2271 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2272                         u8 loopback_type, u8 enable)
2273 {
2274         struct be_mcc_wrb *wrb;
2275         struct be_cmd_req_set_lmode *req;
2276         int status;
2277
2278         spin_lock_bh(&adapter->mcc_lock);
2279
2280         wrb = wrb_from_mccq(adapter);
2281         if (!wrb) {
2282                 status = -EBUSY;
2283                 goto err;
2284         }
2285
2286         req = embedded_payload(wrb);
2287
2288         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2289                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2290                         NULL);
2291
2292         req->src_port = port_num;
2293         req->dest_port = port_num;
2294         req->loopback_type = loopback_type;
2295         req->loopback_state = enable;
2296
2297         status = be_mcc_notify_wait(adapter);
2298 err:
2299         spin_unlock_bh(&adapter->mcc_lock);
2300         return status;
2301 }
2302
2303 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2304                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2305 {
2306         struct be_mcc_wrb *wrb;
2307         struct be_cmd_req_loopback_test *req;
2308         int status;
2309
2310         spin_lock_bh(&adapter->mcc_lock);
2311
2312         wrb = wrb_from_mccq(adapter);
2313         if (!wrb) {
2314                 status = -EBUSY;
2315                 goto err;
2316         }
2317
2318         req = embedded_payload(wrb);
2319
2320         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2321                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2322         req->hdr.timeout = cpu_to_le32(4);
2323
2324         req->pattern = cpu_to_le64(pattern);
2325         req->src_port = cpu_to_le32(port_num);
2326         req->dest_port = cpu_to_le32(port_num);
2327         req->pkt_size = cpu_to_le32(pkt_size);
2328         req->num_pkts = cpu_to_le32(num_pkts);
2329         req->loopback_type = cpu_to_le32(loopback_type);
2330
2331         status = be_mcc_notify_wait(adapter);
2332         if (!status) {
2333                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2334                 status = le32_to_cpu(resp->status);
2335         }
2336
2337 err:
2338         spin_unlock_bh(&adapter->mcc_lock);
2339         return status;
2340 }
2341
2342 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2343                                 u32 byte_cnt, struct be_dma_mem *cmd)
2344 {
2345         struct be_mcc_wrb *wrb;
2346         struct be_cmd_req_ddrdma_test *req;
2347         int status;
2348         int i, j = 0;
2349
2350         spin_lock_bh(&adapter->mcc_lock);
2351
2352         wrb = wrb_from_mccq(adapter);
2353         if (!wrb) {
2354                 status = -EBUSY;
2355                 goto err;
2356         }
2357         req = cmd->va;
2358         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2359                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2360
2361         req->pattern = cpu_to_le64(pattern);
2362         req->byte_count = cpu_to_le32(byte_cnt);
2363         for (i = 0; i < byte_cnt; i++) {
2364                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2365                 j++;
2366                 if (j > 7)
2367                         j = 0;
2368         }
2369
2370         status = be_mcc_notify_wait(adapter);
2371
2372         if (!status) {
2373                 struct be_cmd_resp_ddrdma_test *resp;
2374                 resp = cmd->va;
2375                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2376                                 resp->snd_err) {
2377                         status = -1;
2378                 }
2379         }
2380
2381 err:
2382         spin_unlock_bh(&adapter->mcc_lock);
2383         return status;
2384 }
2385
2386 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2387                                 struct be_dma_mem *nonemb_cmd)
2388 {
2389         struct be_mcc_wrb *wrb;
2390         struct be_cmd_req_seeprom_read *req;
2391         int status;
2392
2393         spin_lock_bh(&adapter->mcc_lock);
2394
2395         wrb = wrb_from_mccq(adapter);
2396         if (!wrb) {
2397                 status = -EBUSY;
2398                 goto err;
2399         }
2400         req = nonemb_cmd->va;
2401
2402         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2403                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2404                         nonemb_cmd);
2405
2406         status = be_mcc_notify_wait(adapter);
2407
2408 err:
2409         spin_unlock_bh(&adapter->mcc_lock);
2410         return status;
2411 }
2412
2413 int be_cmd_get_phy_info(struct be_adapter *adapter)
2414 {
2415         struct be_mcc_wrb *wrb;
2416         struct be_cmd_req_get_phy_info *req;
2417         struct be_dma_mem cmd;
2418         int status;
2419
2420         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2421                             CMD_SUBSYSTEM_COMMON))
2422                 return -EPERM;
2423
2424         spin_lock_bh(&adapter->mcc_lock);
2425
2426         wrb = wrb_from_mccq(adapter);
2427         if (!wrb) {
2428                 status = -EBUSY;
2429                 goto err;
2430         }
2431         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2432         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2433                                         &cmd.dma);
2434         if (!cmd.va) {
2435                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2436                 status = -ENOMEM;
2437                 goto err;
2438         }
2439
2440         req = cmd.va;
2441
2442         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2443                         OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2444                         wrb, &cmd);
2445
2446         status = be_mcc_notify_wait(adapter);
2447         if (!status) {
2448                 struct be_phy_info *resp_phy_info =
2449                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2450                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2451                 adapter->phy.interface_type =
2452                         le16_to_cpu(resp_phy_info->interface_type);
2453                 adapter->phy.auto_speeds_supported =
2454                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
2455                 adapter->phy.fixed_speeds_supported =
2456                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2457                 adapter->phy.misc_params =
2458                         le32_to_cpu(resp_phy_info->misc_params);
2459
2460                 if (BE2_chip(adapter)) {
2461                         adapter->phy.fixed_speeds_supported =
2462                                 BE_SUPPORTED_SPEED_10GBPS |
2463                                 BE_SUPPORTED_SPEED_1GBPS;
2464                 }
2465         }
2466         pci_free_consistent(adapter->pdev, cmd.size,
2467                                 cmd.va, cmd.dma);
2468 err:
2469         spin_unlock_bh(&adapter->mcc_lock);
2470         return status;
2471 }
2472
2473 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2474 {
2475         struct be_mcc_wrb *wrb;
2476         struct be_cmd_req_set_qos *req;
2477         int status;
2478
2479         spin_lock_bh(&adapter->mcc_lock);
2480
2481         wrb = wrb_from_mccq(adapter);
2482         if (!wrb) {
2483                 status = -EBUSY;
2484                 goto err;
2485         }
2486
2487         req = embedded_payload(wrb);
2488
2489         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2490                         OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2491
2492         req->hdr.domain = domain;
2493         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2494         req->max_bps_nic = cpu_to_le32(bps);
2495
2496         status = be_mcc_notify_wait(adapter);
2497
2498 err:
2499         spin_unlock_bh(&adapter->mcc_lock);
2500         return status;
2501 }
2502
2503 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2504 {
2505         struct be_mcc_wrb *wrb;
2506         struct be_cmd_req_cntl_attribs *req;
2507         struct be_cmd_resp_cntl_attribs *resp;
2508         int status;
2509         int payload_len = max(sizeof(*req), sizeof(*resp));
2510         struct mgmt_controller_attrib *attribs;
2511         struct be_dma_mem attribs_cmd;
2512
2513         if (mutex_lock_interruptible(&adapter->mbox_lock))
2514                 return -1;
2515
2516         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2517         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2518         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2519                                                 &attribs_cmd.dma);
2520         if (!attribs_cmd.va) {
2521                 dev_err(&adapter->pdev->dev,
2522                                 "Memory allocation failure\n");
2523                 status = -ENOMEM;
2524                 goto err;
2525         }
2526
2527         wrb = wrb_from_mbox(adapter);
2528         if (!wrb) {
2529                 status = -EBUSY;
2530                 goto err;
2531         }
2532         req = attribs_cmd.va;
2533
2534         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2535                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2536                         &attribs_cmd);
2537
2538         status = be_mbox_notify_wait(adapter);
2539         if (!status) {
2540                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2541                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2542         }
2543
2544 err:
2545         mutex_unlock(&adapter->mbox_lock);
2546         if (attribs_cmd.va)
2547                 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2548                                     attribs_cmd.va, attribs_cmd.dma);
2549         return status;
2550 }
2551
2552 /* Uses mbox */
2553 int be_cmd_req_native_mode(struct be_adapter *adapter)
2554 {
2555         struct be_mcc_wrb *wrb;
2556         struct be_cmd_req_set_func_cap *req;
2557         int status;
2558
2559         if (mutex_lock_interruptible(&adapter->mbox_lock))
2560                 return -1;
2561
2562         wrb = wrb_from_mbox(adapter);
2563         if (!wrb) {
2564                 status = -EBUSY;
2565                 goto err;
2566         }
2567
2568         req = embedded_payload(wrb);
2569
2570         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2571                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2572
2573         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2574                                 CAPABILITY_BE3_NATIVE_ERX_API);
2575         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2576
2577         status = be_mbox_notify_wait(adapter);
2578         if (!status) {
2579                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2580                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2581                                         CAPABILITY_BE3_NATIVE_ERX_API;
2582                 if (!adapter->be3_native)
2583                         dev_warn(&adapter->pdev->dev,
2584                                  "adapter not in advanced mode\n");
2585         }
2586 err:
2587         mutex_unlock(&adapter->mbox_lock);
2588         return status;
2589 }
2590
2591 /* Get privilege(s) for a function */
2592 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2593                              u32 domain)
2594 {
2595         struct be_mcc_wrb *wrb;
2596         struct be_cmd_req_get_fn_privileges *req;
2597         int status;
2598
2599         spin_lock_bh(&adapter->mcc_lock);
2600
2601         wrb = wrb_from_mccq(adapter);
2602         if (!wrb) {
2603                 status = -EBUSY;
2604                 goto err;
2605         }
2606
2607         req = embedded_payload(wrb);
2608
2609         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2610                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2611                                wrb, NULL);
2612
2613         req->hdr.domain = domain;
2614
2615         status = be_mcc_notify_wait(adapter);
2616         if (!status) {
2617                 struct be_cmd_resp_get_fn_privileges *resp =
2618                                                 embedded_payload(wrb);
2619                 *privilege = le32_to_cpu(resp->privilege_mask);
2620         }
2621
2622 err:
2623         spin_unlock_bh(&adapter->mcc_lock);
2624         return status;
2625 }
2626
2627 /* Set privilege(s) for a function */
2628 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2629                              u32 domain)
2630 {
2631         struct be_mcc_wrb *wrb;
2632         struct be_cmd_req_set_fn_privileges *req;
2633         int status;
2634
2635         spin_lock_bh(&adapter->mcc_lock);
2636
2637         wrb = wrb_from_mccq(adapter);
2638         if (!wrb) {
2639                 status = -EBUSY;
2640                 goto err;
2641         }
2642
2643         req = embedded_payload(wrb);
2644         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2645                                OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
2646                                wrb, NULL);
2647         req->hdr.domain = domain;
2648         if (lancer_chip(adapter))
2649                 req->privileges_lancer = cpu_to_le32(privileges);
2650         else
2651                 req->privileges = cpu_to_le32(privileges);
2652
2653         status = be_mcc_notify_wait(adapter);
2654 err:
2655         spin_unlock_bh(&adapter->mcc_lock);
2656         return status;
2657 }
2658
2659 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
2660  * pmac_id_valid: false => pmac_id or MAC address is requested.
2661  *                If pmac_id is returned, pmac_id_valid is returned as true
2662  */
2663 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2664                              bool *pmac_id_valid, u32 *pmac_id, u8 domain)
2665 {
2666         struct be_mcc_wrb *wrb;
2667         struct be_cmd_req_get_mac_list *req;
2668         int status;
2669         int mac_count;
2670         struct be_dma_mem get_mac_list_cmd;
2671         int i;
2672
2673         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2674         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2675         get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2676                         get_mac_list_cmd.size,
2677                         &get_mac_list_cmd.dma);
2678
2679         if (!get_mac_list_cmd.va) {
2680                 dev_err(&adapter->pdev->dev,
2681                                 "Memory allocation failure during GET_MAC_LIST\n");
2682                 return -ENOMEM;
2683         }
2684
2685         spin_lock_bh(&adapter->mcc_lock);
2686
2687         wrb = wrb_from_mccq(adapter);
2688         if (!wrb) {
2689                 status = -EBUSY;
2690                 goto out;
2691         }
2692
2693         req = get_mac_list_cmd.va;
2694
2695         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2696                                OPCODE_COMMON_GET_MAC_LIST,
2697                                get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
2698         req->hdr.domain = domain;
2699         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2700         if (*pmac_id_valid) {
2701                 req->mac_id = cpu_to_le32(*pmac_id);
2702                 req->iface_id = cpu_to_le16(adapter->if_handle);
2703                 req->perm_override = 0;
2704         } else {
2705                 req->perm_override = 1;
2706         }
2707
2708         status = be_mcc_notify_wait(adapter);
2709         if (!status) {
2710                 struct be_cmd_resp_get_mac_list *resp =
2711                                                 get_mac_list_cmd.va;
2712
2713                 if (*pmac_id_valid) {
2714                         memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
2715                                ETH_ALEN);
2716                         goto out;
2717                 }
2718
2719                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2720                 /* Mac list returned could contain one or more active mac_ids
2721                  * or one or more true or pseudo permanant mac addresses.
2722                  * If an active mac_id is present, return first active mac_id
2723                  * found.
2724                  */
2725                 for (i = 0; i < mac_count; i++) {
2726                         struct get_list_macaddr *mac_entry;
2727                         u16 mac_addr_size;
2728                         u32 mac_id;
2729
2730                         mac_entry = &resp->macaddr_list[i];
2731                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2732                         /* mac_id is a 32 bit value and mac_addr size
2733                          * is 6 bytes
2734                          */
2735                         if (mac_addr_size == sizeof(u32)) {
2736                                 *pmac_id_valid = true;
2737                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2738                                 *pmac_id = le32_to_cpu(mac_id);
2739                                 goto out;
2740                         }
2741                 }
2742                 /* If no active mac_id found, return first mac addr */
2743                 *pmac_id_valid = false;
2744                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2745                                                                 ETH_ALEN);
2746         }
2747
2748 out:
2749         spin_unlock_bh(&adapter->mcc_lock);
2750         pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2751                         get_mac_list_cmd.va, get_mac_list_cmd.dma);
2752         return status;
2753 }
2754
2755 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id, u8 *mac)
2756 {
2757         bool active = true;
2758
2759         if (BEx_chip(adapter))
2760                 return be_cmd_mac_addr_query(adapter, mac, false,
2761                                              adapter->if_handle, curr_pmac_id);
2762         else
2763                 /* Fetch the MAC address using pmac_id */
2764                 return be_cmd_get_mac_from_list(adapter, mac, &active,
2765                                                 &curr_pmac_id, 0);
2766 }
2767
2768 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
2769 {
2770         int status;
2771         bool pmac_valid = false;
2772
2773         memset(mac, 0, ETH_ALEN);
2774
2775         if (BEx_chip(adapter)) {
2776                 if (be_physfn(adapter))
2777                         status = be_cmd_mac_addr_query(adapter, mac, true, 0,
2778                                                        0);
2779                 else
2780                         status = be_cmd_mac_addr_query(adapter, mac, false,
2781                                                        adapter->if_handle, 0);
2782         } else {
2783                 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
2784                                                   NULL, 0);
2785         }
2786
2787         return status;
2788 }
2789
2790 /* Uses synchronous MCCQ */
2791 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2792                         u8 mac_count, u32 domain)
2793 {
2794         struct be_mcc_wrb *wrb;
2795         struct be_cmd_req_set_mac_list *req;
2796         int status;
2797         struct be_dma_mem cmd;
2798
2799         memset(&cmd, 0, sizeof(struct be_dma_mem));
2800         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2801         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2802                         &cmd.dma, GFP_KERNEL);
2803         if (!cmd.va)
2804                 return -ENOMEM;
2805
2806         spin_lock_bh(&adapter->mcc_lock);
2807
2808         wrb = wrb_from_mccq(adapter);
2809         if (!wrb) {
2810                 status = -EBUSY;
2811                 goto err;
2812         }
2813
2814         req = cmd.va;
2815         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2816                                 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2817                                 wrb, &cmd);
2818
2819         req->hdr.domain = domain;
2820         req->mac_count = mac_count;
2821         if (mac_count)
2822                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2823
2824         status = be_mcc_notify_wait(adapter);
2825
2826 err:
2827         dma_free_coherent(&adapter->pdev->dev, cmd.size,
2828                                 cmd.va, cmd.dma);
2829         spin_unlock_bh(&adapter->mcc_lock);
2830         return status;
2831 }
2832
2833 /* Wrapper to delete any active MACs and provision the new mac.
2834  * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
2835  * current list are active.
2836  */
2837 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
2838 {
2839         bool active_mac = false;
2840         u8 old_mac[ETH_ALEN];
2841         u32 pmac_id;
2842         int status;
2843
2844         status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
2845                                           &pmac_id, dom);
2846         if (!status && active_mac)
2847                 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
2848
2849         return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
2850 }
2851
2852 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2853                         u32 domain, u16 intf_id)
2854 {
2855         struct be_mcc_wrb *wrb;
2856         struct be_cmd_req_set_hsw_config *req;
2857         void *ctxt;
2858         int status;
2859
2860         spin_lock_bh(&adapter->mcc_lock);
2861
2862         wrb = wrb_from_mccq(adapter);
2863         if (!wrb) {
2864                 status = -EBUSY;
2865                 goto err;
2866         }
2867
2868         req = embedded_payload(wrb);
2869         ctxt = &req->context;
2870
2871         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2872                         OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2873
2874         req->hdr.domain = domain;
2875         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2876         if (pvid) {
2877                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2878                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2879         }
2880
2881         be_dws_cpu_to_le(req->context, sizeof(req->context));
2882         status = be_mcc_notify_wait(adapter);
2883
2884 err:
2885         spin_unlock_bh(&adapter->mcc_lock);
2886         return status;
2887 }
2888
2889 /* Get Hyper switch config */
2890 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2891                         u32 domain, u16 intf_id)
2892 {
2893         struct be_mcc_wrb *wrb;
2894         struct be_cmd_req_get_hsw_config *req;
2895         void *ctxt;
2896         int status;
2897         u16 vid;
2898
2899         spin_lock_bh(&adapter->mcc_lock);
2900
2901         wrb = wrb_from_mccq(adapter);
2902         if (!wrb) {
2903                 status = -EBUSY;
2904                 goto err;
2905         }
2906
2907         req = embedded_payload(wrb);
2908         ctxt = &req->context;
2909
2910         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2911                         OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2912
2913         req->hdr.domain = domain;
2914         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2915                                                                 intf_id);
2916         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2917         be_dws_cpu_to_le(req->context, sizeof(req->context));
2918
2919         status = be_mcc_notify_wait(adapter);
2920         if (!status) {
2921                 struct be_cmd_resp_get_hsw_config *resp =
2922                                                 embedded_payload(wrb);
2923                 be_dws_le_to_cpu(&resp->context,
2924                                                 sizeof(resp->context));
2925                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2926                                                         pvid, &resp->context);
2927                 *pvid = le16_to_cpu(vid);
2928         }
2929
2930 err:
2931         spin_unlock_bh(&adapter->mcc_lock);
2932         return status;
2933 }
2934
2935 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2936 {
2937         struct be_mcc_wrb *wrb;
2938         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2939         int status;
2940         int payload_len = sizeof(*req);
2941         struct be_dma_mem cmd;
2942
2943         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2944                             CMD_SUBSYSTEM_ETH))
2945                 return -EPERM;
2946
2947         if (mutex_lock_interruptible(&adapter->mbox_lock))
2948                 return -1;
2949
2950         memset(&cmd, 0, sizeof(struct be_dma_mem));
2951         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2952         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2953                                                &cmd.dma);
2954         if (!cmd.va) {
2955                 dev_err(&adapter->pdev->dev,
2956                                 "Memory allocation failure\n");
2957                 status = -ENOMEM;
2958                 goto err;
2959         }
2960
2961         wrb = wrb_from_mbox(adapter);
2962         if (!wrb) {
2963                 status = -EBUSY;
2964                 goto err;
2965         }
2966
2967         req = cmd.va;
2968
2969         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2970                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2971                                payload_len, wrb, &cmd);
2972
2973         req->hdr.version = 1;
2974         req->query_options = BE_GET_WOL_CAP;
2975
2976         status = be_mbox_notify_wait(adapter);
2977         if (!status) {
2978                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2979                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2980
2981                 /* the command could succeed misleadingly on old f/w
2982                  * which is not aware of the V1 version. fake an error. */
2983                 if (resp->hdr.response_length < payload_len) {
2984                         status = -1;
2985                         goto err;
2986                 }
2987                 adapter->wol_cap = resp->wol_settings;
2988         }
2989 err:
2990         mutex_unlock(&adapter->mbox_lock);
2991         if (cmd.va)
2992                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2993         return status;
2994
2995 }
2996 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2997                                    struct be_dma_mem *cmd)
2998 {
2999         struct be_mcc_wrb *wrb;
3000         struct be_cmd_req_get_ext_fat_caps *req;
3001         int status;
3002
3003         if (mutex_lock_interruptible(&adapter->mbox_lock))
3004                 return -1;
3005
3006         wrb = wrb_from_mbox(adapter);
3007         if (!wrb) {
3008                 status = -EBUSY;
3009                 goto err;
3010         }
3011
3012         req = cmd->va;
3013         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3014                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3015                                cmd->size, wrb, cmd);
3016         req->parameter_type = cpu_to_le32(1);
3017
3018         status = be_mbox_notify_wait(adapter);
3019 err:
3020         mutex_unlock(&adapter->mbox_lock);
3021         return status;
3022 }
3023
3024 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3025                                    struct be_dma_mem *cmd,
3026                                    struct be_fat_conf_params *configs)
3027 {
3028         struct be_mcc_wrb *wrb;
3029         struct be_cmd_req_set_ext_fat_caps *req;
3030         int status;
3031
3032         spin_lock_bh(&adapter->mcc_lock);
3033
3034         wrb = wrb_from_mccq(adapter);
3035         if (!wrb) {
3036                 status = -EBUSY;
3037                 goto err;
3038         }
3039
3040         req = cmd->va;
3041         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3042         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3043                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3044                                cmd->size, wrb, cmd);
3045
3046         status = be_mcc_notify_wait(adapter);
3047 err:
3048         spin_unlock_bh(&adapter->mcc_lock);
3049         return status;
3050 }
3051
3052 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
3053 {
3054         struct be_mcc_wrb *wrb;
3055         struct be_cmd_req_get_port_name *req;
3056         int status;
3057
3058         if (!lancer_chip(adapter)) {
3059                 *port_name = adapter->hba_port_num + '0';
3060                 return 0;
3061         }
3062
3063         spin_lock_bh(&adapter->mcc_lock);
3064
3065         wrb = wrb_from_mccq(adapter);
3066         if (!wrb) {
3067                 status = -EBUSY;
3068                 goto err;
3069         }
3070
3071         req = embedded_payload(wrb);
3072
3073         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3074                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3075                                NULL);
3076         req->hdr.version = 1;
3077
3078         status = be_mcc_notify_wait(adapter);
3079         if (!status) {
3080                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
3081                 *port_name = resp->port_name[adapter->hba_port_num];
3082         } else {
3083                 *port_name = adapter->hba_port_num + '0';
3084         }
3085 err:
3086         spin_unlock_bh(&adapter->mcc_lock);
3087         return status;
3088 }
3089
3090 static struct be_nic_resource_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
3091                                                     u32 max_buf_size)
3092 {
3093         struct be_nic_resource_desc *desc = (struct be_nic_resource_desc *)buf;
3094         int i;
3095
3096         for (i = 0; i < desc_count; i++) {
3097                 desc->desc_len = desc->desc_len ? : RESOURCE_DESC_SIZE;
3098                 if (((void *)desc + desc->desc_len) >
3099                     (void *)(buf + max_buf_size))
3100                         return NULL;
3101
3102                 if (desc->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
3103                     desc->desc_type == NIC_RESOURCE_DESC_TYPE_V1)
3104                         return desc;
3105
3106                 desc = (void *)desc + desc->desc_len;
3107         }
3108
3109         return NULL;
3110 }
3111
3112 /* Uses Mbox */
3113 int be_cmd_get_func_config(struct be_adapter *adapter)
3114 {
3115         struct be_mcc_wrb *wrb;
3116         struct be_cmd_req_get_func_config *req;
3117         int status;
3118         struct be_dma_mem cmd;
3119
3120         if (mutex_lock_interruptible(&adapter->mbox_lock))
3121                 return -1;
3122
3123         memset(&cmd, 0, sizeof(struct be_dma_mem));
3124         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3125         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3126                                       &cmd.dma);
3127         if (!cmd.va) {
3128                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3129                 status = -ENOMEM;
3130                 goto err;
3131         }
3132
3133         wrb = wrb_from_mbox(adapter);
3134         if (!wrb) {
3135                 status = -EBUSY;
3136                 goto err;
3137         }
3138
3139         req = cmd.va;
3140
3141         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3142                                OPCODE_COMMON_GET_FUNC_CONFIG,
3143                                cmd.size, wrb, &cmd);
3144
3145         if (skyhawk_chip(adapter))
3146                 req->hdr.version = 1;
3147
3148         status = be_mbox_notify_wait(adapter);
3149         if (!status) {
3150                 struct be_cmd_resp_get_func_config *resp = cmd.va;
3151                 u32 desc_count = le32_to_cpu(resp->desc_count);
3152                 struct be_nic_resource_desc *desc;
3153
3154                 desc = be_get_nic_desc(resp->func_param, desc_count,
3155                                        sizeof(resp->func_param));
3156                 if (!desc) {
3157                         status = -EINVAL;
3158                         goto err;
3159                 }
3160
3161                 adapter->pf_number = desc->pf_num;
3162                 adapter->max_pmac_cnt = le16_to_cpu(desc->unicast_mac_count);
3163                 adapter->max_vlans = le16_to_cpu(desc->vlan_count);
3164                 adapter->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3165                 adapter->max_tx_queues = le16_to_cpu(desc->txq_count);
3166                 adapter->max_rss_queues = le16_to_cpu(desc->rssq_count);
3167                 adapter->max_rx_queues = le16_to_cpu(desc->rq_count);
3168
3169                 adapter->max_event_queues = le16_to_cpu(desc->eq_count);
3170                 adapter->if_cap_flags = le32_to_cpu(desc->cap_flags);
3171
3172                 /* Clear flags that driver is not interested in */
3173                 adapter->if_cap_flags &=  BE_IF_CAP_FLAGS_WANT;
3174         }
3175 err:
3176         mutex_unlock(&adapter->mbox_lock);
3177         if (cmd.va)
3178                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3179         return status;
3180 }
3181
3182 /* Uses mbox */
3183 static int be_cmd_get_profile_config_mbox(struct be_adapter *adapter,
3184                                         u8 domain, struct be_dma_mem *cmd)
3185 {
3186         struct be_mcc_wrb *wrb;
3187         struct be_cmd_req_get_profile_config *req;
3188         int status;
3189
3190         if (mutex_lock_interruptible(&adapter->mbox_lock))
3191                 return -1;
3192         wrb = wrb_from_mbox(adapter);
3193
3194         req = cmd->va;
3195         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3196                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3197                                cmd->size, wrb, cmd);
3198
3199         req->type = ACTIVE_PROFILE_TYPE;
3200         req->hdr.domain = domain;
3201         if (!lancer_chip(adapter))
3202                 req->hdr.version = 1;
3203
3204         status = be_mbox_notify_wait(adapter);
3205
3206         mutex_unlock(&adapter->mbox_lock);
3207         return status;
3208 }
3209
3210 /* Uses sync mcc */
3211 static int be_cmd_get_profile_config_mccq(struct be_adapter *adapter,
3212                                         u8 domain, struct be_dma_mem *cmd)
3213 {
3214         struct be_mcc_wrb *wrb;
3215         struct be_cmd_req_get_profile_config *req;
3216         int status;
3217
3218         spin_lock_bh(&adapter->mcc_lock);
3219
3220         wrb = wrb_from_mccq(adapter);
3221         if (!wrb) {
3222                 status = -EBUSY;
3223                 goto err;
3224         }
3225
3226         req = cmd->va;
3227         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3228                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3229                                cmd->size, wrb, cmd);
3230
3231         req->type = ACTIVE_PROFILE_TYPE;
3232         req->hdr.domain = domain;
3233         if (!lancer_chip(adapter))
3234                 req->hdr.version = 1;
3235
3236         status = be_mcc_notify_wait(adapter);
3237
3238 err:
3239         spin_unlock_bh(&adapter->mcc_lock);
3240         return status;
3241 }
3242
3243 /* Uses sync mcc, if MCCQ is already created otherwise mbox */
3244 int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags,
3245                               u16 *txq_count, u8 domain)
3246 {
3247         struct be_queue_info *mccq = &adapter->mcc_obj.q;
3248         struct be_dma_mem cmd;
3249         int status;
3250
3251         memset(&cmd, 0, sizeof(struct be_dma_mem));
3252         if (!lancer_chip(adapter))
3253                 cmd.size = sizeof(struct be_cmd_resp_get_profile_config_v1);
3254         else
3255                 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3256         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3257                                       &cmd.dma);
3258         if (!cmd.va) {
3259                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3260                 return -ENOMEM;
3261         }
3262
3263         if (!mccq->created)
3264                 status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd);
3265         else
3266                 status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd);
3267         if (!status) {
3268                 struct be_cmd_resp_get_profile_config *resp = cmd.va;
3269                 u32 desc_count = le32_to_cpu(resp->desc_count);
3270                 struct be_nic_resource_desc *desc;
3271
3272                 desc = be_get_nic_desc(resp->func_param, desc_count,
3273                                        sizeof(resp->func_param));
3274
3275                 if (!desc) {
3276                         status = -EINVAL;
3277                         goto err;
3278                 }
3279                 if (cap_flags)
3280                         *cap_flags = le32_to_cpu(desc->cap_flags);
3281                 if (txq_count)
3282                         *txq_count = le32_to_cpu(desc->txq_count);
3283         }
3284 err:
3285         if (cmd.va)
3286                 pci_free_consistent(adapter->pdev, cmd.size,
3287                                     cmd.va, cmd.dma);
3288         return status;
3289 }
3290
3291 /* Uses sync mcc */
3292 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
3293                               u8 domain)
3294 {
3295         struct be_mcc_wrb *wrb;
3296         struct be_cmd_req_set_profile_config *req;
3297         int status;
3298
3299         spin_lock_bh(&adapter->mcc_lock);
3300
3301         wrb = wrb_from_mccq(adapter);
3302         if (!wrb) {
3303                 status = -EBUSY;
3304                 goto err;
3305         }
3306
3307         req = embedded_payload(wrb);
3308
3309         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3310                                OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3311                                wrb, NULL);
3312
3313         req->hdr.domain = domain;
3314         req->desc_count = cpu_to_le32(1);
3315
3316         req->nic_desc.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3317         req->nic_desc.desc_len = RESOURCE_DESC_SIZE;
3318         req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV);
3319         req->nic_desc.pf_num = adapter->pf_number;
3320         req->nic_desc.vf_num = domain;
3321
3322         /* Mark fields invalid */
3323         req->nic_desc.unicast_mac_count = 0xFFFF;
3324         req->nic_desc.mcc_count = 0xFFFF;
3325         req->nic_desc.vlan_count = 0xFFFF;
3326         req->nic_desc.mcast_mac_count = 0xFFFF;
3327         req->nic_desc.txq_count = 0xFFFF;
3328         req->nic_desc.rq_count = 0xFFFF;
3329         req->nic_desc.rssq_count = 0xFFFF;
3330         req->nic_desc.lro_count = 0xFFFF;
3331         req->nic_desc.cq_count = 0xFFFF;
3332         req->nic_desc.toe_conn_count = 0xFFFF;
3333         req->nic_desc.eq_count = 0xFFFF;
3334         req->nic_desc.link_param = 0xFF;
3335         req->nic_desc.bw_min = 0xFFFFFFFF;
3336         req->nic_desc.acpi_params = 0xFF;
3337         req->nic_desc.wol_param = 0x0F;
3338
3339         /* Change BW */
3340         req->nic_desc.bw_min = cpu_to_le32(bps);
3341         req->nic_desc.bw_max = cpu_to_le32(bps);
3342         status = be_mcc_notify_wait(adapter);
3343 err:
3344         spin_unlock_bh(&adapter->mcc_lock);
3345         return status;
3346 }
3347
3348 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3349                      int vf_num)
3350 {
3351         struct be_mcc_wrb *wrb;
3352         struct be_cmd_req_get_iface_list *req;
3353         struct be_cmd_resp_get_iface_list *resp;
3354         int status;
3355
3356         spin_lock_bh(&adapter->mcc_lock);
3357
3358         wrb = wrb_from_mccq(adapter);
3359         if (!wrb) {
3360                 status = -EBUSY;
3361                 goto err;
3362         }
3363         req = embedded_payload(wrb);
3364
3365         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3366                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3367                                wrb, NULL);
3368         req->hdr.domain = vf_num + 1;
3369
3370         status = be_mcc_notify_wait(adapter);
3371         if (!status) {
3372                 resp = (struct be_cmd_resp_get_iface_list *)req;
3373                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3374         }
3375
3376 err:
3377         spin_unlock_bh(&adapter->mcc_lock);
3378         return status;
3379 }
3380
3381 static int lancer_wait_idle(struct be_adapter *adapter)
3382 {
3383 #define SLIPORT_IDLE_TIMEOUT 30
3384         u32 reg_val;
3385         int status = 0, i;
3386
3387         for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
3388                 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
3389                 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
3390                         break;
3391
3392                 ssleep(1);
3393         }
3394
3395         if (i == SLIPORT_IDLE_TIMEOUT)
3396                 status = -1;
3397
3398         return status;
3399 }
3400
3401 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
3402 {
3403         int status = 0;
3404
3405         status = lancer_wait_idle(adapter);
3406         if (status)
3407                 return status;
3408
3409         iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
3410
3411         return status;
3412 }
3413
3414 /* Routine to check whether dump image is present or not */
3415 bool dump_present(struct be_adapter *adapter)
3416 {
3417         u32 sliport_status = 0;
3418
3419         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
3420         return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
3421 }
3422
3423 int lancer_initiate_dump(struct be_adapter *adapter)
3424 {
3425         int status;
3426
3427         /* give firmware reset and diagnostic dump */
3428         status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
3429                                      PHYSDEV_CONTROL_DD_MASK);
3430         if (status < 0) {
3431                 dev_err(&adapter->pdev->dev, "Firmware reset failed\n");
3432                 return status;
3433         }
3434
3435         status = lancer_wait_idle(adapter);
3436         if (status)
3437                 return status;
3438
3439         if (!dump_present(adapter)) {
3440                 dev_err(&adapter->pdev->dev, "Dump image not present\n");
3441                 return -1;
3442         }
3443
3444         return 0;
3445 }
3446
3447 /* Uses sync mcc */
3448 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3449 {
3450         struct be_mcc_wrb *wrb;
3451         struct be_cmd_enable_disable_vf *req;
3452         int status;
3453
3454         if (!lancer_chip(adapter))
3455                 return 0;
3456
3457         spin_lock_bh(&adapter->mcc_lock);
3458
3459         wrb = wrb_from_mccq(adapter);
3460         if (!wrb) {
3461                 status = -EBUSY;
3462                 goto err;
3463         }
3464
3465         req = embedded_payload(wrb);
3466
3467         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3468                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3469                                wrb, NULL);
3470
3471         req->hdr.domain = domain;
3472         req->enable = 1;
3473         status = be_mcc_notify_wait(adapter);
3474 err:
3475         spin_unlock_bh(&adapter->mcc_lock);
3476         return status;
3477 }
3478
3479 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
3480 {
3481         struct be_mcc_wrb *wrb;
3482         struct be_cmd_req_intr_set *req;
3483         int status;
3484
3485         if (mutex_lock_interruptible(&adapter->mbox_lock))
3486                 return -1;
3487
3488         wrb = wrb_from_mbox(adapter);
3489
3490         req = embedded_payload(wrb);
3491
3492         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3493                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
3494                                wrb, NULL);
3495
3496         req->intr_enabled = intr_enable;
3497
3498         status = be_mbox_notify_wait(adapter);
3499
3500         mutex_unlock(&adapter->mbox_lock);
3501         return status;
3502 }
3503
3504 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3505                         int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3506 {
3507         struct be_adapter *adapter = netdev_priv(netdev_handle);
3508         struct be_mcc_wrb *wrb;
3509         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3510         struct be_cmd_req_hdr *req;
3511         struct be_cmd_resp_hdr *resp;
3512         int status;
3513
3514         spin_lock_bh(&adapter->mcc_lock);
3515
3516         wrb = wrb_from_mccq(adapter);
3517         if (!wrb) {
3518                 status = -EBUSY;
3519                 goto err;
3520         }
3521         req = embedded_payload(wrb);
3522         resp = embedded_payload(wrb);
3523
3524         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3525                                hdr->opcode, wrb_payload_size, wrb, NULL);
3526         memcpy(req, wrb_payload, wrb_payload_size);
3527         be_dws_cpu_to_le(req, wrb_payload_size);
3528
3529         status = be_mcc_notify_wait(adapter);
3530         if (cmd_status)
3531                 *cmd_status = (status & 0xffff);
3532         if (ext_status)
3533                 *ext_status = 0;
3534         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3535         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3536 err:
3537         spin_unlock_bh(&adapter->mcc_lock);
3538         return status;
3539 }
3540 EXPORT_SYMBOL(be_roce_mcc_cmd);