drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2013 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static struct be_cmd_priv_map cmd_priv_map[] = {
  23         {
  24                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  25                 CMD_SUBSYSTEM_ETH,
  26                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  27                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  28         },
  29         {
  30                 OPCODE_COMMON_GET_FLOW_CONTROL,
  31                 CMD_SUBSYSTEM_COMMON,
  32                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  33                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  34         },
  35         {
  36                 OPCODE_COMMON_SET_FLOW_CONTROL,
  37                 CMD_SUBSYSTEM_COMMON,
  38                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  39                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  40         },
  41         {
  42                 OPCODE_ETH_GET_PPORT_STATS,
  43                 CMD_SUBSYSTEM_ETH,
  44                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  45                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  46         },
  47         {
  48                 OPCODE_COMMON_GET_PHY_DETAILS,
  49                 CMD_SUBSYSTEM_COMMON,
  50                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  51                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  52         }
  53 };
  54
  55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode,
  56                            u8 subsystem)
  57 {
  58         int i;
  59         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
  60         u32 cmd_privileges = adapter->cmd_privileges;
  61
  62         for (i = 0; i < num_entries; i++)
  63                 if (opcode == cmd_priv_map[i].opcode &&
  64                     subsystem == cmd_priv_map[i].subsystem)
  65                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
  66                                 return false;
  67
  68         return true;
  69 }
  70
  71 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  72 {
  73         return wrb->payload.embedded_payload;
  74 }
  75
  76 static void be_mcc_notify(struct be_adapter *adapter)
  77 {
  78         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  79         u32 val = 0;
  80
  81         if (be_error(adapter))
  82                 return;
  83
  84         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  85         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  86
  87         wmb();
  88         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  89 }
  90
  91 /* To check if valid bit is set, check the entire word as we don't know
  92  * the endianness of the data (old entry is host endian while a new entry is
  93  * little endian) */
  94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  95 {
  96         u32 flags;
  97
  98         if (compl->flags != 0) {
  99                 flags = le32_to_cpu(compl->flags);
 100                 if (flags & CQE_FLAGS_VALID_MASK) {
 101                         compl->flags = flags;
 102                         return true;
 103                 }
 104         }
 105         return false;
 106 }
 107
 108 /* Need to reset the entire word that houses the valid bit */
 109 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 110 {
 111         compl->flags = 0;
 112 }
 113
 114 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 115 {
 116         unsigned long addr;
 117
 118         addr = tag1;
 119         addr = ((addr << 16) << 16) | tag0;
 120         return (void *)addr;
 121 }
 122
 123 static int be_mcc_compl_process(struct be_adapter *adapter,
 124                                 struct be_mcc_compl *compl)
 125 {
 126         u16 compl_status, extd_status;
 127         struct be_cmd_resp_hdr *resp_hdr;
 128         u8 opcode = 0, subsystem = 0;
 129
 130         /* Just swap the status to host endian; mcc tag is opaquely copied
 131          * from mcc_wrb */
 132         be_dws_le_to_cpu(compl, 4);
 133
 134         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
 135                                 CQE_STATUS_COMPL_MASK;
 136
 137         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 138
 139         if (resp_hdr) {
 140                 opcode = resp_hdr->opcode;
 141                 subsystem = resp_hdr->subsystem;
 142         }
 143
 144         if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
 145              (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
 146             (subsystem == CMD_SUBSYSTEM_COMMON)) {
 147                 adapter->flash_status = compl_status;
 148                 complete(&adapter->flash_compl);
 149         }
 150
 151         if (compl_status == MCC_STATUS_SUCCESS) {
 152                 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
 153                      (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
 154                     (subsystem == CMD_SUBSYSTEM_ETH)) {
 155                         be_parse_stats(adapter);
 156                         adapter->stats_cmd_sent = false;
 157                 }
 158                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 159                     subsystem == CMD_SUBSYSTEM_COMMON) {
 160                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 161                                 (void *)resp_hdr;
 162                         adapter->drv_stats.be_on_die_temperature =
 163                                 resp->on_die_temperature;
 164                 }
 165         } else {
 166                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
 167                         adapter->be_get_temp_freq = 0;
 168
 169                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 170                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 171                         goto done;
 172
 173                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 174                         dev_warn(&adapter->pdev->dev,
 175                                  "VF is not privileged to issue opcode %d-%d\n",
 176                                  opcode, subsystem);
 177                 } else {
 178                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 179                                         CQE_STATUS_EXTD_MASK;
 180                         dev_err(&adapter->pdev->dev,
 181                                 "opcode %d-%d failed:status %d-%d\n",
 182                                 opcode, subsystem, compl_status, extd_status);
 183                 }
 184         }
 185 done:
 186         return compl_status;
 187 }
 188
 189 /* Link state evt is a string of bytes; no need for endian swapping */
 190 static void be_async_link_state_process(struct be_adapter *adapter,
 191                 struct be_async_event_link_state *evt)
 192 {
 193         /* When link status changes, link speed must be re-queried from FW */
 194         adapter->phy.link_speed = -1;
 195
 196         /* Ignore physical link event */
 197         if (lancer_chip(adapter) &&
 198             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 199                 return;
 200
 201         /* For the initial link status do not rely on the ASYNC event as
 202          * it may not be received in some cases.
 203          */
 204         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 205                 be_link_status_update(adapter, evt->port_link_status);
 206 }
 207
 208 /* Grp5 CoS Priority evt */
 209 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 210                 struct be_async_event_grp5_cos_priority *evt)
 211 {
 212         if (evt->valid) {
 213                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 214                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 215                 adapter->recommended_prio =
 216                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 217         }
 218 }
 219
 220 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 221 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 222                 struct be_async_event_grp5_qos_link_speed *evt)
 223 {
 224         if (adapter->phy.link_speed >= 0 &&
 225             evt->physical_port == adapter->port_num)
 226                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 227 }
 228
 229 /*Grp5 PVID evt*/
 230 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 231                 struct be_async_event_grp5_pvid_state *evt)
 232 {
 233         if (evt->enabled)
 234                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 235         else
 236                 adapter->pvid = 0;
 237 }
 238
 239 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 240                 u32 trailer, struct be_mcc_compl *evt)
 241 {
 242         u8 event_type = 0;
 243
 244         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 245                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 246
 247         switch (event_type) {
 248         case ASYNC_EVENT_COS_PRIORITY:
 249                 be_async_grp5_cos_priority_process(adapter,
 250                 (struct be_async_event_grp5_cos_priority *)evt);
 251         break;
 252         case ASYNC_EVENT_QOS_SPEED:
 253                 be_async_grp5_qos_speed_process(adapter,
 254                 (struct be_async_event_grp5_qos_link_speed *)evt);
 255         break;
 256         case ASYNC_EVENT_PVID_STATE:
 257                 be_async_grp5_pvid_state_process(adapter,
 258                 (struct be_async_event_grp5_pvid_state *)evt);
 259         break;
 260         default:
 261                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
 262                 break;
 263         }
 264 }
 265
 266 static inline bool is_link_state_evt(u32 trailer)
 267 {
 268         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 269                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 270                                 ASYNC_EVENT_CODE_LINK_STATE;
 271 }
 272
 273 static inline bool is_grp5_evt(u32 trailer)
 274 {
 275         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 276                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 277                                 ASYNC_EVENT_CODE_GRP_5);
 278 }
 279
 280 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 281 {
 282         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 283         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 284
 285         if (be_mcc_compl_is_new(compl)) {
 286                 queue_tail_inc(mcc_cq);
 287                 return compl;
 288         }
 289         return NULL;
 290 }
 291
 292 void be_async_mcc_enable(struct be_adapter *adapter)
 293 {
 294         spin_lock_bh(&adapter->mcc_cq_lock);
 295
 296         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 297         adapter->mcc_obj.rearm_cq = true;
 298
 299         spin_unlock_bh(&adapter->mcc_cq_lock);
 300 }
 301
 302 void be_async_mcc_disable(struct be_adapter *adapter)
 303 {
 304         spin_lock_bh(&adapter->mcc_cq_lock);
 305
 306         adapter->mcc_obj.rearm_cq = false;
 307         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 308
 309         spin_unlock_bh(&adapter->mcc_cq_lock);
 310 }
 311
 312 int be_process_mcc(struct be_adapter *adapter)
 313 {
 314         struct be_mcc_compl *compl;
 315         int num = 0, status = 0;
 316         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 317
 318         spin_lock(&adapter->mcc_cq_lock);
 319         while ((compl = be_mcc_compl_get(adapter))) {
 320                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 321                         /* Interpret flags as an async trailer */
 322                         if (is_link_state_evt(compl->flags))
 323                                 be_async_link_state_process(adapter,
 324                                 (struct be_async_event_link_state *) compl);
 325                         else if (is_grp5_evt(compl->flags))
 326                                 be_async_grp5_evt_process(adapter,
 327                                 compl->flags, compl);
 328                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 329                                 status = be_mcc_compl_process(adapter, compl);
 330                                 atomic_dec(&mcc_obj->q.used);
 331                 }
 332                 be_mcc_compl_use(compl);
 333                 num++;
 334         }
 335
 336         if (num)
 337                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 338
 339         spin_unlock(&adapter->mcc_cq_lock);
 340         return status;
 341 }
 342
 343 /* Wait till no more pending mcc requests are present */
 344 static int be_mcc_wait_compl(struct be_adapter *adapter)
 345 {
 346 #define mcc_timeout             120000 /* 12s timeout */
 347         int i, status = 0;
 348         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 349
 350         for (i = 0; i < mcc_timeout; i++) {
 351                 if (be_error(adapter))
 352                         return -EIO;
 353
 354                 local_bh_disable();
 355                 status = be_process_mcc(adapter);
 356                 local_bh_enable();
 357
 358                 if (atomic_read(&mcc_obj->q.used) == 0)
 359                         break;
 360                 udelay(100);
 361         }
 362         if (i == mcc_timeout) {
 363                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 364                 adapter->fw_timeout = true;
 365                 return -EIO;
 366         }
 367         return status;
 368 }
 369
 370 /* Notify MCC requests and wait for completion */
 371 static int be_mcc_notify_wait(struct be_adapter *adapter)
 372 {
 373         int status;
 374         struct be_mcc_wrb *wrb;
 375         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 376         u16 index = mcc_obj->q.head;
 377         struct be_cmd_resp_hdr *resp;
 378
 379         index_dec(&index, mcc_obj->q.len);
 380         wrb = queue_index_node(&mcc_obj->q, index);
 381
 382         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 383
 384         be_mcc_notify(adapter);
 385
 386         status = be_mcc_wait_compl(adapter);
 387         if (status == -EIO)
 388                 goto out;
 389
 390         status = resp->status;
 391 out:
 392         return status;
 393 }
 394
 395 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 396 {
 397         int msecs = 0;
 398         u32 ready;
 399
 400         do {
 401                 if (be_error(adapter))
 402                         return -EIO;
 403
 404                 ready = ioread32(db);
 405                 if (ready == 0xffffffff)
 406                         return -1;
 407
 408                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 409                 if (ready)
 410                         break;
 411
 412                 if (msecs > 4000) {
 413                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 414                         adapter->fw_timeout = true;
 415                         be_detect_error(adapter);
 416                         return -1;
 417                 }
 418
 419                 msleep(1);
 420                 msecs++;
 421         } while (true);
 422
 423         return 0;
 424 }
 425
 426 /*
 427  * Insert the mailbox address into the doorbell in two steps
 428  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 429  */
 430 static int be_mbox_notify_wait(struct be_adapter *adapter)
 431 {
 432         int status;
 433         u32 val = 0;
 434         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 435         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 436         struct be_mcc_mailbox *mbox = mbox_mem->va;
 437         struct be_mcc_compl *compl = &mbox->compl;
 438
 439         /* wait for ready to be set */
 440         status = be_mbox_db_ready_wait(adapter, db);
 441         if (status != 0)
 442                 return status;
 443
 444         val |= MPU_MAILBOX_DB_HI_MASK;
 445         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 446         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 447         iowrite32(val, db);
 448
 449         /* wait for ready to be set */
 450         status = be_mbox_db_ready_wait(adapter, db);
 451         if (status != 0)
 452                 return status;
 453
 454         val = 0;
 455         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 456         val |= (u32)(mbox_mem->dma >> 4) << 2;
 457         iowrite32(val, db);
 458
 459         status = be_mbox_db_ready_wait(adapter, db);
 460         if (status != 0)
 461                 return status;
 462
 463         /* A cq entry has been made now */
 464         if (be_mcc_compl_is_new(compl)) {
 465                 status = be_mcc_compl_process(adapter, &mbox->compl);
 466                 be_mcc_compl_use(compl);
 467                 if (status)
 468                         return status;
 469         } else {
 470                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 471                 return -1;
 472         }
 473         return 0;
 474 }
 475
 476 static u16 be_POST_stage_get(struct be_adapter *adapter)
 477 {
 478         u32 sem;
 479
 480         if (BEx_chip(adapter))
 481                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 482         else
 483                 pci_read_config_dword(adapter->pdev,
 484                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 485
 486         return sem & POST_STAGE_MASK;
 487 }
 488
 489 int lancer_wait_ready(struct be_adapter *adapter)
 490 {
 491 #define SLIPORT_READY_TIMEOUT 30
 492         u32 sliport_status;
 493         int status = 0, i;
 494
 495         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 496                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 497                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 498                         break;
 499
 500                 msleep(1000);
 501         }
 502
 503         if (i == SLIPORT_READY_TIMEOUT)
 504                 status = -1;
 505
 506         return status;
 507 }
 508
 509 static bool lancer_provisioning_error(struct be_adapter *adapter)
 510 {
 511         u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
 512         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 513         if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
 514                 sliport_err1 = ioread32(adapter->db +
 515                                         SLIPORT_ERROR1_OFFSET);
 516                 sliport_err2 = ioread32(adapter->db +
 517                                         SLIPORT_ERROR2_OFFSET);
 518
 519                 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
 520                     sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
 521                         return true;
 522         }
 523         return false;
 524 }
 525
 526 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 527 {
 528         int status;
 529         u32 sliport_status, err, reset_needed;
 530         bool resource_error;
 531
 532         resource_error = lancer_provisioning_error(adapter);
 533         if (resource_error)
 534                 return -1;
 535
 536         status = lancer_wait_ready(adapter);
 537         if (!status) {
 538                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 539                 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
 540                 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
 541                 if (err && reset_needed) {
 542                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
 543                                   adapter->db + SLIPORT_CONTROL_OFFSET);
 544
 545                         /* check adapter has corrected the error */
 546                         status = lancer_wait_ready(adapter);
 547                         sliport_status = ioread32(adapter->db +
 548                                                   SLIPORT_STATUS_OFFSET);
 549                         sliport_status &= (SLIPORT_STATUS_ERR_MASK |
 550                                                 SLIPORT_STATUS_RN_MASK);
 551                         if (status || sliport_status)
 552                                 status = -1;
 553                 } else if (err || reset_needed) {
 554                         status = -1;
 555                 }
 556         }
 557         /* Stop error recovery if error is not recoverable.
 558          * No resource error is temporary errors and will go away
 559          * when PF provisions resources.
 560          */
 561         resource_error = lancer_provisioning_error(adapter);
 562         if (status == -1 && !resource_error)
 563                 adapter->eeh_error = true;
 564
 565         return status;
 566 }
 567
 568 int be_fw_wait_ready(struct be_adapter *adapter)
 569 {
 570         u16 stage;
 571         int status, timeout = 0;
 572         struct device *dev = &adapter->pdev->dev;
 573
 574         if (lancer_chip(adapter)) {
 575                 status = lancer_wait_ready(adapter);
 576                 return status;
 577         }
 578
 579         do {
 580                 stage = be_POST_stage_get(adapter);
 581                 if (stage == POST_STAGE_ARMFW_RDY)
 582                         return 0;
 583
 584                 dev_info(dev, "Waiting for POST, %ds elapsed\n",
 585                          timeout);
 586                 if (msleep_interruptible(2000)) {
 587                         dev_err(dev, "Waiting for POST aborted\n");
 588                         return -EINTR;
 589                 }
 590                 timeout += 2;
 591         } while (timeout < 60);
 592
 593         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 594         return -1;
 595 }
 596
 597
 598 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 599 {
 600         return &wrb->payload.sgl[0];
 601 }
 602
 603
 604 /* Don't touch the hdr after it's prepared */
 605 /* mem will be NULL for embedded commands */
 606 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 607                                 u8 subsystem, u8 opcode, int cmd_len,
 608                                 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
 609 {
 610         struct be_sge *sge;
 611         unsigned long addr = (unsigned long)req_hdr;
 612         u64 req_addr = addr;
 613
 614         req_hdr->opcode = opcode;
 615         req_hdr->subsystem = subsystem;
 616         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 617         req_hdr->version = 0;
 618
 619         wrb->tag0 = req_addr & 0xFFFFFFFF;
 620         wrb->tag1 = upper_32_bits(req_addr);
 621
 622         wrb->payload_length = cmd_len;
 623         if (mem) {
 624                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 625                         MCC_WRB_SGE_CNT_SHIFT;
 626                 sge = nonembedded_sgl(wrb);
 627                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 628                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 629                 sge->len = cpu_to_le32(mem->size);
 630         } else
 631                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 632         be_dws_cpu_to_le(wrb, 8);
 633 }
 634
 635 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 636                         struct be_dma_mem *mem)
 637 {
 638         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 639         u64 dma = (u64)mem->dma;
 640
 641         for (i = 0; i < buf_pages; i++) {
 642                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 643                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 644                 dma += PAGE_SIZE_4K;
 645         }
 646 }
 647
 648 /* Converts interrupt delay in microseconds to multiplier value */
 649 static u32 eq_delay_to_mult(u32 usec_delay)
 650 {
 651 #define MAX_INTR_RATE                   651042
 652         const u32 round = 10;
 653         u32 multiplier;
 654
 655         if (usec_delay == 0)
 656                 multiplier = 0;
 657         else {
 658                 u32 interrupt_rate = 1000000 / usec_delay;
 659                 /* Max delay, corresponding to the lowest interrupt rate */
 660                 if (interrupt_rate == 0)
 661                         multiplier = 1023;
 662                 else {
 663                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 664                         multiplier /= interrupt_rate;
 665                         /* Round the multiplier to the closest value.*/
 666                         multiplier = (multiplier + round/2) / round;
 667                         multiplier = min(multiplier, (u32)1023);
 668                 }
 669         }
 670         return multiplier;
 671 }
 672
 673 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 674 {
 675         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 676         struct be_mcc_wrb *wrb
 677                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 678         memset(wrb, 0, sizeof(*wrb));
 679         return wrb;
 680 }
 681
 682 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 683 {
 684         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 685         struct be_mcc_wrb *wrb;
 686
 687         if (!mccq->created)
 688                 return NULL;
 689
 690         if (atomic_read(&mccq->used) >= mccq->len)
 691                 return NULL;
 692
 693         wrb = queue_head_node(mccq);
 694         queue_head_inc(mccq);
 695         atomic_inc(&mccq->used);
 696         memset(wrb, 0, sizeof(*wrb));
 697         return wrb;
 698 }
 699
 700 /* Tell fw we're about to start firing cmds by writing a
 701  * special pattern across the wrb hdr; uses mbox
 702  */
 703 int be_cmd_fw_init(struct be_adapter *adapter)
 704 {
 705         u8 *wrb;
 706         int status;
 707
 708         if (lancer_chip(adapter))
 709                 return 0;
 710
 711         if (mutex_lock_interruptible(&adapter->mbox_lock))
 712                 return -1;
 713
 714         wrb = (u8 *)wrb_from_mbox(adapter);
 715         *wrb++ = 0xFF;
 716         *wrb++ = 0x12;
 717         *wrb++ = 0x34;
 718         *wrb++ = 0xFF;
 719         *wrb++ = 0xFF;
 720         *wrb++ = 0x56;
 721         *wrb++ = 0x78;
 722         *wrb = 0xFF;
 723
 724         status = be_mbox_notify_wait(adapter);
 725
 726         mutex_unlock(&adapter->mbox_lock);
 727         return status;
 728 }
 729
 730 /* Tell fw we're done with firing cmds by writing a
 731  * special pattern across the wrb hdr; uses mbox
 732  */
 733 int be_cmd_fw_clean(struct be_adapter *adapter)
 734 {
 735         u8 *wrb;
 736         int status;
 737
 738         if (lancer_chip(adapter))
 739                 return 0;
 740
 741         if (mutex_lock_interruptible(&adapter->mbox_lock))
 742                 return -1;
 743
 744         wrb = (u8 *)wrb_from_mbox(adapter);
 745         *wrb++ = 0xFF;
 746         *wrb++ = 0xAA;
 747         *wrb++ = 0xBB;
 748         *wrb++ = 0xFF;
 749         *wrb++ = 0xFF;
 750         *wrb++ = 0xCC;
 751         *wrb++ = 0xDD;
 752         *wrb = 0xFF;
 753
 754         status = be_mbox_notify_wait(adapter);
 755
 756         mutex_unlock(&adapter->mbox_lock);
 757         return status;
 758 }
 759
 760 int be_cmd_eq_create(struct be_adapter *adapter,
 761                 struct be_queue_info *eq, int eq_delay)
 762 {
 763         struct be_mcc_wrb *wrb;
 764         struct be_cmd_req_eq_create *req;
 765         struct be_dma_mem *q_mem = &eq->dma_mem;
 766         int status;
 767
 768         if (mutex_lock_interruptible(&adapter->mbox_lock))
 769                 return -1;
 770
 771         wrb = wrb_from_mbox(adapter);
 772         req = embedded_payload(wrb);
 773
 774         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 775                 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
 776
 777         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 778
 779         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 780         /* 4byte eqe*/
 781         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 782         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 783                         __ilog2_u32(eq->len/256));
 784         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 785                         eq_delay_to_mult(eq_delay));
 786         be_dws_cpu_to_le(req->context, sizeof(req->context));
 787
 788         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 789
 790         status = be_mbox_notify_wait(adapter);
 791         if (!status) {
 792                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 793                 eq->id = le16_to_cpu(resp->eq_id);
 794                 eq->created = true;
 795         }
 796
 797         mutex_unlock(&adapter->mbox_lock);
 798         return status;
 799 }
 800
 801 /* Use MCC */
 802 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 803                           bool permanent, u32 if_handle, u32 pmac_id)
 804 {
 805         struct be_mcc_wrb *wrb;
 806         struct be_cmd_req_mac_query *req;
 807         int status;
 808
 809         spin_lock_bh(&adapter->mcc_lock);
 810
 811         wrb = wrb_from_mccq(adapter);
 812         if (!wrb) {
 813                 status = -EBUSY;
 814                 goto err;
 815         }
 816         req = embedded_payload(wrb);
 817
 818         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 819                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
 820         req->type = MAC_ADDRESS_TYPE_NETWORK;
 821         if (permanent) {
 822                 req->permanent = 1;
 823         } else {
 824                 req->if_id = cpu_to_le16((u16) if_handle);
 825                 req->pmac_id = cpu_to_le32(pmac_id);
 826                 req->permanent = 0;
 827         }
 828
 829         status = be_mcc_notify_wait(adapter);
 830         if (!status) {
 831                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 832                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 833         }
 834
 835 err:
 836         spin_unlock_bh(&adapter->mcc_lock);
 837         return status;
 838 }
 839
 840 /* Uses synchronous MCCQ */
 841 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 842                 u32 if_id, u32 *pmac_id, u32 domain)
 843 {
 844         struct be_mcc_wrb *wrb;
 845         struct be_cmd_req_pmac_add *req;
 846         int status;
 847
 848         spin_lock_bh(&adapter->mcc_lock);
 849
 850         wrb = wrb_from_mccq(adapter);
 851         if (!wrb) {
 852                 status = -EBUSY;
 853                 goto err;
 854         }
 855         req = embedded_payload(wrb);
 856
 857         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 858                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
 859
 860         req->hdr.domain = domain;
 861         req->if_id = cpu_to_le32(if_id);
 862         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 863
 864         status = be_mcc_notify_wait(adapter);
 865         if (!status) {
 866                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 867                 *pmac_id = le32_to_cpu(resp->pmac_id);
 868         }
 869
 870 err:
 871         spin_unlock_bh(&adapter->mcc_lock);
 872
 873          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
 874                 status = -EPERM;
 875
 876         return status;
 877 }
 878
 879 /* Uses synchronous MCCQ */
 880 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
 881 {
 882         struct be_mcc_wrb *wrb;
 883         struct be_cmd_req_pmac_del *req;
 884         int status;
 885
 886         if (pmac_id == -1)
 887                 return 0;
 888
 889         spin_lock_bh(&adapter->mcc_lock);
 890
 891         wrb = wrb_from_mccq(adapter);
 892         if (!wrb) {
 893                 status = -EBUSY;
 894                 goto err;
 895         }
 896         req = embedded_payload(wrb);
 897
 898         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 899                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
 900
 901         req->hdr.domain = dom;
 902         req->if_id = cpu_to_le32(if_id);
 903         req->pmac_id = cpu_to_le32(pmac_id);
 904
 905         status = be_mcc_notify_wait(adapter);
 906
 907 err:
 908         spin_unlock_bh(&adapter->mcc_lock);
 909         return status;
 910 }
 911
 912 /* Uses Mbox */
 913 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
 914                 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
 915 {
 916         struct be_mcc_wrb *wrb;
 917         struct be_cmd_req_cq_create *req;
 918         struct be_dma_mem *q_mem = &cq->dma_mem;
 919         void *ctxt;
 920         int status;
 921
 922         if (mutex_lock_interruptible(&adapter->mbox_lock))
 923                 return -1;
 924
 925         wrb = wrb_from_mbox(adapter);
 926         req = embedded_payload(wrb);
 927         ctxt = &req->context;
 928
 929         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 930                 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
 931
 932         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 933         if (lancer_chip(adapter)) {
 934                 req->hdr.version = 2;
 935                 req->page_size = 1; /* 1 for 4K */
 936                 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
 937                                                                 no_delay);
 938                 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
 939                                                 __ilog2_u32(cq->len/256));
 940                 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
 941                 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
 942                                                                 ctxt, 1);
 943                 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
 944                                                                 ctxt, eq->id);
 945         } else {
 946                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 947                                                                 coalesce_wm);
 948                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 949                                                                 ctxt, no_delay);
 950                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 951                                                 __ilog2_u32(cq->len/256));
 952                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 953                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 954                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 955         }
 956
 957         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 958
 959         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 960
 961         status = be_mbox_notify_wait(adapter);
 962         if (!status) {
 963                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 964                 cq->id = le16_to_cpu(resp->cq_id);
 965                 cq->created = true;
 966         }
 967
 968         mutex_unlock(&adapter->mbox_lock);
 969
 970         return status;
 971 }
 972
 973 static u32 be_encoded_q_len(int q_len)
 974 {
 975         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
 976         if (len_encoded == 16)
 977                 len_encoded = 0;
 978         return len_encoded;
 979 }
 980
 981 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
 982                         struct be_queue_info *mccq,
 983                         struct be_queue_info *cq)
 984 {
 985         struct be_mcc_wrb *wrb;
 986         struct be_cmd_req_mcc_ext_create *req;
 987         struct be_dma_mem *q_mem = &mccq->dma_mem;
 988         void *ctxt;
 989         int status;
 990
 991         if (mutex_lock_interruptible(&adapter->mbox_lock))
 992                 return -1;
 993
 994         wrb = wrb_from_mbox(adapter);
 995         req = embedded_payload(wrb);
 996         ctxt = &req->context;
 997
 998         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 999                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
1000
1001         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1002         if (lancer_chip(adapter)) {
1003                 req->hdr.version = 1;
1004                 req->cq_id = cpu_to_le16(cq->id);
1005
1006                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
1007                                                 be_encoded_q_len(mccq->len));
1008                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
1009                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
1010                                                                 ctxt, cq->id);
1011                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
1012                                                                  ctxt, 1);
1013
1014         } else {
1015                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1016                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1017                                                 be_encoded_q_len(mccq->len));
1018                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1019         }
1020
1021         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1022         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
1023         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1024
1025         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1026
1027         status = be_mbox_notify_wait(adapter);
1028         if (!status) {
1029                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1030                 mccq->id = le16_to_cpu(resp->id);
1031                 mccq->created = true;
1032         }
1033         mutex_unlock(&adapter->mbox_lock);
1034
1035         return status;
1036 }
1037
1038 int be_cmd_mccq_org_create(struct be_adapter *adapter,
1039                         struct be_queue_info *mccq,
1040                         struct be_queue_info *cq)
1041 {
1042         struct be_mcc_wrb *wrb;
1043         struct be_cmd_req_mcc_create *req;
1044         struct be_dma_mem *q_mem = &mccq->dma_mem;
1045         void *ctxt;
1046         int status;
1047
1048         if (mutex_lock_interruptible(&adapter->mbox_lock))
1049                 return -1;
1050
1051         wrb = wrb_from_mbox(adapter);
1052         req = embedded_payload(wrb);
1053         ctxt = &req->context;
1054
1055         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1056                         OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
1057
1058         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1059
1060         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1061         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1062                         be_encoded_q_len(mccq->len));
1063         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1064
1065         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1066
1067         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1068
1069         status = be_mbox_notify_wait(adapter);
1070         if (!status) {
1071                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1072                 mccq->id = le16_to_cpu(resp->id);
1073                 mccq->created = true;
1074         }
1075
1076         mutex_unlock(&adapter->mbox_lock);
1077         return status;
1078 }
1079
1080 int be_cmd_mccq_create(struct be_adapter *adapter,
1081                         struct be_queue_info *mccq,
1082                         struct be_queue_info *cq)
1083 {
1084         int status;
1085
1086         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1087         if (status && !lancer_chip(adapter)) {
1088                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1089                         "or newer to avoid conflicting priorities between NIC "
1090                         "and FCoE traffic");
1091                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1092         }
1093         return status;
1094 }
1095
1096 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1097 {
1098         struct be_mcc_wrb *wrb;
1099         struct be_cmd_req_eth_tx_create *req;
1100         struct be_queue_info *txq = &txo->q;
1101         struct be_queue_info *cq = &txo->cq;
1102         struct be_dma_mem *q_mem = &txq->dma_mem;
1103         int status, ver = 0;
1104
1105         spin_lock_bh(&adapter->mcc_lock);
1106
1107         wrb = wrb_from_mccq(adapter);
1108         if (!wrb) {
1109                 status = -EBUSY;
1110                 goto err;
1111         }
1112
1113         req = embedded_payload(wrb);
1114
1115         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1116                 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
1117
1118         if (lancer_chip(adapter)) {
1119                 req->hdr.version = 1;
1120                 req->if_id = cpu_to_le16(adapter->if_handle);
1121         } else if (BEx_chip(adapter)) {
1122                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1123                         req->hdr.version = 2;
1124         } else { /* For SH */
1125                 req->hdr.version = 2;
1126         }
1127
1128         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1129         req->ulp_num = BE_ULP1_NUM;
1130         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1131         req->cq_id = cpu_to_le16(cq->id);
1132         req->queue_size = be_encoded_q_len(txq->len);
1133         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1134
1135         ver = req->hdr.version;
1136
1137         status = be_mcc_notify_wait(adapter);
1138         if (!status) {
1139                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
1140                 txq->id = le16_to_cpu(resp->cid);
1141                 if (ver == 2)
1142                         txo->db_offset = le32_to_cpu(resp->db_offset);
1143                 else
1144                         txo->db_offset = DB_TXULP1_OFFSET;
1145                 txq->created = true;
1146         }
1147
1148 err:
1149         spin_unlock_bh(&adapter->mcc_lock);
1150
1151         return status;
1152 }
1153
1154 /* Uses MCC */
1155 int be_cmd_rxq_create(struct be_adapter *adapter,
1156                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1157                 u32 if_id, u32 rss, u8 *rss_id)
1158 {
1159         struct be_mcc_wrb *wrb;
1160         struct be_cmd_req_eth_rx_create *req;
1161         struct be_dma_mem *q_mem = &rxq->dma_mem;
1162         int status;
1163
1164         spin_lock_bh(&adapter->mcc_lock);
1165
1166         wrb = wrb_from_mccq(adapter);
1167         if (!wrb) {
1168                 status = -EBUSY;
1169                 goto err;
1170         }
1171         req = embedded_payload(wrb);
1172
1173         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1174                                 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1175
1176         req->cq_id = cpu_to_le16(cq_id);
1177         req->frag_size = fls(frag_size) - 1;
1178         req->num_pages = 2;
1179         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1180         req->interface_id = cpu_to_le32(if_id);
1181         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1182         req->rss_queue = cpu_to_le32(rss);
1183
1184         status = be_mcc_notify_wait(adapter);
1185         if (!status) {
1186                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1187                 rxq->id = le16_to_cpu(resp->id);
1188                 rxq->created = true;
1189                 *rss_id = resp->rss_id;
1190         }
1191
1192 err:
1193         spin_unlock_bh(&adapter->mcc_lock);
1194         return status;
1195 }
1196
1197 /* Generic destroyer function for all types of queues
1198  * Uses Mbox
1199  */
1200 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1201                 int queue_type)
1202 {
1203         struct be_mcc_wrb *wrb;
1204         struct be_cmd_req_q_destroy *req;
1205         u8 subsys = 0, opcode = 0;
1206         int status;
1207
1208         if (mutex_lock_interruptible(&adapter->mbox_lock))
1209                 return -1;
1210
1211         wrb = wrb_from_mbox(adapter);
1212         req = embedded_payload(wrb);
1213
1214         switch (queue_type) {
1215         case QTYPE_EQ:
1216                 subsys = CMD_SUBSYSTEM_COMMON;
1217                 opcode = OPCODE_COMMON_EQ_DESTROY;
1218                 break;
1219         case QTYPE_CQ:
1220                 subsys = CMD_SUBSYSTEM_COMMON;
1221                 opcode = OPCODE_COMMON_CQ_DESTROY;
1222                 break;
1223         case QTYPE_TXQ:
1224                 subsys = CMD_SUBSYSTEM_ETH;
1225                 opcode = OPCODE_ETH_TX_DESTROY;
1226                 break;
1227         case QTYPE_RXQ:
1228                 subsys = CMD_SUBSYSTEM_ETH;
1229                 opcode = OPCODE_ETH_RX_DESTROY;
1230                 break;
1231         case QTYPE_MCCQ:
1232                 subsys = CMD_SUBSYSTEM_COMMON;
1233                 opcode = OPCODE_COMMON_MCC_DESTROY;
1234                 break;
1235         default:
1236                 BUG();
1237         }
1238
1239         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1240                                 NULL);
1241         req->id = cpu_to_le16(q->id);
1242
1243         status = be_mbox_notify_wait(adapter);
1244         q->created = false;
1245
1246         mutex_unlock(&adapter->mbox_lock);
1247         return status;
1248 }
1249
1250 /* Uses MCC */
1251 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1252 {
1253         struct be_mcc_wrb *wrb;
1254         struct be_cmd_req_q_destroy *req;
1255         int status;
1256
1257         spin_lock_bh(&adapter->mcc_lock);
1258
1259         wrb = wrb_from_mccq(adapter);
1260         if (!wrb) {
1261                 status = -EBUSY;
1262                 goto err;
1263         }
1264         req = embedded_payload(wrb);
1265
1266         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1267                         OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1268         req->id = cpu_to_le16(q->id);
1269
1270         status = be_mcc_notify_wait(adapter);
1271         q->created = false;
1272
1273 err:
1274         spin_unlock_bh(&adapter->mcc_lock);
1275         return status;
1276 }
1277
1278 /* Create an rx filtering policy configuration on an i/f
1279  * Uses MCCQ
1280  */
1281 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1282                      u32 *if_handle, u32 domain)
1283 {
1284         struct be_mcc_wrb *wrb;
1285         struct be_cmd_req_if_create *req;
1286         int status;
1287
1288         spin_lock_bh(&adapter->mcc_lock);
1289
1290         wrb = wrb_from_mccq(adapter);
1291         if (!wrb) {
1292                 status = -EBUSY;
1293                 goto err;
1294         }
1295         req = embedded_payload(wrb);
1296
1297         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1298                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1299         req->hdr.domain = domain;
1300         req->capability_flags = cpu_to_le32(cap_flags);
1301         req->enable_flags = cpu_to_le32(en_flags);
1302
1303         req->pmac_invalid = true;
1304
1305         status = be_mcc_notify_wait(adapter);
1306         if (!status) {
1307                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1308                 *if_handle = le32_to_cpu(resp->interface_id);
1309         }
1310
1311 err:
1312         spin_unlock_bh(&adapter->mcc_lock);
1313         return status;
1314 }
1315
1316 /* Uses MCCQ */
1317 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1318 {
1319         struct be_mcc_wrb *wrb;
1320         struct be_cmd_req_if_destroy *req;
1321         int status;
1322
1323         if (interface_id == -1)
1324                 return 0;
1325
1326         spin_lock_bh(&adapter->mcc_lock);
1327
1328         wrb = wrb_from_mccq(adapter);
1329         if (!wrb) {
1330                 status = -EBUSY;
1331                 goto err;
1332         }
1333         req = embedded_payload(wrb);
1334
1335         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1336                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1337         req->hdr.domain = domain;
1338         req->interface_id = cpu_to_le32(interface_id);
1339
1340         status = be_mcc_notify_wait(adapter);
1341 err:
1342         spin_unlock_bh(&adapter->mcc_lock);
1343         return status;
1344 }
1345
1346 /* Get stats is a non embedded command: the request is not embedded inside
1347  * WRB but is a separate dma memory block
1348  * Uses asynchronous MCC
1349  */
1350 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1351 {
1352         struct be_mcc_wrb *wrb;
1353         struct be_cmd_req_hdr *hdr;
1354         int status = 0;
1355
1356         spin_lock_bh(&adapter->mcc_lock);
1357
1358         wrb = wrb_from_mccq(adapter);
1359         if (!wrb) {
1360                 status = -EBUSY;
1361                 goto err;
1362         }
1363         hdr = nonemb_cmd->va;
1364
1365         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1366                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1367
1368         /* version 1 of the cmd is not supported only by BE2 */
1369         if (!BE2_chip(adapter))
1370                 hdr->version = 1;
1371
1372         be_mcc_notify(adapter);
1373         adapter->stats_cmd_sent = true;
1374
1375 err:
1376         spin_unlock_bh(&adapter->mcc_lock);
1377         return status;
1378 }
1379
1380 /* Lancer Stats */
1381 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1382                                 struct be_dma_mem *nonemb_cmd)
1383 {
1384
1385         struct be_mcc_wrb *wrb;
1386         struct lancer_cmd_req_pport_stats *req;
1387         int status = 0;
1388
1389         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1390                             CMD_SUBSYSTEM_ETH))
1391                 return -EPERM;
1392
1393         spin_lock_bh(&adapter->mcc_lock);
1394
1395         wrb = wrb_from_mccq(adapter);
1396         if (!wrb) {
1397                 status = -EBUSY;
1398                 goto err;
1399         }
1400         req = nonemb_cmd->va;
1401
1402         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1403                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1404                         nonemb_cmd);
1405
1406         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1407         req->cmd_params.params.reset_stats = 0;
1408
1409         be_mcc_notify(adapter);
1410         adapter->stats_cmd_sent = true;
1411
1412 err:
1413         spin_unlock_bh(&adapter->mcc_lock);
1414         return status;
1415 }
1416
1417 static int be_mac_to_link_speed(int mac_speed)
1418 {
1419         switch (mac_speed) {
1420         case PHY_LINK_SPEED_ZERO:
1421                 return 0;
1422         case PHY_LINK_SPEED_10MBPS:
1423                 return 10;
1424         case PHY_LINK_SPEED_100MBPS:
1425                 return 100;
1426         case PHY_LINK_SPEED_1GBPS:
1427                 return 1000;
1428         case PHY_LINK_SPEED_10GBPS:
1429                 return 10000;
1430         }
1431         return 0;
1432 }
1433
1434 /* Uses synchronous mcc
1435  * Returns link_speed in Mbps
1436  */
1437 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1438                              u8 *link_status, u32 dom)
1439 {
1440         struct be_mcc_wrb *wrb;
1441         struct be_cmd_req_link_status *req;
1442         int status;
1443
1444         spin_lock_bh(&adapter->mcc_lock);
1445
1446         if (link_status)
1447                 *link_status = LINK_DOWN;
1448
1449         wrb = wrb_from_mccq(adapter);
1450         if (!wrb) {
1451                 status = -EBUSY;
1452                 goto err;
1453         }
1454         req = embedded_payload(wrb);
1455
1456         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1457                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1458
1459         /* version 1 of the cmd is not supported only by BE2 */
1460         if (!BE2_chip(adapter))
1461                 req->hdr.version = 1;
1462
1463         req->hdr.domain = dom;
1464
1465         status = be_mcc_notify_wait(adapter);
1466         if (!status) {
1467                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1468                 if (link_speed) {
1469                         *link_speed = resp->link_speed ?
1470                                       le16_to_cpu(resp->link_speed) * 10 :
1471                                       be_mac_to_link_speed(resp->mac_speed);
1472
1473                         if (!resp->logical_link_status)
1474                                 *link_speed = 0;
1475                 }
1476                 if (link_status)
1477                         *link_status = resp->logical_link_status;
1478         }
1479
1480 err:
1481         spin_unlock_bh(&adapter->mcc_lock);
1482         return status;
1483 }
1484
1485 /* Uses synchronous mcc */
1486 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1487 {
1488         struct be_mcc_wrb *wrb;
1489         struct be_cmd_req_get_cntl_addnl_attribs *req;
1490         int status;
1491
1492         spin_lock_bh(&adapter->mcc_lock);
1493
1494         wrb = wrb_from_mccq(adapter);
1495         if (!wrb) {
1496                 status = -EBUSY;
1497                 goto err;
1498         }
1499         req = embedded_payload(wrb);
1500
1501         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1502                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1503                 wrb, NULL);
1504
1505         be_mcc_notify(adapter);
1506
1507 err:
1508         spin_unlock_bh(&adapter->mcc_lock);
1509         return status;
1510 }
1511
1512 /* Uses synchronous mcc */
1513 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1514 {
1515         struct be_mcc_wrb *wrb;
1516         struct be_cmd_req_get_fat *req;
1517         int status;
1518
1519         spin_lock_bh(&adapter->mcc_lock);
1520
1521         wrb = wrb_from_mccq(adapter);
1522         if (!wrb) {
1523                 status = -EBUSY;
1524                 goto err;
1525         }
1526         req = embedded_payload(wrb);
1527
1528         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1529                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1530         req->fat_operation = cpu_to_le32(QUERY_FAT);
1531         status = be_mcc_notify_wait(adapter);
1532         if (!status) {
1533                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1534                 if (log_size && resp->log_size)
1535                         *log_size = le32_to_cpu(resp->log_size) -
1536                                         sizeof(u32);
1537         }
1538 err:
1539         spin_unlock_bh(&adapter->mcc_lock);
1540         return status;
1541 }
1542
1543 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1544 {
1545         struct be_dma_mem get_fat_cmd;
1546         struct be_mcc_wrb *wrb;
1547         struct be_cmd_req_get_fat *req;
1548         u32 offset = 0, total_size, buf_size,
1549                                 log_offset = sizeof(u32), payload_len;
1550         int status;
1551
1552         if (buf_len == 0)
1553                 return;
1554
1555         total_size = buf_len;
1556
1557         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1558         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1559                         get_fat_cmd.size,
1560                         &get_fat_cmd.dma);
1561         if (!get_fat_cmd.va) {
1562                 status = -ENOMEM;
1563                 dev_err(&adapter->pdev->dev,
1564                 "Memory allocation failure while retrieving FAT data\n");
1565                 return;
1566         }
1567
1568         spin_lock_bh(&adapter->mcc_lock);
1569
1570         while (total_size) {
1571                 buf_size = min(total_size, (u32)60*1024);
1572                 total_size -= buf_size;
1573
1574                 wrb = wrb_from_mccq(adapter);
1575                 if (!wrb) {
1576                         status = -EBUSY;
1577                         goto err;
1578                 }
1579                 req = get_fat_cmd.va;
1580
1581                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1582                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1583                                 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1584                                 &get_fat_cmd);
1585
1586                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1587                 req->read_log_offset = cpu_to_le32(log_offset);
1588                 req->read_log_length = cpu_to_le32(buf_size);
1589                 req->data_buffer_size = cpu_to_le32(buf_size);
1590
1591                 status = be_mcc_notify_wait(adapter);
1592                 if (!status) {
1593                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1594                         memcpy(buf + offset,
1595                                 resp->data_buffer,
1596                                 le32_to_cpu(resp->read_log_length));
1597                 } else {
1598                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1599                         goto err;
1600                 }
1601                 offset += buf_size;
1602                 log_offset += buf_size;
1603         }
1604 err:
1605         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1606                         get_fat_cmd.va,
1607                         get_fat_cmd.dma);
1608         spin_unlock_bh(&adapter->mcc_lock);
1609 }
1610
1611 /* Uses synchronous mcc */
1612 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1613                         char *fw_on_flash)
1614 {
1615         struct be_mcc_wrb *wrb;
1616         struct be_cmd_req_get_fw_version *req;
1617         int status;
1618
1619         spin_lock_bh(&adapter->mcc_lock);
1620
1621         wrb = wrb_from_mccq(adapter);
1622         if (!wrb) {
1623                 status = -EBUSY;
1624                 goto err;
1625         }
1626
1627         req = embedded_payload(wrb);
1628
1629         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1630                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1631         status = be_mcc_notify_wait(adapter);
1632         if (!status) {
1633                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1634                 strcpy(fw_ver, resp->firmware_version_string);
1635                 if (fw_on_flash)
1636                         strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1637         }
1638 err:
1639         spin_unlock_bh(&adapter->mcc_lock);
1640         return status;
1641 }
1642
1643 /* set the EQ delay interval of an EQ to specified value
1644  * Uses async mcc
1645  */
1646 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1647 {
1648         struct be_mcc_wrb *wrb;
1649         struct be_cmd_req_modify_eq_delay *req;
1650         int status = 0;
1651
1652         spin_lock_bh(&adapter->mcc_lock);
1653
1654         wrb = wrb_from_mccq(adapter);
1655         if (!wrb) {
1656                 status = -EBUSY;
1657                 goto err;
1658         }
1659         req = embedded_payload(wrb);
1660
1661         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1662                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1663
1664         req->num_eq = cpu_to_le32(1);
1665         req->delay[0].eq_id = cpu_to_le32(eq_id);
1666         req->delay[0].phase = 0;
1667         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1668
1669         be_mcc_notify(adapter);
1670
1671 err:
1672         spin_unlock_bh(&adapter->mcc_lock);
1673         return status;
1674 }
1675
1676 /* Uses sycnhronous mcc */
1677 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1678                         u32 num, bool untagged, bool promiscuous)
1679 {
1680         struct be_mcc_wrb *wrb;
1681         struct be_cmd_req_vlan_config *req;
1682         int status;
1683
1684         spin_lock_bh(&adapter->mcc_lock);
1685
1686         wrb = wrb_from_mccq(adapter);
1687         if (!wrb) {
1688                 status = -EBUSY;
1689                 goto err;
1690         }
1691         req = embedded_payload(wrb);
1692
1693         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1694                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1695
1696         req->interface_id = if_id;
1697         req->promiscuous = promiscuous;
1698         req->untagged = untagged;
1699         req->num_vlan = num;
1700         if (!promiscuous) {
1701                 memcpy(req->normal_vlan, vtag_array,
1702                         req->num_vlan * sizeof(vtag_array[0]));
1703         }
1704
1705         status = be_mcc_notify_wait(adapter);
1706
1707 err:
1708         spin_unlock_bh(&adapter->mcc_lock);
1709         return status;
1710 }
1711
1712 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1713 {
1714         struct be_mcc_wrb *wrb;
1715         struct be_dma_mem *mem = &adapter->rx_filter;
1716         struct be_cmd_req_rx_filter *req = mem->va;
1717         int status;
1718
1719         spin_lock_bh(&adapter->mcc_lock);
1720
1721         wrb = wrb_from_mccq(adapter);
1722         if (!wrb) {
1723                 status = -EBUSY;
1724                 goto err;
1725         }
1726         memset(req, 0, sizeof(*req));
1727         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1728                                 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1729                                 wrb, mem);
1730
1731         req->if_id = cpu_to_le32(adapter->if_handle);
1732         if (flags & IFF_PROMISC) {
1733                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1734                                         BE_IF_FLAGS_VLAN_PROMISCUOUS);
1735                 if (value == ON)
1736                         req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1737                                                 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1738         } else if (flags & IFF_ALLMULTI) {
1739                 req->if_flags_mask = req->if_flags =
1740                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1741         } else {
1742                 struct netdev_hw_addr *ha;
1743                 int i = 0;
1744
1745                 req->if_flags_mask = req->if_flags =
1746                                 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1747
1748                 /* Reset mcast promisc mode if already set by setting mask
1749                  * and not setting flags field
1750                  */
1751                 req->if_flags_mask |=
1752                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1753                                     adapter->if_cap_flags);
1754
1755                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1756                 netdev_for_each_mc_addr(ha, adapter->netdev)
1757                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1758         }
1759
1760         status = be_mcc_notify_wait(adapter);
1761 err:
1762         spin_unlock_bh(&adapter->mcc_lock);
1763         return status;
1764 }
1765
1766 /* Uses synchrounous mcc */
1767 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1768 {
1769         struct be_mcc_wrb *wrb;
1770         struct be_cmd_req_set_flow_control *req;
1771         int status;
1772
1773         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1774                             CMD_SUBSYSTEM_COMMON))
1775                 return -EPERM;
1776
1777         spin_lock_bh(&adapter->mcc_lock);
1778
1779         wrb = wrb_from_mccq(adapter);
1780         if (!wrb) {
1781                 status = -EBUSY;
1782                 goto err;
1783         }
1784         req = embedded_payload(wrb);
1785
1786         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1787                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1788
1789         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1790         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1791
1792         status = be_mcc_notify_wait(adapter);
1793
1794 err:
1795         spin_unlock_bh(&adapter->mcc_lock);
1796         return status;
1797 }
1798
1799 /* Uses sycn mcc */
1800 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1801 {
1802         struct be_mcc_wrb *wrb;
1803         struct be_cmd_req_get_flow_control *req;
1804         int status;
1805
1806         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1807                             CMD_SUBSYSTEM_COMMON))
1808                 return -EPERM;
1809
1810         spin_lock_bh(&adapter->mcc_lock);
1811
1812         wrb = wrb_from_mccq(adapter);
1813         if (!wrb) {
1814                 status = -EBUSY;
1815                 goto err;
1816         }
1817         req = embedded_payload(wrb);
1818
1819         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1820                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1821
1822         status = be_mcc_notify_wait(adapter);
1823         if (!status) {
1824                 struct be_cmd_resp_get_flow_control *resp =
1825                                                 embedded_payload(wrb);
1826                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1827                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1828         }
1829
1830 err:
1831         spin_unlock_bh(&adapter->mcc_lock);
1832         return status;
1833 }
1834
1835 /* Uses mbox */
1836 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1837                         u32 *mode, u32 *caps, u16 *asic_rev)
1838 {
1839         struct be_mcc_wrb *wrb;
1840         struct be_cmd_req_query_fw_cfg *req;
1841         int status;
1842
1843         if (mutex_lock_interruptible(&adapter->mbox_lock))
1844                 return -1;
1845
1846         wrb = wrb_from_mbox(adapter);
1847         req = embedded_payload(wrb);
1848
1849         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1850                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1851
1852         status = be_mbox_notify_wait(adapter);
1853         if (!status) {
1854                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1855                 *port_num = le32_to_cpu(resp->phys_port);
1856                 *mode = le32_to_cpu(resp->function_mode);
1857                 *caps = le32_to_cpu(resp->function_caps);
1858                 *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
1859         }
1860
1861         mutex_unlock(&adapter->mbox_lock);
1862         return status;
1863 }
1864
1865 /* Uses mbox */
1866 int be_cmd_reset_function(struct be_adapter *adapter)
1867 {
1868         struct be_mcc_wrb *wrb;
1869         struct be_cmd_req_hdr *req;
1870         int status;
1871
1872         if (lancer_chip(adapter)) {
1873                 status = lancer_wait_ready(adapter);
1874                 if (!status) {
1875                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
1876                                   adapter->db + SLIPORT_CONTROL_OFFSET);
1877                         status = lancer_test_and_set_rdy_state(adapter);
1878                 }
1879                 if (status) {
1880                         dev_err(&adapter->pdev->dev,
1881                                 "Adapter in non recoverable error\n");
1882                 }
1883                 return status;
1884         }
1885
1886         if (mutex_lock_interruptible(&adapter->mbox_lock))
1887                 return -1;
1888
1889         wrb = wrb_from_mbox(adapter);
1890         req = embedded_payload(wrb);
1891
1892         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1893                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1894
1895         status = be_mbox_notify_wait(adapter);
1896
1897         mutex_unlock(&adapter->mbox_lock);
1898         return status;
1899 }
1900
1901 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1902 {
1903         struct be_mcc_wrb *wrb;
1904         struct be_cmd_req_rss_config *req;
1905         u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1906                         0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1907                         0x3ea83c02, 0x4a110304};
1908         int status;
1909
1910         if (mutex_lock_interruptible(&adapter->mbox_lock))
1911                 return -1;
1912
1913         wrb = wrb_from_mbox(adapter);
1914         req = embedded_payload(wrb);
1915
1916         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1917                 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1918
1919         req->if_id = cpu_to_le32(adapter->if_handle);
1920         req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4 |
1921                                       RSS_ENABLE_TCP_IPV6 | RSS_ENABLE_IPV6);
1922
1923         if (lancer_chip(adapter) || skyhawk_chip(adapter)) {
1924                 req->hdr.version = 1;
1925                 req->enable_rss |= cpu_to_le16(RSS_ENABLE_UDP_IPV4 |
1926                                                RSS_ENABLE_UDP_IPV6);
1927         }
1928
1929         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1930         memcpy(req->cpu_table, rsstable, table_size);
1931         memcpy(req->hash, myhash, sizeof(myhash));
1932         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1933
1934         status = be_mbox_notify_wait(adapter);
1935
1936         mutex_unlock(&adapter->mbox_lock);
1937         return status;
1938 }
1939
1940 /* Uses sync mcc */
1941 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1942                         u8 bcn, u8 sts, u8 state)
1943 {
1944         struct be_mcc_wrb *wrb;
1945         struct be_cmd_req_enable_disable_beacon *req;
1946         int status;
1947
1948         spin_lock_bh(&adapter->mcc_lock);
1949
1950         wrb = wrb_from_mccq(adapter);
1951         if (!wrb) {
1952                 status = -EBUSY;
1953                 goto err;
1954         }
1955         req = embedded_payload(wrb);
1956
1957         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1958                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
1959
1960         req->port_num = port_num;
1961         req->beacon_state = state;
1962         req->beacon_duration = bcn;
1963         req->status_duration = sts;
1964
1965         status = be_mcc_notify_wait(adapter);
1966
1967 err:
1968         spin_unlock_bh(&adapter->mcc_lock);
1969         return status;
1970 }
1971
1972 /* Uses sync mcc */
1973 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1974 {
1975         struct be_mcc_wrb *wrb;
1976         struct be_cmd_req_get_beacon_state *req;
1977         int status;
1978
1979         spin_lock_bh(&adapter->mcc_lock);
1980
1981         wrb = wrb_from_mccq(adapter);
1982         if (!wrb) {
1983                 status = -EBUSY;
1984                 goto err;
1985         }
1986         req = embedded_payload(wrb);
1987
1988         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1989                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
1990
1991         req->port_num = port_num;
1992
1993         status = be_mcc_notify_wait(adapter);
1994         if (!status) {
1995                 struct be_cmd_resp_get_beacon_state *resp =
1996                                                 embedded_payload(wrb);
1997                 *state = resp->beacon_state;
1998         }
1999
2000 err:
2001         spin_unlock_bh(&adapter->mcc_lock);
2002         return status;
2003 }
2004
2005 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2006                             u32 data_size, u32 data_offset,
2007                             const char *obj_name, u32 *data_written,
2008                             u8 *change_status, u8 *addn_status)
2009 {
2010         struct be_mcc_wrb *wrb;
2011         struct lancer_cmd_req_write_object *req;
2012         struct lancer_cmd_resp_write_object *resp;
2013         void *ctxt = NULL;
2014         int status;
2015
2016         spin_lock_bh(&adapter->mcc_lock);
2017         adapter->flash_status = 0;
2018
2019         wrb = wrb_from_mccq(adapter);
2020         if (!wrb) {
2021                 status = -EBUSY;
2022                 goto err_unlock;
2023         }
2024
2025         req = embedded_payload(wrb);
2026
2027         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2028                                 OPCODE_COMMON_WRITE_OBJECT,
2029                                 sizeof(struct lancer_cmd_req_write_object), wrb,
2030                                 NULL);
2031
2032         ctxt = &req->context;
2033         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2034                         write_length, ctxt, data_size);
2035
2036         if (data_size == 0)
2037                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2038                                 eof, ctxt, 1);
2039         else
2040                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2041                                 eof, ctxt, 0);
2042
2043         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2044         req->write_offset = cpu_to_le32(data_offset);
2045         strcpy(req->object_name, obj_name);
2046         req->descriptor_count = cpu_to_le32(1);
2047         req->buf_len = cpu_to_le32(data_size);
2048         req->addr_low = cpu_to_le32((cmd->dma +
2049                                 sizeof(struct lancer_cmd_req_write_object))
2050                                 & 0xFFFFFFFF);
2051         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2052                                 sizeof(struct lancer_cmd_req_write_object)));
2053
2054         be_mcc_notify(adapter);
2055         spin_unlock_bh(&adapter->mcc_lock);
2056
2057         if (!wait_for_completion_timeout(&adapter->flash_compl,
2058                                          msecs_to_jiffies(30000)))
2059                 status = -1;
2060         else
2061                 status = adapter->flash_status;
2062
2063         resp = embedded_payload(wrb);
2064         if (!status) {
2065                 *data_written = le32_to_cpu(resp->actual_write_len);
2066                 *change_status = resp->change_status;
2067         } else {
2068                 *addn_status = resp->additional_status;
2069         }
2070
2071         return status;
2072
2073 err_unlock:
2074         spin_unlock_bh(&adapter->mcc_lock);
2075         return status;
2076 }
2077
2078 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2079                 u32 data_size, u32 data_offset, const char *obj_name,
2080                 u32 *data_read, u32 *eof, u8 *addn_status)
2081 {
2082         struct be_mcc_wrb *wrb;
2083         struct lancer_cmd_req_read_object *req;
2084         struct lancer_cmd_resp_read_object *resp;
2085         int status;
2086
2087         spin_lock_bh(&adapter->mcc_lock);
2088
2089         wrb = wrb_from_mccq(adapter);
2090         if (!wrb) {
2091                 status = -EBUSY;
2092                 goto err_unlock;
2093         }
2094
2095         req = embedded_payload(wrb);
2096
2097         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2098                         OPCODE_COMMON_READ_OBJECT,
2099                         sizeof(struct lancer_cmd_req_read_object), wrb,
2100                         NULL);
2101
2102         req->desired_read_len = cpu_to_le32(data_size);
2103         req->read_offset = cpu_to_le32(data_offset);
2104         strcpy(req->object_name, obj_name);
2105         req->descriptor_count = cpu_to_le32(1);
2106         req->buf_len = cpu_to_le32(data_size);
2107         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2108         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2109
2110         status = be_mcc_notify_wait(adapter);
2111
2112         resp = embedded_payload(wrb);
2113         if (!status) {
2114                 *data_read = le32_to_cpu(resp->actual_read_len);
2115                 *eof = le32_to_cpu(resp->eof);
2116         } else {
2117                 *addn_status = resp->additional_status;
2118         }
2119
2120 err_unlock:
2121         spin_unlock_bh(&adapter->mcc_lock);
2122         return status;
2123 }
2124
2125 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2126                         u32 flash_type, u32 flash_opcode, u32 buf_size)
2127 {
2128         struct be_mcc_wrb *wrb;
2129         struct be_cmd_write_flashrom *req;
2130         int status;
2131
2132         spin_lock_bh(&adapter->mcc_lock);
2133         adapter->flash_status = 0;
2134
2135         wrb = wrb_from_mccq(adapter);
2136         if (!wrb) {
2137                 status = -EBUSY;
2138                 goto err_unlock;
2139         }
2140         req = cmd->va;
2141
2142         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2143                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
2144
2145         req->params.op_type = cpu_to_le32(flash_type);
2146         req->params.op_code = cpu_to_le32(flash_opcode);
2147         req->params.data_buf_size = cpu_to_le32(buf_size);
2148
2149         be_mcc_notify(adapter);
2150         spin_unlock_bh(&adapter->mcc_lock);
2151
2152         if (!wait_for_completion_timeout(&adapter->flash_compl,
2153                         msecs_to_jiffies(40000)))
2154                 status = -1;
2155         else
2156                 status = adapter->flash_status;
2157
2158         return status;
2159
2160 err_unlock:
2161         spin_unlock_bh(&adapter->mcc_lock);
2162         return status;
2163 }
2164
2165 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2166                          int offset)
2167 {
2168         struct be_mcc_wrb *wrb;
2169         struct be_cmd_read_flash_crc *req;
2170         int status;
2171
2172         spin_lock_bh(&adapter->mcc_lock);
2173
2174         wrb = wrb_from_mccq(adapter);
2175         if (!wrb) {
2176                 status = -EBUSY;
2177                 goto err;
2178         }
2179         req = embedded_payload(wrb);
2180
2181         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2182                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2183                                wrb, NULL);
2184
2185         req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2186         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2187         req->params.offset = cpu_to_le32(offset);
2188         req->params.data_buf_size = cpu_to_le32(0x4);
2189
2190         status = be_mcc_notify_wait(adapter);
2191         if (!status)
2192                 memcpy(flashed_crc, req->crc, 4);
2193
2194 err:
2195         spin_unlock_bh(&adapter->mcc_lock);
2196         return status;
2197 }
2198
2199 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2200                                 struct be_dma_mem *nonemb_cmd)
2201 {
2202         struct be_mcc_wrb *wrb;
2203         struct be_cmd_req_acpi_wol_magic_config *req;
2204         int status;
2205
2206         spin_lock_bh(&adapter->mcc_lock);
2207
2208         wrb = wrb_from_mccq(adapter);
2209         if (!wrb) {
2210                 status = -EBUSY;
2211                 goto err;
2212         }
2213         req = nonemb_cmd->va;
2214
2215         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2216                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2217                 nonemb_cmd);
2218         memcpy(req->magic_mac, mac, ETH_ALEN);
2219
2220         status = be_mcc_notify_wait(adapter);
2221
2222 err:
2223         spin_unlock_bh(&adapter->mcc_lock);
2224         return status;
2225 }
2226
2227 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2228                         u8 loopback_type, u8 enable)
2229 {
2230         struct be_mcc_wrb *wrb;
2231         struct be_cmd_req_set_lmode *req;
2232         int status;
2233
2234         spin_lock_bh(&adapter->mcc_lock);
2235
2236         wrb = wrb_from_mccq(adapter);
2237         if (!wrb) {
2238                 status = -EBUSY;
2239                 goto err;
2240         }
2241
2242         req = embedded_payload(wrb);
2243
2244         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2245                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2246                         NULL);
2247
2248         req->src_port = port_num;
2249         req->dest_port = port_num;
2250         req->loopback_type = loopback_type;
2251         req->loopback_state = enable;
2252
2253         status = be_mcc_notify_wait(adapter);
2254 err:
2255         spin_unlock_bh(&adapter->mcc_lock);
2256         return status;
2257 }
2258
2259 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2260                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2261 {
2262         struct be_mcc_wrb *wrb;
2263         struct be_cmd_req_loopback_test *req;
2264         int status;
2265
2266         spin_lock_bh(&adapter->mcc_lock);
2267
2268         wrb = wrb_from_mccq(adapter);
2269         if (!wrb) {
2270                 status = -EBUSY;
2271                 goto err;
2272         }
2273
2274         req = embedded_payload(wrb);
2275
2276         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2277                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2278         req->hdr.timeout = cpu_to_le32(4);
2279
2280         req->pattern = cpu_to_le64(pattern);
2281         req->src_port = cpu_to_le32(port_num);
2282         req->dest_port = cpu_to_le32(port_num);
2283         req->pkt_size = cpu_to_le32(pkt_size);
2284         req->num_pkts = cpu_to_le32(num_pkts);
2285         req->loopback_type = cpu_to_le32(loopback_type);
2286
2287         status = be_mcc_notify_wait(adapter);
2288         if (!status) {
2289                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2290                 status = le32_to_cpu(resp->status);
2291         }
2292
2293 err:
2294         spin_unlock_bh(&adapter->mcc_lock);
2295         return status;
2296 }
2297
2298 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2299                                 u32 byte_cnt, struct be_dma_mem *cmd)
2300 {
2301         struct be_mcc_wrb *wrb;
2302         struct be_cmd_req_ddrdma_test *req;
2303         int status;
2304         int i, j = 0;
2305
2306         spin_lock_bh(&adapter->mcc_lock);
2307
2308         wrb = wrb_from_mccq(adapter);
2309         if (!wrb) {
2310                 status = -EBUSY;
2311                 goto err;
2312         }
2313         req = cmd->va;
2314         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2315                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2316
2317         req->pattern = cpu_to_le64(pattern);
2318         req->byte_count = cpu_to_le32(byte_cnt);
2319         for (i = 0; i < byte_cnt; i++) {
2320                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2321                 j++;
2322                 if (j > 7)
2323                         j = 0;
2324         }
2325
2326         status = be_mcc_notify_wait(adapter);
2327
2328         if (!status) {
2329                 struct be_cmd_resp_ddrdma_test *resp;
2330                 resp = cmd->va;
2331                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2332                                 resp->snd_err) {
2333                         status = -1;
2334                 }
2335         }
2336
2337 err:
2338         spin_unlock_bh(&adapter->mcc_lock);
2339         return status;
2340 }
2341
2342 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2343                                 struct be_dma_mem *nonemb_cmd)
2344 {
2345         struct be_mcc_wrb *wrb;
2346         struct be_cmd_req_seeprom_read *req;
2347         int status;
2348
2349         spin_lock_bh(&adapter->mcc_lock);
2350
2351         wrb = wrb_from_mccq(adapter);
2352         if (!wrb) {
2353                 status = -EBUSY;
2354                 goto err;
2355         }
2356         req = nonemb_cmd->va;
2357
2358         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2359                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2360                         nonemb_cmd);
2361
2362         status = be_mcc_notify_wait(adapter);
2363
2364 err:
2365         spin_unlock_bh(&adapter->mcc_lock);
2366         return status;
2367 }
2368
2369 int be_cmd_get_phy_info(struct be_adapter *adapter)
2370 {
2371         struct be_mcc_wrb *wrb;
2372         struct be_cmd_req_get_phy_info *req;
2373         struct be_dma_mem cmd;
2374         int status;
2375
2376         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2377                             CMD_SUBSYSTEM_COMMON))
2378                 return -EPERM;
2379
2380         spin_lock_bh(&adapter->mcc_lock);
2381
2382         wrb = wrb_from_mccq(adapter);
2383         if (!wrb) {
2384                 status = -EBUSY;
2385                 goto err;
2386         }
2387         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2388         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2389                                         &cmd.dma);
2390         if (!cmd.va) {
2391                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2392                 status = -ENOMEM;
2393                 goto err;
2394         }
2395
2396         req = cmd.va;
2397
2398         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2399                         OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2400                         wrb, &cmd);
2401
2402         status = be_mcc_notify_wait(adapter);
2403         if (!status) {
2404                 struct be_phy_info *resp_phy_info =
2405                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2406                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2407                 adapter->phy.interface_type =
2408                         le16_to_cpu(resp_phy_info->interface_type);
2409                 adapter->phy.auto_speeds_supported =
2410                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
2411                 adapter->phy.fixed_speeds_supported =
2412                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2413                 adapter->phy.misc_params =
2414                         le32_to_cpu(resp_phy_info->misc_params);
2415         }
2416         pci_free_consistent(adapter->pdev, cmd.size,
2417                                 cmd.va, cmd.dma);
2418 err:
2419         spin_unlock_bh(&adapter->mcc_lock);
2420         return status;
2421 }
2422
2423 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2424 {
2425         struct be_mcc_wrb *wrb;
2426         struct be_cmd_req_set_qos *req;
2427         int status;
2428
2429         spin_lock_bh(&adapter->mcc_lock);
2430
2431         wrb = wrb_from_mccq(adapter);
2432         if (!wrb) {
2433                 status = -EBUSY;
2434                 goto err;
2435         }
2436
2437         req = embedded_payload(wrb);
2438
2439         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2440                         OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2441
2442         req->hdr.domain = domain;
2443         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2444         req->max_bps_nic = cpu_to_le32(bps);
2445
2446         status = be_mcc_notify_wait(adapter);
2447
2448 err:
2449         spin_unlock_bh(&adapter->mcc_lock);
2450         return status;
2451 }
2452
2453 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2454 {
2455         struct be_mcc_wrb *wrb;
2456         struct be_cmd_req_cntl_attribs *req;
2457         struct be_cmd_resp_cntl_attribs *resp;
2458         int status;
2459         int payload_len = max(sizeof(*req), sizeof(*resp));
2460         struct mgmt_controller_attrib *attribs;
2461         struct be_dma_mem attribs_cmd;
2462
2463         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2464         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2465         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2466                                                 &attribs_cmd.dma);
2467         if (!attribs_cmd.va) {
2468                 dev_err(&adapter->pdev->dev,
2469                                 "Memory allocation failure\n");
2470                 return -ENOMEM;
2471         }
2472
2473         if (mutex_lock_interruptible(&adapter->mbox_lock))
2474                 return -1;
2475
2476         wrb = wrb_from_mbox(adapter);
2477         if (!wrb) {
2478                 status = -EBUSY;
2479                 goto err;
2480         }
2481         req = attribs_cmd.va;
2482
2483         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2484                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2485                         &attribs_cmd);
2486
2487         status = be_mbox_notify_wait(adapter);
2488         if (!status) {
2489                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2490                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2491         }
2492
2493 err:
2494         mutex_unlock(&adapter->mbox_lock);
2495         pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2496                                         attribs_cmd.dma);
2497         return status;
2498 }
2499
2500 /* Uses mbox */
2501 int be_cmd_req_native_mode(struct be_adapter *adapter)
2502 {
2503         struct be_mcc_wrb *wrb;
2504         struct be_cmd_req_set_func_cap *req;
2505         int status;
2506
2507         if (mutex_lock_interruptible(&adapter->mbox_lock))
2508                 return -1;
2509
2510         wrb = wrb_from_mbox(adapter);
2511         if (!wrb) {
2512                 status = -EBUSY;
2513                 goto err;
2514         }
2515
2516         req = embedded_payload(wrb);
2517
2518         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2519                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2520
2521         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2522                                 CAPABILITY_BE3_NATIVE_ERX_API);
2523         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2524
2525         status = be_mbox_notify_wait(adapter);
2526         if (!status) {
2527                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2528                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2529                                         CAPABILITY_BE3_NATIVE_ERX_API;
2530                 if (!adapter->be3_native)
2531                         dev_warn(&adapter->pdev->dev,
2532                                  "adapter not in advanced mode\n");
2533         }
2534 err:
2535         mutex_unlock(&adapter->mbox_lock);
2536         return status;
2537 }
2538
2539 /* Get privilege(s) for a function */
2540 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2541                              u32 domain)
2542 {
2543         struct be_mcc_wrb *wrb;
2544         struct be_cmd_req_get_fn_privileges *req;
2545         int status;
2546
2547         spin_lock_bh(&adapter->mcc_lock);
2548
2549         wrb = wrb_from_mccq(adapter);
2550         if (!wrb) {
2551                 status = -EBUSY;
2552                 goto err;
2553         }
2554
2555         req = embedded_payload(wrb);
2556
2557         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2558                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2559                                wrb, NULL);
2560
2561         req->hdr.domain = domain;
2562
2563         status = be_mcc_notify_wait(adapter);
2564         if (!status) {
2565                 struct be_cmd_resp_get_fn_privileges *resp =
2566                                                 embedded_payload(wrb);
2567                 *privilege = le32_to_cpu(resp->privilege_mask);
2568         }
2569
2570 err:
2571         spin_unlock_bh(&adapter->mcc_lock);
2572         return status;
2573 }
2574
2575 /* Uses synchronous MCCQ */
2576 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2577                              bool *pmac_id_active, u32 *pmac_id, u8 domain)
2578 {
2579         struct be_mcc_wrb *wrb;
2580         struct be_cmd_req_get_mac_list *req;
2581         int status;
2582         int mac_count;
2583         struct be_dma_mem get_mac_list_cmd;
2584         int i;
2585
2586         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2587         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2588         get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2589                         get_mac_list_cmd.size,
2590                         &get_mac_list_cmd.dma);
2591
2592         if (!get_mac_list_cmd.va) {
2593                 dev_err(&adapter->pdev->dev,
2594                                 "Memory allocation failure during GET_MAC_LIST\n");
2595                 return -ENOMEM;
2596         }
2597
2598         spin_lock_bh(&adapter->mcc_lock);
2599
2600         wrb = wrb_from_mccq(adapter);
2601         if (!wrb) {
2602                 status = -EBUSY;
2603                 goto out;
2604         }
2605
2606         req = get_mac_list_cmd.va;
2607
2608         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2609                                 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req),
2610                                 wrb, &get_mac_list_cmd);
2611
2612         req->hdr.domain = domain;
2613         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2614         req->perm_override = 1;
2615
2616         status = be_mcc_notify_wait(adapter);
2617         if (!status) {
2618                 struct be_cmd_resp_get_mac_list *resp =
2619                                                 get_mac_list_cmd.va;
2620                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2621                 /* Mac list returned could contain one or more active mac_ids
2622                  * or one or more true or pseudo permanant mac addresses.
2623                  * If an active mac_id is present, return first active mac_id
2624                  * found.
2625                  */
2626                 for (i = 0; i < mac_count; i++) {
2627                         struct get_list_macaddr *mac_entry;
2628                         u16 mac_addr_size;
2629                         u32 mac_id;
2630
2631                         mac_entry = &resp->macaddr_list[i];
2632                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2633                         /* mac_id is a 32 bit value and mac_addr size
2634                          * is 6 bytes
2635                          */
2636                         if (mac_addr_size == sizeof(u32)) {
2637                                 *pmac_id_active = true;
2638                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2639                                 *pmac_id = le32_to_cpu(mac_id);
2640                                 goto out;
2641                         }
2642                 }
2643                 /* If no active mac_id found, return first mac addr */
2644                 *pmac_id_active = false;
2645                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2646                                                                 ETH_ALEN);
2647         }
2648
2649 out:
2650         spin_unlock_bh(&adapter->mcc_lock);
2651         pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2652                         get_mac_list_cmd.va, get_mac_list_cmd.dma);
2653         return status;
2654 }
2655
2656 /* Uses synchronous MCCQ */
2657 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2658                         u8 mac_count, u32 domain)
2659 {
2660         struct be_mcc_wrb *wrb;
2661         struct be_cmd_req_set_mac_list *req;
2662         int status;
2663         struct be_dma_mem cmd;
2664
2665         memset(&cmd, 0, sizeof(struct be_dma_mem));
2666         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2667         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2668                         &cmd.dma, GFP_KERNEL);
2669         if (!cmd.va)
2670                 return -ENOMEM;
2671
2672         spin_lock_bh(&adapter->mcc_lock);
2673
2674         wrb = wrb_from_mccq(adapter);
2675         if (!wrb) {
2676                 status = -EBUSY;
2677                 goto err;
2678         }
2679
2680         req = cmd.va;
2681         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2682                                 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2683                                 wrb, &cmd);
2684
2685         req->hdr.domain = domain;
2686         req->mac_count = mac_count;
2687         if (mac_count)
2688                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2689
2690         status = be_mcc_notify_wait(adapter);
2691
2692 err:
2693         dma_free_coherent(&adapter->pdev->dev, cmd.size,
2694                                 cmd.va, cmd.dma);
2695         spin_unlock_bh(&adapter->mcc_lock);
2696         return status;
2697 }
2698
2699 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2700                         u32 domain, u16 intf_id)
2701 {
2702         struct be_mcc_wrb *wrb;
2703         struct be_cmd_req_set_hsw_config *req;
2704         void *ctxt;
2705         int status;
2706
2707         spin_lock_bh(&adapter->mcc_lock);
2708
2709         wrb = wrb_from_mccq(adapter);
2710         if (!wrb) {
2711                 status = -EBUSY;
2712                 goto err;
2713         }
2714
2715         req = embedded_payload(wrb);
2716         ctxt = &req->context;
2717
2718         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2719                         OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2720
2721         req->hdr.domain = domain;
2722         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2723         if (pvid) {
2724                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2725                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2726         }
2727
2728         be_dws_cpu_to_le(req->context, sizeof(req->context));
2729         status = be_mcc_notify_wait(adapter);
2730
2731 err:
2732         spin_unlock_bh(&adapter->mcc_lock);
2733         return status;
2734 }
2735
2736 /* Get Hyper switch config */
2737 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2738                         u32 domain, u16 intf_id)
2739 {
2740         struct be_mcc_wrb *wrb;
2741         struct be_cmd_req_get_hsw_config *req;
2742         void *ctxt;
2743         int status;
2744         u16 vid;
2745
2746         spin_lock_bh(&adapter->mcc_lock);
2747
2748         wrb = wrb_from_mccq(adapter);
2749         if (!wrb) {
2750                 status = -EBUSY;
2751                 goto err;
2752         }
2753
2754         req = embedded_payload(wrb);
2755         ctxt = &req->context;
2756
2757         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2758                         OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2759
2760         req->hdr.domain = domain;
2761         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2762                                                                 intf_id);
2763         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2764         be_dws_cpu_to_le(req->context, sizeof(req->context));
2765
2766         status = be_mcc_notify_wait(adapter);
2767         if (!status) {
2768                 struct be_cmd_resp_get_hsw_config *resp =
2769                                                 embedded_payload(wrb);
2770                 be_dws_le_to_cpu(&resp->context,
2771                                                 sizeof(resp->context));
2772                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2773                                                         pvid, &resp->context);
2774                 *pvid = le16_to_cpu(vid);
2775         }
2776
2777 err:
2778         spin_unlock_bh(&adapter->mcc_lock);
2779         return status;
2780 }
2781
2782 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2783 {
2784         struct be_mcc_wrb *wrb;
2785         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2786         int status;
2787         int payload_len = sizeof(*req);
2788         struct be_dma_mem cmd;
2789
2790         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2791                             CMD_SUBSYSTEM_ETH))
2792                 return -EPERM;
2793
2794         memset(&cmd, 0, sizeof(struct be_dma_mem));
2795         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2796         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2797                                                &cmd.dma);
2798         if (!cmd.va) {
2799                 dev_err(&adapter->pdev->dev,
2800                                 "Memory allocation failure\n");
2801                 return -ENOMEM;
2802         }
2803
2804         if (mutex_lock_interruptible(&adapter->mbox_lock))
2805                 return -1;
2806
2807         wrb = wrb_from_mbox(adapter);
2808         if (!wrb) {
2809                 status = -EBUSY;
2810                 goto err;
2811         }
2812
2813         req = cmd.va;
2814
2815         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2816                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2817                                payload_len, wrb, &cmd);
2818
2819         req->hdr.version = 1;
2820         req->query_options = BE_GET_WOL_CAP;
2821
2822         status = be_mbox_notify_wait(adapter);
2823         if (!status) {
2824                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2825                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2826
2827                 /* the command could succeed misleadingly on old f/w
2828                  * which is not aware of the V1 version. fake an error. */
2829                 if (resp->hdr.response_length < payload_len) {
2830                         status = -1;
2831                         goto err;
2832                 }
2833                 adapter->wol_cap = resp->wol_settings;
2834         }
2835 err:
2836         mutex_unlock(&adapter->mbox_lock);
2837         pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2838         return status;
2839
2840 }
2841 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2842                                    struct be_dma_mem *cmd)
2843 {
2844         struct be_mcc_wrb *wrb;
2845         struct be_cmd_req_get_ext_fat_caps *req;
2846         int status;
2847
2848         if (mutex_lock_interruptible(&adapter->mbox_lock))
2849                 return -1;
2850
2851         wrb = wrb_from_mbox(adapter);
2852         if (!wrb) {
2853                 status = -EBUSY;
2854                 goto err;
2855         }
2856
2857         req = cmd->va;
2858         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2859                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
2860                                cmd->size, wrb, cmd);
2861         req->parameter_type = cpu_to_le32(1);
2862
2863         status = be_mbox_notify_wait(adapter);
2864 err:
2865         mutex_unlock(&adapter->mbox_lock);
2866         return status;
2867 }
2868
2869 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2870                                    struct be_dma_mem *cmd,
2871                                    struct be_fat_conf_params *configs)
2872 {
2873         struct be_mcc_wrb *wrb;
2874         struct be_cmd_req_set_ext_fat_caps *req;
2875         int status;
2876
2877         spin_lock_bh(&adapter->mcc_lock);
2878
2879         wrb = wrb_from_mccq(adapter);
2880         if (!wrb) {
2881                 status = -EBUSY;
2882                 goto err;
2883         }
2884
2885         req = cmd->va;
2886         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
2887         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2888                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
2889                                cmd->size, wrb, cmd);
2890
2891         status = be_mcc_notify_wait(adapter);
2892 err:
2893         spin_unlock_bh(&adapter->mcc_lock);
2894         return status;
2895 }
2896
2897 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
2898 {
2899         struct be_mcc_wrb *wrb;
2900         struct be_cmd_req_get_port_name *req;
2901         int status;
2902
2903         if (!lancer_chip(adapter)) {
2904                 *port_name = adapter->hba_port_num + '0';
2905                 return 0;
2906         }
2907
2908         spin_lock_bh(&adapter->mcc_lock);
2909
2910         wrb = wrb_from_mccq(adapter);
2911         if (!wrb) {
2912                 status = -EBUSY;
2913                 goto err;
2914         }
2915
2916         req = embedded_payload(wrb);
2917
2918         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2919                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
2920                                NULL);
2921         req->hdr.version = 1;
2922
2923         status = be_mcc_notify_wait(adapter);
2924         if (!status) {
2925                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
2926                 *port_name = resp->port_name[adapter->hba_port_num];
2927         } else {
2928                 *port_name = adapter->hba_port_num + '0';
2929         }
2930 err:
2931         spin_unlock_bh(&adapter->mcc_lock);
2932         return status;
2933 }
2934
2935 static struct be_nic_resource_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
2936                                                     u32 max_buf_size)
2937 {
2938         struct be_nic_resource_desc *desc = (struct be_nic_resource_desc *)buf;
2939         int i;
2940
2941         for (i = 0; i < desc_count; i++) {
2942                 desc->desc_len = RESOURCE_DESC_SIZE;
2943                 if (((void *)desc + desc->desc_len) >
2944                     (void *)(buf + max_buf_size)) {
2945                         desc = NULL;
2946                         break;
2947                 }
2948
2949                 if (desc->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
2950                     desc->desc_type == NIC_RESOURCE_DESC_TYPE_V1)
2951                         break;
2952
2953                 desc = (void *)desc + desc->desc_len;
2954         }
2955
2956         if (!desc || i == MAX_RESOURCE_DESC)
2957                 return NULL;
2958
2959         return desc;
2960 }
2961
2962 /* Uses Mbox */
2963 int be_cmd_get_func_config(struct be_adapter *adapter)
2964 {
2965         struct be_mcc_wrb *wrb;
2966         struct be_cmd_req_get_func_config *req;
2967         int status;
2968         struct be_dma_mem cmd;
2969
2970         memset(&cmd, 0, sizeof(struct be_dma_mem));
2971         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
2972         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2973                                       &cmd.dma);
2974         if (!cmd.va) {
2975                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2976                 return -ENOMEM;
2977         }
2978         if (mutex_lock_interruptible(&adapter->mbox_lock))
2979                 return -1;
2980
2981         wrb = wrb_from_mbox(adapter);
2982         if (!wrb) {
2983                 status = -EBUSY;
2984                 goto err;
2985         }
2986
2987         req = cmd.va;
2988
2989         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2990                                OPCODE_COMMON_GET_FUNC_CONFIG,
2991                                cmd.size, wrb, &cmd);
2992
2993         status = be_mbox_notify_wait(adapter);
2994         if (!status) {
2995                 struct be_cmd_resp_get_func_config *resp = cmd.va;
2996                 u32 desc_count = le32_to_cpu(resp->desc_count);
2997                 struct be_nic_resource_desc *desc;
2998
2999                 desc = be_get_nic_desc(resp->func_param, desc_count,
3000                                        sizeof(resp->func_param));
3001                 if (!desc) {
3002                         status = -EINVAL;
3003                         goto err;
3004                 }
3005
3006                 adapter->pf_number = desc->pf_num;
3007                 adapter->max_pmac_cnt = le16_to_cpu(desc->unicast_mac_count);
3008                 adapter->max_vlans = le16_to_cpu(desc->vlan_count);
3009                 adapter->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3010                 adapter->max_tx_queues = le16_to_cpu(desc->txq_count);
3011                 adapter->max_rss_queues = le16_to_cpu(desc->rssq_count);
3012                 adapter->max_rx_queues = le16_to_cpu(desc->rq_count);
3013
3014                 adapter->max_event_queues = le16_to_cpu(desc->eq_count);
3015                 adapter->if_cap_flags = le32_to_cpu(desc->cap_flags);
3016         }
3017 err:
3018         mutex_unlock(&adapter->mbox_lock);
3019         pci_free_consistent(adapter->pdev, cmd.size,
3020                             cmd.va, cmd.dma);
3021         return status;
3022 }
3023
3024 /* Uses mbox */
3025 int be_cmd_get_profile_config_mbox(struct be_adapter *adapter,
3026                                    u8 domain, struct be_dma_mem *cmd)
3027 {
3028         struct be_mcc_wrb *wrb;
3029         struct be_cmd_req_get_profile_config *req;
3030         int status;
3031
3032         if (mutex_lock_interruptible(&adapter->mbox_lock))
3033                 return -1;
3034         wrb = wrb_from_mbox(adapter);
3035
3036         req = cmd->va;
3037         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3038                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3039                                cmd->size, wrb, cmd);
3040
3041         req->type = ACTIVE_PROFILE_TYPE;
3042         req->hdr.domain = domain;
3043         if (!lancer_chip(adapter))
3044                 req->hdr.version = 1;
3045
3046         status = be_mbox_notify_wait(adapter);
3047
3048         mutex_unlock(&adapter->mbox_lock);
3049         return status;
3050 }
3051
3052 /* Uses sync mcc */
3053 int be_cmd_get_profile_config_mccq(struct be_adapter *adapter,
3054                                    u8 domain, struct be_dma_mem *cmd)
3055 {
3056         struct be_mcc_wrb *wrb;
3057         struct be_cmd_req_get_profile_config *req;
3058         int status;
3059
3060         spin_lock_bh(&adapter->mcc_lock);
3061
3062         wrb = wrb_from_mccq(adapter);
3063         if (!wrb) {
3064                 status = -EBUSY;
3065                 goto err;
3066         }
3067
3068         req = cmd->va;
3069         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3070                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3071                                cmd->size, wrb, cmd);
3072
3073         req->type = ACTIVE_PROFILE_TYPE;
3074         req->hdr.domain = domain;
3075         if (!lancer_chip(adapter))
3076                 req->hdr.version = 1;
3077
3078         status = be_mcc_notify_wait(adapter);
3079
3080 err:
3081         spin_unlock_bh(&adapter->mcc_lock);
3082         return status;
3083 }
3084
3085 /* Uses sync mcc, if MCCQ is already created otherwise mbox */
3086 int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags,
3087                               u16 *txq_count, u8 domain)
3088 {
3089         struct be_queue_info *mccq = &adapter->mcc_obj.q;
3090         struct be_dma_mem cmd;
3091         int status;
3092
3093         memset(&cmd, 0, sizeof(struct be_dma_mem));
3094         if (!lancer_chip(adapter))
3095                 cmd.size = sizeof(struct be_cmd_resp_get_profile_config_v1);
3096         else
3097                 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3098         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3099                                       &cmd.dma);
3100         if (!cmd.va) {
3101                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3102                 return -ENOMEM;
3103         }
3104
3105         if (!mccq->created)
3106                 status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd);
3107         else
3108                 status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd);
3109         if (!status) {
3110                 struct be_cmd_resp_get_profile_config *resp = cmd.va;
3111                 u32 desc_count = le32_to_cpu(resp->desc_count);
3112                 struct be_nic_resource_desc *desc;
3113
3114                 desc = be_get_nic_desc(resp->func_param, desc_count,
3115                                        sizeof(resp->func_param));
3116
3117                 if (!desc) {
3118                         status = -EINVAL;
3119                         goto err;
3120                 }
3121                 if (cap_flags)
3122                         *cap_flags = le32_to_cpu(desc->cap_flags);
3123                 if (txq_count)
3124                         *txq_count = le32_to_cpu(desc->txq_count);
3125         }
3126 err:
3127         if (cmd.va)
3128                 pci_free_consistent(adapter->pdev, cmd.size,
3129                                     cmd.va, cmd.dma);
3130         return status;
3131 }
3132
3133 /* Uses sync mcc */
3134 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
3135                               u8 domain)
3136 {
3137         struct be_mcc_wrb *wrb;
3138         struct be_cmd_req_set_profile_config *req;
3139         int status;
3140
3141         spin_lock_bh(&adapter->mcc_lock);
3142
3143         wrb = wrb_from_mccq(adapter);
3144         if (!wrb) {
3145                 status = -EBUSY;
3146                 goto err;
3147         }
3148
3149         req = embedded_payload(wrb);
3150
3151         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3152                                OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3153                                wrb, NULL);
3154
3155         req->hdr.domain = domain;
3156         req->desc_count = cpu_to_le32(1);
3157
3158         req->nic_desc.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3159         req->nic_desc.desc_len = RESOURCE_DESC_SIZE;
3160         req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV);
3161         req->nic_desc.pf_num = adapter->pf_number;
3162         req->nic_desc.vf_num = domain;
3163
3164         /* Mark fields invalid */
3165         req->nic_desc.unicast_mac_count = 0xFFFF;
3166         req->nic_desc.mcc_count = 0xFFFF;
3167         req->nic_desc.vlan_count = 0xFFFF;
3168         req->nic_desc.mcast_mac_count = 0xFFFF;
3169         req->nic_desc.txq_count = 0xFFFF;
3170         req->nic_desc.rq_count = 0xFFFF;
3171         req->nic_desc.rssq_count = 0xFFFF;
3172         req->nic_desc.lro_count = 0xFFFF;
3173         req->nic_desc.cq_count = 0xFFFF;
3174         req->nic_desc.toe_conn_count = 0xFFFF;
3175         req->nic_desc.eq_count = 0xFFFF;
3176         req->nic_desc.link_param = 0xFF;
3177         req->nic_desc.bw_min = 0xFFFFFFFF;
3178         req->nic_desc.acpi_params = 0xFF;
3179         req->nic_desc.wol_param = 0x0F;
3180
3181         /* Change BW */
3182         req->nic_desc.bw_min = cpu_to_le32(bps);
3183         req->nic_desc.bw_max = cpu_to_le32(bps);
3184         status = be_mcc_notify_wait(adapter);
3185 err:
3186         spin_unlock_bh(&adapter->mcc_lock);
3187         return status;
3188 }
3189
3190 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3191                      int vf_num)
3192 {
3193         struct be_mcc_wrb *wrb;
3194         struct be_cmd_req_get_iface_list *req;
3195         struct be_cmd_resp_get_iface_list *resp;
3196         int status;
3197
3198         spin_lock_bh(&adapter->mcc_lock);
3199
3200         wrb = wrb_from_mccq(adapter);
3201         if (!wrb) {
3202                 status = -EBUSY;
3203                 goto err;
3204         }
3205         req = embedded_payload(wrb);
3206
3207         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3208                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3209                                wrb, NULL);
3210         req->hdr.domain = vf_num + 1;
3211
3212         status = be_mcc_notify_wait(adapter);
3213         if (!status) {
3214                 resp = (struct be_cmd_resp_get_iface_list *)req;
3215                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3216         }
3217
3218 err:
3219         spin_unlock_bh(&adapter->mcc_lock);
3220         return status;
3221 }
3222
3223 /* Uses sync mcc */
3224 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3225 {
3226         struct be_mcc_wrb *wrb;
3227         struct be_cmd_enable_disable_vf *req;
3228         int status;
3229
3230         if (!lancer_chip(adapter))
3231                 return 0;
3232
3233         spin_lock_bh(&adapter->mcc_lock);
3234
3235         wrb = wrb_from_mccq(adapter);
3236         if (!wrb) {
3237                 status = -EBUSY;
3238                 goto err;
3239         }
3240
3241         req = embedded_payload(wrb);
3242
3243         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3244                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3245                                wrb, NULL);
3246
3247         req->hdr.domain = domain;
3248         req->enable = 1;
3249         status = be_mcc_notify_wait(adapter);
3250 err:
3251         spin_unlock_bh(&adapter->mcc_lock);
3252         return status;
3253 }
3254
3255 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
3256 {
3257         struct be_mcc_wrb *wrb;
3258         struct be_cmd_req_intr_set *req;
3259         int status;
3260
3261         if (mutex_lock_interruptible(&adapter->mbox_lock))
3262                 return -1;
3263
3264         wrb = wrb_from_mbox(adapter);
3265
3266         req = embedded_payload(wrb);
3267
3268         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3269                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
3270                                wrb, NULL);
3271
3272         req->intr_enabled = intr_enable;
3273
3274         status = be_mbox_notify_wait(adapter);
3275
3276         mutex_unlock(&adapter->mbox_lock);
3277         return status;
3278 }
3279
3280 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3281                         int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3282 {
3283         struct be_adapter *adapter = netdev_priv(netdev_handle);
3284         struct be_mcc_wrb *wrb;
3285         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3286         struct be_cmd_req_hdr *req;
3287         struct be_cmd_resp_hdr *resp;
3288         int status;
3289
3290         spin_lock_bh(&adapter->mcc_lock);
3291
3292         wrb = wrb_from_mccq(adapter);
3293         if (!wrb) {
3294                 status = -EBUSY;
3295                 goto err;
3296         }
3297         req = embedded_payload(wrb);
3298         resp = embedded_payload(wrb);
3299
3300         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3301                                hdr->opcode, wrb_payload_size, wrb, NULL);
3302         memcpy(req, wrb_payload, wrb_payload_size);
3303         be_dws_cpu_to_le(req, wrb_payload_size);
3304
3305         status = be_mcc_notify_wait(adapter);
3306         if (cmd_status)
3307                 *cmd_status = (status & 0xffff);
3308         if (ext_status)
3309                 *ext_status = 0;
3310         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3311         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3312 err:
3313         spin_unlock_bh(&adapter->mcc_lock);
3314         return status;
3315 }
3316 EXPORT_SYMBOL(be_roce_mcc_cmd);