drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2011 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  23 {
  24         return wrb->payload.embedded_payload;
  25 }
  26
  27 static void be_mcc_notify(struct be_adapter *adapter)
  28 {
  29         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  30         u32 val = 0;
  31
  32         if (be_error(adapter))
  33                 return;
  34
  35         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  36         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  37
  38         wmb();
  39         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  40 }
  41
  42 /* To check if valid bit is set, check the entire word as we don't know
  43  * the endianness of the data (old entry is host endian while a new entry is
  44  * little endian) */
  45 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  46 {
  47         if (compl->flags != 0) {
  48                 compl->flags = le32_to_cpu(compl->flags);
  49                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
  50                 return true;
  51         } else {
  52                 return false;
  53         }
  54 }
  55
  56 /* Need to reset the entire word that houses the valid bit */
  57 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
  58 {
  59         compl->flags = 0;
  60 }
  61
  62 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
  63 {
  64         unsigned long addr;
  65
  66         addr = tag1;
  67         addr = ((addr << 16) << 16) | tag0;
  68         return (void *)addr;
  69 }
  70
  71 static int be_mcc_compl_process(struct be_adapter *adapter,
  72                                 struct be_mcc_compl *compl)
  73 {
  74         u16 compl_status, extd_status;
  75         struct be_cmd_resp_hdr *resp_hdr;
  76         u8 opcode = 0, subsystem = 0;
  77
  78         /* Just swap the status to host endian; mcc tag is opaquely copied
  79          * from mcc_wrb */
  80         be_dws_le_to_cpu(compl, 4);
  81
  82         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
  83                                 CQE_STATUS_COMPL_MASK;
  84
  85         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
  86
  87         if (resp_hdr) {
  88                 opcode = resp_hdr->opcode;
  89                 subsystem = resp_hdr->subsystem;
  90         }
  91
  92         if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
  93              (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
  94             (subsystem == CMD_SUBSYSTEM_COMMON)) {
  95                 adapter->flash_status = compl_status;
  96                 complete(&adapter->flash_compl);
  97         }
  98
  99         if (compl_status == MCC_STATUS_SUCCESS) {
 100                 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
 101                      (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
 102                     (subsystem == CMD_SUBSYSTEM_ETH)) {
 103                         be_parse_stats(adapter);
 104                         adapter->stats_cmd_sent = false;
 105                 }
 106                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 107                     subsystem == CMD_SUBSYSTEM_COMMON) {
 108                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 109                                 (void *)resp_hdr;
 110                         adapter->drv_stats.be_on_die_temperature =
 111                                 resp->on_die_temperature;
 112                 }
 113         } else {
 114                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
 115                         adapter->be_get_temp_freq = 0;
 116
 117                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 118                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 119                         goto done;
 120
 121                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 122                         dev_warn(&adapter->pdev->dev,
 123                                  "opcode %d-%d is not permitted\n",
 124                                  opcode, subsystem);
 125                 } else {
 126                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 127                                         CQE_STATUS_EXTD_MASK;
 128                         dev_err(&adapter->pdev->dev,
 129                                 "opcode %d-%d failed:status %d-%d\n",
 130                                 opcode, subsystem, compl_status, extd_status);
 131                 }
 132         }
 133 done:
 134         return compl_status;
 135 }
 136
 137 /* Link state evt is a string of bytes; no need for endian swapping */
 138 static void be_async_link_state_process(struct be_adapter *adapter,
 139                 struct be_async_event_link_state *evt)
 140 {
 141         /* When link status changes, link speed must be re-queried from FW */
 142         adapter->phy.link_speed = -1;
 143
 144         /* Ignore physical link event */
 145         if (lancer_chip(adapter) &&
 146             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 147                 return;
 148
 149         /* For the initial link status do not rely on the ASYNC event as
 150          * it may not be received in some cases.
 151          */
 152         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 153                 be_link_status_update(adapter, evt->port_link_status);
 154 }
 155
 156 /* Grp5 CoS Priority evt */
 157 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 158                 struct be_async_event_grp5_cos_priority *evt)
 159 {
 160         if (evt->valid) {
 161                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 162                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 163                 adapter->recommended_prio =
 164                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 165         }
 166 }
 167
 168 /* Grp5 QOS Speed evt */
 169 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 170                 struct be_async_event_grp5_qos_link_speed *evt)
 171 {
 172         if (evt->physical_port == adapter->port_num) {
 173                 /* qos_link_speed is in units of 10 Mbps */
 174                 adapter->phy.link_speed = evt->qos_link_speed * 10;
 175         }
 176 }
 177
 178 /*Grp5 PVID evt*/
 179 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 180                 struct be_async_event_grp5_pvid_state *evt)
 181 {
 182         if (evt->enabled)
 183                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 184         else
 185                 adapter->pvid = 0;
 186 }
 187
 188 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 189                 u32 trailer, struct be_mcc_compl *evt)
 190 {
 191         u8 event_type = 0;
 192
 193         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 194                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 195
 196         switch (event_type) {
 197         case ASYNC_EVENT_COS_PRIORITY:
 198                 be_async_grp5_cos_priority_process(adapter,
 199                 (struct be_async_event_grp5_cos_priority *)evt);
 200         break;
 201         case ASYNC_EVENT_QOS_SPEED:
 202                 be_async_grp5_qos_speed_process(adapter,
 203                 (struct be_async_event_grp5_qos_link_speed *)evt);
 204         break;
 205         case ASYNC_EVENT_PVID_STATE:
 206                 be_async_grp5_pvid_state_process(adapter,
 207                 (struct be_async_event_grp5_pvid_state *)evt);
 208         break;
 209         default:
 210                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
 211                 break;
 212         }
 213 }
 214
 215 static inline bool is_link_state_evt(u32 trailer)
 216 {
 217         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 218                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 219                                 ASYNC_EVENT_CODE_LINK_STATE;
 220 }
 221
 222 static inline bool is_grp5_evt(u32 trailer)
 223 {
 224         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 225                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 226                                 ASYNC_EVENT_CODE_GRP_5);
 227 }
 228
 229 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 230 {
 231         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 232         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 233
 234         if (be_mcc_compl_is_new(compl)) {
 235                 queue_tail_inc(mcc_cq);
 236                 return compl;
 237         }
 238         return NULL;
 239 }
 240
 241 void be_async_mcc_enable(struct be_adapter *adapter)
 242 {
 243         spin_lock_bh(&adapter->mcc_cq_lock);
 244
 245         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 246         adapter->mcc_obj.rearm_cq = true;
 247
 248         spin_unlock_bh(&adapter->mcc_cq_lock);
 249 }
 250
 251 void be_async_mcc_disable(struct be_adapter *adapter)
 252 {
 253         adapter->mcc_obj.rearm_cq = false;
 254 }
 255
 256 int be_process_mcc(struct be_adapter *adapter)
 257 {
 258         struct be_mcc_compl *compl;
 259         int num = 0, status = 0;
 260         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 261
 262         spin_lock_bh(&adapter->mcc_cq_lock);
 263         while ((compl = be_mcc_compl_get(adapter))) {
 264                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 265                         /* Interpret flags as an async trailer */
 266                         if (is_link_state_evt(compl->flags))
 267                                 be_async_link_state_process(adapter,
 268                                 (struct be_async_event_link_state *) compl);
 269                         else if (is_grp5_evt(compl->flags))
 270                                 be_async_grp5_evt_process(adapter,
 271                                 compl->flags, compl);
 272                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 273                                 status = be_mcc_compl_process(adapter, compl);
 274                                 atomic_dec(&mcc_obj->q.used);
 275                 }
 276                 be_mcc_compl_use(compl);
 277                 num++;
 278         }
 279
 280         if (num)
 281                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 282
 283         spin_unlock_bh(&adapter->mcc_cq_lock);
 284         return status;
 285 }
 286
 287 /* Wait till no more pending mcc requests are present */
 288 static int be_mcc_wait_compl(struct be_adapter *adapter)
 289 {
 290 #define mcc_timeout             120000 /* 12s timeout */
 291         int i, status = 0;
 292         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 293
 294         for (i = 0; i < mcc_timeout; i++) {
 295                 if (be_error(adapter))
 296                         return -EIO;
 297
 298                 status = be_process_mcc(adapter);
 299
 300                 if (atomic_read(&mcc_obj->q.used) == 0)
 301                         break;
 302                 udelay(100);
 303         }
 304         if (i == mcc_timeout) {
 305                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 306                 adapter->fw_timeout = true;
 307                 return -EIO;
 308         }
 309         return status;
 310 }
 311
 312 /* Notify MCC requests and wait for completion */
 313 static int be_mcc_notify_wait(struct be_adapter *adapter)
 314 {
 315         int status;
 316         struct be_mcc_wrb *wrb;
 317         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 318         u16 index = mcc_obj->q.head;
 319         struct be_cmd_resp_hdr *resp;
 320
 321         index_dec(&index, mcc_obj->q.len);
 322         wrb = queue_index_node(&mcc_obj->q, index);
 323
 324         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 325
 326         be_mcc_notify(adapter);
 327
 328         status = be_mcc_wait_compl(adapter);
 329         if (status == -EIO)
 330                 goto out;
 331
 332         status = resp->status;
 333 out:
 334         return status;
 335 }
 336
 337 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 338 {
 339         int msecs = 0;
 340         u32 ready;
 341
 342         do {
 343                 if (be_error(adapter))
 344                         return -EIO;
 345
 346                 ready = ioread32(db);
 347                 if (ready == 0xffffffff)
 348                         return -1;
 349
 350                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 351                 if (ready)
 352                         break;
 353
 354                 if (msecs > 4000) {
 355                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 356                         adapter->fw_timeout = true;
 357                         be_detect_error(adapter);
 358                         return -1;
 359                 }
 360
 361                 msleep(1);
 362                 msecs++;
 363         } while (true);
 364
 365         return 0;
 366 }
 367
 368 /*
 369  * Insert the mailbox address into the doorbell in two steps
 370  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 371  */
 372 static int be_mbox_notify_wait(struct be_adapter *adapter)
 373 {
 374         int status;
 375         u32 val = 0;
 376         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 377         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 378         struct be_mcc_mailbox *mbox = mbox_mem->va;
 379         struct be_mcc_compl *compl = &mbox->compl;
 380
 381         /* wait for ready to be set */
 382         status = be_mbox_db_ready_wait(adapter, db);
 383         if (status != 0)
 384                 return status;
 385
 386         val |= MPU_MAILBOX_DB_HI_MASK;
 387         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 388         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 389         iowrite32(val, db);
 390
 391         /* wait for ready to be set */
 392         status = be_mbox_db_ready_wait(adapter, db);
 393         if (status != 0)
 394                 return status;
 395
 396         val = 0;
 397         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 398         val |= (u32)(mbox_mem->dma >> 4) << 2;
 399         iowrite32(val, db);
 400
 401         status = be_mbox_db_ready_wait(adapter, db);
 402         if (status != 0)
 403                 return status;
 404
 405         /* A cq entry has been made now */
 406         if (be_mcc_compl_is_new(compl)) {
 407                 status = be_mcc_compl_process(adapter, &mbox->compl);
 408                 be_mcc_compl_use(compl);
 409                 if (status)
 410                         return status;
 411         } else {
 412                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 413                 return -1;
 414         }
 415         return 0;
 416 }
 417
 418 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
 419 {
 420         u32 sem;
 421
 422         if (lancer_chip(adapter))
 423                 sem  = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
 424         else
 425                 sem  = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 426
 427         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
 428         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
 429                 return -1;
 430         else
 431                 return 0;
 432 }
 433
 434 int lancer_wait_ready(struct be_adapter *adapter)
 435 {
 436 #define SLIPORT_READY_TIMEOUT 30
 437         u32 sliport_status;
 438         int status = 0, i;
 439
 440         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 441                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 442                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 443                         break;
 444
 445                 msleep(1000);
 446         }
 447
 448         if (i == SLIPORT_READY_TIMEOUT)
 449                 status = -1;
 450
 451         return status;
 452 }
 453
 454 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 455 {
 456         int status;
 457         u32 sliport_status, err, reset_needed;
 458         status = lancer_wait_ready(adapter);
 459         if (!status) {
 460                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 461                 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
 462                 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
 463                 if (err && reset_needed) {
 464                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
 465                                   adapter->db + SLIPORT_CONTROL_OFFSET);
 466
 467                         /* check adapter has corrected the error */
 468                         status = lancer_wait_ready(adapter);
 469                         sliport_status = ioread32(adapter->db +
 470                                                   SLIPORT_STATUS_OFFSET);
 471                         sliport_status &= (SLIPORT_STATUS_ERR_MASK |
 472                                                 SLIPORT_STATUS_RN_MASK);
 473                         if (status || sliport_status)
 474                                 status = -1;
 475                 } else if (err || reset_needed) {
 476                         status = -1;
 477                 }
 478         }
 479         return status;
 480 }
 481
 482 int be_fw_wait_ready(struct be_adapter *adapter)
 483 {
 484         u16 stage;
 485         int status, timeout = 0;
 486         struct device *dev = &adapter->pdev->dev;
 487
 488         if (lancer_chip(adapter)) {
 489                 status = lancer_wait_ready(adapter);
 490                 return status;
 491         }
 492
 493         do {
 494                 status = be_POST_stage_get(adapter, &stage);
 495                 if (status) {
 496                         dev_err(dev, "POST error; stage=0x%x\n", stage);
 497                         return -1;
 498                 } else if (stage != POST_STAGE_ARMFW_RDY) {
 499                         if (msleep_interruptible(2000)) {
 500                                 dev_err(dev, "Waiting for POST aborted\n");
 501                                 return -EINTR;
 502                         }
 503                         timeout += 2;
 504                 } else {
 505                         return 0;
 506                 }
 507         } while (timeout < 60);
 508
 509         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 510         return -1;
 511 }
 512
 513
 514 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 515 {
 516         return &wrb->payload.sgl[0];
 517 }
 518
 519
 520 /* Don't touch the hdr after it's prepared */
 521 /* mem will be NULL for embedded commands */
 522 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 523                                 u8 subsystem, u8 opcode, int cmd_len,
 524                                 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
 525 {
 526         struct be_sge *sge;
 527         unsigned long addr = (unsigned long)req_hdr;
 528         u64 req_addr = addr;
 529
 530         req_hdr->opcode = opcode;
 531         req_hdr->subsystem = subsystem;
 532         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 533         req_hdr->version = 0;
 534
 535         wrb->tag0 = req_addr & 0xFFFFFFFF;
 536         wrb->tag1 = upper_32_bits(req_addr);
 537
 538         wrb->payload_length = cmd_len;
 539         if (mem) {
 540                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 541                         MCC_WRB_SGE_CNT_SHIFT;
 542                 sge = nonembedded_sgl(wrb);
 543                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 544                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 545                 sge->len = cpu_to_le32(mem->size);
 546         } else
 547                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 548         be_dws_cpu_to_le(wrb, 8);
 549 }
 550
 551 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 552                         struct be_dma_mem *mem)
 553 {
 554         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 555         u64 dma = (u64)mem->dma;
 556
 557         for (i = 0; i < buf_pages; i++) {
 558                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 559                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 560                 dma += PAGE_SIZE_4K;
 561         }
 562 }
 563
 564 /* Converts interrupt delay in microseconds to multiplier value */
 565 static u32 eq_delay_to_mult(u32 usec_delay)
 566 {
 567 #define MAX_INTR_RATE                   651042
 568         const u32 round = 10;
 569         u32 multiplier;
 570
 571         if (usec_delay == 0)
 572                 multiplier = 0;
 573         else {
 574                 u32 interrupt_rate = 1000000 / usec_delay;
 575                 /* Max delay, corresponding to the lowest interrupt rate */
 576                 if (interrupt_rate == 0)
 577                         multiplier = 1023;
 578                 else {
 579                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 580                         multiplier /= interrupt_rate;
 581                         /* Round the multiplier to the closest value.*/
 582                         multiplier = (multiplier + round/2) / round;
 583                         multiplier = min(multiplier, (u32)1023);
 584                 }
 585         }
 586         return multiplier;
 587 }
 588
 589 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 590 {
 591         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 592         struct be_mcc_wrb *wrb
 593                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 594         memset(wrb, 0, sizeof(*wrb));
 595         return wrb;
 596 }
 597
 598 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 599 {
 600         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 601         struct be_mcc_wrb *wrb;
 602
 603         if (atomic_read(&mccq->used) >= mccq->len) {
 604                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
 605                 return NULL;
 606         }
 607
 608         wrb = queue_head_node(mccq);
 609         queue_head_inc(mccq);
 610         atomic_inc(&mccq->used);
 611         memset(wrb, 0, sizeof(*wrb));
 612         return wrb;
 613 }
 614
 615 /* Tell fw we're about to start firing cmds by writing a
 616  * special pattern across the wrb hdr; uses mbox
 617  */
 618 int be_cmd_fw_init(struct be_adapter *adapter)
 619 {
 620         u8 *wrb;
 621         int status;
 622
 623         if (lancer_chip(adapter))
 624                 return 0;
 625
 626         if (mutex_lock_interruptible(&adapter->mbox_lock))
 627                 return -1;
 628
 629         wrb = (u8 *)wrb_from_mbox(adapter);
 630         *wrb++ = 0xFF;
 631         *wrb++ = 0x12;
 632         *wrb++ = 0x34;
 633         *wrb++ = 0xFF;
 634         *wrb++ = 0xFF;
 635         *wrb++ = 0x56;
 636         *wrb++ = 0x78;
 637         *wrb = 0xFF;
 638
 639         status = be_mbox_notify_wait(adapter);
 640
 641         mutex_unlock(&adapter->mbox_lock);
 642         return status;
 643 }
 644
 645 /* Tell fw we're done with firing cmds by writing a
 646  * special pattern across the wrb hdr; uses mbox
 647  */
 648 int be_cmd_fw_clean(struct be_adapter *adapter)
 649 {
 650         u8 *wrb;
 651         int status;
 652
 653         if (lancer_chip(adapter))
 654                 return 0;
 655
 656         if (mutex_lock_interruptible(&adapter->mbox_lock))
 657                 return -1;
 658
 659         wrb = (u8 *)wrb_from_mbox(adapter);
 660         *wrb++ = 0xFF;
 661         *wrb++ = 0xAA;
 662         *wrb++ = 0xBB;
 663         *wrb++ = 0xFF;
 664         *wrb++ = 0xFF;
 665         *wrb++ = 0xCC;
 666         *wrb++ = 0xDD;
 667         *wrb = 0xFF;
 668
 669         status = be_mbox_notify_wait(adapter);
 670
 671         mutex_unlock(&adapter->mbox_lock);
 672         return status;
 673 }
 674
 675 int be_cmd_eq_create(struct be_adapter *adapter,
 676                 struct be_queue_info *eq, int eq_delay)
 677 {
 678         struct be_mcc_wrb *wrb;
 679         struct be_cmd_req_eq_create *req;
 680         struct be_dma_mem *q_mem = &eq->dma_mem;
 681         int status;
 682
 683         if (mutex_lock_interruptible(&adapter->mbox_lock))
 684                 return -1;
 685
 686         wrb = wrb_from_mbox(adapter);
 687         req = embedded_payload(wrb);
 688
 689         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 690                 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
 691
 692         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 693
 694         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 695         /* 4byte eqe*/
 696         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 697         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 698                         __ilog2_u32(eq->len/256));
 699         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 700                         eq_delay_to_mult(eq_delay));
 701         be_dws_cpu_to_le(req->context, sizeof(req->context));
 702
 703         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 704
 705         status = be_mbox_notify_wait(adapter);
 706         if (!status) {
 707                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 708                 eq->id = le16_to_cpu(resp->eq_id);
 709                 eq->created = true;
 710         }
 711
 712         mutex_unlock(&adapter->mbox_lock);
 713         return status;
 714 }
 715
 716 /* Use MCC */
 717 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 718                         u8 type, bool permanent, u32 if_handle, u32 pmac_id)
 719 {
 720         struct be_mcc_wrb *wrb;
 721         struct be_cmd_req_mac_query *req;
 722         int status;
 723
 724         spin_lock_bh(&adapter->mcc_lock);
 725
 726         wrb = wrb_from_mccq(adapter);
 727         if (!wrb) {
 728                 status = -EBUSY;
 729                 goto err;
 730         }
 731         req = embedded_payload(wrb);
 732
 733         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 734                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
 735         req->type = type;
 736         if (permanent) {
 737                 req->permanent = 1;
 738         } else {
 739                 req->if_id = cpu_to_le16((u16) if_handle);
 740                 req->pmac_id = cpu_to_le32(pmac_id);
 741                 req->permanent = 0;
 742         }
 743
 744         status = be_mcc_notify_wait(adapter);
 745         if (!status) {
 746                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 747                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 748         }
 749
 750 err:
 751         spin_unlock_bh(&adapter->mcc_lock);
 752         return status;
 753 }
 754
 755 /* Uses synchronous MCCQ */
 756 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 757                 u32 if_id, u32 *pmac_id, u32 domain)
 758 {
 759         struct be_mcc_wrb *wrb;
 760         struct be_cmd_req_pmac_add *req;
 761         int status;
 762
 763         spin_lock_bh(&adapter->mcc_lock);
 764
 765         wrb = wrb_from_mccq(adapter);
 766         if (!wrb) {
 767                 status = -EBUSY;
 768                 goto err;
 769         }
 770         req = embedded_payload(wrb);
 771
 772         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 773                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
 774
 775         req->hdr.domain = domain;
 776         req->if_id = cpu_to_le32(if_id);
 777         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 778
 779         status = be_mcc_notify_wait(adapter);
 780         if (!status) {
 781                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 782                 *pmac_id = le32_to_cpu(resp->pmac_id);
 783         }
 784
 785 err:
 786         spin_unlock_bh(&adapter->mcc_lock);
 787
 788          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
 789                 status = -EPERM;
 790
 791         return status;
 792 }
 793
 794 /* Uses synchronous MCCQ */
 795 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
 796 {
 797         struct be_mcc_wrb *wrb;
 798         struct be_cmd_req_pmac_del *req;
 799         int status;
 800
 801         if (pmac_id == -1)
 802                 return 0;
 803
 804         spin_lock_bh(&adapter->mcc_lock);
 805
 806         wrb = wrb_from_mccq(adapter);
 807         if (!wrb) {
 808                 status = -EBUSY;
 809                 goto err;
 810         }
 811         req = embedded_payload(wrb);
 812
 813         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 814                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
 815
 816         req->hdr.domain = dom;
 817         req->if_id = cpu_to_le32(if_id);
 818         req->pmac_id = cpu_to_le32(pmac_id);
 819
 820         status = be_mcc_notify_wait(adapter);
 821
 822 err:
 823         spin_unlock_bh(&adapter->mcc_lock);
 824         return status;
 825 }
 826
 827 /* Uses Mbox */
 828 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
 829                 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
 830 {
 831         struct be_mcc_wrb *wrb;
 832         struct be_cmd_req_cq_create *req;
 833         struct be_dma_mem *q_mem = &cq->dma_mem;
 834         void *ctxt;
 835         int status;
 836
 837         if (mutex_lock_interruptible(&adapter->mbox_lock))
 838                 return -1;
 839
 840         wrb = wrb_from_mbox(adapter);
 841         req = embedded_payload(wrb);
 842         ctxt = &req->context;
 843
 844         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 845                 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
 846
 847         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 848         if (lancer_chip(adapter)) {
 849                 req->hdr.version = 2;
 850                 req->page_size = 1; /* 1 for 4K */
 851                 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
 852                                                                 no_delay);
 853                 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
 854                                                 __ilog2_u32(cq->len/256));
 855                 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
 856                 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
 857                                                                 ctxt, 1);
 858                 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
 859                                                                 ctxt, eq->id);
 860         } else {
 861                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 862                                                                 coalesce_wm);
 863                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 864                                                                 ctxt, no_delay);
 865                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 866                                                 __ilog2_u32(cq->len/256));
 867                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 868                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 869                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 870         }
 871
 872         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 873
 874         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 875
 876         status = be_mbox_notify_wait(adapter);
 877         if (!status) {
 878                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 879                 cq->id = le16_to_cpu(resp->cq_id);
 880                 cq->created = true;
 881         }
 882
 883         mutex_unlock(&adapter->mbox_lock);
 884
 885         return status;
 886 }
 887
 888 static u32 be_encoded_q_len(int q_len)
 889 {
 890         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
 891         if (len_encoded == 16)
 892                 len_encoded = 0;
 893         return len_encoded;
 894 }
 895
 896 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
 897                         struct be_queue_info *mccq,
 898                         struct be_queue_info *cq)
 899 {
 900         struct be_mcc_wrb *wrb;
 901         struct be_cmd_req_mcc_ext_create *req;
 902         struct be_dma_mem *q_mem = &mccq->dma_mem;
 903         void *ctxt;
 904         int status;
 905
 906         if (mutex_lock_interruptible(&adapter->mbox_lock))
 907                 return -1;
 908
 909         wrb = wrb_from_mbox(adapter);
 910         req = embedded_payload(wrb);
 911         ctxt = &req->context;
 912
 913         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 914                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
 915
 916         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 917         if (lancer_chip(adapter)) {
 918                 req->hdr.version = 1;
 919                 req->cq_id = cpu_to_le16(cq->id);
 920
 921                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
 922                                                 be_encoded_q_len(mccq->len));
 923                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
 924                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
 925                                                                 ctxt, cq->id);
 926                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
 927                                                                  ctxt, 1);
 928
 929         } else {
 930                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
 931                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
 932                                                 be_encoded_q_len(mccq->len));
 933                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
 934         }
 935
 936         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
 937         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
 938         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 939
 940         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 941
 942         status = be_mbox_notify_wait(adapter);
 943         if (!status) {
 944                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 945                 mccq->id = le16_to_cpu(resp->id);
 946                 mccq->created = true;
 947         }
 948         mutex_unlock(&adapter->mbox_lock);
 949
 950         return status;
 951 }
 952
 953 int be_cmd_mccq_org_create(struct be_adapter *adapter,
 954                         struct be_queue_info *mccq,
 955                         struct be_queue_info *cq)
 956 {
 957         struct be_mcc_wrb *wrb;
 958         struct be_cmd_req_mcc_create *req;
 959         struct be_dma_mem *q_mem = &mccq->dma_mem;
 960         void *ctxt;
 961         int status;
 962
 963         if (mutex_lock_interruptible(&adapter->mbox_lock))
 964                 return -1;
 965
 966         wrb = wrb_from_mbox(adapter);
 967         req = embedded_payload(wrb);
 968         ctxt = &req->context;
 969
 970         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 971                         OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
 972
 973         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 974
 975         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
 976         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
 977                         be_encoded_q_len(mccq->len));
 978         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
 979
 980         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 981
 982         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 983
 984         status = be_mbox_notify_wait(adapter);
 985         if (!status) {
 986                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 987                 mccq->id = le16_to_cpu(resp->id);
 988                 mccq->created = true;
 989         }
 990
 991         mutex_unlock(&adapter->mbox_lock);
 992         return status;
 993 }
 994
 995 int be_cmd_mccq_create(struct be_adapter *adapter,
 996                         struct be_queue_info *mccq,
 997                         struct be_queue_info *cq)
 998 {
 999         int status;
1000
1001         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1002         if (status && !lancer_chip(adapter)) {
1003                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1004                         "or newer to avoid conflicting priorities between NIC "
1005                         "and FCoE traffic");
1006                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1007         }
1008         return status;
1009 }
1010
1011 int be_cmd_txq_create(struct be_adapter *adapter,
1012                         struct be_queue_info *txq,
1013                         struct be_queue_info *cq)
1014 {
1015         struct be_mcc_wrb *wrb;
1016         struct be_cmd_req_eth_tx_create *req;
1017         struct be_dma_mem *q_mem = &txq->dma_mem;
1018         void *ctxt;
1019         int status;
1020
1021         spin_lock_bh(&adapter->mcc_lock);
1022
1023         wrb = wrb_from_mccq(adapter);
1024         if (!wrb) {
1025                 status = -EBUSY;
1026                 goto err;
1027         }
1028
1029         req = embedded_payload(wrb);
1030         ctxt = &req->context;
1031
1032         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1033                 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
1034
1035         if (lancer_chip(adapter)) {
1036                 req->hdr.version = 1;
1037                 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
1038                                         adapter->if_handle);
1039         }
1040
1041         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1042         req->ulp_num = BE_ULP1_NUM;
1043         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1044
1045         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
1046                 be_encoded_q_len(txq->len));
1047         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
1048         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
1049
1050         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1051
1052         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1053
1054         status = be_mcc_notify_wait(adapter);
1055         if (!status) {
1056                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
1057                 txq->id = le16_to_cpu(resp->cid);
1058                 txq->created = true;
1059         }
1060
1061 err:
1062         spin_unlock_bh(&adapter->mcc_lock);
1063
1064         return status;
1065 }
1066
1067 /* Uses MCC */
1068 int be_cmd_rxq_create(struct be_adapter *adapter,
1069                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1070                 u32 if_id, u32 rss, u8 *rss_id)
1071 {
1072         struct be_mcc_wrb *wrb;
1073         struct be_cmd_req_eth_rx_create *req;
1074         struct be_dma_mem *q_mem = &rxq->dma_mem;
1075         int status;
1076
1077         spin_lock_bh(&adapter->mcc_lock);
1078
1079         wrb = wrb_from_mccq(adapter);
1080         if (!wrb) {
1081                 status = -EBUSY;
1082                 goto err;
1083         }
1084         req = embedded_payload(wrb);
1085
1086         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1087                                 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1088
1089         req->cq_id = cpu_to_le16(cq_id);
1090         req->frag_size = fls(frag_size) - 1;
1091         req->num_pages = 2;
1092         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1093         req->interface_id = cpu_to_le32(if_id);
1094         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1095         req->rss_queue = cpu_to_le32(rss);
1096
1097         status = be_mcc_notify_wait(adapter);
1098         if (!status) {
1099                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1100                 rxq->id = le16_to_cpu(resp->id);
1101                 rxq->created = true;
1102                 *rss_id = resp->rss_id;
1103         }
1104
1105 err:
1106         spin_unlock_bh(&adapter->mcc_lock);
1107         return status;
1108 }
1109
1110 /* Generic destroyer function for all types of queues
1111  * Uses Mbox
1112  */
1113 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1114                 int queue_type)
1115 {
1116         struct be_mcc_wrb *wrb;
1117         struct be_cmd_req_q_destroy *req;
1118         u8 subsys = 0, opcode = 0;
1119         int status;
1120
1121         if (mutex_lock_interruptible(&adapter->mbox_lock))
1122                 return -1;
1123
1124         wrb = wrb_from_mbox(adapter);
1125         req = embedded_payload(wrb);
1126
1127         switch (queue_type) {
1128         case QTYPE_EQ:
1129                 subsys = CMD_SUBSYSTEM_COMMON;
1130                 opcode = OPCODE_COMMON_EQ_DESTROY;
1131                 break;
1132         case QTYPE_CQ:
1133                 subsys = CMD_SUBSYSTEM_COMMON;
1134                 opcode = OPCODE_COMMON_CQ_DESTROY;
1135                 break;
1136         case QTYPE_TXQ:
1137                 subsys = CMD_SUBSYSTEM_ETH;
1138                 opcode = OPCODE_ETH_TX_DESTROY;
1139                 break;
1140         case QTYPE_RXQ:
1141                 subsys = CMD_SUBSYSTEM_ETH;
1142                 opcode = OPCODE_ETH_RX_DESTROY;
1143                 break;
1144         case QTYPE_MCCQ:
1145                 subsys = CMD_SUBSYSTEM_COMMON;
1146                 opcode = OPCODE_COMMON_MCC_DESTROY;
1147                 break;
1148         default:
1149                 BUG();
1150         }
1151
1152         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1153                                 NULL);
1154         req->id = cpu_to_le16(q->id);
1155
1156         status = be_mbox_notify_wait(adapter);
1157         if (!status)
1158                 q->created = false;
1159
1160         mutex_unlock(&adapter->mbox_lock);
1161         return status;
1162 }
1163
1164 /* Uses MCC */
1165 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1166 {
1167         struct be_mcc_wrb *wrb;
1168         struct be_cmd_req_q_destroy *req;
1169         int status;
1170
1171         spin_lock_bh(&adapter->mcc_lock);
1172
1173         wrb = wrb_from_mccq(adapter);
1174         if (!wrb) {
1175                 status = -EBUSY;
1176                 goto err;
1177         }
1178         req = embedded_payload(wrb);
1179
1180         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1181                         OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1182         req->id = cpu_to_le16(q->id);
1183
1184         status = be_mcc_notify_wait(adapter);
1185         if (!status)
1186                 q->created = false;
1187
1188 err:
1189         spin_unlock_bh(&adapter->mcc_lock);
1190         return status;
1191 }
1192
1193 /* Create an rx filtering policy configuration on an i/f
1194  * Uses MCCQ
1195  */
1196 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1197                      u32 *if_handle, u32 domain)
1198 {
1199         struct be_mcc_wrb *wrb;
1200         struct be_cmd_req_if_create *req;
1201         int status;
1202
1203         spin_lock_bh(&adapter->mcc_lock);
1204
1205         wrb = wrb_from_mccq(adapter);
1206         if (!wrb) {
1207                 status = -EBUSY;
1208                 goto err;
1209         }
1210         req = embedded_payload(wrb);
1211
1212         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1213                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1214         req->hdr.domain = domain;
1215         req->capability_flags = cpu_to_le32(cap_flags);
1216         req->enable_flags = cpu_to_le32(en_flags);
1217
1218         req->pmac_invalid = true;
1219
1220         status = be_mcc_notify_wait(adapter);
1221         if (!status) {
1222                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1223                 *if_handle = le32_to_cpu(resp->interface_id);
1224         }
1225
1226 err:
1227         spin_unlock_bh(&adapter->mcc_lock);
1228         return status;
1229 }
1230
1231 /* Uses MCCQ */
1232 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1233 {
1234         struct be_mcc_wrb *wrb;
1235         struct be_cmd_req_if_destroy *req;
1236         int status;
1237
1238         if (interface_id == -1)
1239                 return 0;
1240
1241         spin_lock_bh(&adapter->mcc_lock);
1242
1243         wrb = wrb_from_mccq(adapter);
1244         if (!wrb) {
1245                 status = -EBUSY;
1246                 goto err;
1247         }
1248         req = embedded_payload(wrb);
1249
1250         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1251                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1252         req->hdr.domain = domain;
1253         req->interface_id = cpu_to_le32(interface_id);
1254
1255         status = be_mcc_notify_wait(adapter);
1256 err:
1257         spin_unlock_bh(&adapter->mcc_lock);
1258         return status;
1259 }
1260
1261 /* Get stats is a non embedded command: the request is not embedded inside
1262  * WRB but is a separate dma memory block
1263  * Uses asynchronous MCC
1264  */
1265 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1266 {
1267         struct be_mcc_wrb *wrb;
1268         struct be_cmd_req_hdr *hdr;
1269         int status = 0;
1270
1271         spin_lock_bh(&adapter->mcc_lock);
1272
1273         wrb = wrb_from_mccq(adapter);
1274         if (!wrb) {
1275                 status = -EBUSY;
1276                 goto err;
1277         }
1278         hdr = nonemb_cmd->va;
1279
1280         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1281                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1282
1283         if (adapter->generation == BE_GEN3)
1284                 hdr->version = 1;
1285
1286         be_mcc_notify(adapter);
1287         adapter->stats_cmd_sent = true;
1288
1289 err:
1290         spin_unlock_bh(&adapter->mcc_lock);
1291         return status;
1292 }
1293
1294 /* Lancer Stats */
1295 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1296                                 struct be_dma_mem *nonemb_cmd)
1297 {
1298
1299         struct be_mcc_wrb *wrb;
1300         struct lancer_cmd_req_pport_stats *req;
1301         int status = 0;
1302
1303         spin_lock_bh(&adapter->mcc_lock);
1304
1305         wrb = wrb_from_mccq(adapter);
1306         if (!wrb) {
1307                 status = -EBUSY;
1308                 goto err;
1309         }
1310         req = nonemb_cmd->va;
1311
1312         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1313                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1314                         nonemb_cmd);
1315
1316         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1317         req->cmd_params.params.reset_stats = 0;
1318
1319         be_mcc_notify(adapter);
1320         adapter->stats_cmd_sent = true;
1321
1322 err:
1323         spin_unlock_bh(&adapter->mcc_lock);
1324         return status;
1325 }
1326
1327 /* Uses synchronous mcc */
1328 int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed,
1329                              u16 *link_speed, u8 *link_status, u32 dom)
1330 {
1331         struct be_mcc_wrb *wrb;
1332         struct be_cmd_req_link_status *req;
1333         int status;
1334
1335         spin_lock_bh(&adapter->mcc_lock);
1336
1337         if (link_status)
1338                 *link_status = LINK_DOWN;
1339
1340         wrb = wrb_from_mccq(adapter);
1341         if (!wrb) {
1342                 status = -EBUSY;
1343                 goto err;
1344         }
1345         req = embedded_payload(wrb);
1346
1347         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1348                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1349
1350         if (adapter->generation == BE_GEN3 || lancer_chip(adapter))
1351                 req->hdr.version = 1;
1352
1353         req->hdr.domain = dom;
1354
1355         status = be_mcc_notify_wait(adapter);
1356         if (!status) {
1357                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1358                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1359                         if (link_speed)
1360                                 *link_speed = le16_to_cpu(resp->link_speed);
1361                         if (mac_speed)
1362                                 *mac_speed = resp->mac_speed;
1363                 }
1364                 if (link_status)
1365                         *link_status = resp->logical_link_status;
1366         }
1367
1368 err:
1369         spin_unlock_bh(&adapter->mcc_lock);
1370         return status;
1371 }
1372
1373 /* Uses synchronous mcc */
1374 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1375 {
1376         struct be_mcc_wrb *wrb;
1377         struct be_cmd_req_get_cntl_addnl_attribs *req;
1378         int status;
1379
1380         spin_lock_bh(&adapter->mcc_lock);
1381
1382         wrb = wrb_from_mccq(adapter);
1383         if (!wrb) {
1384                 status = -EBUSY;
1385                 goto err;
1386         }
1387         req = embedded_payload(wrb);
1388
1389         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1390                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1391                 wrb, NULL);
1392
1393         be_mcc_notify(adapter);
1394
1395 err:
1396         spin_unlock_bh(&adapter->mcc_lock);
1397         return status;
1398 }
1399
1400 /* Uses synchronous mcc */
1401 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1402 {
1403         struct be_mcc_wrb *wrb;
1404         struct be_cmd_req_get_fat *req;
1405         int status;
1406
1407         spin_lock_bh(&adapter->mcc_lock);
1408
1409         wrb = wrb_from_mccq(adapter);
1410         if (!wrb) {
1411                 status = -EBUSY;
1412                 goto err;
1413         }
1414         req = embedded_payload(wrb);
1415
1416         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1417                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1418         req->fat_operation = cpu_to_le32(QUERY_FAT);
1419         status = be_mcc_notify_wait(adapter);
1420         if (!status) {
1421                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1422                 if (log_size && resp->log_size)
1423                         *log_size = le32_to_cpu(resp->log_size) -
1424                                         sizeof(u32);
1425         }
1426 err:
1427         spin_unlock_bh(&adapter->mcc_lock);
1428         return status;
1429 }
1430
1431 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1432 {
1433         struct be_dma_mem get_fat_cmd;
1434         struct be_mcc_wrb *wrb;
1435         struct be_cmd_req_get_fat *req;
1436         u32 offset = 0, total_size, buf_size,
1437                                 log_offset = sizeof(u32), payload_len;
1438         int status;
1439
1440         if (buf_len == 0)
1441                 return;
1442
1443         total_size = buf_len;
1444
1445         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1446         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1447                         get_fat_cmd.size,
1448                         &get_fat_cmd.dma);
1449         if (!get_fat_cmd.va) {
1450                 status = -ENOMEM;
1451                 dev_err(&adapter->pdev->dev,
1452                 "Memory allocation failure while retrieving FAT data\n");
1453                 return;
1454         }
1455
1456         spin_lock_bh(&adapter->mcc_lock);
1457
1458         while (total_size) {
1459                 buf_size = min(total_size, (u32)60*1024);
1460                 total_size -= buf_size;
1461
1462                 wrb = wrb_from_mccq(adapter);
1463                 if (!wrb) {
1464                         status = -EBUSY;
1465                         goto err;
1466                 }
1467                 req = get_fat_cmd.va;
1468
1469                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1470                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1471                                 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1472                                 &get_fat_cmd);
1473
1474                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1475                 req->read_log_offset = cpu_to_le32(log_offset);
1476                 req->read_log_length = cpu_to_le32(buf_size);
1477                 req->data_buffer_size = cpu_to_le32(buf_size);
1478
1479                 status = be_mcc_notify_wait(adapter);
1480                 if (!status) {
1481                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1482                         memcpy(buf + offset,
1483                                 resp->data_buffer,
1484                                 le32_to_cpu(resp->read_log_length));
1485                 } else {
1486                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1487                         goto err;
1488                 }
1489                 offset += buf_size;
1490                 log_offset += buf_size;
1491         }
1492 err:
1493         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1494                         get_fat_cmd.va,
1495                         get_fat_cmd.dma);
1496         spin_unlock_bh(&adapter->mcc_lock);
1497 }
1498
1499 /* Uses synchronous mcc */
1500 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1501                         char *fw_on_flash)
1502 {
1503         struct be_mcc_wrb *wrb;
1504         struct be_cmd_req_get_fw_version *req;
1505         int status;
1506
1507         spin_lock_bh(&adapter->mcc_lock);
1508
1509         wrb = wrb_from_mccq(adapter);
1510         if (!wrb) {
1511                 status = -EBUSY;
1512                 goto err;
1513         }
1514
1515         req = embedded_payload(wrb);
1516
1517         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1518                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1519         status = be_mcc_notify_wait(adapter);
1520         if (!status) {
1521                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1522                 strcpy(fw_ver, resp->firmware_version_string);
1523                 if (fw_on_flash)
1524                         strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1525         }
1526 err:
1527         spin_unlock_bh(&adapter->mcc_lock);
1528         return status;
1529 }
1530
1531 /* set the EQ delay interval of an EQ to specified value
1532  * Uses async mcc
1533  */
1534 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1535 {
1536         struct be_mcc_wrb *wrb;
1537         struct be_cmd_req_modify_eq_delay *req;
1538         int status = 0;
1539
1540         spin_lock_bh(&adapter->mcc_lock);
1541
1542         wrb = wrb_from_mccq(adapter);
1543         if (!wrb) {
1544                 status = -EBUSY;
1545                 goto err;
1546         }
1547         req = embedded_payload(wrb);
1548
1549         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1550                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1551
1552         req->num_eq = cpu_to_le32(1);
1553         req->delay[0].eq_id = cpu_to_le32(eq_id);
1554         req->delay[0].phase = 0;
1555         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1556
1557         be_mcc_notify(adapter);
1558
1559 err:
1560         spin_unlock_bh(&adapter->mcc_lock);
1561         return status;
1562 }
1563
1564 /* Uses sycnhronous mcc */
1565 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1566                         u32 num, bool untagged, bool promiscuous)
1567 {
1568         struct be_mcc_wrb *wrb;
1569         struct be_cmd_req_vlan_config *req;
1570         int status;
1571
1572         spin_lock_bh(&adapter->mcc_lock);
1573
1574         wrb = wrb_from_mccq(adapter);
1575         if (!wrb) {
1576                 status = -EBUSY;
1577                 goto err;
1578         }
1579         req = embedded_payload(wrb);
1580
1581         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1582                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1583
1584         req->interface_id = if_id;
1585         req->promiscuous = promiscuous;
1586         req->untagged = untagged;
1587         req->num_vlan = num;
1588         if (!promiscuous) {
1589                 memcpy(req->normal_vlan, vtag_array,
1590                         req->num_vlan * sizeof(vtag_array[0]));
1591         }
1592
1593         status = be_mcc_notify_wait(adapter);
1594
1595 err:
1596         spin_unlock_bh(&adapter->mcc_lock);
1597         return status;
1598 }
1599
1600 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1601 {
1602         struct be_mcc_wrb *wrb;
1603         struct be_dma_mem *mem = &adapter->rx_filter;
1604         struct be_cmd_req_rx_filter *req = mem->va;
1605         int status;
1606
1607         spin_lock_bh(&adapter->mcc_lock);
1608
1609         wrb = wrb_from_mccq(adapter);
1610         if (!wrb) {
1611                 status = -EBUSY;
1612                 goto err;
1613         }
1614         memset(req, 0, sizeof(*req));
1615         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1616                                 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1617                                 wrb, mem);
1618
1619         req->if_id = cpu_to_le32(adapter->if_handle);
1620         if (flags & IFF_PROMISC) {
1621                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1622                                         BE_IF_FLAGS_VLAN_PROMISCUOUS);
1623                 if (value == ON)
1624                         req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1625                                                 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1626         } else if (flags & IFF_ALLMULTI) {
1627                 req->if_flags_mask = req->if_flags =
1628                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1629         } else {
1630                 struct netdev_hw_addr *ha;
1631                 int i = 0;
1632
1633                 req->if_flags_mask = req->if_flags =
1634                                 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1635
1636                 /* Reset mcast promisc mode if already set by setting mask
1637                  * and not setting flags field
1638                  */
1639                 if (!lancer_chip(adapter) || be_physfn(adapter))
1640                         req->if_flags_mask |=
1641                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1642
1643                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1644                 netdev_for_each_mc_addr(ha, adapter->netdev)
1645                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1646         }
1647
1648         status = be_mcc_notify_wait(adapter);
1649 err:
1650         spin_unlock_bh(&adapter->mcc_lock);
1651         return status;
1652 }
1653
1654 /* Uses synchrounous mcc */
1655 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1656 {
1657         struct be_mcc_wrb *wrb;
1658         struct be_cmd_req_set_flow_control *req;
1659         int status;
1660
1661         spin_lock_bh(&adapter->mcc_lock);
1662
1663         wrb = wrb_from_mccq(adapter);
1664         if (!wrb) {
1665                 status = -EBUSY;
1666                 goto err;
1667         }
1668         req = embedded_payload(wrb);
1669
1670         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1671                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1672
1673         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1674         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1675
1676         status = be_mcc_notify_wait(adapter);
1677
1678 err:
1679         spin_unlock_bh(&adapter->mcc_lock);
1680         return status;
1681 }
1682
1683 /* Uses sycn mcc */
1684 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1685 {
1686         struct be_mcc_wrb *wrb;
1687         struct be_cmd_req_get_flow_control *req;
1688         int status;
1689
1690         spin_lock_bh(&adapter->mcc_lock);
1691
1692         wrb = wrb_from_mccq(adapter);
1693         if (!wrb) {
1694                 status = -EBUSY;
1695                 goto err;
1696         }
1697         req = embedded_payload(wrb);
1698
1699         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1700                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1701
1702         status = be_mcc_notify_wait(adapter);
1703         if (!status) {
1704                 struct be_cmd_resp_get_flow_control *resp =
1705                                                 embedded_payload(wrb);
1706                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1707                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1708         }
1709
1710 err:
1711         spin_unlock_bh(&adapter->mcc_lock);
1712         return status;
1713 }
1714
1715 /* Uses mbox */
1716 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1717                 u32 *mode, u32 *caps)
1718 {
1719         struct be_mcc_wrb *wrb;
1720         struct be_cmd_req_query_fw_cfg *req;
1721         int status;
1722
1723         if (mutex_lock_interruptible(&adapter->mbox_lock))
1724                 return -1;
1725
1726         wrb = wrb_from_mbox(adapter);
1727         req = embedded_payload(wrb);
1728
1729         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1730                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1731
1732         status = be_mbox_notify_wait(adapter);
1733         if (!status) {
1734                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1735                 *port_num = le32_to_cpu(resp->phys_port);
1736                 *mode = le32_to_cpu(resp->function_mode);
1737                 *caps = le32_to_cpu(resp->function_caps);
1738         }
1739
1740         mutex_unlock(&adapter->mbox_lock);
1741         return status;
1742 }
1743
1744 /* Uses mbox */
1745 int be_cmd_reset_function(struct be_adapter *adapter)
1746 {
1747         struct be_mcc_wrb *wrb;
1748         struct be_cmd_req_hdr *req;
1749         int status;
1750
1751         if (lancer_chip(adapter)) {
1752                 status = lancer_wait_ready(adapter);
1753                 if (!status) {
1754                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
1755                                   adapter->db + SLIPORT_CONTROL_OFFSET);
1756                         status = lancer_test_and_set_rdy_state(adapter);
1757                 }
1758                 if (status) {
1759                         dev_err(&adapter->pdev->dev,
1760                                 "Adapter in non recoverable error\n");
1761                 }
1762                 return status;
1763         }
1764
1765         if (mutex_lock_interruptible(&adapter->mbox_lock))
1766                 return -1;
1767
1768         wrb = wrb_from_mbox(adapter);
1769         req = embedded_payload(wrb);
1770
1771         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1772                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1773
1774         status = be_mbox_notify_wait(adapter);
1775
1776         mutex_unlock(&adapter->mbox_lock);
1777         return status;
1778 }
1779
1780 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1781 {
1782         struct be_mcc_wrb *wrb;
1783         struct be_cmd_req_rss_config *req;
1784         u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1785                         0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1786                         0x3ea83c02, 0x4a110304};
1787         int status;
1788
1789         if (mutex_lock_interruptible(&adapter->mbox_lock))
1790                 return -1;
1791
1792         wrb = wrb_from_mbox(adapter);
1793         req = embedded_payload(wrb);
1794
1795         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1796                 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1797
1798         req->if_id = cpu_to_le32(adapter->if_handle);
1799         req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4 |
1800                                       RSS_ENABLE_TCP_IPV6 | RSS_ENABLE_IPV6);
1801
1802         if (lancer_chip(adapter) || skyhawk_chip(adapter)) {
1803                 req->hdr.version = 1;
1804                 req->enable_rss |= cpu_to_le16(RSS_ENABLE_UDP_IPV4 |
1805                                                RSS_ENABLE_UDP_IPV6);
1806         }
1807
1808         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1809         memcpy(req->cpu_table, rsstable, table_size);
1810         memcpy(req->hash, myhash, sizeof(myhash));
1811         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1812
1813         status = be_mbox_notify_wait(adapter);
1814
1815         mutex_unlock(&adapter->mbox_lock);
1816         return status;
1817 }
1818
1819 /* Uses sync mcc */
1820 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1821                         u8 bcn, u8 sts, u8 state)
1822 {
1823         struct be_mcc_wrb *wrb;
1824         struct be_cmd_req_enable_disable_beacon *req;
1825         int status;
1826
1827         spin_lock_bh(&adapter->mcc_lock);
1828
1829         wrb = wrb_from_mccq(adapter);
1830         if (!wrb) {
1831                 status = -EBUSY;
1832                 goto err;
1833         }
1834         req = embedded_payload(wrb);
1835
1836         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1837                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
1838
1839         req->port_num = port_num;
1840         req->beacon_state = state;
1841         req->beacon_duration = bcn;
1842         req->status_duration = sts;
1843
1844         status = be_mcc_notify_wait(adapter);
1845
1846 err:
1847         spin_unlock_bh(&adapter->mcc_lock);
1848         return status;
1849 }
1850
1851 /* Uses sync mcc */
1852 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1853 {
1854         struct be_mcc_wrb *wrb;
1855         struct be_cmd_req_get_beacon_state *req;
1856         int status;
1857
1858         spin_lock_bh(&adapter->mcc_lock);
1859
1860         wrb = wrb_from_mccq(adapter);
1861         if (!wrb) {
1862                 status = -EBUSY;
1863                 goto err;
1864         }
1865         req = embedded_payload(wrb);
1866
1867         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1868                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
1869
1870         req->port_num = port_num;
1871
1872         status = be_mcc_notify_wait(adapter);
1873         if (!status) {
1874                 struct be_cmd_resp_get_beacon_state *resp =
1875                                                 embedded_payload(wrb);
1876                 *state = resp->beacon_state;
1877         }
1878
1879 err:
1880         spin_unlock_bh(&adapter->mcc_lock);
1881         return status;
1882 }
1883
1884 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1885                             u32 data_size, u32 data_offset,
1886                             const char *obj_name, u32 *data_written,
1887                             u8 *change_status, u8 *addn_status)
1888 {
1889         struct be_mcc_wrb *wrb;
1890         struct lancer_cmd_req_write_object *req;
1891         struct lancer_cmd_resp_write_object *resp;
1892         void *ctxt = NULL;
1893         int status;
1894
1895         spin_lock_bh(&adapter->mcc_lock);
1896         adapter->flash_status = 0;
1897
1898         wrb = wrb_from_mccq(adapter);
1899         if (!wrb) {
1900                 status = -EBUSY;
1901                 goto err_unlock;
1902         }
1903
1904         req = embedded_payload(wrb);
1905
1906         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1907                                 OPCODE_COMMON_WRITE_OBJECT,
1908                                 sizeof(struct lancer_cmd_req_write_object), wrb,
1909                                 NULL);
1910
1911         ctxt = &req->context;
1912         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1913                         write_length, ctxt, data_size);
1914
1915         if (data_size == 0)
1916                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1917                                 eof, ctxt, 1);
1918         else
1919                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1920                                 eof, ctxt, 0);
1921
1922         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1923         req->write_offset = cpu_to_le32(data_offset);
1924         strcpy(req->object_name, obj_name);
1925         req->descriptor_count = cpu_to_le32(1);
1926         req->buf_len = cpu_to_le32(data_size);
1927         req->addr_low = cpu_to_le32((cmd->dma +
1928                                 sizeof(struct lancer_cmd_req_write_object))
1929                                 & 0xFFFFFFFF);
1930         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1931                                 sizeof(struct lancer_cmd_req_write_object)));
1932
1933         be_mcc_notify(adapter);
1934         spin_unlock_bh(&adapter->mcc_lock);
1935
1936         if (!wait_for_completion_timeout(&adapter->flash_compl,
1937                                          msecs_to_jiffies(30000)))
1938                 status = -1;
1939         else
1940                 status = adapter->flash_status;
1941
1942         resp = embedded_payload(wrb);
1943         if (!status) {
1944                 *data_written = le32_to_cpu(resp->actual_write_len);
1945                 *change_status = resp->change_status;
1946         } else {
1947                 *addn_status = resp->additional_status;
1948         }
1949
1950         return status;
1951
1952 err_unlock:
1953         spin_unlock_bh(&adapter->mcc_lock);
1954         return status;
1955 }
1956
1957 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1958                 u32 data_size, u32 data_offset, const char *obj_name,
1959                 u32 *data_read, u32 *eof, u8 *addn_status)
1960 {
1961         struct be_mcc_wrb *wrb;
1962         struct lancer_cmd_req_read_object *req;
1963         struct lancer_cmd_resp_read_object *resp;
1964         int status;
1965
1966         spin_lock_bh(&adapter->mcc_lock);
1967
1968         wrb = wrb_from_mccq(adapter);
1969         if (!wrb) {
1970                 status = -EBUSY;
1971                 goto err_unlock;
1972         }
1973
1974         req = embedded_payload(wrb);
1975
1976         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1977                         OPCODE_COMMON_READ_OBJECT,
1978                         sizeof(struct lancer_cmd_req_read_object), wrb,
1979                         NULL);
1980
1981         req->desired_read_len = cpu_to_le32(data_size);
1982         req->read_offset = cpu_to_le32(data_offset);
1983         strcpy(req->object_name, obj_name);
1984         req->descriptor_count = cpu_to_le32(1);
1985         req->buf_len = cpu_to_le32(data_size);
1986         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
1987         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
1988
1989         status = be_mcc_notify_wait(adapter);
1990
1991         resp = embedded_payload(wrb);
1992         if (!status) {
1993                 *data_read = le32_to_cpu(resp->actual_read_len);
1994                 *eof = le32_to_cpu(resp->eof);
1995         } else {
1996                 *addn_status = resp->additional_status;
1997         }
1998
1999 err_unlock:
2000         spin_unlock_bh(&adapter->mcc_lock);
2001         return status;
2002 }
2003
2004 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2005                         u32 flash_type, u32 flash_opcode, u32 buf_size)
2006 {
2007         struct be_mcc_wrb *wrb;
2008         struct be_cmd_write_flashrom *req;
2009         int status;
2010
2011         spin_lock_bh(&adapter->mcc_lock);
2012         adapter->flash_status = 0;
2013
2014         wrb = wrb_from_mccq(adapter);
2015         if (!wrb) {
2016                 status = -EBUSY;
2017                 goto err_unlock;
2018         }
2019         req = cmd->va;
2020
2021         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2022                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
2023
2024         req->params.op_type = cpu_to_le32(flash_type);
2025         req->params.op_code = cpu_to_le32(flash_opcode);
2026         req->params.data_buf_size = cpu_to_le32(buf_size);
2027
2028         be_mcc_notify(adapter);
2029         spin_unlock_bh(&adapter->mcc_lock);
2030
2031         if (!wait_for_completion_timeout(&adapter->flash_compl,
2032                         msecs_to_jiffies(40000)))
2033                 status = -1;
2034         else
2035                 status = adapter->flash_status;
2036
2037         return status;
2038
2039 err_unlock:
2040         spin_unlock_bh(&adapter->mcc_lock);
2041         return status;
2042 }
2043
2044 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2045                          int offset)
2046 {
2047         struct be_mcc_wrb *wrb;
2048         struct be_cmd_write_flashrom *req;
2049         int status;
2050
2051         spin_lock_bh(&adapter->mcc_lock);
2052
2053         wrb = wrb_from_mccq(adapter);
2054         if (!wrb) {
2055                 status = -EBUSY;
2056                 goto err;
2057         }
2058         req = embedded_payload(wrb);
2059
2060         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2061                 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4, wrb, NULL);
2062
2063         req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2064         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2065         req->params.offset = cpu_to_le32(offset);
2066         req->params.data_buf_size = cpu_to_le32(0x4);
2067
2068         status = be_mcc_notify_wait(adapter);
2069         if (!status)
2070                 memcpy(flashed_crc, req->params.data_buf, 4);
2071
2072 err:
2073         spin_unlock_bh(&adapter->mcc_lock);
2074         return status;
2075 }
2076
2077 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2078                                 struct be_dma_mem *nonemb_cmd)
2079 {
2080         struct be_mcc_wrb *wrb;
2081         struct be_cmd_req_acpi_wol_magic_config *req;
2082         int status;
2083
2084         spin_lock_bh(&adapter->mcc_lock);
2085
2086         wrb = wrb_from_mccq(adapter);
2087         if (!wrb) {
2088                 status = -EBUSY;
2089                 goto err;
2090         }
2091         req = nonemb_cmd->va;
2092
2093         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2094                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2095                 nonemb_cmd);
2096         memcpy(req->magic_mac, mac, ETH_ALEN);
2097
2098         status = be_mcc_notify_wait(adapter);
2099
2100 err:
2101         spin_unlock_bh(&adapter->mcc_lock);
2102         return status;
2103 }
2104
2105 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2106                         u8 loopback_type, u8 enable)
2107 {
2108         struct be_mcc_wrb *wrb;
2109         struct be_cmd_req_set_lmode *req;
2110         int status;
2111
2112         spin_lock_bh(&adapter->mcc_lock);
2113
2114         wrb = wrb_from_mccq(adapter);
2115         if (!wrb) {
2116                 status = -EBUSY;
2117                 goto err;
2118         }
2119
2120         req = embedded_payload(wrb);
2121
2122         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2123                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2124                         NULL);
2125
2126         req->src_port = port_num;
2127         req->dest_port = port_num;
2128         req->loopback_type = loopback_type;
2129         req->loopback_state = enable;
2130
2131         status = be_mcc_notify_wait(adapter);
2132 err:
2133         spin_unlock_bh(&adapter->mcc_lock);
2134         return status;
2135 }
2136
2137 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2138                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2139 {
2140         struct be_mcc_wrb *wrb;
2141         struct be_cmd_req_loopback_test *req;
2142         int status;
2143
2144         spin_lock_bh(&adapter->mcc_lock);
2145
2146         wrb = wrb_from_mccq(adapter);
2147         if (!wrb) {
2148                 status = -EBUSY;
2149                 goto err;
2150         }
2151
2152         req = embedded_payload(wrb);
2153
2154         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2155                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2156         req->hdr.timeout = cpu_to_le32(4);
2157
2158         req->pattern = cpu_to_le64(pattern);
2159         req->src_port = cpu_to_le32(port_num);
2160         req->dest_port = cpu_to_le32(port_num);
2161         req->pkt_size = cpu_to_le32(pkt_size);
2162         req->num_pkts = cpu_to_le32(num_pkts);
2163         req->loopback_type = cpu_to_le32(loopback_type);
2164
2165         status = be_mcc_notify_wait(adapter);
2166         if (!status) {
2167                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2168                 status = le32_to_cpu(resp->status);
2169         }
2170
2171 err:
2172         spin_unlock_bh(&adapter->mcc_lock);
2173         return status;
2174 }
2175
2176 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2177                                 u32 byte_cnt, struct be_dma_mem *cmd)
2178 {
2179         struct be_mcc_wrb *wrb;
2180         struct be_cmd_req_ddrdma_test *req;
2181         int status;
2182         int i, j = 0;
2183
2184         spin_lock_bh(&adapter->mcc_lock);
2185
2186         wrb = wrb_from_mccq(adapter);
2187         if (!wrb) {
2188                 status = -EBUSY;
2189                 goto err;
2190         }
2191         req = cmd->va;
2192         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2193                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2194
2195         req->pattern = cpu_to_le64(pattern);
2196         req->byte_count = cpu_to_le32(byte_cnt);
2197         for (i = 0; i < byte_cnt; i++) {
2198                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2199                 j++;
2200                 if (j > 7)
2201                         j = 0;
2202         }
2203
2204         status = be_mcc_notify_wait(adapter);
2205
2206         if (!status) {
2207                 struct be_cmd_resp_ddrdma_test *resp;
2208                 resp = cmd->va;
2209                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2210                                 resp->snd_err) {
2211                         status = -1;
2212                 }
2213         }
2214
2215 err:
2216         spin_unlock_bh(&adapter->mcc_lock);
2217         return status;
2218 }
2219
2220 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2221                                 struct be_dma_mem *nonemb_cmd)
2222 {
2223         struct be_mcc_wrb *wrb;
2224         struct be_cmd_req_seeprom_read *req;
2225         struct be_sge *sge;
2226         int status;
2227
2228         spin_lock_bh(&adapter->mcc_lock);
2229
2230         wrb = wrb_from_mccq(adapter);
2231         if (!wrb) {
2232                 status = -EBUSY;
2233                 goto err;
2234         }
2235         req = nonemb_cmd->va;
2236         sge = nonembedded_sgl(wrb);
2237
2238         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2239                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2240                         nonemb_cmd);
2241
2242         status = be_mcc_notify_wait(adapter);
2243
2244 err:
2245         spin_unlock_bh(&adapter->mcc_lock);
2246         return status;
2247 }
2248
2249 int be_cmd_get_phy_info(struct be_adapter *adapter)
2250 {
2251         struct be_mcc_wrb *wrb;
2252         struct be_cmd_req_get_phy_info *req;
2253         struct be_dma_mem cmd;
2254         int status;
2255
2256         spin_lock_bh(&adapter->mcc_lock);
2257
2258         wrb = wrb_from_mccq(adapter);
2259         if (!wrb) {
2260                 status = -EBUSY;
2261                 goto err;
2262         }
2263         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2264         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2265                                         &cmd.dma);
2266         if (!cmd.va) {
2267                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2268                 status = -ENOMEM;
2269                 goto err;
2270         }
2271
2272         req = cmd.va;
2273
2274         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2275                         OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2276                         wrb, &cmd);
2277
2278         status = be_mcc_notify_wait(adapter);
2279         if (!status) {
2280                 struct be_phy_info *resp_phy_info =
2281                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2282                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2283                 adapter->phy.interface_type =
2284                         le16_to_cpu(resp_phy_info->interface_type);
2285                 adapter->phy.auto_speeds_supported =
2286                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
2287                 adapter->phy.fixed_speeds_supported =
2288                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2289                 adapter->phy.misc_params =
2290                         le32_to_cpu(resp_phy_info->misc_params);
2291         }
2292         pci_free_consistent(adapter->pdev, cmd.size,
2293                                 cmd.va, cmd.dma);
2294 err:
2295         spin_unlock_bh(&adapter->mcc_lock);
2296         return status;
2297 }
2298
2299 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2300 {
2301         struct be_mcc_wrb *wrb;
2302         struct be_cmd_req_set_qos *req;
2303         int status;
2304
2305         spin_lock_bh(&adapter->mcc_lock);
2306
2307         wrb = wrb_from_mccq(adapter);
2308         if (!wrb) {
2309                 status = -EBUSY;
2310                 goto err;
2311         }
2312
2313         req = embedded_payload(wrb);
2314
2315         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2316                         OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2317
2318         req->hdr.domain = domain;
2319         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2320         req->max_bps_nic = cpu_to_le32(bps);
2321
2322         status = be_mcc_notify_wait(adapter);
2323
2324 err:
2325         spin_unlock_bh(&adapter->mcc_lock);
2326         return status;
2327 }
2328
2329 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2330 {
2331         struct be_mcc_wrb *wrb;
2332         struct be_cmd_req_cntl_attribs *req;
2333         struct be_cmd_resp_cntl_attribs *resp;
2334         int status;
2335         int payload_len = max(sizeof(*req), sizeof(*resp));
2336         struct mgmt_controller_attrib *attribs;
2337         struct be_dma_mem attribs_cmd;
2338
2339         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2340         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2341         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2342                                                 &attribs_cmd.dma);
2343         if (!attribs_cmd.va) {
2344                 dev_err(&adapter->pdev->dev,
2345                                 "Memory allocation failure\n");
2346                 return -ENOMEM;
2347         }
2348
2349         if (mutex_lock_interruptible(&adapter->mbox_lock))
2350                 return -1;
2351
2352         wrb = wrb_from_mbox(adapter);
2353         if (!wrb) {
2354                 status = -EBUSY;
2355                 goto err;
2356         }
2357         req = attribs_cmd.va;
2358
2359         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2360                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2361                         &attribs_cmd);
2362
2363         status = be_mbox_notify_wait(adapter);
2364         if (!status) {
2365                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2366                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2367         }
2368
2369 err:
2370         mutex_unlock(&adapter->mbox_lock);
2371         pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2372                                         attribs_cmd.dma);
2373         return status;
2374 }
2375
2376 /* Uses mbox */
2377 int be_cmd_req_native_mode(struct be_adapter *adapter)
2378 {
2379         struct be_mcc_wrb *wrb;
2380         struct be_cmd_req_set_func_cap *req;
2381         int status;
2382
2383         if (mutex_lock_interruptible(&adapter->mbox_lock))
2384                 return -1;
2385
2386         wrb = wrb_from_mbox(adapter);
2387         if (!wrb) {
2388                 status = -EBUSY;
2389                 goto err;
2390         }
2391
2392         req = embedded_payload(wrb);
2393
2394         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2395                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2396
2397         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2398                                 CAPABILITY_BE3_NATIVE_ERX_API);
2399         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2400
2401         status = be_mbox_notify_wait(adapter);
2402         if (!status) {
2403                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2404                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2405                                         CAPABILITY_BE3_NATIVE_ERX_API;
2406         }
2407 err:
2408         mutex_unlock(&adapter->mbox_lock);
2409         return status;
2410 }
2411
2412 /* Uses synchronous MCCQ */
2413 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2414                              bool *pmac_id_active, u32 *pmac_id, u8 domain)
2415 {
2416         struct be_mcc_wrb *wrb;
2417         struct be_cmd_req_get_mac_list *req;
2418         int status;
2419         int mac_count;
2420         struct be_dma_mem get_mac_list_cmd;
2421         int i;
2422
2423         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2424         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2425         get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2426                         get_mac_list_cmd.size,
2427                         &get_mac_list_cmd.dma);
2428
2429         if (!get_mac_list_cmd.va) {
2430                 dev_err(&adapter->pdev->dev,
2431                                 "Memory allocation failure during GET_MAC_LIST\n");
2432                 return -ENOMEM;
2433         }
2434
2435         spin_lock_bh(&adapter->mcc_lock);
2436
2437         wrb = wrb_from_mccq(adapter);
2438         if (!wrb) {
2439                 status = -EBUSY;
2440                 goto out;
2441         }
2442
2443         req = get_mac_list_cmd.va;
2444
2445         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2446                                 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req),
2447                                 wrb, &get_mac_list_cmd);
2448
2449         req->hdr.domain = domain;
2450         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2451         req->perm_override = 1;
2452
2453         status = be_mcc_notify_wait(adapter);
2454         if (!status) {
2455                 struct be_cmd_resp_get_mac_list *resp =
2456                                                 get_mac_list_cmd.va;
2457                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2458                 /* Mac list returned could contain one or more active mac_ids
2459                  * or one or more true or pseudo permanant mac addresses.
2460                  * If an active mac_id is present, return first active mac_id
2461                  * found.
2462                  */
2463                 for (i = 0; i < mac_count; i++) {
2464                         struct get_list_macaddr *mac_entry;
2465                         u16 mac_addr_size;
2466                         u32 mac_id;
2467
2468                         mac_entry = &resp->macaddr_list[i];
2469                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2470                         /* mac_id is a 32 bit value and mac_addr size
2471                          * is 6 bytes
2472                          */
2473                         if (mac_addr_size == sizeof(u32)) {
2474                                 *pmac_id_active = true;
2475                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2476                                 *pmac_id = le32_to_cpu(mac_id);
2477                                 goto out;
2478                         }
2479                 }
2480                 /* If no active mac_id found, return first mac addr */
2481                 *pmac_id_active = false;
2482                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2483                                                                 ETH_ALEN);
2484         }
2485
2486 out:
2487         spin_unlock_bh(&adapter->mcc_lock);
2488         pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2489                         get_mac_list_cmd.va, get_mac_list_cmd.dma);
2490         return status;
2491 }
2492
2493 /* Uses synchronous MCCQ */
2494 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2495                         u8 mac_count, u32 domain)
2496 {
2497         struct be_mcc_wrb *wrb;
2498         struct be_cmd_req_set_mac_list *req;
2499         int status;
2500         struct be_dma_mem cmd;
2501
2502         memset(&cmd, 0, sizeof(struct be_dma_mem));
2503         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2504         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2505                         &cmd.dma, GFP_KERNEL);
2506         if (!cmd.va) {
2507                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2508                 return -ENOMEM;
2509         }
2510
2511         spin_lock_bh(&adapter->mcc_lock);
2512
2513         wrb = wrb_from_mccq(adapter);
2514         if (!wrb) {
2515                 status = -EBUSY;
2516                 goto err;
2517         }
2518
2519         req = cmd.va;
2520         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2521                                 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2522                                 wrb, &cmd);
2523
2524         req->hdr.domain = domain;
2525         req->mac_count = mac_count;
2526         if (mac_count)
2527                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2528
2529         status = be_mcc_notify_wait(adapter);
2530
2531 err:
2532         dma_free_coherent(&adapter->pdev->dev, cmd.size,
2533                                 cmd.va, cmd.dma);
2534         spin_unlock_bh(&adapter->mcc_lock);
2535         return status;
2536 }
2537
2538 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2539                         u32 domain, u16 intf_id)
2540 {
2541         struct be_mcc_wrb *wrb;
2542         struct be_cmd_req_set_hsw_config *req;
2543         void *ctxt;
2544         int status;
2545
2546         spin_lock_bh(&adapter->mcc_lock);
2547
2548         wrb = wrb_from_mccq(adapter);
2549         if (!wrb) {
2550                 status = -EBUSY;
2551                 goto err;
2552         }
2553
2554         req = embedded_payload(wrb);
2555         ctxt = &req->context;
2556
2557         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2558                         OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2559
2560         req->hdr.domain = domain;
2561         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2562         if (pvid) {
2563                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2564                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2565         }
2566
2567         be_dws_cpu_to_le(req->context, sizeof(req->context));
2568         status = be_mcc_notify_wait(adapter);
2569
2570 err:
2571         spin_unlock_bh(&adapter->mcc_lock);
2572         return status;
2573 }
2574
2575 /* Get Hyper switch config */
2576 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2577                         u32 domain, u16 intf_id)
2578 {
2579         struct be_mcc_wrb *wrb;
2580         struct be_cmd_req_get_hsw_config *req;
2581         void *ctxt;
2582         int status;
2583         u16 vid;
2584
2585         spin_lock_bh(&adapter->mcc_lock);
2586
2587         wrb = wrb_from_mccq(adapter);
2588         if (!wrb) {
2589                 status = -EBUSY;
2590                 goto err;
2591         }
2592
2593         req = embedded_payload(wrb);
2594         ctxt = &req->context;
2595
2596         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2597                         OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2598
2599         req->hdr.domain = domain;
2600         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2601                                                                 intf_id);
2602         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2603         be_dws_cpu_to_le(req->context, sizeof(req->context));
2604
2605         status = be_mcc_notify_wait(adapter);
2606         if (!status) {
2607                 struct be_cmd_resp_get_hsw_config *resp =
2608                                                 embedded_payload(wrb);
2609                 be_dws_le_to_cpu(&resp->context,
2610                                                 sizeof(resp->context));
2611                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2612                                                         pvid, &resp->context);
2613                 *pvid = le16_to_cpu(vid);
2614         }
2615
2616 err:
2617         spin_unlock_bh(&adapter->mcc_lock);
2618         return status;
2619 }
2620
2621 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2622 {
2623         struct be_mcc_wrb *wrb;
2624         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2625         int status;
2626         int payload_len = sizeof(*req);
2627         struct be_dma_mem cmd;
2628
2629         memset(&cmd, 0, sizeof(struct be_dma_mem));
2630         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2631         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2632                                                &cmd.dma);
2633         if (!cmd.va) {
2634                 dev_err(&adapter->pdev->dev,
2635                                 "Memory allocation failure\n");
2636                 return -ENOMEM;
2637         }
2638
2639         if (mutex_lock_interruptible(&adapter->mbox_lock))
2640                 return -1;
2641
2642         wrb = wrb_from_mbox(adapter);
2643         if (!wrb) {
2644                 status = -EBUSY;
2645                 goto err;
2646         }
2647
2648         req = cmd.va;
2649
2650         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2651                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2652                                payload_len, wrb, &cmd);
2653
2654         req->hdr.version = 1;
2655         req->query_options = BE_GET_WOL_CAP;
2656
2657         status = be_mbox_notify_wait(adapter);
2658         if (!status) {
2659                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2660                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2661
2662                 /* the command could succeed misleadingly on old f/w
2663                  * which is not aware of the V1 version. fake an error. */
2664                 if (resp->hdr.response_length < payload_len) {
2665                         status = -1;
2666                         goto err;
2667                 }
2668                 adapter->wol_cap = resp->wol_settings;
2669         }
2670 err:
2671         mutex_unlock(&adapter->mbox_lock);
2672         pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2673         return status;
2674
2675 }
2676 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2677                                    struct be_dma_mem *cmd)
2678 {
2679         struct be_mcc_wrb *wrb;
2680         struct be_cmd_req_get_ext_fat_caps *req;
2681         int status;
2682
2683         if (mutex_lock_interruptible(&adapter->mbox_lock))
2684                 return -1;
2685
2686         wrb = wrb_from_mbox(adapter);
2687         if (!wrb) {
2688                 status = -EBUSY;
2689                 goto err;
2690         }
2691
2692         req = cmd->va;
2693         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2694                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
2695                                cmd->size, wrb, cmd);
2696         req->parameter_type = cpu_to_le32(1);
2697
2698         status = be_mbox_notify_wait(adapter);
2699 err:
2700         mutex_unlock(&adapter->mbox_lock);
2701         return status;
2702 }
2703
2704 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2705                                    struct be_dma_mem *cmd,
2706                                    struct be_fat_conf_params *configs)
2707 {
2708         struct be_mcc_wrb *wrb;
2709         struct be_cmd_req_set_ext_fat_caps *req;
2710         int status;
2711
2712         spin_lock_bh(&adapter->mcc_lock);
2713
2714         wrb = wrb_from_mccq(adapter);
2715         if (!wrb) {
2716                 status = -EBUSY;
2717                 goto err;
2718         }
2719
2720         req = cmd->va;
2721         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
2722         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2723                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
2724                                cmd->size, wrb, cmd);
2725
2726         status = be_mcc_notify_wait(adapter);
2727 err:
2728         spin_unlock_bh(&adapter->mcc_lock);
2729         return status;
2730 }
2731
2732 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
2733 {
2734         struct be_mcc_wrb *wrb;
2735         struct be_cmd_req_get_port_name *req;
2736         int status;
2737
2738         if (!lancer_chip(adapter)) {
2739                 *port_name = adapter->hba_port_num + '0';
2740                 return 0;
2741         }
2742
2743         spin_lock_bh(&adapter->mcc_lock);
2744
2745         wrb = wrb_from_mccq(adapter);
2746         if (!wrb) {
2747                 status = -EBUSY;
2748                 goto err;
2749         }
2750
2751         req = embedded_payload(wrb);
2752
2753         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2754                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
2755                                NULL);
2756         req->hdr.version = 1;
2757
2758         status = be_mcc_notify_wait(adapter);
2759         if (!status) {
2760                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
2761                 *port_name = resp->port_name[adapter->hba_port_num];
2762         } else {
2763                 *port_name = adapter->hba_port_num + '0';
2764         }
2765 err:
2766         spin_unlock_bh(&adapter->mcc_lock);
2767         return status;
2768 }
2769
2770 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
2771                         int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
2772 {
2773         struct be_adapter *adapter = netdev_priv(netdev_handle);
2774         struct be_mcc_wrb *wrb;
2775         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
2776         struct be_cmd_req_hdr *req;
2777         struct be_cmd_resp_hdr *resp;
2778         int status;
2779
2780         spin_lock_bh(&adapter->mcc_lock);
2781
2782         wrb = wrb_from_mccq(adapter);
2783         if (!wrb) {
2784                 status = -EBUSY;
2785                 goto err;
2786         }
2787         req = embedded_payload(wrb);
2788         resp = embedded_payload(wrb);
2789
2790         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
2791                                hdr->opcode, wrb_payload_size, wrb, NULL);
2792         memcpy(req, wrb_payload, wrb_payload_size);
2793         be_dws_cpu_to_le(req, wrb_payload_size);
2794
2795         status = be_mcc_notify_wait(adapter);
2796         if (cmd_status)
2797                 *cmd_status = (status & 0xffff);
2798         if (ext_status)
2799                 *ext_status = 0;
2800         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
2801         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
2802 err:
2803         spin_unlock_bh(&adapter->mcc_lock);
2804         return status;
2805 }
2806 EXPORT_SYMBOL(be_roce_mcc_cmd);