2 * Copyright(c) 2015 EZchip Technologies.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
21 #define NPS_ENET_NAPI_POLL_WEIGHT 0x2
22 #define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF
23 #define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7
24 #define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5
25 #define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC
26 #define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7
27 #define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3
28 #define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14
29 #define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC
30 #define NPS_ENET_ENABLE 1
31 #define NPS_ENET_DISABLE 0
33 /* register definitions */
34 #define NPS_ENET_REG_TX_CTL 0x800
35 #define NPS_ENET_REG_TX_BUF 0x808
36 #define NPS_ENET_REG_RX_CTL 0x810
37 #define NPS_ENET_REG_RX_BUF 0x818
38 #define NPS_ENET_REG_BUF_INT_ENABLE 0x8C0
39 #define NPS_ENET_REG_GE_MAC_CFG_0 0x1000
40 #define NPS_ENET_REG_GE_MAC_CFG_1 0x1004
41 #define NPS_ENET_REG_GE_MAC_CFG_2 0x1008
42 #define NPS_ENET_REG_GE_MAC_CFG_3 0x100C
43 #define NPS_ENET_REG_GE_RST 0x1400
44 #define NPS_ENET_REG_PHASE_FIFO_CTL 0x1404
46 /* Tx control register */
47 struct nps_enet_tx_ctl {
49 /* ct: SW sets to indicate frame ready in Tx buffer for
50 * transmission. HW resets to when transmission done
52 * nt: Length in bytes of Tx frame loaded to Tx buffer
67 /* Rx control register */
68 struct nps_enet_rx_ctl {
70 /* cr: HW sets to indicate frame ready in Rx buffer.
71 * SW resets to indicate host read received frame
72 * and new frames can be written to Rx buffer
73 * er: Rx error indication
74 * crc: Rx CRC error indication
75 * nr: Length in bytes of Rx frame loaded by MAC to Rx buffer
91 /* Interrupt enable for data buffer events register */
92 struct nps_enet_buf_int_enable {
94 /* tx_done: Interrupt generation in the case when new frame
95 * is ready in Rx buffer
96 * rx_rdy: Interrupt generation in the case when current frame
97 * was read from TX buffer
110 /* Gbps Eth MAC Configuration 0 register */
111 struct nps_enet_ge_mac_cfg_0 {
113 /* tx_pr_len: Transmit preamble length in bytes
114 * tx_ifg_nib: Tx idle pattern
115 * nib_mode: Nibble (4-bit) Mode
116 * rx_pr_check_en: Receive preamble Check Enable
117 * tx_ifg: Transmit inter-Frame Gap
118 * rx_ifg: Receive inter-Frame Gap
119 * tx_fc_retr: Transmit Flow Control Retransmit Mode
120 * rx_length_check_en: Receive Length Check Enable
121 * rx_crc_ignore: Results of the CRC check are ignored
122 * rx_crc_strip: MAC strips the CRC from received frames
123 * rx_fc_en: Receive Flow Control Enable
124 * tx_crc_en: Transmit CRC Enabled
125 * tx_pad_en: Transmit Padding Enable
126 * tx_cf_en: Transmit Flow Control Enable
127 * tx_en: Transmit Enable
128 * rx_en: Receive Enable
139 rx_length_check_en:1,
154 /* Gbps Eth MAC Configuration 1 register */
155 struct nps_enet_ge_mac_cfg_1 {
157 /* octet_3: MAC address octet 3
158 * octet_2: MAC address octet 2
159 * octet_1: MAC address octet 1
160 * octet_0: MAC address octet 0
174 /* Gbps Eth MAC Configuration 2 register */
175 struct nps_enet_ge_mac_cfg_2 {
177 /* transmit_flush_en: MAC flush enable
178 * stat_en: RMON statistics interface enable
179 * disc_da: Discard frames with DA different
181 * disc_bc: Discard broadcast frames
182 * disc_mc: Discard multicast frames
183 * octet_5: MAC address octet 5
184 * octet_4: MAC address octet 4
204 /* Gbps Eth MAC Configuration 3 register */
205 struct nps_enet_ge_mac_cfg_3 {
207 /* ext_oob_cbfc_sel: Selects one of the 4 profiles for
208 * extended OOB in-flow-control indication
209 * max_len: Maximum receive frame length in bytes
210 * tx_cbfc_en: Enable transmission of class-based
211 * flow control packets
212 * rx_ifg_th: Threshold for IFG status reporting via OOB
213 * cf_timeout: Configurable time to decrement FC counters
214 * cf_drop: Drop control frames
215 * redirect_cbfc_sel: Selects one of CBFC redirect profiles
216 * rx_cbfc_redir_en: Enable Rx class-based flow
218 * rx_cbfc_en: Enable Rx class-based flow control
219 * tm_hd_mode: TM header mode
239 /* GE MAC, PCS reset control register */
240 struct nps_enet_ge_rst {
242 /* gmac_0: GE MAC reset
243 * spcs_0: SGMII PCS reset
257 /* Tx phase sync FIFO control register */
258 struct nps_enet_phase_fifo_ctl {
260 /* init: initialize serdes TX phase sync FIFO pointers
261 * rst: reset serdes TX phase sync FIFO
275 * struct nps_enet_priv - Storage of ENET's private information.
276 * @regs_base: Base address of ENET memory-mapped control registers.
277 * @irq: For RX/TX IRQ number.
278 * @tx_packet_sent: SW indication if frame is being sent.
279 * @tx_skb: socket buffer of sent frame.
280 * @napi: Structure for NAPI.
282 struct nps_enet_priv {
283 void __iomem *regs_base;
286 struct sk_buff *tx_skb;
287 struct napi_struct napi;
288 struct nps_enet_ge_mac_cfg_2 ge_mac_cfg_2;
289 struct nps_enet_ge_mac_cfg_3 ge_mac_cfg_3;
293 * nps_reg_set - Sets ENET register with provided value.
294 * @priv: Pointer to EZchip ENET private data structure.
295 * @reg: Register offset from base address.
296 * @value: Value to set in register.
298 static inline void nps_enet_reg_set(struct nps_enet_priv *priv,
301 iowrite32be(value, priv->regs_base + reg);
305 * nps_reg_get - Gets value of specified ENET register.
306 * @priv: Pointer to EZchip ENET private data structure.
307 * @reg: Register offset from base address.
309 * returns: Value of requested register.
311 static inline u32 nps_enet_reg_get(struct nps_enet_priv *priv, s32 reg)
313 return ioread32be(priv->regs_base + reg);
316 #endif /* _NPS_ENET_H */