2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/spinlock.h>
38 #include <linux/workqueue.h>
39 #include <linux/bitops.h>
41 #include <linux/irq.h>
42 #include <linux/clk.h>
43 #include <linux/platform_device.h>
44 #include <linux/phy.h>
45 #include <linux/fec.h>
47 #include <linux/of_device.h>
48 #include <linux/of_gpio.h>
49 #include <linux/of_net.h>
50 #include <linux/pinctrl/consumer.h>
51 #include <linux/regulator/consumer.h>
53 #include <asm/cacheflush.h>
57 #if defined(CONFIG_ARM)
58 #define FEC_ALIGNMENT 0xf
60 #define FEC_ALIGNMENT 0x3
63 #define DRIVER_NAME "fec"
64 #define FEC_NAPI_WEIGHT 64
66 /* Pause frame feild and FIFO threshold */
67 #define FEC_ENET_FCE (1 << 5)
68 #define FEC_ENET_RSEM_V 0x84
69 #define FEC_ENET_RSFL_V 16
70 #define FEC_ENET_RAEM_V 0x8
71 #define FEC_ENET_RAFL_V 0x8
72 #define FEC_ENET_OPD_V 0xFFF0
74 /* Controller is ENET-MAC */
75 #define FEC_QUIRK_ENET_MAC (1 << 0)
76 /* Controller needs driver to swap frame */
77 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
78 /* Controller uses gasket */
79 #define FEC_QUIRK_USE_GASKET (1 << 2)
80 /* Controller has GBIT support */
81 #define FEC_QUIRK_HAS_GBIT (1 << 3)
82 /* Controller has extend desc buffer */
83 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
85 static struct platform_device_id fec_devtype[] = {
87 /* keep it for coldfire */
92 .driver_data = FEC_QUIRK_USE_GASKET,
98 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
101 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
102 FEC_QUIRK_HAS_BUFDESC_EX,
105 .driver_data = FEC_QUIRK_ENET_MAC,
110 MODULE_DEVICE_TABLE(platform, fec_devtype);
113 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
114 IMX27_FEC, /* runs on i.mx27/35/51 */
120 static const struct of_device_id fec_dt_ids[] = {
121 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
122 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
123 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
124 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
125 { .compatible = "fsl,mvf-fec", .data = &fec_devtype[MVF_FEC], },
128 MODULE_DEVICE_TABLE(of, fec_dt_ids);
130 static unsigned char macaddr[ETH_ALEN];
131 module_param_array(macaddr, byte, NULL, 0);
132 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
134 #if defined(CONFIG_M5272)
136 * Some hardware gets it MAC address out of local flash memory.
137 * if this is non-zero then assume it is the address to get MAC from.
139 #if defined(CONFIG_NETtel)
140 #define FEC_FLASHMAC 0xf0006006
141 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
142 #define FEC_FLASHMAC 0xf0006000
143 #elif defined(CONFIG_CANCam)
144 #define FEC_FLASHMAC 0xf0020000
145 #elif defined (CONFIG_M5272C3)
146 #define FEC_FLASHMAC (0xffe04000 + 4)
147 #elif defined(CONFIG_MOD5272)
148 #define FEC_FLASHMAC 0xffc0406b
150 #define FEC_FLASHMAC 0
152 #endif /* CONFIG_M5272 */
154 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
155 #error "FEC: descriptor ring size constants too large"
158 /* Interrupt events/masks. */
159 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
160 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
161 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
162 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
163 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
164 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
165 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
166 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
167 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
168 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
170 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
171 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
173 /* The FEC stores dest/src/type, data, and checksum for receive packets.
175 #define PKT_MAXBUF_SIZE 1518
176 #define PKT_MINBUF_SIZE 64
177 #define PKT_MAXBLR_SIZE 1520
180 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
181 * size bits. Other FEC hardware does not, so we need to take that into
182 * account when setting it.
184 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
185 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
186 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
188 #define OPT_FRAME_SIZE 0
191 /* FEC MII MMFR bits definition */
192 #define FEC_MMFR_ST (1 << 30)
193 #define FEC_MMFR_OP_READ (2 << 28)
194 #define FEC_MMFR_OP_WRITE (1 << 28)
195 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
196 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
197 #define FEC_MMFR_TA (2 << 16)
198 #define FEC_MMFR_DATA(v) (v & 0xffff)
200 #define FEC_MII_TIMEOUT 30000 /* us */
202 /* Transmitter timeout */
203 #define TX_TIMEOUT (2 * HZ)
205 #define FEC_PAUSE_FLAG_AUTONEG 0x1
206 #define FEC_PAUSE_FLAG_ENABLE 0x2
210 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
212 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
214 return (struct bufdesc *)(ex + 1);
219 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
221 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
223 return (struct bufdesc *)(ex - 1);
228 static void *swap_buffer(void *bufaddr, int len)
231 unsigned int *buf = bufaddr;
233 for (i = 0; i < (len + 3) / 4; i++, buf++)
234 *buf = cpu_to_be32(*buf);
240 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
242 struct fec_enet_private *fep = netdev_priv(ndev);
243 const struct platform_device_id *id_entry =
244 platform_get_device_id(fep->pdev);
247 unsigned short status;
251 /* Link is down or autonegotiation is in progress. */
252 return NETDEV_TX_BUSY;
255 /* Fill in a Tx ring entry */
258 status = bdp->cbd_sc;
260 if (status & BD_ENET_TX_READY) {
261 /* Ooops. All transmit buffers are full. Bail out.
262 * This should not happen, since ndev->tbusy should be set.
264 netdev_err(ndev, "tx queue full!\n");
265 return NETDEV_TX_BUSY;
268 /* Clear all of the status flags */
269 status &= ~BD_ENET_TX_STATS;
271 /* Set buffer length and buffer pointer */
273 bdp->cbd_datlen = skb->len;
276 * On some FEC implementations data must be aligned on
277 * 4-byte boundaries. Use bounce buffers to copy data
278 * and get it aligned. Ugh.
281 index = (struct bufdesc_ex *)bdp -
282 (struct bufdesc_ex *)fep->tx_bd_base;
284 index = bdp - fep->tx_bd_base;
286 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
287 memcpy(fep->tx_bounce[index], skb->data, skb->len);
288 bufaddr = fep->tx_bounce[index];
292 * Some design made an incorrect assumption on endian mode of
293 * the system that it's running on. As the result, driver has to
294 * swap every frame going to and coming from the controller.
296 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
297 swap_buffer(bufaddr, skb->len);
299 /* Save skb pointer */
300 fep->tx_skbuff[index] = skb;
302 /* Push the data cache so the CPM does not get stale memory
305 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
306 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
308 /* Send it on its way. Tell FEC it's ready, interrupt when done,
309 * it's the last BD of the frame, and to put the CRC on the end.
311 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
312 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
313 bdp->cbd_sc = status;
315 if (fep->bufdesc_ex) {
317 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
319 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
321 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
322 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
325 ebdp->cbd_esc = BD_ENET_TX_INT;
328 /* If this was the last BD in the ring, start at the beginning again. */
329 if (status & BD_ENET_TX_WRAP)
330 bdp = fep->tx_bd_base;
332 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
336 if (fep->cur_tx == fep->dirty_tx)
337 netif_stop_queue(ndev);
339 /* Trigger transmission start */
340 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
342 skb_tx_timestamp(skb);
347 /* Init RX & TX buffer descriptors
349 static void fec_enet_bd_init(struct net_device *dev)
351 struct fec_enet_private *fep = netdev_priv(dev);
355 /* Initialize the receive buffer descriptors. */
356 bdp = fep->rx_bd_base;
357 for (i = 0; i < RX_RING_SIZE; i++) {
359 /* Initialize the BD for every fragment in the page. */
360 if (bdp->cbd_bufaddr)
361 bdp->cbd_sc = BD_ENET_RX_EMPTY;
364 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
367 /* Set the last buffer to wrap */
368 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
369 bdp->cbd_sc |= BD_SC_WRAP;
371 fep->cur_rx = fep->rx_bd_base;
373 /* ...and the same for transmit */
374 bdp = fep->tx_bd_base;
376 for (i = 0; i < TX_RING_SIZE; i++) {
378 /* Initialize the BD for every fragment in the page. */
380 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
381 dev_kfree_skb_any(fep->tx_skbuff[i]);
382 fep->tx_skbuff[i] = NULL;
384 bdp->cbd_bufaddr = 0;
385 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
388 /* Set the last buffer to wrap */
389 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
390 bdp->cbd_sc |= BD_SC_WRAP;
394 /* This function is called to start or restart the FEC during a link
395 * change. This only happens when switching between half and full
399 fec_restart(struct net_device *ndev, int duplex)
401 struct fec_enet_private *fep = netdev_priv(ndev);
402 const struct platform_device_id *id_entry =
403 platform_get_device_id(fep->pdev);
406 u32 rcntl = OPT_FRAME_SIZE | 0x04;
407 u32 ecntl = 0x2; /* ETHEREN */
409 /* Whack a reset. We should wait for this. */
410 writel(1, fep->hwp + FEC_ECNTRL);
414 * enet-mac reset will reset mac address registers too,
415 * so need to reconfigure it.
417 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
418 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
419 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
420 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
423 /* Clear any outstanding interrupt. */
424 writel(0xffc00000, fep->hwp + FEC_IEVENT);
426 /* Reset all multicast. */
427 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
428 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
430 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
431 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
434 /* Set maximum receive buffer size. */
435 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
437 fec_enet_bd_init(ndev);
439 /* Set receive and transmit descriptor base. */
440 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
442 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
443 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
445 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
446 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
449 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
450 if (fep->tx_skbuff[i]) {
451 dev_kfree_skb_any(fep->tx_skbuff[i]);
452 fep->tx_skbuff[i] = NULL;
456 /* Enable MII mode */
459 writel(0x04, fep->hwp + FEC_X_CNTRL);
463 writel(0x0, fep->hwp + FEC_X_CNTRL);
466 fep->full_duplex = duplex;
469 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
472 * The phy interface and speed need to get configured
473 * differently on enet-mac.
475 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
476 /* Enable flow control and length check */
477 rcntl |= 0x40000000 | 0x00000020;
479 /* RGMII, RMII or MII */
480 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
482 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
487 /* 1G, 100M or 10M */
489 if (fep->phy_dev->speed == SPEED_1000)
491 else if (fep->phy_dev->speed == SPEED_100)
497 #ifdef FEC_MIIGSK_ENR
498 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
500 /* disable the gasket and wait */
501 writel(0, fep->hwp + FEC_MIIGSK_ENR);
502 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
506 * configure the gasket:
507 * RMII, 50 MHz, no loopback, no echo
508 * MII, 25 MHz, no loopback, no echo
510 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
511 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
512 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
513 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
514 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
516 /* re-enable the gasket */
517 writel(2, fep->hwp + FEC_MIIGSK_ENR);
522 /* enable pause frame*/
523 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
524 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
525 fep->phy_dev && fep->phy_dev->pause)) {
526 rcntl |= FEC_ENET_FCE;
528 /* set FIFO thresh hold parameter to reduce overrun */
529 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
530 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
531 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
532 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
535 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
537 rcntl &= ~FEC_ENET_FCE;
540 writel(rcntl, fep->hwp + FEC_R_CNTRL);
542 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
543 /* enable ENET endian swap */
545 /* enable ENET store and forward mode */
546 writel(1 << 8, fep->hwp + FEC_X_WMRK);
552 /* And last, enable the transmit and receive processing */
553 writel(ecntl, fep->hwp + FEC_ECNTRL);
554 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
557 fec_ptp_start_cyclecounter(ndev);
559 /* Enable interrupts we wish to service */
560 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
564 fec_stop(struct net_device *ndev)
566 struct fec_enet_private *fep = netdev_priv(ndev);
567 const struct platform_device_id *id_entry =
568 platform_get_device_id(fep->pdev);
569 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
571 /* We cannot expect a graceful transmit stop without link !!! */
573 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
575 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
576 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
579 /* Whack a reset. We should wait for this. */
580 writel(1, fep->hwp + FEC_ECNTRL);
582 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
583 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
585 /* We have to keep ENET enabled to have MII interrupt stay working */
586 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
587 writel(2, fep->hwp + FEC_ECNTRL);
588 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
594 fec_timeout(struct net_device *ndev)
596 struct fec_enet_private *fep = netdev_priv(ndev);
598 ndev->stats.tx_errors++;
600 fec_restart(ndev, fep->full_duplex);
601 netif_wake_queue(ndev);
605 fec_enet_tx(struct net_device *ndev)
607 struct fec_enet_private *fep;
609 unsigned short status;
613 fep = netdev_priv(ndev);
616 /* get next bdp of dirty_tx */
617 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
618 bdp = fep->tx_bd_base;
620 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
622 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
624 /* current queue is empty */
625 if (bdp == fep->cur_tx)
629 index = (struct bufdesc_ex *)bdp -
630 (struct bufdesc_ex *)fep->tx_bd_base;
632 index = bdp - fep->tx_bd_base;
634 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
635 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
636 bdp->cbd_bufaddr = 0;
638 skb = fep->tx_skbuff[index];
640 /* Check for errors. */
641 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
642 BD_ENET_TX_RL | BD_ENET_TX_UN |
644 ndev->stats.tx_errors++;
645 if (status & BD_ENET_TX_HB) /* No heartbeat */
646 ndev->stats.tx_heartbeat_errors++;
647 if (status & BD_ENET_TX_LC) /* Late collision */
648 ndev->stats.tx_window_errors++;
649 if (status & BD_ENET_TX_RL) /* Retrans limit */
650 ndev->stats.tx_aborted_errors++;
651 if (status & BD_ENET_TX_UN) /* Underrun */
652 ndev->stats.tx_fifo_errors++;
653 if (status & BD_ENET_TX_CSL) /* Carrier lost */
654 ndev->stats.tx_carrier_errors++;
656 ndev->stats.tx_packets++;
659 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
661 struct skb_shared_hwtstamps shhwtstamps;
663 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
665 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
666 spin_lock_irqsave(&fep->tmreg_lock, flags);
667 shhwtstamps.hwtstamp = ns_to_ktime(
668 timecounter_cyc2time(&fep->tc, ebdp->ts));
669 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
670 skb_tstamp_tx(skb, &shhwtstamps);
673 if (status & BD_ENET_TX_READY)
674 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
676 /* Deferred means some collisions occurred during transmit,
677 * but we eventually sent the packet OK.
679 if (status & BD_ENET_TX_DEF)
680 ndev->stats.collisions++;
682 /* Free the sk buffer associated with this last transmit */
683 dev_kfree_skb_any(skb);
684 fep->tx_skbuff[index] = NULL;
688 /* Update pointer to next buffer descriptor to be transmitted */
689 if (status & BD_ENET_TX_WRAP)
690 bdp = fep->tx_bd_base;
692 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
694 /* Since we have freed up a buffer, the ring is no longer full
696 if (fep->dirty_tx != fep->cur_tx) {
697 if (netif_queue_stopped(ndev))
698 netif_wake_queue(ndev);
705 /* During a receive, the cur_rx points to the current incoming buffer.
706 * When we update through the ring, if the next incoming buffer has
707 * not been given to the system, we just set the empty indicator,
708 * effectively tossing the packet.
711 fec_enet_rx(struct net_device *ndev, int budget)
713 struct fec_enet_private *fep = netdev_priv(ndev);
714 const struct platform_device_id *id_entry =
715 platform_get_device_id(fep->pdev);
717 unsigned short status;
721 int pkt_received = 0;
727 /* First, grab all of the stats for the incoming packet.
728 * These get messed up if we get called due to a busy condition.
732 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
734 if (pkt_received >= budget)
738 /* Since we have allocated space to hold a complete frame,
739 * the last indicator should be set.
741 if ((status & BD_ENET_RX_LAST) == 0)
742 netdev_err(ndev, "rcv is not +last\n");
745 goto rx_processing_done;
747 /* Check for errors. */
748 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
749 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
750 ndev->stats.rx_errors++;
751 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
752 /* Frame too long or too short. */
753 ndev->stats.rx_length_errors++;
755 if (status & BD_ENET_RX_NO) /* Frame alignment */
756 ndev->stats.rx_frame_errors++;
757 if (status & BD_ENET_RX_CR) /* CRC Error */
758 ndev->stats.rx_crc_errors++;
759 if (status & BD_ENET_RX_OV) /* FIFO overrun */
760 ndev->stats.rx_fifo_errors++;
763 /* Report late collisions as a frame error.
764 * On this error, the BD is closed, but we don't know what we
765 * have in the buffer. So, just drop this frame on the floor.
767 if (status & BD_ENET_RX_CL) {
768 ndev->stats.rx_errors++;
769 ndev->stats.rx_frame_errors++;
770 goto rx_processing_done;
773 /* Process the incoming frame. */
774 ndev->stats.rx_packets++;
775 pkt_len = bdp->cbd_datlen;
776 ndev->stats.rx_bytes += pkt_len;
777 data = (__u8*)__va(bdp->cbd_bufaddr);
779 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
780 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
782 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
783 swap_buffer(data, pkt_len);
785 /* This does 16 byte alignment, exactly what we need.
786 * The packet length includes FCS, but we don't want to
787 * include that when passing upstream as it messes up
788 * bridging applications.
790 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
792 if (unlikely(!skb)) {
793 ndev->stats.rx_dropped++;
795 skb_reserve(skb, NET_IP_ALIGN);
796 skb_put(skb, pkt_len - 4); /* Make room */
797 skb_copy_to_linear_data(skb, data, pkt_len - 4);
798 skb->protocol = eth_type_trans(skb, ndev);
800 /* Get receive timestamp from the skb */
801 if (fep->hwts_rx_en && fep->bufdesc_ex) {
802 struct skb_shared_hwtstamps *shhwtstamps =
805 struct bufdesc_ex *ebdp =
806 (struct bufdesc_ex *)bdp;
808 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
810 spin_lock_irqsave(&fep->tmreg_lock, flags);
811 shhwtstamps->hwtstamp = ns_to_ktime(
812 timecounter_cyc2time(&fep->tc, ebdp->ts));
813 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
816 if (!skb_defer_rx_timestamp(skb))
817 napi_gro_receive(&fep->napi, skb);
820 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
821 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
823 /* Clear the status flags for this buffer */
824 status &= ~BD_ENET_RX_STATS;
826 /* Mark the buffer empty */
827 status |= BD_ENET_RX_EMPTY;
828 bdp->cbd_sc = status;
830 if (fep->bufdesc_ex) {
831 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
833 ebdp->cbd_esc = BD_ENET_RX_INT;
838 /* Update BD pointer to next entry */
839 if (status & BD_ENET_RX_WRAP)
840 bdp = fep->rx_bd_base;
842 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
843 /* Doing this here will keep the FEC running while we process
844 * incoming frames. On a heavily loaded network, we should be
845 * able to keep up at the expense of system resources.
847 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
855 fec_enet_interrupt(int irq, void *dev_id)
857 struct net_device *ndev = dev_id;
858 struct fec_enet_private *fep = netdev_priv(ndev);
860 irqreturn_t ret = IRQ_NONE;
863 int_events = readl(fep->hwp + FEC_IEVENT);
864 writel(int_events, fep->hwp + FEC_IEVENT);
866 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
869 /* Disable the RX interrupt */
870 if (napi_schedule_prep(&fep->napi)) {
871 writel(FEC_RX_DISABLED_IMASK,
872 fep->hwp + FEC_IMASK);
873 __napi_schedule(&fep->napi);
877 if (int_events & FEC_ENET_MII) {
879 complete(&fep->mdio_done);
881 } while (int_events);
886 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
888 struct net_device *ndev = napi->dev;
889 int pkts = fec_enet_rx(ndev, budget);
890 struct fec_enet_private *fep = netdev_priv(ndev);
896 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
901 /* ------------------------------------------------------------------------- */
902 static void fec_get_mac(struct net_device *ndev)
904 struct fec_enet_private *fep = netdev_priv(ndev);
905 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
906 unsigned char *iap, tmpaddr[ETH_ALEN];
909 * try to get mac address in following order:
911 * 1) module parameter via kernel command line in form
912 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
917 * 2) from device tree data
919 if (!is_valid_ether_addr(iap)) {
920 struct device_node *np = fep->pdev->dev.of_node;
922 const char *mac = of_get_mac_address(np);
924 iap = (unsigned char *) mac;
929 * 3) from flash or fuse (via platform data)
931 if (!is_valid_ether_addr(iap)) {
934 iap = (unsigned char *)FEC_FLASHMAC;
937 iap = (unsigned char *)&pdata->mac;
942 * 4) FEC mac registers set by bootloader
944 if (!is_valid_ether_addr(iap)) {
945 *((unsigned long *) &tmpaddr[0]) =
946 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
947 *((unsigned short *) &tmpaddr[4]) =
948 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
952 memcpy(ndev->dev_addr, iap, ETH_ALEN);
954 /* Adjust MAC if using macaddr */
956 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
959 /* ------------------------------------------------------------------------- */
964 static void fec_enet_adjust_link(struct net_device *ndev)
966 struct fec_enet_private *fep = netdev_priv(ndev);
967 struct phy_device *phy_dev = fep->phy_dev;
970 int status_change = 0;
972 spin_lock_irqsave(&fep->hw_lock, flags);
974 /* Prevent a state halted on mii error */
975 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
976 phy_dev->state = PHY_RESUMING;
982 fep->link = phy_dev->link;
986 if (fep->full_duplex != phy_dev->duplex)
989 if (phy_dev->speed != fep->speed) {
990 fep->speed = phy_dev->speed;
994 /* if any of the above changed restart the FEC */
996 fec_restart(ndev, phy_dev->duplex);
1000 fep->link = phy_dev->link;
1006 spin_unlock_irqrestore(&fep->hw_lock, flags);
1009 phy_print_status(phy_dev);
1012 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1014 struct fec_enet_private *fep = bus->priv;
1015 unsigned long time_left;
1017 fep->mii_timeout = 0;
1018 init_completion(&fep->mdio_done);
1020 /* start a read op */
1021 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1022 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1023 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1025 /* wait for end of transfer */
1026 time_left = wait_for_completion_timeout(&fep->mdio_done,
1027 usecs_to_jiffies(FEC_MII_TIMEOUT));
1028 if (time_left == 0) {
1029 fep->mii_timeout = 1;
1030 netdev_err(fep->netdev, "MDIO read timeout\n");
1035 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1038 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1041 struct fec_enet_private *fep = bus->priv;
1042 unsigned long time_left;
1044 fep->mii_timeout = 0;
1045 init_completion(&fep->mdio_done);
1047 /* start a write op */
1048 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1049 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1050 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1051 fep->hwp + FEC_MII_DATA);
1053 /* wait for end of transfer */
1054 time_left = wait_for_completion_timeout(&fep->mdio_done,
1055 usecs_to_jiffies(FEC_MII_TIMEOUT));
1056 if (time_left == 0) {
1057 fep->mii_timeout = 1;
1058 netdev_err(fep->netdev, "MDIO write timeout\n");
1065 static int fec_enet_mdio_reset(struct mii_bus *bus)
1070 static int fec_enet_mii_probe(struct net_device *ndev)
1072 struct fec_enet_private *fep = netdev_priv(ndev);
1073 const struct platform_device_id *id_entry =
1074 platform_get_device_id(fep->pdev);
1075 struct phy_device *phy_dev = NULL;
1076 char mdio_bus_id[MII_BUS_ID_SIZE];
1077 char phy_name[MII_BUS_ID_SIZE + 3];
1079 int dev_id = fep->dev_id;
1081 fep->phy_dev = NULL;
1083 /* check for attached phy */
1084 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1085 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1087 if (fep->mii_bus->phy_map[phy_id] == NULL)
1089 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1093 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1097 if (phy_id >= PHY_MAX_ADDR) {
1098 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1099 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1103 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1104 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1105 fep->phy_interface);
1106 if (IS_ERR(phy_dev)) {
1107 netdev_err(ndev, "could not attach to PHY\n");
1108 return PTR_ERR(phy_dev);
1111 /* mask with MAC supported features */
1112 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1113 phy_dev->supported &= PHY_GBIT_FEATURES;
1114 phy_dev->supported |= SUPPORTED_Pause;
1117 phy_dev->supported &= PHY_BASIC_FEATURES;
1119 phy_dev->advertising = phy_dev->supported;
1121 fep->phy_dev = phy_dev;
1123 fep->full_duplex = 0;
1125 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1126 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1132 static int fec_enet_mii_init(struct platform_device *pdev)
1134 static struct mii_bus *fec0_mii_bus;
1135 struct net_device *ndev = platform_get_drvdata(pdev);
1136 struct fec_enet_private *fep = netdev_priv(ndev);
1137 const struct platform_device_id *id_entry =
1138 platform_get_device_id(fep->pdev);
1139 int err = -ENXIO, i;
1142 * The dual fec interfaces are not equivalent with enet-mac.
1143 * Here are the differences:
1145 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1146 * - fec0 acts as the 1588 time master while fec1 is slave
1147 * - external phys can only be configured by fec0
1149 * That is to say fec1 can not work independently. It only works
1150 * when fec0 is working. The reason behind this design is that the
1151 * second interface is added primarily for Switch mode.
1153 * Because of the last point above, both phys are attached on fec0
1154 * mdio interface in board design, and need to be configured by
1157 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1158 /* fec1 uses fec0 mii_bus */
1159 if (mii_cnt && fec0_mii_bus) {
1160 fep->mii_bus = fec0_mii_bus;
1167 fep->mii_timeout = 0;
1170 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1172 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1173 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1174 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1177 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1178 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1180 fep->phy_speed <<= 1;
1181 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1183 fep->mii_bus = mdiobus_alloc();
1184 if (fep->mii_bus == NULL) {
1189 fep->mii_bus->name = "fec_enet_mii_bus";
1190 fep->mii_bus->read = fec_enet_mdio_read;
1191 fep->mii_bus->write = fec_enet_mdio_write;
1192 fep->mii_bus->reset = fec_enet_mdio_reset;
1193 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1194 pdev->name, fep->dev_id + 1);
1195 fep->mii_bus->priv = fep;
1196 fep->mii_bus->parent = &pdev->dev;
1198 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1199 if (!fep->mii_bus->irq) {
1201 goto err_out_free_mdiobus;
1204 for (i = 0; i < PHY_MAX_ADDR; i++)
1205 fep->mii_bus->irq[i] = PHY_POLL;
1207 if (mdiobus_register(fep->mii_bus))
1208 goto err_out_free_mdio_irq;
1212 /* save fec0 mii_bus */
1213 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1214 fec0_mii_bus = fep->mii_bus;
1218 err_out_free_mdio_irq:
1219 kfree(fep->mii_bus->irq);
1220 err_out_free_mdiobus:
1221 mdiobus_free(fep->mii_bus);
1226 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1228 if (--mii_cnt == 0) {
1229 mdiobus_unregister(fep->mii_bus);
1230 kfree(fep->mii_bus->irq);
1231 mdiobus_free(fep->mii_bus);
1235 static int fec_enet_get_settings(struct net_device *ndev,
1236 struct ethtool_cmd *cmd)
1238 struct fec_enet_private *fep = netdev_priv(ndev);
1239 struct phy_device *phydev = fep->phy_dev;
1244 return phy_ethtool_gset(phydev, cmd);
1247 static int fec_enet_set_settings(struct net_device *ndev,
1248 struct ethtool_cmd *cmd)
1250 struct fec_enet_private *fep = netdev_priv(ndev);
1251 struct phy_device *phydev = fep->phy_dev;
1256 return phy_ethtool_sset(phydev, cmd);
1259 static void fec_enet_get_drvinfo(struct net_device *ndev,
1260 struct ethtool_drvinfo *info)
1262 struct fec_enet_private *fep = netdev_priv(ndev);
1264 strlcpy(info->driver, fep->pdev->dev.driver->name,
1265 sizeof(info->driver));
1266 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1267 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1270 static int fec_enet_get_ts_info(struct net_device *ndev,
1271 struct ethtool_ts_info *info)
1273 struct fec_enet_private *fep = netdev_priv(ndev);
1275 if (fep->bufdesc_ex) {
1277 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1278 SOF_TIMESTAMPING_RX_SOFTWARE |
1279 SOF_TIMESTAMPING_SOFTWARE |
1280 SOF_TIMESTAMPING_TX_HARDWARE |
1281 SOF_TIMESTAMPING_RX_HARDWARE |
1282 SOF_TIMESTAMPING_RAW_HARDWARE;
1284 info->phc_index = ptp_clock_index(fep->ptp_clock);
1286 info->phc_index = -1;
1288 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1289 (1 << HWTSTAMP_TX_ON);
1291 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1292 (1 << HWTSTAMP_FILTER_ALL);
1295 return ethtool_op_get_ts_info(ndev, info);
1299 static void fec_enet_get_pauseparam(struct net_device *ndev,
1300 struct ethtool_pauseparam *pause)
1302 struct fec_enet_private *fep = netdev_priv(ndev);
1304 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1305 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1306 pause->rx_pause = pause->tx_pause;
1309 static int fec_enet_set_pauseparam(struct net_device *ndev,
1310 struct ethtool_pauseparam *pause)
1312 struct fec_enet_private *fep = netdev_priv(ndev);
1314 if (pause->tx_pause != pause->rx_pause) {
1316 "hardware only support enable/disable both tx and rx");
1320 fep->pause_flag = 0;
1322 /* tx pause must be same as rx pause */
1323 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1324 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1326 if (pause->rx_pause || pause->autoneg) {
1327 fep->phy_dev->supported |= ADVERTISED_Pause;
1328 fep->phy_dev->advertising |= ADVERTISED_Pause;
1330 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1331 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1334 if (pause->autoneg) {
1335 if (netif_running(ndev))
1337 phy_start_aneg(fep->phy_dev);
1339 if (netif_running(ndev))
1340 fec_restart(ndev, 0);
1345 static const struct ethtool_ops fec_enet_ethtool_ops = {
1346 .get_pauseparam = fec_enet_get_pauseparam,
1347 .set_pauseparam = fec_enet_set_pauseparam,
1348 .get_settings = fec_enet_get_settings,
1349 .set_settings = fec_enet_set_settings,
1350 .get_drvinfo = fec_enet_get_drvinfo,
1351 .get_link = ethtool_op_get_link,
1352 .get_ts_info = fec_enet_get_ts_info,
1355 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1357 struct fec_enet_private *fep = netdev_priv(ndev);
1358 struct phy_device *phydev = fep->phy_dev;
1360 if (!netif_running(ndev))
1366 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
1367 return fec_ptp_ioctl(ndev, rq, cmd);
1369 return phy_mii_ioctl(phydev, rq, cmd);
1372 static void fec_enet_free_buffers(struct net_device *ndev)
1374 struct fec_enet_private *fep = netdev_priv(ndev);
1376 struct sk_buff *skb;
1377 struct bufdesc *bdp;
1379 bdp = fep->rx_bd_base;
1380 for (i = 0; i < RX_RING_SIZE; i++) {
1381 skb = fep->rx_skbuff[i];
1383 if (bdp->cbd_bufaddr)
1384 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1385 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1388 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1391 bdp = fep->tx_bd_base;
1392 for (i = 0; i < TX_RING_SIZE; i++)
1393 kfree(fep->tx_bounce[i]);
1396 static int fec_enet_alloc_buffers(struct net_device *ndev)
1398 struct fec_enet_private *fep = netdev_priv(ndev);
1400 struct sk_buff *skb;
1401 struct bufdesc *bdp;
1403 bdp = fep->rx_bd_base;
1404 for (i = 0; i < RX_RING_SIZE; i++) {
1405 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1407 fec_enet_free_buffers(ndev);
1410 fep->rx_skbuff[i] = skb;
1412 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1413 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1414 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1416 if (fep->bufdesc_ex) {
1417 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1418 ebdp->cbd_esc = BD_ENET_RX_INT;
1421 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1424 /* Set the last buffer to wrap. */
1425 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1426 bdp->cbd_sc |= BD_SC_WRAP;
1428 bdp = fep->tx_bd_base;
1429 for (i = 0; i < TX_RING_SIZE; i++) {
1430 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1433 bdp->cbd_bufaddr = 0;
1435 if (fep->bufdesc_ex) {
1436 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1437 ebdp->cbd_esc = BD_ENET_TX_INT;
1440 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1443 /* Set the last buffer to wrap. */
1444 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1445 bdp->cbd_sc |= BD_SC_WRAP;
1451 fec_enet_open(struct net_device *ndev)
1453 struct fec_enet_private *fep = netdev_priv(ndev);
1456 napi_enable(&fep->napi);
1458 /* I should reset the ring buffers here, but I don't yet know
1459 * a simple way to do that.
1462 ret = fec_enet_alloc_buffers(ndev);
1466 /* Probe and connect to PHY when open the interface */
1467 ret = fec_enet_mii_probe(ndev);
1469 fec_enet_free_buffers(ndev);
1472 phy_start(fep->phy_dev);
1473 netif_start_queue(ndev);
1479 fec_enet_close(struct net_device *ndev)
1481 struct fec_enet_private *fep = netdev_priv(ndev);
1483 /* Don't know what to do yet. */
1484 napi_disable(&fep->napi);
1486 netif_stop_queue(ndev);
1490 phy_stop(fep->phy_dev);
1491 phy_disconnect(fep->phy_dev);
1494 fec_enet_free_buffers(ndev);
1499 /* Set or clear the multicast filter for this adaptor.
1500 * Skeleton taken from sunlance driver.
1501 * The CPM Ethernet implementation allows Multicast as well as individual
1502 * MAC address filtering. Some of the drivers check to make sure it is
1503 * a group multicast address, and discard those that are not. I guess I
1504 * will do the same for now, but just remove the test if you want
1505 * individual filtering as well (do the upper net layers want or support
1506 * this kind of feature?).
1509 #define HASH_BITS 6 /* #bits in hash */
1510 #define CRC32_POLY 0xEDB88320
1512 static void set_multicast_list(struct net_device *ndev)
1514 struct fec_enet_private *fep = netdev_priv(ndev);
1515 struct netdev_hw_addr *ha;
1516 unsigned int i, bit, data, crc, tmp;
1519 if (ndev->flags & IFF_PROMISC) {
1520 tmp = readl(fep->hwp + FEC_R_CNTRL);
1522 writel(tmp, fep->hwp + FEC_R_CNTRL);
1526 tmp = readl(fep->hwp + FEC_R_CNTRL);
1528 writel(tmp, fep->hwp + FEC_R_CNTRL);
1530 if (ndev->flags & IFF_ALLMULTI) {
1531 /* Catch all multicast addresses, so set the
1534 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1535 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1540 /* Clear filter and add the addresses in hash register
1542 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1543 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1545 netdev_for_each_mc_addr(ha, ndev) {
1546 /* calculate crc32 value of mac address */
1549 for (i = 0; i < ndev->addr_len; i++) {
1551 for (bit = 0; bit < 8; bit++, data >>= 1) {
1553 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1557 /* only upper 6 bits (HASH_BITS) are used
1558 * which point to specific bit in he hash registers
1560 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1563 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1564 tmp |= 1 << (hash - 32);
1565 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1567 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1569 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1574 /* Set a MAC change in hardware. */
1576 fec_set_mac_address(struct net_device *ndev, void *p)
1578 struct fec_enet_private *fep = netdev_priv(ndev);
1579 struct sockaddr *addr = p;
1581 if (!is_valid_ether_addr(addr->sa_data))
1582 return -EADDRNOTAVAIL;
1584 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1586 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1587 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1588 fep->hwp + FEC_ADDR_LOW);
1589 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1590 fep->hwp + FEC_ADDR_HIGH);
1594 #ifdef CONFIG_NET_POLL_CONTROLLER
1596 * fec_poll_controller - FEC Poll controller function
1597 * @dev: The FEC network adapter
1599 * Polled functionality used by netconsole and others in non interrupt mode
1602 static void fec_poll_controller(struct net_device *dev)
1605 struct fec_enet_private *fep = netdev_priv(dev);
1607 for (i = 0; i < FEC_IRQ_NUM; i++) {
1608 if (fep->irq[i] > 0) {
1609 disable_irq(fep->irq[i]);
1610 fec_enet_interrupt(fep->irq[i], dev);
1611 enable_irq(fep->irq[i]);
1617 static const struct net_device_ops fec_netdev_ops = {
1618 .ndo_open = fec_enet_open,
1619 .ndo_stop = fec_enet_close,
1620 .ndo_start_xmit = fec_enet_start_xmit,
1621 .ndo_set_rx_mode = set_multicast_list,
1622 .ndo_change_mtu = eth_change_mtu,
1623 .ndo_validate_addr = eth_validate_addr,
1624 .ndo_tx_timeout = fec_timeout,
1625 .ndo_set_mac_address = fec_set_mac_address,
1626 .ndo_do_ioctl = fec_enet_ioctl,
1627 #ifdef CONFIG_NET_POLL_CONTROLLER
1628 .ndo_poll_controller = fec_poll_controller,
1633 * XXX: We need to clean up on failure exits here.
1636 static int fec_enet_init(struct net_device *ndev)
1638 struct fec_enet_private *fep = netdev_priv(ndev);
1639 struct bufdesc *cbd_base;
1641 /* Allocate memory for buffer descriptors. */
1642 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1647 memset(cbd_base, 0, PAGE_SIZE);
1648 spin_lock_init(&fep->hw_lock);
1652 /* Get the Ethernet address */
1655 /* Set receive and transmit descriptor base. */
1656 fep->rx_bd_base = cbd_base;
1657 if (fep->bufdesc_ex)
1658 fep->tx_bd_base = (struct bufdesc *)
1659 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
1661 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1663 /* The FEC Ethernet specific entries in the device structure */
1664 ndev->watchdog_timeo = TX_TIMEOUT;
1665 ndev->netdev_ops = &fec_netdev_ops;
1666 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1668 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
1669 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
1671 fec_restart(ndev, 0);
1677 static void fec_reset_phy(struct platform_device *pdev)
1681 struct device_node *np = pdev->dev.of_node;
1686 of_property_read_u32(np, "phy-reset-duration", &msec);
1687 /* A sane reset duration should not be longer than 1s */
1691 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1692 if (!gpio_is_valid(phy_reset))
1695 err = devm_gpio_request_one(&pdev->dev, phy_reset,
1696 GPIOF_OUT_INIT_LOW, "phy-reset");
1698 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
1702 gpio_set_value(phy_reset, 1);
1704 #else /* CONFIG_OF */
1705 static void fec_reset_phy(struct platform_device *pdev)
1708 * In case of platform probe, the reset has been done
1712 #endif /* CONFIG_OF */
1715 fec_probe(struct platform_device *pdev)
1717 struct fec_enet_private *fep;
1718 struct fec_platform_data *pdata;
1719 struct net_device *ndev;
1720 int i, irq, ret = 0;
1722 const struct of_device_id *of_id;
1724 struct pinctrl *pinctrl;
1725 struct regulator *reg_phy;
1727 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1729 pdev->id_entry = of_id->data;
1731 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1735 /* Init network device */
1736 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1740 SET_NETDEV_DEV(ndev, &pdev->dev);
1742 /* setup board info structure */
1743 fep = netdev_priv(ndev);
1745 /* default enable pause frame auto negotiation */
1746 if (pdev->id_entry &&
1747 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
1748 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
1750 fep->hwp = devm_request_and_ioremap(&pdev->dev, r);
1752 fep->dev_id = dev_id++;
1754 fep->bufdesc_ex = 0;
1758 goto failed_ioremap;
1761 platform_set_drvdata(pdev, ndev);
1763 ret = of_get_phy_mode(pdev->dev.of_node);
1765 pdata = pdev->dev.platform_data;
1767 fep->phy_interface = pdata->phy;
1769 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1771 fep->phy_interface = ret;
1774 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1775 if (IS_ERR(pinctrl)) {
1776 ret = PTR_ERR(pinctrl);
1780 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1781 if (IS_ERR(fep->clk_ipg)) {
1782 ret = PTR_ERR(fep->clk_ipg);
1786 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1787 if (IS_ERR(fep->clk_ahb)) {
1788 ret = PTR_ERR(fep->clk_ahb);
1792 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
1794 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
1795 if (IS_ERR(fep->clk_ptp)) {
1796 ret = PTR_ERR(fep->clk_ptp);
1797 fep->bufdesc_ex = 0;
1800 clk_prepare_enable(fep->clk_ahb);
1801 clk_prepare_enable(fep->clk_ipg);
1802 if (!IS_ERR(fep->clk_ptp))
1803 clk_prepare_enable(fep->clk_ptp);
1805 reg_phy = devm_regulator_get(&pdev->dev, "phy");
1806 if (!IS_ERR(reg_phy)) {
1807 ret = regulator_enable(reg_phy);
1810 "Failed to enable phy regulator: %d\n", ret);
1811 goto failed_regulator;
1815 fec_reset_phy(pdev);
1817 if (fep->bufdesc_ex)
1818 fec_ptp_init(ndev, pdev);
1820 ret = fec_enet_init(ndev);
1824 for (i = 0; i < FEC_IRQ_NUM; i++) {
1825 irq = platform_get_irq(pdev, i);
1832 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1835 irq = platform_get_irq(pdev, i);
1836 free_irq(irq, ndev);
1842 ret = fec_enet_mii_init(pdev);
1844 goto failed_mii_init;
1846 /* Carrier starts down, phylib will bring it up */
1847 netif_carrier_off(ndev);
1849 ret = register_netdev(ndev);
1851 goto failed_register;
1853 if (fep->bufdesc_ex && fep->ptp_clock)
1854 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
1859 fec_enet_mii_remove(fep);
1862 for (i = 0; i < FEC_IRQ_NUM; i++) {
1863 irq = platform_get_irq(pdev, i);
1865 free_irq(irq, ndev);
1869 clk_disable_unprepare(fep->clk_ahb);
1870 clk_disable_unprepare(fep->clk_ipg);
1871 if (!IS_ERR(fep->clk_ptp))
1872 clk_disable_unprepare(fep->clk_ptp);
1882 fec_drv_remove(struct platform_device *pdev)
1884 struct net_device *ndev = platform_get_drvdata(pdev);
1885 struct fec_enet_private *fep = netdev_priv(ndev);
1888 unregister_netdev(ndev);
1889 fec_enet_mii_remove(fep);
1890 del_timer_sync(&fep->time_keep);
1891 clk_disable_unprepare(fep->clk_ptp);
1893 ptp_clock_unregister(fep->ptp_clock);
1894 clk_disable_unprepare(fep->clk_ahb);
1895 clk_disable_unprepare(fep->clk_ipg);
1896 for (i = 0; i < FEC_IRQ_NUM; i++) {
1897 int irq = platform_get_irq(pdev, i);
1899 free_irq(irq, ndev);
1903 platform_set_drvdata(pdev, NULL);
1908 #ifdef CONFIG_PM_SLEEP
1910 fec_suspend(struct device *dev)
1912 struct net_device *ndev = dev_get_drvdata(dev);
1913 struct fec_enet_private *fep = netdev_priv(ndev);
1915 if (netif_running(ndev)) {
1917 netif_device_detach(ndev);
1919 clk_disable_unprepare(fep->clk_ahb);
1920 clk_disable_unprepare(fep->clk_ipg);
1926 fec_resume(struct device *dev)
1928 struct net_device *ndev = dev_get_drvdata(dev);
1929 struct fec_enet_private *fep = netdev_priv(ndev);
1931 clk_prepare_enable(fep->clk_ahb);
1932 clk_prepare_enable(fep->clk_ipg);
1933 if (netif_running(ndev)) {
1934 fec_restart(ndev, fep->full_duplex);
1935 netif_device_attach(ndev);
1940 #endif /* CONFIG_PM_SLEEP */
1942 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
1944 static struct platform_driver fec_driver = {
1946 .name = DRIVER_NAME,
1947 .owner = THIS_MODULE,
1949 .of_match_table = fec_dt_ids,
1951 .id_table = fec_devtype,
1953 .remove = fec_drv_remove,
1956 module_platform_driver(fec_driver);
1958 MODULE_LICENSE("GPL");