2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_mdio.h>
56 #include <linux/of_net.h>
57 #include <linux/regulator/consumer.h>
58 #include <linux/if_vlan.h>
59 #include <linux/pinctrl/consumer.h>
60 #include <linux/prefetch.h>
62 #include <asm/cacheflush.h>
66 static void set_multicast_list(struct net_device *ndev);
67 static void fec_enet_itr_coal_init(struct net_device *ndev);
69 #define DRIVER_NAME "fec"
71 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
81 static struct platform_device_id fec_devtype[] = {
83 /* keep it for coldfire */
88 .driver_data = FEC_QUIRK_USE_GASKET,
94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
98 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
99 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
101 .name = "mvf600-fec",
102 .driver_data = FEC_QUIRK_ENET_MAC,
104 .name = "imx6sx-fec",
105 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
106 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
107 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
108 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE,
113 MODULE_DEVICE_TABLE(platform, fec_devtype);
116 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
117 IMX27_FEC, /* runs on i.mx27/35/51 */
124 static const struct of_device_id fec_dt_ids[] = {
125 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
126 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
127 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
128 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
129 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
130 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
133 MODULE_DEVICE_TABLE(of, fec_dt_ids);
135 static unsigned char macaddr[ETH_ALEN];
136 module_param_array(macaddr, byte, NULL, 0);
137 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
139 #if defined(CONFIG_M5272)
141 * Some hardware gets it MAC address out of local flash memory.
142 * if this is non-zero then assume it is the address to get MAC from.
144 #if defined(CONFIG_NETtel)
145 #define FEC_FLASHMAC 0xf0006006
146 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
147 #define FEC_FLASHMAC 0xf0006000
148 #elif defined(CONFIG_CANCam)
149 #define FEC_FLASHMAC 0xf0020000
150 #elif defined (CONFIG_M5272C3)
151 #define FEC_FLASHMAC (0xffe04000 + 4)
152 #elif defined(CONFIG_MOD5272)
153 #define FEC_FLASHMAC 0xffc0406b
155 #define FEC_FLASHMAC 0
157 #endif /* CONFIG_M5272 */
159 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
161 #define PKT_MAXBUF_SIZE 1522
162 #define PKT_MINBUF_SIZE 64
163 #define PKT_MAXBLR_SIZE 1536
165 /* FEC receive acceleration */
166 #define FEC_RACC_IPDIS (1 << 1)
167 #define FEC_RACC_PRODIS (1 << 2)
168 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
171 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
172 * size bits. Other FEC hardware does not, so we need to take that into
173 * account when setting it.
175 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
176 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
177 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
179 #define OPT_FRAME_SIZE 0
182 /* FEC MII MMFR bits definition */
183 #define FEC_MMFR_ST (1 << 30)
184 #define FEC_MMFR_OP_READ (2 << 28)
185 #define FEC_MMFR_OP_WRITE (1 << 28)
186 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
187 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
188 #define FEC_MMFR_TA (2 << 16)
189 #define FEC_MMFR_DATA(v) (v & 0xffff)
191 #define FEC_MII_TIMEOUT 30000 /* us */
193 /* Transmitter timeout */
194 #define TX_TIMEOUT (2 * HZ)
196 #define FEC_PAUSE_FLAG_AUTONEG 0x1
197 #define FEC_PAUSE_FLAG_ENABLE 0x2
199 #define COPYBREAK_DEFAULT 256
201 #define TSO_HEADER_SIZE 128
202 /* Max number of allowed TCP segments for software TSO */
203 #define FEC_MAX_TSO_SEGS 100
204 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
206 #define IS_TSO_HEADER(txq, addr) \
207 ((addr >= txq->tso_hdrs_dma) && \
208 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
213 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
214 struct fec_enet_private *fep,
217 struct bufdesc *new_bd = bdp + 1;
218 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
219 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
220 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
221 struct bufdesc_ex *ex_base;
222 struct bufdesc *base;
225 if (bdp >= txq->tx_bd_base) {
226 base = txq->tx_bd_base;
227 ring_size = txq->tx_ring_size;
228 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
230 base = rxq->rx_bd_base;
231 ring_size = rxq->rx_ring_size;
232 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
236 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
237 ex_base : ex_new_bd);
239 return (new_bd >= (base + ring_size)) ?
244 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
245 struct fec_enet_private *fep,
248 struct bufdesc *new_bd = bdp - 1;
249 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
250 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
251 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
252 struct bufdesc_ex *ex_base;
253 struct bufdesc *base;
256 if (bdp >= txq->tx_bd_base) {
257 base = txq->tx_bd_base;
258 ring_size = txq->tx_ring_size;
259 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
261 base = rxq->rx_bd_base;
262 ring_size = rxq->rx_ring_size;
263 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
267 return (struct bufdesc *)((ex_new_bd < ex_base) ?
268 (ex_new_bd + ring_size) : ex_new_bd);
270 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
273 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
274 struct fec_enet_private *fep)
276 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
279 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
280 struct fec_enet_priv_tx_q *txq)
284 entries = ((const char *)txq->dirty_tx -
285 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
287 return entries > 0 ? entries : entries + txq->tx_ring_size;
290 static void *swap_buffer(void *bufaddr, int len)
293 unsigned int *buf = bufaddr;
295 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
296 *buf = cpu_to_be32(*buf);
301 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
304 unsigned int *src = src_buf;
305 unsigned int *dst = dst_buf;
307 for (i = 0; i < len; i += 4, src++, dst++)
311 static void fec_dump(struct net_device *ndev)
313 struct fec_enet_private *fep = netdev_priv(ndev);
315 struct fec_enet_priv_tx_q *txq;
318 netdev_info(ndev, "TX ring dump\n");
319 pr_info("Nr SC addr len SKB\n");
321 txq = fep->tx_queue[0];
322 bdp = txq->tx_bd_base;
325 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
327 bdp == txq->cur_tx ? 'S' : ' ',
328 bdp == txq->dirty_tx ? 'H' : ' ',
329 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
330 txq->tx_skbuff[index]);
331 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
333 } while (bdp != txq->tx_bd_base);
336 static inline bool is_ipv4_pkt(struct sk_buff *skb)
338 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
342 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
344 /* Only run for packets requiring a checksum. */
345 if (skb->ip_summed != CHECKSUM_PARTIAL)
348 if (unlikely(skb_cow_head(skb, 0)))
351 if (is_ipv4_pkt(skb))
352 ip_hdr(skb)->check = 0;
353 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
359 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
361 struct net_device *ndev)
363 struct fec_enet_private *fep = netdev_priv(ndev);
364 struct bufdesc *bdp = txq->cur_tx;
365 struct bufdesc_ex *ebdp;
366 int nr_frags = skb_shinfo(skb)->nr_frags;
367 unsigned short queue = skb_get_queue_mapping(skb);
369 unsigned short status;
370 unsigned int estatus = 0;
371 skb_frag_t *this_frag;
377 for (frag = 0; frag < nr_frags; frag++) {
378 this_frag = &skb_shinfo(skb)->frags[frag];
379 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
380 ebdp = (struct bufdesc_ex *)bdp;
382 status = bdp->cbd_sc;
383 status &= ~BD_ENET_TX_STATS;
384 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
385 frag_len = skb_shinfo(skb)->frags[frag].size;
387 /* Handle the last BD specially */
388 if (frag == nr_frags - 1) {
389 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
390 if (fep->bufdesc_ex) {
391 estatus |= BD_ENET_TX_INT;
392 if (unlikely(skb_shinfo(skb)->tx_flags &
393 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
394 estatus |= BD_ENET_TX_TS;
398 if (fep->bufdesc_ex) {
399 if (fep->quirks & FEC_QUIRK_HAS_AVB)
400 estatus |= FEC_TX_BD_FTYPE(queue);
401 if (skb->ip_summed == CHECKSUM_PARTIAL)
402 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
404 ebdp->cbd_esc = estatus;
407 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
409 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
410 if (((unsigned long) bufaddr) & fep->tx_align ||
411 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
412 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
413 bufaddr = txq->tx_bounce[index];
415 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
416 swap_buffer(bufaddr, frag_len);
419 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
421 if (dma_mapping_error(&fep->pdev->dev, addr)) {
422 dev_kfree_skb_any(skb);
424 netdev_err(ndev, "Tx DMA memory map failed\n");
425 goto dma_mapping_error;
428 bdp->cbd_bufaddr = addr;
429 bdp->cbd_datlen = frag_len;
430 bdp->cbd_sc = status;
439 for (i = 0; i < frag; i++) {
440 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
441 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
442 bdp->cbd_datlen, DMA_TO_DEVICE);
447 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
448 struct sk_buff *skb, struct net_device *ndev)
450 struct fec_enet_private *fep = netdev_priv(ndev);
451 int nr_frags = skb_shinfo(skb)->nr_frags;
452 struct bufdesc *bdp, *last_bdp;
455 unsigned short status;
456 unsigned short buflen;
457 unsigned short queue;
458 unsigned int estatus = 0;
463 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
464 if (entries_free < MAX_SKB_FRAGS + 1) {
465 dev_kfree_skb_any(skb);
467 netdev_err(ndev, "NOT enough BD for SG!\n");
471 /* Protocol checksum off-load for TCP and UDP. */
472 if (fec_enet_clear_csum(skb, ndev)) {
473 dev_kfree_skb_any(skb);
477 /* Fill in a Tx ring entry */
479 status = bdp->cbd_sc;
480 status &= ~BD_ENET_TX_STATS;
482 /* Set buffer length and buffer pointer */
484 buflen = skb_headlen(skb);
486 queue = skb_get_queue_mapping(skb);
487 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
488 if (((unsigned long) bufaddr) & fep->tx_align ||
489 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
490 memcpy(txq->tx_bounce[index], skb->data, buflen);
491 bufaddr = txq->tx_bounce[index];
493 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
494 swap_buffer(bufaddr, buflen);
497 /* Push the data cache so the CPM does not get stale memory data. */
498 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
499 if (dma_mapping_error(&fep->pdev->dev, addr)) {
500 dev_kfree_skb_any(skb);
502 netdev_err(ndev, "Tx DMA memory map failed\n");
507 ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
511 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
512 if (fep->bufdesc_ex) {
513 estatus = BD_ENET_TX_INT;
514 if (unlikely(skb_shinfo(skb)->tx_flags &
515 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
516 estatus |= BD_ENET_TX_TS;
520 if (fep->bufdesc_ex) {
522 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
524 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
526 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
528 if (fep->quirks & FEC_QUIRK_HAS_AVB)
529 estatus |= FEC_TX_BD_FTYPE(queue);
531 if (skb->ip_summed == CHECKSUM_PARTIAL)
532 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
535 ebdp->cbd_esc = estatus;
538 last_bdp = txq->cur_tx;
539 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
540 /* Save skb pointer */
541 txq->tx_skbuff[index] = skb;
543 bdp->cbd_datlen = buflen;
544 bdp->cbd_bufaddr = addr;
546 /* Send it on its way. Tell FEC it's ready, interrupt when done,
547 * it's the last BD of the frame, and to put the CRC on the end.
549 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
550 bdp->cbd_sc = status;
552 /* If this was the last BD in the ring, start at the beginning again. */
553 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
555 skb_tx_timestamp(skb);
559 /* Trigger transmission start */
560 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
566 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
567 struct net_device *ndev,
568 struct bufdesc *bdp, int index, char *data,
569 int size, bool last_tcp, bool is_last)
571 struct fec_enet_private *fep = netdev_priv(ndev);
572 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
573 unsigned short queue = skb_get_queue_mapping(skb);
574 unsigned short status;
575 unsigned int estatus = 0;
578 status = bdp->cbd_sc;
579 status &= ~BD_ENET_TX_STATS;
581 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
583 if (((unsigned long) data) & fep->tx_align ||
584 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
585 memcpy(txq->tx_bounce[index], data, size);
586 data = txq->tx_bounce[index];
588 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
589 swap_buffer(data, size);
592 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
593 if (dma_mapping_error(&fep->pdev->dev, addr)) {
594 dev_kfree_skb_any(skb);
596 netdev_err(ndev, "Tx DMA memory map failed\n");
597 return NETDEV_TX_BUSY;
600 bdp->cbd_datlen = size;
601 bdp->cbd_bufaddr = addr;
603 if (fep->bufdesc_ex) {
604 if (fep->quirks & FEC_QUIRK_HAS_AVB)
605 estatus |= FEC_TX_BD_FTYPE(queue);
606 if (skb->ip_summed == CHECKSUM_PARTIAL)
607 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
609 ebdp->cbd_esc = estatus;
612 /* Handle the last BD specially */
614 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
616 status |= BD_ENET_TX_INTR;
618 ebdp->cbd_esc |= BD_ENET_TX_INT;
621 bdp->cbd_sc = status;
627 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
628 struct sk_buff *skb, struct net_device *ndev,
629 struct bufdesc *bdp, int index)
631 struct fec_enet_private *fep = netdev_priv(ndev);
632 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
633 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
634 unsigned short queue = skb_get_queue_mapping(skb);
636 unsigned long dmabuf;
637 unsigned short status;
638 unsigned int estatus = 0;
640 status = bdp->cbd_sc;
641 status &= ~BD_ENET_TX_STATS;
642 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
644 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
645 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
646 if (((unsigned long)bufaddr) & fep->tx_align ||
647 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
648 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
649 bufaddr = txq->tx_bounce[index];
651 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
652 swap_buffer(bufaddr, hdr_len);
654 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
655 hdr_len, DMA_TO_DEVICE);
656 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
657 dev_kfree_skb_any(skb);
659 netdev_err(ndev, "Tx DMA memory map failed\n");
660 return NETDEV_TX_BUSY;
664 bdp->cbd_bufaddr = dmabuf;
665 bdp->cbd_datlen = hdr_len;
667 if (fep->bufdesc_ex) {
668 if (fep->quirks & FEC_QUIRK_HAS_AVB)
669 estatus |= FEC_TX_BD_FTYPE(queue);
670 if (skb->ip_summed == CHECKSUM_PARTIAL)
671 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
673 ebdp->cbd_esc = estatus;
676 bdp->cbd_sc = status;
681 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
683 struct net_device *ndev)
685 struct fec_enet_private *fep = netdev_priv(ndev);
686 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
687 int total_len, data_left;
688 struct bufdesc *bdp = txq->cur_tx;
689 unsigned short queue = skb_get_queue_mapping(skb);
691 unsigned int index = 0;
694 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
695 dev_kfree_skb_any(skb);
697 netdev_err(ndev, "NOT enough BD for TSO!\n");
701 /* Protocol checksum off-load for TCP and UDP. */
702 if (fec_enet_clear_csum(skb, ndev)) {
703 dev_kfree_skb_any(skb);
707 /* Initialize the TSO handler, and prepare the first payload */
708 tso_start(skb, &tso);
710 total_len = skb->len - hdr_len;
711 while (total_len > 0) {
714 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
715 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
716 total_len -= data_left;
718 /* prepare packet headers: MAC + IP + TCP */
719 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
720 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
721 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
725 while (data_left > 0) {
728 size = min_t(int, tso.size, data_left);
729 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
730 index = fec_enet_get_bd_index(txq->tx_bd_base,
732 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
741 tso_build_data(skb, &tso, size);
744 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
747 /* Save skb pointer */
748 txq->tx_skbuff[index] = skb;
750 skb_tx_timestamp(skb);
753 /* Trigger transmission start */
754 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
755 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
756 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
757 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
758 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
759 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
764 /* TODO: Release all used data descriptors for TSO */
769 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
771 struct fec_enet_private *fep = netdev_priv(ndev);
773 unsigned short queue;
774 struct fec_enet_priv_tx_q *txq;
775 struct netdev_queue *nq;
778 queue = skb_get_queue_mapping(skb);
779 txq = fep->tx_queue[queue];
780 nq = netdev_get_tx_queue(ndev, queue);
783 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
785 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
789 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
790 if (entries_free <= txq->tx_stop_threshold)
791 netif_tx_stop_queue(nq);
796 /* Init RX & TX buffer descriptors
798 static void fec_enet_bd_init(struct net_device *dev)
800 struct fec_enet_private *fep = netdev_priv(dev);
801 struct fec_enet_priv_tx_q *txq;
802 struct fec_enet_priv_rx_q *rxq;
807 for (q = 0; q < fep->num_rx_queues; q++) {
808 /* Initialize the receive buffer descriptors. */
809 rxq = fep->rx_queue[q];
810 bdp = rxq->rx_bd_base;
812 for (i = 0; i < rxq->rx_ring_size; i++) {
814 /* Initialize the BD for every fragment in the page. */
815 if (bdp->cbd_bufaddr)
816 bdp->cbd_sc = BD_ENET_RX_EMPTY;
819 bdp = fec_enet_get_nextdesc(bdp, fep, q);
822 /* Set the last buffer to wrap */
823 bdp = fec_enet_get_prevdesc(bdp, fep, q);
824 bdp->cbd_sc |= BD_SC_WRAP;
826 rxq->cur_rx = rxq->rx_bd_base;
829 for (q = 0; q < fep->num_tx_queues; q++) {
830 /* ...and the same for transmit */
831 txq = fep->tx_queue[q];
832 bdp = txq->tx_bd_base;
835 for (i = 0; i < txq->tx_ring_size; i++) {
836 /* Initialize the BD for every fragment in the page. */
838 if (txq->tx_skbuff[i]) {
839 dev_kfree_skb_any(txq->tx_skbuff[i]);
840 txq->tx_skbuff[i] = NULL;
842 bdp->cbd_bufaddr = 0;
843 bdp = fec_enet_get_nextdesc(bdp, fep, q);
846 /* Set the last buffer to wrap */
847 bdp = fec_enet_get_prevdesc(bdp, fep, q);
848 bdp->cbd_sc |= BD_SC_WRAP;
853 static void fec_enet_active_rxring(struct net_device *ndev)
855 struct fec_enet_private *fep = netdev_priv(ndev);
858 for (i = 0; i < fep->num_rx_queues; i++)
859 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
862 static void fec_enet_enable_ring(struct net_device *ndev)
864 struct fec_enet_private *fep = netdev_priv(ndev);
865 struct fec_enet_priv_tx_q *txq;
866 struct fec_enet_priv_rx_q *rxq;
869 for (i = 0; i < fep->num_rx_queues; i++) {
870 rxq = fep->rx_queue[i];
871 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
875 writel(RCMR_MATCHEN | RCMR_CMP(i),
876 fep->hwp + FEC_RCMR(i));
879 for (i = 0; i < fep->num_tx_queues; i++) {
880 txq = fep->tx_queue[i];
881 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
885 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
886 fep->hwp + FEC_DMA_CFG(i));
890 static void fec_enet_reset_skb(struct net_device *ndev)
892 struct fec_enet_private *fep = netdev_priv(ndev);
893 struct fec_enet_priv_tx_q *txq;
896 for (i = 0; i < fep->num_tx_queues; i++) {
897 txq = fep->tx_queue[i];
899 for (j = 0; j < txq->tx_ring_size; j++) {
900 if (txq->tx_skbuff[j]) {
901 dev_kfree_skb_any(txq->tx_skbuff[j]);
902 txq->tx_skbuff[j] = NULL;
909 * This function is called to start or restart the FEC during a link
910 * change, transmit timeout, or to reconfigure the FEC. The network
911 * packet processing for this device must be stopped before this call.
914 fec_restart(struct net_device *ndev)
916 struct fec_enet_private *fep = netdev_priv(ndev);
919 u32 rcntl = OPT_FRAME_SIZE | 0x04;
920 u32 ecntl = 0x2; /* ETHEREN */
922 /* Whack a reset. We should wait for this.
923 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
924 * instead of reset MAC itself.
926 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
927 writel(0, fep->hwp + FEC_ECNTRL);
929 writel(1, fep->hwp + FEC_ECNTRL);
934 * enet-mac reset will reset mac address registers too,
935 * so need to reconfigure it.
937 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
938 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
939 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
940 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
943 /* Clear any outstanding interrupt. */
944 writel(0xffc00000, fep->hwp + FEC_IEVENT);
946 /* Set maximum receive buffer size. */
947 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
949 fec_enet_bd_init(ndev);
951 fec_enet_enable_ring(ndev);
953 /* Reset tx SKB buffers. */
954 fec_enet_reset_skb(ndev);
956 /* Enable MII mode */
957 if (fep->full_duplex == DUPLEX_FULL) {
959 writel(0x04, fep->hwp + FEC_X_CNTRL);
963 writel(0x0, fep->hwp + FEC_X_CNTRL);
967 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
969 #if !defined(CONFIG_M5272)
970 /* set RX checksum */
971 val = readl(fep->hwp + FEC_RACC);
972 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
973 val |= FEC_RACC_OPTIONS;
975 val &= ~FEC_RACC_OPTIONS;
976 writel(val, fep->hwp + FEC_RACC);
980 * The phy interface and speed need to get configured
981 * differently on enet-mac.
983 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
984 /* Enable flow control and length check */
985 rcntl |= 0x40000000 | 0x00000020;
987 /* RGMII, RMII or MII */
988 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
990 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
995 /* 1G, 100M or 10M */
997 if (fep->phy_dev->speed == SPEED_1000)
999 else if (fep->phy_dev->speed == SPEED_100)
1005 #ifdef FEC_MIIGSK_ENR
1006 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1008 /* disable the gasket and wait */
1009 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1010 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1014 * configure the gasket:
1015 * RMII, 50 MHz, no loopback, no echo
1016 * MII, 25 MHz, no loopback, no echo
1018 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1019 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1020 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1021 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1022 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1024 /* re-enable the gasket */
1025 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1030 #if !defined(CONFIG_M5272)
1031 /* enable pause frame*/
1032 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1033 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1034 fep->phy_dev && fep->phy_dev->pause)) {
1035 rcntl |= FEC_ENET_FCE;
1037 /* set FIFO threshold parameter to reduce overrun */
1038 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1039 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1040 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1041 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1044 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1046 rcntl &= ~FEC_ENET_FCE;
1048 #endif /* !defined(CONFIG_M5272) */
1050 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1052 /* Setup multicast filter. */
1053 set_multicast_list(ndev);
1054 #ifndef CONFIG_M5272
1055 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1056 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1059 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1060 /* enable ENET endian swap */
1062 /* enable ENET store and forward mode */
1063 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1066 if (fep->bufdesc_ex)
1069 #ifndef CONFIG_M5272
1070 /* Enable the MIB statistic event counters */
1071 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1074 /* And last, enable the transmit and receive processing */
1075 writel(ecntl, fep->hwp + FEC_ECNTRL);
1076 fec_enet_active_rxring(ndev);
1078 if (fep->bufdesc_ex)
1079 fec_ptp_start_cyclecounter(ndev);
1081 /* Enable interrupts we wish to service */
1082 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1084 /* Init the interrupt coalescing */
1085 fec_enet_itr_coal_init(ndev);
1090 fec_stop(struct net_device *ndev)
1092 struct fec_enet_private *fep = netdev_priv(ndev);
1093 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1095 /* We cannot expect a graceful transmit stop without link !!! */
1097 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1099 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1100 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1103 /* Whack a reset. We should wait for this.
1104 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1105 * instead of reset MAC itself.
1107 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1108 writel(0, fep->hwp + FEC_ECNTRL);
1110 writel(1, fep->hwp + FEC_ECNTRL);
1113 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1114 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1116 /* We have to keep ENET enabled to have MII interrupt stay working */
1117 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1118 writel(2, fep->hwp + FEC_ECNTRL);
1119 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1125 fec_timeout(struct net_device *ndev)
1127 struct fec_enet_private *fep = netdev_priv(ndev);
1131 ndev->stats.tx_errors++;
1133 schedule_work(&fep->tx_timeout_work);
1136 static void fec_enet_timeout_work(struct work_struct *work)
1138 struct fec_enet_private *fep =
1139 container_of(work, struct fec_enet_private, tx_timeout_work);
1140 struct net_device *ndev = fep->netdev;
1143 if (netif_device_present(ndev) || netif_running(ndev)) {
1144 napi_disable(&fep->napi);
1145 netif_tx_lock_bh(ndev);
1147 netif_wake_queue(ndev);
1148 netif_tx_unlock_bh(ndev);
1149 napi_enable(&fep->napi);
1155 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1156 struct skb_shared_hwtstamps *hwtstamps)
1158 unsigned long flags;
1161 spin_lock_irqsave(&fep->tmreg_lock, flags);
1162 ns = timecounter_cyc2time(&fep->tc, ts);
1163 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1165 memset(hwtstamps, 0, sizeof(*hwtstamps));
1166 hwtstamps->hwtstamp = ns_to_ktime(ns);
1170 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1172 struct fec_enet_private *fep;
1173 struct bufdesc *bdp;
1174 unsigned short status;
1175 struct sk_buff *skb;
1176 struct fec_enet_priv_tx_q *txq;
1177 struct netdev_queue *nq;
1181 fep = netdev_priv(ndev);
1183 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1185 txq = fep->tx_queue[queue_id];
1186 /* get next bdp of dirty_tx */
1187 nq = netdev_get_tx_queue(ndev, queue_id);
1188 bdp = txq->dirty_tx;
1190 /* get next bdp of dirty_tx */
1191 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1193 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
1195 /* current queue is empty */
1196 if (bdp == txq->cur_tx)
1199 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
1201 skb = txq->tx_skbuff[index];
1202 txq->tx_skbuff[index] = NULL;
1203 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
1204 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1205 bdp->cbd_datlen, DMA_TO_DEVICE);
1206 bdp->cbd_bufaddr = 0;
1208 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1212 /* Check for errors. */
1213 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1214 BD_ENET_TX_RL | BD_ENET_TX_UN |
1216 ndev->stats.tx_errors++;
1217 if (status & BD_ENET_TX_HB) /* No heartbeat */
1218 ndev->stats.tx_heartbeat_errors++;
1219 if (status & BD_ENET_TX_LC) /* Late collision */
1220 ndev->stats.tx_window_errors++;
1221 if (status & BD_ENET_TX_RL) /* Retrans limit */
1222 ndev->stats.tx_aborted_errors++;
1223 if (status & BD_ENET_TX_UN) /* Underrun */
1224 ndev->stats.tx_fifo_errors++;
1225 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1226 ndev->stats.tx_carrier_errors++;
1228 ndev->stats.tx_packets++;
1229 ndev->stats.tx_bytes += skb->len;
1232 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1234 struct skb_shared_hwtstamps shhwtstamps;
1235 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1237 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
1238 skb_tstamp_tx(skb, &shhwtstamps);
1241 /* Deferred means some collisions occurred during transmit,
1242 * but we eventually sent the packet OK.
1244 if (status & BD_ENET_TX_DEF)
1245 ndev->stats.collisions++;
1247 /* Free the sk buffer associated with this last transmit */
1248 dev_kfree_skb_any(skb);
1250 txq->dirty_tx = bdp;
1252 /* Update pointer to next buffer descriptor to be transmitted */
1253 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1255 /* Since we have freed up a buffer, the ring is no longer full
1257 if (netif_queue_stopped(ndev)) {
1258 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1259 if (entries_free >= txq->tx_wake_threshold)
1260 netif_tx_wake_queue(nq);
1264 /* ERR006538: Keep the transmitter going */
1265 if (bdp != txq->cur_tx &&
1266 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1267 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1271 fec_enet_tx(struct net_device *ndev)
1273 struct fec_enet_private *fep = netdev_priv(ndev);
1275 /* First process class A queue, then Class B and Best Effort queue */
1276 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1277 clear_bit(queue_id, &fep->work_tx);
1278 fec_enet_tx_queue(ndev, queue_id);
1284 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1286 struct fec_enet_private *fep = netdev_priv(ndev);
1289 off = ((unsigned long)skb->data) & fep->rx_align;
1291 skb_reserve(skb, fep->rx_align + 1 - off);
1293 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1294 FEC_ENET_RX_FRSIZE - fep->rx_align,
1296 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1297 if (net_ratelimit())
1298 netdev_err(ndev, "Rx DMA memory map failed\n");
1305 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1306 struct bufdesc *bdp, u32 length, bool swap)
1308 struct fec_enet_private *fep = netdev_priv(ndev);
1309 struct sk_buff *new_skb;
1311 if (length > fep->rx_copybreak)
1314 new_skb = netdev_alloc_skb(ndev, length);
1318 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1319 FEC_ENET_RX_FRSIZE - fep->rx_align,
1322 memcpy(new_skb->data, (*skb)->data, length);
1324 swap_buffer2(new_skb->data, (*skb)->data, length);
1330 /* During a receive, the cur_rx points to the current incoming buffer.
1331 * When we update through the ring, if the next incoming buffer has
1332 * not been given to the system, we just set the empty indicator,
1333 * effectively tossing the packet.
1336 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1338 struct fec_enet_private *fep = netdev_priv(ndev);
1339 struct fec_enet_priv_rx_q *rxq;
1340 struct bufdesc *bdp;
1341 unsigned short status;
1342 struct sk_buff *skb_new = NULL;
1343 struct sk_buff *skb;
1346 int pkt_received = 0;
1347 struct bufdesc_ex *ebdp = NULL;
1348 bool vlan_packet_rcvd = false;
1352 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1357 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1358 rxq = fep->rx_queue[queue_id];
1360 /* First, grab all of the stats for the incoming packet.
1361 * These get messed up if we get called due to a busy condition.
1365 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1367 if (pkt_received >= budget)
1371 /* Since we have allocated space to hold a complete frame,
1372 * the last indicator should be set.
1374 if ((status & BD_ENET_RX_LAST) == 0)
1375 netdev_err(ndev, "rcv is not +last\n");
1378 /* Check for errors. */
1379 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1380 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1381 ndev->stats.rx_errors++;
1382 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1383 /* Frame too long or too short. */
1384 ndev->stats.rx_length_errors++;
1386 if (status & BD_ENET_RX_NO) /* Frame alignment */
1387 ndev->stats.rx_frame_errors++;
1388 if (status & BD_ENET_RX_CR) /* CRC Error */
1389 ndev->stats.rx_crc_errors++;
1390 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1391 ndev->stats.rx_fifo_errors++;
1394 /* Report late collisions as a frame error.
1395 * On this error, the BD is closed, but we don't know what we
1396 * have in the buffer. So, just drop this frame on the floor.
1398 if (status & BD_ENET_RX_CL) {
1399 ndev->stats.rx_errors++;
1400 ndev->stats.rx_frame_errors++;
1401 goto rx_processing_done;
1404 /* Process the incoming frame. */
1405 ndev->stats.rx_packets++;
1406 pkt_len = bdp->cbd_datlen;
1407 ndev->stats.rx_bytes += pkt_len;
1409 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1410 skb = rxq->rx_skbuff[index];
1412 /* The packet length includes FCS, but we don't want to
1413 * include that when passing upstream as it messes up
1414 * bridging applications.
1416 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1418 if (!is_copybreak) {
1419 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1420 if (unlikely(!skb_new)) {
1421 ndev->stats.rx_dropped++;
1422 goto rx_processing_done;
1424 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1425 FEC_ENET_RX_FRSIZE - fep->rx_align,
1429 prefetch(skb->data - NET_IP_ALIGN);
1430 skb_put(skb, pkt_len - 4);
1432 if (!is_copybreak && need_swap)
1433 swap_buffer(data, pkt_len);
1435 /* Extract the enhanced buffer descriptor */
1437 if (fep->bufdesc_ex)
1438 ebdp = (struct bufdesc_ex *)bdp;
1440 /* If this is a VLAN packet remove the VLAN Tag */
1441 vlan_packet_rcvd = false;
1442 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1443 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1444 /* Push and remove the vlan tag */
1445 struct vlan_hdr *vlan_header =
1446 (struct vlan_hdr *) (data + ETH_HLEN);
1447 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1449 vlan_packet_rcvd = true;
1451 skb_copy_to_linear_data_offset(skb, VLAN_HLEN,
1452 data, (2 * ETH_ALEN));
1453 skb_pull(skb, VLAN_HLEN);
1456 skb->protocol = eth_type_trans(skb, ndev);
1458 /* Get receive timestamp from the skb */
1459 if (fep->hwts_rx_en && fep->bufdesc_ex)
1460 fec_enet_hwtstamp(fep, ebdp->ts,
1461 skb_hwtstamps(skb));
1463 if (fep->bufdesc_ex &&
1464 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1465 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1466 /* don't check it */
1467 skb->ip_summed = CHECKSUM_UNNECESSARY;
1469 skb_checksum_none_assert(skb);
1473 /* Handle received VLAN packets */
1474 if (vlan_packet_rcvd)
1475 __vlan_hwaccel_put_tag(skb,
1479 napi_gro_receive(&fep->napi, skb);
1482 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1483 FEC_ENET_RX_FRSIZE - fep->rx_align,
1486 rxq->rx_skbuff[index] = skb_new;
1487 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1491 /* Clear the status flags for this buffer */
1492 status &= ~BD_ENET_RX_STATS;
1494 /* Mark the buffer empty */
1495 status |= BD_ENET_RX_EMPTY;
1496 bdp->cbd_sc = status;
1498 if (fep->bufdesc_ex) {
1499 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1501 ebdp->cbd_esc = BD_ENET_RX_INT;
1506 /* Update BD pointer to next entry */
1507 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1509 /* Doing this here will keep the FEC running while we process
1510 * incoming frames. On a heavily loaded network, we should be
1511 * able to keep up at the expense of system resources.
1513 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
1516 return pkt_received;
1520 fec_enet_rx(struct net_device *ndev, int budget)
1522 int pkt_received = 0;
1524 struct fec_enet_private *fep = netdev_priv(ndev);
1526 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1527 clear_bit(queue_id, &fep->work_rx);
1528 pkt_received += fec_enet_rx_queue(ndev,
1529 budget - pkt_received, queue_id);
1531 return pkt_received;
1535 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1537 if (int_events == 0)
1540 if (int_events & FEC_ENET_RXF)
1541 fep->work_rx |= (1 << 2);
1542 if (int_events & FEC_ENET_RXF_1)
1543 fep->work_rx |= (1 << 0);
1544 if (int_events & FEC_ENET_RXF_2)
1545 fep->work_rx |= (1 << 1);
1547 if (int_events & FEC_ENET_TXF)
1548 fep->work_tx |= (1 << 2);
1549 if (int_events & FEC_ENET_TXF_1)
1550 fep->work_tx |= (1 << 0);
1551 if (int_events & FEC_ENET_TXF_2)
1552 fep->work_tx |= (1 << 1);
1558 fec_enet_interrupt(int irq, void *dev_id)
1560 struct net_device *ndev = dev_id;
1561 struct fec_enet_private *fep = netdev_priv(ndev);
1562 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF;
1564 irqreturn_t ret = IRQ_NONE;
1566 int_events = readl(fep->hwp + FEC_IEVENT);
1567 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT);
1568 fec_enet_collect_events(fep, int_events);
1570 if (int_events & napi_mask) {
1573 /* Disable the NAPI interrupts */
1574 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1575 napi_schedule(&fep->napi);
1578 if (int_events & FEC_ENET_MII) {
1580 complete(&fep->mdio_done);
1584 fec_ptp_check_pps_event(fep);
1589 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1591 struct net_device *ndev = napi->dev;
1592 struct fec_enet_private *fep = netdev_priv(ndev);
1596 * Clear any pending transmit or receive interrupts before
1597 * processing the rings to avoid racing with the hardware.
1599 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT);
1601 pkts = fec_enet_rx(ndev, budget);
1605 if (pkts < budget) {
1606 napi_complete(napi);
1607 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1612 /* ------------------------------------------------------------------------- */
1613 static void fec_get_mac(struct net_device *ndev)
1615 struct fec_enet_private *fep = netdev_priv(ndev);
1616 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1617 unsigned char *iap, tmpaddr[ETH_ALEN];
1620 * try to get mac address in following order:
1622 * 1) module parameter via kernel command line in form
1623 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1628 * 2) from device tree data
1630 if (!is_valid_ether_addr(iap)) {
1631 struct device_node *np = fep->pdev->dev.of_node;
1633 const char *mac = of_get_mac_address(np);
1635 iap = (unsigned char *) mac;
1640 * 3) from flash or fuse (via platform data)
1642 if (!is_valid_ether_addr(iap)) {
1645 iap = (unsigned char *)FEC_FLASHMAC;
1648 iap = (unsigned char *)&pdata->mac;
1653 * 4) FEC mac registers set by bootloader
1655 if (!is_valid_ether_addr(iap)) {
1656 *((__be32 *) &tmpaddr[0]) =
1657 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1658 *((__be16 *) &tmpaddr[4]) =
1659 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1664 * 5) random mac address
1666 if (!is_valid_ether_addr(iap)) {
1667 /* Report it and use a random ethernet address instead */
1668 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1669 eth_hw_addr_random(ndev);
1670 netdev_info(ndev, "Using random MAC address: %pM\n",
1675 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1677 /* Adjust MAC if using macaddr */
1679 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1682 /* ------------------------------------------------------------------------- */
1687 static void fec_enet_adjust_link(struct net_device *ndev)
1689 struct fec_enet_private *fep = netdev_priv(ndev);
1690 struct phy_device *phy_dev = fep->phy_dev;
1691 int status_change = 0;
1693 /* Prevent a state halted on mii error */
1694 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1695 phy_dev->state = PHY_RESUMING;
1700 * If the netdev is down, or is going down, we're not interested
1701 * in link state events, so just mark our idea of the link as down
1702 * and ignore the event.
1704 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1706 } else if (phy_dev->link) {
1708 fep->link = phy_dev->link;
1712 if (fep->full_duplex != phy_dev->duplex) {
1713 fep->full_duplex = phy_dev->duplex;
1717 if (phy_dev->speed != fep->speed) {
1718 fep->speed = phy_dev->speed;
1722 /* if any of the above changed restart the FEC */
1723 if (status_change) {
1724 napi_disable(&fep->napi);
1725 netif_tx_lock_bh(ndev);
1727 netif_wake_queue(ndev);
1728 netif_tx_unlock_bh(ndev);
1729 napi_enable(&fep->napi);
1733 napi_disable(&fep->napi);
1734 netif_tx_lock_bh(ndev);
1736 netif_tx_unlock_bh(ndev);
1737 napi_enable(&fep->napi);
1738 fep->link = phy_dev->link;
1744 phy_print_status(phy_dev);
1747 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1749 struct fec_enet_private *fep = bus->priv;
1750 unsigned long time_left;
1752 fep->mii_timeout = 0;
1753 init_completion(&fep->mdio_done);
1755 /* start a read op */
1756 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1757 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1758 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1760 /* wait for end of transfer */
1761 time_left = wait_for_completion_timeout(&fep->mdio_done,
1762 usecs_to_jiffies(FEC_MII_TIMEOUT));
1763 if (time_left == 0) {
1764 fep->mii_timeout = 1;
1765 netdev_err(fep->netdev, "MDIO read timeout\n");
1770 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1773 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1776 struct fec_enet_private *fep = bus->priv;
1777 unsigned long time_left;
1779 fep->mii_timeout = 0;
1780 init_completion(&fep->mdio_done);
1782 /* start a write op */
1783 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1784 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1785 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1786 fep->hwp + FEC_MII_DATA);
1788 /* wait for end of transfer */
1789 time_left = wait_for_completion_timeout(&fep->mdio_done,
1790 usecs_to_jiffies(FEC_MII_TIMEOUT));
1791 if (time_left == 0) {
1792 fep->mii_timeout = 1;
1793 netdev_err(fep->netdev, "MDIO write timeout\n");
1800 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1802 struct fec_enet_private *fep = netdev_priv(ndev);
1806 ret = clk_prepare_enable(fep->clk_ahb);
1809 ret = clk_prepare_enable(fep->clk_ipg);
1811 goto failed_clk_ipg;
1812 if (fep->clk_enet_out) {
1813 ret = clk_prepare_enable(fep->clk_enet_out);
1815 goto failed_clk_enet_out;
1818 mutex_lock(&fep->ptp_clk_mutex);
1819 ret = clk_prepare_enable(fep->clk_ptp);
1821 mutex_unlock(&fep->ptp_clk_mutex);
1822 goto failed_clk_ptp;
1824 fep->ptp_clk_on = true;
1826 mutex_unlock(&fep->ptp_clk_mutex);
1829 ret = clk_prepare_enable(fep->clk_ref);
1831 goto failed_clk_ref;
1834 clk_disable_unprepare(fep->clk_ahb);
1835 clk_disable_unprepare(fep->clk_ipg);
1836 if (fep->clk_enet_out)
1837 clk_disable_unprepare(fep->clk_enet_out);
1839 mutex_lock(&fep->ptp_clk_mutex);
1840 clk_disable_unprepare(fep->clk_ptp);
1841 fep->ptp_clk_on = false;
1842 mutex_unlock(&fep->ptp_clk_mutex);
1845 clk_disable_unprepare(fep->clk_ref);
1852 clk_disable_unprepare(fep->clk_ref);
1854 if (fep->clk_enet_out)
1855 clk_disable_unprepare(fep->clk_enet_out);
1856 failed_clk_enet_out:
1857 clk_disable_unprepare(fep->clk_ipg);
1859 clk_disable_unprepare(fep->clk_ahb);
1864 static int fec_enet_mii_probe(struct net_device *ndev)
1866 struct fec_enet_private *fep = netdev_priv(ndev);
1867 struct phy_device *phy_dev = NULL;
1868 char mdio_bus_id[MII_BUS_ID_SIZE];
1869 char phy_name[MII_BUS_ID_SIZE + 3];
1871 int dev_id = fep->dev_id;
1873 fep->phy_dev = NULL;
1875 if (fep->phy_node) {
1876 phy_dev = of_phy_connect(ndev, fep->phy_node,
1877 &fec_enet_adjust_link, 0,
1878 fep->phy_interface);
1880 /* check for attached phy */
1881 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1882 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1884 if (fep->mii_bus->phy_map[phy_id] == NULL)
1886 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1890 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1894 if (phy_id >= PHY_MAX_ADDR) {
1895 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1896 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1900 snprintf(phy_name, sizeof(phy_name),
1901 PHY_ID_FMT, mdio_bus_id, phy_id);
1902 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1903 fep->phy_interface);
1906 if (IS_ERR(phy_dev)) {
1907 netdev_err(ndev, "could not attach to PHY\n");
1908 return PTR_ERR(phy_dev);
1911 /* mask with MAC supported features */
1912 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1913 phy_dev->supported &= PHY_GBIT_FEATURES;
1914 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1915 #if !defined(CONFIG_M5272)
1916 phy_dev->supported |= SUPPORTED_Pause;
1920 phy_dev->supported &= PHY_BASIC_FEATURES;
1922 phy_dev->advertising = phy_dev->supported;
1924 fep->phy_dev = phy_dev;
1926 fep->full_duplex = 0;
1928 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1929 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1935 static int fec_enet_mii_init(struct platform_device *pdev)
1937 static struct mii_bus *fec0_mii_bus;
1938 struct net_device *ndev = platform_get_drvdata(pdev);
1939 struct fec_enet_private *fep = netdev_priv(ndev);
1940 struct device_node *node;
1941 int err = -ENXIO, i;
1944 * The dual fec interfaces are not equivalent with enet-mac.
1945 * Here are the differences:
1947 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1948 * - fec0 acts as the 1588 time master while fec1 is slave
1949 * - external phys can only be configured by fec0
1951 * That is to say fec1 can not work independently. It only works
1952 * when fec0 is working. The reason behind this design is that the
1953 * second interface is added primarily for Switch mode.
1955 * Because of the last point above, both phys are attached on fec0
1956 * mdio interface in board design, and need to be configured by
1959 if ((fep->quirks & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1960 /* fec1 uses fec0 mii_bus */
1961 if (mii_cnt && fec0_mii_bus) {
1962 fep->mii_bus = fec0_mii_bus;
1969 fep->mii_timeout = 0;
1972 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1974 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1975 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1976 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1979 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1980 if (fep->quirks & FEC_QUIRK_ENET_MAC)
1982 fep->phy_speed <<= 1;
1983 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1985 fep->mii_bus = mdiobus_alloc();
1986 if (fep->mii_bus == NULL) {
1991 fep->mii_bus->name = "fec_enet_mii_bus";
1992 fep->mii_bus->read = fec_enet_mdio_read;
1993 fep->mii_bus->write = fec_enet_mdio_write;
1994 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1995 pdev->name, fep->dev_id + 1);
1996 fep->mii_bus->priv = fep;
1997 fep->mii_bus->parent = &pdev->dev;
1999 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
2000 if (!fep->mii_bus->irq) {
2002 goto err_out_free_mdiobus;
2005 for (i = 0; i < PHY_MAX_ADDR; i++)
2006 fep->mii_bus->irq[i] = PHY_POLL;
2008 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2010 err = of_mdiobus_register(fep->mii_bus, node);
2013 err = mdiobus_register(fep->mii_bus);
2017 goto err_out_free_mdio_irq;
2021 /* save fec0 mii_bus */
2022 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2023 fec0_mii_bus = fep->mii_bus;
2027 err_out_free_mdio_irq:
2028 kfree(fep->mii_bus->irq);
2029 err_out_free_mdiobus:
2030 mdiobus_free(fep->mii_bus);
2035 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2037 if (--mii_cnt == 0) {
2038 mdiobus_unregister(fep->mii_bus);
2039 kfree(fep->mii_bus->irq);
2040 mdiobus_free(fep->mii_bus);
2044 static int fec_enet_get_settings(struct net_device *ndev,
2045 struct ethtool_cmd *cmd)
2047 struct fec_enet_private *fep = netdev_priv(ndev);
2048 struct phy_device *phydev = fep->phy_dev;
2053 return phy_ethtool_gset(phydev, cmd);
2056 static int fec_enet_set_settings(struct net_device *ndev,
2057 struct ethtool_cmd *cmd)
2059 struct fec_enet_private *fep = netdev_priv(ndev);
2060 struct phy_device *phydev = fep->phy_dev;
2065 return phy_ethtool_sset(phydev, cmd);
2068 static void fec_enet_get_drvinfo(struct net_device *ndev,
2069 struct ethtool_drvinfo *info)
2071 struct fec_enet_private *fep = netdev_priv(ndev);
2073 strlcpy(info->driver, fep->pdev->dev.driver->name,
2074 sizeof(info->driver));
2075 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2076 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2079 static int fec_enet_get_ts_info(struct net_device *ndev,
2080 struct ethtool_ts_info *info)
2082 struct fec_enet_private *fep = netdev_priv(ndev);
2084 if (fep->bufdesc_ex) {
2086 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2087 SOF_TIMESTAMPING_RX_SOFTWARE |
2088 SOF_TIMESTAMPING_SOFTWARE |
2089 SOF_TIMESTAMPING_TX_HARDWARE |
2090 SOF_TIMESTAMPING_RX_HARDWARE |
2091 SOF_TIMESTAMPING_RAW_HARDWARE;
2093 info->phc_index = ptp_clock_index(fep->ptp_clock);
2095 info->phc_index = -1;
2097 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2098 (1 << HWTSTAMP_TX_ON);
2100 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2101 (1 << HWTSTAMP_FILTER_ALL);
2104 return ethtool_op_get_ts_info(ndev, info);
2108 #if !defined(CONFIG_M5272)
2110 static void fec_enet_get_pauseparam(struct net_device *ndev,
2111 struct ethtool_pauseparam *pause)
2113 struct fec_enet_private *fep = netdev_priv(ndev);
2115 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2116 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2117 pause->rx_pause = pause->tx_pause;
2120 static int fec_enet_set_pauseparam(struct net_device *ndev,
2121 struct ethtool_pauseparam *pause)
2123 struct fec_enet_private *fep = netdev_priv(ndev);
2128 if (pause->tx_pause != pause->rx_pause) {
2130 "hardware only support enable/disable both tx and rx");
2134 fep->pause_flag = 0;
2136 /* tx pause must be same as rx pause */
2137 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2138 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2140 if (pause->rx_pause || pause->autoneg) {
2141 fep->phy_dev->supported |= ADVERTISED_Pause;
2142 fep->phy_dev->advertising |= ADVERTISED_Pause;
2144 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2145 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2148 if (pause->autoneg) {
2149 if (netif_running(ndev))
2151 phy_start_aneg(fep->phy_dev);
2153 if (netif_running(ndev)) {
2154 napi_disable(&fep->napi);
2155 netif_tx_lock_bh(ndev);
2157 netif_wake_queue(ndev);
2158 netif_tx_unlock_bh(ndev);
2159 napi_enable(&fep->napi);
2165 static const struct fec_stat {
2166 char name[ETH_GSTRING_LEN];
2170 { "tx_dropped", RMON_T_DROP },
2171 { "tx_packets", RMON_T_PACKETS },
2172 { "tx_broadcast", RMON_T_BC_PKT },
2173 { "tx_multicast", RMON_T_MC_PKT },
2174 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2175 { "tx_undersize", RMON_T_UNDERSIZE },
2176 { "tx_oversize", RMON_T_OVERSIZE },
2177 { "tx_fragment", RMON_T_FRAG },
2178 { "tx_jabber", RMON_T_JAB },
2179 { "tx_collision", RMON_T_COL },
2180 { "tx_64byte", RMON_T_P64 },
2181 { "tx_65to127byte", RMON_T_P65TO127 },
2182 { "tx_128to255byte", RMON_T_P128TO255 },
2183 { "tx_256to511byte", RMON_T_P256TO511 },
2184 { "tx_512to1023byte", RMON_T_P512TO1023 },
2185 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2186 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2187 { "tx_octets", RMON_T_OCTETS },
2190 { "IEEE_tx_drop", IEEE_T_DROP },
2191 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2192 { "IEEE_tx_1col", IEEE_T_1COL },
2193 { "IEEE_tx_mcol", IEEE_T_MCOL },
2194 { "IEEE_tx_def", IEEE_T_DEF },
2195 { "IEEE_tx_lcol", IEEE_T_LCOL },
2196 { "IEEE_tx_excol", IEEE_T_EXCOL },
2197 { "IEEE_tx_macerr", IEEE_T_MACERR },
2198 { "IEEE_tx_cserr", IEEE_T_CSERR },
2199 { "IEEE_tx_sqe", IEEE_T_SQE },
2200 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2201 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2204 { "rx_packets", RMON_R_PACKETS },
2205 { "rx_broadcast", RMON_R_BC_PKT },
2206 { "rx_multicast", RMON_R_MC_PKT },
2207 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2208 { "rx_undersize", RMON_R_UNDERSIZE },
2209 { "rx_oversize", RMON_R_OVERSIZE },
2210 { "rx_fragment", RMON_R_FRAG },
2211 { "rx_jabber", RMON_R_JAB },
2212 { "rx_64byte", RMON_R_P64 },
2213 { "rx_65to127byte", RMON_R_P65TO127 },
2214 { "rx_128to255byte", RMON_R_P128TO255 },
2215 { "rx_256to511byte", RMON_R_P256TO511 },
2216 { "rx_512to1023byte", RMON_R_P512TO1023 },
2217 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2218 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2219 { "rx_octets", RMON_R_OCTETS },
2222 { "IEEE_rx_drop", IEEE_R_DROP },
2223 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2224 { "IEEE_rx_crc", IEEE_R_CRC },
2225 { "IEEE_rx_align", IEEE_R_ALIGN },
2226 { "IEEE_rx_macerr", IEEE_R_MACERR },
2227 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2228 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2231 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2232 struct ethtool_stats *stats, u64 *data)
2234 struct fec_enet_private *fep = netdev_priv(dev);
2237 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2238 data[i] = readl(fep->hwp + fec_stats[i].offset);
2241 static void fec_enet_get_strings(struct net_device *netdev,
2242 u32 stringset, u8 *data)
2245 switch (stringset) {
2247 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2248 memcpy(data + i * ETH_GSTRING_LEN,
2249 fec_stats[i].name, ETH_GSTRING_LEN);
2254 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2258 return ARRAY_SIZE(fec_stats);
2263 #endif /* !defined(CONFIG_M5272) */
2265 static int fec_enet_nway_reset(struct net_device *dev)
2267 struct fec_enet_private *fep = netdev_priv(dev);
2268 struct phy_device *phydev = fep->phy_dev;
2273 return genphy_restart_aneg(phydev);
2276 /* ITR clock source is enet system clock (clk_ahb).
2277 * TCTT unit is cycle_ns * 64 cycle
2278 * So, the ICTT value = X us / (cycle_ns * 64)
2280 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2282 struct fec_enet_private *fep = netdev_priv(ndev);
2284 return us * (fep->itr_clk_rate / 64000) / 1000;
2287 /* Set threshold for interrupt coalescing */
2288 static void fec_enet_itr_coal_set(struct net_device *ndev)
2290 struct fec_enet_private *fep = netdev_priv(ndev);
2293 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2296 /* Must be greater than zero to avoid unpredictable behavior */
2297 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2298 !fep->tx_time_itr || !fep->tx_pkts_itr)
2301 /* Select enet system clock as Interrupt Coalescing
2302 * timer Clock Source
2304 rx_itr = FEC_ITR_CLK_SEL;
2305 tx_itr = FEC_ITR_CLK_SEL;
2307 /* set ICFT and ICTT */
2308 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2309 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2310 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2311 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2313 rx_itr |= FEC_ITR_EN;
2314 tx_itr |= FEC_ITR_EN;
2316 writel(tx_itr, fep->hwp + FEC_TXIC0);
2317 writel(rx_itr, fep->hwp + FEC_RXIC0);
2318 writel(tx_itr, fep->hwp + FEC_TXIC1);
2319 writel(rx_itr, fep->hwp + FEC_RXIC1);
2320 writel(tx_itr, fep->hwp + FEC_TXIC2);
2321 writel(rx_itr, fep->hwp + FEC_RXIC2);
2325 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2327 struct fec_enet_private *fep = netdev_priv(ndev);
2329 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2332 ec->rx_coalesce_usecs = fep->rx_time_itr;
2333 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2335 ec->tx_coalesce_usecs = fep->tx_time_itr;
2336 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2342 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2344 struct fec_enet_private *fep = netdev_priv(ndev);
2347 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2350 if (ec->rx_max_coalesced_frames > 255) {
2351 pr_err("Rx coalesced frames exceed hardware limiation");
2355 if (ec->tx_max_coalesced_frames > 255) {
2356 pr_err("Tx coalesced frame exceed hardware limiation");
2360 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2361 if (cycle > 0xFFFF) {
2362 pr_err("Rx coalesed usec exceeed hardware limiation");
2366 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2367 if (cycle > 0xFFFF) {
2368 pr_err("Rx coalesed usec exceeed hardware limiation");
2372 fep->rx_time_itr = ec->rx_coalesce_usecs;
2373 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2375 fep->tx_time_itr = ec->tx_coalesce_usecs;
2376 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2378 fec_enet_itr_coal_set(ndev);
2383 static void fec_enet_itr_coal_init(struct net_device *ndev)
2385 struct ethtool_coalesce ec;
2387 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2388 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2390 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2391 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2393 fec_enet_set_coalesce(ndev, &ec);
2396 static int fec_enet_get_tunable(struct net_device *netdev,
2397 const struct ethtool_tunable *tuna,
2400 struct fec_enet_private *fep = netdev_priv(netdev);
2404 case ETHTOOL_RX_COPYBREAK:
2405 *(u32 *)data = fep->rx_copybreak;
2415 static int fec_enet_set_tunable(struct net_device *netdev,
2416 const struct ethtool_tunable *tuna,
2419 struct fec_enet_private *fep = netdev_priv(netdev);
2423 case ETHTOOL_RX_COPYBREAK:
2424 fep->rx_copybreak = *(u32 *)data;
2434 static const struct ethtool_ops fec_enet_ethtool_ops = {
2435 .get_settings = fec_enet_get_settings,
2436 .set_settings = fec_enet_set_settings,
2437 .get_drvinfo = fec_enet_get_drvinfo,
2438 .nway_reset = fec_enet_nway_reset,
2439 .get_link = ethtool_op_get_link,
2440 .get_coalesce = fec_enet_get_coalesce,
2441 .set_coalesce = fec_enet_set_coalesce,
2442 #ifndef CONFIG_M5272
2443 .get_pauseparam = fec_enet_get_pauseparam,
2444 .set_pauseparam = fec_enet_set_pauseparam,
2445 .get_strings = fec_enet_get_strings,
2446 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2447 .get_sset_count = fec_enet_get_sset_count,
2449 .get_ts_info = fec_enet_get_ts_info,
2450 .get_tunable = fec_enet_get_tunable,
2451 .set_tunable = fec_enet_set_tunable,
2454 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2456 struct fec_enet_private *fep = netdev_priv(ndev);
2457 struct phy_device *phydev = fep->phy_dev;
2459 if (!netif_running(ndev))
2465 if (fep->bufdesc_ex) {
2466 if (cmd == SIOCSHWTSTAMP)
2467 return fec_ptp_set(ndev, rq);
2468 if (cmd == SIOCGHWTSTAMP)
2469 return fec_ptp_get(ndev, rq);
2472 return phy_mii_ioctl(phydev, rq, cmd);
2475 static void fec_enet_free_buffers(struct net_device *ndev)
2477 struct fec_enet_private *fep = netdev_priv(ndev);
2479 struct sk_buff *skb;
2480 struct bufdesc *bdp;
2481 struct fec_enet_priv_tx_q *txq;
2482 struct fec_enet_priv_rx_q *rxq;
2485 for (q = 0; q < fep->num_rx_queues; q++) {
2486 rxq = fep->rx_queue[q];
2487 bdp = rxq->rx_bd_base;
2488 for (i = 0; i < rxq->rx_ring_size; i++) {
2489 skb = rxq->rx_skbuff[i];
2490 rxq->rx_skbuff[i] = NULL;
2492 dma_unmap_single(&fep->pdev->dev,
2494 FEC_ENET_RX_FRSIZE - fep->rx_align,
2498 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2502 for (q = 0; q < fep->num_tx_queues; q++) {
2503 txq = fep->tx_queue[q];
2504 bdp = txq->tx_bd_base;
2505 for (i = 0; i < txq->tx_ring_size; i++) {
2506 kfree(txq->tx_bounce[i]);
2507 txq->tx_bounce[i] = NULL;
2508 skb = txq->tx_skbuff[i];
2509 txq->tx_skbuff[i] = NULL;
2515 static void fec_enet_free_queue(struct net_device *ndev)
2517 struct fec_enet_private *fep = netdev_priv(ndev);
2519 struct fec_enet_priv_tx_q *txq;
2521 for (i = 0; i < fep->num_tx_queues; i++)
2522 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2523 txq = fep->tx_queue[i];
2524 dma_free_coherent(NULL,
2525 txq->tx_ring_size * TSO_HEADER_SIZE,
2530 for (i = 0; i < fep->num_rx_queues; i++)
2531 if (fep->rx_queue[i])
2532 kfree(fep->rx_queue[i]);
2534 for (i = 0; i < fep->num_tx_queues; i++)
2535 if (fep->tx_queue[i])
2536 kfree(fep->tx_queue[i]);
2539 static int fec_enet_alloc_queue(struct net_device *ndev)
2541 struct fec_enet_private *fep = netdev_priv(ndev);
2544 struct fec_enet_priv_tx_q *txq;
2546 for (i = 0; i < fep->num_tx_queues; i++) {
2547 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2553 fep->tx_queue[i] = txq;
2554 txq->tx_ring_size = TX_RING_SIZE;
2555 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2557 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2558 txq->tx_wake_threshold =
2559 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2561 txq->tso_hdrs = dma_alloc_coherent(NULL,
2562 txq->tx_ring_size * TSO_HEADER_SIZE,
2565 if (!txq->tso_hdrs) {
2571 for (i = 0; i < fep->num_rx_queues; i++) {
2572 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2574 if (!fep->rx_queue[i]) {
2579 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2580 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2585 fec_enet_free_queue(ndev);
2590 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2592 struct fec_enet_private *fep = netdev_priv(ndev);
2594 struct sk_buff *skb;
2595 struct bufdesc *bdp;
2596 struct fec_enet_priv_rx_q *rxq;
2598 rxq = fep->rx_queue[queue];
2599 bdp = rxq->rx_bd_base;
2600 for (i = 0; i < rxq->rx_ring_size; i++) {
2601 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2605 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2610 rxq->rx_skbuff[i] = skb;
2611 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2613 if (fep->bufdesc_ex) {
2614 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2615 ebdp->cbd_esc = BD_ENET_RX_INT;
2618 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2621 /* Set the last buffer to wrap. */
2622 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2623 bdp->cbd_sc |= BD_SC_WRAP;
2627 fec_enet_free_buffers(ndev);
2632 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2634 struct fec_enet_private *fep = netdev_priv(ndev);
2636 struct bufdesc *bdp;
2637 struct fec_enet_priv_tx_q *txq;
2639 txq = fep->tx_queue[queue];
2640 bdp = txq->tx_bd_base;
2641 for (i = 0; i < txq->tx_ring_size; i++) {
2642 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2643 if (!txq->tx_bounce[i])
2647 bdp->cbd_bufaddr = 0;
2649 if (fep->bufdesc_ex) {
2650 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2651 ebdp->cbd_esc = BD_ENET_TX_INT;
2654 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2657 /* Set the last buffer to wrap. */
2658 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2659 bdp->cbd_sc |= BD_SC_WRAP;
2664 fec_enet_free_buffers(ndev);
2668 static int fec_enet_alloc_buffers(struct net_device *ndev)
2670 struct fec_enet_private *fep = netdev_priv(ndev);
2673 for (i = 0; i < fep->num_rx_queues; i++)
2674 if (fec_enet_alloc_rxq_buffers(ndev, i))
2677 for (i = 0; i < fep->num_tx_queues; i++)
2678 if (fec_enet_alloc_txq_buffers(ndev, i))
2684 fec_enet_open(struct net_device *ndev)
2686 struct fec_enet_private *fep = netdev_priv(ndev);
2689 pinctrl_pm_select_default_state(&fep->pdev->dev);
2690 ret = fec_enet_clk_enable(ndev, true);
2694 /* I should reset the ring buffers here, but I don't yet know
2695 * a simple way to do that.
2698 ret = fec_enet_alloc_buffers(ndev);
2700 goto err_enet_alloc;
2702 /* Probe and connect to PHY when open the interface */
2703 ret = fec_enet_mii_probe(ndev);
2705 goto err_enet_mii_probe;
2708 napi_enable(&fep->napi);
2709 phy_start(fep->phy_dev);
2710 netif_tx_start_all_queues(ndev);
2715 fec_enet_free_buffers(ndev);
2717 fec_enet_clk_enable(ndev, false);
2718 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2723 fec_enet_close(struct net_device *ndev)
2725 struct fec_enet_private *fep = netdev_priv(ndev);
2727 phy_stop(fep->phy_dev);
2729 if (netif_device_present(ndev)) {
2730 napi_disable(&fep->napi);
2731 netif_tx_disable(ndev);
2735 phy_disconnect(fep->phy_dev);
2736 fep->phy_dev = NULL;
2738 fec_enet_clk_enable(ndev, false);
2739 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2740 fec_enet_free_buffers(ndev);
2745 /* Set or clear the multicast filter for this adaptor.
2746 * Skeleton taken from sunlance driver.
2747 * The CPM Ethernet implementation allows Multicast as well as individual
2748 * MAC address filtering. Some of the drivers check to make sure it is
2749 * a group multicast address, and discard those that are not. I guess I
2750 * will do the same for now, but just remove the test if you want
2751 * individual filtering as well (do the upper net layers want or support
2752 * this kind of feature?).
2755 #define HASH_BITS 6 /* #bits in hash */
2756 #define CRC32_POLY 0xEDB88320
2758 static void set_multicast_list(struct net_device *ndev)
2760 struct fec_enet_private *fep = netdev_priv(ndev);
2761 struct netdev_hw_addr *ha;
2762 unsigned int i, bit, data, crc, tmp;
2765 if (ndev->flags & IFF_PROMISC) {
2766 tmp = readl(fep->hwp + FEC_R_CNTRL);
2768 writel(tmp, fep->hwp + FEC_R_CNTRL);
2772 tmp = readl(fep->hwp + FEC_R_CNTRL);
2774 writel(tmp, fep->hwp + FEC_R_CNTRL);
2776 if (ndev->flags & IFF_ALLMULTI) {
2777 /* Catch all multicast addresses, so set the
2780 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2781 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2786 /* Clear filter and add the addresses in hash register
2788 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2789 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2791 netdev_for_each_mc_addr(ha, ndev) {
2792 /* calculate crc32 value of mac address */
2795 for (i = 0; i < ndev->addr_len; i++) {
2797 for (bit = 0; bit < 8; bit++, data >>= 1) {
2799 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2803 /* only upper 6 bits (HASH_BITS) are used
2804 * which point to specific bit in he hash registers
2806 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2809 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2810 tmp |= 1 << (hash - 32);
2811 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2813 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2815 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2820 /* Set a MAC change in hardware. */
2822 fec_set_mac_address(struct net_device *ndev, void *p)
2824 struct fec_enet_private *fep = netdev_priv(ndev);
2825 struct sockaddr *addr = p;
2828 if (!is_valid_ether_addr(addr->sa_data))
2829 return -EADDRNOTAVAIL;
2830 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2833 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2834 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2835 fep->hwp + FEC_ADDR_LOW);
2836 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2837 fep->hwp + FEC_ADDR_HIGH);
2841 #ifdef CONFIG_NET_POLL_CONTROLLER
2843 * fec_poll_controller - FEC Poll controller function
2844 * @dev: The FEC network adapter
2846 * Polled functionality used by netconsole and others in non interrupt mode
2849 static void fec_poll_controller(struct net_device *dev)
2852 struct fec_enet_private *fep = netdev_priv(dev);
2854 for (i = 0; i < FEC_IRQ_NUM; i++) {
2855 if (fep->irq[i] > 0) {
2856 disable_irq(fep->irq[i]);
2857 fec_enet_interrupt(fep->irq[i], dev);
2858 enable_irq(fep->irq[i]);
2864 #define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
2865 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
2866 netdev_features_t features)
2868 struct fec_enet_private *fep = netdev_priv(netdev);
2869 netdev_features_t changed = features ^ netdev->features;
2871 netdev->features = features;
2873 /* Receive checksum has been changed */
2874 if (changed & NETIF_F_RXCSUM) {
2875 if (features & NETIF_F_RXCSUM)
2876 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2878 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2882 static int fec_set_features(struct net_device *netdev,
2883 netdev_features_t features)
2885 struct fec_enet_private *fep = netdev_priv(netdev);
2886 netdev_features_t changed = features ^ netdev->features;
2888 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
2889 napi_disable(&fep->napi);
2890 netif_tx_lock_bh(netdev);
2892 fec_enet_set_netdev_features(netdev, features);
2893 fec_restart(netdev);
2894 netif_tx_wake_all_queues(netdev);
2895 netif_tx_unlock_bh(netdev);
2896 napi_enable(&fep->napi);
2898 fec_enet_set_netdev_features(netdev, features);
2904 static const struct net_device_ops fec_netdev_ops = {
2905 .ndo_open = fec_enet_open,
2906 .ndo_stop = fec_enet_close,
2907 .ndo_start_xmit = fec_enet_start_xmit,
2908 .ndo_set_rx_mode = set_multicast_list,
2909 .ndo_change_mtu = eth_change_mtu,
2910 .ndo_validate_addr = eth_validate_addr,
2911 .ndo_tx_timeout = fec_timeout,
2912 .ndo_set_mac_address = fec_set_mac_address,
2913 .ndo_do_ioctl = fec_enet_ioctl,
2914 #ifdef CONFIG_NET_POLL_CONTROLLER
2915 .ndo_poll_controller = fec_poll_controller,
2917 .ndo_set_features = fec_set_features,
2921 * XXX: We need to clean up on failure exits here.
2924 static int fec_enet_init(struct net_device *ndev)
2926 struct fec_enet_private *fep = netdev_priv(ndev);
2927 struct fec_enet_priv_tx_q *txq;
2928 struct fec_enet_priv_rx_q *rxq;
2929 struct bufdesc *cbd_base;
2934 #if defined(CONFIG_ARM)
2935 fep->rx_align = 0xf;
2936 fep->tx_align = 0xf;
2938 fep->rx_align = 0x3;
2939 fep->tx_align = 0x3;
2942 fec_enet_alloc_queue(ndev);
2944 if (fep->bufdesc_ex)
2945 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2947 fep->bufdesc_size = sizeof(struct bufdesc);
2948 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
2951 /* Allocate memory for buffer descriptors. */
2952 cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma,
2958 memset(cbd_base, 0, bd_size);
2960 /* Get the Ethernet address */
2962 /* make sure MAC we just acquired is programmed into the hw */
2963 fec_set_mac_address(ndev, NULL);
2965 /* Set receive and transmit descriptor base. */
2966 for (i = 0; i < fep->num_rx_queues; i++) {
2967 rxq = fep->rx_queue[i];
2969 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
2970 rxq->bd_dma = bd_dma;
2971 if (fep->bufdesc_ex) {
2972 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
2973 cbd_base = (struct bufdesc *)
2974 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
2976 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
2977 cbd_base += rxq->rx_ring_size;
2981 for (i = 0; i < fep->num_tx_queues; i++) {
2982 txq = fep->tx_queue[i];
2984 txq->tx_bd_base = (struct bufdesc *)cbd_base;
2985 txq->bd_dma = bd_dma;
2986 if (fep->bufdesc_ex) {
2987 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
2988 cbd_base = (struct bufdesc *)
2989 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
2991 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
2992 cbd_base += txq->tx_ring_size;
2997 /* The FEC Ethernet specific entries in the device structure */
2998 ndev->watchdog_timeo = TX_TIMEOUT;
2999 ndev->netdev_ops = &fec_netdev_ops;
3000 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3002 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3003 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3005 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3006 /* enable hw VLAN support */
3007 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3009 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3010 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3012 /* enable hw accelerator */
3013 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3014 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3015 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3018 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3020 fep->rx_align = 0x3f;
3023 ndev->hw_features = ndev->features;
3031 static void fec_reset_phy(struct platform_device *pdev)
3035 struct device_node *np = pdev->dev.of_node;
3040 of_property_read_u32(np, "phy-reset-duration", &msec);
3041 /* A sane reset duration should not be longer than 1s */
3045 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3046 if (!gpio_is_valid(phy_reset))
3049 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3050 GPIOF_OUT_INIT_LOW, "phy-reset");
3052 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3056 gpio_set_value(phy_reset, 1);
3058 #else /* CONFIG_OF */
3059 static void fec_reset_phy(struct platform_device *pdev)
3062 * In case of platform probe, the reset has been done
3066 #endif /* CONFIG_OF */
3069 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3071 struct device_node *np = pdev->dev.of_node;
3074 *num_tx = *num_rx = 1;
3076 if (!np || !of_device_is_available(np))
3079 /* parse the num of tx and rx queues */
3080 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3084 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3088 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3089 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3095 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3096 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3105 fec_probe(struct platform_device *pdev)
3107 struct fec_enet_private *fep;
3108 struct fec_platform_data *pdata;
3109 struct net_device *ndev;
3110 int i, irq, ret = 0;
3112 const struct of_device_id *of_id;
3114 struct device_node *np = pdev->dev.of_node, *phy_node;
3118 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3120 /* Init network device */
3121 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3122 num_tx_qs, num_rx_qs);
3126 SET_NETDEV_DEV(ndev, &pdev->dev);
3128 /* setup board info structure */
3129 fep = netdev_priv(ndev);
3131 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3133 pdev->id_entry = of_id->data;
3134 fep->quirks = pdev->id_entry->driver_data;
3136 fep->num_rx_queues = num_rx_qs;
3137 fep->num_tx_queues = num_tx_qs;
3139 #if !defined(CONFIG_M5272)
3140 /* default enable pause frame auto negotiation */
3141 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3142 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3145 /* Select default pin state */
3146 pinctrl_pm_select_default_state(&pdev->dev);
3148 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3149 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3150 if (IS_ERR(fep->hwp)) {
3151 ret = PTR_ERR(fep->hwp);
3152 goto failed_ioremap;
3156 fep->dev_id = dev_id++;
3158 platform_set_drvdata(pdev, ndev);
3160 phy_node = of_parse_phandle(np, "phy-handle", 0);
3161 if (!phy_node && of_phy_is_fixed_link(np)) {
3162 ret = of_phy_register_fixed_link(np);
3165 "broken fixed-link specification\n");
3168 phy_node = of_node_get(np);
3170 fep->phy_node = phy_node;
3172 ret = of_get_phy_mode(pdev->dev.of_node);
3174 pdata = dev_get_platdata(&pdev->dev);
3176 fep->phy_interface = pdata->phy;
3178 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3180 fep->phy_interface = ret;
3183 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3184 if (IS_ERR(fep->clk_ipg)) {
3185 ret = PTR_ERR(fep->clk_ipg);
3189 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3190 if (IS_ERR(fep->clk_ahb)) {
3191 ret = PTR_ERR(fep->clk_ahb);
3195 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3197 /* enet_out is optional, depends on board */
3198 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3199 if (IS_ERR(fep->clk_enet_out))
3200 fep->clk_enet_out = NULL;
3202 fep->ptp_clk_on = false;
3203 mutex_init(&fep->ptp_clk_mutex);
3205 /* clk_ref is optional, depends on board */
3206 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3207 if (IS_ERR(fep->clk_ref))
3208 fep->clk_ref = NULL;
3210 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3211 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3212 if (IS_ERR(fep->clk_ptp)) {
3213 fep->clk_ptp = NULL;
3214 fep->bufdesc_ex = false;
3217 ret = fec_enet_clk_enable(ndev, true);
3221 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3222 if (!IS_ERR(fep->reg_phy)) {
3223 ret = regulator_enable(fep->reg_phy);
3226 "Failed to enable phy regulator: %d\n", ret);
3227 goto failed_regulator;
3230 fep->reg_phy = NULL;
3233 fec_reset_phy(pdev);
3235 if (fep->bufdesc_ex)
3238 ret = fec_enet_init(ndev);
3242 for (i = 0; i < FEC_IRQ_NUM; i++) {
3243 irq = platform_get_irq(pdev, i);
3250 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3251 0, pdev->name, ndev);
3256 init_completion(&fep->mdio_done);
3257 ret = fec_enet_mii_init(pdev);
3259 goto failed_mii_init;
3261 /* Carrier starts down, phylib will bring it up */
3262 netif_carrier_off(ndev);
3263 fec_enet_clk_enable(ndev, false);
3264 pinctrl_pm_select_sleep_state(&pdev->dev);
3266 ret = register_netdev(ndev);
3268 goto failed_register;
3270 if (fep->bufdesc_ex && fep->ptp_clock)
3271 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3273 fep->rx_copybreak = COPYBREAK_DEFAULT;
3274 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3278 fec_enet_mii_remove(fep);
3283 regulator_disable(fep->reg_phy);
3285 fec_enet_clk_enable(ndev, false);
3288 of_node_put(phy_node);
3296 fec_drv_remove(struct platform_device *pdev)
3298 struct net_device *ndev = platform_get_drvdata(pdev);
3299 struct fec_enet_private *fep = netdev_priv(ndev);
3301 cancel_delayed_work_sync(&fep->time_keep);
3302 cancel_work_sync(&fep->tx_timeout_work);
3303 unregister_netdev(ndev);
3304 fec_enet_mii_remove(fep);
3306 regulator_disable(fep->reg_phy);
3308 ptp_clock_unregister(fep->ptp_clock);
3309 fec_enet_clk_enable(ndev, false);
3310 of_node_put(fep->phy_node);
3316 static int __maybe_unused fec_suspend(struct device *dev)
3318 struct net_device *ndev = dev_get_drvdata(dev);
3319 struct fec_enet_private *fep = netdev_priv(ndev);
3322 if (netif_running(ndev)) {
3323 phy_stop(fep->phy_dev);
3324 napi_disable(&fep->napi);
3325 netif_tx_lock_bh(ndev);
3326 netif_device_detach(ndev);
3327 netif_tx_unlock_bh(ndev);
3329 fec_enet_clk_enable(ndev, false);
3330 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3335 regulator_disable(fep->reg_phy);
3340 static int __maybe_unused fec_resume(struct device *dev)
3342 struct net_device *ndev = dev_get_drvdata(dev);
3343 struct fec_enet_private *fep = netdev_priv(ndev);
3347 ret = regulator_enable(fep->reg_phy);
3353 if (netif_running(ndev)) {
3354 pinctrl_pm_select_default_state(&fep->pdev->dev);
3355 ret = fec_enet_clk_enable(ndev, true);
3361 netif_tx_lock_bh(ndev);
3362 netif_device_attach(ndev);
3363 netif_tx_unlock_bh(ndev);
3364 napi_enable(&fep->napi);
3365 phy_start(fep->phy_dev);
3373 regulator_disable(fep->reg_phy);
3377 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
3379 static struct platform_driver fec_driver = {
3381 .name = DRIVER_NAME,
3382 .owner = THIS_MODULE,
3384 .of_match_table = fec_dt_ids,
3386 .id_table = fec_devtype,
3388 .remove = fec_drv_remove,
3391 module_platform_driver(fec_driver);
3393 MODULE_ALIAS("platform:"DRIVER_NAME);
3394 MODULE_LICENSE("GPL");