2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/spinlock.h>
38 #include <linux/workqueue.h>
39 #include <linux/bitops.h>
41 #include <linux/irq.h>
42 #include <linux/clk.h>
43 #include <linux/platform_device.h>
44 #include <linux/phy.h>
45 #include <linux/fec.h>
47 #include <linux/of_device.h>
48 #include <linux/of_gpio.h>
49 #include <linux/of_net.h>
50 #include <linux/pinctrl/consumer.h>
51 #include <linux/regulator/consumer.h>
53 #include <asm/cacheflush.h>
56 #include <asm/coldfire.h>
57 #include <asm/mcfsim.h>
62 #if defined(CONFIG_ARM)
63 #define FEC_ALIGNMENT 0xf
65 #define FEC_ALIGNMENT 0x3
68 #define DRIVER_NAME "fec"
69 #define FEC_NAPI_WEIGHT 64
71 /* Pause frame feild and FIFO threshold */
72 #define FEC_ENET_FCE (1 << 5)
73 #define FEC_ENET_RSEM_V 0x84
74 #define FEC_ENET_RSFL_V 16
75 #define FEC_ENET_RAEM_V 0x8
76 #define FEC_ENET_RAFL_V 0x8
77 #define FEC_ENET_OPD_V 0xFFF0
79 /* Controller is ENET-MAC */
80 #define FEC_QUIRK_ENET_MAC (1 << 0)
81 /* Controller needs driver to swap frame */
82 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
83 /* Controller uses gasket */
84 #define FEC_QUIRK_USE_GASKET (1 << 2)
85 /* Controller has GBIT support */
86 #define FEC_QUIRK_HAS_GBIT (1 << 3)
87 /* Controller has extend desc buffer */
88 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
90 static struct platform_device_id fec_devtype[] = {
92 /* keep it for coldfire */
97 .driver_data = FEC_QUIRK_USE_GASKET,
103 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
107 FEC_QUIRK_HAS_BUFDESC_EX,
110 .driver_data = FEC_QUIRK_ENET_MAC,
115 MODULE_DEVICE_TABLE(platform, fec_devtype);
118 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
119 IMX27_FEC, /* runs on i.mx27/35/51 */
125 static const struct of_device_id fec_dt_ids[] = {
126 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
127 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
128 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
129 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
130 { .compatible = "fsl,mvf-fec", .data = &fec_devtype[MVF_FEC], },
133 MODULE_DEVICE_TABLE(of, fec_dt_ids);
135 static unsigned char macaddr[ETH_ALEN];
136 module_param_array(macaddr, byte, NULL, 0);
137 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
139 #if defined(CONFIG_M5272)
141 * Some hardware gets it MAC address out of local flash memory.
142 * if this is non-zero then assume it is the address to get MAC from.
144 #if defined(CONFIG_NETtel)
145 #define FEC_FLASHMAC 0xf0006006
146 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
147 #define FEC_FLASHMAC 0xf0006000
148 #elif defined(CONFIG_CANCam)
149 #define FEC_FLASHMAC 0xf0020000
150 #elif defined (CONFIG_M5272C3)
151 #define FEC_FLASHMAC (0xffe04000 + 4)
152 #elif defined(CONFIG_MOD5272)
153 #define FEC_FLASHMAC 0xffc0406b
155 #define FEC_FLASHMAC 0
157 #endif /* CONFIG_M5272 */
159 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
160 #error "FEC: descriptor ring size constants too large"
163 /* Interrupt events/masks. */
164 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
165 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
166 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
167 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
168 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
169 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
170 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
171 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
172 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
173 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
175 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
176 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
178 /* The FEC stores dest/src/type, data, and checksum for receive packets.
180 #define PKT_MAXBUF_SIZE 1518
181 #define PKT_MINBUF_SIZE 64
182 #define PKT_MAXBLR_SIZE 1520
185 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
186 * size bits. Other FEC hardware does not, so we need to take that into
187 * account when setting it.
189 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
190 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
191 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
193 #define OPT_FRAME_SIZE 0
196 /* FEC MII MMFR bits definition */
197 #define FEC_MMFR_ST (1 << 30)
198 #define FEC_MMFR_OP_READ (2 << 28)
199 #define FEC_MMFR_OP_WRITE (1 << 28)
200 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
201 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
202 #define FEC_MMFR_TA (2 << 16)
203 #define FEC_MMFR_DATA(v) (v & 0xffff)
205 #define FEC_MII_TIMEOUT 30000 /* us */
207 /* Transmitter timeout */
208 #define TX_TIMEOUT (2 * HZ)
210 #define FEC_PAUSE_FLAG_AUTONEG 0x1
211 #define FEC_PAUSE_FLAG_ENABLE 0x2
215 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
217 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
219 return (struct bufdesc *)(ex + 1);
224 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
226 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
228 return (struct bufdesc *)(ex - 1);
233 static void *swap_buffer(void *bufaddr, int len)
236 unsigned int *buf = bufaddr;
238 for (i = 0; i < (len + 3) / 4; i++, buf++)
239 *buf = cpu_to_be32(*buf);
245 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
247 struct fec_enet_private *fep = netdev_priv(ndev);
248 const struct platform_device_id *id_entry =
249 platform_get_device_id(fep->pdev);
252 unsigned short status;
256 /* Link is down or autonegotiation is in progress. */
257 return NETDEV_TX_BUSY;
260 /* Fill in a Tx ring entry */
263 status = bdp->cbd_sc;
265 if (status & BD_ENET_TX_READY) {
266 /* Ooops. All transmit buffers are full. Bail out.
267 * This should not happen, since ndev->tbusy should be set.
269 printk("%s: tx queue full!.\n", ndev->name);
270 return NETDEV_TX_BUSY;
273 /* Clear all of the status flags */
274 status &= ~BD_ENET_TX_STATS;
276 /* Set buffer length and buffer pointer */
278 bdp->cbd_datlen = skb->len;
281 * On some FEC implementations data must be aligned on
282 * 4-byte boundaries. Use bounce buffers to copy data
283 * and get it aligned. Ugh.
286 index = (struct bufdesc_ex *)bdp -
287 (struct bufdesc_ex *)fep->tx_bd_base;
289 index = bdp - fep->tx_bd_base;
291 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
292 memcpy(fep->tx_bounce[index], skb->data, skb->len);
293 bufaddr = fep->tx_bounce[index];
297 * Some design made an incorrect assumption on endian mode of
298 * the system that it's running on. As the result, driver has to
299 * swap every frame going to and coming from the controller.
301 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
302 swap_buffer(bufaddr, skb->len);
304 /* Save skb pointer */
305 fep->tx_skbuff[index] = skb;
307 /* Push the data cache so the CPM does not get stale memory
310 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
311 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
313 /* Send it on its way. Tell FEC it's ready, interrupt when done,
314 * it's the last BD of the frame, and to put the CRC on the end.
316 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
317 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
318 bdp->cbd_sc = status;
320 if (fep->bufdesc_ex) {
322 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
324 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
326 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
327 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
330 ebdp->cbd_esc = BD_ENET_TX_INT;
333 /* If this was the last BD in the ring, start at the beginning again. */
334 if (status & BD_ENET_TX_WRAP)
335 bdp = fep->tx_bd_base;
337 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
341 if (fep->cur_tx == fep->dirty_tx)
342 netif_stop_queue(ndev);
344 /* Trigger transmission start */
345 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
347 skb_tx_timestamp(skb);
352 /* Init RX & TX buffer descriptors
354 static void fec_enet_bd_init(struct net_device *dev)
356 struct fec_enet_private *fep = netdev_priv(dev);
360 /* Initialize the receive buffer descriptors. */
361 bdp = fep->rx_bd_base;
362 for (i = 0; i < RX_RING_SIZE; i++) {
364 /* Initialize the BD for every fragment in the page. */
365 if (bdp->cbd_bufaddr)
366 bdp->cbd_sc = BD_ENET_RX_EMPTY;
369 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
372 /* Set the last buffer to wrap */
373 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
374 bdp->cbd_sc |= BD_SC_WRAP;
376 fep->cur_rx = fep->rx_bd_base;
378 /* ...and the same for transmit */
379 bdp = fep->tx_bd_base;
381 for (i = 0; i < TX_RING_SIZE; i++) {
383 /* Initialize the BD for every fragment in the page. */
385 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
386 dev_kfree_skb_any(fep->tx_skbuff[i]);
387 fep->tx_skbuff[i] = NULL;
389 bdp->cbd_bufaddr = 0;
390 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
393 /* Set the last buffer to wrap */
394 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
395 bdp->cbd_sc |= BD_SC_WRAP;
399 /* This function is called to start or restart the FEC during a link
400 * change. This only happens when switching between half and full
404 fec_restart(struct net_device *ndev, int duplex)
406 struct fec_enet_private *fep = netdev_priv(ndev);
407 const struct platform_device_id *id_entry =
408 platform_get_device_id(fep->pdev);
411 u32 rcntl = OPT_FRAME_SIZE | 0x04;
412 u32 ecntl = 0x2; /* ETHEREN */
414 /* Whack a reset. We should wait for this. */
415 writel(1, fep->hwp + FEC_ECNTRL);
419 * enet-mac reset will reset mac address registers too,
420 * so need to reconfigure it.
422 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
423 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
424 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
425 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
428 /* Clear any outstanding interrupt. */
429 writel(0xffc00000, fep->hwp + FEC_IEVENT);
431 /* Reset all multicast. */
432 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
433 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
435 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
436 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
439 /* Set maximum receive buffer size. */
440 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
442 fec_enet_bd_init(ndev);
444 /* Set receive and transmit descriptor base. */
445 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
447 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
448 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
450 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
451 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
454 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
455 if (fep->tx_skbuff[i]) {
456 dev_kfree_skb_any(fep->tx_skbuff[i]);
457 fep->tx_skbuff[i] = NULL;
461 /* Enable MII mode */
464 writel(0x04, fep->hwp + FEC_X_CNTRL);
468 writel(0x0, fep->hwp + FEC_X_CNTRL);
471 fep->full_duplex = duplex;
474 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
477 * The phy interface and speed need to get configured
478 * differently on enet-mac.
480 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
481 /* Enable flow control and length check */
482 rcntl |= 0x40000000 | 0x00000020;
484 /* RGMII, RMII or MII */
485 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
487 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
492 /* 1G, 100M or 10M */
494 if (fep->phy_dev->speed == SPEED_1000)
496 else if (fep->phy_dev->speed == SPEED_100)
502 #ifdef FEC_MIIGSK_ENR
503 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
505 /* disable the gasket and wait */
506 writel(0, fep->hwp + FEC_MIIGSK_ENR);
507 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
511 * configure the gasket:
512 * RMII, 50 MHz, no loopback, no echo
513 * MII, 25 MHz, no loopback, no echo
515 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
516 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
517 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
518 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
519 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
521 /* re-enable the gasket */
522 writel(2, fep->hwp + FEC_MIIGSK_ENR);
527 /* enable pause frame*/
528 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
529 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
530 fep->phy_dev && fep->phy_dev->pause)) {
531 rcntl |= FEC_ENET_FCE;
533 /* set FIFO thresh hold parameter to reduce overrun */
534 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
535 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
536 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
537 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
540 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
542 rcntl &= ~FEC_ENET_FCE;
545 writel(rcntl, fep->hwp + FEC_R_CNTRL);
547 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
548 /* enable ENET endian swap */
550 /* enable ENET store and forward mode */
551 writel(1 << 8, fep->hwp + FEC_X_WMRK);
557 /* And last, enable the transmit and receive processing */
558 writel(ecntl, fep->hwp + FEC_ECNTRL);
559 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
562 fec_ptp_start_cyclecounter(ndev);
564 /* Enable interrupts we wish to service */
565 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
569 fec_stop(struct net_device *ndev)
571 struct fec_enet_private *fep = netdev_priv(ndev);
572 const struct platform_device_id *id_entry =
573 platform_get_device_id(fep->pdev);
574 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
576 /* We cannot expect a graceful transmit stop without link !!! */
578 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
580 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
581 printk("fec_stop : Graceful transmit stop did not complete !\n");
584 /* Whack a reset. We should wait for this. */
585 writel(1, fep->hwp + FEC_ECNTRL);
587 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
588 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
590 /* We have to keep ENET enabled to have MII interrupt stay working */
591 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
592 writel(2, fep->hwp + FEC_ECNTRL);
593 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
599 fec_timeout(struct net_device *ndev)
601 struct fec_enet_private *fep = netdev_priv(ndev);
603 ndev->stats.tx_errors++;
605 fec_restart(ndev, fep->full_duplex);
606 netif_wake_queue(ndev);
610 fec_enet_tx(struct net_device *ndev)
612 struct fec_enet_private *fep;
614 unsigned short status;
618 fep = netdev_priv(ndev);
621 /* get next bdp of dirty_tx */
622 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
623 bdp = fep->tx_bd_base;
625 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
627 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
629 /* current queue is empty */
630 if (bdp == fep->cur_tx)
634 index = (struct bufdesc_ex *)bdp -
635 (struct bufdesc_ex *)fep->tx_bd_base;
637 index = bdp - fep->tx_bd_base;
639 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
640 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
641 bdp->cbd_bufaddr = 0;
643 skb = fep->tx_skbuff[index];
645 /* Check for errors. */
646 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
647 BD_ENET_TX_RL | BD_ENET_TX_UN |
649 ndev->stats.tx_errors++;
650 if (status & BD_ENET_TX_HB) /* No heartbeat */
651 ndev->stats.tx_heartbeat_errors++;
652 if (status & BD_ENET_TX_LC) /* Late collision */
653 ndev->stats.tx_window_errors++;
654 if (status & BD_ENET_TX_RL) /* Retrans limit */
655 ndev->stats.tx_aborted_errors++;
656 if (status & BD_ENET_TX_UN) /* Underrun */
657 ndev->stats.tx_fifo_errors++;
658 if (status & BD_ENET_TX_CSL) /* Carrier lost */
659 ndev->stats.tx_carrier_errors++;
661 ndev->stats.tx_packets++;
664 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
666 struct skb_shared_hwtstamps shhwtstamps;
668 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
670 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
671 spin_lock_irqsave(&fep->tmreg_lock, flags);
672 shhwtstamps.hwtstamp = ns_to_ktime(
673 timecounter_cyc2time(&fep->tc, ebdp->ts));
674 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
675 skb_tstamp_tx(skb, &shhwtstamps);
678 if (status & BD_ENET_TX_READY)
679 printk("HEY! Enet xmit interrupt and TX_READY.\n");
681 /* Deferred means some collisions occurred during transmit,
682 * but we eventually sent the packet OK.
684 if (status & BD_ENET_TX_DEF)
685 ndev->stats.collisions++;
687 /* Free the sk buffer associated with this last transmit */
688 dev_kfree_skb_any(skb);
689 fep->tx_skbuff[index] = NULL;
693 /* Update pointer to next buffer descriptor to be transmitted */
694 if (status & BD_ENET_TX_WRAP)
695 bdp = fep->tx_bd_base;
697 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
699 /* Since we have freed up a buffer, the ring is no longer full
701 if (fep->dirty_tx != fep->cur_tx) {
702 if (netif_queue_stopped(ndev))
703 netif_wake_queue(ndev);
710 /* During a receive, the cur_rx points to the current incoming buffer.
711 * When we update through the ring, if the next incoming buffer has
712 * not been given to the system, we just set the empty indicator,
713 * effectively tossing the packet.
716 fec_enet_rx(struct net_device *ndev, int budget)
718 struct fec_enet_private *fep = netdev_priv(ndev);
719 const struct platform_device_id *id_entry =
720 platform_get_device_id(fep->pdev);
722 unsigned short status;
726 int pkt_received = 0;
732 /* First, grab all of the stats for the incoming packet.
733 * These get messed up if we get called due to a busy condition.
737 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
739 if (pkt_received >= budget)
743 /* Since we have allocated space to hold a complete frame,
744 * the last indicator should be set.
746 if ((status & BD_ENET_RX_LAST) == 0)
747 printk("FEC ENET: rcv is not +last\n");
750 goto rx_processing_done;
752 /* Check for errors. */
753 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
754 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
755 ndev->stats.rx_errors++;
756 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
757 /* Frame too long or too short. */
758 ndev->stats.rx_length_errors++;
760 if (status & BD_ENET_RX_NO) /* Frame alignment */
761 ndev->stats.rx_frame_errors++;
762 if (status & BD_ENET_RX_CR) /* CRC Error */
763 ndev->stats.rx_crc_errors++;
764 if (status & BD_ENET_RX_OV) /* FIFO overrun */
765 ndev->stats.rx_fifo_errors++;
768 /* Report late collisions as a frame error.
769 * On this error, the BD is closed, but we don't know what we
770 * have in the buffer. So, just drop this frame on the floor.
772 if (status & BD_ENET_RX_CL) {
773 ndev->stats.rx_errors++;
774 ndev->stats.rx_frame_errors++;
775 goto rx_processing_done;
778 /* Process the incoming frame. */
779 ndev->stats.rx_packets++;
780 pkt_len = bdp->cbd_datlen;
781 ndev->stats.rx_bytes += pkt_len;
782 data = (__u8*)__va(bdp->cbd_bufaddr);
784 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
785 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
787 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
788 swap_buffer(data, pkt_len);
790 /* This does 16 byte alignment, exactly what we need.
791 * The packet length includes FCS, but we don't want to
792 * include that when passing upstream as it messes up
793 * bridging applications.
795 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
797 if (unlikely(!skb)) {
798 ndev->stats.rx_dropped++;
800 skb_reserve(skb, NET_IP_ALIGN);
801 skb_put(skb, pkt_len - 4); /* Make room */
802 skb_copy_to_linear_data(skb, data, pkt_len - 4);
803 skb->protocol = eth_type_trans(skb, ndev);
805 /* Get receive timestamp from the skb */
806 if (fep->hwts_rx_en && fep->bufdesc_ex) {
807 struct skb_shared_hwtstamps *shhwtstamps =
810 struct bufdesc_ex *ebdp =
811 (struct bufdesc_ex *)bdp;
813 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
815 spin_lock_irqsave(&fep->tmreg_lock, flags);
816 shhwtstamps->hwtstamp = ns_to_ktime(
817 timecounter_cyc2time(&fep->tc, ebdp->ts));
818 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
821 if (!skb_defer_rx_timestamp(skb))
822 napi_gro_receive(&fep->napi, skb);
825 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
826 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
828 /* Clear the status flags for this buffer */
829 status &= ~BD_ENET_RX_STATS;
831 /* Mark the buffer empty */
832 status |= BD_ENET_RX_EMPTY;
833 bdp->cbd_sc = status;
835 if (fep->bufdesc_ex) {
836 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
838 ebdp->cbd_esc = BD_ENET_RX_INT;
843 /* Update BD pointer to next entry */
844 if (status & BD_ENET_RX_WRAP)
845 bdp = fep->rx_bd_base;
847 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
848 /* Doing this here will keep the FEC running while we process
849 * incoming frames. On a heavily loaded network, we should be
850 * able to keep up at the expense of system resources.
852 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
860 fec_enet_interrupt(int irq, void *dev_id)
862 struct net_device *ndev = dev_id;
863 struct fec_enet_private *fep = netdev_priv(ndev);
865 irqreturn_t ret = IRQ_NONE;
868 int_events = readl(fep->hwp + FEC_IEVENT);
869 writel(int_events, fep->hwp + FEC_IEVENT);
871 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
874 /* Disable the RX interrupt */
875 if (napi_schedule_prep(&fep->napi)) {
876 writel(FEC_RX_DISABLED_IMASK,
877 fep->hwp + FEC_IMASK);
878 __napi_schedule(&fep->napi);
882 if (int_events & FEC_ENET_MII) {
884 complete(&fep->mdio_done);
886 } while (int_events);
891 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
893 struct net_device *ndev = napi->dev;
894 int pkts = fec_enet_rx(ndev, budget);
895 struct fec_enet_private *fep = netdev_priv(ndev);
901 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
906 /* ------------------------------------------------------------------------- */
907 static void fec_get_mac(struct net_device *ndev)
909 struct fec_enet_private *fep = netdev_priv(ndev);
910 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
911 unsigned char *iap, tmpaddr[ETH_ALEN];
914 * try to get mac address in following order:
916 * 1) module parameter via kernel command line in form
917 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
922 * 2) from device tree data
924 if (!is_valid_ether_addr(iap)) {
925 struct device_node *np = fep->pdev->dev.of_node;
927 const char *mac = of_get_mac_address(np);
929 iap = (unsigned char *) mac;
934 * 3) from flash or fuse (via platform data)
936 if (!is_valid_ether_addr(iap)) {
939 iap = (unsigned char *)FEC_FLASHMAC;
942 iap = (unsigned char *)&pdata->mac;
947 * 4) FEC mac registers set by bootloader
949 if (!is_valid_ether_addr(iap)) {
950 *((unsigned long *) &tmpaddr[0]) =
951 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
952 *((unsigned short *) &tmpaddr[4]) =
953 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
957 memcpy(ndev->dev_addr, iap, ETH_ALEN);
959 /* Adjust MAC if using macaddr */
961 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
964 /* ------------------------------------------------------------------------- */
969 static void fec_enet_adjust_link(struct net_device *ndev)
971 struct fec_enet_private *fep = netdev_priv(ndev);
972 struct phy_device *phy_dev = fep->phy_dev;
975 int status_change = 0;
977 spin_lock_irqsave(&fep->hw_lock, flags);
979 /* Prevent a state halted on mii error */
980 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
981 phy_dev->state = PHY_RESUMING;
987 fep->link = phy_dev->link;
991 if (fep->full_duplex != phy_dev->duplex)
994 if (phy_dev->speed != fep->speed) {
995 fep->speed = phy_dev->speed;
999 /* if any of the above changed restart the FEC */
1001 fec_restart(ndev, phy_dev->duplex);
1010 spin_unlock_irqrestore(&fep->hw_lock, flags);
1013 phy_print_status(phy_dev);
1016 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1018 struct fec_enet_private *fep = bus->priv;
1019 unsigned long time_left;
1021 fep->mii_timeout = 0;
1022 init_completion(&fep->mdio_done);
1024 /* start a read op */
1025 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1026 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1027 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1029 /* wait for end of transfer */
1030 time_left = wait_for_completion_timeout(&fep->mdio_done,
1031 usecs_to_jiffies(FEC_MII_TIMEOUT));
1032 if (time_left == 0) {
1033 fep->mii_timeout = 1;
1034 printk(KERN_ERR "FEC: MDIO read timeout\n");
1039 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1042 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1045 struct fec_enet_private *fep = bus->priv;
1046 unsigned long time_left;
1048 fep->mii_timeout = 0;
1049 init_completion(&fep->mdio_done);
1051 /* start a write op */
1052 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1053 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1054 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1055 fep->hwp + FEC_MII_DATA);
1057 /* wait for end of transfer */
1058 time_left = wait_for_completion_timeout(&fep->mdio_done,
1059 usecs_to_jiffies(FEC_MII_TIMEOUT));
1060 if (time_left == 0) {
1061 fep->mii_timeout = 1;
1062 printk(KERN_ERR "FEC: MDIO write timeout\n");
1069 static int fec_enet_mdio_reset(struct mii_bus *bus)
1074 static int fec_enet_mii_probe(struct net_device *ndev)
1076 struct fec_enet_private *fep = netdev_priv(ndev);
1077 const struct platform_device_id *id_entry =
1078 platform_get_device_id(fep->pdev);
1079 struct phy_device *phy_dev = NULL;
1080 char mdio_bus_id[MII_BUS_ID_SIZE];
1081 char phy_name[MII_BUS_ID_SIZE + 3];
1083 int dev_id = fep->dev_id;
1085 fep->phy_dev = NULL;
1087 /* check for attached phy */
1088 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1089 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1091 if (fep->mii_bus->phy_map[phy_id] == NULL)
1093 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1097 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1101 if (phy_id >= PHY_MAX_ADDR) {
1103 "%s: no PHY, assuming direct connection to switch\n",
1105 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1109 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1110 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1111 fep->phy_interface);
1112 if (IS_ERR(phy_dev)) {
1113 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
1114 return PTR_ERR(phy_dev);
1117 /* mask with MAC supported features */
1118 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1119 phy_dev->supported &= PHY_GBIT_FEATURES;
1120 phy_dev->supported |= SUPPORTED_Pause;
1123 phy_dev->supported &= PHY_BASIC_FEATURES;
1125 phy_dev->advertising = phy_dev->supported;
1127 fep->phy_dev = phy_dev;
1129 fep->full_duplex = 0;
1132 "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1134 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1140 static int fec_enet_mii_init(struct platform_device *pdev)
1142 static struct mii_bus *fec0_mii_bus;
1143 struct net_device *ndev = platform_get_drvdata(pdev);
1144 struct fec_enet_private *fep = netdev_priv(ndev);
1145 const struct platform_device_id *id_entry =
1146 platform_get_device_id(fep->pdev);
1147 int err = -ENXIO, i;
1150 * The dual fec interfaces are not equivalent with enet-mac.
1151 * Here are the differences:
1153 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1154 * - fec0 acts as the 1588 time master while fec1 is slave
1155 * - external phys can only be configured by fec0
1157 * That is to say fec1 can not work independently. It only works
1158 * when fec0 is working. The reason behind this design is that the
1159 * second interface is added primarily for Switch mode.
1161 * Because of the last point above, both phys are attached on fec0
1162 * mdio interface in board design, and need to be configured by
1165 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1166 /* fec1 uses fec0 mii_bus */
1167 if (mii_cnt && fec0_mii_bus) {
1168 fep->mii_bus = fec0_mii_bus;
1175 fep->mii_timeout = 0;
1178 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1180 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1181 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1182 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1185 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1186 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1188 fep->phy_speed <<= 1;
1189 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1191 fep->mii_bus = mdiobus_alloc();
1192 if (fep->mii_bus == NULL) {
1197 fep->mii_bus->name = "fec_enet_mii_bus";
1198 fep->mii_bus->read = fec_enet_mdio_read;
1199 fep->mii_bus->write = fec_enet_mdio_write;
1200 fep->mii_bus->reset = fec_enet_mdio_reset;
1201 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1202 pdev->name, fep->dev_id + 1);
1203 fep->mii_bus->priv = fep;
1204 fep->mii_bus->parent = &pdev->dev;
1206 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1207 if (!fep->mii_bus->irq) {
1209 goto err_out_free_mdiobus;
1212 for (i = 0; i < PHY_MAX_ADDR; i++)
1213 fep->mii_bus->irq[i] = PHY_POLL;
1215 if (mdiobus_register(fep->mii_bus))
1216 goto err_out_free_mdio_irq;
1220 /* save fec0 mii_bus */
1221 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1222 fec0_mii_bus = fep->mii_bus;
1226 err_out_free_mdio_irq:
1227 kfree(fep->mii_bus->irq);
1228 err_out_free_mdiobus:
1229 mdiobus_free(fep->mii_bus);
1234 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1236 if (--mii_cnt == 0) {
1237 mdiobus_unregister(fep->mii_bus);
1238 kfree(fep->mii_bus->irq);
1239 mdiobus_free(fep->mii_bus);
1243 static int fec_enet_get_settings(struct net_device *ndev,
1244 struct ethtool_cmd *cmd)
1246 struct fec_enet_private *fep = netdev_priv(ndev);
1247 struct phy_device *phydev = fep->phy_dev;
1252 return phy_ethtool_gset(phydev, cmd);
1255 static int fec_enet_set_settings(struct net_device *ndev,
1256 struct ethtool_cmd *cmd)
1258 struct fec_enet_private *fep = netdev_priv(ndev);
1259 struct phy_device *phydev = fep->phy_dev;
1264 return phy_ethtool_sset(phydev, cmd);
1267 static void fec_enet_get_drvinfo(struct net_device *ndev,
1268 struct ethtool_drvinfo *info)
1270 struct fec_enet_private *fep = netdev_priv(ndev);
1272 strlcpy(info->driver, fep->pdev->dev.driver->name,
1273 sizeof(info->driver));
1274 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1275 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1278 static int fec_enet_get_ts_info(struct net_device *ndev,
1279 struct ethtool_ts_info *info)
1281 struct fec_enet_private *fep = netdev_priv(ndev);
1283 if (fep->bufdesc_ex) {
1285 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1286 SOF_TIMESTAMPING_RX_SOFTWARE |
1287 SOF_TIMESTAMPING_SOFTWARE |
1288 SOF_TIMESTAMPING_TX_HARDWARE |
1289 SOF_TIMESTAMPING_RX_HARDWARE |
1290 SOF_TIMESTAMPING_RAW_HARDWARE;
1292 info->phc_index = ptp_clock_index(fep->ptp_clock);
1294 info->phc_index = -1;
1296 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1297 (1 << HWTSTAMP_TX_ON);
1299 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1300 (1 << HWTSTAMP_FILTER_ALL);
1303 return ethtool_op_get_ts_info(ndev, info);
1307 static void fec_enet_get_pauseparam(struct net_device *ndev,
1308 struct ethtool_pauseparam *pause)
1310 struct fec_enet_private *fep = netdev_priv(ndev);
1312 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1313 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1314 pause->rx_pause = pause->tx_pause;
1317 static int fec_enet_set_pauseparam(struct net_device *ndev,
1318 struct ethtool_pauseparam *pause)
1320 struct fec_enet_private *fep = netdev_priv(ndev);
1322 if (pause->tx_pause != pause->rx_pause) {
1324 "hardware only support enable/disable both tx and rx");
1328 fep->pause_flag = 0;
1330 /* tx pause must be same as rx pause */
1331 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1332 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1334 if (pause->rx_pause || pause->autoneg) {
1335 fep->phy_dev->supported |= ADVERTISED_Pause;
1336 fep->phy_dev->advertising |= ADVERTISED_Pause;
1338 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1339 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1342 if (pause->autoneg) {
1343 if (netif_running(ndev))
1345 phy_start_aneg(fep->phy_dev);
1347 if (netif_running(ndev))
1348 fec_restart(ndev, 0);
1353 static const struct ethtool_ops fec_enet_ethtool_ops = {
1354 .get_pauseparam = fec_enet_get_pauseparam,
1355 .set_pauseparam = fec_enet_set_pauseparam,
1356 .get_settings = fec_enet_get_settings,
1357 .set_settings = fec_enet_set_settings,
1358 .get_drvinfo = fec_enet_get_drvinfo,
1359 .get_link = ethtool_op_get_link,
1360 .get_ts_info = fec_enet_get_ts_info,
1363 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1365 struct fec_enet_private *fep = netdev_priv(ndev);
1366 struct phy_device *phydev = fep->phy_dev;
1368 if (!netif_running(ndev))
1374 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
1375 return fec_ptp_ioctl(ndev, rq, cmd);
1377 return phy_mii_ioctl(phydev, rq, cmd);
1380 static void fec_enet_free_buffers(struct net_device *ndev)
1382 struct fec_enet_private *fep = netdev_priv(ndev);
1384 struct sk_buff *skb;
1385 struct bufdesc *bdp;
1387 bdp = fep->rx_bd_base;
1388 for (i = 0; i < RX_RING_SIZE; i++) {
1389 skb = fep->rx_skbuff[i];
1391 if (bdp->cbd_bufaddr)
1392 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1393 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1396 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1399 bdp = fep->tx_bd_base;
1400 for (i = 0; i < TX_RING_SIZE; i++)
1401 kfree(fep->tx_bounce[i]);
1404 static int fec_enet_alloc_buffers(struct net_device *ndev)
1406 struct fec_enet_private *fep = netdev_priv(ndev);
1408 struct sk_buff *skb;
1409 struct bufdesc *bdp;
1411 bdp = fep->rx_bd_base;
1412 for (i = 0; i < RX_RING_SIZE; i++) {
1413 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1415 fec_enet_free_buffers(ndev);
1418 fep->rx_skbuff[i] = skb;
1420 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1421 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1422 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1424 if (fep->bufdesc_ex) {
1425 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1426 ebdp->cbd_esc = BD_ENET_RX_INT;
1429 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1432 /* Set the last buffer to wrap. */
1433 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1434 bdp->cbd_sc |= BD_SC_WRAP;
1436 bdp = fep->tx_bd_base;
1437 for (i = 0; i < TX_RING_SIZE; i++) {
1438 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1441 bdp->cbd_bufaddr = 0;
1443 if (fep->bufdesc_ex) {
1444 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1445 ebdp->cbd_esc = BD_ENET_TX_INT;
1448 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1451 /* Set the last buffer to wrap. */
1452 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1453 bdp->cbd_sc |= BD_SC_WRAP;
1459 fec_enet_open(struct net_device *ndev)
1461 struct fec_enet_private *fep = netdev_priv(ndev);
1464 napi_enable(&fep->napi);
1466 /* I should reset the ring buffers here, but I don't yet know
1467 * a simple way to do that.
1470 ret = fec_enet_alloc_buffers(ndev);
1474 /* Probe and connect to PHY when open the interface */
1475 ret = fec_enet_mii_probe(ndev);
1477 fec_enet_free_buffers(ndev);
1480 phy_start(fep->phy_dev);
1481 netif_start_queue(ndev);
1487 fec_enet_close(struct net_device *ndev)
1489 struct fec_enet_private *fep = netdev_priv(ndev);
1491 /* Don't know what to do yet. */
1492 napi_disable(&fep->napi);
1494 netif_stop_queue(ndev);
1498 phy_stop(fep->phy_dev);
1499 phy_disconnect(fep->phy_dev);
1502 fec_enet_free_buffers(ndev);
1507 /* Set or clear the multicast filter for this adaptor.
1508 * Skeleton taken from sunlance driver.
1509 * The CPM Ethernet implementation allows Multicast as well as individual
1510 * MAC address filtering. Some of the drivers check to make sure it is
1511 * a group multicast address, and discard those that are not. I guess I
1512 * will do the same for now, but just remove the test if you want
1513 * individual filtering as well (do the upper net layers want or support
1514 * this kind of feature?).
1517 #define HASH_BITS 6 /* #bits in hash */
1518 #define CRC32_POLY 0xEDB88320
1520 static void set_multicast_list(struct net_device *ndev)
1522 struct fec_enet_private *fep = netdev_priv(ndev);
1523 struct netdev_hw_addr *ha;
1524 unsigned int i, bit, data, crc, tmp;
1527 if (ndev->flags & IFF_PROMISC) {
1528 tmp = readl(fep->hwp + FEC_R_CNTRL);
1530 writel(tmp, fep->hwp + FEC_R_CNTRL);
1534 tmp = readl(fep->hwp + FEC_R_CNTRL);
1536 writel(tmp, fep->hwp + FEC_R_CNTRL);
1538 if (ndev->flags & IFF_ALLMULTI) {
1539 /* Catch all multicast addresses, so set the
1542 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1543 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1548 /* Clear filter and add the addresses in hash register
1550 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1551 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1553 netdev_for_each_mc_addr(ha, ndev) {
1554 /* calculate crc32 value of mac address */
1557 for (i = 0; i < ndev->addr_len; i++) {
1559 for (bit = 0; bit < 8; bit++, data >>= 1) {
1561 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1565 /* only upper 6 bits (HASH_BITS) are used
1566 * which point to specific bit in he hash registers
1568 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1571 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1572 tmp |= 1 << (hash - 32);
1573 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1575 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1577 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1582 /* Set a MAC change in hardware. */
1584 fec_set_mac_address(struct net_device *ndev, void *p)
1586 struct fec_enet_private *fep = netdev_priv(ndev);
1587 struct sockaddr *addr = p;
1589 if (!is_valid_ether_addr(addr->sa_data))
1590 return -EADDRNOTAVAIL;
1592 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1594 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1595 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1596 fep->hwp + FEC_ADDR_LOW);
1597 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1598 fep->hwp + FEC_ADDR_HIGH);
1602 #ifdef CONFIG_NET_POLL_CONTROLLER
1604 * fec_poll_controller - FEC Poll controller function
1605 * @dev: The FEC network adapter
1607 * Polled functionality used by netconsole and others in non interrupt mode
1610 static void fec_poll_controller(struct net_device *dev)
1613 struct fec_enet_private *fep = netdev_priv(dev);
1615 for (i = 0; i < FEC_IRQ_NUM; i++) {
1616 if (fep->irq[i] > 0) {
1617 disable_irq(fep->irq[i]);
1618 fec_enet_interrupt(fep->irq[i], dev);
1619 enable_irq(fep->irq[i]);
1625 static const struct net_device_ops fec_netdev_ops = {
1626 .ndo_open = fec_enet_open,
1627 .ndo_stop = fec_enet_close,
1628 .ndo_start_xmit = fec_enet_start_xmit,
1629 .ndo_set_rx_mode = set_multicast_list,
1630 .ndo_change_mtu = eth_change_mtu,
1631 .ndo_validate_addr = eth_validate_addr,
1632 .ndo_tx_timeout = fec_timeout,
1633 .ndo_set_mac_address = fec_set_mac_address,
1634 .ndo_do_ioctl = fec_enet_ioctl,
1635 #ifdef CONFIG_NET_POLL_CONTROLLER
1636 .ndo_poll_controller = fec_poll_controller,
1641 * XXX: We need to clean up on failure exits here.
1644 static int fec_enet_init(struct net_device *ndev)
1646 struct fec_enet_private *fep = netdev_priv(ndev);
1647 struct bufdesc *cbd_base;
1649 /* Allocate memory for buffer descriptors. */
1650 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1655 memset(cbd_base, 0, PAGE_SIZE);
1656 spin_lock_init(&fep->hw_lock);
1660 /* Get the Ethernet address */
1663 /* Set receive and transmit descriptor base. */
1664 fep->rx_bd_base = cbd_base;
1665 if (fep->bufdesc_ex)
1666 fep->tx_bd_base = (struct bufdesc *)
1667 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
1669 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1671 /* The FEC Ethernet specific entries in the device structure */
1672 ndev->watchdog_timeo = TX_TIMEOUT;
1673 ndev->netdev_ops = &fec_netdev_ops;
1674 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1676 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
1677 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
1679 fec_restart(ndev, 0);
1685 static void fec_reset_phy(struct platform_device *pdev)
1689 struct device_node *np = pdev->dev.of_node;
1694 of_property_read_u32(np, "phy-reset-duration", &msec);
1695 /* A sane reset duration should not be longer than 1s */
1699 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1700 if (!gpio_is_valid(phy_reset))
1703 err = devm_gpio_request_one(&pdev->dev, phy_reset,
1704 GPIOF_OUT_INIT_LOW, "phy-reset");
1706 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
1710 gpio_set_value(phy_reset, 1);
1712 #else /* CONFIG_OF */
1713 static void fec_reset_phy(struct platform_device *pdev)
1716 * In case of platform probe, the reset has been done
1720 #endif /* CONFIG_OF */
1723 fec_probe(struct platform_device *pdev)
1725 struct fec_enet_private *fep;
1726 struct fec_platform_data *pdata;
1727 struct net_device *ndev;
1728 int i, irq, ret = 0;
1730 const struct of_device_id *of_id;
1732 struct pinctrl *pinctrl;
1733 struct regulator *reg_phy;
1735 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1737 pdev->id_entry = of_id->data;
1739 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1743 /* Init network device */
1744 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1748 SET_NETDEV_DEV(ndev, &pdev->dev);
1750 /* setup board info structure */
1751 fep = netdev_priv(ndev);
1753 /* default enable pause frame auto negotiation */
1754 if (pdev->id_entry &&
1755 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
1756 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
1758 fep->hwp = devm_request_and_ioremap(&pdev->dev, r);
1760 fep->dev_id = dev_id++;
1762 fep->bufdesc_ex = 0;
1766 goto failed_ioremap;
1769 platform_set_drvdata(pdev, ndev);
1771 ret = of_get_phy_mode(pdev->dev.of_node);
1773 pdata = pdev->dev.platform_data;
1775 fep->phy_interface = pdata->phy;
1777 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1779 fep->phy_interface = ret;
1782 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1783 if (IS_ERR(pinctrl)) {
1784 ret = PTR_ERR(pinctrl);
1788 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1789 if (IS_ERR(fep->clk_ipg)) {
1790 ret = PTR_ERR(fep->clk_ipg);
1794 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1795 if (IS_ERR(fep->clk_ahb)) {
1796 ret = PTR_ERR(fep->clk_ahb);
1800 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
1802 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
1803 if (IS_ERR(fep->clk_ptp)) {
1804 ret = PTR_ERR(fep->clk_ptp);
1805 fep->bufdesc_ex = 0;
1808 clk_prepare_enable(fep->clk_ahb);
1809 clk_prepare_enable(fep->clk_ipg);
1810 if (!IS_ERR(fep->clk_ptp))
1811 clk_prepare_enable(fep->clk_ptp);
1813 reg_phy = devm_regulator_get(&pdev->dev, "phy");
1814 if (!IS_ERR(reg_phy)) {
1815 ret = regulator_enable(reg_phy);
1818 "Failed to enable phy regulator: %d\n", ret);
1819 goto failed_regulator;
1823 fec_reset_phy(pdev);
1825 if (fep->bufdesc_ex)
1826 fec_ptp_init(ndev, pdev);
1828 ret = fec_enet_init(ndev);
1832 for (i = 0; i < FEC_IRQ_NUM; i++) {
1833 irq = platform_get_irq(pdev, i);
1840 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1843 irq = platform_get_irq(pdev, i);
1844 free_irq(irq, ndev);
1850 ret = fec_enet_mii_init(pdev);
1852 goto failed_mii_init;
1854 /* Carrier starts down, phylib will bring it up */
1855 netif_carrier_off(ndev);
1857 ret = register_netdev(ndev);
1859 goto failed_register;
1864 fec_enet_mii_remove(fep);
1867 for (i = 0; i < FEC_IRQ_NUM; i++) {
1868 irq = platform_get_irq(pdev, i);
1870 free_irq(irq, ndev);
1874 clk_disable_unprepare(fep->clk_ahb);
1875 clk_disable_unprepare(fep->clk_ipg);
1876 if (!IS_ERR(fep->clk_ptp))
1877 clk_disable_unprepare(fep->clk_ptp);
1887 fec_drv_remove(struct platform_device *pdev)
1889 struct net_device *ndev = platform_get_drvdata(pdev);
1890 struct fec_enet_private *fep = netdev_priv(ndev);
1893 unregister_netdev(ndev);
1894 fec_enet_mii_remove(fep);
1895 del_timer_sync(&fep->time_keep);
1896 clk_disable_unprepare(fep->clk_ptp);
1898 ptp_clock_unregister(fep->ptp_clock);
1899 clk_disable_unprepare(fep->clk_ahb);
1900 clk_disable_unprepare(fep->clk_ipg);
1901 for (i = 0; i < FEC_IRQ_NUM; i++) {
1902 int irq = platform_get_irq(pdev, i);
1904 free_irq(irq, ndev);
1908 platform_set_drvdata(pdev, NULL);
1915 fec_suspend(struct device *dev)
1917 struct net_device *ndev = dev_get_drvdata(dev);
1918 struct fec_enet_private *fep = netdev_priv(ndev);
1920 if (netif_running(ndev)) {
1922 netif_device_detach(ndev);
1924 clk_disable_unprepare(fep->clk_ahb);
1925 clk_disable_unprepare(fep->clk_ipg);
1931 fec_resume(struct device *dev)
1933 struct net_device *ndev = dev_get_drvdata(dev);
1934 struct fec_enet_private *fep = netdev_priv(ndev);
1936 clk_prepare_enable(fep->clk_ahb);
1937 clk_prepare_enable(fep->clk_ipg);
1938 if (netif_running(ndev)) {
1939 fec_restart(ndev, fep->full_duplex);
1940 netif_device_attach(ndev);
1946 static const struct dev_pm_ops fec_pm_ops = {
1947 .suspend = fec_suspend,
1948 .resume = fec_resume,
1949 .freeze = fec_suspend,
1951 .poweroff = fec_suspend,
1952 .restore = fec_resume,
1956 static struct platform_driver fec_driver = {
1958 .name = DRIVER_NAME,
1959 .owner = THIS_MODULE,
1963 .of_match_table = fec_dt_ids,
1965 .id_table = fec_devtype,
1967 .remove = fec_drv_remove,
1970 module_platform_driver(fec_driver);
1972 MODULE_LICENSE("GPL");