drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/of_mdio.h>
  82 #include <linux/of_platform.h>
  83 #include <linux/ip.h>
  84 #include <linux/tcp.h>
  85 #include <linux/udp.h>
  86 #include <linux/in.h>
  87 #include <linux/net_tstamp.h>
  88
  89 #include <asm/io.h>
  90 #include <asm/reg.h>
  91 #include <asm/irq.h>
  92 #include <asm/uaccess.h>
  93 #include <linux/module.h>
  94 #include <linux/dma-mapping.h>
  95 #include <linux/crc32.h>
  96 #include <linux/mii.h>
  97 #include <linux/phy.h>
  98 #include <linux/phy_fixed.h>
  99 #include <linux/of.h>
 100 #include <linux/of_net.h>
 101
 102 #include "gianfar.h"
 103
 104 #define TX_TIMEOUT      (1*HZ)
 105
 106 const char gfar_driver_version[] = "1.3";
 107
 108 static int gfar_enet_open(struct net_device *dev);
 109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 110 static void gfar_reset_task(struct work_struct *work);
 111 static void gfar_timeout(struct net_device *dev);
 112 static int gfar_close(struct net_device *dev);
 113 struct sk_buff *gfar_new_skb(struct net_device *dev);
 114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 115                            struct sk_buff *skb);
 116 static int gfar_set_mac_address(struct net_device *dev);
 117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 118 static irqreturn_t gfar_error(int irq, void *dev_id);
 119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 121 static void adjust_link(struct net_device *dev);
 122 static void init_registers(struct net_device *dev);
 123 static int init_phy(struct net_device *dev);
 124 static int gfar_probe(struct platform_device *ofdev);
 125 static int gfar_remove(struct platform_device *ofdev);
 126 static void free_skb_resources(struct gfar_private *priv);
 127 static void gfar_set_multi(struct net_device *dev);
 128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 129 static void gfar_configure_serdes(struct net_device *dev);
 130 static int gfar_poll(struct napi_struct *napi, int budget);
 131 #ifdef CONFIG_NET_POLL_CONTROLLER
 132 static void gfar_netpoll(struct net_device *dev);
 133 #endif
 134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 136 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 137                                int amount_pull, struct napi_struct *napi);
 138 void gfar_halt(struct net_device *dev);
 139 static void gfar_halt_nodisable(struct net_device *dev);
 140 void gfar_start(struct net_device *dev);
 141 static void gfar_clear_exact_match(struct net_device *dev);
 142 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 143                                   const u8 *addr);
 144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 145
 146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 148 MODULE_LICENSE("GPL");
 149
 150 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 151                             dma_addr_t buf)
 152 {
 153         u32 lstatus;
 154
 155         bdp->bufPtr = buf;
 156
 157         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 158         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 159                 lstatus |= BD_LFLAG(RXBD_WRAP);
 160
 161         eieio();
 162
 163         bdp->lstatus = lstatus;
 164 }
 165
 166 static int gfar_init_bds(struct net_device *ndev)
 167 {
 168         struct gfar_private *priv = netdev_priv(ndev);
 169         struct gfar_priv_tx_q *tx_queue = NULL;
 170         struct gfar_priv_rx_q *rx_queue = NULL;
 171         struct txbd8 *txbdp;
 172         struct rxbd8 *rxbdp;
 173         int i, j;
 174
 175         for (i = 0; i < priv->num_tx_queues; i++) {
 176                 tx_queue = priv->tx_queue[i];
 177                 /* Initialize some variables in our dev structure */
 178                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 179                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 180                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 181                 tx_queue->skb_curtx = 0;
 182                 tx_queue->skb_dirtytx = 0;
 183
 184                 /* Initialize Transmit Descriptor Ring */
 185                 txbdp = tx_queue->tx_bd_base;
 186                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 187                         txbdp->lstatus = 0;
 188                         txbdp->bufPtr = 0;
 189                         txbdp++;
 190                 }
 191
 192                 /* Set the last descriptor in the ring to indicate wrap */
 193                 txbdp--;
 194                 txbdp->status |= TXBD_WRAP;
 195         }
 196
 197         for (i = 0; i < priv->num_rx_queues; i++) {
 198                 rx_queue = priv->rx_queue[i];
 199                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 200                 rx_queue->skb_currx = 0;
 201                 rxbdp = rx_queue->rx_bd_base;
 202
 203                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 204                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 205
 206                         if (skb) {
 207                                 gfar_init_rxbdp(rx_queue, rxbdp,
 208                                                 rxbdp->bufPtr);
 209                         } else {
 210                                 skb = gfar_new_skb(ndev);
 211                                 if (!skb) {
 212                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 213                                         return -ENOMEM;
 214                                 }
 215                                 rx_queue->rx_skbuff[j] = skb;
 216
 217                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 218                         }
 219
 220                         rxbdp++;
 221                 }
 222
 223         }
 224
 225         return 0;
 226 }
 227
 228 static int gfar_alloc_skb_resources(struct net_device *ndev)
 229 {
 230         void *vaddr;
 231         dma_addr_t addr;
 232         int i, j, k;
 233         struct gfar_private *priv = netdev_priv(ndev);
 234         struct device *dev = priv->dev;
 235         struct gfar_priv_tx_q *tx_queue = NULL;
 236         struct gfar_priv_rx_q *rx_queue = NULL;
 237
 238         priv->total_tx_ring_size = 0;
 239         for (i = 0; i < priv->num_tx_queues; i++)
 240                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 241
 242         priv->total_rx_ring_size = 0;
 243         for (i = 0; i < priv->num_rx_queues; i++)
 244                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 245
 246         /* Allocate memory for the buffer descriptors */
 247         vaddr = dma_alloc_coherent(dev,
 248                                    (priv->total_tx_ring_size *
 249                                     sizeof(struct txbd8)) +
 250                                    (priv->total_rx_ring_size *
 251                                     sizeof(struct rxbd8)),
 252                                    &addr, GFP_KERNEL);
 253         if (!vaddr)
 254                 return -ENOMEM;
 255
 256         for (i = 0; i < priv->num_tx_queues; i++) {
 257                 tx_queue = priv->tx_queue[i];
 258                 tx_queue->tx_bd_base = vaddr;
 259                 tx_queue->tx_bd_dma_base = addr;
 260                 tx_queue->dev = ndev;
 261                 /* enet DMA only understands physical addresses */
 262                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 263                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 264         }
 265
 266         /* Start the rx descriptor ring where the tx ring leaves off */
 267         for (i = 0; i < priv->num_rx_queues; i++) {
 268                 rx_queue = priv->rx_queue[i];
 269                 rx_queue->rx_bd_base = vaddr;
 270                 rx_queue->rx_bd_dma_base = addr;
 271                 rx_queue->dev = ndev;
 272                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 273                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 274         }
 275
 276         /* Setup the skbuff rings */
 277         for (i = 0; i < priv->num_tx_queues; i++) {
 278                 tx_queue = priv->tx_queue[i];
 279                 tx_queue->tx_skbuff =
 280                         kmalloc_array(tx_queue->tx_ring_size,
 281                                       sizeof(*tx_queue->tx_skbuff),
 282                                       GFP_KERNEL);
 283                 if (!tx_queue->tx_skbuff)
 284                         goto cleanup;
 285
 286                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 287                         tx_queue->tx_skbuff[k] = NULL;
 288         }
 289
 290         for (i = 0; i < priv->num_rx_queues; i++) {
 291                 rx_queue = priv->rx_queue[i];
 292                 rx_queue->rx_skbuff =
 293                         kmalloc_array(rx_queue->rx_ring_size,
 294                                       sizeof(*rx_queue->rx_skbuff),
 295                                       GFP_KERNEL);
 296                 if (!rx_queue->rx_skbuff)
 297                         goto cleanup;
 298
 299                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 300                         rx_queue->rx_skbuff[j] = NULL;
 301         }
 302
 303         if (gfar_init_bds(ndev))
 304                 goto cleanup;
 305
 306         return 0;
 307
 308 cleanup:
 309         free_skb_resources(priv);
 310         return -ENOMEM;
 311 }
 312
 313 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 314 {
 315         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 316         u32 __iomem *baddr;
 317         int i;
 318
 319         baddr = &regs->tbase0;
 320         for (i = 0; i < priv->num_tx_queues; i++) {
 321                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 322                 baddr += 2;
 323         }
 324
 325         baddr = &regs->rbase0;
 326         for (i = 0; i < priv->num_rx_queues; i++) {
 327                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 328                 baddr += 2;
 329         }
 330 }
 331
 332 static void gfar_init_mac(struct net_device *ndev)
 333 {
 334         struct gfar_private *priv = netdev_priv(ndev);
 335         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 336         u32 rctrl = 0;
 337         u32 tctrl = 0;
 338         u32 attrs = 0;
 339
 340         /* write the tx/rx base registers */
 341         gfar_init_tx_rx_base(priv);
 342
 343         /* Configure the coalescing support */
 344         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 345
 346         /* set this when rx hw offload (TOE) functions are being used */
 347         priv->uses_rxfcb = 0;
 348
 349         if (priv->rx_filer_enable) {
 350                 rctrl |= RCTRL_FILREN;
 351                 /* Program the RIR0 reg with the required distribution */
 352                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 353         }
 354
 355         /* Restore PROMISC mode */
 356         if (ndev->flags & IFF_PROMISC)
 357                 rctrl |= RCTRL_PROM;
 358
 359         if (ndev->features & NETIF_F_RXCSUM) {
 360                 rctrl |= RCTRL_CHECKSUMMING;
 361                 priv->uses_rxfcb = 1;
 362         }
 363
 364         if (priv->extended_hash) {
 365                 rctrl |= RCTRL_EXTHASH;
 366
 367                 gfar_clear_exact_match(ndev);
 368                 rctrl |= RCTRL_EMEN;
 369         }
 370
 371         if (priv->padding) {
 372                 rctrl &= ~RCTRL_PAL_MASK;
 373                 rctrl |= RCTRL_PADDING(priv->padding);
 374         }
 375
 376         /* Insert receive time stamps into padding alignment bytes */
 377         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 378                 rctrl &= ~RCTRL_PAL_MASK;
 379                 rctrl |= RCTRL_PADDING(8);
 380                 priv->padding = 8;
 381         }
 382
 383         /* Enable HW time stamping if requested from user space */
 384         if (priv->hwts_rx_en) {
 385                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 386                 priv->uses_rxfcb = 1;
 387         }
 388
 389         if (ndev->features & NETIF_F_HW_VLAN_RX) {
 390                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 391                 priv->uses_rxfcb = 1;
 392         }
 393
 394         /* Init rctrl based on our settings */
 395         gfar_write(&regs->rctrl, rctrl);
 396
 397         if (ndev->features & NETIF_F_IP_CSUM)
 398                 tctrl |= TCTRL_INIT_CSUM;
 399
 400         if (priv->prio_sched_en)
 401                 tctrl |= TCTRL_TXSCHED_PRIO;
 402         else {
 403                 tctrl |= TCTRL_TXSCHED_WRRS;
 404                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 405                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 406         }
 407
 408         gfar_write(&regs->tctrl, tctrl);
 409
 410         /* Set the extraction length and index */
 411         attrs = ATTRELI_EL(priv->rx_stash_size) |
 412                 ATTRELI_EI(priv->rx_stash_index);
 413
 414         gfar_write(&regs->attreli, attrs);
 415
 416         /* Start with defaults, and add stashing or locking
 417          * depending on the approprate variables
 418          */
 419         attrs = ATTR_INIT_SETTINGS;
 420
 421         if (priv->bd_stash_en)
 422                 attrs |= ATTR_BDSTASH;
 423
 424         if (priv->rx_stash_size != 0)
 425                 attrs |= ATTR_BUFSTASH;
 426
 427         gfar_write(&regs->attr, attrs);
 428
 429         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 430         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 431         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 432 }
 433
 434 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 435 {
 436         struct gfar_private *priv = netdev_priv(dev);
 437         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 438         unsigned long tx_packets = 0, tx_bytes = 0;
 439         int i;
 440
 441         for (i = 0; i < priv->num_rx_queues; i++) {
 442                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 443                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 444                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 445         }
 446
 447         dev->stats.rx_packets = rx_packets;
 448         dev->stats.rx_bytes   = rx_bytes;
 449         dev->stats.rx_dropped = rx_dropped;
 450
 451         for (i = 0; i < priv->num_tx_queues; i++) {
 452                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 453                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 454         }
 455
 456         dev->stats.tx_bytes   = tx_bytes;
 457         dev->stats.tx_packets = tx_packets;
 458
 459         return &dev->stats;
 460 }
 461
 462 static const struct net_device_ops gfar_netdev_ops = {
 463         .ndo_open = gfar_enet_open,
 464         .ndo_start_xmit = gfar_start_xmit,
 465         .ndo_stop = gfar_close,
 466         .ndo_change_mtu = gfar_change_mtu,
 467         .ndo_set_features = gfar_set_features,
 468         .ndo_set_rx_mode = gfar_set_multi,
 469         .ndo_tx_timeout = gfar_timeout,
 470         .ndo_do_ioctl = gfar_ioctl,
 471         .ndo_get_stats = gfar_get_stats,
 472         .ndo_set_mac_address = eth_mac_addr,
 473         .ndo_validate_addr = eth_validate_addr,
 474 #ifdef CONFIG_NET_POLL_CONTROLLER
 475         .ndo_poll_controller = gfar_netpoll,
 476 #endif
 477 };
 478
 479 void lock_rx_qs(struct gfar_private *priv)
 480 {
 481         int i;
 482
 483         for (i = 0; i < priv->num_rx_queues; i++)
 484                 spin_lock(&priv->rx_queue[i]->rxlock);
 485 }
 486
 487 void lock_tx_qs(struct gfar_private *priv)
 488 {
 489         int i;
 490
 491         for (i = 0; i < priv->num_tx_queues; i++)
 492                 spin_lock(&priv->tx_queue[i]->txlock);
 493 }
 494
 495 void unlock_rx_qs(struct gfar_private *priv)
 496 {
 497         int i;
 498
 499         for (i = 0; i < priv->num_rx_queues; i++)
 500                 spin_unlock(&priv->rx_queue[i]->rxlock);
 501 }
 502
 503 void unlock_tx_qs(struct gfar_private *priv)
 504 {
 505         int i;
 506
 507         for (i = 0; i < priv->num_tx_queues; i++)
 508                 spin_unlock(&priv->tx_queue[i]->txlock);
 509 }
 510
 511 static void free_tx_pointers(struct gfar_private *priv)
 512 {
 513         int i;
 514
 515         for (i = 0; i < priv->num_tx_queues; i++)
 516                 kfree(priv->tx_queue[i]);
 517 }
 518
 519 static void free_rx_pointers(struct gfar_private *priv)
 520 {
 521         int i;
 522
 523         for (i = 0; i < priv->num_rx_queues; i++)
 524                 kfree(priv->rx_queue[i]);
 525 }
 526
 527 static void unmap_group_regs(struct gfar_private *priv)
 528 {
 529         int i;
 530
 531         for (i = 0; i < MAXGROUPS; i++)
 532                 if (priv->gfargrp[i].regs)
 533                         iounmap(priv->gfargrp[i].regs);
 534 }
 535
 536 static void free_gfar_dev(struct gfar_private *priv)
 537 {
 538         int i, j;
 539
 540         for (i = 0; i < priv->num_grps; i++)
 541                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 542                         kfree(priv->gfargrp[i].irqinfo[j]);
 543                         priv->gfargrp[i].irqinfo[j] = NULL;
 544                 }
 545
 546         free_netdev(priv->ndev);
 547 }
 548
 549 static void disable_napi(struct gfar_private *priv)
 550 {
 551         int i;
 552
 553         for (i = 0; i < priv->num_grps; i++)
 554                 napi_disable(&priv->gfargrp[i].napi);
 555 }
 556
 557 static void enable_napi(struct gfar_private *priv)
 558 {
 559         int i;
 560
 561         for (i = 0; i < priv->num_grps; i++)
 562                 napi_enable(&priv->gfargrp[i].napi);
 563 }
 564
 565 static int gfar_parse_group(struct device_node *np,
 566                             struct gfar_private *priv, const char *model)
 567 {
 568         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 569         u32 *queue_mask;
 570         int i;
 571
 572         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 573                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 574                                           GFP_KERNEL);
 575                 if (!grp->irqinfo[i])
 576                         return -ENOMEM;
 577         }
 578
 579         grp->regs = of_iomap(np, 0);
 580         if (!grp->regs)
 581                 return -ENOMEM;
 582
 583         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 584
 585         /* If we aren't the FEC we have multiple interrupts */
 586         if (model && strcasecmp(model, "FEC")) {
 587                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 588                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 589                 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
 590                     gfar_irq(grp, RX)->irq == NO_IRQ ||
 591                     gfar_irq(grp, ER)->irq == NO_IRQ)
 592                         return -EINVAL;
 593         }
 594
 595         grp->grp_id = priv->num_grps;
 596         grp->priv = priv;
 597         spin_lock_init(&grp->grplock);
 598         if (priv->mode == MQ_MG_MODE) {
 599                 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
 600                 grp->rx_bit_map = queue_mask ?
 601                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 602                 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
 603                 grp->tx_bit_map = queue_mask ?
 604                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 605         } else {
 606                 grp->rx_bit_map = 0xFF;
 607                 grp->tx_bit_map = 0xFF;
 608         }
 609         priv->num_grps++;
 610
 611         return 0;
 612 }
 613
 614 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 615 {
 616         const char *model;
 617         const char *ctype;
 618         const void *mac_addr;
 619         int err = 0, i;
 620         struct net_device *dev = NULL;
 621         struct gfar_private *priv = NULL;
 622         struct device_node *np = ofdev->dev.of_node;
 623         struct device_node *child = NULL;
 624         const u32 *stash;
 625         const u32 *stash_len;
 626         const u32 *stash_idx;
 627         unsigned int num_tx_qs, num_rx_qs;
 628         u32 *tx_queues, *rx_queues;
 629
 630         if (!np || !of_device_is_available(np))
 631                 return -ENODEV;
 632
 633         /* parse the num of tx and rx queues */
 634         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 635         num_tx_qs = tx_queues ? *tx_queues : 1;
 636
 637         if (num_tx_qs > MAX_TX_QS) {
 638                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 639                        num_tx_qs, MAX_TX_QS);
 640                 pr_err("Cannot do alloc_etherdev, aborting\n");
 641                 return -EINVAL;
 642         }
 643
 644         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 645         num_rx_qs = rx_queues ? *rx_queues : 1;
 646
 647         if (num_rx_qs > MAX_RX_QS) {
 648                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 649                        num_rx_qs, MAX_RX_QS);
 650                 pr_err("Cannot do alloc_etherdev, aborting\n");
 651                 return -EINVAL;
 652         }
 653
 654         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 655         dev = *pdev;
 656         if (NULL == dev)
 657                 return -ENOMEM;
 658
 659         priv = netdev_priv(dev);
 660         priv->ndev = dev;
 661
 662         priv->num_tx_queues = num_tx_qs;
 663         netif_set_real_num_rx_queues(dev, num_rx_qs);
 664         priv->num_rx_queues = num_rx_qs;
 665         priv->num_grps = 0x0;
 666
 667         /* Init Rx queue filer rule set linked list */
 668         INIT_LIST_HEAD(&priv->rx_list.list);
 669         priv->rx_list.count = 0;
 670         mutex_init(&priv->rx_queue_access);
 671
 672         model = of_get_property(np, "model", NULL);
 673
 674         for (i = 0; i < MAXGROUPS; i++)
 675                 priv->gfargrp[i].regs = NULL;
 676
 677         /* Parse and initialize group specific information */
 678         if (of_device_is_compatible(np, "fsl,etsec2")) {
 679                 priv->mode = MQ_MG_MODE;
 680                 for_each_child_of_node(np, child) {
 681                         err = gfar_parse_group(child, priv, model);
 682                         if (err)
 683                                 goto err_grp_init;
 684                 }
 685         } else {
 686                 priv->mode = SQ_SG_MODE;
 687                 err = gfar_parse_group(np, priv, model);
 688                 if (err)
 689                         goto err_grp_init;
 690         }
 691
 692         for (i = 0; i < priv->num_tx_queues; i++)
 693                priv->tx_queue[i] = NULL;
 694         for (i = 0; i < priv->num_rx_queues; i++)
 695                 priv->rx_queue[i] = NULL;
 696
 697         for (i = 0; i < priv->num_tx_queues; i++) {
 698                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 699                                             GFP_KERNEL);
 700                 if (!priv->tx_queue[i]) {
 701                         err = -ENOMEM;
 702                         goto tx_alloc_failed;
 703                 }
 704                 priv->tx_queue[i]->tx_skbuff = NULL;
 705                 priv->tx_queue[i]->qindex = i;
 706                 priv->tx_queue[i]->dev = dev;
 707                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 708         }
 709
 710         for (i = 0; i < priv->num_rx_queues; i++) {
 711                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 712                                             GFP_KERNEL);
 713                 if (!priv->rx_queue[i]) {
 714                         err = -ENOMEM;
 715                         goto rx_alloc_failed;
 716                 }
 717                 priv->rx_queue[i]->rx_skbuff = NULL;
 718                 priv->rx_queue[i]->qindex = i;
 719                 priv->rx_queue[i]->dev = dev;
 720                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 721         }
 722
 723
 724         stash = of_get_property(np, "bd-stash", NULL);
 725
 726         if (stash) {
 727                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 728                 priv->bd_stash_en = 1;
 729         }
 730
 731         stash_len = of_get_property(np, "rx-stash-len", NULL);
 732
 733         if (stash_len)
 734                 priv->rx_stash_size = *stash_len;
 735
 736         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 737
 738         if (stash_idx)
 739                 priv->rx_stash_index = *stash_idx;
 740
 741         if (stash_len || stash_idx)
 742                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 743
 744         mac_addr = of_get_mac_address(np);
 745
 746         if (mac_addr)
 747                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 748
 749         if (model && !strcasecmp(model, "TSEC"))
 750                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 751                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 752                                      FSL_GIANFAR_DEV_HAS_RMON |
 753                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 754
 755         if (model && !strcasecmp(model, "eTSEC"))
 756                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 757                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 758                                      FSL_GIANFAR_DEV_HAS_RMON |
 759                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 760                                      FSL_GIANFAR_DEV_HAS_PADDING |
 761                                      FSL_GIANFAR_DEV_HAS_CSUM |
 762                                      FSL_GIANFAR_DEV_HAS_VLAN |
 763                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 764                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 765                                      FSL_GIANFAR_DEV_HAS_TIMER;
 766
 767         ctype = of_get_property(np, "phy-connection-type", NULL);
 768
 769         /* We only care about rgmii-id.  The rest are autodetected */
 770         if (ctype && !strcmp(ctype, "rgmii-id"))
 771                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 772         else
 773                 priv->interface = PHY_INTERFACE_MODE_MII;
 774
 775         if (of_get_property(np, "fsl,magic-packet", NULL))
 776                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 777
 778         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 779
 780         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 781         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 782
 783         return 0;
 784
 785 rx_alloc_failed:
 786         free_rx_pointers(priv);
 787 tx_alloc_failed:
 788         free_tx_pointers(priv);
 789 err_grp_init:
 790         unmap_group_regs(priv);
 791         free_gfar_dev(priv);
 792         return err;
 793 }
 794
 795 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 796                                struct ifreq *ifr, int cmd)
 797 {
 798         struct hwtstamp_config config;
 799         struct gfar_private *priv = netdev_priv(netdev);
 800
 801         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 802                 return -EFAULT;
 803
 804         /* reserved for future extensions */
 805         if (config.flags)
 806                 return -EINVAL;
 807
 808         switch (config.tx_type) {
 809         case HWTSTAMP_TX_OFF:
 810                 priv->hwts_tx_en = 0;
 811                 break;
 812         case HWTSTAMP_TX_ON:
 813                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 814                         return -ERANGE;
 815                 priv->hwts_tx_en = 1;
 816                 break;
 817         default:
 818                 return -ERANGE;
 819         }
 820
 821         switch (config.rx_filter) {
 822         case HWTSTAMP_FILTER_NONE:
 823                 if (priv->hwts_rx_en) {
 824                         stop_gfar(netdev);
 825                         priv->hwts_rx_en = 0;
 826                         startup_gfar(netdev);
 827                 }
 828                 break;
 829         default:
 830                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 831                         return -ERANGE;
 832                 if (!priv->hwts_rx_en) {
 833                         stop_gfar(netdev);
 834                         priv->hwts_rx_en = 1;
 835                         startup_gfar(netdev);
 836                 }
 837                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 838                 break;
 839         }
 840
 841         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 842                 -EFAULT : 0;
 843 }
 844
 845 /* Ioctl MII Interface */
 846 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 847 {
 848         struct gfar_private *priv = netdev_priv(dev);
 849
 850         if (!netif_running(dev))
 851                 return -EINVAL;
 852
 853         if (cmd == SIOCSHWTSTAMP)
 854                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 855
 856         if (!priv->phydev)
 857                 return -ENODEV;
 858
 859         return phy_mii_ioctl(priv->phydev, rq, cmd);
 860 }
 861
 862 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 863 {
 864         unsigned int new_bit_map = 0x0;
 865         int mask = 0x1 << (max_qs - 1), i;
 866
 867         for (i = 0; i < max_qs; i++) {
 868                 if (bit_map & mask)
 869                         new_bit_map = new_bit_map + (1 << i);
 870                 mask = mask >> 0x1;
 871         }
 872         return new_bit_map;
 873 }
 874
 875 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 876                                    u32 class)
 877 {
 878         u32 rqfpr = FPR_FILER_MASK;
 879         u32 rqfcr = 0x0;
 880
 881         rqfar--;
 882         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 883         priv->ftp_rqfpr[rqfar] = rqfpr;
 884         priv->ftp_rqfcr[rqfar] = rqfcr;
 885         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 886
 887         rqfar--;
 888         rqfcr = RQFCR_CMP_NOMATCH;
 889         priv->ftp_rqfpr[rqfar] = rqfpr;
 890         priv->ftp_rqfcr[rqfar] = rqfcr;
 891         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 892
 893         rqfar--;
 894         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 895         rqfpr = class;
 896         priv->ftp_rqfcr[rqfar] = rqfcr;
 897         priv->ftp_rqfpr[rqfar] = rqfpr;
 898         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 899
 900         rqfar--;
 901         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 902         rqfpr = class;
 903         priv->ftp_rqfcr[rqfar] = rqfcr;
 904         priv->ftp_rqfpr[rqfar] = rqfpr;
 905         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 906
 907         return rqfar;
 908 }
 909
 910 static void gfar_init_filer_table(struct gfar_private *priv)
 911 {
 912         int i = 0x0;
 913         u32 rqfar = MAX_FILER_IDX;
 914         u32 rqfcr = 0x0;
 915         u32 rqfpr = FPR_FILER_MASK;
 916
 917         /* Default rule */
 918         rqfcr = RQFCR_CMP_MATCH;
 919         priv->ftp_rqfcr[rqfar] = rqfcr;
 920         priv->ftp_rqfpr[rqfar] = rqfpr;
 921         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 922
 923         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 924         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 925         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 926         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 927         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 928         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 929
 930         /* cur_filer_idx indicated the first non-masked rule */
 931         priv->cur_filer_idx = rqfar;
 932
 933         /* Rest are masked rules */
 934         rqfcr = RQFCR_CMP_NOMATCH;
 935         for (i = 0; i < rqfar; i++) {
 936                 priv->ftp_rqfcr[i] = rqfcr;
 937                 priv->ftp_rqfpr[i] = rqfpr;
 938                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 939         }
 940 }
 941
 942 static void gfar_detect_errata(struct gfar_private *priv)
 943 {
 944         struct device *dev = &priv->ofdev->dev;
 945         unsigned int pvr = mfspr(SPRN_PVR);
 946         unsigned int svr = mfspr(SPRN_SVR);
 947         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 948         unsigned int rev = svr & 0xffff;
 949
 950         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 951         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 952             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 953                 priv->errata |= GFAR_ERRATA_74;
 954
 955         /* MPC8313 and MPC837x all rev */
 956         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 957             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 958                 priv->errata |= GFAR_ERRATA_76;
 959
 960         /* MPC8313 and MPC837x all rev */
 961         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 962             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 963                 priv->errata |= GFAR_ERRATA_A002;
 964
 965         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
 966         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
 967             (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
 968                 priv->errata |= GFAR_ERRATA_12;
 969
 970         if (priv->errata)
 971                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 972                          priv->errata);
 973 }
 974
 975 /* Set up the ethernet device structure, private data,
 976  * and anything else we need before we start
 977  */
 978 static int gfar_probe(struct platform_device *ofdev)
 979 {
 980         u32 tempval;
 981         struct net_device *dev = NULL;
 982         struct gfar_private *priv = NULL;
 983         struct gfar __iomem *regs = NULL;
 984         int err = 0, i, grp_idx = 0;
 985         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 986         u32 isrg = 0;
 987         u32 __iomem *baddr;
 988
 989         err = gfar_of_init(ofdev, &dev);
 990
 991         if (err)
 992                 return err;
 993
 994         priv = netdev_priv(dev);
 995         priv->ndev = dev;
 996         priv->ofdev = ofdev;
 997         priv->dev = &ofdev->dev;
 998         SET_NETDEV_DEV(dev, &ofdev->dev);
 999
1000         spin_lock_init(&priv->bflock);
1001         INIT_WORK(&priv->reset_task, gfar_reset_task);
1002
1003         dev_set_drvdata(&ofdev->dev, priv);
1004         regs = priv->gfargrp[0].regs;
1005
1006         gfar_detect_errata(priv);
1007
1008         /* Stop the DMA engine now, in case it was running before
1009          * (The firmware could have used it, and left it running).
1010          */
1011         gfar_halt(dev);
1012
1013         /* Reset MAC layer */
1014         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1015
1016         /* We need to delay at least 3 TX clocks */
1017         udelay(2);
1018
1019         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1020         gfar_write(&regs->maccfg1, tempval);
1021
1022         /* Initialize MACCFG2. */
1023         tempval = MACCFG2_INIT_SETTINGS;
1024         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1025                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1026         gfar_write(&regs->maccfg2, tempval);
1027
1028         /* Initialize ECNTRL */
1029         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1030
1031         /* Set the dev->base_addr to the gfar reg region */
1032         dev->base_addr = (unsigned long) regs;
1033
1034         /* Fill in the dev structure */
1035         dev->watchdog_timeo = TX_TIMEOUT;
1036         dev->mtu = 1500;
1037         dev->netdev_ops = &gfar_netdev_ops;
1038         dev->ethtool_ops = &gfar_ethtool_ops;
1039
1040         /* Register for napi ...We are registering NAPI for each grp */
1041         for (i = 0; i < priv->num_grps; i++)
1042                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1043                                GFAR_DEV_WEIGHT);
1044
1045         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1046                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1047                                    NETIF_F_RXCSUM;
1048                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1049                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1050         }
1051
1052         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1053                 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1054                 dev->features |= NETIF_F_HW_VLAN_RX;
1055         }
1056
1057         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1058                 priv->extended_hash = 1;
1059                 priv->hash_width = 9;
1060
1061                 priv->hash_regs[0] = &regs->igaddr0;
1062                 priv->hash_regs[1] = &regs->igaddr1;
1063                 priv->hash_regs[2] = &regs->igaddr2;
1064                 priv->hash_regs[3] = &regs->igaddr3;
1065                 priv->hash_regs[4] = &regs->igaddr4;
1066                 priv->hash_regs[5] = &regs->igaddr5;
1067                 priv->hash_regs[6] = &regs->igaddr6;
1068                 priv->hash_regs[7] = &regs->igaddr7;
1069                 priv->hash_regs[8] = &regs->gaddr0;
1070                 priv->hash_regs[9] = &regs->gaddr1;
1071                 priv->hash_regs[10] = &regs->gaddr2;
1072                 priv->hash_regs[11] = &regs->gaddr3;
1073                 priv->hash_regs[12] = &regs->gaddr4;
1074                 priv->hash_regs[13] = &regs->gaddr5;
1075                 priv->hash_regs[14] = &regs->gaddr6;
1076                 priv->hash_regs[15] = &regs->gaddr7;
1077
1078         } else {
1079                 priv->extended_hash = 0;
1080                 priv->hash_width = 8;
1081
1082                 priv->hash_regs[0] = &regs->gaddr0;
1083                 priv->hash_regs[1] = &regs->gaddr1;
1084                 priv->hash_regs[2] = &regs->gaddr2;
1085                 priv->hash_regs[3] = &regs->gaddr3;
1086                 priv->hash_regs[4] = &regs->gaddr4;
1087                 priv->hash_regs[5] = &regs->gaddr5;
1088                 priv->hash_regs[6] = &regs->gaddr6;
1089                 priv->hash_regs[7] = &regs->gaddr7;
1090         }
1091
1092         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1093                 priv->padding = DEFAULT_PADDING;
1094         else
1095                 priv->padding = 0;
1096
1097         if (dev->features & NETIF_F_IP_CSUM ||
1098             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1099                 dev->needed_headroom = GMAC_FCB_LEN;
1100
1101         /* Program the isrg regs only if number of grps > 1 */
1102         if (priv->num_grps > 1) {
1103                 baddr = &regs->isrg0;
1104                 for (i = 0; i < priv->num_grps; i++) {
1105                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1106                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1107                         gfar_write(baddr, isrg);
1108                         baddr++;
1109                         isrg = 0x0;
1110                 }
1111         }
1112
1113         /* Need to reverse the bit maps as  bit_map's MSB is q0
1114          * but, for_each_set_bit parses from right to left, which
1115          * basically reverses the queue numbers
1116          */
1117         for (i = 0; i< priv->num_grps; i++) {
1118                 priv->gfargrp[i].tx_bit_map =
1119                         reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1120                 priv->gfargrp[i].rx_bit_map =
1121                         reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1122         }
1123
1124         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1125          * also assign queues to groups
1126          */
1127         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1128                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1129
1130                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1131                                  priv->num_rx_queues) {
1132                         priv->gfargrp[grp_idx].num_rx_queues++;
1133                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1134                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1135                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1136                 }
1137                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1138
1139                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1140                                  priv->num_tx_queues) {
1141                         priv->gfargrp[grp_idx].num_tx_queues++;
1142                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1143                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1144                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1145                 }
1146                 priv->gfargrp[grp_idx].rstat = rstat;
1147                 priv->gfargrp[grp_idx].tstat = tstat;
1148                 rstat = tstat =0;
1149         }
1150
1151         gfar_write(&regs->rqueue, rqueue);
1152         gfar_write(&regs->tqueue, tqueue);
1153
1154         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1155
1156         /* Initializing some of the rx/tx queue level parameters */
1157         for (i = 0; i < priv->num_tx_queues; i++) {
1158                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1159                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1160                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1161                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1162         }
1163
1164         for (i = 0; i < priv->num_rx_queues; i++) {
1165                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1166                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1167                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1168         }
1169
1170         /* always enable rx filer */
1171         priv->rx_filer_enable = 1;
1172         /* Enable most messages by default */
1173         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1174         /* use pritority h/w tx queue scheduling for single queue devices */
1175         if (priv->num_tx_queues == 1)
1176                 priv->prio_sched_en = 1;
1177
1178         /* Carrier starts down, phylib will bring it up */
1179         netif_carrier_off(dev);
1180
1181         err = register_netdev(dev);
1182
1183         if (err) {
1184                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1185                 goto register_fail;
1186         }
1187
1188         device_init_wakeup(&dev->dev,
1189                            priv->device_flags &
1190                            FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1191
1192         /* fill out IRQ number and name fields */
1193         for (i = 0; i < priv->num_grps; i++) {
1194                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1195                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1196                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1197                                 dev->name, "_g", '0' + i, "_tx");
1198                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1199                                 dev->name, "_g", '0' + i, "_rx");
1200                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1201                                 dev->name, "_g", '0' + i, "_er");
1202                 } else
1203                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1204         }
1205
1206         /* Initialize the filer table */
1207         gfar_init_filer_table(priv);
1208
1209         /* Create all the sysfs files */
1210         gfar_init_sysfs(dev);
1211
1212         /* Print out the device info */
1213         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1214
1215         /* Even more device info helps when determining which kernel
1216          * provided which set of benchmarks.
1217          */
1218         netdev_info(dev, "Running with NAPI enabled\n");
1219         for (i = 0; i < priv->num_rx_queues; i++)
1220                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1221                             i, priv->rx_queue[i]->rx_ring_size);
1222         for (i = 0; i < priv->num_tx_queues; i++)
1223                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1224                             i, priv->tx_queue[i]->tx_ring_size);
1225
1226         return 0;
1227
1228 register_fail:
1229         unmap_group_regs(priv);
1230         free_tx_pointers(priv);
1231         free_rx_pointers(priv);
1232         if (priv->phy_node)
1233                 of_node_put(priv->phy_node);
1234         if (priv->tbi_node)
1235                 of_node_put(priv->tbi_node);
1236         free_gfar_dev(priv);
1237         return err;
1238 }
1239
1240 static int gfar_remove(struct platform_device *ofdev)
1241 {
1242         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1243
1244         if (priv->phy_node)
1245                 of_node_put(priv->phy_node);
1246         if (priv->tbi_node)
1247                 of_node_put(priv->tbi_node);
1248
1249         dev_set_drvdata(&ofdev->dev, NULL);
1250
1251         unregister_netdev(priv->ndev);
1252         unmap_group_regs(priv);
1253         free_gfar_dev(priv);
1254
1255         return 0;
1256 }
1257
1258 #ifdef CONFIG_PM
1259
1260 static int gfar_suspend(struct device *dev)
1261 {
1262         struct gfar_private *priv = dev_get_drvdata(dev);
1263         struct net_device *ndev = priv->ndev;
1264         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1265         unsigned long flags;
1266         u32 tempval;
1267
1268         int magic_packet = priv->wol_en &&
1269                            (priv->device_flags &
1270                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1271
1272         netif_device_detach(ndev);
1273
1274         if (netif_running(ndev)) {
1275
1276                 local_irq_save(flags);
1277                 lock_tx_qs(priv);
1278                 lock_rx_qs(priv);
1279
1280                 gfar_halt_nodisable(ndev);
1281
1282                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1283                 tempval = gfar_read(&regs->maccfg1);
1284
1285                 tempval &= ~MACCFG1_TX_EN;
1286
1287                 if (!magic_packet)
1288                         tempval &= ~MACCFG1_RX_EN;
1289
1290                 gfar_write(&regs->maccfg1, tempval);
1291
1292                 unlock_rx_qs(priv);
1293                 unlock_tx_qs(priv);
1294                 local_irq_restore(flags);
1295
1296                 disable_napi(priv);
1297
1298                 if (magic_packet) {
1299                         /* Enable interrupt on Magic Packet */
1300                         gfar_write(&regs->imask, IMASK_MAG);
1301
1302                         /* Enable Magic Packet mode */
1303                         tempval = gfar_read(&regs->maccfg2);
1304                         tempval |= MACCFG2_MPEN;
1305                         gfar_write(&regs->maccfg2, tempval);
1306                 } else {
1307                         phy_stop(priv->phydev);
1308                 }
1309         }
1310
1311         return 0;
1312 }
1313
1314 static int gfar_resume(struct device *dev)
1315 {
1316         struct gfar_private *priv = dev_get_drvdata(dev);
1317         struct net_device *ndev = priv->ndev;
1318         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1319         unsigned long flags;
1320         u32 tempval;
1321         int magic_packet = priv->wol_en &&
1322                            (priv->device_flags &
1323                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1324
1325         if (!netif_running(ndev)) {
1326                 netif_device_attach(ndev);
1327                 return 0;
1328         }
1329
1330         if (!magic_packet && priv->phydev)
1331                 phy_start(priv->phydev);
1332
1333         /* Disable Magic Packet mode, in case something
1334          * else woke us up.
1335          */
1336         local_irq_save(flags);
1337         lock_tx_qs(priv);
1338         lock_rx_qs(priv);
1339
1340         tempval = gfar_read(&regs->maccfg2);
1341         tempval &= ~MACCFG2_MPEN;
1342         gfar_write(&regs->maccfg2, tempval);
1343
1344         gfar_start(ndev);
1345
1346         unlock_rx_qs(priv);
1347         unlock_tx_qs(priv);
1348         local_irq_restore(flags);
1349
1350         netif_device_attach(ndev);
1351
1352         enable_napi(priv);
1353
1354         return 0;
1355 }
1356
1357 static int gfar_restore(struct device *dev)
1358 {
1359         struct gfar_private *priv = dev_get_drvdata(dev);
1360         struct net_device *ndev = priv->ndev;
1361
1362         if (!netif_running(ndev)) {
1363                 netif_device_attach(ndev);
1364
1365                 return 0;
1366         }
1367
1368         if (gfar_init_bds(ndev)) {
1369                 free_skb_resources(priv);
1370                 return -ENOMEM;
1371         }
1372
1373         init_registers(ndev);
1374         gfar_set_mac_address(ndev);
1375         gfar_init_mac(ndev);
1376         gfar_start(ndev);
1377
1378         priv->oldlink = 0;
1379         priv->oldspeed = 0;
1380         priv->oldduplex = -1;
1381
1382         if (priv->phydev)
1383                 phy_start(priv->phydev);
1384
1385         netif_device_attach(ndev);
1386         enable_napi(priv);
1387
1388         return 0;
1389 }
1390
1391 static struct dev_pm_ops gfar_pm_ops = {
1392         .suspend = gfar_suspend,
1393         .resume = gfar_resume,
1394         .freeze = gfar_suspend,
1395         .thaw = gfar_resume,
1396         .restore = gfar_restore,
1397 };
1398
1399 #define GFAR_PM_OPS (&gfar_pm_ops)
1400
1401 #else
1402
1403 #define GFAR_PM_OPS NULL
1404
1405 #endif
1406
1407 /* Reads the controller's registers to determine what interface
1408  * connects it to the PHY.
1409  */
1410 static phy_interface_t gfar_get_interface(struct net_device *dev)
1411 {
1412         struct gfar_private *priv = netdev_priv(dev);
1413         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1414         u32 ecntrl;
1415
1416         ecntrl = gfar_read(&regs->ecntrl);
1417
1418         if (ecntrl & ECNTRL_SGMII_MODE)
1419                 return PHY_INTERFACE_MODE_SGMII;
1420
1421         if (ecntrl & ECNTRL_TBI_MODE) {
1422                 if (ecntrl & ECNTRL_REDUCED_MODE)
1423                         return PHY_INTERFACE_MODE_RTBI;
1424                 else
1425                         return PHY_INTERFACE_MODE_TBI;
1426         }
1427
1428         if (ecntrl & ECNTRL_REDUCED_MODE) {
1429                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1430                         return PHY_INTERFACE_MODE_RMII;
1431                 }
1432                 else {
1433                         phy_interface_t interface = priv->interface;
1434
1435                         /* This isn't autodetected right now, so it must
1436                          * be set by the device tree or platform code.
1437                          */
1438                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1439                                 return PHY_INTERFACE_MODE_RGMII_ID;
1440
1441                         return PHY_INTERFACE_MODE_RGMII;
1442                 }
1443         }
1444
1445         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1446                 return PHY_INTERFACE_MODE_GMII;
1447
1448         return PHY_INTERFACE_MODE_MII;
1449 }
1450
1451
1452 /* Initializes driver's PHY state, and attaches to the PHY.
1453  * Returns 0 on success.
1454  */
1455 static int init_phy(struct net_device *dev)
1456 {
1457         struct gfar_private *priv = netdev_priv(dev);
1458         uint gigabit_support =
1459                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1460                 SUPPORTED_1000baseT_Full : 0;
1461         phy_interface_t interface;
1462
1463         priv->oldlink = 0;
1464         priv->oldspeed = 0;
1465         priv->oldduplex = -1;
1466
1467         interface = gfar_get_interface(dev);
1468
1469         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1470                                       interface);
1471         if (!priv->phydev)
1472                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1473                                                          interface);
1474         if (!priv->phydev) {
1475                 dev_err(&dev->dev, "could not attach to PHY\n");
1476                 return -ENODEV;
1477         }
1478
1479         if (interface == PHY_INTERFACE_MODE_SGMII)
1480                 gfar_configure_serdes(dev);
1481
1482         /* Remove any features not supported by the controller */
1483         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1484         priv->phydev->advertising = priv->phydev->supported;
1485
1486         return 0;
1487 }
1488
1489 /* Initialize TBI PHY interface for communicating with the
1490  * SERDES lynx PHY on the chip.  We communicate with this PHY
1491  * through the MDIO bus on each controller, treating it as a
1492  * "normal" PHY at the address found in the TBIPA register.  We assume
1493  * that the TBIPA register is valid.  Either the MDIO bus code will set
1494  * it to a value that doesn't conflict with other PHYs on the bus, or the
1495  * value doesn't matter, as there are no other PHYs on the bus.
1496  */
1497 static void gfar_configure_serdes(struct net_device *dev)
1498 {
1499         struct gfar_private *priv = netdev_priv(dev);
1500         struct phy_device *tbiphy;
1501
1502         if (!priv->tbi_node) {
1503                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1504                                     "device tree specify a tbi-handle\n");
1505                 return;
1506         }
1507
1508         tbiphy = of_phy_find_device(priv->tbi_node);
1509         if (!tbiphy) {
1510                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1511                 return;
1512         }
1513
1514         /* If the link is already up, we must already be ok, and don't need to
1515          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1516          * everything for us?  Resetting it takes the link down and requires
1517          * several seconds for it to come back.
1518          */
1519         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1520                 return;
1521
1522         /* Single clk mode, mii mode off(for serdes communication) */
1523         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1524
1525         phy_write(tbiphy, MII_ADVERTISE,
1526                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1527                   ADVERTISE_1000XPSE_ASYM);
1528
1529         phy_write(tbiphy, MII_BMCR,
1530                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1531                   BMCR_SPEED1000);
1532 }
1533
1534 static void init_registers(struct net_device *dev)
1535 {
1536         struct gfar_private *priv = netdev_priv(dev);
1537         struct gfar __iomem *regs = NULL;
1538         int i;
1539
1540         for (i = 0; i < priv->num_grps; i++) {
1541                 regs = priv->gfargrp[i].regs;
1542                 /* Clear IEVENT */
1543                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1544
1545                 /* Initialize IMASK */
1546                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1547         }
1548
1549         regs = priv->gfargrp[0].regs;
1550         /* Init hash registers to zero */
1551         gfar_write(&regs->igaddr0, 0);
1552         gfar_write(&regs->igaddr1, 0);
1553         gfar_write(&regs->igaddr2, 0);
1554         gfar_write(&regs->igaddr3, 0);
1555         gfar_write(&regs->igaddr4, 0);
1556         gfar_write(&regs->igaddr5, 0);
1557         gfar_write(&regs->igaddr6, 0);
1558         gfar_write(&regs->igaddr7, 0);
1559
1560         gfar_write(&regs->gaddr0, 0);
1561         gfar_write(&regs->gaddr1, 0);
1562         gfar_write(&regs->gaddr2, 0);
1563         gfar_write(&regs->gaddr3, 0);
1564         gfar_write(&regs->gaddr4, 0);
1565         gfar_write(&regs->gaddr5, 0);
1566         gfar_write(&regs->gaddr6, 0);
1567         gfar_write(&regs->gaddr7, 0);
1568
1569         /* Zero out the rmon mib registers if it has them */
1570         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1571                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1572
1573                 /* Mask off the CAM interrupts */
1574                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1575                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1576         }
1577
1578         /* Initialize the max receive buffer length */
1579         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1580
1581         /* Initialize the Minimum Frame Length Register */
1582         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1583 }
1584
1585 static int __gfar_is_rx_idle(struct gfar_private *priv)
1586 {
1587         u32 res;
1588
1589         /* Normaly TSEC should not hang on GRS commands, so we should
1590          * actually wait for IEVENT_GRSC flag.
1591          */
1592         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1593                 return 0;
1594
1595         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1596          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1597          * and the Rx can be safely reset.
1598          */
1599         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1600         res &= 0x7f807f80;
1601         if ((res & 0xffff) == (res >> 16))
1602                 return 1;
1603
1604         return 0;
1605 }
1606
1607 /* Halt the receive and transmit queues */
1608 static void gfar_halt_nodisable(struct net_device *dev)
1609 {
1610         struct gfar_private *priv = netdev_priv(dev);
1611         struct gfar __iomem *regs = NULL;
1612         u32 tempval;
1613         int i;
1614
1615         for (i = 0; i < priv->num_grps; i++) {
1616                 regs = priv->gfargrp[i].regs;
1617                 /* Mask all interrupts */
1618                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1619
1620                 /* Clear all interrupts */
1621                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1622         }
1623
1624         regs = priv->gfargrp[0].regs;
1625         /* Stop the DMA, and wait for it to stop */
1626         tempval = gfar_read(&regs->dmactrl);
1627         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1628             (DMACTRL_GRS | DMACTRL_GTS)) {
1629                 int ret;
1630
1631                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1632                 gfar_write(&regs->dmactrl, tempval);
1633
1634                 do {
1635                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1636                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1637                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1638                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1639                                 ret = __gfar_is_rx_idle(priv);
1640                 } while (!ret);
1641         }
1642 }
1643
1644 /* Halt the receive and transmit queues */
1645 void gfar_halt(struct net_device *dev)
1646 {
1647         struct gfar_private *priv = netdev_priv(dev);
1648         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1649         u32 tempval;
1650
1651         gfar_halt_nodisable(dev);
1652
1653         /* Disable Rx and Tx */
1654         tempval = gfar_read(&regs->maccfg1);
1655         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1656         gfar_write(&regs->maccfg1, tempval);
1657 }
1658
1659 static void free_grp_irqs(struct gfar_priv_grp *grp)
1660 {
1661         free_irq(gfar_irq(grp, TX)->irq, grp);
1662         free_irq(gfar_irq(grp, RX)->irq, grp);
1663         free_irq(gfar_irq(grp, ER)->irq, grp);
1664 }
1665
1666 void stop_gfar(struct net_device *dev)
1667 {
1668         struct gfar_private *priv = netdev_priv(dev);
1669         unsigned long flags;
1670         int i;
1671
1672         phy_stop(priv->phydev);
1673
1674
1675         /* Lock it down */
1676         local_irq_save(flags);
1677         lock_tx_qs(priv);
1678         lock_rx_qs(priv);
1679
1680         gfar_halt(dev);
1681
1682         unlock_rx_qs(priv);
1683         unlock_tx_qs(priv);
1684         local_irq_restore(flags);
1685
1686         /* Free the IRQs */
1687         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1688                 for (i = 0; i < priv->num_grps; i++)
1689                         free_grp_irqs(&priv->gfargrp[i]);
1690         } else {
1691                 for (i = 0; i < priv->num_grps; i++)
1692                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1693                                  &priv->gfargrp[i]);
1694         }
1695
1696         free_skb_resources(priv);
1697 }
1698
1699 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1700 {
1701         struct txbd8 *txbdp;
1702         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1703         int i, j;
1704
1705         txbdp = tx_queue->tx_bd_base;
1706
1707         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1708                 if (!tx_queue->tx_skbuff[i])
1709                         continue;
1710
1711                 dma_unmap_single(priv->dev, txbdp->bufPtr,
1712                                  txbdp->length, DMA_TO_DEVICE);
1713                 txbdp->lstatus = 0;
1714                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1715                      j++) {
1716                         txbdp++;
1717                         dma_unmap_page(priv->dev, txbdp->bufPtr,
1718                                        txbdp->length, DMA_TO_DEVICE);
1719                 }
1720                 txbdp++;
1721                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1722                 tx_queue->tx_skbuff[i] = NULL;
1723         }
1724         kfree(tx_queue->tx_skbuff);
1725         tx_queue->tx_skbuff = NULL;
1726 }
1727
1728 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1729 {
1730         struct rxbd8 *rxbdp;
1731         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1732         int i;
1733
1734         rxbdp = rx_queue->rx_bd_base;
1735
1736         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1737                 if (rx_queue->rx_skbuff[i]) {
1738                         dma_unmap_single(priv->dev, rxbdp->bufPtr,
1739                                          priv->rx_buffer_size,
1740                                          DMA_FROM_DEVICE);
1741                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1742                         rx_queue->rx_skbuff[i] = NULL;
1743                 }
1744                 rxbdp->lstatus = 0;
1745                 rxbdp->bufPtr = 0;
1746                 rxbdp++;
1747         }
1748         kfree(rx_queue->rx_skbuff);
1749         rx_queue->rx_skbuff = NULL;
1750 }
1751
1752 /* If there are any tx skbs or rx skbs still around, free them.
1753  * Then free tx_skbuff and rx_skbuff
1754  */
1755 static void free_skb_resources(struct gfar_private *priv)
1756 {
1757         struct gfar_priv_tx_q *tx_queue = NULL;
1758         struct gfar_priv_rx_q *rx_queue = NULL;
1759         int i;
1760
1761         /* Go through all the buffer descriptors and free their data buffers */
1762         for (i = 0; i < priv->num_tx_queues; i++) {
1763                 struct netdev_queue *txq;
1764
1765                 tx_queue = priv->tx_queue[i];
1766                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1767                 if (tx_queue->tx_skbuff)
1768                         free_skb_tx_queue(tx_queue);
1769                 netdev_tx_reset_queue(txq);
1770         }
1771
1772         for (i = 0; i < priv->num_rx_queues; i++) {
1773                 rx_queue = priv->rx_queue[i];
1774                 if (rx_queue->rx_skbuff)
1775                         free_skb_rx_queue(rx_queue);
1776         }
1777
1778         dma_free_coherent(priv->dev,
1779                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1780                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1781                           priv->tx_queue[0]->tx_bd_base,
1782                           priv->tx_queue[0]->tx_bd_dma_base);
1783 }
1784
1785 void gfar_start(struct net_device *dev)
1786 {
1787         struct gfar_private *priv = netdev_priv(dev);
1788         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1789         u32 tempval;
1790         int i = 0;
1791
1792         /* Enable Rx and Tx in MACCFG1 */
1793         tempval = gfar_read(&regs->maccfg1);
1794         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1795         gfar_write(&regs->maccfg1, tempval);
1796
1797         /* Initialize DMACTRL to have WWR and WOP */
1798         tempval = gfar_read(&regs->dmactrl);
1799         tempval |= DMACTRL_INIT_SETTINGS;
1800         gfar_write(&regs->dmactrl, tempval);
1801
1802         /* Make sure we aren't stopped */
1803         tempval = gfar_read(&regs->dmactrl);
1804         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1805         gfar_write(&regs->dmactrl, tempval);
1806
1807         for (i = 0; i < priv->num_grps; i++) {
1808                 regs = priv->gfargrp[i].regs;
1809                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1810                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1811                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1812                 /* Unmask the interrupts we look for */
1813                 gfar_write(&regs->imask, IMASK_DEFAULT);
1814         }
1815
1816         dev->trans_start = jiffies; /* prevent tx timeout */
1817 }
1818
1819 void gfar_configure_coalescing(struct gfar_private *priv,
1820                                unsigned long tx_mask, unsigned long rx_mask)
1821 {
1822         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1823         u32 __iomem *baddr;
1824         int i = 0;
1825
1826         /* Backward compatible case ---- even if we enable
1827          * multiple queues, there's only single reg to program
1828          */
1829         gfar_write(&regs->txic, 0);
1830         if (likely(priv->tx_queue[0]->txcoalescing))
1831                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1832
1833         gfar_write(&regs->rxic, 0);
1834         if (unlikely(priv->rx_queue[0]->rxcoalescing))
1835                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1836
1837         if (priv->mode == MQ_MG_MODE) {
1838                 baddr = &regs->txic0;
1839                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1840                         gfar_write(baddr + i, 0);
1841                         if (likely(priv->tx_queue[i]->txcoalescing))
1842                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1843                 }
1844
1845                 baddr = &regs->rxic0;
1846                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1847                         gfar_write(baddr + i, 0);
1848                         if (likely(priv->rx_queue[i]->rxcoalescing))
1849                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1850                 }
1851         }
1852 }
1853
1854 static int register_grp_irqs(struct gfar_priv_grp *grp)
1855 {
1856         struct gfar_private *priv = grp->priv;
1857         struct net_device *dev = priv->ndev;
1858         int err;
1859
1860         /* If the device has multiple interrupts, register for
1861          * them.  Otherwise, only register for the one
1862          */
1863         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1864                 /* Install our interrupt handlers for Error,
1865                  * Transmit, and Receive
1866                  */
1867                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1868                                   gfar_irq(grp, ER)->name, grp);
1869                 if (err < 0) {
1870                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1871                                   gfar_irq(grp, ER)->irq);
1872
1873                         goto err_irq_fail;
1874                 }
1875                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1876                                   gfar_irq(grp, TX)->name, grp);
1877                 if (err < 0) {
1878                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1879                                   gfar_irq(grp, TX)->irq);
1880                         goto tx_irq_fail;
1881                 }
1882                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1883                                   gfar_irq(grp, RX)->name, grp);
1884                 if (err < 0) {
1885                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1886                                   gfar_irq(grp, RX)->irq);
1887                         goto rx_irq_fail;
1888                 }
1889         } else {
1890                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1891                                   gfar_irq(grp, TX)->name, grp);
1892                 if (err < 0) {
1893                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1894                                   gfar_irq(grp, TX)->irq);
1895                         goto err_irq_fail;
1896                 }
1897         }
1898
1899         return 0;
1900
1901 rx_irq_fail:
1902         free_irq(gfar_irq(grp, TX)->irq, grp);
1903 tx_irq_fail:
1904         free_irq(gfar_irq(grp, ER)->irq, grp);
1905 err_irq_fail:
1906         return err;
1907
1908 }
1909
1910 /* Bring the controller up and running */
1911 int startup_gfar(struct net_device *ndev)
1912 {
1913         struct gfar_private *priv = netdev_priv(ndev);
1914         struct gfar __iomem *regs = NULL;
1915         int err, i, j;
1916
1917         for (i = 0; i < priv->num_grps; i++) {
1918                 regs= priv->gfargrp[i].regs;
1919                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1920         }
1921
1922         regs= priv->gfargrp[0].regs;
1923         err = gfar_alloc_skb_resources(ndev);
1924         if (err)
1925                 return err;
1926
1927         gfar_init_mac(ndev);
1928
1929         for (i = 0; i < priv->num_grps; i++) {
1930                 err = register_grp_irqs(&priv->gfargrp[i]);
1931                 if (err) {
1932                         for (j = 0; j < i; j++)
1933                                 free_grp_irqs(&priv->gfargrp[j]);
1934                         goto irq_fail;
1935                 }
1936         }
1937
1938         /* Start the controller */
1939         gfar_start(ndev);
1940
1941         phy_start(priv->phydev);
1942
1943         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1944
1945         return 0;
1946
1947 irq_fail:
1948         free_skb_resources(priv);
1949         return err;
1950 }
1951
1952 /* Called when something needs to use the ethernet device
1953  * Returns 0 for success.
1954  */
1955 static int gfar_enet_open(struct net_device *dev)
1956 {
1957         struct gfar_private *priv = netdev_priv(dev);
1958         int err;
1959
1960         enable_napi(priv);
1961
1962         /* Initialize a bunch of registers */
1963         init_registers(dev);
1964
1965         gfar_set_mac_address(dev);
1966
1967         err = init_phy(dev);
1968
1969         if (err) {
1970                 disable_napi(priv);
1971                 return err;
1972         }
1973
1974         err = startup_gfar(dev);
1975         if (err) {
1976                 disable_napi(priv);
1977                 return err;
1978         }
1979
1980         netif_tx_start_all_queues(dev);
1981
1982         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1983
1984         return err;
1985 }
1986
1987 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1988 {
1989         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1990
1991         memset(fcb, 0, GMAC_FCB_LEN);
1992
1993         return fcb;
1994 }
1995
1996 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1997                                     int fcb_length)
1998 {
1999         /* If we're here, it's a IP packet with a TCP or UDP
2000          * payload.  We set it to checksum, using a pseudo-header
2001          * we provide
2002          */
2003         u8 flags = TXFCB_DEFAULT;
2004
2005         /* Tell the controller what the protocol is
2006          * And provide the already calculated phcs
2007          */
2008         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2009                 flags |= TXFCB_UDP;
2010                 fcb->phcs = udp_hdr(skb)->check;
2011         } else
2012                 fcb->phcs = tcp_hdr(skb)->check;
2013
2014         /* l3os is the distance between the start of the
2015          * frame (skb->data) and the start of the IP hdr.
2016          * l4os is the distance between the start of the
2017          * l3 hdr and the l4 hdr
2018          */
2019         fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2020         fcb->l4os = skb_network_header_len(skb);
2021
2022         fcb->flags = flags;
2023 }
2024
2025 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2026 {
2027         fcb->flags |= TXFCB_VLN;
2028         fcb->vlctl = vlan_tx_tag_get(skb);
2029 }
2030
2031 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2032                                       struct txbd8 *base, int ring_size)
2033 {
2034         struct txbd8 *new_bd = bdp + stride;
2035
2036         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2037 }
2038
2039 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2040                                       int ring_size)
2041 {
2042         return skip_txbd(bdp, 1, base, ring_size);
2043 }
2044
2045 /* This is called by the kernel when a frame is ready for transmission.
2046  * It is pointed to by the dev->hard_start_xmit function pointer
2047  */
2048 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2049 {
2050         struct gfar_private *priv = netdev_priv(dev);
2051         struct gfar_priv_tx_q *tx_queue = NULL;
2052         struct netdev_queue *txq;
2053         struct gfar __iomem *regs = NULL;
2054         struct txfcb *fcb = NULL;
2055         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2056         u32 lstatus;
2057         int i, rq = 0, do_tstamp = 0;
2058         u32 bufaddr;
2059         unsigned long flags;
2060         unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2061
2062         /* TOE=1 frames larger than 2500 bytes may see excess delays
2063          * before start of transmission.
2064          */
2065         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2066                      skb->ip_summed == CHECKSUM_PARTIAL &&
2067                      skb->len > 2500)) {
2068                 int ret;
2069
2070                 ret = skb_checksum_help(skb);
2071                 if (ret)
2072                         return ret;
2073         }
2074
2075         rq = skb->queue_mapping;
2076         tx_queue = priv->tx_queue[rq];
2077         txq = netdev_get_tx_queue(dev, rq);
2078         base = tx_queue->tx_bd_base;
2079         regs = tx_queue->grp->regs;
2080
2081         /* check if time stamp should be generated */
2082         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2083                      priv->hwts_tx_en)) {
2084                 do_tstamp = 1;
2085                 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2086         }
2087
2088         /* make space for additional header when fcb is needed */
2089         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2090              vlan_tx_tag_present(skb) ||
2091              unlikely(do_tstamp)) &&
2092             (skb_headroom(skb) < fcb_length)) {
2093                 struct sk_buff *skb_new;
2094
2095                 skb_new = skb_realloc_headroom(skb, fcb_length);
2096                 if (!skb_new) {
2097                         dev->stats.tx_errors++;
2098                         kfree_skb(skb);
2099                         return NETDEV_TX_OK;
2100                 }
2101
2102                 if (skb->sk)
2103                         skb_set_owner_w(skb_new, skb->sk);
2104                 consume_skb(skb);
2105                 skb = skb_new;
2106         }
2107
2108         /* total number of fragments in the SKB */
2109         nr_frags = skb_shinfo(skb)->nr_frags;
2110
2111         /* calculate the required number of TxBDs for this skb */
2112         if (unlikely(do_tstamp))
2113                 nr_txbds = nr_frags + 2;
2114         else
2115                 nr_txbds = nr_frags + 1;
2116
2117         /* check if there is space to queue this packet */
2118         if (nr_txbds > tx_queue->num_txbdfree) {
2119                 /* no space, stop the queue */
2120                 netif_tx_stop_queue(txq);
2121                 dev->stats.tx_fifo_errors++;
2122                 return NETDEV_TX_BUSY;
2123         }
2124
2125         /* Update transmit stats */
2126         tx_queue->stats.tx_bytes += skb->len;
2127         tx_queue->stats.tx_packets++;
2128
2129         txbdp = txbdp_start = tx_queue->cur_tx;
2130         lstatus = txbdp->lstatus;
2131
2132         /* Time stamp insertion requires one additional TxBD */
2133         if (unlikely(do_tstamp))
2134                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2135                                                  tx_queue->tx_ring_size);
2136
2137         if (nr_frags == 0) {
2138                 if (unlikely(do_tstamp))
2139                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2140                                                           TXBD_INTERRUPT);
2141                 else
2142                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2143         } else {
2144                 /* Place the fragment addresses and lengths into the TxBDs */
2145                 for (i = 0; i < nr_frags; i++) {
2146                         /* Point at the next BD, wrapping as needed */
2147                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2148
2149                         length = skb_shinfo(skb)->frags[i].size;
2150
2151                         lstatus = txbdp->lstatus | length |
2152                                   BD_LFLAG(TXBD_READY);
2153
2154                         /* Handle the last BD specially */
2155                         if (i == nr_frags - 1)
2156                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2157
2158                         bufaddr = skb_frag_dma_map(priv->dev,
2159                                                    &skb_shinfo(skb)->frags[i],
2160                                                    0,
2161                                                    length,
2162                                                    DMA_TO_DEVICE);
2163
2164                         /* set the TxBD length and buffer pointer */
2165                         txbdp->bufPtr = bufaddr;
2166                         txbdp->lstatus = lstatus;
2167                 }
2168
2169                 lstatus = txbdp_start->lstatus;
2170         }
2171
2172         /* Add TxPAL between FCB and frame if required */
2173         if (unlikely(do_tstamp)) {
2174                 skb_push(skb, GMAC_TXPAL_LEN);
2175                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2176         }
2177
2178         /* Set up checksumming */
2179         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2180                 fcb = gfar_add_fcb(skb);
2181                 /* as specified by errata */
2182                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2183                              ((unsigned long)fcb % 0x20) > 0x18)) {
2184                         __skb_pull(skb, GMAC_FCB_LEN);
2185                         skb_checksum_help(skb);
2186                 } else {
2187                         lstatus |= BD_LFLAG(TXBD_TOE);
2188                         gfar_tx_checksum(skb, fcb, fcb_length);
2189                 }
2190         }
2191
2192         if (vlan_tx_tag_present(skb)) {
2193                 if (unlikely(NULL == fcb)) {
2194                         fcb = gfar_add_fcb(skb);
2195                         lstatus |= BD_LFLAG(TXBD_TOE);
2196                 }
2197
2198                 gfar_tx_vlan(skb, fcb);
2199         }
2200
2201         /* Setup tx hardware time stamping if requested */
2202         if (unlikely(do_tstamp)) {
2203                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2204                 if (fcb == NULL)
2205                         fcb = gfar_add_fcb(skb);
2206                 fcb->ptp = 1;
2207                 lstatus |= BD_LFLAG(TXBD_TOE);
2208         }
2209
2210         txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
2211                                              skb_headlen(skb), DMA_TO_DEVICE);
2212
2213         /* If time stamping is requested one additional TxBD must be set up. The
2214          * first TxBD points to the FCB and must have a data length of
2215          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2216          * the full frame length.
2217          */
2218         if (unlikely(do_tstamp)) {
2219                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2220                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2221                                          (skb_headlen(skb) - fcb_length);
2222                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2223         } else {
2224                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2225         }
2226
2227         netdev_tx_sent_queue(txq, skb->len);
2228
2229         /* We can work in parallel with gfar_clean_tx_ring(), except
2230          * when modifying num_txbdfree. Note that we didn't grab the lock
2231          * when we were reading the num_txbdfree and checking for available
2232          * space, that's because outside of this function it can only grow,
2233          * and once we've got needed space, it cannot suddenly disappear.
2234          *
2235          * The lock also protects us from gfar_error(), which can modify
2236          * regs->tstat and thus retrigger the transfers, which is why we
2237          * also must grab the lock before setting ready bit for the first
2238          * to be transmitted BD.
2239          */
2240         spin_lock_irqsave(&tx_queue->txlock, flags);
2241
2242         /* The powerpc-specific eieio() is used, as wmb() has too strong
2243          * semantics (it requires synchronization between cacheable and
2244          * uncacheable mappings, which eieio doesn't provide and which we
2245          * don't need), thus requiring a more expensive sync instruction.  At
2246          * some point, the set of architecture-independent barrier functions
2247          * should be expanded to include weaker barriers.
2248          */
2249         eieio();
2250
2251         txbdp_start->lstatus = lstatus;
2252
2253         eieio(); /* force lstatus write before tx_skbuff */
2254
2255         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2256
2257         /* Update the current skb pointer to the next entry we will use
2258          * (wrapping if necessary)
2259          */
2260         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2261                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2262
2263         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2264
2265         /* reduce TxBD free count */
2266         tx_queue->num_txbdfree -= (nr_txbds);
2267
2268         /* If the next BD still needs to be cleaned up, then the bds
2269          * are full.  We need to tell the kernel to stop sending us stuff.
2270          */
2271         if (!tx_queue->num_txbdfree) {
2272                 netif_tx_stop_queue(txq);
2273
2274                 dev->stats.tx_fifo_errors++;
2275         }
2276
2277         /* Tell the DMA to go go go */
2278         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2279
2280         /* Unlock priv */
2281         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2282
2283         return NETDEV_TX_OK;
2284 }
2285
2286 /* Stops the kernel queue, and halts the controller */
2287 static int gfar_close(struct net_device *dev)
2288 {
2289         struct gfar_private *priv = netdev_priv(dev);
2290
2291         disable_napi(priv);
2292
2293         cancel_work_sync(&priv->reset_task);
2294         stop_gfar(dev);
2295
2296         /* Disconnect from the PHY */
2297         phy_disconnect(priv->phydev);
2298         priv->phydev = NULL;
2299
2300         netif_tx_stop_all_queues(dev);
2301
2302         return 0;
2303 }
2304
2305 /* Changes the mac address if the controller is not running. */
2306 static int gfar_set_mac_address(struct net_device *dev)
2307 {
2308         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2309
2310         return 0;
2311 }
2312
2313 /* Check if rx parser should be activated */
2314 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2315 {
2316         struct gfar __iomem *regs;
2317         u32 tempval;
2318
2319         regs = priv->gfargrp[0].regs;
2320
2321         tempval = gfar_read(&regs->rctrl);
2322         /* If parse is no longer required, then disable parser */
2323         if (tempval & RCTRL_REQ_PARSER) {
2324                 tempval |= RCTRL_PRSDEP_INIT;
2325                 priv->uses_rxfcb = 1;
2326         } else {
2327                 tempval &= ~RCTRL_PRSDEP_INIT;
2328                 priv->uses_rxfcb = 0;
2329         }
2330         gfar_write(&regs->rctrl, tempval);
2331 }
2332
2333 /* Enables and disables VLAN insertion/extraction */
2334 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2335 {
2336         struct gfar_private *priv = netdev_priv(dev);
2337         struct gfar __iomem *regs = NULL;
2338         unsigned long flags;
2339         u32 tempval;
2340
2341         regs = priv->gfargrp[0].regs;
2342         local_irq_save(flags);
2343         lock_rx_qs(priv);
2344
2345         if (features & NETIF_F_HW_VLAN_TX) {
2346                 /* Enable VLAN tag insertion */
2347                 tempval = gfar_read(&regs->tctrl);
2348                 tempval |= TCTRL_VLINS;
2349                 gfar_write(&regs->tctrl, tempval);
2350         } else {
2351                 /* Disable VLAN tag insertion */
2352                 tempval = gfar_read(&regs->tctrl);
2353                 tempval &= ~TCTRL_VLINS;
2354                 gfar_write(&regs->tctrl, tempval);
2355         }
2356
2357         if (features & NETIF_F_HW_VLAN_RX) {
2358                 /* Enable VLAN tag extraction */
2359                 tempval = gfar_read(&regs->rctrl);
2360                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2361                 gfar_write(&regs->rctrl, tempval);
2362                 priv->uses_rxfcb = 1;
2363         } else {
2364                 /* Disable VLAN tag extraction */
2365                 tempval = gfar_read(&regs->rctrl);
2366                 tempval &= ~RCTRL_VLEX;
2367                 gfar_write(&regs->rctrl, tempval);
2368
2369                 gfar_check_rx_parser_mode(priv);
2370         }
2371
2372         gfar_change_mtu(dev, dev->mtu);
2373
2374         unlock_rx_qs(priv);
2375         local_irq_restore(flags);
2376 }
2377
2378 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2379 {
2380         int tempsize, tempval;
2381         struct gfar_private *priv = netdev_priv(dev);
2382         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2383         int oldsize = priv->rx_buffer_size;
2384         int frame_size = new_mtu + ETH_HLEN;
2385
2386         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2387                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2388                 return -EINVAL;
2389         }
2390
2391         if (priv->uses_rxfcb)
2392                 frame_size += GMAC_FCB_LEN;
2393
2394         frame_size += priv->padding;
2395
2396         tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2397                    INCREMENTAL_BUFFER_SIZE;
2398
2399         /* Only stop and start the controller if it isn't already
2400          * stopped, and we changed something
2401          */
2402         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2403                 stop_gfar(dev);
2404
2405         priv->rx_buffer_size = tempsize;
2406
2407         dev->mtu = new_mtu;
2408
2409         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2410         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2411
2412         /* If the mtu is larger than the max size for standard
2413          * ethernet frames (ie, a jumbo frame), then set maccfg2
2414          * to allow huge frames, and to check the length
2415          */
2416         tempval = gfar_read(&regs->maccfg2);
2417
2418         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2419             gfar_has_errata(priv, GFAR_ERRATA_74))
2420                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2421         else
2422                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2423
2424         gfar_write(&regs->maccfg2, tempval);
2425
2426         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2427                 startup_gfar(dev);
2428
2429         return 0;
2430 }
2431
2432 /* gfar_reset_task gets scheduled when a packet has not been
2433  * transmitted after a set amount of time.
2434  * For now, assume that clearing out all the structures, and
2435  * starting over will fix the problem.
2436  */
2437 static void gfar_reset_task(struct work_struct *work)
2438 {
2439         struct gfar_private *priv = container_of(work, struct gfar_private,
2440                                                  reset_task);
2441         struct net_device *dev = priv->ndev;
2442
2443         if (dev->flags & IFF_UP) {
2444                 netif_tx_stop_all_queues(dev);
2445                 stop_gfar(dev);
2446                 startup_gfar(dev);
2447                 netif_tx_start_all_queues(dev);
2448         }
2449
2450         netif_tx_schedule_all(dev);
2451 }
2452
2453 static void gfar_timeout(struct net_device *dev)
2454 {
2455         struct gfar_private *priv = netdev_priv(dev);
2456
2457         dev->stats.tx_errors++;
2458         schedule_work(&priv->reset_task);
2459 }
2460
2461 static void gfar_align_skb(struct sk_buff *skb)
2462 {
2463         /* We need the data buffer to be aligned properly.  We will reserve
2464          * as many bytes as needed to align the data properly
2465          */
2466         skb_reserve(skb, RXBUF_ALIGNMENT -
2467                     (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2468 }
2469
2470 /* Interrupt Handler for Transmit complete */
2471 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2472 {
2473         struct net_device *dev = tx_queue->dev;
2474         struct netdev_queue *txq;
2475         struct gfar_private *priv = netdev_priv(dev);
2476         struct gfar_priv_rx_q *rx_queue = NULL;
2477         struct txbd8 *bdp, *next = NULL;
2478         struct txbd8 *lbdp = NULL;
2479         struct txbd8 *base = tx_queue->tx_bd_base;
2480         struct sk_buff *skb;
2481         int skb_dirtytx;
2482         int tx_ring_size = tx_queue->tx_ring_size;
2483         int frags = 0, nr_txbds = 0;
2484         int i;
2485         int howmany = 0;
2486         int tqi = tx_queue->qindex;
2487         unsigned int bytes_sent = 0;
2488         u32 lstatus;
2489         size_t buflen;
2490
2491         rx_queue = priv->rx_queue[tqi];
2492         txq = netdev_get_tx_queue(dev, tqi);
2493         bdp = tx_queue->dirty_tx;
2494         skb_dirtytx = tx_queue->skb_dirtytx;
2495
2496         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2497                 unsigned long flags;
2498
2499                 frags = skb_shinfo(skb)->nr_frags;
2500
2501                 /* When time stamping, one additional TxBD must be freed.
2502                  * Also, we need to dma_unmap_single() the TxPAL.
2503                  */
2504                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2505                         nr_txbds = frags + 2;
2506                 else
2507                         nr_txbds = frags + 1;
2508
2509                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2510
2511                 lstatus = lbdp->lstatus;
2512
2513                 /* Only clean completed frames */
2514                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2515                     (lstatus & BD_LENGTH_MASK))
2516                         break;
2517
2518                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2519                         next = next_txbd(bdp, base, tx_ring_size);
2520                         buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2521                 } else
2522                         buflen = bdp->length;
2523
2524                 dma_unmap_single(priv->dev, bdp->bufPtr,
2525                                  buflen, DMA_TO_DEVICE);
2526
2527                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2528                         struct skb_shared_hwtstamps shhwtstamps;
2529                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2530
2531                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2532                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2533                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2534                         skb_tstamp_tx(skb, &shhwtstamps);
2535                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2536                         bdp = next;
2537                 }
2538
2539                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2540                 bdp = next_txbd(bdp, base, tx_ring_size);
2541
2542                 for (i = 0; i < frags; i++) {
2543                         dma_unmap_page(priv->dev, bdp->bufPtr,
2544                                        bdp->length, DMA_TO_DEVICE);
2545                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2546                         bdp = next_txbd(bdp, base, tx_ring_size);
2547                 }
2548
2549                 bytes_sent += skb->len;
2550
2551                 dev_kfree_skb_any(skb);
2552
2553                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2554
2555                 skb_dirtytx = (skb_dirtytx + 1) &
2556                               TX_RING_MOD_MASK(tx_ring_size);
2557
2558                 howmany++;
2559                 spin_lock_irqsave(&tx_queue->txlock, flags);
2560                 tx_queue->num_txbdfree += nr_txbds;
2561                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2562         }
2563
2564         /* If we freed a buffer, we can restart transmission, if necessary */
2565         if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2566                 netif_wake_subqueue(dev, tqi);
2567
2568         /* Update dirty indicators */
2569         tx_queue->skb_dirtytx = skb_dirtytx;
2570         tx_queue->dirty_tx = bdp;
2571
2572         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2573
2574         return howmany;
2575 }
2576
2577 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2578 {
2579         unsigned long flags;
2580
2581         spin_lock_irqsave(&gfargrp->grplock, flags);
2582         if (napi_schedule_prep(&gfargrp->napi)) {
2583                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2584                 __napi_schedule(&gfargrp->napi);
2585         } else {
2586                 /* Clear IEVENT, so interrupts aren't called again
2587                  * because of the packets that have already arrived.
2588                  */
2589                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2590         }
2591         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2592
2593 }
2594
2595 /* Interrupt Handler for Transmit complete */
2596 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2597 {
2598         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2599         return IRQ_HANDLED;
2600 }
2601
2602 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2603                            struct sk_buff *skb)
2604 {
2605         struct net_device *dev = rx_queue->dev;
2606         struct gfar_private *priv = netdev_priv(dev);
2607         dma_addr_t buf;
2608
2609         buf = dma_map_single(priv->dev, skb->data,
2610                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2611         gfar_init_rxbdp(rx_queue, bdp, buf);
2612 }
2613
2614 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2615 {
2616         struct gfar_private *priv = netdev_priv(dev);
2617         struct sk_buff *skb;
2618
2619         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2620         if (!skb)
2621                 return NULL;
2622
2623         gfar_align_skb(skb);
2624
2625         return skb;
2626 }
2627
2628 struct sk_buff *gfar_new_skb(struct net_device *dev)
2629 {
2630         return gfar_alloc_skb(dev);
2631 }
2632
2633 static inline void count_errors(unsigned short status, struct net_device *dev)
2634 {
2635         struct gfar_private *priv = netdev_priv(dev);
2636         struct net_device_stats *stats = &dev->stats;
2637         struct gfar_extra_stats *estats = &priv->extra_stats;
2638
2639         /* If the packet was truncated, none of the other errors matter */
2640         if (status & RXBD_TRUNCATED) {
2641                 stats->rx_length_errors++;
2642
2643                 atomic64_inc(&estats->rx_trunc);
2644
2645                 return;
2646         }
2647         /* Count the errors, if there were any */
2648         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2649                 stats->rx_length_errors++;
2650
2651                 if (status & RXBD_LARGE)
2652                         atomic64_inc(&estats->rx_large);
2653                 else
2654                         atomic64_inc(&estats->rx_short);
2655         }
2656         if (status & RXBD_NONOCTET) {
2657                 stats->rx_frame_errors++;
2658                 atomic64_inc(&estats->rx_nonoctet);
2659         }
2660         if (status & RXBD_CRCERR) {
2661                 atomic64_inc(&estats->rx_crcerr);
2662                 stats->rx_crc_errors++;
2663         }
2664         if (status & RXBD_OVERRUN) {
2665                 atomic64_inc(&estats->rx_overrun);
2666                 stats->rx_crc_errors++;
2667         }
2668 }
2669
2670 irqreturn_t gfar_receive(int irq, void *grp_id)
2671 {
2672         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2673         return IRQ_HANDLED;
2674 }
2675
2676 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2677 {
2678         /* If valid headers were found, and valid sums
2679          * were verified, then we tell the kernel that no
2680          * checksumming is necessary.  Otherwise, it is [FIXME]
2681          */
2682         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2683                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2684         else
2685                 skb_checksum_none_assert(skb);
2686 }
2687
2688
2689 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2690 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2691                                int amount_pull, struct napi_struct *napi)
2692 {
2693         struct gfar_private *priv = netdev_priv(dev);
2694         struct rxfcb *fcb = NULL;
2695
2696         gro_result_t ret;
2697
2698         /* fcb is at the beginning if exists */
2699         fcb = (struct rxfcb *)skb->data;
2700
2701         /* Remove the FCB from the skb
2702          * Remove the padded bytes, if there are any
2703          */
2704         if (amount_pull) {
2705                 skb_record_rx_queue(skb, fcb->rq);
2706                 skb_pull(skb, amount_pull);
2707         }
2708
2709         /* Get receive timestamp from the skb */
2710         if (priv->hwts_rx_en) {
2711                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2712                 u64 *ns = (u64 *) skb->data;
2713
2714                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2715                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2716         }
2717
2718         if (priv->padding)
2719                 skb_pull(skb, priv->padding);
2720
2721         if (dev->features & NETIF_F_RXCSUM)
2722                 gfar_rx_checksum(skb, fcb);
2723
2724         /* Tell the skb what kind of packet this is */
2725         skb->protocol = eth_type_trans(skb, dev);
2726
2727         /* There's need to check for NETIF_F_HW_VLAN_RX here.
2728          * Even if vlan rx accel is disabled, on some chips
2729          * RXFCB_VLN is pseudo randomly set.
2730          */
2731         if (dev->features & NETIF_F_HW_VLAN_RX &&
2732             fcb->flags & RXFCB_VLN)
2733                 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2734
2735         /* Send the packet up the stack */
2736         ret = napi_gro_receive(napi, skb);
2737
2738         if (unlikely(GRO_DROP == ret))
2739                 atomic64_inc(&priv->extra_stats.kernel_dropped);
2740 }
2741
2742 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2743  * until the budget/quota has been reached. Returns the number
2744  * of frames handled
2745  */
2746 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2747 {
2748         struct net_device *dev = rx_queue->dev;
2749         struct rxbd8 *bdp, *base;
2750         struct sk_buff *skb;
2751         int pkt_len;
2752         int amount_pull;
2753         int howmany = 0;
2754         struct gfar_private *priv = netdev_priv(dev);
2755
2756         /* Get the first full descriptor */
2757         bdp = rx_queue->cur_rx;
2758         base = rx_queue->rx_bd_base;
2759
2760         amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2761
2762         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2763                 struct sk_buff *newskb;
2764
2765                 rmb();
2766
2767                 /* Add another skb for the future */
2768                 newskb = gfar_new_skb(dev);
2769
2770                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2771
2772                 dma_unmap_single(priv->dev, bdp->bufPtr,
2773                                  priv->rx_buffer_size, DMA_FROM_DEVICE);
2774
2775                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2776                              bdp->length > priv->rx_buffer_size))
2777                         bdp->status = RXBD_LARGE;
2778
2779                 /* We drop the frame if we failed to allocate a new buffer */
2780                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2781                              bdp->status & RXBD_ERR)) {
2782                         count_errors(bdp->status, dev);
2783
2784                         if (unlikely(!newskb))
2785                                 newskb = skb;
2786                         else if (skb)
2787                                 dev_kfree_skb(skb);
2788                 } else {
2789                         /* Increment the number of packets */
2790                         rx_queue->stats.rx_packets++;
2791                         howmany++;
2792
2793                         if (likely(skb)) {
2794                                 pkt_len = bdp->length - ETH_FCS_LEN;
2795                                 /* Remove the FCS from the packet length */
2796                                 skb_put(skb, pkt_len);
2797                                 rx_queue->stats.rx_bytes += pkt_len;
2798                                 skb_record_rx_queue(skb, rx_queue->qindex);
2799                                 gfar_process_frame(dev, skb, amount_pull,
2800                                                    &rx_queue->grp->napi);
2801
2802                         } else {
2803                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2804                                 rx_queue->stats.rx_dropped++;
2805                                 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2806                         }
2807
2808                 }
2809
2810                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2811
2812                 /* Setup the new bdp */
2813                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2814
2815                 /* Update to the next pointer */
2816                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2817
2818                 /* update to point at the next skb */
2819                 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2820                                       RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2821         }
2822
2823         /* Update the current rxbd pointer to be the next one */
2824         rx_queue->cur_rx = bdp;
2825
2826         return howmany;
2827 }
2828
2829 static int gfar_poll(struct napi_struct *napi, int budget)
2830 {
2831         struct gfar_priv_grp *gfargrp =
2832                 container_of(napi, struct gfar_priv_grp, napi);
2833         struct gfar_private *priv = gfargrp->priv;
2834         struct gfar __iomem *regs = gfargrp->regs;
2835         struct gfar_priv_tx_q *tx_queue = NULL;
2836         struct gfar_priv_rx_q *rx_queue = NULL;
2837         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2838         int tx_cleaned = 0, i, left_over_budget = budget;
2839         unsigned long serviced_queues = 0;
2840         int num_queues = 0;
2841
2842         num_queues = gfargrp->num_rx_queues;
2843         budget_per_queue = budget/num_queues;
2844
2845         /* Clear IEVENT, so interrupts aren't called again
2846          * because of the packets that have already arrived
2847          */
2848         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2849
2850         while (num_queues && left_over_budget) {
2851                 budget_per_queue = left_over_budget/num_queues;
2852                 left_over_budget = 0;
2853
2854                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2855                         if (test_bit(i, &serviced_queues))
2856                                 continue;
2857                         rx_queue = priv->rx_queue[i];
2858                         tx_queue = priv->tx_queue[rx_queue->qindex];
2859
2860                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2861                         rx_cleaned_per_queue =
2862                                 gfar_clean_rx_ring(rx_queue, budget_per_queue);
2863                         rx_cleaned += rx_cleaned_per_queue;
2864                         if (rx_cleaned_per_queue < budget_per_queue) {
2865                                 left_over_budget = left_over_budget +
2866                                         (budget_per_queue -
2867                                          rx_cleaned_per_queue);
2868                                 set_bit(i, &serviced_queues);
2869                                 num_queues--;
2870                         }
2871                 }
2872         }
2873
2874         if (tx_cleaned)
2875                 return budget;
2876
2877         if (rx_cleaned < budget) {
2878                 napi_complete(napi);
2879
2880                 /* Clear the halt bit in RSTAT */
2881                 gfar_write(&regs->rstat, gfargrp->rstat);
2882
2883                 gfar_write(&regs->imask, IMASK_DEFAULT);
2884
2885                 /* If we are coalescing interrupts, update the timer
2886                  * Otherwise, clear it
2887                  */
2888                 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2889                                           gfargrp->tx_bit_map);
2890         }
2891
2892         return rx_cleaned;
2893 }
2894
2895 #ifdef CONFIG_NET_POLL_CONTROLLER
2896 /* Polling 'interrupt' - used by things like netconsole to send skbs
2897  * without having to re-enable interrupts. It's not called while
2898  * the interrupt routine is executing.
2899  */
2900 static void gfar_netpoll(struct net_device *dev)
2901 {
2902         struct gfar_private *priv = netdev_priv(dev);
2903         int i;
2904
2905         /* If the device has multiple interrupts, run tx/rx */
2906         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2907                 for (i = 0; i < priv->num_grps; i++) {
2908                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
2909
2910                         disable_irq(gfar_irq(grp, TX)->irq);
2911                         disable_irq(gfar_irq(grp, RX)->irq);
2912                         disable_irq(gfar_irq(grp, ER)->irq);
2913                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2914                         enable_irq(gfar_irq(grp, ER)->irq);
2915                         enable_irq(gfar_irq(grp, RX)->irq);
2916                         enable_irq(gfar_irq(grp, TX)->irq);
2917                 }
2918         } else {
2919                 for (i = 0; i < priv->num_grps; i++) {
2920                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
2921
2922                         disable_irq(gfar_irq(grp, TX)->irq);
2923                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2924                         enable_irq(gfar_irq(grp, TX)->irq);
2925                 }
2926         }
2927 }
2928 #endif
2929
2930 /* The interrupt handler for devices with one interrupt */
2931 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2932 {
2933         struct gfar_priv_grp *gfargrp = grp_id;
2934
2935         /* Save ievent for future reference */
2936         u32 events = gfar_read(&gfargrp->regs->ievent);
2937
2938         /* Check for reception */
2939         if (events & IEVENT_RX_MASK)
2940                 gfar_receive(irq, grp_id);
2941
2942         /* Check for transmit completion */
2943         if (events & IEVENT_TX_MASK)
2944                 gfar_transmit(irq, grp_id);
2945
2946         /* Check for errors */
2947         if (events & IEVENT_ERR_MASK)
2948                 gfar_error(irq, grp_id);
2949
2950         return IRQ_HANDLED;
2951 }
2952
2953 /* Called every time the controller might need to be made
2954  * aware of new link state.  The PHY code conveys this
2955  * information through variables in the phydev structure, and this
2956  * function converts those variables into the appropriate
2957  * register values, and can bring down the device if needed.
2958  */
2959 static void adjust_link(struct net_device *dev)
2960 {
2961         struct gfar_private *priv = netdev_priv(dev);
2962         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2963         unsigned long flags;
2964         struct phy_device *phydev = priv->phydev;
2965         int new_state = 0;
2966
2967         local_irq_save(flags);
2968         lock_tx_qs(priv);
2969
2970         if (phydev->link) {
2971                 u32 tempval = gfar_read(&regs->maccfg2);
2972                 u32 ecntrl = gfar_read(&regs->ecntrl);
2973
2974                 /* Now we make sure that we can be in full duplex mode.
2975                  * If not, we operate in half-duplex mode.
2976                  */
2977                 if (phydev->duplex != priv->oldduplex) {
2978                         new_state = 1;
2979                         if (!(phydev->duplex))
2980                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2981                         else
2982                                 tempval |= MACCFG2_FULL_DUPLEX;
2983
2984                         priv->oldduplex = phydev->duplex;
2985                 }
2986
2987                 if (phydev->speed != priv->oldspeed) {
2988                         new_state = 1;
2989                         switch (phydev->speed) {
2990                         case 1000:
2991                                 tempval =
2992                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2993
2994                                 ecntrl &= ~(ECNTRL_R100);
2995                                 break;
2996                         case 100:
2997                         case 10:
2998                                 tempval =
2999                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3000
3001                                 /* Reduced mode distinguishes
3002                                  * between 10 and 100
3003                                  */
3004                                 if (phydev->speed == SPEED_100)
3005                                         ecntrl |= ECNTRL_R100;
3006                                 else
3007                                         ecntrl &= ~(ECNTRL_R100);
3008                                 break;
3009                         default:
3010                                 netif_warn(priv, link, dev,
3011                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3012                                            phydev->speed);
3013                                 break;
3014                         }
3015
3016                         priv->oldspeed = phydev->speed;
3017                 }
3018
3019                 gfar_write(&regs->maccfg2, tempval);
3020                 gfar_write(&regs->ecntrl, ecntrl);
3021
3022                 if (!priv->oldlink) {
3023                         new_state = 1;
3024                         priv->oldlink = 1;
3025                 }
3026         } else if (priv->oldlink) {
3027                 new_state = 1;
3028                 priv->oldlink = 0;
3029                 priv->oldspeed = 0;
3030                 priv->oldduplex = -1;
3031         }
3032
3033         if (new_state && netif_msg_link(priv))
3034                 phy_print_status(phydev);
3035         unlock_tx_qs(priv);
3036         local_irq_restore(flags);
3037 }
3038
3039 /* Update the hash table based on the current list of multicast
3040  * addresses we subscribe to.  Also, change the promiscuity of
3041  * the device based on the flags (this function is called
3042  * whenever dev->flags is changed
3043  */
3044 static void gfar_set_multi(struct net_device *dev)
3045 {
3046         struct netdev_hw_addr *ha;
3047         struct gfar_private *priv = netdev_priv(dev);
3048         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3049         u32 tempval;
3050
3051         if (dev->flags & IFF_PROMISC) {
3052                 /* Set RCTRL to PROM */
3053                 tempval = gfar_read(&regs->rctrl);
3054                 tempval |= RCTRL_PROM;
3055                 gfar_write(&regs->rctrl, tempval);
3056         } else {
3057                 /* Set RCTRL to not PROM */
3058                 tempval = gfar_read(&regs->rctrl);
3059                 tempval &= ~(RCTRL_PROM);
3060                 gfar_write(&regs->rctrl, tempval);
3061         }
3062
3063         if (dev->flags & IFF_ALLMULTI) {
3064                 /* Set the hash to rx all multicast frames */
3065                 gfar_write(&regs->igaddr0, 0xffffffff);
3066                 gfar_write(&regs->igaddr1, 0xffffffff);
3067                 gfar_write(&regs->igaddr2, 0xffffffff);
3068                 gfar_write(&regs->igaddr3, 0xffffffff);
3069                 gfar_write(&regs->igaddr4, 0xffffffff);
3070                 gfar_write(&regs->igaddr5, 0xffffffff);
3071                 gfar_write(&regs->igaddr6, 0xffffffff);
3072                 gfar_write(&regs->igaddr7, 0xffffffff);
3073                 gfar_write(&regs->gaddr0, 0xffffffff);
3074                 gfar_write(&regs->gaddr1, 0xffffffff);
3075                 gfar_write(&regs->gaddr2, 0xffffffff);
3076                 gfar_write(&regs->gaddr3, 0xffffffff);
3077                 gfar_write(&regs->gaddr4, 0xffffffff);
3078                 gfar_write(&regs->gaddr5, 0xffffffff);
3079                 gfar_write(&regs->gaddr6, 0xffffffff);
3080                 gfar_write(&regs->gaddr7, 0xffffffff);
3081         } else {
3082                 int em_num;
3083                 int idx;
3084
3085                 /* zero out the hash */
3086                 gfar_write(&regs->igaddr0, 0x0);
3087                 gfar_write(&regs->igaddr1, 0x0);
3088                 gfar_write(&regs->igaddr2, 0x0);
3089                 gfar_write(&regs->igaddr3, 0x0);
3090                 gfar_write(&regs->igaddr4, 0x0);
3091                 gfar_write(&regs->igaddr5, 0x0);
3092                 gfar_write(&regs->igaddr6, 0x0);
3093                 gfar_write(&regs->igaddr7, 0x0);
3094                 gfar_write(&regs->gaddr0, 0x0);
3095                 gfar_write(&regs->gaddr1, 0x0);
3096                 gfar_write(&regs->gaddr2, 0x0);
3097                 gfar_write(&regs->gaddr3, 0x0);
3098                 gfar_write(&regs->gaddr4, 0x0);
3099                 gfar_write(&regs->gaddr5, 0x0);
3100                 gfar_write(&regs->gaddr6, 0x0);
3101                 gfar_write(&regs->gaddr7, 0x0);
3102
3103                 /* If we have extended hash tables, we need to
3104                  * clear the exact match registers to prepare for
3105                  * setting them
3106                  */
3107                 if (priv->extended_hash) {
3108                         em_num = GFAR_EM_NUM + 1;
3109                         gfar_clear_exact_match(dev);
3110                         idx = 1;
3111                 } else {
3112                         idx = 0;
3113                         em_num = 0;
3114                 }
3115
3116                 if (netdev_mc_empty(dev))
3117                         return;
3118
3119                 /* Parse the list, and set the appropriate bits */
3120                 netdev_for_each_mc_addr(ha, dev) {
3121                         if (idx < em_num) {
3122                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3123                                 idx++;
3124                         } else
3125                                 gfar_set_hash_for_addr(dev, ha->addr);
3126                 }
3127         }
3128 }
3129
3130
3131 /* Clears each of the exact match registers to zero, so they
3132  * don't interfere with normal reception
3133  */
3134 static void gfar_clear_exact_match(struct net_device *dev)
3135 {
3136         int idx;
3137         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3138
3139         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3140                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3141 }
3142
3143 /* Set the appropriate hash bit for the given addr */
3144 /* The algorithm works like so:
3145  * 1) Take the Destination Address (ie the multicast address), and
3146  * do a CRC on it (little endian), and reverse the bits of the
3147  * result.
3148  * 2) Use the 8 most significant bits as a hash into a 256-entry
3149  * table.  The table is controlled through 8 32-bit registers:
3150  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3151  * gaddr7.  This means that the 3 most significant bits in the
3152  * hash index which gaddr register to use, and the 5 other bits
3153  * indicate which bit (assuming an IBM numbering scheme, which
3154  * for PowerPC (tm) is usually the case) in the register holds
3155  * the entry.
3156  */
3157 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3158 {
3159         u32 tempval;
3160         struct gfar_private *priv = netdev_priv(dev);
3161         u32 result = ether_crc(ETH_ALEN, addr);
3162         int width = priv->hash_width;
3163         u8 whichbit = (result >> (32 - width)) & 0x1f;
3164         u8 whichreg = result >> (32 - width + 5);
3165         u32 value = (1 << (31-whichbit));
3166
3167         tempval = gfar_read(priv->hash_regs[whichreg]);
3168         tempval |= value;
3169         gfar_write(priv->hash_regs[whichreg], tempval);
3170 }
3171
3172
3173 /* There are multiple MAC Address register pairs on some controllers
3174  * This function sets the numth pair to a given address
3175  */
3176 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3177                                   const u8 *addr)
3178 {
3179         struct gfar_private *priv = netdev_priv(dev);
3180         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3181         int idx;
3182         char tmpbuf[ETH_ALEN];
3183         u32 tempval;
3184         u32 __iomem *macptr = &regs->macstnaddr1;
3185
3186         macptr += num*2;
3187
3188         /* Now copy it into the mac registers backwards, cuz
3189          * little endian is silly
3190          */
3191         for (idx = 0; idx < ETH_ALEN; idx++)
3192                 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3193
3194         gfar_write(macptr, *((u32 *) (tmpbuf)));
3195
3196         tempval = *((u32 *) (tmpbuf + 4));
3197
3198         gfar_write(macptr+1, tempval);
3199 }
3200
3201 /* GFAR error interrupt handler */
3202 static irqreturn_t gfar_error(int irq, void *grp_id)
3203 {
3204         struct gfar_priv_grp *gfargrp = grp_id;
3205         struct gfar __iomem *regs = gfargrp->regs;
3206         struct gfar_private *priv= gfargrp->priv;
3207         struct net_device *dev = priv->ndev;
3208
3209         /* Save ievent for future reference */
3210         u32 events = gfar_read(&regs->ievent);
3211
3212         /* Clear IEVENT */
3213         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3214
3215         /* Magic Packet is not an error. */
3216         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3217             (events & IEVENT_MAG))
3218                 events &= ~IEVENT_MAG;
3219
3220         /* Hmm... */
3221         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3222                 netdev_dbg(dev,
3223                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3224                            events, gfar_read(&regs->imask));
3225
3226         /* Update the error counters */
3227         if (events & IEVENT_TXE) {
3228                 dev->stats.tx_errors++;
3229
3230                 if (events & IEVENT_LC)
3231                         dev->stats.tx_window_errors++;
3232                 if (events & IEVENT_CRL)
3233                         dev->stats.tx_aborted_errors++;
3234                 if (events & IEVENT_XFUN) {
3235                         unsigned long flags;
3236
3237                         netif_dbg(priv, tx_err, dev,
3238                                   "TX FIFO underrun, packet dropped\n");
3239                         dev->stats.tx_dropped++;
3240                         atomic64_inc(&priv->extra_stats.tx_underrun);
3241
3242                         local_irq_save(flags);
3243                         lock_tx_qs(priv);
3244
3245                         /* Reactivate the Tx Queues */
3246                         gfar_write(&regs->tstat, gfargrp->tstat);
3247
3248                         unlock_tx_qs(priv);
3249                         local_irq_restore(flags);
3250                 }
3251                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3252         }
3253         if (events & IEVENT_BSY) {
3254                 dev->stats.rx_errors++;
3255                 atomic64_inc(&priv->extra_stats.rx_bsy);
3256
3257                 gfar_receive(irq, grp_id);
3258
3259                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3260                           gfar_read(&regs->rstat));
3261         }
3262         if (events & IEVENT_BABR) {
3263                 dev->stats.rx_errors++;
3264                 atomic64_inc(&priv->extra_stats.rx_babr);
3265
3266                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3267         }
3268         if (events & IEVENT_EBERR) {
3269                 atomic64_inc(&priv->extra_stats.eberr);
3270                 netif_dbg(priv, rx_err, dev, "bus error\n");
3271         }
3272         if (events & IEVENT_RXC)
3273                 netif_dbg(priv, rx_status, dev, "control frame\n");
3274
3275         if (events & IEVENT_BABT) {
3276                 atomic64_inc(&priv->extra_stats.tx_babt);
3277                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3278         }
3279         return IRQ_HANDLED;
3280 }
3281
3282 static struct of_device_id gfar_match[] =
3283 {
3284         {
3285                 .type = "network",
3286                 .compatible = "gianfar",
3287         },
3288         {
3289                 .compatible = "fsl,etsec2",
3290         },
3291         {},
3292 };
3293 MODULE_DEVICE_TABLE(of, gfar_match);
3294
3295 /* Structure for a device driver */
3296 static struct platform_driver gfar_driver = {
3297         .driver = {
3298                 .name = "fsl-gianfar",
3299                 .owner = THIS_MODULE,
3300                 .pm = GFAR_PM_OPS,
3301                 .of_match_table = gfar_match,
3302         },
3303         .probe = gfar_probe,
3304         .remove = gfar_remove,
3305 };
3306
3307 module_platform_driver(gfar_driver);