drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/of_mdio.h>
  82 #include <linux/of_platform.h>
  83 #include <linux/ip.h>
  84 #include <linux/tcp.h>
  85 #include <linux/udp.h>
  86 #include <linux/in.h>
  87 #include <linux/net_tstamp.h>
  88
  89 #include <asm/io.h>
  90 #include <asm/reg.h>
  91 #include <asm/mpc85xx.h>
  92 #include <asm/irq.h>
  93 #include <asm/uaccess.h>
  94 #include <linux/module.h>
  95 #include <linux/dma-mapping.h>
  96 #include <linux/crc32.h>
  97 #include <linux/mii.h>
  98 #include <linux/phy.h>
  99 #include <linux/phy_fixed.h>
 100 #include <linux/of.h>
 101 #include <linux/of_net.h>
 102
 103 #include "gianfar.h"
 104
 105 #define TX_TIMEOUT      (1*HZ)
 106
 107 const char gfar_driver_version[] = "1.3";
 108
 109 static int gfar_enet_open(struct net_device *dev);
 110 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 111 static void gfar_reset_task(struct work_struct *work);
 112 static void gfar_timeout(struct net_device *dev);
 113 static int gfar_close(struct net_device *dev);
 114 struct sk_buff *gfar_new_skb(struct net_device *dev);
 115 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 116                            struct sk_buff *skb);
 117 static int gfar_set_mac_address(struct net_device *dev);
 118 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 119 static irqreturn_t gfar_error(int irq, void *dev_id);
 120 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 121 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 122 static void adjust_link(struct net_device *dev);
 123 static void init_registers(struct net_device *dev);
 124 static int init_phy(struct net_device *dev);
 125 static int gfar_probe(struct platform_device *ofdev);
 126 static int gfar_remove(struct platform_device *ofdev);
 127 static void free_skb_resources(struct gfar_private *priv);
 128 static void gfar_set_multi(struct net_device *dev);
 129 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 130 static void gfar_configure_serdes(struct net_device *dev);
 131 static int gfar_poll(struct napi_struct *napi, int budget);
 132 static int gfar_poll_sq(struct napi_struct *napi, int budget);
 133 #ifdef CONFIG_NET_POLL_CONTROLLER
 134 static void gfar_netpoll(struct net_device *dev);
 135 #endif
 136 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 137 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 138 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 139                                int amount_pull, struct napi_struct *napi);
 140 void gfar_halt(struct net_device *dev);
 141 static void gfar_halt_nodisable(struct net_device *dev);
 142 void gfar_start(struct net_device *dev);
 143 static void gfar_clear_exact_match(struct net_device *dev);
 144 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 145                                   const u8 *addr);
 146 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 147
 148 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 149 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 150 MODULE_LICENSE("GPL");
 151
 152 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 153                             dma_addr_t buf)
 154 {
 155         u32 lstatus;
 156
 157         bdp->bufPtr = buf;
 158
 159         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 160         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 161                 lstatus |= BD_LFLAG(RXBD_WRAP);
 162
 163         eieio();
 164
 165         bdp->lstatus = lstatus;
 166 }
 167
 168 static int gfar_init_bds(struct net_device *ndev)
 169 {
 170         struct gfar_private *priv = netdev_priv(ndev);
 171         struct gfar_priv_tx_q *tx_queue = NULL;
 172         struct gfar_priv_rx_q *rx_queue = NULL;
 173         struct txbd8 *txbdp;
 174         struct rxbd8 *rxbdp;
 175         int i, j;
 176
 177         for (i = 0; i < priv->num_tx_queues; i++) {
 178                 tx_queue = priv->tx_queue[i];
 179                 /* Initialize some variables in our dev structure */
 180                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 181                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 182                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 183                 tx_queue->skb_curtx = 0;
 184                 tx_queue->skb_dirtytx = 0;
 185
 186                 /* Initialize Transmit Descriptor Ring */
 187                 txbdp = tx_queue->tx_bd_base;
 188                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 189                         txbdp->lstatus = 0;
 190                         txbdp->bufPtr = 0;
 191                         txbdp++;
 192                 }
 193
 194                 /* Set the last descriptor in the ring to indicate wrap */
 195                 txbdp--;
 196                 txbdp->status |= TXBD_WRAP;
 197         }
 198
 199         for (i = 0; i < priv->num_rx_queues; i++) {
 200                 rx_queue = priv->rx_queue[i];
 201                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 202                 rx_queue->skb_currx = 0;
 203                 rxbdp = rx_queue->rx_bd_base;
 204
 205                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 206                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 207
 208                         if (skb) {
 209                                 gfar_init_rxbdp(rx_queue, rxbdp,
 210                                                 rxbdp->bufPtr);
 211                         } else {
 212                                 skb = gfar_new_skb(ndev);
 213                                 if (!skb) {
 214                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 215                                         return -ENOMEM;
 216                                 }
 217                                 rx_queue->rx_skbuff[j] = skb;
 218
 219                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 220                         }
 221
 222                         rxbdp++;
 223                 }
 224
 225         }
 226
 227         return 0;
 228 }
 229
 230 static int gfar_alloc_skb_resources(struct net_device *ndev)
 231 {
 232         void *vaddr;
 233         dma_addr_t addr;
 234         int i, j, k;
 235         struct gfar_private *priv = netdev_priv(ndev);
 236         struct device *dev = priv->dev;
 237         struct gfar_priv_tx_q *tx_queue = NULL;
 238         struct gfar_priv_rx_q *rx_queue = NULL;
 239
 240         priv->total_tx_ring_size = 0;
 241         for (i = 0; i < priv->num_tx_queues; i++)
 242                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 243
 244         priv->total_rx_ring_size = 0;
 245         for (i = 0; i < priv->num_rx_queues; i++)
 246                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 247
 248         /* Allocate memory for the buffer descriptors */
 249         vaddr = dma_alloc_coherent(dev,
 250                                    (priv->total_tx_ring_size *
 251                                     sizeof(struct txbd8)) +
 252                                    (priv->total_rx_ring_size *
 253                                     sizeof(struct rxbd8)),
 254                                    &addr, GFP_KERNEL);
 255         if (!vaddr)
 256                 return -ENOMEM;
 257
 258         for (i = 0; i < priv->num_tx_queues; i++) {
 259                 tx_queue = priv->tx_queue[i];
 260                 tx_queue->tx_bd_base = vaddr;
 261                 tx_queue->tx_bd_dma_base = addr;
 262                 tx_queue->dev = ndev;
 263                 /* enet DMA only understands physical addresses */
 264                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 265                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 266         }
 267
 268         /* Start the rx descriptor ring where the tx ring leaves off */
 269         for (i = 0; i < priv->num_rx_queues; i++) {
 270                 rx_queue = priv->rx_queue[i];
 271                 rx_queue->rx_bd_base = vaddr;
 272                 rx_queue->rx_bd_dma_base = addr;
 273                 rx_queue->dev = ndev;
 274                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 275                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 276         }
 277
 278         /* Setup the skbuff rings */
 279         for (i = 0; i < priv->num_tx_queues; i++) {
 280                 tx_queue = priv->tx_queue[i];
 281                 tx_queue->tx_skbuff =
 282                         kmalloc_array(tx_queue->tx_ring_size,
 283                                       sizeof(*tx_queue->tx_skbuff),
 284                                       GFP_KERNEL);
 285                 if (!tx_queue->tx_skbuff)
 286                         goto cleanup;
 287
 288                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 289                         tx_queue->tx_skbuff[k] = NULL;
 290         }
 291
 292         for (i = 0; i < priv->num_rx_queues; i++) {
 293                 rx_queue = priv->rx_queue[i];
 294                 rx_queue->rx_skbuff =
 295                         kmalloc_array(rx_queue->rx_ring_size,
 296                                       sizeof(*rx_queue->rx_skbuff),
 297                                       GFP_KERNEL);
 298                 if (!rx_queue->rx_skbuff)
 299                         goto cleanup;
 300
 301                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 302                         rx_queue->rx_skbuff[j] = NULL;
 303         }
 304
 305         if (gfar_init_bds(ndev))
 306                 goto cleanup;
 307
 308         return 0;
 309
 310 cleanup:
 311         free_skb_resources(priv);
 312         return -ENOMEM;
 313 }
 314
 315 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 316 {
 317         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 318         u32 __iomem *baddr;
 319         int i;
 320
 321         baddr = &regs->tbase0;
 322         for (i = 0; i < priv->num_tx_queues; i++) {
 323                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 324                 baddr += 2;
 325         }
 326
 327         baddr = &regs->rbase0;
 328         for (i = 0; i < priv->num_rx_queues; i++) {
 329                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 330                 baddr += 2;
 331         }
 332 }
 333
 334 static void gfar_init_mac(struct net_device *ndev)
 335 {
 336         struct gfar_private *priv = netdev_priv(ndev);
 337         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 338         u32 rctrl = 0;
 339         u32 tctrl = 0;
 340         u32 attrs = 0;
 341
 342         /* write the tx/rx base registers */
 343         gfar_init_tx_rx_base(priv);
 344
 345         /* Configure the coalescing support */
 346         gfar_configure_coalescing_all(priv);
 347
 348         /* set this when rx hw offload (TOE) functions are being used */
 349         priv->uses_rxfcb = 0;
 350
 351         if (priv->rx_filer_enable) {
 352                 rctrl |= RCTRL_FILREN;
 353                 /* Program the RIR0 reg with the required distribution */
 354                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 355         }
 356
 357         /* Restore PROMISC mode */
 358         if (ndev->flags & IFF_PROMISC)
 359                 rctrl |= RCTRL_PROM;
 360
 361         if (ndev->features & NETIF_F_RXCSUM) {
 362                 rctrl |= RCTRL_CHECKSUMMING;
 363                 priv->uses_rxfcb = 1;
 364         }
 365
 366         if (priv->extended_hash) {
 367                 rctrl |= RCTRL_EXTHASH;
 368
 369                 gfar_clear_exact_match(ndev);
 370                 rctrl |= RCTRL_EMEN;
 371         }
 372
 373         if (priv->padding) {
 374                 rctrl &= ~RCTRL_PAL_MASK;
 375                 rctrl |= RCTRL_PADDING(priv->padding);
 376         }
 377
 378         /* Insert receive time stamps into padding alignment bytes */
 379         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 380                 rctrl &= ~RCTRL_PAL_MASK;
 381                 rctrl |= RCTRL_PADDING(8);
 382                 priv->padding = 8;
 383         }
 384
 385         /* Enable HW time stamping if requested from user space */
 386         if (priv->hwts_rx_en) {
 387                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 388                 priv->uses_rxfcb = 1;
 389         }
 390
 391         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) {
 392                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 393                 priv->uses_rxfcb = 1;
 394         }
 395
 396         /* Init rctrl based on our settings */
 397         gfar_write(&regs->rctrl, rctrl);
 398
 399         if (ndev->features & NETIF_F_IP_CSUM)
 400                 tctrl |= TCTRL_INIT_CSUM;
 401
 402         if (priv->prio_sched_en)
 403                 tctrl |= TCTRL_TXSCHED_PRIO;
 404         else {
 405                 tctrl |= TCTRL_TXSCHED_WRRS;
 406                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 407                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 408         }
 409
 410         gfar_write(&regs->tctrl, tctrl);
 411
 412         /* Set the extraction length and index */
 413         attrs = ATTRELI_EL(priv->rx_stash_size) |
 414                 ATTRELI_EI(priv->rx_stash_index);
 415
 416         gfar_write(&regs->attreli, attrs);
 417
 418         /* Start with defaults, and add stashing or locking
 419          * depending on the approprate variables
 420          */
 421         attrs = ATTR_INIT_SETTINGS;
 422
 423         if (priv->bd_stash_en)
 424                 attrs |= ATTR_BDSTASH;
 425
 426         if (priv->rx_stash_size != 0)
 427                 attrs |= ATTR_BUFSTASH;
 428
 429         gfar_write(&regs->attr, attrs);
 430
 431         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 432         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 433         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 434 }
 435
 436 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 437 {
 438         struct gfar_private *priv = netdev_priv(dev);
 439         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 440         unsigned long tx_packets = 0, tx_bytes = 0;
 441         int i;
 442
 443         for (i = 0; i < priv->num_rx_queues; i++) {
 444                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 445                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 446                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 447         }
 448
 449         dev->stats.rx_packets = rx_packets;
 450         dev->stats.rx_bytes   = rx_bytes;
 451         dev->stats.rx_dropped = rx_dropped;
 452
 453         for (i = 0; i < priv->num_tx_queues; i++) {
 454                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 455                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 456         }
 457
 458         dev->stats.tx_bytes   = tx_bytes;
 459         dev->stats.tx_packets = tx_packets;
 460
 461         return &dev->stats;
 462 }
 463
 464 static const struct net_device_ops gfar_netdev_ops = {
 465         .ndo_open = gfar_enet_open,
 466         .ndo_start_xmit = gfar_start_xmit,
 467         .ndo_stop = gfar_close,
 468         .ndo_change_mtu = gfar_change_mtu,
 469         .ndo_set_features = gfar_set_features,
 470         .ndo_set_rx_mode = gfar_set_multi,
 471         .ndo_tx_timeout = gfar_timeout,
 472         .ndo_do_ioctl = gfar_ioctl,
 473         .ndo_get_stats = gfar_get_stats,
 474         .ndo_set_mac_address = eth_mac_addr,
 475         .ndo_validate_addr = eth_validate_addr,
 476 #ifdef CONFIG_NET_POLL_CONTROLLER
 477         .ndo_poll_controller = gfar_netpoll,
 478 #endif
 479 };
 480
 481 void lock_rx_qs(struct gfar_private *priv)
 482 {
 483         int i;
 484
 485         for (i = 0; i < priv->num_rx_queues; i++)
 486                 spin_lock(&priv->rx_queue[i]->rxlock);
 487 }
 488
 489 void lock_tx_qs(struct gfar_private *priv)
 490 {
 491         int i;
 492
 493         for (i = 0; i < priv->num_tx_queues; i++)
 494                 spin_lock(&priv->tx_queue[i]->txlock);
 495 }
 496
 497 void unlock_rx_qs(struct gfar_private *priv)
 498 {
 499         int i;
 500
 501         for (i = 0; i < priv->num_rx_queues; i++)
 502                 spin_unlock(&priv->rx_queue[i]->rxlock);
 503 }
 504
 505 void unlock_tx_qs(struct gfar_private *priv)
 506 {
 507         int i;
 508
 509         for (i = 0; i < priv->num_tx_queues; i++)
 510                 spin_unlock(&priv->tx_queue[i]->txlock);
 511 }
 512
 513 static void free_tx_pointers(struct gfar_private *priv)
 514 {
 515         int i;
 516
 517         for (i = 0; i < priv->num_tx_queues; i++)
 518                 kfree(priv->tx_queue[i]);
 519 }
 520
 521 static void free_rx_pointers(struct gfar_private *priv)
 522 {
 523         int i;
 524
 525         for (i = 0; i < priv->num_rx_queues; i++)
 526                 kfree(priv->rx_queue[i]);
 527 }
 528
 529 static void unmap_group_regs(struct gfar_private *priv)
 530 {
 531         int i;
 532
 533         for (i = 0; i < MAXGROUPS; i++)
 534                 if (priv->gfargrp[i].regs)
 535                         iounmap(priv->gfargrp[i].regs);
 536 }
 537
 538 static void free_gfar_dev(struct gfar_private *priv)
 539 {
 540         int i, j;
 541
 542         for (i = 0; i < priv->num_grps; i++)
 543                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 544                         kfree(priv->gfargrp[i].irqinfo[j]);
 545                         priv->gfargrp[i].irqinfo[j] = NULL;
 546                 }
 547
 548         free_netdev(priv->ndev);
 549 }
 550
 551 static void disable_napi(struct gfar_private *priv)
 552 {
 553         int i;
 554
 555         for (i = 0; i < priv->num_grps; i++)
 556                 napi_disable(&priv->gfargrp[i].napi);
 557 }
 558
 559 static void enable_napi(struct gfar_private *priv)
 560 {
 561         int i;
 562
 563         for (i = 0; i < priv->num_grps; i++)
 564                 napi_enable(&priv->gfargrp[i].napi);
 565 }
 566
 567 static int gfar_parse_group(struct device_node *np,
 568                             struct gfar_private *priv, const char *model)
 569 {
 570         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 571         u32 *queue_mask;
 572         int i;
 573
 574         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 575                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 576                                           GFP_KERNEL);
 577                 if (!grp->irqinfo[i])
 578                         return -ENOMEM;
 579         }
 580
 581         grp->regs = of_iomap(np, 0);
 582         if (!grp->regs)
 583                 return -ENOMEM;
 584
 585         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 586
 587         /* If we aren't the FEC we have multiple interrupts */
 588         if (model && strcasecmp(model, "FEC")) {
 589                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 590                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 591                 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
 592                     gfar_irq(grp, RX)->irq == NO_IRQ ||
 593                     gfar_irq(grp, ER)->irq == NO_IRQ)
 594                         return -EINVAL;
 595         }
 596
 597         grp->priv = priv;
 598         spin_lock_init(&grp->grplock);
 599         if (priv->mode == MQ_MG_MODE) {
 600                 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
 601                 grp->rx_bit_map = queue_mask ?
 602                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 603                 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
 604                 grp->tx_bit_map = queue_mask ?
 605                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 606         } else {
 607                 grp->rx_bit_map = 0xFF;
 608                 grp->tx_bit_map = 0xFF;
 609         }
 610         priv->num_grps++;
 611
 612         return 0;
 613 }
 614
 615 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 616 {
 617         const char *model;
 618         const char *ctype;
 619         const void *mac_addr;
 620         int err = 0, i;
 621         struct net_device *dev = NULL;
 622         struct gfar_private *priv = NULL;
 623         struct device_node *np = ofdev->dev.of_node;
 624         struct device_node *child = NULL;
 625         const u32 *stash;
 626         const u32 *stash_len;
 627         const u32 *stash_idx;
 628         unsigned int num_tx_qs, num_rx_qs;
 629         u32 *tx_queues, *rx_queues;
 630
 631         if (!np || !of_device_is_available(np))
 632                 return -ENODEV;
 633
 634         /* parse the num of tx and rx queues */
 635         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 636         num_tx_qs = tx_queues ? *tx_queues : 1;
 637
 638         if (num_tx_qs > MAX_TX_QS) {
 639                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 640                        num_tx_qs, MAX_TX_QS);
 641                 pr_err("Cannot do alloc_etherdev, aborting\n");
 642                 return -EINVAL;
 643         }
 644
 645         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 646         num_rx_qs = rx_queues ? *rx_queues : 1;
 647
 648         if (num_rx_qs > MAX_RX_QS) {
 649                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 650                        num_rx_qs, MAX_RX_QS);
 651                 pr_err("Cannot do alloc_etherdev, aborting\n");
 652                 return -EINVAL;
 653         }
 654
 655         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 656         dev = *pdev;
 657         if (NULL == dev)
 658                 return -ENOMEM;
 659
 660         priv = netdev_priv(dev);
 661         priv->ndev = dev;
 662
 663         priv->num_tx_queues = num_tx_qs;
 664         netif_set_real_num_rx_queues(dev, num_rx_qs);
 665         priv->num_rx_queues = num_rx_qs;
 666         priv->num_grps = 0x0;
 667
 668         /* Init Rx queue filer rule set linked list */
 669         INIT_LIST_HEAD(&priv->rx_list.list);
 670         priv->rx_list.count = 0;
 671         mutex_init(&priv->rx_queue_access);
 672
 673         model = of_get_property(np, "model", NULL);
 674
 675         for (i = 0; i < MAXGROUPS; i++)
 676                 priv->gfargrp[i].regs = NULL;
 677
 678         /* Parse and initialize group specific information */
 679         if (of_device_is_compatible(np, "fsl,etsec2")) {
 680                 priv->mode = MQ_MG_MODE;
 681                 for_each_child_of_node(np, child) {
 682                         err = gfar_parse_group(child, priv, model);
 683                         if (err)
 684                                 goto err_grp_init;
 685                 }
 686         } else {
 687                 priv->mode = SQ_SG_MODE;
 688                 err = gfar_parse_group(np, priv, model);
 689                 if (err)
 690                         goto err_grp_init;
 691         }
 692
 693         for (i = 0; i < priv->num_tx_queues; i++)
 694                 priv->tx_queue[i] = NULL;
 695         for (i = 0; i < priv->num_rx_queues; i++)
 696                 priv->rx_queue[i] = NULL;
 697
 698         for (i = 0; i < priv->num_tx_queues; i++) {
 699                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 700                                             GFP_KERNEL);
 701                 if (!priv->tx_queue[i]) {
 702                         err = -ENOMEM;
 703                         goto tx_alloc_failed;
 704                 }
 705                 priv->tx_queue[i]->tx_skbuff = NULL;
 706                 priv->tx_queue[i]->qindex = i;
 707                 priv->tx_queue[i]->dev = dev;
 708                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 709         }
 710
 711         for (i = 0; i < priv->num_rx_queues; i++) {
 712                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 713                                             GFP_KERNEL);
 714                 if (!priv->rx_queue[i]) {
 715                         err = -ENOMEM;
 716                         goto rx_alloc_failed;
 717                 }
 718                 priv->rx_queue[i]->rx_skbuff = NULL;
 719                 priv->rx_queue[i]->qindex = i;
 720                 priv->rx_queue[i]->dev = dev;
 721                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 722         }
 723
 724
 725         stash = of_get_property(np, "bd-stash", NULL);
 726
 727         if (stash) {
 728                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 729                 priv->bd_stash_en = 1;
 730         }
 731
 732         stash_len = of_get_property(np, "rx-stash-len", NULL);
 733
 734         if (stash_len)
 735                 priv->rx_stash_size = *stash_len;
 736
 737         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 738
 739         if (stash_idx)
 740                 priv->rx_stash_index = *stash_idx;
 741
 742         if (stash_len || stash_idx)
 743                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 744
 745         mac_addr = of_get_mac_address(np);
 746
 747         if (mac_addr)
 748                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 749
 750         if (model && !strcasecmp(model, "TSEC"))
 751                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 752                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 753                                      FSL_GIANFAR_DEV_HAS_RMON |
 754                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 755
 756         if (model && !strcasecmp(model, "eTSEC"))
 757                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 758                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 759                                      FSL_GIANFAR_DEV_HAS_RMON |
 760                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 761                                      FSL_GIANFAR_DEV_HAS_PADDING |
 762                                      FSL_GIANFAR_DEV_HAS_CSUM |
 763                                      FSL_GIANFAR_DEV_HAS_VLAN |
 764                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 765                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 766                                      FSL_GIANFAR_DEV_HAS_TIMER;
 767
 768         ctype = of_get_property(np, "phy-connection-type", NULL);
 769
 770         /* We only care about rgmii-id.  The rest are autodetected */
 771         if (ctype && !strcmp(ctype, "rgmii-id"))
 772                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 773         else
 774                 priv->interface = PHY_INTERFACE_MODE_MII;
 775
 776         if (of_get_property(np, "fsl,magic-packet", NULL))
 777                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 778
 779         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 780
 781         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 782         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 783
 784         return 0;
 785
 786 rx_alloc_failed:
 787         free_rx_pointers(priv);
 788 tx_alloc_failed:
 789         free_tx_pointers(priv);
 790 err_grp_init:
 791         unmap_group_regs(priv);
 792         free_gfar_dev(priv);
 793         return err;
 794 }
 795
 796 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 797                                struct ifreq *ifr, int cmd)
 798 {
 799         struct hwtstamp_config config;
 800         struct gfar_private *priv = netdev_priv(netdev);
 801
 802         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 803                 return -EFAULT;
 804
 805         /* reserved for future extensions */
 806         if (config.flags)
 807                 return -EINVAL;
 808
 809         switch (config.tx_type) {
 810         case HWTSTAMP_TX_OFF:
 811                 priv->hwts_tx_en = 0;
 812                 break;
 813         case HWTSTAMP_TX_ON:
 814                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 815                         return -ERANGE;
 816                 priv->hwts_tx_en = 1;
 817                 break;
 818         default:
 819                 return -ERANGE;
 820         }
 821
 822         switch (config.rx_filter) {
 823         case HWTSTAMP_FILTER_NONE:
 824                 if (priv->hwts_rx_en) {
 825                         stop_gfar(netdev);
 826                         priv->hwts_rx_en = 0;
 827                         startup_gfar(netdev);
 828                 }
 829                 break;
 830         default:
 831                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 832                         return -ERANGE;
 833                 if (!priv->hwts_rx_en) {
 834                         stop_gfar(netdev);
 835                         priv->hwts_rx_en = 1;
 836                         startup_gfar(netdev);
 837                 }
 838                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 839                 break;
 840         }
 841
 842         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 843                 -EFAULT : 0;
 844 }
 845
 846 /* Ioctl MII Interface */
 847 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 848 {
 849         struct gfar_private *priv = netdev_priv(dev);
 850
 851         if (!netif_running(dev))
 852                 return -EINVAL;
 853
 854         if (cmd == SIOCSHWTSTAMP)
 855                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 856
 857         if (!priv->phydev)
 858                 return -ENODEV;
 859
 860         return phy_mii_ioctl(priv->phydev, rq, cmd);
 861 }
 862
 863 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 864 {
 865         unsigned int new_bit_map = 0x0;
 866         int mask = 0x1 << (max_qs - 1), i;
 867
 868         for (i = 0; i < max_qs; i++) {
 869                 if (bit_map & mask)
 870                         new_bit_map = new_bit_map + (1 << i);
 871                 mask = mask >> 0x1;
 872         }
 873         return new_bit_map;
 874 }
 875
 876 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 877                                    u32 class)
 878 {
 879         u32 rqfpr = FPR_FILER_MASK;
 880         u32 rqfcr = 0x0;
 881
 882         rqfar--;
 883         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 884         priv->ftp_rqfpr[rqfar] = rqfpr;
 885         priv->ftp_rqfcr[rqfar] = rqfcr;
 886         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 887
 888         rqfar--;
 889         rqfcr = RQFCR_CMP_NOMATCH;
 890         priv->ftp_rqfpr[rqfar] = rqfpr;
 891         priv->ftp_rqfcr[rqfar] = rqfcr;
 892         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 893
 894         rqfar--;
 895         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 896         rqfpr = class;
 897         priv->ftp_rqfcr[rqfar] = rqfcr;
 898         priv->ftp_rqfpr[rqfar] = rqfpr;
 899         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 900
 901         rqfar--;
 902         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 903         rqfpr = class;
 904         priv->ftp_rqfcr[rqfar] = rqfcr;
 905         priv->ftp_rqfpr[rqfar] = rqfpr;
 906         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 907
 908         return rqfar;
 909 }
 910
 911 static void gfar_init_filer_table(struct gfar_private *priv)
 912 {
 913         int i = 0x0;
 914         u32 rqfar = MAX_FILER_IDX;
 915         u32 rqfcr = 0x0;
 916         u32 rqfpr = FPR_FILER_MASK;
 917
 918         /* Default rule */
 919         rqfcr = RQFCR_CMP_MATCH;
 920         priv->ftp_rqfcr[rqfar] = rqfcr;
 921         priv->ftp_rqfpr[rqfar] = rqfpr;
 922         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 923
 924         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 925         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 926         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 927         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 928         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 929         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 930
 931         /* cur_filer_idx indicated the first non-masked rule */
 932         priv->cur_filer_idx = rqfar;
 933
 934         /* Rest are masked rules */
 935         rqfcr = RQFCR_CMP_NOMATCH;
 936         for (i = 0; i < rqfar; i++) {
 937                 priv->ftp_rqfcr[i] = rqfcr;
 938                 priv->ftp_rqfpr[i] = rqfpr;
 939                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 940         }
 941 }
 942
 943 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
 944 {
 945         unsigned int pvr = mfspr(SPRN_PVR);
 946         unsigned int svr = mfspr(SPRN_SVR);
 947         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 948         unsigned int rev = svr & 0xffff;
 949
 950         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 951         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 952             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 953                 priv->errata |= GFAR_ERRATA_74;
 954
 955         /* MPC8313 and MPC837x all rev */
 956         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 957             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 958                 priv->errata |= GFAR_ERRATA_76;
 959
 960         /* MPC8313 Rev < 2.0 */
 961         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
 962                 priv->errata |= GFAR_ERRATA_12;
 963 }
 964
 965 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
 966 {
 967         unsigned int svr = mfspr(SPRN_SVR);
 968
 969         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
 970                 priv->errata |= GFAR_ERRATA_12;
 971 }
 972
 973 static void gfar_detect_errata(struct gfar_private *priv)
 974 {
 975         struct device *dev = &priv->ofdev->dev;
 976
 977         /* no plans to fix */
 978         priv->errata |= GFAR_ERRATA_A002;
 979
 980         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
 981                 __gfar_detect_errata_85xx(priv);
 982         else /* non-mpc85xx parts, i.e. e300 core based */
 983                 __gfar_detect_errata_83xx(priv);
 984
 985         if (priv->errata)
 986                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 987                          priv->errata);
 988 }
 989
 990 /* Set up the ethernet device structure, private data,
 991  * and anything else we need before we start
 992  */
 993 static int gfar_probe(struct platform_device *ofdev)
 994 {
 995         u32 tempval;
 996         struct net_device *dev = NULL;
 997         struct gfar_private *priv = NULL;
 998         struct gfar __iomem *regs = NULL;
 999         int err = 0, i, grp_idx = 0;
1000         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
1001         u32 isrg = 0;
1002         u32 __iomem *baddr;
1003
1004         err = gfar_of_init(ofdev, &dev);
1005
1006         if (err)
1007                 return err;
1008
1009         priv = netdev_priv(dev);
1010         priv->ndev = dev;
1011         priv->ofdev = ofdev;
1012         priv->dev = &ofdev->dev;
1013         SET_NETDEV_DEV(dev, &ofdev->dev);
1014
1015         spin_lock_init(&priv->bflock);
1016         INIT_WORK(&priv->reset_task, gfar_reset_task);
1017
1018         platform_set_drvdata(ofdev, priv);
1019         regs = priv->gfargrp[0].regs;
1020
1021         gfar_detect_errata(priv);
1022
1023         /* Stop the DMA engine now, in case it was running before
1024          * (The firmware could have used it, and left it running).
1025          */
1026         gfar_halt(dev);
1027
1028         /* Reset MAC layer */
1029         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1030
1031         /* We need to delay at least 3 TX clocks */
1032         udelay(2);
1033
1034         tempval = 0;
1035         if (!priv->pause_aneg_en && priv->tx_pause_en)
1036                 tempval |= MACCFG1_TX_FLOW;
1037         if (!priv->pause_aneg_en && priv->rx_pause_en)
1038                 tempval |= MACCFG1_RX_FLOW;
1039         /* the soft reset bit is not self-resetting, so we need to
1040          * clear it before resuming normal operation
1041          */
1042         gfar_write(&regs->maccfg1, tempval);
1043
1044         /* Initialize MACCFG2. */
1045         tempval = MACCFG2_INIT_SETTINGS;
1046         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1047                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1048         gfar_write(&regs->maccfg2, tempval);
1049
1050         /* Initialize ECNTRL */
1051         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1052
1053         /* Set the dev->base_addr to the gfar reg region */
1054         dev->base_addr = (unsigned long) regs;
1055
1056         /* Fill in the dev structure */
1057         dev->watchdog_timeo = TX_TIMEOUT;
1058         dev->mtu = 1500;
1059         dev->netdev_ops = &gfar_netdev_ops;
1060         dev->ethtool_ops = &gfar_ethtool_ops;
1061
1062         /* Register for napi ...We are registering NAPI for each grp */
1063         if (priv->mode == SQ_SG_MODE)
1064                 netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq,
1065                                GFAR_DEV_WEIGHT);
1066         else
1067                 for (i = 0; i < priv->num_grps; i++)
1068                         netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1069                                        GFAR_DEV_WEIGHT);
1070
1071         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1072                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1073                                    NETIF_F_RXCSUM;
1074                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1075                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1076         }
1077
1078         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1079                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1080                                     NETIF_F_HW_VLAN_CTAG_RX;
1081                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1082         }
1083
1084         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1085                 priv->extended_hash = 1;
1086                 priv->hash_width = 9;
1087
1088                 priv->hash_regs[0] = &regs->igaddr0;
1089                 priv->hash_regs[1] = &regs->igaddr1;
1090                 priv->hash_regs[2] = &regs->igaddr2;
1091                 priv->hash_regs[3] = &regs->igaddr3;
1092                 priv->hash_regs[4] = &regs->igaddr4;
1093                 priv->hash_regs[5] = &regs->igaddr5;
1094                 priv->hash_regs[6] = &regs->igaddr6;
1095                 priv->hash_regs[7] = &regs->igaddr7;
1096                 priv->hash_regs[8] = &regs->gaddr0;
1097                 priv->hash_regs[9] = &regs->gaddr1;
1098                 priv->hash_regs[10] = &regs->gaddr2;
1099                 priv->hash_regs[11] = &regs->gaddr3;
1100                 priv->hash_regs[12] = &regs->gaddr4;
1101                 priv->hash_regs[13] = &regs->gaddr5;
1102                 priv->hash_regs[14] = &regs->gaddr6;
1103                 priv->hash_regs[15] = &regs->gaddr7;
1104
1105         } else {
1106                 priv->extended_hash = 0;
1107                 priv->hash_width = 8;
1108
1109                 priv->hash_regs[0] = &regs->gaddr0;
1110                 priv->hash_regs[1] = &regs->gaddr1;
1111                 priv->hash_regs[2] = &regs->gaddr2;
1112                 priv->hash_regs[3] = &regs->gaddr3;
1113                 priv->hash_regs[4] = &regs->gaddr4;
1114                 priv->hash_regs[5] = &regs->gaddr5;
1115                 priv->hash_regs[6] = &regs->gaddr6;
1116                 priv->hash_regs[7] = &regs->gaddr7;
1117         }
1118
1119         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1120                 priv->padding = DEFAULT_PADDING;
1121         else
1122                 priv->padding = 0;
1123
1124         if (dev->features & NETIF_F_IP_CSUM ||
1125             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1126                 dev->needed_headroom = GMAC_FCB_LEN;
1127
1128         /* Program the isrg regs only if number of grps > 1 */
1129         if (priv->num_grps > 1) {
1130                 baddr = &regs->isrg0;
1131                 for (i = 0; i < priv->num_grps; i++) {
1132                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1133                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1134                         gfar_write(baddr, isrg);
1135                         baddr++;
1136                         isrg = 0x0;
1137                 }
1138         }
1139
1140         /* Need to reverse the bit maps as  bit_map's MSB is q0
1141          * but, for_each_set_bit parses from right to left, which
1142          * basically reverses the queue numbers
1143          */
1144         for (i = 0; i< priv->num_grps; i++) {
1145                 priv->gfargrp[i].tx_bit_map =
1146                         reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1147                 priv->gfargrp[i].rx_bit_map =
1148                         reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1149         }
1150
1151         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1152          * also assign queues to groups
1153          */
1154         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1155                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1156
1157                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1158                                  priv->num_rx_queues) {
1159                         priv->gfargrp[grp_idx].num_rx_queues++;
1160                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1161                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1162                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1163                 }
1164                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1165
1166                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1167                                  priv->num_tx_queues) {
1168                         priv->gfargrp[grp_idx].num_tx_queues++;
1169                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1170                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1171                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1172                 }
1173                 priv->gfargrp[grp_idx].rstat = rstat;
1174                 priv->gfargrp[grp_idx].tstat = tstat;
1175                 rstat = tstat =0;
1176         }
1177
1178         gfar_write(&regs->rqueue, rqueue);
1179         gfar_write(&regs->tqueue, tqueue);
1180
1181         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1182
1183         /* Initializing some of the rx/tx queue level parameters */
1184         for (i = 0; i < priv->num_tx_queues; i++) {
1185                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1186                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1187                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1188                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1189         }
1190
1191         for (i = 0; i < priv->num_rx_queues; i++) {
1192                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1193                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1194                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1195         }
1196
1197         /* always enable rx filer */
1198         priv->rx_filer_enable = 1;
1199         /* Enable most messages by default */
1200         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1201         /* use pritority h/w tx queue scheduling for single queue devices */
1202         if (priv->num_tx_queues == 1)
1203                 priv->prio_sched_en = 1;
1204
1205         /* Carrier starts down, phylib will bring it up */
1206         netif_carrier_off(dev);
1207
1208         err = register_netdev(dev);
1209
1210         if (err) {
1211                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1212                 goto register_fail;
1213         }
1214
1215         device_init_wakeup(&dev->dev,
1216                            priv->device_flags &
1217                            FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1218
1219         /* fill out IRQ number and name fields */
1220         for (i = 0; i < priv->num_grps; i++) {
1221                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1222                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1223                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1224                                 dev->name, "_g", '0' + i, "_tx");
1225                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1226                                 dev->name, "_g", '0' + i, "_rx");
1227                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1228                                 dev->name, "_g", '0' + i, "_er");
1229                 } else
1230                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1231         }
1232
1233         /* Initialize the filer table */
1234         gfar_init_filer_table(priv);
1235
1236         /* Create all the sysfs files */
1237         gfar_init_sysfs(dev);
1238
1239         /* Print out the device info */
1240         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1241
1242         /* Even more device info helps when determining which kernel
1243          * provided which set of benchmarks.
1244          */
1245         netdev_info(dev, "Running with NAPI enabled\n");
1246         for (i = 0; i < priv->num_rx_queues; i++)
1247                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1248                             i, priv->rx_queue[i]->rx_ring_size);
1249         for (i = 0; i < priv->num_tx_queues; i++)
1250                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1251                             i, priv->tx_queue[i]->tx_ring_size);
1252
1253         return 0;
1254
1255 register_fail:
1256         unmap_group_regs(priv);
1257         free_tx_pointers(priv);
1258         free_rx_pointers(priv);
1259         if (priv->phy_node)
1260                 of_node_put(priv->phy_node);
1261         if (priv->tbi_node)
1262                 of_node_put(priv->tbi_node);
1263         free_gfar_dev(priv);
1264         return err;
1265 }
1266
1267 static int gfar_remove(struct platform_device *ofdev)
1268 {
1269         struct gfar_private *priv = platform_get_drvdata(ofdev);
1270
1271         if (priv->phy_node)
1272                 of_node_put(priv->phy_node);
1273         if (priv->tbi_node)
1274                 of_node_put(priv->tbi_node);
1275
1276         unregister_netdev(priv->ndev);
1277         unmap_group_regs(priv);
1278         free_gfar_dev(priv);
1279
1280         return 0;
1281 }
1282
1283 #ifdef CONFIG_PM
1284
1285 static int gfar_suspend(struct device *dev)
1286 {
1287         struct gfar_private *priv = dev_get_drvdata(dev);
1288         struct net_device *ndev = priv->ndev;
1289         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1290         unsigned long flags;
1291         u32 tempval;
1292
1293         int magic_packet = priv->wol_en &&
1294                            (priv->device_flags &
1295                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1296
1297         netif_device_detach(ndev);
1298
1299         if (netif_running(ndev)) {
1300
1301                 local_irq_save(flags);
1302                 lock_tx_qs(priv);
1303                 lock_rx_qs(priv);
1304
1305                 gfar_halt_nodisable(ndev);
1306
1307                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1308                 tempval = gfar_read(&regs->maccfg1);
1309
1310                 tempval &= ~MACCFG1_TX_EN;
1311
1312                 if (!magic_packet)
1313                         tempval &= ~MACCFG1_RX_EN;
1314
1315                 gfar_write(&regs->maccfg1, tempval);
1316
1317                 unlock_rx_qs(priv);
1318                 unlock_tx_qs(priv);
1319                 local_irq_restore(flags);
1320
1321                 disable_napi(priv);
1322
1323                 if (magic_packet) {
1324                         /* Enable interrupt on Magic Packet */
1325                         gfar_write(&regs->imask, IMASK_MAG);
1326
1327                         /* Enable Magic Packet mode */
1328                         tempval = gfar_read(&regs->maccfg2);
1329                         tempval |= MACCFG2_MPEN;
1330                         gfar_write(&regs->maccfg2, tempval);
1331                 } else {
1332                         phy_stop(priv->phydev);
1333                 }
1334         }
1335
1336         return 0;
1337 }
1338
1339 static int gfar_resume(struct device *dev)
1340 {
1341         struct gfar_private *priv = dev_get_drvdata(dev);
1342         struct net_device *ndev = priv->ndev;
1343         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1344         unsigned long flags;
1345         u32 tempval;
1346         int magic_packet = priv->wol_en &&
1347                            (priv->device_flags &
1348                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1349
1350         if (!netif_running(ndev)) {
1351                 netif_device_attach(ndev);
1352                 return 0;
1353         }
1354
1355         if (!magic_packet && priv->phydev)
1356                 phy_start(priv->phydev);
1357
1358         /* Disable Magic Packet mode, in case something
1359          * else woke us up.
1360          */
1361         local_irq_save(flags);
1362         lock_tx_qs(priv);
1363         lock_rx_qs(priv);
1364
1365         tempval = gfar_read(&regs->maccfg2);
1366         tempval &= ~MACCFG2_MPEN;
1367         gfar_write(&regs->maccfg2, tempval);
1368
1369         gfar_start(ndev);
1370
1371         unlock_rx_qs(priv);
1372         unlock_tx_qs(priv);
1373         local_irq_restore(flags);
1374
1375         netif_device_attach(ndev);
1376
1377         enable_napi(priv);
1378
1379         return 0;
1380 }
1381
1382 static int gfar_restore(struct device *dev)
1383 {
1384         struct gfar_private *priv = dev_get_drvdata(dev);
1385         struct net_device *ndev = priv->ndev;
1386
1387         if (!netif_running(ndev)) {
1388                 netif_device_attach(ndev);
1389
1390                 return 0;
1391         }
1392
1393         if (gfar_init_bds(ndev)) {
1394                 free_skb_resources(priv);
1395                 return -ENOMEM;
1396         }
1397
1398         init_registers(ndev);
1399         gfar_set_mac_address(ndev);
1400         gfar_init_mac(ndev);
1401         gfar_start(ndev);
1402
1403         priv->oldlink = 0;
1404         priv->oldspeed = 0;
1405         priv->oldduplex = -1;
1406
1407         if (priv->phydev)
1408                 phy_start(priv->phydev);
1409
1410         netif_device_attach(ndev);
1411         enable_napi(priv);
1412
1413         return 0;
1414 }
1415
1416 static struct dev_pm_ops gfar_pm_ops = {
1417         .suspend = gfar_suspend,
1418         .resume = gfar_resume,
1419         .freeze = gfar_suspend,
1420         .thaw = gfar_resume,
1421         .restore = gfar_restore,
1422 };
1423
1424 #define GFAR_PM_OPS (&gfar_pm_ops)
1425
1426 #else
1427
1428 #define GFAR_PM_OPS NULL
1429
1430 #endif
1431
1432 /* Reads the controller's registers to determine what interface
1433  * connects it to the PHY.
1434  */
1435 static phy_interface_t gfar_get_interface(struct net_device *dev)
1436 {
1437         struct gfar_private *priv = netdev_priv(dev);
1438         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1439         u32 ecntrl;
1440
1441         ecntrl = gfar_read(&regs->ecntrl);
1442
1443         if (ecntrl & ECNTRL_SGMII_MODE)
1444                 return PHY_INTERFACE_MODE_SGMII;
1445
1446         if (ecntrl & ECNTRL_TBI_MODE) {
1447                 if (ecntrl & ECNTRL_REDUCED_MODE)
1448                         return PHY_INTERFACE_MODE_RTBI;
1449                 else
1450                         return PHY_INTERFACE_MODE_TBI;
1451         }
1452
1453         if (ecntrl & ECNTRL_REDUCED_MODE) {
1454                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1455                         return PHY_INTERFACE_MODE_RMII;
1456                 }
1457                 else {
1458                         phy_interface_t interface = priv->interface;
1459
1460                         /* This isn't autodetected right now, so it must
1461                          * be set by the device tree or platform code.
1462                          */
1463                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1464                                 return PHY_INTERFACE_MODE_RGMII_ID;
1465
1466                         return PHY_INTERFACE_MODE_RGMII;
1467                 }
1468         }
1469
1470         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1471                 return PHY_INTERFACE_MODE_GMII;
1472
1473         return PHY_INTERFACE_MODE_MII;
1474 }
1475
1476
1477 /* Initializes driver's PHY state, and attaches to the PHY.
1478  * Returns 0 on success.
1479  */
1480 static int init_phy(struct net_device *dev)
1481 {
1482         struct gfar_private *priv = netdev_priv(dev);
1483         uint gigabit_support =
1484                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1485                 GFAR_SUPPORTED_GBIT : 0;
1486         phy_interface_t interface;
1487
1488         priv->oldlink = 0;
1489         priv->oldspeed = 0;
1490         priv->oldduplex = -1;
1491
1492         interface = gfar_get_interface(dev);
1493
1494         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1495                                       interface);
1496         if (!priv->phydev)
1497                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1498                                                          interface);
1499         if (!priv->phydev) {
1500                 dev_err(&dev->dev, "could not attach to PHY\n");
1501                 return -ENODEV;
1502         }
1503
1504         if (interface == PHY_INTERFACE_MODE_SGMII)
1505                 gfar_configure_serdes(dev);
1506
1507         /* Remove any features not supported by the controller */
1508         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1509         priv->phydev->advertising = priv->phydev->supported;
1510
1511         return 0;
1512 }
1513
1514 /* Initialize TBI PHY interface for communicating with the
1515  * SERDES lynx PHY on the chip.  We communicate with this PHY
1516  * through the MDIO bus on each controller, treating it as a
1517  * "normal" PHY at the address found in the TBIPA register.  We assume
1518  * that the TBIPA register is valid.  Either the MDIO bus code will set
1519  * it to a value that doesn't conflict with other PHYs on the bus, or the
1520  * value doesn't matter, as there are no other PHYs on the bus.
1521  */
1522 static void gfar_configure_serdes(struct net_device *dev)
1523 {
1524         struct gfar_private *priv = netdev_priv(dev);
1525         struct phy_device *tbiphy;
1526
1527         if (!priv->tbi_node) {
1528                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1529                                     "device tree specify a tbi-handle\n");
1530                 return;
1531         }
1532
1533         tbiphy = of_phy_find_device(priv->tbi_node);
1534         if (!tbiphy) {
1535                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1536                 return;
1537         }
1538
1539         /* If the link is already up, we must already be ok, and don't need to
1540          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1541          * everything for us?  Resetting it takes the link down and requires
1542          * several seconds for it to come back.
1543          */
1544         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1545                 return;
1546
1547         /* Single clk mode, mii mode off(for serdes communication) */
1548         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1549
1550         phy_write(tbiphy, MII_ADVERTISE,
1551                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1552                   ADVERTISE_1000XPSE_ASYM);
1553
1554         phy_write(tbiphy, MII_BMCR,
1555                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1556                   BMCR_SPEED1000);
1557 }
1558
1559 static void init_registers(struct net_device *dev)
1560 {
1561         struct gfar_private *priv = netdev_priv(dev);
1562         struct gfar __iomem *regs = NULL;
1563         int i;
1564
1565         for (i = 0; i < priv->num_grps; i++) {
1566                 regs = priv->gfargrp[i].regs;
1567                 /* Clear IEVENT */
1568                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1569
1570                 /* Initialize IMASK */
1571                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1572         }
1573
1574         regs = priv->gfargrp[0].regs;
1575         /* Init hash registers to zero */
1576         gfar_write(&regs->igaddr0, 0);
1577         gfar_write(&regs->igaddr1, 0);
1578         gfar_write(&regs->igaddr2, 0);
1579         gfar_write(&regs->igaddr3, 0);
1580         gfar_write(&regs->igaddr4, 0);
1581         gfar_write(&regs->igaddr5, 0);
1582         gfar_write(&regs->igaddr6, 0);
1583         gfar_write(&regs->igaddr7, 0);
1584
1585         gfar_write(&regs->gaddr0, 0);
1586         gfar_write(&regs->gaddr1, 0);
1587         gfar_write(&regs->gaddr2, 0);
1588         gfar_write(&regs->gaddr3, 0);
1589         gfar_write(&regs->gaddr4, 0);
1590         gfar_write(&regs->gaddr5, 0);
1591         gfar_write(&regs->gaddr6, 0);
1592         gfar_write(&regs->gaddr7, 0);
1593
1594         /* Zero out the rmon mib registers if it has them */
1595         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1596                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1597
1598                 /* Mask off the CAM interrupts */
1599                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1600                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1601         }
1602
1603         /* Initialize the max receive buffer length */
1604         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1605
1606         /* Initialize the Minimum Frame Length Register */
1607         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1608 }
1609
1610 static int __gfar_is_rx_idle(struct gfar_private *priv)
1611 {
1612         u32 res;
1613
1614         /* Normaly TSEC should not hang on GRS commands, so we should
1615          * actually wait for IEVENT_GRSC flag.
1616          */
1617         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1618                 return 0;
1619
1620         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1621          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1622          * and the Rx can be safely reset.
1623          */
1624         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1625         res &= 0x7f807f80;
1626         if ((res & 0xffff) == (res >> 16))
1627                 return 1;
1628
1629         return 0;
1630 }
1631
1632 /* Halt the receive and transmit queues */
1633 static void gfar_halt_nodisable(struct net_device *dev)
1634 {
1635         struct gfar_private *priv = netdev_priv(dev);
1636         struct gfar __iomem *regs = NULL;
1637         u32 tempval;
1638         int i;
1639
1640         for (i = 0; i < priv->num_grps; i++) {
1641                 regs = priv->gfargrp[i].regs;
1642                 /* Mask all interrupts */
1643                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1644
1645                 /* Clear all interrupts */
1646                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1647         }
1648
1649         regs = priv->gfargrp[0].regs;
1650         /* Stop the DMA, and wait for it to stop */
1651         tempval = gfar_read(&regs->dmactrl);
1652         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1653             (DMACTRL_GRS | DMACTRL_GTS)) {
1654                 int ret;
1655
1656                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1657                 gfar_write(&regs->dmactrl, tempval);
1658
1659                 do {
1660                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1661                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1662                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1663                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1664                                 ret = __gfar_is_rx_idle(priv);
1665                 } while (!ret);
1666         }
1667 }
1668
1669 /* Halt the receive and transmit queues */
1670 void gfar_halt(struct net_device *dev)
1671 {
1672         struct gfar_private *priv = netdev_priv(dev);
1673         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1674         u32 tempval;
1675
1676         gfar_halt_nodisable(dev);
1677
1678         /* Disable Rx and Tx */
1679         tempval = gfar_read(&regs->maccfg1);
1680         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1681         gfar_write(&regs->maccfg1, tempval);
1682 }
1683
1684 static void free_grp_irqs(struct gfar_priv_grp *grp)
1685 {
1686         free_irq(gfar_irq(grp, TX)->irq, grp);
1687         free_irq(gfar_irq(grp, RX)->irq, grp);
1688         free_irq(gfar_irq(grp, ER)->irq, grp);
1689 }
1690
1691 void stop_gfar(struct net_device *dev)
1692 {
1693         struct gfar_private *priv = netdev_priv(dev);
1694         unsigned long flags;
1695         int i;
1696
1697         phy_stop(priv->phydev);
1698
1699
1700         /* Lock it down */
1701         local_irq_save(flags);
1702         lock_tx_qs(priv);
1703         lock_rx_qs(priv);
1704
1705         gfar_halt(dev);
1706
1707         unlock_rx_qs(priv);
1708         unlock_tx_qs(priv);
1709         local_irq_restore(flags);
1710
1711         /* Free the IRQs */
1712         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1713                 for (i = 0; i < priv->num_grps; i++)
1714                         free_grp_irqs(&priv->gfargrp[i]);
1715         } else {
1716                 for (i = 0; i < priv->num_grps; i++)
1717                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1718                                  &priv->gfargrp[i]);
1719         }
1720
1721         free_skb_resources(priv);
1722 }
1723
1724 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1725 {
1726         struct txbd8 *txbdp;
1727         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1728         int i, j;
1729
1730         txbdp = tx_queue->tx_bd_base;
1731
1732         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1733                 if (!tx_queue->tx_skbuff[i])
1734                         continue;
1735
1736                 dma_unmap_single(priv->dev, txbdp->bufPtr,
1737                                  txbdp->length, DMA_TO_DEVICE);
1738                 txbdp->lstatus = 0;
1739                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1740                      j++) {
1741                         txbdp++;
1742                         dma_unmap_page(priv->dev, txbdp->bufPtr,
1743                                        txbdp->length, DMA_TO_DEVICE);
1744                 }
1745                 txbdp++;
1746                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1747                 tx_queue->tx_skbuff[i] = NULL;
1748         }
1749         kfree(tx_queue->tx_skbuff);
1750         tx_queue->tx_skbuff = NULL;
1751 }
1752
1753 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1754 {
1755         struct rxbd8 *rxbdp;
1756         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1757         int i;
1758
1759         rxbdp = rx_queue->rx_bd_base;
1760
1761         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1762                 if (rx_queue->rx_skbuff[i]) {
1763                         dma_unmap_single(priv->dev, rxbdp->bufPtr,
1764                                          priv->rx_buffer_size,
1765                                          DMA_FROM_DEVICE);
1766                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1767                         rx_queue->rx_skbuff[i] = NULL;
1768                 }
1769                 rxbdp->lstatus = 0;
1770                 rxbdp->bufPtr = 0;
1771                 rxbdp++;
1772         }
1773         kfree(rx_queue->rx_skbuff);
1774         rx_queue->rx_skbuff = NULL;
1775 }
1776
1777 /* If there are any tx skbs or rx skbs still around, free them.
1778  * Then free tx_skbuff and rx_skbuff
1779  */
1780 static void free_skb_resources(struct gfar_private *priv)
1781 {
1782         struct gfar_priv_tx_q *tx_queue = NULL;
1783         struct gfar_priv_rx_q *rx_queue = NULL;
1784         int i;
1785
1786         /* Go through all the buffer descriptors and free their data buffers */
1787         for (i = 0; i < priv->num_tx_queues; i++) {
1788                 struct netdev_queue *txq;
1789
1790                 tx_queue = priv->tx_queue[i];
1791                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1792                 if (tx_queue->tx_skbuff)
1793                         free_skb_tx_queue(tx_queue);
1794                 netdev_tx_reset_queue(txq);
1795         }
1796
1797         for (i = 0; i < priv->num_rx_queues; i++) {
1798                 rx_queue = priv->rx_queue[i];
1799                 if (rx_queue->rx_skbuff)
1800                         free_skb_rx_queue(rx_queue);
1801         }
1802
1803         dma_free_coherent(priv->dev,
1804                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1805                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1806                           priv->tx_queue[0]->tx_bd_base,
1807                           priv->tx_queue[0]->tx_bd_dma_base);
1808 }
1809
1810 void gfar_start(struct net_device *dev)
1811 {
1812         struct gfar_private *priv = netdev_priv(dev);
1813         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1814         u32 tempval;
1815         int i = 0;
1816
1817         /* Enable Rx and Tx in MACCFG1 */
1818         tempval = gfar_read(&regs->maccfg1);
1819         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1820         gfar_write(&regs->maccfg1, tempval);
1821
1822         /* Initialize DMACTRL to have WWR and WOP */
1823         tempval = gfar_read(&regs->dmactrl);
1824         tempval |= DMACTRL_INIT_SETTINGS;
1825         gfar_write(&regs->dmactrl, tempval);
1826
1827         /* Make sure we aren't stopped */
1828         tempval = gfar_read(&regs->dmactrl);
1829         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1830         gfar_write(&regs->dmactrl, tempval);
1831
1832         for (i = 0; i < priv->num_grps; i++) {
1833                 regs = priv->gfargrp[i].regs;
1834                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1835                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1836                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1837                 /* Unmask the interrupts we look for */
1838                 gfar_write(&regs->imask, IMASK_DEFAULT);
1839         }
1840
1841         dev->trans_start = jiffies; /* prevent tx timeout */
1842 }
1843
1844 static void gfar_configure_coalescing(struct gfar_private *priv,
1845                                unsigned long tx_mask, unsigned long rx_mask)
1846 {
1847         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1848         u32 __iomem *baddr;
1849
1850         if (priv->mode == MQ_MG_MODE) {
1851                 int i = 0;
1852
1853                 baddr = &regs->txic0;
1854                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1855                         gfar_write(baddr + i, 0);
1856                         if (likely(priv->tx_queue[i]->txcoalescing))
1857                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1858                 }
1859
1860                 baddr = &regs->rxic0;
1861                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1862                         gfar_write(baddr + i, 0);
1863                         if (likely(priv->rx_queue[i]->rxcoalescing))
1864                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1865                 }
1866         } else {
1867                 /* Backward compatible case -- even if we enable
1868                  * multiple queues, there's only single reg to program
1869                  */
1870                 gfar_write(&regs->txic, 0);
1871                 if (likely(priv->tx_queue[0]->txcoalescing))
1872                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1873
1874                 gfar_write(&regs->rxic, 0);
1875                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1876                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1877         }
1878 }
1879
1880 void gfar_configure_coalescing_all(struct gfar_private *priv)
1881 {
1882         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1883 }
1884
1885 static int register_grp_irqs(struct gfar_priv_grp *grp)
1886 {
1887         struct gfar_private *priv = grp->priv;
1888         struct net_device *dev = priv->ndev;
1889         int err;
1890
1891         /* If the device has multiple interrupts, register for
1892          * them.  Otherwise, only register for the one
1893          */
1894         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1895                 /* Install our interrupt handlers for Error,
1896                  * Transmit, and Receive
1897                  */
1898                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1899                                   gfar_irq(grp, ER)->name, grp);
1900                 if (err < 0) {
1901                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1902                                   gfar_irq(grp, ER)->irq);
1903
1904                         goto err_irq_fail;
1905                 }
1906                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1907                                   gfar_irq(grp, TX)->name, grp);
1908                 if (err < 0) {
1909                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1910                                   gfar_irq(grp, TX)->irq);
1911                         goto tx_irq_fail;
1912                 }
1913                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1914                                   gfar_irq(grp, RX)->name, grp);
1915                 if (err < 0) {
1916                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1917                                   gfar_irq(grp, RX)->irq);
1918                         goto rx_irq_fail;
1919                 }
1920         } else {
1921                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1922                                   gfar_irq(grp, TX)->name, grp);
1923                 if (err < 0) {
1924                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1925                                   gfar_irq(grp, TX)->irq);
1926                         goto err_irq_fail;
1927                 }
1928         }
1929
1930         return 0;
1931
1932 rx_irq_fail:
1933         free_irq(gfar_irq(grp, TX)->irq, grp);
1934 tx_irq_fail:
1935         free_irq(gfar_irq(grp, ER)->irq, grp);
1936 err_irq_fail:
1937         return err;
1938
1939 }
1940
1941 /* Bring the controller up and running */
1942 int startup_gfar(struct net_device *ndev)
1943 {
1944         struct gfar_private *priv = netdev_priv(ndev);
1945         struct gfar __iomem *regs = NULL;
1946         int err, i, j;
1947
1948         for (i = 0; i < priv->num_grps; i++) {
1949                 regs= priv->gfargrp[i].regs;
1950                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1951         }
1952
1953         regs= priv->gfargrp[0].regs;
1954         err = gfar_alloc_skb_resources(ndev);
1955         if (err)
1956                 return err;
1957
1958         gfar_init_mac(ndev);
1959
1960         for (i = 0; i < priv->num_grps; i++) {
1961                 err = register_grp_irqs(&priv->gfargrp[i]);
1962                 if (err) {
1963                         for (j = 0; j < i; j++)
1964                                 free_grp_irqs(&priv->gfargrp[j]);
1965                         goto irq_fail;
1966                 }
1967         }
1968
1969         /* Start the controller */
1970         gfar_start(ndev);
1971
1972         phy_start(priv->phydev);
1973
1974         gfar_configure_coalescing_all(priv);
1975
1976         return 0;
1977
1978 irq_fail:
1979         free_skb_resources(priv);
1980         return err;
1981 }
1982
1983 /* Called when something needs to use the ethernet device
1984  * Returns 0 for success.
1985  */
1986 static int gfar_enet_open(struct net_device *dev)
1987 {
1988         struct gfar_private *priv = netdev_priv(dev);
1989         int err;
1990
1991         enable_napi(priv);
1992
1993         /* Initialize a bunch of registers */
1994         init_registers(dev);
1995
1996         gfar_set_mac_address(dev);
1997
1998         err = init_phy(dev);
1999
2000         if (err) {
2001                 disable_napi(priv);
2002                 return err;
2003         }
2004
2005         err = startup_gfar(dev);
2006         if (err) {
2007                 disable_napi(priv);
2008                 return err;
2009         }
2010
2011         netif_tx_start_all_queues(dev);
2012
2013         device_set_wakeup_enable(&dev->dev, priv->wol_en);
2014
2015         return err;
2016 }
2017
2018 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2019 {
2020         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2021
2022         memset(fcb, 0, GMAC_FCB_LEN);
2023
2024         return fcb;
2025 }
2026
2027 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2028                                     int fcb_length)
2029 {
2030         /* If we're here, it's a IP packet with a TCP or UDP
2031          * payload.  We set it to checksum, using a pseudo-header
2032          * we provide
2033          */
2034         u8 flags = TXFCB_DEFAULT;
2035
2036         /* Tell the controller what the protocol is
2037          * And provide the already calculated phcs
2038          */
2039         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2040                 flags |= TXFCB_UDP;
2041                 fcb->phcs = udp_hdr(skb)->check;
2042         } else
2043                 fcb->phcs = tcp_hdr(skb)->check;
2044
2045         /* l3os is the distance between the start of the
2046          * frame (skb->data) and the start of the IP hdr.
2047          * l4os is the distance between the start of the
2048          * l3 hdr and the l4 hdr
2049          */
2050         fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2051         fcb->l4os = skb_network_header_len(skb);
2052
2053         fcb->flags = flags;
2054 }
2055
2056 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2057 {
2058         fcb->flags |= TXFCB_VLN;
2059         fcb->vlctl = vlan_tx_tag_get(skb);
2060 }
2061
2062 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2063                                       struct txbd8 *base, int ring_size)
2064 {
2065         struct txbd8 *new_bd = bdp + stride;
2066
2067         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2068 }
2069
2070 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2071                                       int ring_size)
2072 {
2073         return skip_txbd(bdp, 1, base, ring_size);
2074 }
2075
2076 /* eTSEC12: csum generation not supported for some fcb offsets */
2077 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2078                                        unsigned long fcb_addr)
2079 {
2080         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2081                (fcb_addr % 0x20) > 0x18);
2082 }
2083
2084 /* eTSEC76: csum generation for frames larger than 2500 may
2085  * cause excess delays before start of transmission
2086  */
2087 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2088                                        unsigned int len)
2089 {
2090         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2091                (len > 2500));
2092 }
2093
2094 /* This is called by the kernel when a frame is ready for transmission.
2095  * It is pointed to by the dev->hard_start_xmit function pointer
2096  */
2097 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2098 {
2099         struct gfar_private *priv = netdev_priv(dev);
2100         struct gfar_priv_tx_q *tx_queue = NULL;
2101         struct netdev_queue *txq;
2102         struct gfar __iomem *regs = NULL;
2103         struct txfcb *fcb = NULL;
2104         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2105         u32 lstatus;
2106         int i, rq = 0;
2107         int do_tstamp, do_csum, do_vlan;
2108         u32 bufaddr;
2109         unsigned long flags;
2110         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2111
2112         rq = skb->queue_mapping;
2113         tx_queue = priv->tx_queue[rq];
2114         txq = netdev_get_tx_queue(dev, rq);
2115         base = tx_queue->tx_bd_base;
2116         regs = tx_queue->grp->regs;
2117
2118         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2119         do_vlan = vlan_tx_tag_present(skb);
2120         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2121                     priv->hwts_tx_en;
2122
2123         if (do_csum || do_vlan)
2124                 fcb_len = GMAC_FCB_LEN;
2125
2126         /* check if time stamp should be generated */
2127         if (unlikely(do_tstamp))
2128                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2129
2130         /* make space for additional header when fcb is needed */
2131         if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2132                 struct sk_buff *skb_new;
2133
2134                 skb_new = skb_realloc_headroom(skb, fcb_len);
2135                 if (!skb_new) {
2136                         dev->stats.tx_errors++;
2137                         kfree_skb(skb);
2138                         return NETDEV_TX_OK;
2139                 }
2140
2141                 if (skb->sk)
2142                         skb_set_owner_w(skb_new, skb->sk);
2143                 consume_skb(skb);
2144                 skb = skb_new;
2145         }
2146
2147         /* total number of fragments in the SKB */
2148         nr_frags = skb_shinfo(skb)->nr_frags;
2149
2150         /* calculate the required number of TxBDs for this skb */
2151         if (unlikely(do_tstamp))
2152                 nr_txbds = nr_frags + 2;
2153         else
2154                 nr_txbds = nr_frags + 1;
2155
2156         /* check if there is space to queue this packet */
2157         if (nr_txbds > tx_queue->num_txbdfree) {
2158                 /* no space, stop the queue */
2159                 netif_tx_stop_queue(txq);
2160                 dev->stats.tx_fifo_errors++;
2161                 return NETDEV_TX_BUSY;
2162         }
2163
2164         /* Update transmit stats */
2165         bytes_sent = skb->len;
2166         tx_queue->stats.tx_bytes += bytes_sent;
2167         /* keep Tx bytes on wire for BQL accounting */
2168         GFAR_CB(skb)->bytes_sent = bytes_sent;
2169         tx_queue->stats.tx_packets++;
2170
2171         txbdp = txbdp_start = tx_queue->cur_tx;
2172         lstatus = txbdp->lstatus;
2173
2174         /* Time stamp insertion requires one additional TxBD */
2175         if (unlikely(do_tstamp))
2176                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2177                                                  tx_queue->tx_ring_size);
2178
2179         if (nr_frags == 0) {
2180                 if (unlikely(do_tstamp))
2181                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2182                                                           TXBD_INTERRUPT);
2183                 else
2184                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2185         } else {
2186                 /* Place the fragment addresses and lengths into the TxBDs */
2187                 for (i = 0; i < nr_frags; i++) {
2188                         unsigned int frag_len;
2189                         /* Point at the next BD, wrapping as needed */
2190                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2191
2192                         frag_len = skb_shinfo(skb)->frags[i].size;
2193
2194                         lstatus = txbdp->lstatus | frag_len |
2195                                   BD_LFLAG(TXBD_READY);
2196
2197                         /* Handle the last BD specially */
2198                         if (i == nr_frags - 1)
2199                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2200
2201                         bufaddr = skb_frag_dma_map(priv->dev,
2202                                                    &skb_shinfo(skb)->frags[i],
2203                                                    0,
2204                                                    frag_len,
2205                                                    DMA_TO_DEVICE);
2206
2207                         /* set the TxBD length and buffer pointer */
2208                         txbdp->bufPtr = bufaddr;
2209                         txbdp->lstatus = lstatus;
2210                 }
2211
2212                 lstatus = txbdp_start->lstatus;
2213         }
2214
2215         /* Add TxPAL between FCB and frame if required */
2216         if (unlikely(do_tstamp)) {
2217                 skb_push(skb, GMAC_TXPAL_LEN);
2218                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2219         }
2220
2221         /* Add TxFCB if required */
2222         if (fcb_len) {
2223                 fcb = gfar_add_fcb(skb);
2224                 lstatus |= BD_LFLAG(TXBD_TOE);
2225         }
2226
2227         /* Set up checksumming */
2228         if (do_csum) {
2229                 gfar_tx_checksum(skb, fcb, fcb_len);
2230
2231                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2232                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
2233                         __skb_pull(skb, GMAC_FCB_LEN);
2234                         skb_checksum_help(skb);
2235                         if (do_vlan || do_tstamp) {
2236                                 /* put back a new fcb for vlan/tstamp TOE */
2237                                 fcb = gfar_add_fcb(skb);
2238                         } else {
2239                                 /* Tx TOE not used */
2240                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2241                                 fcb = NULL;
2242                         }
2243                 }
2244         }
2245
2246         if (do_vlan)
2247                 gfar_tx_vlan(skb, fcb);
2248
2249         /* Setup tx hardware time stamping if requested */
2250         if (unlikely(do_tstamp)) {
2251                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2252                 fcb->ptp = 1;
2253         }
2254
2255         txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
2256                                              skb_headlen(skb), DMA_TO_DEVICE);
2257
2258         /* If time stamping is requested one additional TxBD must be set up. The
2259          * first TxBD points to the FCB and must have a data length of
2260          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2261          * the full frame length.
2262          */
2263         if (unlikely(do_tstamp)) {
2264                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len;
2265                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2266                                          (skb_headlen(skb) - fcb_len);
2267                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2268         } else {
2269                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2270         }
2271
2272         netdev_tx_sent_queue(txq, bytes_sent);
2273
2274         /* We can work in parallel with gfar_clean_tx_ring(), except
2275          * when modifying num_txbdfree. Note that we didn't grab the lock
2276          * when we were reading the num_txbdfree and checking for available
2277          * space, that's because outside of this function it can only grow,
2278          * and once we've got needed space, it cannot suddenly disappear.
2279          *
2280          * The lock also protects us from gfar_error(), which can modify
2281          * regs->tstat and thus retrigger the transfers, which is why we
2282          * also must grab the lock before setting ready bit for the first
2283          * to be transmitted BD.
2284          */
2285         spin_lock_irqsave(&tx_queue->txlock, flags);
2286
2287         /* The powerpc-specific eieio() is used, as wmb() has too strong
2288          * semantics (it requires synchronization between cacheable and
2289          * uncacheable mappings, which eieio doesn't provide and which we
2290          * don't need), thus requiring a more expensive sync instruction.  At
2291          * some point, the set of architecture-independent barrier functions
2292          * should be expanded to include weaker barriers.
2293          */
2294         eieio();
2295
2296         txbdp_start->lstatus = lstatus;
2297
2298         eieio(); /* force lstatus write before tx_skbuff */
2299
2300         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2301
2302         /* Update the current skb pointer to the next entry we will use
2303          * (wrapping if necessary)
2304          */
2305         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2306                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2307
2308         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2309
2310         /* reduce TxBD free count */
2311         tx_queue->num_txbdfree -= (nr_txbds);
2312
2313         /* If the next BD still needs to be cleaned up, then the bds
2314          * are full.  We need to tell the kernel to stop sending us stuff.
2315          */
2316         if (!tx_queue->num_txbdfree) {
2317                 netif_tx_stop_queue(txq);
2318
2319                 dev->stats.tx_fifo_errors++;
2320         }
2321
2322         /* Tell the DMA to go go go */
2323         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2324
2325         /* Unlock priv */
2326         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2327
2328         return NETDEV_TX_OK;
2329 }
2330
2331 /* Stops the kernel queue, and halts the controller */
2332 static int gfar_close(struct net_device *dev)
2333 {
2334         struct gfar_private *priv = netdev_priv(dev);
2335
2336         disable_napi(priv);
2337
2338         cancel_work_sync(&priv->reset_task);
2339         stop_gfar(dev);
2340
2341         /* Disconnect from the PHY */
2342         phy_disconnect(priv->phydev);
2343         priv->phydev = NULL;
2344
2345         netif_tx_stop_all_queues(dev);
2346
2347         return 0;
2348 }
2349
2350 /* Changes the mac address if the controller is not running. */
2351 static int gfar_set_mac_address(struct net_device *dev)
2352 {
2353         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2354
2355         return 0;
2356 }
2357
2358 /* Check if rx parser should be activated */
2359 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2360 {
2361         struct gfar __iomem *regs;
2362         u32 tempval;
2363
2364         regs = priv->gfargrp[0].regs;
2365
2366         tempval = gfar_read(&regs->rctrl);
2367         /* If parse is no longer required, then disable parser */
2368         if (tempval & RCTRL_REQ_PARSER) {
2369                 tempval |= RCTRL_PRSDEP_INIT;
2370                 priv->uses_rxfcb = 1;
2371         } else {
2372                 tempval &= ~RCTRL_PRSDEP_INIT;
2373                 priv->uses_rxfcb = 0;
2374         }
2375         gfar_write(&regs->rctrl, tempval);
2376 }
2377
2378 /* Enables and disables VLAN insertion/extraction */
2379 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2380 {
2381         struct gfar_private *priv = netdev_priv(dev);
2382         struct gfar __iomem *regs = NULL;
2383         unsigned long flags;
2384         u32 tempval;
2385
2386         regs = priv->gfargrp[0].regs;
2387         local_irq_save(flags);
2388         lock_rx_qs(priv);
2389
2390         if (features & NETIF_F_HW_VLAN_CTAG_TX) {
2391                 /* Enable VLAN tag insertion */
2392                 tempval = gfar_read(&regs->tctrl);
2393                 tempval |= TCTRL_VLINS;
2394                 gfar_write(&regs->tctrl, tempval);
2395         } else {
2396                 /* Disable VLAN tag insertion */
2397                 tempval = gfar_read(&regs->tctrl);
2398                 tempval &= ~TCTRL_VLINS;
2399                 gfar_write(&regs->tctrl, tempval);
2400         }
2401
2402         if (features & NETIF_F_HW_VLAN_CTAG_RX) {
2403                 /* Enable VLAN tag extraction */
2404                 tempval = gfar_read(&regs->rctrl);
2405                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2406                 gfar_write(&regs->rctrl, tempval);
2407                 priv->uses_rxfcb = 1;
2408         } else {
2409                 /* Disable VLAN tag extraction */
2410                 tempval = gfar_read(&regs->rctrl);
2411                 tempval &= ~RCTRL_VLEX;
2412                 gfar_write(&regs->rctrl, tempval);
2413
2414                 gfar_check_rx_parser_mode(priv);
2415         }
2416
2417         gfar_change_mtu(dev, dev->mtu);
2418
2419         unlock_rx_qs(priv);
2420         local_irq_restore(flags);
2421 }
2422
2423 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2424 {
2425         int tempsize, tempval;
2426         struct gfar_private *priv = netdev_priv(dev);
2427         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2428         int oldsize = priv->rx_buffer_size;
2429         int frame_size = new_mtu + ETH_HLEN;
2430
2431         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2432                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2433                 return -EINVAL;
2434         }
2435
2436         if (priv->uses_rxfcb)
2437                 frame_size += GMAC_FCB_LEN;
2438
2439         frame_size += priv->padding;
2440
2441         tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2442                    INCREMENTAL_BUFFER_SIZE;
2443
2444         /* Only stop and start the controller if it isn't already
2445          * stopped, and we changed something
2446          */
2447         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2448                 stop_gfar(dev);
2449
2450         priv->rx_buffer_size = tempsize;
2451
2452         dev->mtu = new_mtu;
2453
2454         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2455         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2456
2457         /* If the mtu is larger than the max size for standard
2458          * ethernet frames (ie, a jumbo frame), then set maccfg2
2459          * to allow huge frames, and to check the length
2460          */
2461         tempval = gfar_read(&regs->maccfg2);
2462
2463         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2464             gfar_has_errata(priv, GFAR_ERRATA_74))
2465                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2466         else
2467                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2468
2469         gfar_write(&regs->maccfg2, tempval);
2470
2471         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2472                 startup_gfar(dev);
2473
2474         return 0;
2475 }
2476
2477 /* gfar_reset_task gets scheduled when a packet has not been
2478  * transmitted after a set amount of time.
2479  * For now, assume that clearing out all the structures, and
2480  * starting over will fix the problem.
2481  */
2482 static void gfar_reset_task(struct work_struct *work)
2483 {
2484         struct gfar_private *priv = container_of(work, struct gfar_private,
2485                                                  reset_task);
2486         struct net_device *dev = priv->ndev;
2487
2488         if (dev->flags & IFF_UP) {
2489                 netif_tx_stop_all_queues(dev);
2490                 stop_gfar(dev);
2491                 startup_gfar(dev);
2492                 netif_tx_start_all_queues(dev);
2493         }
2494
2495         netif_tx_schedule_all(dev);
2496 }
2497
2498 static void gfar_timeout(struct net_device *dev)
2499 {
2500         struct gfar_private *priv = netdev_priv(dev);
2501
2502         dev->stats.tx_errors++;
2503         schedule_work(&priv->reset_task);
2504 }
2505
2506 static void gfar_align_skb(struct sk_buff *skb)
2507 {
2508         /* We need the data buffer to be aligned properly.  We will reserve
2509          * as many bytes as needed to align the data properly
2510          */
2511         skb_reserve(skb, RXBUF_ALIGNMENT -
2512                     (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2513 }
2514
2515 /* Interrupt Handler for Transmit complete */
2516 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2517 {
2518         struct net_device *dev = tx_queue->dev;
2519         struct netdev_queue *txq;
2520         struct gfar_private *priv = netdev_priv(dev);
2521         struct txbd8 *bdp, *next = NULL;
2522         struct txbd8 *lbdp = NULL;
2523         struct txbd8 *base = tx_queue->tx_bd_base;
2524         struct sk_buff *skb;
2525         int skb_dirtytx;
2526         int tx_ring_size = tx_queue->tx_ring_size;
2527         int frags = 0, nr_txbds = 0;
2528         int i;
2529         int howmany = 0;
2530         int tqi = tx_queue->qindex;
2531         unsigned int bytes_sent = 0;
2532         u32 lstatus;
2533         size_t buflen;
2534
2535         txq = netdev_get_tx_queue(dev, tqi);
2536         bdp = tx_queue->dirty_tx;
2537         skb_dirtytx = tx_queue->skb_dirtytx;
2538
2539         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2540                 unsigned long flags;
2541
2542                 frags = skb_shinfo(skb)->nr_frags;
2543
2544                 /* When time stamping, one additional TxBD must be freed.
2545                  * Also, we need to dma_unmap_single() the TxPAL.
2546                  */
2547                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2548                         nr_txbds = frags + 2;
2549                 else
2550                         nr_txbds = frags + 1;
2551
2552                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2553
2554                 lstatus = lbdp->lstatus;
2555
2556                 /* Only clean completed frames */
2557                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2558                     (lstatus & BD_LENGTH_MASK))
2559                         break;
2560
2561                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2562                         next = next_txbd(bdp, base, tx_ring_size);
2563                         buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2564                 } else
2565                         buflen = bdp->length;
2566
2567                 dma_unmap_single(priv->dev, bdp->bufPtr,
2568                                  buflen, DMA_TO_DEVICE);
2569
2570                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2571                         struct skb_shared_hwtstamps shhwtstamps;
2572                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2573
2574                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2575                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2576                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2577                         skb_tstamp_tx(skb, &shhwtstamps);
2578                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2579                         bdp = next;
2580                 }
2581
2582                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2583                 bdp = next_txbd(bdp, base, tx_ring_size);
2584
2585                 for (i = 0; i < frags; i++) {
2586                         dma_unmap_page(priv->dev, bdp->bufPtr,
2587                                        bdp->length, DMA_TO_DEVICE);
2588                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2589                         bdp = next_txbd(bdp, base, tx_ring_size);
2590                 }
2591
2592                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2593
2594                 dev_kfree_skb_any(skb);
2595
2596                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2597
2598                 skb_dirtytx = (skb_dirtytx + 1) &
2599                               TX_RING_MOD_MASK(tx_ring_size);
2600
2601                 howmany++;
2602                 spin_lock_irqsave(&tx_queue->txlock, flags);
2603                 tx_queue->num_txbdfree += nr_txbds;
2604                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2605         }
2606
2607         /* If we freed a buffer, we can restart transmission, if necessary */
2608         if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2609                 netif_wake_subqueue(dev, tqi);
2610
2611         /* Update dirty indicators */
2612         tx_queue->skb_dirtytx = skb_dirtytx;
2613         tx_queue->dirty_tx = bdp;
2614
2615         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2616 }
2617
2618 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2619 {
2620         unsigned long flags;
2621
2622         spin_lock_irqsave(&gfargrp->grplock, flags);
2623         if (napi_schedule_prep(&gfargrp->napi)) {
2624                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2625                 __napi_schedule(&gfargrp->napi);
2626         } else {
2627                 /* Clear IEVENT, so interrupts aren't called again
2628                  * because of the packets that have already arrived.
2629                  */
2630                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2631         }
2632         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2633
2634 }
2635
2636 /* Interrupt Handler for Transmit complete */
2637 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2638 {
2639         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2640         return IRQ_HANDLED;
2641 }
2642
2643 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2644                            struct sk_buff *skb)
2645 {
2646         struct net_device *dev = rx_queue->dev;
2647         struct gfar_private *priv = netdev_priv(dev);
2648         dma_addr_t buf;
2649
2650         buf = dma_map_single(priv->dev, skb->data,
2651                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2652         gfar_init_rxbdp(rx_queue, bdp, buf);
2653 }
2654
2655 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2656 {
2657         struct gfar_private *priv = netdev_priv(dev);
2658         struct sk_buff *skb;
2659
2660         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2661         if (!skb)
2662                 return NULL;
2663
2664         gfar_align_skb(skb);
2665
2666         return skb;
2667 }
2668
2669 struct sk_buff *gfar_new_skb(struct net_device *dev)
2670 {
2671         return gfar_alloc_skb(dev);
2672 }
2673
2674 static inline void count_errors(unsigned short status, struct net_device *dev)
2675 {
2676         struct gfar_private *priv = netdev_priv(dev);
2677         struct net_device_stats *stats = &dev->stats;
2678         struct gfar_extra_stats *estats = &priv->extra_stats;
2679
2680         /* If the packet was truncated, none of the other errors matter */
2681         if (status & RXBD_TRUNCATED) {
2682                 stats->rx_length_errors++;
2683
2684                 atomic64_inc(&estats->rx_trunc);
2685
2686                 return;
2687         }
2688         /* Count the errors, if there were any */
2689         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2690                 stats->rx_length_errors++;
2691
2692                 if (status & RXBD_LARGE)
2693                         atomic64_inc(&estats->rx_large);
2694                 else
2695                         atomic64_inc(&estats->rx_short);
2696         }
2697         if (status & RXBD_NONOCTET) {
2698                 stats->rx_frame_errors++;
2699                 atomic64_inc(&estats->rx_nonoctet);
2700         }
2701         if (status & RXBD_CRCERR) {
2702                 atomic64_inc(&estats->rx_crcerr);
2703                 stats->rx_crc_errors++;
2704         }
2705         if (status & RXBD_OVERRUN) {
2706                 atomic64_inc(&estats->rx_overrun);
2707                 stats->rx_crc_errors++;
2708         }
2709 }
2710
2711 irqreturn_t gfar_receive(int irq, void *grp_id)
2712 {
2713         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2714         return IRQ_HANDLED;
2715 }
2716
2717 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2718 {
2719         /* If valid headers were found, and valid sums
2720          * were verified, then we tell the kernel that no
2721          * checksumming is necessary.  Otherwise, it is [FIXME]
2722          */
2723         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2724                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2725         else
2726                 skb_checksum_none_assert(skb);
2727 }
2728
2729
2730 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2731 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2732                                int amount_pull, struct napi_struct *napi)
2733 {
2734         struct gfar_private *priv = netdev_priv(dev);
2735         struct rxfcb *fcb = NULL;
2736
2737         /* fcb is at the beginning if exists */
2738         fcb = (struct rxfcb *)skb->data;
2739
2740         /* Remove the FCB from the skb
2741          * Remove the padded bytes, if there are any
2742          */
2743         if (amount_pull) {
2744                 skb_record_rx_queue(skb, fcb->rq);
2745                 skb_pull(skb, amount_pull);
2746         }
2747
2748         /* Get receive timestamp from the skb */
2749         if (priv->hwts_rx_en) {
2750                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2751                 u64 *ns = (u64 *) skb->data;
2752
2753                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2754                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2755         }
2756
2757         if (priv->padding)
2758                 skb_pull(skb, priv->padding);
2759
2760         if (dev->features & NETIF_F_RXCSUM)
2761                 gfar_rx_checksum(skb, fcb);
2762
2763         /* Tell the skb what kind of packet this is */
2764         skb->protocol = eth_type_trans(skb, dev);
2765
2766         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2767          * Even if vlan rx accel is disabled, on some chips
2768          * RXFCB_VLN is pseudo randomly set.
2769          */
2770         if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2771             fcb->flags & RXFCB_VLN)
2772                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl);
2773
2774         /* Send the packet up the stack */
2775         napi_gro_receive(napi, skb);
2776
2777 }
2778
2779 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2780  * until the budget/quota has been reached. Returns the number
2781  * of frames handled
2782  */
2783 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2784 {
2785         struct net_device *dev = rx_queue->dev;
2786         struct rxbd8 *bdp, *base;
2787         struct sk_buff *skb;
2788         int pkt_len;
2789         int amount_pull;
2790         int howmany = 0;
2791         struct gfar_private *priv = netdev_priv(dev);
2792
2793         /* Get the first full descriptor */
2794         bdp = rx_queue->cur_rx;
2795         base = rx_queue->rx_bd_base;
2796
2797         amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2798
2799         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2800                 struct sk_buff *newskb;
2801
2802                 rmb();
2803
2804                 /* Add another skb for the future */
2805                 newskb = gfar_new_skb(dev);
2806
2807                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2808
2809                 dma_unmap_single(priv->dev, bdp->bufPtr,
2810                                  priv->rx_buffer_size, DMA_FROM_DEVICE);
2811
2812                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2813                              bdp->length > priv->rx_buffer_size))
2814                         bdp->status = RXBD_LARGE;
2815
2816                 /* We drop the frame if we failed to allocate a new buffer */
2817                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2818                              bdp->status & RXBD_ERR)) {
2819                         count_errors(bdp->status, dev);
2820
2821                         if (unlikely(!newskb))
2822                                 newskb = skb;
2823                         else if (skb)
2824                                 dev_kfree_skb(skb);
2825                 } else {
2826                         /* Increment the number of packets */
2827                         rx_queue->stats.rx_packets++;
2828                         howmany++;
2829
2830                         if (likely(skb)) {
2831                                 pkt_len = bdp->length - ETH_FCS_LEN;
2832                                 /* Remove the FCS from the packet length */
2833                                 skb_put(skb, pkt_len);
2834                                 rx_queue->stats.rx_bytes += pkt_len;
2835                                 skb_record_rx_queue(skb, rx_queue->qindex);
2836                                 gfar_process_frame(dev, skb, amount_pull,
2837                                                    &rx_queue->grp->napi);
2838
2839                         } else {
2840                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2841                                 rx_queue->stats.rx_dropped++;
2842                                 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2843                         }
2844
2845                 }
2846
2847                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2848
2849                 /* Setup the new bdp */
2850                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2851
2852                 /* Update to the next pointer */
2853                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2854
2855                 /* update to point at the next skb */
2856                 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2857                                       RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2858         }
2859
2860         /* Update the current rxbd pointer to be the next one */
2861         rx_queue->cur_rx = bdp;
2862
2863         return howmany;
2864 }
2865
2866 static int gfar_poll_sq(struct napi_struct *napi, int budget)
2867 {
2868         struct gfar_priv_grp *gfargrp =
2869                 container_of(napi, struct gfar_priv_grp, napi);
2870         struct gfar __iomem *regs = gfargrp->regs;
2871         struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0];
2872         struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0];
2873         int work_done = 0;
2874
2875         /* Clear IEVENT, so interrupts aren't called again
2876          * because of the packets that have already arrived
2877          */
2878         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2879
2880         /* run Tx cleanup to completion */
2881         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2882                 gfar_clean_tx_ring(tx_queue);
2883
2884         work_done = gfar_clean_rx_ring(rx_queue, budget);
2885
2886         if (work_done < budget) {
2887                 napi_complete(napi);
2888                 /* Clear the halt bit in RSTAT */
2889                 gfar_write(&regs->rstat, gfargrp->rstat);
2890
2891                 gfar_write(&regs->imask, IMASK_DEFAULT);
2892
2893                 /* If we are coalescing interrupts, update the timer
2894                  * Otherwise, clear it
2895                  */
2896                 gfar_write(&regs->txic, 0);
2897                 if (likely(tx_queue->txcoalescing))
2898                         gfar_write(&regs->txic, tx_queue->txic);
2899
2900                 gfar_write(&regs->rxic, 0);
2901                 if (unlikely(rx_queue->rxcoalescing))
2902                         gfar_write(&regs->rxic, rx_queue->rxic);
2903         }
2904
2905         return work_done;
2906 }
2907
2908 static int gfar_poll(struct napi_struct *napi, int budget)
2909 {
2910         struct gfar_priv_grp *gfargrp =
2911                 container_of(napi, struct gfar_priv_grp, napi);
2912         struct gfar_private *priv = gfargrp->priv;
2913         struct gfar __iomem *regs = gfargrp->regs;
2914         struct gfar_priv_tx_q *tx_queue = NULL;
2915         struct gfar_priv_rx_q *rx_queue = NULL;
2916         int work_done = 0, work_done_per_q = 0;
2917         int i, budget_per_q = 0;
2918         int has_tx_work;
2919         unsigned long rstat_rxf;
2920         int num_act_queues;
2921
2922         /* Clear IEVENT, so interrupts aren't called again
2923          * because of the packets that have already arrived
2924          */
2925         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2926
2927         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
2928
2929         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2930         if (num_act_queues)
2931                 budget_per_q = budget/num_act_queues;
2932
2933         while (1) {
2934                 has_tx_work = 0;
2935                 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2936                         tx_queue = priv->tx_queue[i];
2937                         /* run Tx cleanup to completion */
2938                         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2939                                 gfar_clean_tx_ring(tx_queue);
2940                                 has_tx_work = 1;
2941                         }
2942                 }
2943
2944                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2945                         /* skip queue if not active */
2946                         if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2947                                 continue;
2948
2949                         rx_queue = priv->rx_queue[i];
2950                         work_done_per_q =
2951                                 gfar_clean_rx_ring(rx_queue, budget_per_q);
2952                         work_done += work_done_per_q;
2953
2954                         /* finished processing this queue */
2955                         if (work_done_per_q < budget_per_q) {
2956                                 /* clear active queue hw indication */
2957                                 gfar_write(&regs->rstat,
2958                                            RSTAT_CLEAR_RXF0 >> i);
2959                                 rstat_rxf &= ~(RSTAT_CLEAR_RXF0 >> i);
2960                                 num_act_queues--;
2961
2962                                 if (!num_act_queues)
2963                                         break;
2964                                 /* recompute budget per Rx queue */
2965                                 budget_per_q =
2966                                         (budget - work_done) / num_act_queues;
2967                         }
2968                 }
2969
2970                 if (work_done >= budget)
2971                         break;
2972
2973                 if (!num_act_queues && !has_tx_work) {
2974
2975                         napi_complete(napi);
2976
2977                         /* Clear the halt bit in RSTAT */
2978                         gfar_write(&regs->rstat, gfargrp->rstat);
2979
2980                         gfar_write(&regs->imask, IMASK_DEFAULT);
2981
2982                         /* If we are coalescing interrupts, update the timer
2983                          * Otherwise, clear it
2984                          */
2985                         gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2986                                                   gfargrp->tx_bit_map);
2987                         break;
2988                 }
2989         }
2990
2991         return work_done;
2992 }
2993
2994 #ifdef CONFIG_NET_POLL_CONTROLLER
2995 /* Polling 'interrupt' - used by things like netconsole to send skbs
2996  * without having to re-enable interrupts. It's not called while
2997  * the interrupt routine is executing.
2998  */
2999 static void gfar_netpoll(struct net_device *dev)
3000 {
3001         struct gfar_private *priv = netdev_priv(dev);
3002         int i;
3003
3004         /* If the device has multiple interrupts, run tx/rx */
3005         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3006                 for (i = 0; i < priv->num_grps; i++) {
3007                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3008
3009                         disable_irq(gfar_irq(grp, TX)->irq);
3010                         disable_irq(gfar_irq(grp, RX)->irq);
3011                         disable_irq(gfar_irq(grp, ER)->irq);
3012                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3013                         enable_irq(gfar_irq(grp, ER)->irq);
3014                         enable_irq(gfar_irq(grp, RX)->irq);
3015                         enable_irq(gfar_irq(grp, TX)->irq);
3016                 }
3017         } else {
3018                 for (i = 0; i < priv->num_grps; i++) {
3019                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3020
3021                         disable_irq(gfar_irq(grp, TX)->irq);
3022                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3023                         enable_irq(gfar_irq(grp, TX)->irq);
3024                 }
3025         }
3026 }
3027 #endif
3028
3029 /* The interrupt handler for devices with one interrupt */
3030 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3031 {
3032         struct gfar_priv_grp *gfargrp = grp_id;
3033
3034         /* Save ievent for future reference */
3035         u32 events = gfar_read(&gfargrp->regs->ievent);
3036
3037         /* Check for reception */
3038         if (events & IEVENT_RX_MASK)
3039                 gfar_receive(irq, grp_id);
3040
3041         /* Check for transmit completion */
3042         if (events & IEVENT_TX_MASK)
3043                 gfar_transmit(irq, grp_id);
3044
3045         /* Check for errors */
3046         if (events & IEVENT_ERR_MASK)
3047                 gfar_error(irq, grp_id);
3048
3049         return IRQ_HANDLED;
3050 }
3051
3052 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3053 {
3054         struct phy_device *phydev = priv->phydev;
3055         u32 val = 0;
3056
3057         if (!phydev->duplex)
3058                 return val;
3059
3060         if (!priv->pause_aneg_en) {
3061                 if (priv->tx_pause_en)
3062                         val |= MACCFG1_TX_FLOW;
3063                 if (priv->rx_pause_en)
3064                         val |= MACCFG1_RX_FLOW;
3065         } else {
3066                 u16 lcl_adv, rmt_adv;
3067                 u8 flowctrl;
3068                 /* get link partner capabilities */
3069                 rmt_adv = 0;
3070                 if (phydev->pause)
3071                         rmt_adv = LPA_PAUSE_CAP;
3072                 if (phydev->asym_pause)
3073                         rmt_adv |= LPA_PAUSE_ASYM;
3074
3075                 lcl_adv = mii_advertise_flowctrl(phydev->advertising);
3076
3077                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3078                 if (flowctrl & FLOW_CTRL_TX)
3079                         val |= MACCFG1_TX_FLOW;
3080                 if (flowctrl & FLOW_CTRL_RX)
3081                         val |= MACCFG1_RX_FLOW;
3082         }
3083
3084         return val;
3085 }
3086
3087 /* Called every time the controller might need to be made
3088  * aware of new link state.  The PHY code conveys this
3089  * information through variables in the phydev structure, and this
3090  * function converts those variables into the appropriate
3091  * register values, and can bring down the device if needed.
3092  */
3093 static void adjust_link(struct net_device *dev)
3094 {
3095         struct gfar_private *priv = netdev_priv(dev);
3096         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3097         unsigned long flags;
3098         struct phy_device *phydev = priv->phydev;
3099         int new_state = 0;
3100
3101         local_irq_save(flags);
3102         lock_tx_qs(priv);
3103
3104         if (phydev->link) {
3105                 u32 tempval1 = gfar_read(&regs->maccfg1);
3106                 u32 tempval = gfar_read(&regs->maccfg2);
3107                 u32 ecntrl = gfar_read(&regs->ecntrl);
3108
3109                 /* Now we make sure that we can be in full duplex mode.
3110                  * If not, we operate in half-duplex mode.
3111                  */
3112                 if (phydev->duplex != priv->oldduplex) {
3113                         new_state = 1;
3114                         if (!(phydev->duplex))
3115                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3116                         else
3117                                 tempval |= MACCFG2_FULL_DUPLEX;
3118
3119                         priv->oldduplex = phydev->duplex;
3120                 }
3121
3122                 if (phydev->speed != priv->oldspeed) {
3123                         new_state = 1;
3124                         switch (phydev->speed) {
3125                         case 1000:
3126                                 tempval =
3127                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3128
3129                                 ecntrl &= ~(ECNTRL_R100);
3130                                 break;
3131                         case 100:
3132                         case 10:
3133                                 tempval =
3134                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3135
3136                                 /* Reduced mode distinguishes
3137                                  * between 10 and 100
3138                                  */
3139                                 if (phydev->speed == SPEED_100)
3140                                         ecntrl |= ECNTRL_R100;
3141                                 else
3142                                         ecntrl &= ~(ECNTRL_R100);
3143                                 break;
3144                         default:
3145                                 netif_warn(priv, link, dev,
3146                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3147                                            phydev->speed);
3148                                 break;
3149                         }
3150
3151                         priv->oldspeed = phydev->speed;
3152                 }
3153
3154                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3155                 tempval1 |= gfar_get_flowctrl_cfg(priv);
3156
3157                 gfar_write(&regs->maccfg1, tempval1);
3158                 gfar_write(&regs->maccfg2, tempval);
3159                 gfar_write(&regs->ecntrl, ecntrl);
3160
3161                 if (!priv->oldlink) {
3162                         new_state = 1;
3163                         priv->oldlink = 1;
3164                 }
3165         } else if (priv->oldlink) {
3166                 new_state = 1;
3167                 priv->oldlink = 0;
3168                 priv->oldspeed = 0;
3169                 priv->oldduplex = -1;
3170         }
3171
3172         if (new_state && netif_msg_link(priv))
3173                 phy_print_status(phydev);
3174         unlock_tx_qs(priv);
3175         local_irq_restore(flags);
3176 }
3177
3178 /* Update the hash table based on the current list of multicast
3179  * addresses we subscribe to.  Also, change the promiscuity of
3180  * the device based on the flags (this function is called
3181  * whenever dev->flags is changed
3182  */
3183 static void gfar_set_multi(struct net_device *dev)
3184 {
3185         struct netdev_hw_addr *ha;
3186         struct gfar_private *priv = netdev_priv(dev);
3187         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3188         u32 tempval;
3189
3190         if (dev->flags & IFF_PROMISC) {
3191                 /* Set RCTRL to PROM */
3192                 tempval = gfar_read(&regs->rctrl);
3193                 tempval |= RCTRL_PROM;
3194                 gfar_write(&regs->rctrl, tempval);
3195         } else {
3196                 /* Set RCTRL to not PROM */
3197                 tempval = gfar_read(&regs->rctrl);
3198                 tempval &= ~(RCTRL_PROM);
3199                 gfar_write(&regs->rctrl, tempval);
3200         }
3201
3202         if (dev->flags & IFF_ALLMULTI) {
3203                 /* Set the hash to rx all multicast frames */
3204                 gfar_write(&regs->igaddr0, 0xffffffff);
3205                 gfar_write(&regs->igaddr1, 0xffffffff);
3206                 gfar_write(&regs->igaddr2, 0xffffffff);
3207                 gfar_write(&regs->igaddr3, 0xffffffff);
3208                 gfar_write(&regs->igaddr4, 0xffffffff);
3209                 gfar_write(&regs->igaddr5, 0xffffffff);
3210                 gfar_write(&regs->igaddr6, 0xffffffff);
3211                 gfar_write(&regs->igaddr7, 0xffffffff);
3212                 gfar_write(&regs->gaddr0, 0xffffffff);
3213                 gfar_write(&regs->gaddr1, 0xffffffff);
3214                 gfar_write(&regs->gaddr2, 0xffffffff);
3215                 gfar_write(&regs->gaddr3, 0xffffffff);
3216                 gfar_write(&regs->gaddr4, 0xffffffff);
3217                 gfar_write(&regs->gaddr5, 0xffffffff);
3218                 gfar_write(&regs->gaddr6, 0xffffffff);
3219                 gfar_write(&regs->gaddr7, 0xffffffff);
3220         } else {
3221                 int em_num;
3222                 int idx;
3223
3224                 /* zero out the hash */
3225                 gfar_write(&regs->igaddr0, 0x0);
3226                 gfar_write(&regs->igaddr1, 0x0);
3227                 gfar_write(&regs->igaddr2, 0x0);
3228                 gfar_write(&regs->igaddr3, 0x0);
3229                 gfar_write(&regs->igaddr4, 0x0);
3230                 gfar_write(&regs->igaddr5, 0x0);
3231                 gfar_write(&regs->igaddr6, 0x0);
3232                 gfar_write(&regs->igaddr7, 0x0);
3233                 gfar_write(&regs->gaddr0, 0x0);
3234                 gfar_write(&regs->gaddr1, 0x0);
3235                 gfar_write(&regs->gaddr2, 0x0);
3236                 gfar_write(&regs->gaddr3, 0x0);
3237                 gfar_write(&regs->gaddr4, 0x0);
3238                 gfar_write(&regs->gaddr5, 0x0);
3239                 gfar_write(&regs->gaddr6, 0x0);
3240                 gfar_write(&regs->gaddr7, 0x0);
3241
3242                 /* If we have extended hash tables, we need to
3243                  * clear the exact match registers to prepare for
3244                  * setting them
3245                  */
3246                 if (priv->extended_hash) {
3247                         em_num = GFAR_EM_NUM + 1;
3248                         gfar_clear_exact_match(dev);
3249                         idx = 1;
3250                 } else {
3251                         idx = 0;
3252                         em_num = 0;
3253                 }
3254
3255                 if (netdev_mc_empty(dev))
3256                         return;
3257
3258                 /* Parse the list, and set the appropriate bits */
3259                 netdev_for_each_mc_addr(ha, dev) {
3260                         if (idx < em_num) {
3261                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3262                                 idx++;
3263                         } else
3264                                 gfar_set_hash_for_addr(dev, ha->addr);
3265                 }
3266         }
3267 }
3268
3269
3270 /* Clears each of the exact match registers to zero, so they
3271  * don't interfere with normal reception
3272  */
3273 static void gfar_clear_exact_match(struct net_device *dev)
3274 {
3275         int idx;
3276         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3277
3278         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3279                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3280 }
3281
3282 /* Set the appropriate hash bit for the given addr */
3283 /* The algorithm works like so:
3284  * 1) Take the Destination Address (ie the multicast address), and
3285  * do a CRC on it (little endian), and reverse the bits of the
3286  * result.
3287  * 2) Use the 8 most significant bits as a hash into a 256-entry
3288  * table.  The table is controlled through 8 32-bit registers:
3289  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3290  * gaddr7.  This means that the 3 most significant bits in the
3291  * hash index which gaddr register to use, and the 5 other bits
3292  * indicate which bit (assuming an IBM numbering scheme, which
3293  * for PowerPC (tm) is usually the case) in the register holds
3294  * the entry.
3295  */
3296 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3297 {
3298         u32 tempval;
3299         struct gfar_private *priv = netdev_priv(dev);
3300         u32 result = ether_crc(ETH_ALEN, addr);
3301         int width = priv->hash_width;
3302         u8 whichbit = (result >> (32 - width)) & 0x1f;
3303         u8 whichreg = result >> (32 - width + 5);
3304         u32 value = (1 << (31-whichbit));
3305
3306         tempval = gfar_read(priv->hash_regs[whichreg]);
3307         tempval |= value;
3308         gfar_write(priv->hash_regs[whichreg], tempval);
3309 }
3310
3311
3312 /* There are multiple MAC Address register pairs on some controllers
3313  * This function sets the numth pair to a given address
3314  */
3315 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3316                                   const u8 *addr)
3317 {
3318         struct gfar_private *priv = netdev_priv(dev);
3319         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3320         int idx;
3321         char tmpbuf[ETH_ALEN];
3322         u32 tempval;
3323         u32 __iomem *macptr = &regs->macstnaddr1;
3324
3325         macptr += num*2;
3326
3327         /* Now copy it into the mac registers backwards, cuz
3328          * little endian is silly
3329          */
3330         for (idx = 0; idx < ETH_ALEN; idx++)
3331                 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3332
3333         gfar_write(macptr, *((u32 *) (tmpbuf)));
3334
3335         tempval = *((u32 *) (tmpbuf + 4));
3336
3337         gfar_write(macptr+1, tempval);
3338 }
3339
3340 /* GFAR error interrupt handler */
3341 static irqreturn_t gfar_error(int irq, void *grp_id)
3342 {
3343         struct gfar_priv_grp *gfargrp = grp_id;
3344         struct gfar __iomem *regs = gfargrp->regs;
3345         struct gfar_private *priv= gfargrp->priv;
3346         struct net_device *dev = priv->ndev;
3347
3348         /* Save ievent for future reference */
3349         u32 events = gfar_read(&regs->ievent);
3350
3351         /* Clear IEVENT */
3352         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3353
3354         /* Magic Packet is not an error. */
3355         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3356             (events & IEVENT_MAG))
3357                 events &= ~IEVENT_MAG;
3358
3359         /* Hmm... */
3360         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3361                 netdev_dbg(dev,
3362                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3363                            events, gfar_read(&regs->imask));
3364
3365         /* Update the error counters */
3366         if (events & IEVENT_TXE) {
3367                 dev->stats.tx_errors++;
3368
3369                 if (events & IEVENT_LC)
3370                         dev->stats.tx_window_errors++;
3371                 if (events & IEVENT_CRL)
3372                         dev->stats.tx_aborted_errors++;
3373                 if (events & IEVENT_XFUN) {
3374                         unsigned long flags;
3375
3376                         netif_dbg(priv, tx_err, dev,
3377                                   "TX FIFO underrun, packet dropped\n");
3378                         dev->stats.tx_dropped++;
3379                         atomic64_inc(&priv->extra_stats.tx_underrun);
3380
3381                         local_irq_save(flags);
3382                         lock_tx_qs(priv);
3383
3384                         /* Reactivate the Tx Queues */
3385                         gfar_write(&regs->tstat, gfargrp->tstat);
3386
3387                         unlock_tx_qs(priv);
3388                         local_irq_restore(flags);
3389                 }
3390                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3391         }
3392         if (events & IEVENT_BSY) {
3393                 dev->stats.rx_errors++;
3394                 atomic64_inc(&priv->extra_stats.rx_bsy);
3395
3396                 gfar_receive(irq, grp_id);
3397
3398                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3399                           gfar_read(&regs->rstat));
3400         }
3401         if (events & IEVENT_BABR) {
3402                 dev->stats.rx_errors++;
3403                 atomic64_inc(&priv->extra_stats.rx_babr);
3404
3405                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3406         }
3407         if (events & IEVENT_EBERR) {
3408                 atomic64_inc(&priv->extra_stats.eberr);
3409                 netif_dbg(priv, rx_err, dev, "bus error\n");
3410         }
3411         if (events & IEVENT_RXC)
3412                 netif_dbg(priv, rx_status, dev, "control frame\n");
3413
3414         if (events & IEVENT_BABT) {
3415                 atomic64_inc(&priv->extra_stats.tx_babt);
3416                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3417         }
3418         return IRQ_HANDLED;
3419 }
3420
3421 static struct of_device_id gfar_match[] =
3422 {
3423         {
3424                 .type = "network",
3425                 .compatible = "gianfar",
3426         },
3427         {
3428                 .compatible = "fsl,etsec2",
3429         },
3430         {},
3431 };
3432 MODULE_DEVICE_TABLE(of, gfar_match);
3433
3434 /* Structure for a device driver */
3435 static struct platform_driver gfar_driver = {
3436         .driver = {
3437                 .name = "fsl-gianfar",
3438                 .owner = THIS_MODULE,
3439                 .pm = GFAR_PM_OPS,
3440                 .of_match_table = gfar_match,
3441         },
3442         .probe = gfar_probe,
3443         .remove = gfar_remove,
3444 };
3445
3446 module_platform_driver(gfar_driver);