1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/delay.h>
74 #include <linux/netdevice.h>
75 #include <linux/etherdevice.h>
76 #include <linux/skbuff.h>
77 #include <linux/if_vlan.h>
78 #include <linux/spinlock.h>
80 #include <linux/of_address.h>
81 #include <linux/of_irq.h>
82 #include <linux/of_mdio.h>
83 #include <linux/of_platform.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
88 #include <linux/net_tstamp.h>
93 #include <asm/mpc85xx.h>
96 #include <asm/uaccess.h>
97 #include <linux/module.h>
98 #include <linux/dma-mapping.h>
99 #include <linux/crc32.h>
100 #include <linux/mii.h>
101 #include <linux/phy.h>
102 #include <linux/phy_fixed.h>
103 #include <linux/of.h>
104 #include <linux/of_net.h>
105 #include <linux/of_address.h>
106 #include <linux/of_irq.h>
110 #define TX_TIMEOUT (1*HZ)
112 const char gfar_driver_version[] = "1.3";
114 static int gfar_enet_open(struct net_device *dev);
115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
116 static void gfar_reset_task(struct work_struct *work);
117 static void gfar_timeout(struct net_device *dev);
118 static int gfar_close(struct net_device *dev);
119 static struct sk_buff *gfar_new_skb(struct net_device *dev,
120 dma_addr_t *bufaddr);
121 static int gfar_set_mac_address(struct net_device *dev);
122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
123 static irqreturn_t gfar_error(int irq, void *dev_id);
124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
126 static void adjust_link(struct net_device *dev);
127 static noinline void gfar_update_link_state(struct gfar_private *priv);
128 static int init_phy(struct net_device *dev);
129 static int gfar_probe(struct platform_device *ofdev);
130 static int gfar_remove(struct platform_device *ofdev);
131 static void free_skb_resources(struct gfar_private *priv);
132 static void gfar_set_multi(struct net_device *dev);
133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
134 static void gfar_configure_serdes(struct net_device *dev);
135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
139 #ifdef CONFIG_NET_POLL_CONTROLLER
140 static void gfar_netpoll(struct net_device *dev);
142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
144 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
145 int amount_pull, struct napi_struct *napi);
146 static void gfar_halt_nodisable(struct gfar_private *priv);
147 static void gfar_clear_exact_match(struct net_device *dev);
148 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
150 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
152 MODULE_AUTHOR("Freescale Semiconductor, Inc");
153 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
154 MODULE_LICENSE("GPL");
156 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
163 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
164 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
165 lstatus |= BD_LFLAG(RXBD_WRAP);
169 bdp->lstatus = lstatus;
172 static int gfar_init_bds(struct net_device *ndev)
174 struct gfar_private *priv = netdev_priv(ndev);
175 struct gfar __iomem *regs = priv->gfargrp[0].regs;
176 struct gfar_priv_tx_q *tx_queue = NULL;
177 struct gfar_priv_rx_q *rx_queue = NULL;
184 for (i = 0; i < priv->num_tx_queues; i++) {
185 tx_queue = priv->tx_queue[i];
186 /* Initialize some variables in our dev structure */
187 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
188 tx_queue->dirty_tx = tx_queue->tx_bd_base;
189 tx_queue->cur_tx = tx_queue->tx_bd_base;
190 tx_queue->skb_curtx = 0;
191 tx_queue->skb_dirtytx = 0;
193 /* Initialize Transmit Descriptor Ring */
194 txbdp = tx_queue->tx_bd_base;
195 for (j = 0; j < tx_queue->tx_ring_size; j++) {
201 /* Set the last descriptor in the ring to indicate wrap */
203 txbdp->status |= TXBD_WRAP;
206 rfbptr = ®s->rfbptr0;
207 for (i = 0; i < priv->num_rx_queues; i++) {
208 rx_queue = priv->rx_queue[i];
209 rx_queue->cur_rx = rx_queue->rx_bd_base;
210 rx_queue->skb_currx = 0;
211 rxbdp = rx_queue->rx_bd_base;
213 for (j = 0; j < rx_queue->rx_ring_size; j++) {
214 struct sk_buff *skb = rx_queue->rx_skbuff[j];
217 bufaddr = rxbdp->bufPtr;
219 skb = gfar_new_skb(ndev, &bufaddr);
221 netdev_err(ndev, "Can't allocate RX buffers\n");
224 rx_queue->rx_skbuff[j] = skb;
227 gfar_init_rxbdp(rx_queue, rxbdp, bufaddr);
231 rx_queue->rfbptr = rfbptr;
238 static int gfar_alloc_skb_resources(struct net_device *ndev)
243 struct gfar_private *priv = netdev_priv(ndev);
244 struct device *dev = priv->dev;
245 struct gfar_priv_tx_q *tx_queue = NULL;
246 struct gfar_priv_rx_q *rx_queue = NULL;
248 priv->total_tx_ring_size = 0;
249 for (i = 0; i < priv->num_tx_queues; i++)
250 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
252 priv->total_rx_ring_size = 0;
253 for (i = 0; i < priv->num_rx_queues; i++)
254 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
256 /* Allocate memory for the buffer descriptors */
257 vaddr = dma_alloc_coherent(dev,
258 (priv->total_tx_ring_size *
259 sizeof(struct txbd8)) +
260 (priv->total_rx_ring_size *
261 sizeof(struct rxbd8)),
266 for (i = 0; i < priv->num_tx_queues; i++) {
267 tx_queue = priv->tx_queue[i];
268 tx_queue->tx_bd_base = vaddr;
269 tx_queue->tx_bd_dma_base = addr;
270 tx_queue->dev = ndev;
271 /* enet DMA only understands physical addresses */
272 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
273 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
276 /* Start the rx descriptor ring where the tx ring leaves off */
277 for (i = 0; i < priv->num_rx_queues; i++) {
278 rx_queue = priv->rx_queue[i];
279 rx_queue->rx_bd_base = vaddr;
280 rx_queue->rx_bd_dma_base = addr;
281 rx_queue->dev = ndev;
282 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
283 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
286 /* Setup the skbuff rings */
287 for (i = 0; i < priv->num_tx_queues; i++) {
288 tx_queue = priv->tx_queue[i];
289 tx_queue->tx_skbuff =
290 kmalloc_array(tx_queue->tx_ring_size,
291 sizeof(*tx_queue->tx_skbuff),
293 if (!tx_queue->tx_skbuff)
296 for (k = 0; k < tx_queue->tx_ring_size; k++)
297 tx_queue->tx_skbuff[k] = NULL;
300 for (i = 0; i < priv->num_rx_queues; i++) {
301 rx_queue = priv->rx_queue[i];
302 rx_queue->rx_skbuff =
303 kmalloc_array(rx_queue->rx_ring_size,
304 sizeof(*rx_queue->rx_skbuff),
306 if (!rx_queue->rx_skbuff)
309 for (j = 0; j < rx_queue->rx_ring_size; j++)
310 rx_queue->rx_skbuff[j] = NULL;
313 if (gfar_init_bds(ndev))
319 free_skb_resources(priv);
323 static void gfar_init_tx_rx_base(struct gfar_private *priv)
325 struct gfar __iomem *regs = priv->gfargrp[0].regs;
329 baddr = ®s->tbase0;
330 for (i = 0; i < priv->num_tx_queues; i++) {
331 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
335 baddr = ®s->rbase0;
336 for (i = 0; i < priv->num_rx_queues; i++) {
337 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
342 static void gfar_init_rqprm(struct gfar_private *priv)
344 struct gfar __iomem *regs = priv->gfargrp[0].regs;
348 baddr = ®s->rqprm0;
349 for (i = 0; i < priv->num_rx_queues; i++) {
350 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
351 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
356 static void gfar_rx_buff_size_config(struct gfar_private *priv)
358 int frame_size = priv->ndev->mtu + ETH_HLEN + ETH_FCS_LEN;
360 /* set this when rx hw offload (TOE) functions are being used */
361 priv->uses_rxfcb = 0;
363 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
364 priv->uses_rxfcb = 1;
366 if (priv->hwts_rx_en)
367 priv->uses_rxfcb = 1;
369 if (priv->uses_rxfcb)
370 frame_size += GMAC_FCB_LEN;
372 frame_size += priv->padding;
374 frame_size = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
375 INCREMENTAL_BUFFER_SIZE;
377 priv->rx_buffer_size = frame_size;
380 static void gfar_mac_rx_config(struct gfar_private *priv)
382 struct gfar __iomem *regs = priv->gfargrp[0].regs;
385 if (priv->rx_filer_enable) {
386 rctrl |= RCTRL_FILREN;
387 /* Program the RIR0 reg with the required distribution */
388 if (priv->poll_mode == GFAR_SQ_POLLING)
389 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0);
390 else /* GFAR_MQ_POLLING */
391 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0);
394 /* Restore PROMISC mode */
395 if (priv->ndev->flags & IFF_PROMISC)
398 if (priv->ndev->features & NETIF_F_RXCSUM)
399 rctrl |= RCTRL_CHECKSUMMING;
401 if (priv->extended_hash)
402 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
405 rctrl &= ~RCTRL_PAL_MASK;
406 rctrl |= RCTRL_PADDING(priv->padding);
409 /* Enable HW time stamping if requested from user space */
410 if (priv->hwts_rx_en)
411 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
413 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
414 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
416 /* Clear the LFC bit */
417 gfar_write(®s->rctrl, rctrl);
418 /* Init flow control threshold values */
419 gfar_init_rqprm(priv);
420 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL);
423 /* Init rctrl based on our settings */
424 gfar_write(®s->rctrl, rctrl);
427 static void gfar_mac_tx_config(struct gfar_private *priv)
429 struct gfar __iomem *regs = priv->gfargrp[0].regs;
432 if (priv->ndev->features & NETIF_F_IP_CSUM)
433 tctrl |= TCTRL_INIT_CSUM;
435 if (priv->prio_sched_en)
436 tctrl |= TCTRL_TXSCHED_PRIO;
438 tctrl |= TCTRL_TXSCHED_WRRS;
439 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
440 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
443 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
444 tctrl |= TCTRL_VLINS;
446 gfar_write(®s->tctrl, tctrl);
449 static void gfar_configure_coalescing(struct gfar_private *priv,
450 unsigned long tx_mask, unsigned long rx_mask)
452 struct gfar __iomem *regs = priv->gfargrp[0].regs;
455 if (priv->mode == MQ_MG_MODE) {
458 baddr = ®s->txic0;
459 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
460 gfar_write(baddr + i, 0);
461 if (likely(priv->tx_queue[i]->txcoalescing))
462 gfar_write(baddr + i, priv->tx_queue[i]->txic);
465 baddr = ®s->rxic0;
466 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
467 gfar_write(baddr + i, 0);
468 if (likely(priv->rx_queue[i]->rxcoalescing))
469 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
472 /* Backward compatible case -- even if we enable
473 * multiple queues, there's only single reg to program
475 gfar_write(®s->txic, 0);
476 if (likely(priv->tx_queue[0]->txcoalescing))
477 gfar_write(®s->txic, priv->tx_queue[0]->txic);
479 gfar_write(®s->rxic, 0);
480 if (unlikely(priv->rx_queue[0]->rxcoalescing))
481 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
485 void gfar_configure_coalescing_all(struct gfar_private *priv)
487 gfar_configure_coalescing(priv, 0xFF, 0xFF);
490 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
492 struct gfar_private *priv = netdev_priv(dev);
493 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
494 unsigned long tx_packets = 0, tx_bytes = 0;
497 for (i = 0; i < priv->num_rx_queues; i++) {
498 rx_packets += priv->rx_queue[i]->stats.rx_packets;
499 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
500 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
503 dev->stats.rx_packets = rx_packets;
504 dev->stats.rx_bytes = rx_bytes;
505 dev->stats.rx_dropped = rx_dropped;
507 for (i = 0; i < priv->num_tx_queues; i++) {
508 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
509 tx_packets += priv->tx_queue[i]->stats.tx_packets;
512 dev->stats.tx_bytes = tx_bytes;
513 dev->stats.tx_packets = tx_packets;
518 static const struct net_device_ops gfar_netdev_ops = {
519 .ndo_open = gfar_enet_open,
520 .ndo_start_xmit = gfar_start_xmit,
521 .ndo_stop = gfar_close,
522 .ndo_change_mtu = gfar_change_mtu,
523 .ndo_set_features = gfar_set_features,
524 .ndo_set_rx_mode = gfar_set_multi,
525 .ndo_tx_timeout = gfar_timeout,
526 .ndo_do_ioctl = gfar_ioctl,
527 .ndo_get_stats = gfar_get_stats,
528 .ndo_set_mac_address = eth_mac_addr,
529 .ndo_validate_addr = eth_validate_addr,
530 #ifdef CONFIG_NET_POLL_CONTROLLER
531 .ndo_poll_controller = gfar_netpoll,
535 static void gfar_ints_disable(struct gfar_private *priv)
538 for (i = 0; i < priv->num_grps; i++) {
539 struct gfar __iomem *regs = priv->gfargrp[i].regs;
541 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
543 /* Initialize IMASK */
544 gfar_write(®s->imask, IMASK_INIT_CLEAR);
548 static void gfar_ints_enable(struct gfar_private *priv)
551 for (i = 0; i < priv->num_grps; i++) {
552 struct gfar __iomem *regs = priv->gfargrp[i].regs;
553 /* Unmask the interrupts we look for */
554 gfar_write(®s->imask, IMASK_DEFAULT);
558 static void lock_tx_qs(struct gfar_private *priv)
562 for (i = 0; i < priv->num_tx_queues; i++)
563 spin_lock(&priv->tx_queue[i]->txlock);
566 static void unlock_tx_qs(struct gfar_private *priv)
570 for (i = 0; i < priv->num_tx_queues; i++)
571 spin_unlock(&priv->tx_queue[i]->txlock);
574 static int gfar_alloc_tx_queues(struct gfar_private *priv)
578 for (i = 0; i < priv->num_tx_queues; i++) {
579 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
581 if (!priv->tx_queue[i])
584 priv->tx_queue[i]->tx_skbuff = NULL;
585 priv->tx_queue[i]->qindex = i;
586 priv->tx_queue[i]->dev = priv->ndev;
587 spin_lock_init(&(priv->tx_queue[i]->txlock));
592 static int gfar_alloc_rx_queues(struct gfar_private *priv)
596 for (i = 0; i < priv->num_rx_queues; i++) {
597 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
599 if (!priv->rx_queue[i])
602 priv->rx_queue[i]->rx_skbuff = NULL;
603 priv->rx_queue[i]->qindex = i;
604 priv->rx_queue[i]->dev = priv->ndev;
609 static void gfar_free_tx_queues(struct gfar_private *priv)
613 for (i = 0; i < priv->num_tx_queues; i++)
614 kfree(priv->tx_queue[i]);
617 static void gfar_free_rx_queues(struct gfar_private *priv)
621 for (i = 0; i < priv->num_rx_queues; i++)
622 kfree(priv->rx_queue[i]);
625 static void unmap_group_regs(struct gfar_private *priv)
629 for (i = 0; i < MAXGROUPS; i++)
630 if (priv->gfargrp[i].regs)
631 iounmap(priv->gfargrp[i].regs);
634 static void free_gfar_dev(struct gfar_private *priv)
638 for (i = 0; i < priv->num_grps; i++)
639 for (j = 0; j < GFAR_NUM_IRQS; j++) {
640 kfree(priv->gfargrp[i].irqinfo[j]);
641 priv->gfargrp[i].irqinfo[j] = NULL;
644 free_netdev(priv->ndev);
647 static void disable_napi(struct gfar_private *priv)
651 for (i = 0; i < priv->num_grps; i++) {
652 napi_disable(&priv->gfargrp[i].napi_rx);
653 napi_disable(&priv->gfargrp[i].napi_tx);
657 static void enable_napi(struct gfar_private *priv)
661 for (i = 0; i < priv->num_grps; i++) {
662 napi_enable(&priv->gfargrp[i].napi_rx);
663 napi_enable(&priv->gfargrp[i].napi_tx);
667 static int gfar_parse_group(struct device_node *np,
668 struct gfar_private *priv, const char *model)
670 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
673 for (i = 0; i < GFAR_NUM_IRQS; i++) {
674 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
676 if (!grp->irqinfo[i])
680 grp->regs = of_iomap(np, 0);
684 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
686 /* If we aren't the FEC we have multiple interrupts */
687 if (model && strcasecmp(model, "FEC")) {
688 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
689 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
690 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
691 gfar_irq(grp, RX)->irq == NO_IRQ ||
692 gfar_irq(grp, ER)->irq == NO_IRQ)
697 spin_lock_init(&grp->grplock);
698 if (priv->mode == MQ_MG_MODE) {
699 u32 *rxq_mask, *txq_mask;
700 rxq_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
701 txq_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
703 if (priv->poll_mode == GFAR_SQ_POLLING) {
704 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
705 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
706 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
707 } else { /* GFAR_MQ_POLLING */
708 grp->rx_bit_map = rxq_mask ?
709 *rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
710 grp->tx_bit_map = txq_mask ?
711 *txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
714 grp->rx_bit_map = 0xFF;
715 grp->tx_bit_map = 0xFF;
718 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
719 * right to left, so we need to revert the 8 bits to get the q index
721 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
722 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
724 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
725 * also assign queues to groups
727 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
729 grp->rx_queue = priv->rx_queue[i];
730 grp->num_rx_queues++;
731 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
732 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
733 priv->rx_queue[i]->grp = grp;
736 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
738 grp->tx_queue = priv->tx_queue[i];
739 grp->num_tx_queues++;
740 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
741 priv->tqueue |= (TQUEUE_EN0 >> i);
742 priv->tx_queue[i]->grp = grp;
750 static int gfar_of_group_count(struct device_node *np)
752 struct device_node *child;
755 for_each_available_child_of_node(np, child)
756 if (!of_node_cmp(child->name, "queue-group"))
762 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
766 const void *mac_addr;
768 struct net_device *dev = NULL;
769 struct gfar_private *priv = NULL;
770 struct device_node *np = ofdev->dev.of_node;
771 struct device_node *child = NULL;
773 const u32 *stash_len;
774 const u32 *stash_idx;
775 unsigned int num_tx_qs, num_rx_qs;
776 u32 *tx_queues, *rx_queues;
777 unsigned short mode, poll_mode;
782 if (of_device_is_compatible(np, "fsl,etsec2")) {
784 poll_mode = GFAR_SQ_POLLING;
787 poll_mode = GFAR_SQ_POLLING;
790 /* parse the num of HW tx and rx queues */
791 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
792 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
794 if (mode == SQ_SG_MODE) {
797 } else { /* MQ_MG_MODE */
798 /* get the actual number of supported groups */
799 unsigned int num_grps = gfar_of_group_count(np);
801 if (num_grps == 0 || num_grps > MAXGROUPS) {
802 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
804 pr_err("Cannot do alloc_etherdev, aborting\n");
808 if (poll_mode == GFAR_SQ_POLLING) {
809 num_tx_qs = num_grps; /* one txq per int group */
810 num_rx_qs = num_grps; /* one rxq per int group */
811 } else { /* GFAR_MQ_POLLING */
812 num_tx_qs = tx_queues ? *tx_queues : 1;
813 num_rx_qs = rx_queues ? *rx_queues : 1;
817 if (num_tx_qs > MAX_TX_QS) {
818 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
819 num_tx_qs, MAX_TX_QS);
820 pr_err("Cannot do alloc_etherdev, aborting\n");
824 if (num_rx_qs > MAX_RX_QS) {
825 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
826 num_rx_qs, MAX_RX_QS);
827 pr_err("Cannot do alloc_etherdev, aborting\n");
831 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
836 priv = netdev_priv(dev);
840 priv->poll_mode = poll_mode;
842 priv->num_tx_queues = num_tx_qs;
843 netif_set_real_num_rx_queues(dev, num_rx_qs);
844 priv->num_rx_queues = num_rx_qs;
846 err = gfar_alloc_tx_queues(priv);
848 goto tx_alloc_failed;
850 err = gfar_alloc_rx_queues(priv);
852 goto rx_alloc_failed;
854 /* Init Rx queue filer rule set linked list */
855 INIT_LIST_HEAD(&priv->rx_list.list);
856 priv->rx_list.count = 0;
857 mutex_init(&priv->rx_queue_access);
859 model = of_get_property(np, "model", NULL);
861 for (i = 0; i < MAXGROUPS; i++)
862 priv->gfargrp[i].regs = NULL;
864 /* Parse and initialize group specific information */
865 if (priv->mode == MQ_MG_MODE) {
866 for_each_available_child_of_node(np, child) {
867 if (of_node_cmp(child->name, "queue-group"))
870 err = gfar_parse_group(child, priv, model);
874 } else { /* SQ_SG_MODE */
875 err = gfar_parse_group(np, priv, model);
880 stash = of_get_property(np, "bd-stash", NULL);
883 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
884 priv->bd_stash_en = 1;
887 stash_len = of_get_property(np, "rx-stash-len", NULL);
890 priv->rx_stash_size = *stash_len;
892 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
895 priv->rx_stash_index = *stash_idx;
897 if (stash_len || stash_idx)
898 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
900 mac_addr = of_get_mac_address(np);
903 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
905 if (model && !strcasecmp(model, "TSEC"))
906 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
907 FSL_GIANFAR_DEV_HAS_COALESCE |
908 FSL_GIANFAR_DEV_HAS_RMON |
909 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
911 if (model && !strcasecmp(model, "eTSEC"))
912 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
913 FSL_GIANFAR_DEV_HAS_COALESCE |
914 FSL_GIANFAR_DEV_HAS_RMON |
915 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
916 FSL_GIANFAR_DEV_HAS_CSUM |
917 FSL_GIANFAR_DEV_HAS_VLAN |
918 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
919 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
920 FSL_GIANFAR_DEV_HAS_TIMER;
922 ctype = of_get_property(np, "phy-connection-type", NULL);
924 /* We only care about rgmii-id. The rest are autodetected */
925 if (ctype && !strcmp(ctype, "rgmii-id"))
926 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
928 priv->interface = PHY_INTERFACE_MODE_MII;
930 if (of_get_property(np, "fsl,magic-packet", NULL))
931 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
933 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
935 /* In the case of a fixed PHY, the DT node associated
936 * to the PHY is the Ethernet MAC DT node.
938 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
939 err = of_phy_register_fixed_link(np);
943 priv->phy_node = of_node_get(np);
946 /* Find the TBI PHY. If it's not there, we don't support SGMII */
947 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
952 unmap_group_regs(priv);
954 gfar_free_rx_queues(priv);
956 gfar_free_tx_queues(priv);
961 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
963 struct hwtstamp_config config;
964 struct gfar_private *priv = netdev_priv(netdev);
966 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
969 /* reserved for future extensions */
973 switch (config.tx_type) {
974 case HWTSTAMP_TX_OFF:
975 priv->hwts_tx_en = 0;
978 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
980 priv->hwts_tx_en = 1;
986 switch (config.rx_filter) {
987 case HWTSTAMP_FILTER_NONE:
988 if (priv->hwts_rx_en) {
989 priv->hwts_rx_en = 0;
994 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
996 if (!priv->hwts_rx_en) {
997 priv->hwts_rx_en = 1;
1000 config.rx_filter = HWTSTAMP_FILTER_ALL;
1004 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1008 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
1010 struct hwtstamp_config config;
1011 struct gfar_private *priv = netdev_priv(netdev);
1014 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1015 config.rx_filter = (priv->hwts_rx_en ?
1016 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
1018 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1022 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1024 struct gfar_private *priv = netdev_priv(dev);
1026 if (!netif_running(dev))
1029 if (cmd == SIOCSHWTSTAMP)
1030 return gfar_hwtstamp_set(dev, rq);
1031 if (cmd == SIOCGHWTSTAMP)
1032 return gfar_hwtstamp_get(dev, rq);
1037 return phy_mii_ioctl(priv->phydev, rq, cmd);
1040 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1043 u32 rqfpr = FPR_FILER_MASK;
1047 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1048 priv->ftp_rqfpr[rqfar] = rqfpr;
1049 priv->ftp_rqfcr[rqfar] = rqfcr;
1050 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1053 rqfcr = RQFCR_CMP_NOMATCH;
1054 priv->ftp_rqfpr[rqfar] = rqfpr;
1055 priv->ftp_rqfcr[rqfar] = rqfcr;
1056 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1059 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1061 priv->ftp_rqfcr[rqfar] = rqfcr;
1062 priv->ftp_rqfpr[rqfar] = rqfpr;
1063 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1066 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1068 priv->ftp_rqfcr[rqfar] = rqfcr;
1069 priv->ftp_rqfpr[rqfar] = rqfpr;
1070 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1075 static void gfar_init_filer_table(struct gfar_private *priv)
1078 u32 rqfar = MAX_FILER_IDX;
1080 u32 rqfpr = FPR_FILER_MASK;
1083 rqfcr = RQFCR_CMP_MATCH;
1084 priv->ftp_rqfcr[rqfar] = rqfcr;
1085 priv->ftp_rqfpr[rqfar] = rqfpr;
1086 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1088 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1089 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1090 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1091 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1092 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1093 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1095 /* cur_filer_idx indicated the first non-masked rule */
1096 priv->cur_filer_idx = rqfar;
1098 /* Rest are masked rules */
1099 rqfcr = RQFCR_CMP_NOMATCH;
1100 for (i = 0; i < rqfar; i++) {
1101 priv->ftp_rqfcr[i] = rqfcr;
1102 priv->ftp_rqfpr[i] = rqfpr;
1103 gfar_write_filer(priv, i, rqfcr, rqfpr);
1108 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1110 unsigned int pvr = mfspr(SPRN_PVR);
1111 unsigned int svr = mfspr(SPRN_SVR);
1112 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1113 unsigned int rev = svr & 0xffff;
1115 /* MPC8313 Rev 2.0 and higher; All MPC837x */
1116 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1117 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1118 priv->errata |= GFAR_ERRATA_74;
1120 /* MPC8313 and MPC837x all rev */
1121 if ((pvr == 0x80850010 && mod == 0x80b0) ||
1122 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1123 priv->errata |= GFAR_ERRATA_76;
1125 /* MPC8313 Rev < 2.0 */
1126 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1127 priv->errata |= GFAR_ERRATA_12;
1130 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1132 unsigned int svr = mfspr(SPRN_SVR);
1134 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1135 priv->errata |= GFAR_ERRATA_12;
1136 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1137 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1138 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1142 static void gfar_detect_errata(struct gfar_private *priv)
1144 struct device *dev = &priv->ofdev->dev;
1146 /* no plans to fix */
1147 priv->errata |= GFAR_ERRATA_A002;
1150 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1151 __gfar_detect_errata_85xx(priv);
1152 else /* non-mpc85xx parts, i.e. e300 core based */
1153 __gfar_detect_errata_83xx(priv);
1157 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1161 void gfar_mac_reset(struct gfar_private *priv)
1163 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1166 /* Reset MAC layer */
1167 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
1169 /* We need to delay at least 3 TX clocks */
1172 /* the soft reset bit is not self-resetting, so we need to
1173 * clear it before resuming normal operation
1175 gfar_write(®s->maccfg1, 0);
1179 /* Compute rx_buff_size based on config flags */
1180 gfar_rx_buff_size_config(priv);
1182 /* Initialize the max receive frame/buffer lengths */
1183 gfar_write(®s->maxfrm, priv->rx_buffer_size);
1184 gfar_write(®s->mrblr, priv->rx_buffer_size);
1186 /* Initialize the Minimum Frame Length Register */
1187 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
1189 /* Initialize MACCFG2. */
1190 tempval = MACCFG2_INIT_SETTINGS;
1192 /* If the mtu is larger than the max size for standard
1193 * ethernet frames (ie, a jumbo frame), then set maccfg2
1194 * to allow huge frames, and to check the length
1196 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
1197 gfar_has_errata(priv, GFAR_ERRATA_74))
1198 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1200 gfar_write(®s->maccfg2, tempval);
1202 /* Clear mac addr hash registers */
1203 gfar_write(®s->igaddr0, 0);
1204 gfar_write(®s->igaddr1, 0);
1205 gfar_write(®s->igaddr2, 0);
1206 gfar_write(®s->igaddr3, 0);
1207 gfar_write(®s->igaddr4, 0);
1208 gfar_write(®s->igaddr5, 0);
1209 gfar_write(®s->igaddr6, 0);
1210 gfar_write(®s->igaddr7, 0);
1212 gfar_write(®s->gaddr0, 0);
1213 gfar_write(®s->gaddr1, 0);
1214 gfar_write(®s->gaddr2, 0);
1215 gfar_write(®s->gaddr3, 0);
1216 gfar_write(®s->gaddr4, 0);
1217 gfar_write(®s->gaddr5, 0);
1218 gfar_write(®s->gaddr6, 0);
1219 gfar_write(®s->gaddr7, 0);
1221 if (priv->extended_hash)
1222 gfar_clear_exact_match(priv->ndev);
1224 gfar_mac_rx_config(priv);
1226 gfar_mac_tx_config(priv);
1228 gfar_set_mac_address(priv->ndev);
1230 gfar_set_multi(priv->ndev);
1232 /* clear ievent and imask before configuring coalescing */
1233 gfar_ints_disable(priv);
1235 /* Configure the coalescing support */
1236 gfar_configure_coalescing_all(priv);
1239 static void gfar_hw_init(struct gfar_private *priv)
1241 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1244 /* Stop the DMA engine now, in case it was running before
1245 * (The firmware could have used it, and left it running).
1249 gfar_mac_reset(priv);
1251 /* Zero out the rmon mib registers if it has them */
1252 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1253 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1255 /* Mask off the CAM interrupts */
1256 gfar_write(®s->rmon.cam1, 0xffffffff);
1257 gfar_write(®s->rmon.cam2, 0xffffffff);
1260 /* Initialize ECNTRL */
1261 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
1263 /* Set the extraction length and index */
1264 attrs = ATTRELI_EL(priv->rx_stash_size) |
1265 ATTRELI_EI(priv->rx_stash_index);
1267 gfar_write(®s->attreli, attrs);
1269 /* Start with defaults, and add stashing
1270 * depending on driver parameters
1272 attrs = ATTR_INIT_SETTINGS;
1274 if (priv->bd_stash_en)
1275 attrs |= ATTR_BDSTASH;
1277 if (priv->rx_stash_size != 0)
1278 attrs |= ATTR_BUFSTASH;
1280 gfar_write(®s->attr, attrs);
1283 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1284 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1285 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1287 /* Program the interrupt steering regs, only for MG devices */
1288 if (priv->num_grps > 1)
1289 gfar_write_isrg(priv);
1292 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1294 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1296 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1297 priv->extended_hash = 1;
1298 priv->hash_width = 9;
1300 priv->hash_regs[0] = ®s->igaddr0;
1301 priv->hash_regs[1] = ®s->igaddr1;
1302 priv->hash_regs[2] = ®s->igaddr2;
1303 priv->hash_regs[3] = ®s->igaddr3;
1304 priv->hash_regs[4] = ®s->igaddr4;
1305 priv->hash_regs[5] = ®s->igaddr5;
1306 priv->hash_regs[6] = ®s->igaddr6;
1307 priv->hash_regs[7] = ®s->igaddr7;
1308 priv->hash_regs[8] = ®s->gaddr0;
1309 priv->hash_regs[9] = ®s->gaddr1;
1310 priv->hash_regs[10] = ®s->gaddr2;
1311 priv->hash_regs[11] = ®s->gaddr3;
1312 priv->hash_regs[12] = ®s->gaddr4;
1313 priv->hash_regs[13] = ®s->gaddr5;
1314 priv->hash_regs[14] = ®s->gaddr6;
1315 priv->hash_regs[15] = ®s->gaddr7;
1318 priv->extended_hash = 0;
1319 priv->hash_width = 8;
1321 priv->hash_regs[0] = ®s->gaddr0;
1322 priv->hash_regs[1] = ®s->gaddr1;
1323 priv->hash_regs[2] = ®s->gaddr2;
1324 priv->hash_regs[3] = ®s->gaddr3;
1325 priv->hash_regs[4] = ®s->gaddr4;
1326 priv->hash_regs[5] = ®s->gaddr5;
1327 priv->hash_regs[6] = ®s->gaddr6;
1328 priv->hash_regs[7] = ®s->gaddr7;
1332 /* Set up the ethernet device structure, private data,
1333 * and anything else we need before we start
1335 static int gfar_probe(struct platform_device *ofdev)
1337 struct net_device *dev = NULL;
1338 struct gfar_private *priv = NULL;
1341 err = gfar_of_init(ofdev, &dev);
1346 priv = netdev_priv(dev);
1348 priv->ofdev = ofdev;
1349 priv->dev = &ofdev->dev;
1350 SET_NETDEV_DEV(dev, &ofdev->dev);
1352 spin_lock_init(&priv->bflock);
1353 INIT_WORK(&priv->reset_task, gfar_reset_task);
1355 platform_set_drvdata(ofdev, priv);
1357 gfar_detect_errata(priv);
1359 /* Set the dev->base_addr to the gfar reg region */
1360 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1362 /* Fill in the dev structure */
1363 dev->watchdog_timeo = TX_TIMEOUT;
1365 dev->netdev_ops = &gfar_netdev_ops;
1366 dev->ethtool_ops = &gfar_ethtool_ops;
1368 /* Register for napi ...We are registering NAPI for each grp */
1369 for (i = 0; i < priv->num_grps; i++) {
1370 if (priv->poll_mode == GFAR_SQ_POLLING) {
1371 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1372 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1373 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1374 gfar_poll_tx_sq, 2);
1376 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1377 gfar_poll_rx, GFAR_DEV_WEIGHT);
1378 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1383 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1384 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1386 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1387 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1390 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1391 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1392 NETIF_F_HW_VLAN_CTAG_RX;
1393 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1396 gfar_init_addr_hash_table(priv);
1398 /* Insert receive time stamps into padding alignment bytes */
1399 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1402 if (dev->features & NETIF_F_IP_CSUM ||
1403 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1404 dev->needed_headroom = GMAC_FCB_LEN;
1406 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1408 /* Initializing some of the rx/tx queue level parameters */
1409 for (i = 0; i < priv->num_tx_queues; i++) {
1410 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1411 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1412 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1413 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1416 for (i = 0; i < priv->num_rx_queues; i++) {
1417 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1418 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1419 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1422 /* always enable rx filer */
1423 priv->rx_filer_enable = 1;
1424 /* Enable most messages by default */
1425 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1426 /* use pritority h/w tx queue scheduling for single queue devices */
1427 if (priv->num_tx_queues == 1)
1428 priv->prio_sched_en = 1;
1430 set_bit(GFAR_DOWN, &priv->state);
1434 /* Carrier starts down, phylib will bring it up */
1435 netif_carrier_off(dev);
1437 err = register_netdev(dev);
1440 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1444 device_init_wakeup(&dev->dev,
1445 priv->device_flags &
1446 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1448 /* fill out IRQ number and name fields */
1449 for (i = 0; i < priv->num_grps; i++) {
1450 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1451 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1452 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1453 dev->name, "_g", '0' + i, "_tx");
1454 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1455 dev->name, "_g", '0' + i, "_rx");
1456 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1457 dev->name, "_g", '0' + i, "_er");
1459 strcpy(gfar_irq(grp, TX)->name, dev->name);
1462 /* Initialize the filer table */
1463 gfar_init_filer_table(priv);
1465 /* Print out the device info */
1466 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1468 /* Even more device info helps when determining which kernel
1469 * provided which set of benchmarks.
1471 netdev_info(dev, "Running with NAPI enabled\n");
1472 for (i = 0; i < priv->num_rx_queues; i++)
1473 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1474 i, priv->rx_queue[i]->rx_ring_size);
1475 for (i = 0; i < priv->num_tx_queues; i++)
1476 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1477 i, priv->tx_queue[i]->tx_ring_size);
1482 unmap_group_regs(priv);
1483 gfar_free_rx_queues(priv);
1484 gfar_free_tx_queues(priv);
1485 of_node_put(priv->phy_node);
1486 of_node_put(priv->tbi_node);
1487 free_gfar_dev(priv);
1491 static int gfar_remove(struct platform_device *ofdev)
1493 struct gfar_private *priv = platform_get_drvdata(ofdev);
1495 of_node_put(priv->phy_node);
1496 of_node_put(priv->tbi_node);
1498 unregister_netdev(priv->ndev);
1499 unmap_group_regs(priv);
1500 gfar_free_rx_queues(priv);
1501 gfar_free_tx_queues(priv);
1502 free_gfar_dev(priv);
1509 static int gfar_suspend(struct device *dev)
1511 struct gfar_private *priv = dev_get_drvdata(dev);
1512 struct net_device *ndev = priv->ndev;
1513 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1514 unsigned long flags;
1517 int magic_packet = priv->wol_en &&
1518 (priv->device_flags &
1519 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1521 netif_device_detach(ndev);
1523 if (netif_running(ndev)) {
1525 local_irq_save(flags);
1528 gfar_halt_nodisable(priv);
1530 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1531 tempval = gfar_read(®s->maccfg1);
1533 tempval &= ~MACCFG1_TX_EN;
1536 tempval &= ~MACCFG1_RX_EN;
1538 gfar_write(®s->maccfg1, tempval);
1541 local_irq_restore(flags);
1546 /* Enable interrupt on Magic Packet */
1547 gfar_write(®s->imask, IMASK_MAG);
1549 /* Enable Magic Packet mode */
1550 tempval = gfar_read(®s->maccfg2);
1551 tempval |= MACCFG2_MPEN;
1552 gfar_write(®s->maccfg2, tempval);
1554 phy_stop(priv->phydev);
1561 static int gfar_resume(struct device *dev)
1563 struct gfar_private *priv = dev_get_drvdata(dev);
1564 struct net_device *ndev = priv->ndev;
1565 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1566 unsigned long flags;
1568 int magic_packet = priv->wol_en &&
1569 (priv->device_flags &
1570 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1572 if (!netif_running(ndev)) {
1573 netif_device_attach(ndev);
1577 if (!magic_packet && priv->phydev)
1578 phy_start(priv->phydev);
1580 /* Disable Magic Packet mode, in case something
1583 local_irq_save(flags);
1586 tempval = gfar_read(®s->maccfg2);
1587 tempval &= ~MACCFG2_MPEN;
1588 gfar_write(®s->maccfg2, tempval);
1593 local_irq_restore(flags);
1595 netif_device_attach(ndev);
1602 static int gfar_restore(struct device *dev)
1604 struct gfar_private *priv = dev_get_drvdata(dev);
1605 struct net_device *ndev = priv->ndev;
1607 if (!netif_running(ndev)) {
1608 netif_device_attach(ndev);
1613 if (gfar_init_bds(ndev)) {
1614 free_skb_resources(priv);
1618 gfar_mac_reset(priv);
1620 gfar_init_tx_rx_base(priv);
1626 priv->oldduplex = -1;
1629 phy_start(priv->phydev);
1631 netif_device_attach(ndev);
1637 static struct dev_pm_ops gfar_pm_ops = {
1638 .suspend = gfar_suspend,
1639 .resume = gfar_resume,
1640 .freeze = gfar_suspend,
1641 .thaw = gfar_resume,
1642 .restore = gfar_restore,
1645 #define GFAR_PM_OPS (&gfar_pm_ops)
1649 #define GFAR_PM_OPS NULL
1653 /* Reads the controller's registers to determine what interface
1654 * connects it to the PHY.
1656 static phy_interface_t gfar_get_interface(struct net_device *dev)
1658 struct gfar_private *priv = netdev_priv(dev);
1659 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1662 ecntrl = gfar_read(®s->ecntrl);
1664 if (ecntrl & ECNTRL_SGMII_MODE)
1665 return PHY_INTERFACE_MODE_SGMII;
1667 if (ecntrl & ECNTRL_TBI_MODE) {
1668 if (ecntrl & ECNTRL_REDUCED_MODE)
1669 return PHY_INTERFACE_MODE_RTBI;
1671 return PHY_INTERFACE_MODE_TBI;
1674 if (ecntrl & ECNTRL_REDUCED_MODE) {
1675 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1676 return PHY_INTERFACE_MODE_RMII;
1679 phy_interface_t interface = priv->interface;
1681 /* This isn't autodetected right now, so it must
1682 * be set by the device tree or platform code.
1684 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1685 return PHY_INTERFACE_MODE_RGMII_ID;
1687 return PHY_INTERFACE_MODE_RGMII;
1691 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1692 return PHY_INTERFACE_MODE_GMII;
1694 return PHY_INTERFACE_MODE_MII;
1698 /* Initializes driver's PHY state, and attaches to the PHY.
1699 * Returns 0 on success.
1701 static int init_phy(struct net_device *dev)
1703 struct gfar_private *priv = netdev_priv(dev);
1704 uint gigabit_support =
1705 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1706 GFAR_SUPPORTED_GBIT : 0;
1707 phy_interface_t interface;
1711 priv->oldduplex = -1;
1713 interface = gfar_get_interface(dev);
1715 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1717 if (!priv->phydev) {
1718 dev_err(&dev->dev, "could not attach to PHY\n");
1722 if (interface == PHY_INTERFACE_MODE_SGMII)
1723 gfar_configure_serdes(dev);
1725 /* Remove any features not supported by the controller */
1726 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1727 priv->phydev->advertising = priv->phydev->supported;
1729 /* Add support for flow control, but don't advertise it by default */
1730 priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1735 /* Initialize TBI PHY interface for communicating with the
1736 * SERDES lynx PHY on the chip. We communicate with this PHY
1737 * through the MDIO bus on each controller, treating it as a
1738 * "normal" PHY at the address found in the TBIPA register. We assume
1739 * that the TBIPA register is valid. Either the MDIO bus code will set
1740 * it to a value that doesn't conflict with other PHYs on the bus, or the
1741 * value doesn't matter, as there are no other PHYs on the bus.
1743 static void gfar_configure_serdes(struct net_device *dev)
1745 struct gfar_private *priv = netdev_priv(dev);
1746 struct phy_device *tbiphy;
1748 if (!priv->tbi_node) {
1749 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1750 "device tree specify a tbi-handle\n");
1754 tbiphy = of_phy_find_device(priv->tbi_node);
1756 dev_err(&dev->dev, "error: Could not get TBI device\n");
1760 /* If the link is already up, we must already be ok, and don't need to
1761 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1762 * everything for us? Resetting it takes the link down and requires
1763 * several seconds for it to come back.
1765 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1768 /* Single clk mode, mii mode off(for serdes communication) */
1769 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1771 phy_write(tbiphy, MII_ADVERTISE,
1772 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1773 ADVERTISE_1000XPSE_ASYM);
1775 phy_write(tbiphy, MII_BMCR,
1776 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1780 static int __gfar_is_rx_idle(struct gfar_private *priv)
1784 /* Normaly TSEC should not hang on GRS commands, so we should
1785 * actually wait for IEVENT_GRSC flag.
1787 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1790 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1791 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1792 * and the Rx can be safely reset.
1794 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1796 if ((res & 0xffff) == (res >> 16))
1802 /* Halt the receive and transmit queues */
1803 static void gfar_halt_nodisable(struct gfar_private *priv)
1805 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1807 unsigned int timeout;
1810 gfar_ints_disable(priv);
1812 if (gfar_is_dma_stopped(priv))
1815 /* Stop the DMA, and wait for it to stop */
1816 tempval = gfar_read(®s->dmactrl);
1817 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1818 gfar_write(®s->dmactrl, tempval);
1822 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1828 stopped = gfar_is_dma_stopped(priv);
1830 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1831 !__gfar_is_rx_idle(priv))
1835 /* Halt the receive and transmit queues */
1836 void gfar_halt(struct gfar_private *priv)
1838 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1841 /* Dissable the Rx/Tx hw queues */
1842 gfar_write(®s->rqueue, 0);
1843 gfar_write(®s->tqueue, 0);
1847 gfar_halt_nodisable(priv);
1849 /* Disable Rx/Tx DMA */
1850 tempval = gfar_read(®s->maccfg1);
1851 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1852 gfar_write(®s->maccfg1, tempval);
1855 void stop_gfar(struct net_device *dev)
1857 struct gfar_private *priv = netdev_priv(dev);
1859 netif_tx_stop_all_queues(dev);
1861 smp_mb__before_atomic();
1862 set_bit(GFAR_DOWN, &priv->state);
1863 smp_mb__after_atomic();
1867 /* disable ints and gracefully shut down Rx/Tx DMA */
1870 phy_stop(priv->phydev);
1872 free_skb_resources(priv);
1875 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1877 struct txbd8 *txbdp;
1878 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1881 txbdp = tx_queue->tx_bd_base;
1883 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1884 if (!tx_queue->tx_skbuff[i])
1887 dma_unmap_single(priv->dev, txbdp->bufPtr,
1888 txbdp->length, DMA_TO_DEVICE);
1890 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1893 dma_unmap_page(priv->dev, txbdp->bufPtr,
1894 txbdp->length, DMA_TO_DEVICE);
1897 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1898 tx_queue->tx_skbuff[i] = NULL;
1900 kfree(tx_queue->tx_skbuff);
1901 tx_queue->tx_skbuff = NULL;
1904 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1906 struct rxbd8 *rxbdp;
1907 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1910 rxbdp = rx_queue->rx_bd_base;
1912 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1913 if (rx_queue->rx_skbuff[i]) {
1914 dma_unmap_single(priv->dev, rxbdp->bufPtr,
1915 priv->rx_buffer_size,
1917 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1918 rx_queue->rx_skbuff[i] = NULL;
1924 kfree(rx_queue->rx_skbuff);
1925 rx_queue->rx_skbuff = NULL;
1928 /* If there are any tx skbs or rx skbs still around, free them.
1929 * Then free tx_skbuff and rx_skbuff
1931 static void free_skb_resources(struct gfar_private *priv)
1933 struct gfar_priv_tx_q *tx_queue = NULL;
1934 struct gfar_priv_rx_q *rx_queue = NULL;
1937 /* Go through all the buffer descriptors and free their data buffers */
1938 for (i = 0; i < priv->num_tx_queues; i++) {
1939 struct netdev_queue *txq;
1941 tx_queue = priv->tx_queue[i];
1942 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1943 if (tx_queue->tx_skbuff)
1944 free_skb_tx_queue(tx_queue);
1945 netdev_tx_reset_queue(txq);
1948 for (i = 0; i < priv->num_rx_queues; i++) {
1949 rx_queue = priv->rx_queue[i];
1950 if (rx_queue->rx_skbuff)
1951 free_skb_rx_queue(rx_queue);
1954 dma_free_coherent(priv->dev,
1955 sizeof(struct txbd8) * priv->total_tx_ring_size +
1956 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1957 priv->tx_queue[0]->tx_bd_base,
1958 priv->tx_queue[0]->tx_bd_dma_base);
1961 void gfar_start(struct gfar_private *priv)
1963 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1967 /* Enable Rx/Tx hw queues */
1968 gfar_write(®s->rqueue, priv->rqueue);
1969 gfar_write(®s->tqueue, priv->tqueue);
1971 /* Initialize DMACTRL to have WWR and WOP */
1972 tempval = gfar_read(®s->dmactrl);
1973 tempval |= DMACTRL_INIT_SETTINGS;
1974 gfar_write(®s->dmactrl, tempval);
1976 /* Make sure we aren't stopped */
1977 tempval = gfar_read(®s->dmactrl);
1978 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1979 gfar_write(®s->dmactrl, tempval);
1981 for (i = 0; i < priv->num_grps; i++) {
1982 regs = priv->gfargrp[i].regs;
1983 /* Clear THLT/RHLT, so that the DMA starts polling now */
1984 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
1985 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1988 /* Enable Rx/Tx DMA */
1989 tempval = gfar_read(®s->maccfg1);
1990 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1991 gfar_write(®s->maccfg1, tempval);
1993 gfar_ints_enable(priv);
1995 priv->ndev->trans_start = jiffies; /* prevent tx timeout */
1998 static void free_grp_irqs(struct gfar_priv_grp *grp)
2000 free_irq(gfar_irq(grp, TX)->irq, grp);
2001 free_irq(gfar_irq(grp, RX)->irq, grp);
2002 free_irq(gfar_irq(grp, ER)->irq, grp);
2005 static int register_grp_irqs(struct gfar_priv_grp *grp)
2007 struct gfar_private *priv = grp->priv;
2008 struct net_device *dev = priv->ndev;
2011 /* If the device has multiple interrupts, register for
2012 * them. Otherwise, only register for the one
2014 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2015 /* Install our interrupt handlers for Error,
2016 * Transmit, and Receive
2018 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2019 gfar_irq(grp, ER)->name, grp);
2021 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2022 gfar_irq(grp, ER)->irq);
2026 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2027 gfar_irq(grp, TX)->name, grp);
2029 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2030 gfar_irq(grp, TX)->irq);
2033 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2034 gfar_irq(grp, RX)->name, grp);
2036 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2037 gfar_irq(grp, RX)->irq);
2041 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2042 gfar_irq(grp, TX)->name, grp);
2044 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2045 gfar_irq(grp, TX)->irq);
2053 free_irq(gfar_irq(grp, TX)->irq, grp);
2055 free_irq(gfar_irq(grp, ER)->irq, grp);
2061 static void gfar_free_irq(struct gfar_private *priv)
2066 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2067 for (i = 0; i < priv->num_grps; i++)
2068 free_grp_irqs(&priv->gfargrp[i]);
2070 for (i = 0; i < priv->num_grps; i++)
2071 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2076 static int gfar_request_irq(struct gfar_private *priv)
2080 for (i = 0; i < priv->num_grps; i++) {
2081 err = register_grp_irqs(&priv->gfargrp[i]);
2083 for (j = 0; j < i; j++)
2084 free_grp_irqs(&priv->gfargrp[j]);
2092 /* Bring the controller up and running */
2093 int startup_gfar(struct net_device *ndev)
2095 struct gfar_private *priv = netdev_priv(ndev);
2098 gfar_mac_reset(priv);
2100 err = gfar_alloc_skb_resources(ndev);
2104 gfar_init_tx_rx_base(priv);
2106 smp_mb__before_atomic();
2107 clear_bit(GFAR_DOWN, &priv->state);
2108 smp_mb__after_atomic();
2110 /* Start Rx/Tx DMA and enable the interrupts */
2113 phy_start(priv->phydev);
2117 netif_tx_wake_all_queues(ndev);
2122 /* Called when something needs to use the ethernet device
2123 * Returns 0 for success.
2125 static int gfar_enet_open(struct net_device *dev)
2127 struct gfar_private *priv = netdev_priv(dev);
2130 err = init_phy(dev);
2134 err = gfar_request_irq(priv);
2138 err = startup_gfar(dev);
2142 device_set_wakeup_enable(&dev->dev, priv->wol_en);
2147 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2149 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2151 memset(fcb, 0, GMAC_FCB_LEN);
2156 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2159 /* If we're here, it's a IP packet with a TCP or UDP
2160 * payload. We set it to checksum, using a pseudo-header
2163 u8 flags = TXFCB_DEFAULT;
2165 /* Tell the controller what the protocol is
2166 * And provide the already calculated phcs
2168 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2170 fcb->phcs = udp_hdr(skb)->check;
2172 fcb->phcs = tcp_hdr(skb)->check;
2174 /* l3os is the distance between the start of the
2175 * frame (skb->data) and the start of the IP hdr.
2176 * l4os is the distance between the start of the
2177 * l3 hdr and the l4 hdr
2179 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2180 fcb->l4os = skb_network_header_len(skb);
2185 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2187 fcb->flags |= TXFCB_VLN;
2188 fcb->vlctl = skb_vlan_tag_get(skb);
2191 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2192 struct txbd8 *base, int ring_size)
2194 struct txbd8 *new_bd = bdp + stride;
2196 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2199 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2202 return skip_txbd(bdp, 1, base, ring_size);
2205 /* eTSEC12: csum generation not supported for some fcb offsets */
2206 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2207 unsigned long fcb_addr)
2209 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2210 (fcb_addr % 0x20) > 0x18);
2213 /* eTSEC76: csum generation for frames larger than 2500 may
2214 * cause excess delays before start of transmission
2216 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2219 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2223 /* This is called by the kernel when a frame is ready for transmission.
2224 * It is pointed to by the dev->hard_start_xmit function pointer
2226 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2228 struct gfar_private *priv = netdev_priv(dev);
2229 struct gfar_priv_tx_q *tx_queue = NULL;
2230 struct netdev_queue *txq;
2231 struct gfar __iomem *regs = NULL;
2232 struct txfcb *fcb = NULL;
2233 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2236 int do_tstamp, do_csum, do_vlan;
2238 unsigned long flags;
2239 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2241 rq = skb->queue_mapping;
2242 tx_queue = priv->tx_queue[rq];
2243 txq = netdev_get_tx_queue(dev, rq);
2244 base = tx_queue->tx_bd_base;
2245 regs = tx_queue->grp->regs;
2247 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2248 do_vlan = skb_vlan_tag_present(skb);
2249 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2252 if (do_csum || do_vlan)
2253 fcb_len = GMAC_FCB_LEN;
2255 /* check if time stamp should be generated */
2256 if (unlikely(do_tstamp))
2257 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2259 /* make space for additional header when fcb is needed */
2260 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2261 struct sk_buff *skb_new;
2263 skb_new = skb_realloc_headroom(skb, fcb_len);
2265 dev->stats.tx_errors++;
2266 dev_kfree_skb_any(skb);
2267 return NETDEV_TX_OK;
2271 skb_set_owner_w(skb_new, skb->sk);
2272 dev_consume_skb_any(skb);
2276 /* total number of fragments in the SKB */
2277 nr_frags = skb_shinfo(skb)->nr_frags;
2279 /* calculate the required number of TxBDs for this skb */
2280 if (unlikely(do_tstamp))
2281 nr_txbds = nr_frags + 2;
2283 nr_txbds = nr_frags + 1;
2285 /* check if there is space to queue this packet */
2286 if (nr_txbds > tx_queue->num_txbdfree) {
2287 /* no space, stop the queue */
2288 netif_tx_stop_queue(txq);
2289 dev->stats.tx_fifo_errors++;
2290 return NETDEV_TX_BUSY;
2293 /* Update transmit stats */
2294 bytes_sent = skb->len;
2295 tx_queue->stats.tx_bytes += bytes_sent;
2296 /* keep Tx bytes on wire for BQL accounting */
2297 GFAR_CB(skb)->bytes_sent = bytes_sent;
2298 tx_queue->stats.tx_packets++;
2300 txbdp = txbdp_start = tx_queue->cur_tx;
2301 lstatus = txbdp->lstatus;
2303 /* Time stamp insertion requires one additional TxBD */
2304 if (unlikely(do_tstamp))
2305 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2306 tx_queue->tx_ring_size);
2308 if (nr_frags == 0) {
2309 if (unlikely(do_tstamp))
2310 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2313 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2315 /* Place the fragment addresses and lengths into the TxBDs */
2316 for (i = 0; i < nr_frags; i++) {
2317 unsigned int frag_len;
2318 /* Point at the next BD, wrapping as needed */
2319 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2321 frag_len = skb_shinfo(skb)->frags[i].size;
2323 lstatus = txbdp->lstatus | frag_len |
2324 BD_LFLAG(TXBD_READY);
2326 /* Handle the last BD specially */
2327 if (i == nr_frags - 1)
2328 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2330 bufaddr = skb_frag_dma_map(priv->dev,
2331 &skb_shinfo(skb)->frags[i],
2335 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2338 /* set the TxBD length and buffer pointer */
2339 txbdp->bufPtr = bufaddr;
2340 txbdp->lstatus = lstatus;
2343 lstatus = txbdp_start->lstatus;
2346 /* Add TxPAL between FCB and frame if required */
2347 if (unlikely(do_tstamp)) {
2348 skb_push(skb, GMAC_TXPAL_LEN);
2349 memset(skb->data, 0, GMAC_TXPAL_LEN);
2352 /* Add TxFCB if required */
2354 fcb = gfar_add_fcb(skb);
2355 lstatus |= BD_LFLAG(TXBD_TOE);
2358 /* Set up checksumming */
2360 gfar_tx_checksum(skb, fcb, fcb_len);
2362 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2363 unlikely(gfar_csum_errata_76(priv, skb->len))) {
2364 __skb_pull(skb, GMAC_FCB_LEN);
2365 skb_checksum_help(skb);
2366 if (do_vlan || do_tstamp) {
2367 /* put back a new fcb for vlan/tstamp TOE */
2368 fcb = gfar_add_fcb(skb);
2370 /* Tx TOE not used */
2371 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2378 gfar_tx_vlan(skb, fcb);
2380 /* Setup tx hardware time stamping if requested */
2381 if (unlikely(do_tstamp)) {
2382 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2386 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2388 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2391 txbdp_start->bufPtr = bufaddr;
2393 /* If time stamping is requested one additional TxBD must be set up. The
2394 * first TxBD points to the FCB and must have a data length of
2395 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2396 * the full frame length.
2398 if (unlikely(do_tstamp)) {
2399 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len;
2400 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2401 (skb_headlen(skb) - fcb_len);
2402 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2404 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2407 netdev_tx_sent_queue(txq, bytes_sent);
2409 /* We can work in parallel with gfar_clean_tx_ring(), except
2410 * when modifying num_txbdfree. Note that we didn't grab the lock
2411 * when we were reading the num_txbdfree and checking for available
2412 * space, that's because outside of this function it can only grow,
2413 * and once we've got needed space, it cannot suddenly disappear.
2415 * The lock also protects us from gfar_error(), which can modify
2416 * regs->tstat and thus retrigger the transfers, which is why we
2417 * also must grab the lock before setting ready bit for the first
2418 * to be transmitted BD.
2420 spin_lock_irqsave(&tx_queue->txlock, flags);
2424 txbdp_start->lstatus = lstatus;
2426 gfar_wmb(); /* force lstatus write before tx_skbuff */
2428 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2430 /* Update the current skb pointer to the next entry we will use
2431 * (wrapping if necessary)
2433 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2434 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2436 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2438 /* reduce TxBD free count */
2439 tx_queue->num_txbdfree -= (nr_txbds);
2441 /* If the next BD still needs to be cleaned up, then the bds
2442 * are full. We need to tell the kernel to stop sending us stuff.
2444 if (!tx_queue->num_txbdfree) {
2445 netif_tx_stop_queue(txq);
2447 dev->stats.tx_fifo_errors++;
2450 /* Tell the DMA to go go go */
2451 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2454 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2456 return NETDEV_TX_OK;
2459 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2461 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2462 for (i = 0; i < nr_frags; i++) {
2463 lstatus = txbdp->lstatus;
2464 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2467 txbdp->lstatus = lstatus & ~BD_LFLAG(TXBD_READY);
2468 bufaddr = txbdp->bufPtr;
2469 dma_unmap_page(priv->dev, bufaddr, txbdp->length,
2471 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2474 dev_kfree_skb_any(skb);
2475 return NETDEV_TX_OK;
2478 /* Stops the kernel queue, and halts the controller */
2479 static int gfar_close(struct net_device *dev)
2481 struct gfar_private *priv = netdev_priv(dev);
2483 cancel_work_sync(&priv->reset_task);
2486 /* Disconnect from the PHY */
2487 phy_disconnect(priv->phydev);
2488 priv->phydev = NULL;
2490 gfar_free_irq(priv);
2495 /* Changes the mac address if the controller is not running. */
2496 static int gfar_set_mac_address(struct net_device *dev)
2498 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2503 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2505 struct gfar_private *priv = netdev_priv(dev);
2506 int frame_size = new_mtu + ETH_HLEN;
2508 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2509 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2513 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2516 if (dev->flags & IFF_UP)
2521 if (dev->flags & IFF_UP)
2524 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2529 void reset_gfar(struct net_device *ndev)
2531 struct gfar_private *priv = netdev_priv(ndev);
2533 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2539 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2542 /* gfar_reset_task gets scheduled when a packet has not been
2543 * transmitted after a set amount of time.
2544 * For now, assume that clearing out all the structures, and
2545 * starting over will fix the problem.
2547 static void gfar_reset_task(struct work_struct *work)
2549 struct gfar_private *priv = container_of(work, struct gfar_private,
2551 reset_gfar(priv->ndev);
2554 static void gfar_timeout(struct net_device *dev)
2556 struct gfar_private *priv = netdev_priv(dev);
2558 dev->stats.tx_errors++;
2559 schedule_work(&priv->reset_task);
2562 static void gfar_align_skb(struct sk_buff *skb)
2564 /* We need the data buffer to be aligned properly. We will reserve
2565 * as many bytes as needed to align the data properly
2567 skb_reserve(skb, RXBUF_ALIGNMENT -
2568 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2571 /* Interrupt Handler for Transmit complete */
2572 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2574 struct net_device *dev = tx_queue->dev;
2575 struct netdev_queue *txq;
2576 struct gfar_private *priv = netdev_priv(dev);
2577 struct txbd8 *bdp, *next = NULL;
2578 struct txbd8 *lbdp = NULL;
2579 struct txbd8 *base = tx_queue->tx_bd_base;
2580 struct sk_buff *skb;
2582 int tx_ring_size = tx_queue->tx_ring_size;
2583 int frags = 0, nr_txbds = 0;
2586 int tqi = tx_queue->qindex;
2587 unsigned int bytes_sent = 0;
2591 txq = netdev_get_tx_queue(dev, tqi);
2592 bdp = tx_queue->dirty_tx;
2593 skb_dirtytx = tx_queue->skb_dirtytx;
2595 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2596 unsigned long flags;
2598 frags = skb_shinfo(skb)->nr_frags;
2600 /* When time stamping, one additional TxBD must be freed.
2601 * Also, we need to dma_unmap_single() the TxPAL.
2603 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2604 nr_txbds = frags + 2;
2606 nr_txbds = frags + 1;
2608 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2610 lstatus = lbdp->lstatus;
2612 /* Only clean completed frames */
2613 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2614 (lstatus & BD_LENGTH_MASK))
2617 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2618 next = next_txbd(bdp, base, tx_ring_size);
2619 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2621 buflen = bdp->length;
2623 dma_unmap_single(priv->dev, bdp->bufPtr,
2624 buflen, DMA_TO_DEVICE);
2626 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2627 struct skb_shared_hwtstamps shhwtstamps;
2628 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2630 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2631 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2632 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2633 skb_tstamp_tx(skb, &shhwtstamps);
2634 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2638 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2639 bdp = next_txbd(bdp, base, tx_ring_size);
2641 for (i = 0; i < frags; i++) {
2642 dma_unmap_page(priv->dev, bdp->bufPtr,
2643 bdp->length, DMA_TO_DEVICE);
2644 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2645 bdp = next_txbd(bdp, base, tx_ring_size);
2648 bytes_sent += GFAR_CB(skb)->bytes_sent;
2650 dev_kfree_skb_any(skb);
2652 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2654 skb_dirtytx = (skb_dirtytx + 1) &
2655 TX_RING_MOD_MASK(tx_ring_size);
2658 spin_lock_irqsave(&tx_queue->txlock, flags);
2659 tx_queue->num_txbdfree += nr_txbds;
2660 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2663 /* If we freed a buffer, we can restart transmission, if necessary */
2664 if (tx_queue->num_txbdfree &&
2665 netif_tx_queue_stopped(txq) &&
2666 !(test_bit(GFAR_DOWN, &priv->state)))
2667 netif_wake_subqueue(priv->ndev, tqi);
2669 /* Update dirty indicators */
2670 tx_queue->skb_dirtytx = skb_dirtytx;
2671 tx_queue->dirty_tx = bdp;
2673 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2676 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2678 struct gfar_private *priv = netdev_priv(dev);
2679 struct sk_buff *skb;
2681 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2685 gfar_align_skb(skb);
2690 static struct sk_buff *gfar_new_skb(struct net_device *dev, dma_addr_t *bufaddr)
2692 struct gfar_private *priv = netdev_priv(dev);
2693 struct sk_buff *skb;
2696 skb = gfar_alloc_skb(dev);
2700 addr = dma_map_single(priv->dev, skb->data,
2701 priv->rx_buffer_size, DMA_FROM_DEVICE);
2702 if (unlikely(dma_mapping_error(priv->dev, addr))) {
2703 dev_kfree_skb_any(skb);
2711 static inline void count_errors(unsigned short status, struct net_device *dev)
2713 struct gfar_private *priv = netdev_priv(dev);
2714 struct net_device_stats *stats = &dev->stats;
2715 struct gfar_extra_stats *estats = &priv->extra_stats;
2717 /* If the packet was truncated, none of the other errors matter */
2718 if (status & RXBD_TRUNCATED) {
2719 stats->rx_length_errors++;
2721 atomic64_inc(&estats->rx_trunc);
2725 /* Count the errors, if there were any */
2726 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2727 stats->rx_length_errors++;
2729 if (status & RXBD_LARGE)
2730 atomic64_inc(&estats->rx_large);
2732 atomic64_inc(&estats->rx_short);
2734 if (status & RXBD_NONOCTET) {
2735 stats->rx_frame_errors++;
2736 atomic64_inc(&estats->rx_nonoctet);
2738 if (status & RXBD_CRCERR) {
2739 atomic64_inc(&estats->rx_crcerr);
2740 stats->rx_crc_errors++;
2742 if (status & RXBD_OVERRUN) {
2743 atomic64_inc(&estats->rx_overrun);
2744 stats->rx_crc_errors++;
2748 irqreturn_t gfar_receive(int irq, void *grp_id)
2750 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2751 unsigned long flags;
2754 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2755 spin_lock_irqsave(&grp->grplock, flags);
2756 imask = gfar_read(&grp->regs->imask);
2757 imask &= IMASK_RX_DISABLED;
2758 gfar_write(&grp->regs->imask, imask);
2759 spin_unlock_irqrestore(&grp->grplock, flags);
2760 __napi_schedule(&grp->napi_rx);
2762 /* Clear IEVENT, so interrupts aren't called again
2763 * because of the packets that have already arrived.
2765 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2771 /* Interrupt Handler for Transmit complete */
2772 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2774 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2775 unsigned long flags;
2778 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2779 spin_lock_irqsave(&grp->grplock, flags);
2780 imask = gfar_read(&grp->regs->imask);
2781 imask &= IMASK_TX_DISABLED;
2782 gfar_write(&grp->regs->imask, imask);
2783 spin_unlock_irqrestore(&grp->grplock, flags);
2784 __napi_schedule(&grp->napi_tx);
2786 /* Clear IEVENT, so interrupts aren't called again
2787 * because of the packets that have already arrived.
2789 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2795 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2797 /* If valid headers were found, and valid sums
2798 * were verified, then we tell the kernel that no
2799 * checksumming is necessary. Otherwise, it is [FIXME]
2801 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2802 skb->ip_summed = CHECKSUM_UNNECESSARY;
2804 skb_checksum_none_assert(skb);
2808 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2809 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2810 int amount_pull, struct napi_struct *napi)
2812 struct gfar_private *priv = netdev_priv(dev);
2813 struct rxfcb *fcb = NULL;
2815 /* fcb is at the beginning if exists */
2816 fcb = (struct rxfcb *)skb->data;
2818 /* Remove the FCB from the skb
2819 * Remove the padded bytes, if there are any
2822 skb_record_rx_queue(skb, fcb->rq);
2823 skb_pull(skb, amount_pull);
2826 /* Get receive timestamp from the skb */
2827 if (priv->hwts_rx_en) {
2828 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2829 u64 *ns = (u64 *) skb->data;
2831 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2832 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2836 skb_pull(skb, priv->padding);
2838 if (dev->features & NETIF_F_RXCSUM)
2839 gfar_rx_checksum(skb, fcb);
2841 /* Tell the skb what kind of packet this is */
2842 skb->protocol = eth_type_trans(skb, dev);
2844 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2845 * Even if vlan rx accel is disabled, on some chips
2846 * RXFCB_VLN is pseudo randomly set.
2848 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2849 fcb->flags & RXFCB_VLN)
2850 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl);
2852 /* Send the packet up the stack */
2853 napi_gro_receive(napi, skb);
2857 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2858 * until the budget/quota has been reached. Returns the number
2861 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2863 struct net_device *dev = rx_queue->dev;
2864 struct rxbd8 *bdp, *base;
2865 struct sk_buff *skb;
2869 struct gfar_private *priv = netdev_priv(dev);
2871 /* Get the first full descriptor */
2872 bdp = rx_queue->cur_rx;
2873 base = rx_queue->rx_bd_base;
2875 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2877 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2878 struct sk_buff *newskb;
2883 /* Add another skb for the future */
2884 newskb = gfar_new_skb(dev, &bufaddr);
2886 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2888 dma_unmap_single(priv->dev, bdp->bufPtr,
2889 priv->rx_buffer_size, DMA_FROM_DEVICE);
2891 if (unlikely(!(bdp->status & RXBD_ERR) &&
2892 bdp->length > priv->rx_buffer_size))
2893 bdp->status = RXBD_LARGE;
2895 /* We drop the frame if we failed to allocate a new buffer */
2896 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2897 bdp->status & RXBD_ERR)) {
2898 count_errors(bdp->status, dev);
2900 if (unlikely(!newskb)) {
2902 bufaddr = bdp->bufPtr;
2906 /* Increment the number of packets */
2907 rx_queue->stats.rx_packets++;
2911 pkt_len = bdp->length - ETH_FCS_LEN;
2912 /* Remove the FCS from the packet length */
2913 skb_put(skb, pkt_len);
2914 rx_queue->stats.rx_bytes += pkt_len;
2915 skb_record_rx_queue(skb, rx_queue->qindex);
2916 gfar_process_frame(dev, skb, amount_pull,
2917 &rx_queue->grp->napi_rx);
2920 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2921 rx_queue->stats.rx_dropped++;
2922 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2927 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2929 /* Setup the new bdp */
2930 gfar_init_rxbdp(rx_queue, bdp, bufaddr);
2932 /* Update Last Free RxBD pointer for LFC */
2933 if (unlikely(rx_queue->rfbptr && priv->tx_actual_en))
2934 gfar_write(rx_queue->rfbptr, (u32)bdp);
2936 /* Update to the next pointer */
2937 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2939 /* update to point at the next skb */
2940 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2941 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2944 /* Update the current rxbd pointer to be the next one */
2945 rx_queue->cur_rx = bdp;
2950 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
2952 struct gfar_priv_grp *gfargrp =
2953 container_of(napi, struct gfar_priv_grp, napi_rx);
2954 struct gfar __iomem *regs = gfargrp->regs;
2955 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
2958 /* Clear IEVENT, so interrupts aren't called again
2959 * because of the packets that have already arrived
2961 gfar_write(®s->ievent, IEVENT_RX_MASK);
2963 work_done = gfar_clean_rx_ring(rx_queue, budget);
2965 if (work_done < budget) {
2967 napi_complete(napi);
2968 /* Clear the halt bit in RSTAT */
2969 gfar_write(®s->rstat, gfargrp->rstat);
2971 spin_lock_irq(&gfargrp->grplock);
2972 imask = gfar_read(®s->imask);
2973 imask |= IMASK_RX_DEFAULT;
2974 gfar_write(®s->imask, imask);
2975 spin_unlock_irq(&gfargrp->grplock);
2981 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
2983 struct gfar_priv_grp *gfargrp =
2984 container_of(napi, struct gfar_priv_grp, napi_tx);
2985 struct gfar __iomem *regs = gfargrp->regs;
2986 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
2989 /* Clear IEVENT, so interrupts aren't called again
2990 * because of the packets that have already arrived
2992 gfar_write(®s->ievent, IEVENT_TX_MASK);
2994 /* run Tx cleanup to completion */
2995 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2996 gfar_clean_tx_ring(tx_queue);
2998 napi_complete(napi);
3000 spin_lock_irq(&gfargrp->grplock);
3001 imask = gfar_read(®s->imask);
3002 imask |= IMASK_TX_DEFAULT;
3003 gfar_write(®s->imask, imask);
3004 spin_unlock_irq(&gfargrp->grplock);
3009 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3011 struct gfar_priv_grp *gfargrp =
3012 container_of(napi, struct gfar_priv_grp, napi_rx);
3013 struct gfar_private *priv = gfargrp->priv;
3014 struct gfar __iomem *regs = gfargrp->regs;
3015 struct gfar_priv_rx_q *rx_queue = NULL;
3016 int work_done = 0, work_done_per_q = 0;
3017 int i, budget_per_q = 0;
3018 unsigned long rstat_rxf;
3021 /* Clear IEVENT, so interrupts aren't called again
3022 * because of the packets that have already arrived
3024 gfar_write(®s->ievent, IEVENT_RX_MASK);
3026 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK;
3028 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3030 budget_per_q = budget/num_act_queues;
3032 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3033 /* skip queue if not active */
3034 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3037 rx_queue = priv->rx_queue[i];
3039 gfar_clean_rx_ring(rx_queue, budget_per_q);
3040 work_done += work_done_per_q;
3042 /* finished processing this queue */
3043 if (work_done_per_q < budget_per_q) {
3044 /* clear active queue hw indication */
3045 gfar_write(®s->rstat,
3046 RSTAT_CLEAR_RXF0 >> i);
3049 if (!num_act_queues)
3054 if (!num_act_queues) {
3056 napi_complete(napi);
3058 /* Clear the halt bit in RSTAT */
3059 gfar_write(®s->rstat, gfargrp->rstat);
3061 spin_lock_irq(&gfargrp->grplock);
3062 imask = gfar_read(®s->imask);
3063 imask |= IMASK_RX_DEFAULT;
3064 gfar_write(®s->imask, imask);
3065 spin_unlock_irq(&gfargrp->grplock);
3071 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3073 struct gfar_priv_grp *gfargrp =
3074 container_of(napi, struct gfar_priv_grp, napi_tx);
3075 struct gfar_private *priv = gfargrp->priv;
3076 struct gfar __iomem *regs = gfargrp->regs;
3077 struct gfar_priv_tx_q *tx_queue = NULL;
3078 int has_tx_work = 0;
3081 /* Clear IEVENT, so interrupts aren't called again
3082 * because of the packets that have already arrived
3084 gfar_write(®s->ievent, IEVENT_TX_MASK);
3086 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3087 tx_queue = priv->tx_queue[i];
3088 /* run Tx cleanup to completion */
3089 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3090 gfar_clean_tx_ring(tx_queue);
3097 napi_complete(napi);
3099 spin_lock_irq(&gfargrp->grplock);
3100 imask = gfar_read(®s->imask);
3101 imask |= IMASK_TX_DEFAULT;
3102 gfar_write(®s->imask, imask);
3103 spin_unlock_irq(&gfargrp->grplock);
3110 #ifdef CONFIG_NET_POLL_CONTROLLER
3111 /* Polling 'interrupt' - used by things like netconsole to send skbs
3112 * without having to re-enable interrupts. It's not called while
3113 * the interrupt routine is executing.
3115 static void gfar_netpoll(struct net_device *dev)
3117 struct gfar_private *priv = netdev_priv(dev);
3120 /* If the device has multiple interrupts, run tx/rx */
3121 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3122 for (i = 0; i < priv->num_grps; i++) {
3123 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3125 disable_irq(gfar_irq(grp, TX)->irq);
3126 disable_irq(gfar_irq(grp, RX)->irq);
3127 disable_irq(gfar_irq(grp, ER)->irq);
3128 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3129 enable_irq(gfar_irq(grp, ER)->irq);
3130 enable_irq(gfar_irq(grp, RX)->irq);
3131 enable_irq(gfar_irq(grp, TX)->irq);
3134 for (i = 0; i < priv->num_grps; i++) {
3135 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3137 disable_irq(gfar_irq(grp, TX)->irq);
3138 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3139 enable_irq(gfar_irq(grp, TX)->irq);
3145 /* The interrupt handler for devices with one interrupt */
3146 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3148 struct gfar_priv_grp *gfargrp = grp_id;
3150 /* Save ievent for future reference */
3151 u32 events = gfar_read(&gfargrp->regs->ievent);
3153 /* Check for reception */
3154 if (events & IEVENT_RX_MASK)
3155 gfar_receive(irq, grp_id);
3157 /* Check for transmit completion */
3158 if (events & IEVENT_TX_MASK)
3159 gfar_transmit(irq, grp_id);
3161 /* Check for errors */
3162 if (events & IEVENT_ERR_MASK)
3163 gfar_error(irq, grp_id);
3168 /* Called every time the controller might need to be made
3169 * aware of new link state. The PHY code conveys this
3170 * information through variables in the phydev structure, and this
3171 * function converts those variables into the appropriate
3172 * register values, and can bring down the device if needed.
3174 static void adjust_link(struct net_device *dev)
3176 struct gfar_private *priv = netdev_priv(dev);
3177 struct phy_device *phydev = priv->phydev;
3179 if (unlikely(phydev->link != priv->oldlink ||
3180 (phydev->link && (phydev->duplex != priv->oldduplex ||
3181 phydev->speed != priv->oldspeed))))
3182 gfar_update_link_state(priv);
3185 /* Update the hash table based on the current list of multicast
3186 * addresses we subscribe to. Also, change the promiscuity of
3187 * the device based on the flags (this function is called
3188 * whenever dev->flags is changed
3190 static void gfar_set_multi(struct net_device *dev)
3192 struct netdev_hw_addr *ha;
3193 struct gfar_private *priv = netdev_priv(dev);
3194 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3197 if (dev->flags & IFF_PROMISC) {
3198 /* Set RCTRL to PROM */
3199 tempval = gfar_read(®s->rctrl);
3200 tempval |= RCTRL_PROM;
3201 gfar_write(®s->rctrl, tempval);
3203 /* Set RCTRL to not PROM */
3204 tempval = gfar_read(®s->rctrl);
3205 tempval &= ~(RCTRL_PROM);
3206 gfar_write(®s->rctrl, tempval);
3209 if (dev->flags & IFF_ALLMULTI) {
3210 /* Set the hash to rx all multicast frames */
3211 gfar_write(®s->igaddr0, 0xffffffff);
3212 gfar_write(®s->igaddr1, 0xffffffff);
3213 gfar_write(®s->igaddr2, 0xffffffff);
3214 gfar_write(®s->igaddr3, 0xffffffff);
3215 gfar_write(®s->igaddr4, 0xffffffff);
3216 gfar_write(®s->igaddr5, 0xffffffff);
3217 gfar_write(®s->igaddr6, 0xffffffff);
3218 gfar_write(®s->igaddr7, 0xffffffff);
3219 gfar_write(®s->gaddr0, 0xffffffff);
3220 gfar_write(®s->gaddr1, 0xffffffff);
3221 gfar_write(®s->gaddr2, 0xffffffff);
3222 gfar_write(®s->gaddr3, 0xffffffff);
3223 gfar_write(®s->gaddr4, 0xffffffff);
3224 gfar_write(®s->gaddr5, 0xffffffff);
3225 gfar_write(®s->gaddr6, 0xffffffff);
3226 gfar_write(®s->gaddr7, 0xffffffff);
3231 /* zero out the hash */
3232 gfar_write(®s->igaddr0, 0x0);
3233 gfar_write(®s->igaddr1, 0x0);
3234 gfar_write(®s->igaddr2, 0x0);
3235 gfar_write(®s->igaddr3, 0x0);
3236 gfar_write(®s->igaddr4, 0x0);
3237 gfar_write(®s->igaddr5, 0x0);
3238 gfar_write(®s->igaddr6, 0x0);
3239 gfar_write(®s->igaddr7, 0x0);
3240 gfar_write(®s->gaddr0, 0x0);
3241 gfar_write(®s->gaddr1, 0x0);
3242 gfar_write(®s->gaddr2, 0x0);
3243 gfar_write(®s->gaddr3, 0x0);
3244 gfar_write(®s->gaddr4, 0x0);
3245 gfar_write(®s->gaddr5, 0x0);
3246 gfar_write(®s->gaddr6, 0x0);
3247 gfar_write(®s->gaddr7, 0x0);
3249 /* If we have extended hash tables, we need to
3250 * clear the exact match registers to prepare for
3253 if (priv->extended_hash) {
3254 em_num = GFAR_EM_NUM + 1;
3255 gfar_clear_exact_match(dev);
3262 if (netdev_mc_empty(dev))
3265 /* Parse the list, and set the appropriate bits */
3266 netdev_for_each_mc_addr(ha, dev) {
3268 gfar_set_mac_for_addr(dev, idx, ha->addr);
3271 gfar_set_hash_for_addr(dev, ha->addr);
3277 /* Clears each of the exact match registers to zero, so they
3278 * don't interfere with normal reception
3280 static void gfar_clear_exact_match(struct net_device *dev)
3283 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3285 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3286 gfar_set_mac_for_addr(dev, idx, zero_arr);
3289 /* Set the appropriate hash bit for the given addr */
3290 /* The algorithm works like so:
3291 * 1) Take the Destination Address (ie the multicast address), and
3292 * do a CRC on it (little endian), and reverse the bits of the
3294 * 2) Use the 8 most significant bits as a hash into a 256-entry
3295 * table. The table is controlled through 8 32-bit registers:
3296 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3297 * gaddr7. This means that the 3 most significant bits in the
3298 * hash index which gaddr register to use, and the 5 other bits
3299 * indicate which bit (assuming an IBM numbering scheme, which
3300 * for PowerPC (tm) is usually the case) in the register holds
3303 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3306 struct gfar_private *priv = netdev_priv(dev);
3307 u32 result = ether_crc(ETH_ALEN, addr);
3308 int width = priv->hash_width;
3309 u8 whichbit = (result >> (32 - width)) & 0x1f;
3310 u8 whichreg = result >> (32 - width + 5);
3311 u32 value = (1 << (31-whichbit));
3313 tempval = gfar_read(priv->hash_regs[whichreg]);
3315 gfar_write(priv->hash_regs[whichreg], tempval);
3319 /* There are multiple MAC Address register pairs on some controllers
3320 * This function sets the numth pair to a given address
3322 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3325 struct gfar_private *priv = netdev_priv(dev);
3326 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3328 u32 __iomem *macptr = ®s->macstnaddr1;
3332 /* For a station address of 0x12345678ABCD in transmission
3333 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3334 * MACnADDR2 is set to 0x34120000.
3336 tempval = (addr[5] << 24) | (addr[4] << 16) |
3337 (addr[3] << 8) | addr[2];
3339 gfar_write(macptr, tempval);
3341 tempval = (addr[1] << 24) | (addr[0] << 16);
3343 gfar_write(macptr+1, tempval);
3346 /* GFAR error interrupt handler */
3347 static irqreturn_t gfar_error(int irq, void *grp_id)
3349 struct gfar_priv_grp *gfargrp = grp_id;
3350 struct gfar __iomem *regs = gfargrp->regs;
3351 struct gfar_private *priv= gfargrp->priv;
3352 struct net_device *dev = priv->ndev;
3354 /* Save ievent for future reference */
3355 u32 events = gfar_read(®s->ievent);
3358 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
3360 /* Magic Packet is not an error. */
3361 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3362 (events & IEVENT_MAG))
3363 events &= ~IEVENT_MAG;
3366 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3368 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3369 events, gfar_read(®s->imask));
3371 /* Update the error counters */
3372 if (events & IEVENT_TXE) {
3373 dev->stats.tx_errors++;
3375 if (events & IEVENT_LC)
3376 dev->stats.tx_window_errors++;
3377 if (events & IEVENT_CRL)
3378 dev->stats.tx_aborted_errors++;
3379 if (events & IEVENT_XFUN) {
3380 unsigned long flags;
3382 netif_dbg(priv, tx_err, dev,
3383 "TX FIFO underrun, packet dropped\n");
3384 dev->stats.tx_dropped++;
3385 atomic64_inc(&priv->extra_stats.tx_underrun);
3387 local_irq_save(flags);
3390 /* Reactivate the Tx Queues */
3391 gfar_write(®s->tstat, gfargrp->tstat);
3394 local_irq_restore(flags);
3396 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3398 if (events & IEVENT_BSY) {
3399 dev->stats.rx_errors++;
3400 atomic64_inc(&priv->extra_stats.rx_bsy);
3402 gfar_receive(irq, grp_id);
3404 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3405 gfar_read(®s->rstat));
3407 if (events & IEVENT_BABR) {
3408 dev->stats.rx_errors++;
3409 atomic64_inc(&priv->extra_stats.rx_babr);
3411 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3413 if (events & IEVENT_EBERR) {
3414 atomic64_inc(&priv->extra_stats.eberr);
3415 netif_dbg(priv, rx_err, dev, "bus error\n");
3417 if (events & IEVENT_RXC)
3418 netif_dbg(priv, rx_status, dev, "control frame\n");
3420 if (events & IEVENT_BABT) {
3421 atomic64_inc(&priv->extra_stats.tx_babt);
3422 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3427 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3429 struct phy_device *phydev = priv->phydev;
3432 if (!phydev->duplex)
3435 if (!priv->pause_aneg_en) {
3436 if (priv->tx_pause_en)
3437 val |= MACCFG1_TX_FLOW;
3438 if (priv->rx_pause_en)
3439 val |= MACCFG1_RX_FLOW;
3441 u16 lcl_adv, rmt_adv;
3443 /* get link partner capabilities */
3446 rmt_adv = LPA_PAUSE_CAP;
3447 if (phydev->asym_pause)
3448 rmt_adv |= LPA_PAUSE_ASYM;
3451 if (phydev->advertising & ADVERTISED_Pause)
3452 lcl_adv |= ADVERTISE_PAUSE_CAP;
3453 if (phydev->advertising & ADVERTISED_Asym_Pause)
3454 lcl_adv |= ADVERTISE_PAUSE_ASYM;
3456 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3457 if (flowctrl & FLOW_CTRL_TX)
3458 val |= MACCFG1_TX_FLOW;
3459 if (flowctrl & FLOW_CTRL_RX)
3460 val |= MACCFG1_RX_FLOW;
3466 static noinline void gfar_update_link_state(struct gfar_private *priv)
3468 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3469 struct phy_device *phydev = priv->phydev;
3470 struct gfar_priv_rx_q *rx_queue = NULL;
3474 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3478 u32 tempval1 = gfar_read(®s->maccfg1);
3479 u32 tempval = gfar_read(®s->maccfg2);
3480 u32 ecntrl = gfar_read(®s->ecntrl);
3481 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
3483 if (phydev->duplex != priv->oldduplex) {
3484 if (!(phydev->duplex))
3485 tempval &= ~(MACCFG2_FULL_DUPLEX);
3487 tempval |= MACCFG2_FULL_DUPLEX;
3489 priv->oldduplex = phydev->duplex;
3492 if (phydev->speed != priv->oldspeed) {
3493 switch (phydev->speed) {
3496 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3498 ecntrl &= ~(ECNTRL_R100);
3503 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3505 /* Reduced mode distinguishes
3506 * between 10 and 100
3508 if (phydev->speed == SPEED_100)
3509 ecntrl |= ECNTRL_R100;
3511 ecntrl &= ~(ECNTRL_R100);
3514 netif_warn(priv, link, priv->ndev,
3515 "Ack! Speed (%d) is not 10/100/1000!\n",
3520 priv->oldspeed = phydev->speed;
3523 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3524 tempval1 |= gfar_get_flowctrl_cfg(priv);
3526 /* Turn last free buffer recording on */
3527 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3528 for (i = 0; i < priv->num_rx_queues; i++) {
3529 rx_queue = priv->rx_queue[i];
3530 bdp = rx_queue->cur_rx;
3531 /* skip to previous bd */
3532 bdp = skip_bd(bdp, rx_queue->rx_ring_size - 1,
3533 rx_queue->rx_bd_base,
3534 rx_queue->rx_ring_size);
3536 if (rx_queue->rfbptr)
3537 gfar_write(rx_queue->rfbptr, (u32)bdp);
3540 priv->tx_actual_en = 1;
3543 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3544 priv->tx_actual_en = 0;
3546 gfar_write(®s->maccfg1, tempval1);
3547 gfar_write(®s->maccfg2, tempval);
3548 gfar_write(®s->ecntrl, ecntrl);
3553 } else if (priv->oldlink) {
3556 priv->oldduplex = -1;
3559 if (netif_msg_link(priv))
3560 phy_print_status(phydev);
3563 static struct of_device_id gfar_match[] =
3567 .compatible = "gianfar",
3570 .compatible = "fsl,etsec2",
3574 MODULE_DEVICE_TABLE(of, gfar_match);
3576 /* Structure for a device driver */
3577 static struct platform_driver gfar_driver = {
3579 .name = "fsl-gianfar",
3581 .of_match_table = gfar_match,
3583 .probe = gfar_probe,
3584 .remove = gfar_remove,
3587 module_platform_driver(gfar_driver);