1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
81 #include <linux/of_mdio.h>
82 #include <linux/of_platform.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
87 #include <linux/net_tstamp.h>
91 #include <asm/mpc85xx.h>
93 #include <asm/uaccess.h>
94 #include <linux/module.h>
95 #include <linux/dma-mapping.h>
96 #include <linux/crc32.h>
97 #include <linux/mii.h>
98 #include <linux/phy.h>
99 #include <linux/phy_fixed.h>
100 #include <linux/of.h>
101 #include <linux/of_net.h>
105 #define TX_TIMEOUT (1*HZ)
107 const char gfar_driver_version[] = "1.3";
109 static int gfar_enet_open(struct net_device *dev);
110 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
111 static void gfar_reset_task(struct work_struct *work);
112 static void gfar_timeout(struct net_device *dev);
113 static int gfar_close(struct net_device *dev);
114 struct sk_buff *gfar_new_skb(struct net_device *dev);
115 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
116 struct sk_buff *skb);
117 static int gfar_set_mac_address(struct net_device *dev);
118 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
119 static irqreturn_t gfar_error(int irq, void *dev_id);
120 static irqreturn_t gfar_transmit(int irq, void *dev_id);
121 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
122 static void adjust_link(struct net_device *dev);
123 static void init_registers(struct net_device *dev);
124 static int init_phy(struct net_device *dev);
125 static int gfar_probe(struct platform_device *ofdev);
126 static int gfar_remove(struct platform_device *ofdev);
127 static void free_skb_resources(struct gfar_private *priv);
128 static void gfar_set_multi(struct net_device *dev);
129 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
130 static void gfar_configure_serdes(struct net_device *dev);
131 static int gfar_poll(struct napi_struct *napi, int budget);
132 static int gfar_poll_sq(struct napi_struct *napi, int budget);
133 #ifdef CONFIG_NET_POLL_CONTROLLER
134 static void gfar_netpoll(struct net_device *dev);
136 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
137 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
138 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
139 int amount_pull, struct napi_struct *napi);
140 void gfar_halt(struct net_device *dev);
141 static void gfar_halt_nodisable(struct net_device *dev);
142 void gfar_start(struct net_device *dev);
143 static void gfar_clear_exact_match(struct net_device *dev);
144 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
146 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
148 MODULE_AUTHOR("Freescale Semiconductor, Inc");
149 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150 MODULE_LICENSE("GPL");
152 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
159 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
160 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
161 lstatus |= BD_LFLAG(RXBD_WRAP);
165 bdp->lstatus = lstatus;
168 static int gfar_init_bds(struct net_device *ndev)
170 struct gfar_private *priv = netdev_priv(ndev);
171 struct gfar_priv_tx_q *tx_queue = NULL;
172 struct gfar_priv_rx_q *rx_queue = NULL;
177 for (i = 0; i < priv->num_tx_queues; i++) {
178 tx_queue = priv->tx_queue[i];
179 /* Initialize some variables in our dev structure */
180 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
181 tx_queue->dirty_tx = tx_queue->tx_bd_base;
182 tx_queue->cur_tx = tx_queue->tx_bd_base;
183 tx_queue->skb_curtx = 0;
184 tx_queue->skb_dirtytx = 0;
186 /* Initialize Transmit Descriptor Ring */
187 txbdp = tx_queue->tx_bd_base;
188 for (j = 0; j < tx_queue->tx_ring_size; j++) {
194 /* Set the last descriptor in the ring to indicate wrap */
196 txbdp->status |= TXBD_WRAP;
199 for (i = 0; i < priv->num_rx_queues; i++) {
200 rx_queue = priv->rx_queue[i];
201 rx_queue->cur_rx = rx_queue->rx_bd_base;
202 rx_queue->skb_currx = 0;
203 rxbdp = rx_queue->rx_bd_base;
205 for (j = 0; j < rx_queue->rx_ring_size; j++) {
206 struct sk_buff *skb = rx_queue->rx_skbuff[j];
209 gfar_init_rxbdp(rx_queue, rxbdp,
212 skb = gfar_new_skb(ndev);
214 netdev_err(ndev, "Can't allocate RX buffers\n");
217 rx_queue->rx_skbuff[j] = skb;
219 gfar_new_rxbdp(rx_queue, rxbdp, skb);
230 static int gfar_alloc_skb_resources(struct net_device *ndev)
235 struct gfar_private *priv = netdev_priv(ndev);
236 struct device *dev = priv->dev;
237 struct gfar_priv_tx_q *tx_queue = NULL;
238 struct gfar_priv_rx_q *rx_queue = NULL;
240 priv->total_tx_ring_size = 0;
241 for (i = 0; i < priv->num_tx_queues; i++)
242 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
244 priv->total_rx_ring_size = 0;
245 for (i = 0; i < priv->num_rx_queues; i++)
246 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
248 /* Allocate memory for the buffer descriptors */
249 vaddr = dma_alloc_coherent(dev,
250 (priv->total_tx_ring_size *
251 sizeof(struct txbd8)) +
252 (priv->total_rx_ring_size *
253 sizeof(struct rxbd8)),
258 for (i = 0; i < priv->num_tx_queues; i++) {
259 tx_queue = priv->tx_queue[i];
260 tx_queue->tx_bd_base = vaddr;
261 tx_queue->tx_bd_dma_base = addr;
262 tx_queue->dev = ndev;
263 /* enet DMA only understands physical addresses */
264 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
265 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
268 /* Start the rx descriptor ring where the tx ring leaves off */
269 for (i = 0; i < priv->num_rx_queues; i++) {
270 rx_queue = priv->rx_queue[i];
271 rx_queue->rx_bd_base = vaddr;
272 rx_queue->rx_bd_dma_base = addr;
273 rx_queue->dev = ndev;
274 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
275 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
278 /* Setup the skbuff rings */
279 for (i = 0; i < priv->num_tx_queues; i++) {
280 tx_queue = priv->tx_queue[i];
281 tx_queue->tx_skbuff =
282 kmalloc_array(tx_queue->tx_ring_size,
283 sizeof(*tx_queue->tx_skbuff),
285 if (!tx_queue->tx_skbuff)
288 for (k = 0; k < tx_queue->tx_ring_size; k++)
289 tx_queue->tx_skbuff[k] = NULL;
292 for (i = 0; i < priv->num_rx_queues; i++) {
293 rx_queue = priv->rx_queue[i];
294 rx_queue->rx_skbuff =
295 kmalloc_array(rx_queue->rx_ring_size,
296 sizeof(*rx_queue->rx_skbuff),
298 if (!rx_queue->rx_skbuff)
301 for (j = 0; j < rx_queue->rx_ring_size; j++)
302 rx_queue->rx_skbuff[j] = NULL;
305 if (gfar_init_bds(ndev))
311 free_skb_resources(priv);
315 static void gfar_init_tx_rx_base(struct gfar_private *priv)
317 struct gfar __iomem *regs = priv->gfargrp[0].regs;
321 baddr = ®s->tbase0;
322 for (i = 0; i < priv->num_tx_queues; i++) {
323 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
327 baddr = ®s->rbase0;
328 for (i = 0; i < priv->num_rx_queues; i++) {
329 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
334 static void gfar_init_mac(struct net_device *ndev)
336 struct gfar_private *priv = netdev_priv(ndev);
337 struct gfar __iomem *regs = priv->gfargrp[0].regs;
342 /* write the tx/rx base registers */
343 gfar_init_tx_rx_base(priv);
345 /* Configure the coalescing support */
346 gfar_configure_coalescing_all(priv);
348 /* set this when rx hw offload (TOE) functions are being used */
349 priv->uses_rxfcb = 0;
351 if (priv->rx_filer_enable) {
352 rctrl |= RCTRL_FILREN;
353 /* Program the RIR0 reg with the required distribution */
354 gfar_write(®s->rir0, DEFAULT_RIR0);
357 /* Restore PROMISC mode */
358 if (ndev->flags & IFF_PROMISC)
361 if (ndev->features & NETIF_F_RXCSUM) {
362 rctrl |= RCTRL_CHECKSUMMING;
363 priv->uses_rxfcb = 1;
366 if (priv->extended_hash) {
367 rctrl |= RCTRL_EXTHASH;
369 gfar_clear_exact_match(ndev);
374 rctrl &= ~RCTRL_PAL_MASK;
375 rctrl |= RCTRL_PADDING(priv->padding);
378 /* Insert receive time stamps into padding alignment bytes */
379 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
380 rctrl &= ~RCTRL_PAL_MASK;
381 rctrl |= RCTRL_PADDING(8);
385 /* Enable HW time stamping if requested from user space */
386 if (priv->hwts_rx_en) {
387 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
388 priv->uses_rxfcb = 1;
391 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) {
392 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
393 priv->uses_rxfcb = 1;
396 /* Init rctrl based on our settings */
397 gfar_write(®s->rctrl, rctrl);
399 if (ndev->features & NETIF_F_IP_CSUM)
400 tctrl |= TCTRL_INIT_CSUM;
402 if (priv->prio_sched_en)
403 tctrl |= TCTRL_TXSCHED_PRIO;
405 tctrl |= TCTRL_TXSCHED_WRRS;
406 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
407 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
410 gfar_write(®s->tctrl, tctrl);
412 /* Set the extraction length and index */
413 attrs = ATTRELI_EL(priv->rx_stash_size) |
414 ATTRELI_EI(priv->rx_stash_index);
416 gfar_write(®s->attreli, attrs);
418 /* Start with defaults, and add stashing or locking
419 * depending on the approprate variables
421 attrs = ATTR_INIT_SETTINGS;
423 if (priv->bd_stash_en)
424 attrs |= ATTR_BDSTASH;
426 if (priv->rx_stash_size != 0)
427 attrs |= ATTR_BUFSTASH;
429 gfar_write(®s->attr, attrs);
431 gfar_write(®s->fifo_tx_thr, priv->fifo_threshold);
432 gfar_write(®s->fifo_tx_starve, priv->fifo_starve);
433 gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off);
436 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
438 struct gfar_private *priv = netdev_priv(dev);
439 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
440 unsigned long tx_packets = 0, tx_bytes = 0;
443 for (i = 0; i < priv->num_rx_queues; i++) {
444 rx_packets += priv->rx_queue[i]->stats.rx_packets;
445 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
446 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
449 dev->stats.rx_packets = rx_packets;
450 dev->stats.rx_bytes = rx_bytes;
451 dev->stats.rx_dropped = rx_dropped;
453 for (i = 0; i < priv->num_tx_queues; i++) {
454 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
455 tx_packets += priv->tx_queue[i]->stats.tx_packets;
458 dev->stats.tx_bytes = tx_bytes;
459 dev->stats.tx_packets = tx_packets;
464 static const struct net_device_ops gfar_netdev_ops = {
465 .ndo_open = gfar_enet_open,
466 .ndo_start_xmit = gfar_start_xmit,
467 .ndo_stop = gfar_close,
468 .ndo_change_mtu = gfar_change_mtu,
469 .ndo_set_features = gfar_set_features,
470 .ndo_set_rx_mode = gfar_set_multi,
471 .ndo_tx_timeout = gfar_timeout,
472 .ndo_do_ioctl = gfar_ioctl,
473 .ndo_get_stats = gfar_get_stats,
474 .ndo_set_mac_address = eth_mac_addr,
475 .ndo_validate_addr = eth_validate_addr,
476 #ifdef CONFIG_NET_POLL_CONTROLLER
477 .ndo_poll_controller = gfar_netpoll,
481 void lock_rx_qs(struct gfar_private *priv)
485 for (i = 0; i < priv->num_rx_queues; i++)
486 spin_lock(&priv->rx_queue[i]->rxlock);
489 void lock_tx_qs(struct gfar_private *priv)
493 for (i = 0; i < priv->num_tx_queues; i++)
494 spin_lock(&priv->tx_queue[i]->txlock);
497 void unlock_rx_qs(struct gfar_private *priv)
501 for (i = 0; i < priv->num_rx_queues; i++)
502 spin_unlock(&priv->rx_queue[i]->rxlock);
505 void unlock_tx_qs(struct gfar_private *priv)
509 for (i = 0; i < priv->num_tx_queues; i++)
510 spin_unlock(&priv->tx_queue[i]->txlock);
513 static void free_tx_pointers(struct gfar_private *priv)
517 for (i = 0; i < priv->num_tx_queues; i++)
518 kfree(priv->tx_queue[i]);
521 static void free_rx_pointers(struct gfar_private *priv)
525 for (i = 0; i < priv->num_rx_queues; i++)
526 kfree(priv->rx_queue[i]);
529 static void unmap_group_regs(struct gfar_private *priv)
533 for (i = 0; i < MAXGROUPS; i++)
534 if (priv->gfargrp[i].regs)
535 iounmap(priv->gfargrp[i].regs);
538 static void free_gfar_dev(struct gfar_private *priv)
542 for (i = 0; i < priv->num_grps; i++)
543 for (j = 0; j < GFAR_NUM_IRQS; j++) {
544 kfree(priv->gfargrp[i].irqinfo[j]);
545 priv->gfargrp[i].irqinfo[j] = NULL;
548 free_netdev(priv->ndev);
551 static void disable_napi(struct gfar_private *priv)
555 for (i = 0; i < priv->num_grps; i++)
556 napi_disable(&priv->gfargrp[i].napi);
559 static void enable_napi(struct gfar_private *priv)
563 for (i = 0; i < priv->num_grps; i++)
564 napi_enable(&priv->gfargrp[i].napi);
567 static int gfar_parse_group(struct device_node *np,
568 struct gfar_private *priv, const char *model)
570 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
574 for (i = 0; i < GFAR_NUM_IRQS; i++) {
575 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
577 if (!grp->irqinfo[i])
581 grp->regs = of_iomap(np, 0);
585 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
587 /* If we aren't the FEC we have multiple interrupts */
588 if (model && strcasecmp(model, "FEC")) {
589 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
590 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
591 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
592 gfar_irq(grp, RX)->irq == NO_IRQ ||
593 gfar_irq(grp, ER)->irq == NO_IRQ)
598 spin_lock_init(&grp->grplock);
599 if (priv->mode == MQ_MG_MODE) {
600 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
601 grp->rx_bit_map = queue_mask ?
602 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
603 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
604 grp->tx_bit_map = queue_mask ?
605 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
607 grp->rx_bit_map = 0xFF;
608 grp->tx_bit_map = 0xFF;
615 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
619 const void *mac_addr;
621 struct net_device *dev = NULL;
622 struct gfar_private *priv = NULL;
623 struct device_node *np = ofdev->dev.of_node;
624 struct device_node *child = NULL;
626 const u32 *stash_len;
627 const u32 *stash_idx;
628 unsigned int num_tx_qs, num_rx_qs;
629 u32 *tx_queues, *rx_queues;
631 if (!np || !of_device_is_available(np))
634 /* parse the num of tx and rx queues */
635 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
636 num_tx_qs = tx_queues ? *tx_queues : 1;
638 if (num_tx_qs > MAX_TX_QS) {
639 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
640 num_tx_qs, MAX_TX_QS);
641 pr_err("Cannot do alloc_etherdev, aborting\n");
645 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
646 num_rx_qs = rx_queues ? *rx_queues : 1;
648 if (num_rx_qs > MAX_RX_QS) {
649 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
650 num_rx_qs, MAX_RX_QS);
651 pr_err("Cannot do alloc_etherdev, aborting\n");
655 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
660 priv = netdev_priv(dev);
663 priv->num_tx_queues = num_tx_qs;
664 netif_set_real_num_rx_queues(dev, num_rx_qs);
665 priv->num_rx_queues = num_rx_qs;
666 priv->num_grps = 0x0;
668 /* Init Rx queue filer rule set linked list */
669 INIT_LIST_HEAD(&priv->rx_list.list);
670 priv->rx_list.count = 0;
671 mutex_init(&priv->rx_queue_access);
673 model = of_get_property(np, "model", NULL);
675 for (i = 0; i < MAXGROUPS; i++)
676 priv->gfargrp[i].regs = NULL;
678 /* Parse and initialize group specific information */
679 if (of_device_is_compatible(np, "fsl,etsec2")) {
680 priv->mode = MQ_MG_MODE;
681 for_each_child_of_node(np, child) {
682 err = gfar_parse_group(child, priv, model);
687 priv->mode = SQ_SG_MODE;
688 err = gfar_parse_group(np, priv, model);
693 for (i = 0; i < priv->num_tx_queues; i++)
694 priv->tx_queue[i] = NULL;
695 for (i = 0; i < priv->num_rx_queues; i++)
696 priv->rx_queue[i] = NULL;
698 for (i = 0; i < priv->num_tx_queues; i++) {
699 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
701 if (!priv->tx_queue[i]) {
703 goto tx_alloc_failed;
705 priv->tx_queue[i]->tx_skbuff = NULL;
706 priv->tx_queue[i]->qindex = i;
707 priv->tx_queue[i]->dev = dev;
708 spin_lock_init(&(priv->tx_queue[i]->txlock));
711 for (i = 0; i < priv->num_rx_queues; i++) {
712 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
714 if (!priv->rx_queue[i]) {
716 goto rx_alloc_failed;
718 priv->rx_queue[i]->rx_skbuff = NULL;
719 priv->rx_queue[i]->qindex = i;
720 priv->rx_queue[i]->dev = dev;
721 spin_lock_init(&(priv->rx_queue[i]->rxlock));
725 stash = of_get_property(np, "bd-stash", NULL);
728 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
729 priv->bd_stash_en = 1;
732 stash_len = of_get_property(np, "rx-stash-len", NULL);
735 priv->rx_stash_size = *stash_len;
737 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
740 priv->rx_stash_index = *stash_idx;
742 if (stash_len || stash_idx)
743 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
745 mac_addr = of_get_mac_address(np);
748 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
750 if (model && !strcasecmp(model, "TSEC"))
751 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
752 FSL_GIANFAR_DEV_HAS_COALESCE |
753 FSL_GIANFAR_DEV_HAS_RMON |
754 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
756 if (model && !strcasecmp(model, "eTSEC"))
757 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
758 FSL_GIANFAR_DEV_HAS_COALESCE |
759 FSL_GIANFAR_DEV_HAS_RMON |
760 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
761 FSL_GIANFAR_DEV_HAS_PADDING |
762 FSL_GIANFAR_DEV_HAS_CSUM |
763 FSL_GIANFAR_DEV_HAS_VLAN |
764 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
765 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
766 FSL_GIANFAR_DEV_HAS_TIMER;
768 ctype = of_get_property(np, "phy-connection-type", NULL);
770 /* We only care about rgmii-id. The rest are autodetected */
771 if (ctype && !strcmp(ctype, "rgmii-id"))
772 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
774 priv->interface = PHY_INTERFACE_MODE_MII;
776 if (of_get_property(np, "fsl,magic-packet", NULL))
777 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
779 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
781 /* Find the TBI PHY. If it's not there, we don't support SGMII */
782 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
787 free_rx_pointers(priv);
789 free_tx_pointers(priv);
791 unmap_group_regs(priv);
796 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
797 struct ifreq *ifr, int cmd)
799 struct hwtstamp_config config;
800 struct gfar_private *priv = netdev_priv(netdev);
802 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
805 /* reserved for future extensions */
809 switch (config.tx_type) {
810 case HWTSTAMP_TX_OFF:
811 priv->hwts_tx_en = 0;
814 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
816 priv->hwts_tx_en = 1;
822 switch (config.rx_filter) {
823 case HWTSTAMP_FILTER_NONE:
824 if (priv->hwts_rx_en) {
826 priv->hwts_rx_en = 0;
827 startup_gfar(netdev);
831 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
833 if (!priv->hwts_rx_en) {
835 priv->hwts_rx_en = 1;
836 startup_gfar(netdev);
838 config.rx_filter = HWTSTAMP_FILTER_ALL;
842 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
846 /* Ioctl MII Interface */
847 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
849 struct gfar_private *priv = netdev_priv(dev);
851 if (!netif_running(dev))
854 if (cmd == SIOCSHWTSTAMP)
855 return gfar_hwtstamp_ioctl(dev, rq, cmd);
860 return phy_mii_ioctl(priv->phydev, rq, cmd);
863 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
865 unsigned int new_bit_map = 0x0;
866 int mask = 0x1 << (max_qs - 1), i;
868 for (i = 0; i < max_qs; i++) {
870 new_bit_map = new_bit_map + (1 << i);
876 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
879 u32 rqfpr = FPR_FILER_MASK;
883 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
884 priv->ftp_rqfpr[rqfar] = rqfpr;
885 priv->ftp_rqfcr[rqfar] = rqfcr;
886 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
889 rqfcr = RQFCR_CMP_NOMATCH;
890 priv->ftp_rqfpr[rqfar] = rqfpr;
891 priv->ftp_rqfcr[rqfar] = rqfcr;
892 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
895 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
897 priv->ftp_rqfcr[rqfar] = rqfcr;
898 priv->ftp_rqfpr[rqfar] = rqfpr;
899 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
902 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
904 priv->ftp_rqfcr[rqfar] = rqfcr;
905 priv->ftp_rqfpr[rqfar] = rqfpr;
906 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
911 static void gfar_init_filer_table(struct gfar_private *priv)
914 u32 rqfar = MAX_FILER_IDX;
916 u32 rqfpr = FPR_FILER_MASK;
919 rqfcr = RQFCR_CMP_MATCH;
920 priv->ftp_rqfcr[rqfar] = rqfcr;
921 priv->ftp_rqfpr[rqfar] = rqfpr;
922 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
924 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
925 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
926 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
927 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
928 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
929 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
931 /* cur_filer_idx indicated the first non-masked rule */
932 priv->cur_filer_idx = rqfar;
934 /* Rest are masked rules */
935 rqfcr = RQFCR_CMP_NOMATCH;
936 for (i = 0; i < rqfar; i++) {
937 priv->ftp_rqfcr[i] = rqfcr;
938 priv->ftp_rqfpr[i] = rqfpr;
939 gfar_write_filer(priv, i, rqfcr, rqfpr);
943 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
945 unsigned int pvr = mfspr(SPRN_PVR);
946 unsigned int svr = mfspr(SPRN_SVR);
947 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
948 unsigned int rev = svr & 0xffff;
950 /* MPC8313 Rev 2.0 and higher; All MPC837x */
951 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
952 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
953 priv->errata |= GFAR_ERRATA_74;
955 /* MPC8313 and MPC837x all rev */
956 if ((pvr == 0x80850010 && mod == 0x80b0) ||
957 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
958 priv->errata |= GFAR_ERRATA_76;
960 /* MPC8313 Rev < 2.0 */
961 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
962 priv->errata |= GFAR_ERRATA_12;
965 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
967 unsigned int svr = mfspr(SPRN_SVR);
969 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
970 priv->errata |= GFAR_ERRATA_12;
971 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
972 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
973 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
976 static void gfar_detect_errata(struct gfar_private *priv)
978 struct device *dev = &priv->ofdev->dev;
980 /* no plans to fix */
981 priv->errata |= GFAR_ERRATA_A002;
983 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
984 __gfar_detect_errata_85xx(priv);
985 else /* non-mpc85xx parts, i.e. e300 core based */
986 __gfar_detect_errata_83xx(priv);
989 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
993 /* Set up the ethernet device structure, private data,
994 * and anything else we need before we start
996 static int gfar_probe(struct platform_device *ofdev)
999 struct net_device *dev = NULL;
1000 struct gfar_private *priv = NULL;
1001 struct gfar __iomem *regs = NULL;
1002 int err = 0, i, grp_idx = 0;
1003 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
1007 err = gfar_of_init(ofdev, &dev);
1012 priv = netdev_priv(dev);
1014 priv->ofdev = ofdev;
1015 priv->dev = &ofdev->dev;
1016 SET_NETDEV_DEV(dev, &ofdev->dev);
1018 spin_lock_init(&priv->bflock);
1019 INIT_WORK(&priv->reset_task, gfar_reset_task);
1021 platform_set_drvdata(ofdev, priv);
1022 regs = priv->gfargrp[0].regs;
1024 gfar_detect_errata(priv);
1026 /* Stop the DMA engine now, in case it was running before
1027 * (The firmware could have used it, and left it running).
1031 /* Reset MAC layer */
1032 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
1034 /* We need to delay at least 3 TX clocks */
1038 if (!priv->pause_aneg_en && priv->tx_pause_en)
1039 tempval |= MACCFG1_TX_FLOW;
1040 if (!priv->pause_aneg_en && priv->rx_pause_en)
1041 tempval |= MACCFG1_RX_FLOW;
1042 /* the soft reset bit is not self-resetting, so we need to
1043 * clear it before resuming normal operation
1045 gfar_write(®s->maccfg1, tempval);
1047 /* Initialize MACCFG2. */
1048 tempval = MACCFG2_INIT_SETTINGS;
1049 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1050 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1051 gfar_write(®s->maccfg2, tempval);
1053 /* Initialize ECNTRL */
1054 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
1056 /* Set the dev->base_addr to the gfar reg region */
1057 dev->base_addr = (unsigned long) regs;
1059 /* Fill in the dev structure */
1060 dev->watchdog_timeo = TX_TIMEOUT;
1062 dev->netdev_ops = &gfar_netdev_ops;
1063 dev->ethtool_ops = &gfar_ethtool_ops;
1065 /* Register for napi ...We are registering NAPI for each grp */
1066 if (priv->mode == SQ_SG_MODE)
1067 netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq,
1070 for (i = 0; i < priv->num_grps; i++)
1071 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1074 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1075 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1077 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1078 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1081 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1082 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1083 NETIF_F_HW_VLAN_CTAG_RX;
1084 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1087 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1088 priv->extended_hash = 1;
1089 priv->hash_width = 9;
1091 priv->hash_regs[0] = ®s->igaddr0;
1092 priv->hash_regs[1] = ®s->igaddr1;
1093 priv->hash_regs[2] = ®s->igaddr2;
1094 priv->hash_regs[3] = ®s->igaddr3;
1095 priv->hash_regs[4] = ®s->igaddr4;
1096 priv->hash_regs[5] = ®s->igaddr5;
1097 priv->hash_regs[6] = ®s->igaddr6;
1098 priv->hash_regs[7] = ®s->igaddr7;
1099 priv->hash_regs[8] = ®s->gaddr0;
1100 priv->hash_regs[9] = ®s->gaddr1;
1101 priv->hash_regs[10] = ®s->gaddr2;
1102 priv->hash_regs[11] = ®s->gaddr3;
1103 priv->hash_regs[12] = ®s->gaddr4;
1104 priv->hash_regs[13] = ®s->gaddr5;
1105 priv->hash_regs[14] = ®s->gaddr6;
1106 priv->hash_regs[15] = ®s->gaddr7;
1109 priv->extended_hash = 0;
1110 priv->hash_width = 8;
1112 priv->hash_regs[0] = ®s->gaddr0;
1113 priv->hash_regs[1] = ®s->gaddr1;
1114 priv->hash_regs[2] = ®s->gaddr2;
1115 priv->hash_regs[3] = ®s->gaddr3;
1116 priv->hash_regs[4] = ®s->gaddr4;
1117 priv->hash_regs[5] = ®s->gaddr5;
1118 priv->hash_regs[6] = ®s->gaddr6;
1119 priv->hash_regs[7] = ®s->gaddr7;
1122 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1123 priv->padding = DEFAULT_PADDING;
1127 if (dev->features & NETIF_F_IP_CSUM ||
1128 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1129 dev->needed_headroom = GMAC_FCB_LEN;
1131 /* Program the isrg regs only if number of grps > 1 */
1132 if (priv->num_grps > 1) {
1133 baddr = ®s->isrg0;
1134 for (i = 0; i < priv->num_grps; i++) {
1135 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1136 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1137 gfar_write(baddr, isrg);
1143 /* Need to reverse the bit maps as bit_map's MSB is q0
1144 * but, for_each_set_bit parses from right to left, which
1145 * basically reverses the queue numbers
1147 for (i = 0; i< priv->num_grps; i++) {
1148 priv->gfargrp[i].tx_bit_map =
1149 reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1150 priv->gfargrp[i].rx_bit_map =
1151 reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1154 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1155 * also assign queues to groups
1157 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1158 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1160 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1161 priv->num_rx_queues) {
1162 priv->gfargrp[grp_idx].num_rx_queues++;
1163 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1164 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1165 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1167 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1169 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1170 priv->num_tx_queues) {
1171 priv->gfargrp[grp_idx].num_tx_queues++;
1172 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1173 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1174 tqueue = tqueue | (TQUEUE_EN0 >> i);
1176 priv->gfargrp[grp_idx].rstat = rstat;
1177 priv->gfargrp[grp_idx].tstat = tstat;
1181 gfar_write(®s->rqueue, rqueue);
1182 gfar_write(®s->tqueue, tqueue);
1184 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1186 /* Initializing some of the rx/tx queue level parameters */
1187 for (i = 0; i < priv->num_tx_queues; i++) {
1188 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1189 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1190 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1191 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1194 for (i = 0; i < priv->num_rx_queues; i++) {
1195 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1196 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1197 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1200 /* always enable rx filer */
1201 priv->rx_filer_enable = 1;
1202 /* Enable most messages by default */
1203 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1204 /* use pritority h/w tx queue scheduling for single queue devices */
1205 if (priv->num_tx_queues == 1)
1206 priv->prio_sched_en = 1;
1208 /* Carrier starts down, phylib will bring it up */
1209 netif_carrier_off(dev);
1211 err = register_netdev(dev);
1214 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1218 device_init_wakeup(&dev->dev,
1219 priv->device_flags &
1220 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1222 /* fill out IRQ number and name fields */
1223 for (i = 0; i < priv->num_grps; i++) {
1224 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1225 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1226 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1227 dev->name, "_g", '0' + i, "_tx");
1228 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1229 dev->name, "_g", '0' + i, "_rx");
1230 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1231 dev->name, "_g", '0' + i, "_er");
1233 strcpy(gfar_irq(grp, TX)->name, dev->name);
1236 /* Initialize the filer table */
1237 gfar_init_filer_table(priv);
1239 /* Create all the sysfs files */
1240 gfar_init_sysfs(dev);
1242 /* Print out the device info */
1243 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1245 /* Even more device info helps when determining which kernel
1246 * provided which set of benchmarks.
1248 netdev_info(dev, "Running with NAPI enabled\n");
1249 for (i = 0; i < priv->num_rx_queues; i++)
1250 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1251 i, priv->rx_queue[i]->rx_ring_size);
1252 for (i = 0; i < priv->num_tx_queues; i++)
1253 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1254 i, priv->tx_queue[i]->tx_ring_size);
1259 unmap_group_regs(priv);
1260 free_tx_pointers(priv);
1261 free_rx_pointers(priv);
1263 of_node_put(priv->phy_node);
1265 of_node_put(priv->tbi_node);
1266 free_gfar_dev(priv);
1270 static int gfar_remove(struct platform_device *ofdev)
1272 struct gfar_private *priv = platform_get_drvdata(ofdev);
1275 of_node_put(priv->phy_node);
1277 of_node_put(priv->tbi_node);
1279 unregister_netdev(priv->ndev);
1280 unmap_group_regs(priv);
1281 free_gfar_dev(priv);
1288 static int gfar_suspend(struct device *dev)
1290 struct gfar_private *priv = dev_get_drvdata(dev);
1291 struct net_device *ndev = priv->ndev;
1292 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1293 unsigned long flags;
1296 int magic_packet = priv->wol_en &&
1297 (priv->device_flags &
1298 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1300 netif_device_detach(ndev);
1302 if (netif_running(ndev)) {
1304 local_irq_save(flags);
1308 gfar_halt_nodisable(ndev);
1310 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1311 tempval = gfar_read(®s->maccfg1);
1313 tempval &= ~MACCFG1_TX_EN;
1316 tempval &= ~MACCFG1_RX_EN;
1318 gfar_write(®s->maccfg1, tempval);
1322 local_irq_restore(flags);
1327 /* Enable interrupt on Magic Packet */
1328 gfar_write(®s->imask, IMASK_MAG);
1330 /* Enable Magic Packet mode */
1331 tempval = gfar_read(®s->maccfg2);
1332 tempval |= MACCFG2_MPEN;
1333 gfar_write(®s->maccfg2, tempval);
1335 phy_stop(priv->phydev);
1342 static int gfar_resume(struct device *dev)
1344 struct gfar_private *priv = dev_get_drvdata(dev);
1345 struct net_device *ndev = priv->ndev;
1346 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1347 unsigned long flags;
1349 int magic_packet = priv->wol_en &&
1350 (priv->device_flags &
1351 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1353 if (!netif_running(ndev)) {
1354 netif_device_attach(ndev);
1358 if (!magic_packet && priv->phydev)
1359 phy_start(priv->phydev);
1361 /* Disable Magic Packet mode, in case something
1364 local_irq_save(flags);
1368 tempval = gfar_read(®s->maccfg2);
1369 tempval &= ~MACCFG2_MPEN;
1370 gfar_write(®s->maccfg2, tempval);
1376 local_irq_restore(flags);
1378 netif_device_attach(ndev);
1385 static int gfar_restore(struct device *dev)
1387 struct gfar_private *priv = dev_get_drvdata(dev);
1388 struct net_device *ndev = priv->ndev;
1390 if (!netif_running(ndev)) {
1391 netif_device_attach(ndev);
1396 if (gfar_init_bds(ndev)) {
1397 free_skb_resources(priv);
1401 init_registers(ndev);
1402 gfar_set_mac_address(ndev);
1403 gfar_init_mac(ndev);
1408 priv->oldduplex = -1;
1411 phy_start(priv->phydev);
1413 netif_device_attach(ndev);
1419 static struct dev_pm_ops gfar_pm_ops = {
1420 .suspend = gfar_suspend,
1421 .resume = gfar_resume,
1422 .freeze = gfar_suspend,
1423 .thaw = gfar_resume,
1424 .restore = gfar_restore,
1427 #define GFAR_PM_OPS (&gfar_pm_ops)
1431 #define GFAR_PM_OPS NULL
1435 /* Reads the controller's registers to determine what interface
1436 * connects it to the PHY.
1438 static phy_interface_t gfar_get_interface(struct net_device *dev)
1440 struct gfar_private *priv = netdev_priv(dev);
1441 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1444 ecntrl = gfar_read(®s->ecntrl);
1446 if (ecntrl & ECNTRL_SGMII_MODE)
1447 return PHY_INTERFACE_MODE_SGMII;
1449 if (ecntrl & ECNTRL_TBI_MODE) {
1450 if (ecntrl & ECNTRL_REDUCED_MODE)
1451 return PHY_INTERFACE_MODE_RTBI;
1453 return PHY_INTERFACE_MODE_TBI;
1456 if (ecntrl & ECNTRL_REDUCED_MODE) {
1457 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1458 return PHY_INTERFACE_MODE_RMII;
1461 phy_interface_t interface = priv->interface;
1463 /* This isn't autodetected right now, so it must
1464 * be set by the device tree or platform code.
1466 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1467 return PHY_INTERFACE_MODE_RGMII_ID;
1469 return PHY_INTERFACE_MODE_RGMII;
1473 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1474 return PHY_INTERFACE_MODE_GMII;
1476 return PHY_INTERFACE_MODE_MII;
1480 /* Initializes driver's PHY state, and attaches to the PHY.
1481 * Returns 0 on success.
1483 static int init_phy(struct net_device *dev)
1485 struct gfar_private *priv = netdev_priv(dev);
1486 uint gigabit_support =
1487 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1488 GFAR_SUPPORTED_GBIT : 0;
1489 phy_interface_t interface;
1493 priv->oldduplex = -1;
1495 interface = gfar_get_interface(dev);
1497 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1500 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1502 if (!priv->phydev) {
1503 dev_err(&dev->dev, "could not attach to PHY\n");
1507 if (interface == PHY_INTERFACE_MODE_SGMII)
1508 gfar_configure_serdes(dev);
1510 /* Remove any features not supported by the controller */
1511 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1512 priv->phydev->advertising = priv->phydev->supported;
1517 /* Initialize TBI PHY interface for communicating with the
1518 * SERDES lynx PHY on the chip. We communicate with this PHY
1519 * through the MDIO bus on each controller, treating it as a
1520 * "normal" PHY at the address found in the TBIPA register. We assume
1521 * that the TBIPA register is valid. Either the MDIO bus code will set
1522 * it to a value that doesn't conflict with other PHYs on the bus, or the
1523 * value doesn't matter, as there are no other PHYs on the bus.
1525 static void gfar_configure_serdes(struct net_device *dev)
1527 struct gfar_private *priv = netdev_priv(dev);
1528 struct phy_device *tbiphy;
1530 if (!priv->tbi_node) {
1531 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1532 "device tree specify a tbi-handle\n");
1536 tbiphy = of_phy_find_device(priv->tbi_node);
1538 dev_err(&dev->dev, "error: Could not get TBI device\n");
1542 /* If the link is already up, we must already be ok, and don't need to
1543 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1544 * everything for us? Resetting it takes the link down and requires
1545 * several seconds for it to come back.
1547 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1550 /* Single clk mode, mii mode off(for serdes communication) */
1551 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1553 phy_write(tbiphy, MII_ADVERTISE,
1554 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1555 ADVERTISE_1000XPSE_ASYM);
1557 phy_write(tbiphy, MII_BMCR,
1558 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1562 static void init_registers(struct net_device *dev)
1564 struct gfar_private *priv = netdev_priv(dev);
1565 struct gfar __iomem *regs = NULL;
1568 for (i = 0; i < priv->num_grps; i++) {
1569 regs = priv->gfargrp[i].regs;
1571 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
1573 /* Initialize IMASK */
1574 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1577 regs = priv->gfargrp[0].regs;
1578 /* Init hash registers to zero */
1579 gfar_write(®s->igaddr0, 0);
1580 gfar_write(®s->igaddr1, 0);
1581 gfar_write(®s->igaddr2, 0);
1582 gfar_write(®s->igaddr3, 0);
1583 gfar_write(®s->igaddr4, 0);
1584 gfar_write(®s->igaddr5, 0);
1585 gfar_write(®s->igaddr6, 0);
1586 gfar_write(®s->igaddr7, 0);
1588 gfar_write(®s->gaddr0, 0);
1589 gfar_write(®s->gaddr1, 0);
1590 gfar_write(®s->gaddr2, 0);
1591 gfar_write(®s->gaddr3, 0);
1592 gfar_write(®s->gaddr4, 0);
1593 gfar_write(®s->gaddr5, 0);
1594 gfar_write(®s->gaddr6, 0);
1595 gfar_write(®s->gaddr7, 0);
1597 /* Zero out the rmon mib registers if it has them */
1598 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1599 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1601 /* Mask off the CAM interrupts */
1602 gfar_write(®s->rmon.cam1, 0xffffffff);
1603 gfar_write(®s->rmon.cam2, 0xffffffff);
1606 /* Initialize the max receive buffer length */
1607 gfar_write(®s->mrblr, priv->rx_buffer_size);
1609 /* Initialize the Minimum Frame Length Register */
1610 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
1613 static int __gfar_is_rx_idle(struct gfar_private *priv)
1617 /* Normaly TSEC should not hang on GRS commands, so we should
1618 * actually wait for IEVENT_GRSC flag.
1620 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1623 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1624 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1625 * and the Rx can be safely reset.
1627 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1629 if ((res & 0xffff) == (res >> 16))
1635 /* Halt the receive and transmit queues */
1636 static void gfar_halt_nodisable(struct net_device *dev)
1638 struct gfar_private *priv = netdev_priv(dev);
1639 struct gfar __iomem *regs = NULL;
1643 for (i = 0; i < priv->num_grps; i++) {
1644 regs = priv->gfargrp[i].regs;
1645 /* Mask all interrupts */
1646 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1648 /* Clear all interrupts */
1649 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
1652 regs = priv->gfargrp[0].regs;
1653 /* Stop the DMA, and wait for it to stop */
1654 tempval = gfar_read(®s->dmactrl);
1655 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1656 (DMACTRL_GRS | DMACTRL_GTS)) {
1659 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1660 gfar_write(®s->dmactrl, tempval);
1663 ret = spin_event_timeout(((gfar_read(®s->ievent) &
1664 (IEVENT_GRSC | IEVENT_GTSC)) ==
1665 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1666 if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC))
1667 ret = __gfar_is_rx_idle(priv);
1672 /* Halt the receive and transmit queues */
1673 void gfar_halt(struct net_device *dev)
1675 struct gfar_private *priv = netdev_priv(dev);
1676 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1679 gfar_halt_nodisable(dev);
1681 /* Disable Rx and Tx */
1682 tempval = gfar_read(®s->maccfg1);
1683 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1684 gfar_write(®s->maccfg1, tempval);
1687 static void free_grp_irqs(struct gfar_priv_grp *grp)
1689 free_irq(gfar_irq(grp, TX)->irq, grp);
1690 free_irq(gfar_irq(grp, RX)->irq, grp);
1691 free_irq(gfar_irq(grp, ER)->irq, grp);
1694 void stop_gfar(struct net_device *dev)
1696 struct gfar_private *priv = netdev_priv(dev);
1697 unsigned long flags;
1700 phy_stop(priv->phydev);
1704 local_irq_save(flags);
1712 local_irq_restore(flags);
1715 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1716 for (i = 0; i < priv->num_grps; i++)
1717 free_grp_irqs(&priv->gfargrp[i]);
1719 for (i = 0; i < priv->num_grps; i++)
1720 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1724 free_skb_resources(priv);
1727 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1729 struct txbd8 *txbdp;
1730 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1733 txbdp = tx_queue->tx_bd_base;
1735 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1736 if (!tx_queue->tx_skbuff[i])
1739 dma_unmap_single(priv->dev, txbdp->bufPtr,
1740 txbdp->length, DMA_TO_DEVICE);
1742 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1745 dma_unmap_page(priv->dev, txbdp->bufPtr,
1746 txbdp->length, DMA_TO_DEVICE);
1749 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1750 tx_queue->tx_skbuff[i] = NULL;
1752 kfree(tx_queue->tx_skbuff);
1753 tx_queue->tx_skbuff = NULL;
1756 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1758 struct rxbd8 *rxbdp;
1759 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1762 rxbdp = rx_queue->rx_bd_base;
1764 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1765 if (rx_queue->rx_skbuff[i]) {
1766 dma_unmap_single(priv->dev, rxbdp->bufPtr,
1767 priv->rx_buffer_size,
1769 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1770 rx_queue->rx_skbuff[i] = NULL;
1776 kfree(rx_queue->rx_skbuff);
1777 rx_queue->rx_skbuff = NULL;
1780 /* If there are any tx skbs or rx skbs still around, free them.
1781 * Then free tx_skbuff and rx_skbuff
1783 static void free_skb_resources(struct gfar_private *priv)
1785 struct gfar_priv_tx_q *tx_queue = NULL;
1786 struct gfar_priv_rx_q *rx_queue = NULL;
1789 /* Go through all the buffer descriptors and free their data buffers */
1790 for (i = 0; i < priv->num_tx_queues; i++) {
1791 struct netdev_queue *txq;
1793 tx_queue = priv->tx_queue[i];
1794 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1795 if (tx_queue->tx_skbuff)
1796 free_skb_tx_queue(tx_queue);
1797 netdev_tx_reset_queue(txq);
1800 for (i = 0; i < priv->num_rx_queues; i++) {
1801 rx_queue = priv->rx_queue[i];
1802 if (rx_queue->rx_skbuff)
1803 free_skb_rx_queue(rx_queue);
1806 dma_free_coherent(priv->dev,
1807 sizeof(struct txbd8) * priv->total_tx_ring_size +
1808 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1809 priv->tx_queue[0]->tx_bd_base,
1810 priv->tx_queue[0]->tx_bd_dma_base);
1813 void gfar_start(struct net_device *dev)
1815 struct gfar_private *priv = netdev_priv(dev);
1816 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1820 /* Enable Rx and Tx in MACCFG1 */
1821 tempval = gfar_read(®s->maccfg1);
1822 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1823 gfar_write(®s->maccfg1, tempval);
1825 /* Initialize DMACTRL to have WWR and WOP */
1826 tempval = gfar_read(®s->dmactrl);
1827 tempval |= DMACTRL_INIT_SETTINGS;
1828 gfar_write(®s->dmactrl, tempval);
1830 /* Make sure we aren't stopped */
1831 tempval = gfar_read(®s->dmactrl);
1832 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1833 gfar_write(®s->dmactrl, tempval);
1835 for (i = 0; i < priv->num_grps; i++) {
1836 regs = priv->gfargrp[i].regs;
1837 /* Clear THLT/RHLT, so that the DMA starts polling now */
1838 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
1839 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1840 /* Unmask the interrupts we look for */
1841 gfar_write(®s->imask, IMASK_DEFAULT);
1844 dev->trans_start = jiffies; /* prevent tx timeout */
1847 static void gfar_configure_coalescing(struct gfar_private *priv,
1848 unsigned long tx_mask, unsigned long rx_mask)
1850 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1853 if (priv->mode == MQ_MG_MODE) {
1856 baddr = ®s->txic0;
1857 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1858 gfar_write(baddr + i, 0);
1859 if (likely(priv->tx_queue[i]->txcoalescing))
1860 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1863 baddr = ®s->rxic0;
1864 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1865 gfar_write(baddr + i, 0);
1866 if (likely(priv->rx_queue[i]->rxcoalescing))
1867 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1870 /* Backward compatible case -- even if we enable
1871 * multiple queues, there's only single reg to program
1873 gfar_write(®s->txic, 0);
1874 if (likely(priv->tx_queue[0]->txcoalescing))
1875 gfar_write(®s->txic, priv->tx_queue[0]->txic);
1877 gfar_write(®s->rxic, 0);
1878 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1879 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
1883 void gfar_configure_coalescing_all(struct gfar_private *priv)
1885 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1888 static int register_grp_irqs(struct gfar_priv_grp *grp)
1890 struct gfar_private *priv = grp->priv;
1891 struct net_device *dev = priv->ndev;
1894 /* If the device has multiple interrupts, register for
1895 * them. Otherwise, only register for the one
1897 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1898 /* Install our interrupt handlers for Error,
1899 * Transmit, and Receive
1901 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1902 gfar_irq(grp, ER)->name, grp);
1904 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1905 gfar_irq(grp, ER)->irq);
1909 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1910 gfar_irq(grp, TX)->name, grp);
1912 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1913 gfar_irq(grp, TX)->irq);
1916 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1917 gfar_irq(grp, RX)->name, grp);
1919 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1920 gfar_irq(grp, RX)->irq);
1924 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1925 gfar_irq(grp, TX)->name, grp);
1927 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1928 gfar_irq(grp, TX)->irq);
1936 free_irq(gfar_irq(grp, TX)->irq, grp);
1938 free_irq(gfar_irq(grp, ER)->irq, grp);
1944 /* Bring the controller up and running */
1945 int startup_gfar(struct net_device *ndev)
1947 struct gfar_private *priv = netdev_priv(ndev);
1948 struct gfar __iomem *regs = NULL;
1951 for (i = 0; i < priv->num_grps; i++) {
1952 regs= priv->gfargrp[i].regs;
1953 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1956 regs= priv->gfargrp[0].regs;
1957 err = gfar_alloc_skb_resources(ndev);
1961 gfar_init_mac(ndev);
1963 for (i = 0; i < priv->num_grps; i++) {
1964 err = register_grp_irqs(&priv->gfargrp[i]);
1966 for (j = 0; j < i; j++)
1967 free_grp_irqs(&priv->gfargrp[j]);
1972 /* Start the controller */
1975 phy_start(priv->phydev);
1977 gfar_configure_coalescing_all(priv);
1982 free_skb_resources(priv);
1986 /* Called when something needs to use the ethernet device
1987 * Returns 0 for success.
1989 static int gfar_enet_open(struct net_device *dev)
1991 struct gfar_private *priv = netdev_priv(dev);
1996 /* Initialize a bunch of registers */
1997 init_registers(dev);
1999 gfar_set_mac_address(dev);
2001 err = init_phy(dev);
2008 err = startup_gfar(dev);
2014 netif_tx_start_all_queues(dev);
2016 device_set_wakeup_enable(&dev->dev, priv->wol_en);
2021 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2023 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2025 memset(fcb, 0, GMAC_FCB_LEN);
2030 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2033 /* If we're here, it's a IP packet with a TCP or UDP
2034 * payload. We set it to checksum, using a pseudo-header
2037 u8 flags = TXFCB_DEFAULT;
2039 /* Tell the controller what the protocol is
2040 * And provide the already calculated phcs
2042 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2044 fcb->phcs = udp_hdr(skb)->check;
2046 fcb->phcs = tcp_hdr(skb)->check;
2048 /* l3os is the distance between the start of the
2049 * frame (skb->data) and the start of the IP hdr.
2050 * l4os is the distance between the start of the
2051 * l3 hdr and the l4 hdr
2053 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2054 fcb->l4os = skb_network_header_len(skb);
2059 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2061 fcb->flags |= TXFCB_VLN;
2062 fcb->vlctl = vlan_tx_tag_get(skb);
2065 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2066 struct txbd8 *base, int ring_size)
2068 struct txbd8 *new_bd = bdp + stride;
2070 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2073 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2076 return skip_txbd(bdp, 1, base, ring_size);
2079 /* eTSEC12: csum generation not supported for some fcb offsets */
2080 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2081 unsigned long fcb_addr)
2083 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2084 (fcb_addr % 0x20) > 0x18);
2087 /* eTSEC76: csum generation for frames larger than 2500 may
2088 * cause excess delays before start of transmission
2090 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2093 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2097 /* This is called by the kernel when a frame is ready for transmission.
2098 * It is pointed to by the dev->hard_start_xmit function pointer
2100 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2102 struct gfar_private *priv = netdev_priv(dev);
2103 struct gfar_priv_tx_q *tx_queue = NULL;
2104 struct netdev_queue *txq;
2105 struct gfar __iomem *regs = NULL;
2106 struct txfcb *fcb = NULL;
2107 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2110 int do_tstamp, do_csum, do_vlan;
2112 unsigned long flags;
2113 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2115 rq = skb->queue_mapping;
2116 tx_queue = priv->tx_queue[rq];
2117 txq = netdev_get_tx_queue(dev, rq);
2118 base = tx_queue->tx_bd_base;
2119 regs = tx_queue->grp->regs;
2121 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2122 do_vlan = vlan_tx_tag_present(skb);
2123 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2126 if (do_csum || do_vlan)
2127 fcb_len = GMAC_FCB_LEN;
2129 /* check if time stamp should be generated */
2130 if (unlikely(do_tstamp))
2131 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2133 /* make space for additional header when fcb is needed */
2134 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2135 struct sk_buff *skb_new;
2137 skb_new = skb_realloc_headroom(skb, fcb_len);
2139 dev->stats.tx_errors++;
2141 return NETDEV_TX_OK;
2145 skb_set_owner_w(skb_new, skb->sk);
2150 /* total number of fragments in the SKB */
2151 nr_frags = skb_shinfo(skb)->nr_frags;
2153 /* calculate the required number of TxBDs for this skb */
2154 if (unlikely(do_tstamp))
2155 nr_txbds = nr_frags + 2;
2157 nr_txbds = nr_frags + 1;
2159 /* check if there is space to queue this packet */
2160 if (nr_txbds > tx_queue->num_txbdfree) {
2161 /* no space, stop the queue */
2162 netif_tx_stop_queue(txq);
2163 dev->stats.tx_fifo_errors++;
2164 return NETDEV_TX_BUSY;
2167 /* Update transmit stats */
2168 bytes_sent = skb->len;
2169 tx_queue->stats.tx_bytes += bytes_sent;
2170 /* keep Tx bytes on wire for BQL accounting */
2171 GFAR_CB(skb)->bytes_sent = bytes_sent;
2172 tx_queue->stats.tx_packets++;
2174 txbdp = txbdp_start = tx_queue->cur_tx;
2175 lstatus = txbdp->lstatus;
2177 /* Time stamp insertion requires one additional TxBD */
2178 if (unlikely(do_tstamp))
2179 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2180 tx_queue->tx_ring_size);
2182 if (nr_frags == 0) {
2183 if (unlikely(do_tstamp))
2184 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2187 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2189 /* Place the fragment addresses and lengths into the TxBDs */
2190 for (i = 0; i < nr_frags; i++) {
2191 unsigned int frag_len;
2192 /* Point at the next BD, wrapping as needed */
2193 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2195 frag_len = skb_shinfo(skb)->frags[i].size;
2197 lstatus = txbdp->lstatus | frag_len |
2198 BD_LFLAG(TXBD_READY);
2200 /* Handle the last BD specially */
2201 if (i == nr_frags - 1)
2202 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2204 bufaddr = skb_frag_dma_map(priv->dev,
2205 &skb_shinfo(skb)->frags[i],
2210 /* set the TxBD length and buffer pointer */
2211 txbdp->bufPtr = bufaddr;
2212 txbdp->lstatus = lstatus;
2215 lstatus = txbdp_start->lstatus;
2218 /* Add TxPAL between FCB and frame if required */
2219 if (unlikely(do_tstamp)) {
2220 skb_push(skb, GMAC_TXPAL_LEN);
2221 memset(skb->data, 0, GMAC_TXPAL_LEN);
2224 /* Add TxFCB if required */
2226 fcb = gfar_add_fcb(skb);
2227 lstatus |= BD_LFLAG(TXBD_TOE);
2230 /* Set up checksumming */
2232 gfar_tx_checksum(skb, fcb, fcb_len);
2234 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2235 unlikely(gfar_csum_errata_76(priv, skb->len))) {
2236 __skb_pull(skb, GMAC_FCB_LEN);
2237 skb_checksum_help(skb);
2238 if (do_vlan || do_tstamp) {
2239 /* put back a new fcb for vlan/tstamp TOE */
2240 fcb = gfar_add_fcb(skb);
2242 /* Tx TOE not used */
2243 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2250 gfar_tx_vlan(skb, fcb);
2252 /* Setup tx hardware time stamping if requested */
2253 if (unlikely(do_tstamp)) {
2254 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2258 txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
2259 skb_headlen(skb), DMA_TO_DEVICE);
2261 /* If time stamping is requested one additional TxBD must be set up. The
2262 * first TxBD points to the FCB and must have a data length of
2263 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2264 * the full frame length.
2266 if (unlikely(do_tstamp)) {
2267 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len;
2268 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2269 (skb_headlen(skb) - fcb_len);
2270 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2272 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2275 netdev_tx_sent_queue(txq, bytes_sent);
2277 /* We can work in parallel with gfar_clean_tx_ring(), except
2278 * when modifying num_txbdfree. Note that we didn't grab the lock
2279 * when we were reading the num_txbdfree and checking for available
2280 * space, that's because outside of this function it can only grow,
2281 * and once we've got needed space, it cannot suddenly disappear.
2283 * The lock also protects us from gfar_error(), which can modify
2284 * regs->tstat and thus retrigger the transfers, which is why we
2285 * also must grab the lock before setting ready bit for the first
2286 * to be transmitted BD.
2288 spin_lock_irqsave(&tx_queue->txlock, flags);
2290 /* The powerpc-specific eieio() is used, as wmb() has too strong
2291 * semantics (it requires synchronization between cacheable and
2292 * uncacheable mappings, which eieio doesn't provide and which we
2293 * don't need), thus requiring a more expensive sync instruction. At
2294 * some point, the set of architecture-independent barrier functions
2295 * should be expanded to include weaker barriers.
2299 txbdp_start->lstatus = lstatus;
2301 eieio(); /* force lstatus write before tx_skbuff */
2303 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2305 /* Update the current skb pointer to the next entry we will use
2306 * (wrapping if necessary)
2308 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2309 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2311 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2313 /* reduce TxBD free count */
2314 tx_queue->num_txbdfree -= (nr_txbds);
2316 /* If the next BD still needs to be cleaned up, then the bds
2317 * are full. We need to tell the kernel to stop sending us stuff.
2319 if (!tx_queue->num_txbdfree) {
2320 netif_tx_stop_queue(txq);
2322 dev->stats.tx_fifo_errors++;
2325 /* Tell the DMA to go go go */
2326 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2329 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2331 return NETDEV_TX_OK;
2334 /* Stops the kernel queue, and halts the controller */
2335 static int gfar_close(struct net_device *dev)
2337 struct gfar_private *priv = netdev_priv(dev);
2341 cancel_work_sync(&priv->reset_task);
2344 /* Disconnect from the PHY */
2345 phy_disconnect(priv->phydev);
2346 priv->phydev = NULL;
2348 netif_tx_stop_all_queues(dev);
2353 /* Changes the mac address if the controller is not running. */
2354 static int gfar_set_mac_address(struct net_device *dev)
2356 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2361 /* Check if rx parser should be activated */
2362 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2364 struct gfar __iomem *regs;
2367 regs = priv->gfargrp[0].regs;
2369 tempval = gfar_read(®s->rctrl);
2370 /* If parse is no longer required, then disable parser */
2371 if (tempval & RCTRL_REQ_PARSER) {
2372 tempval |= RCTRL_PRSDEP_INIT;
2373 priv->uses_rxfcb = 1;
2375 tempval &= ~RCTRL_PRSDEP_INIT;
2376 priv->uses_rxfcb = 0;
2378 gfar_write(®s->rctrl, tempval);
2381 /* Enables and disables VLAN insertion/extraction */
2382 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2384 struct gfar_private *priv = netdev_priv(dev);
2385 struct gfar __iomem *regs = NULL;
2386 unsigned long flags;
2389 regs = priv->gfargrp[0].regs;
2390 local_irq_save(flags);
2393 if (features & NETIF_F_HW_VLAN_CTAG_TX) {
2394 /* Enable VLAN tag insertion */
2395 tempval = gfar_read(®s->tctrl);
2396 tempval |= TCTRL_VLINS;
2397 gfar_write(®s->tctrl, tempval);
2399 /* Disable VLAN tag insertion */
2400 tempval = gfar_read(®s->tctrl);
2401 tempval &= ~TCTRL_VLINS;
2402 gfar_write(®s->tctrl, tempval);
2405 if (features & NETIF_F_HW_VLAN_CTAG_RX) {
2406 /* Enable VLAN tag extraction */
2407 tempval = gfar_read(®s->rctrl);
2408 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2409 gfar_write(®s->rctrl, tempval);
2410 priv->uses_rxfcb = 1;
2412 /* Disable VLAN tag extraction */
2413 tempval = gfar_read(®s->rctrl);
2414 tempval &= ~RCTRL_VLEX;
2415 gfar_write(®s->rctrl, tempval);
2417 gfar_check_rx_parser_mode(priv);
2420 gfar_change_mtu(dev, dev->mtu);
2423 local_irq_restore(flags);
2426 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2428 int tempsize, tempval;
2429 struct gfar_private *priv = netdev_priv(dev);
2430 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2431 int oldsize = priv->rx_buffer_size;
2432 int frame_size = new_mtu + ETH_HLEN;
2434 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2435 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2439 if (priv->uses_rxfcb)
2440 frame_size += GMAC_FCB_LEN;
2442 frame_size += priv->padding;
2444 tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2445 INCREMENTAL_BUFFER_SIZE;
2447 /* Only stop and start the controller if it isn't already
2448 * stopped, and we changed something
2450 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2453 priv->rx_buffer_size = tempsize;
2457 gfar_write(®s->mrblr, priv->rx_buffer_size);
2458 gfar_write(®s->maxfrm, priv->rx_buffer_size);
2460 /* If the mtu is larger than the max size for standard
2461 * ethernet frames (ie, a jumbo frame), then set maccfg2
2462 * to allow huge frames, and to check the length
2464 tempval = gfar_read(®s->maccfg2);
2466 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2467 gfar_has_errata(priv, GFAR_ERRATA_74))
2468 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2470 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2472 gfar_write(®s->maccfg2, tempval);
2474 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2480 /* gfar_reset_task gets scheduled when a packet has not been
2481 * transmitted after a set amount of time.
2482 * For now, assume that clearing out all the structures, and
2483 * starting over will fix the problem.
2485 static void gfar_reset_task(struct work_struct *work)
2487 struct gfar_private *priv = container_of(work, struct gfar_private,
2489 struct net_device *dev = priv->ndev;
2491 if (dev->flags & IFF_UP) {
2492 netif_tx_stop_all_queues(dev);
2495 netif_tx_start_all_queues(dev);
2498 netif_tx_schedule_all(dev);
2501 static void gfar_timeout(struct net_device *dev)
2503 struct gfar_private *priv = netdev_priv(dev);
2505 dev->stats.tx_errors++;
2506 schedule_work(&priv->reset_task);
2509 static void gfar_align_skb(struct sk_buff *skb)
2511 /* We need the data buffer to be aligned properly. We will reserve
2512 * as many bytes as needed to align the data properly
2514 skb_reserve(skb, RXBUF_ALIGNMENT -
2515 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2518 /* Interrupt Handler for Transmit complete */
2519 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2521 struct net_device *dev = tx_queue->dev;
2522 struct netdev_queue *txq;
2523 struct gfar_private *priv = netdev_priv(dev);
2524 struct txbd8 *bdp, *next = NULL;
2525 struct txbd8 *lbdp = NULL;
2526 struct txbd8 *base = tx_queue->tx_bd_base;
2527 struct sk_buff *skb;
2529 int tx_ring_size = tx_queue->tx_ring_size;
2530 int frags = 0, nr_txbds = 0;
2533 int tqi = tx_queue->qindex;
2534 unsigned int bytes_sent = 0;
2538 txq = netdev_get_tx_queue(dev, tqi);
2539 bdp = tx_queue->dirty_tx;
2540 skb_dirtytx = tx_queue->skb_dirtytx;
2542 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2543 unsigned long flags;
2545 frags = skb_shinfo(skb)->nr_frags;
2547 /* When time stamping, one additional TxBD must be freed.
2548 * Also, we need to dma_unmap_single() the TxPAL.
2550 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2551 nr_txbds = frags + 2;
2553 nr_txbds = frags + 1;
2555 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2557 lstatus = lbdp->lstatus;
2559 /* Only clean completed frames */
2560 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2561 (lstatus & BD_LENGTH_MASK))
2564 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2565 next = next_txbd(bdp, base, tx_ring_size);
2566 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2568 buflen = bdp->length;
2570 dma_unmap_single(priv->dev, bdp->bufPtr,
2571 buflen, DMA_TO_DEVICE);
2573 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2574 struct skb_shared_hwtstamps shhwtstamps;
2575 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2577 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2578 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2579 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2580 skb_tstamp_tx(skb, &shhwtstamps);
2581 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2585 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2586 bdp = next_txbd(bdp, base, tx_ring_size);
2588 for (i = 0; i < frags; i++) {
2589 dma_unmap_page(priv->dev, bdp->bufPtr,
2590 bdp->length, DMA_TO_DEVICE);
2591 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2592 bdp = next_txbd(bdp, base, tx_ring_size);
2595 bytes_sent += GFAR_CB(skb)->bytes_sent;
2597 dev_kfree_skb_any(skb);
2599 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2601 skb_dirtytx = (skb_dirtytx + 1) &
2602 TX_RING_MOD_MASK(tx_ring_size);
2605 spin_lock_irqsave(&tx_queue->txlock, flags);
2606 tx_queue->num_txbdfree += nr_txbds;
2607 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2610 /* If we freed a buffer, we can restart transmission, if necessary */
2611 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2612 netif_wake_subqueue(dev, tqi);
2614 /* Update dirty indicators */
2615 tx_queue->skb_dirtytx = skb_dirtytx;
2616 tx_queue->dirty_tx = bdp;
2618 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2621 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2623 unsigned long flags;
2625 spin_lock_irqsave(&gfargrp->grplock, flags);
2626 if (napi_schedule_prep(&gfargrp->napi)) {
2627 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2628 __napi_schedule(&gfargrp->napi);
2630 /* Clear IEVENT, so interrupts aren't called again
2631 * because of the packets that have already arrived.
2633 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2635 spin_unlock_irqrestore(&gfargrp->grplock, flags);
2639 /* Interrupt Handler for Transmit complete */
2640 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2642 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2646 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2647 struct sk_buff *skb)
2649 struct net_device *dev = rx_queue->dev;
2650 struct gfar_private *priv = netdev_priv(dev);
2653 buf = dma_map_single(priv->dev, skb->data,
2654 priv->rx_buffer_size, DMA_FROM_DEVICE);
2655 gfar_init_rxbdp(rx_queue, bdp, buf);
2658 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2660 struct gfar_private *priv = netdev_priv(dev);
2661 struct sk_buff *skb;
2663 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2667 gfar_align_skb(skb);
2672 struct sk_buff *gfar_new_skb(struct net_device *dev)
2674 return gfar_alloc_skb(dev);
2677 static inline void count_errors(unsigned short status, struct net_device *dev)
2679 struct gfar_private *priv = netdev_priv(dev);
2680 struct net_device_stats *stats = &dev->stats;
2681 struct gfar_extra_stats *estats = &priv->extra_stats;
2683 /* If the packet was truncated, none of the other errors matter */
2684 if (status & RXBD_TRUNCATED) {
2685 stats->rx_length_errors++;
2687 atomic64_inc(&estats->rx_trunc);
2691 /* Count the errors, if there were any */
2692 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2693 stats->rx_length_errors++;
2695 if (status & RXBD_LARGE)
2696 atomic64_inc(&estats->rx_large);
2698 atomic64_inc(&estats->rx_short);
2700 if (status & RXBD_NONOCTET) {
2701 stats->rx_frame_errors++;
2702 atomic64_inc(&estats->rx_nonoctet);
2704 if (status & RXBD_CRCERR) {
2705 atomic64_inc(&estats->rx_crcerr);
2706 stats->rx_crc_errors++;
2708 if (status & RXBD_OVERRUN) {
2709 atomic64_inc(&estats->rx_overrun);
2710 stats->rx_crc_errors++;
2714 irqreturn_t gfar_receive(int irq, void *grp_id)
2716 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2720 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2722 /* If valid headers were found, and valid sums
2723 * were verified, then we tell the kernel that no
2724 * checksumming is necessary. Otherwise, it is [FIXME]
2726 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2727 skb->ip_summed = CHECKSUM_UNNECESSARY;
2729 skb_checksum_none_assert(skb);
2733 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2734 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2735 int amount_pull, struct napi_struct *napi)
2737 struct gfar_private *priv = netdev_priv(dev);
2738 struct rxfcb *fcb = NULL;
2740 /* fcb is at the beginning if exists */
2741 fcb = (struct rxfcb *)skb->data;
2743 /* Remove the FCB from the skb
2744 * Remove the padded bytes, if there are any
2747 skb_record_rx_queue(skb, fcb->rq);
2748 skb_pull(skb, amount_pull);
2751 /* Get receive timestamp from the skb */
2752 if (priv->hwts_rx_en) {
2753 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2754 u64 *ns = (u64 *) skb->data;
2756 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2757 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2761 skb_pull(skb, priv->padding);
2763 if (dev->features & NETIF_F_RXCSUM)
2764 gfar_rx_checksum(skb, fcb);
2766 /* Tell the skb what kind of packet this is */
2767 skb->protocol = eth_type_trans(skb, dev);
2769 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2770 * Even if vlan rx accel is disabled, on some chips
2771 * RXFCB_VLN is pseudo randomly set.
2773 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2774 fcb->flags & RXFCB_VLN)
2775 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl);
2777 /* Send the packet up the stack */
2778 napi_gro_receive(napi, skb);
2782 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2783 * until the budget/quota has been reached. Returns the number
2786 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2788 struct net_device *dev = rx_queue->dev;
2789 struct rxbd8 *bdp, *base;
2790 struct sk_buff *skb;
2794 struct gfar_private *priv = netdev_priv(dev);
2796 /* Get the first full descriptor */
2797 bdp = rx_queue->cur_rx;
2798 base = rx_queue->rx_bd_base;
2800 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2802 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2803 struct sk_buff *newskb;
2807 /* Add another skb for the future */
2808 newskb = gfar_new_skb(dev);
2810 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2812 dma_unmap_single(priv->dev, bdp->bufPtr,
2813 priv->rx_buffer_size, DMA_FROM_DEVICE);
2815 if (unlikely(!(bdp->status & RXBD_ERR) &&
2816 bdp->length > priv->rx_buffer_size))
2817 bdp->status = RXBD_LARGE;
2819 /* We drop the frame if we failed to allocate a new buffer */
2820 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2821 bdp->status & RXBD_ERR)) {
2822 count_errors(bdp->status, dev);
2824 if (unlikely(!newskb))
2829 /* Increment the number of packets */
2830 rx_queue->stats.rx_packets++;
2834 pkt_len = bdp->length - ETH_FCS_LEN;
2835 /* Remove the FCS from the packet length */
2836 skb_put(skb, pkt_len);
2837 rx_queue->stats.rx_bytes += pkt_len;
2838 skb_record_rx_queue(skb, rx_queue->qindex);
2839 gfar_process_frame(dev, skb, amount_pull,
2840 &rx_queue->grp->napi);
2843 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2844 rx_queue->stats.rx_dropped++;
2845 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2850 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2852 /* Setup the new bdp */
2853 gfar_new_rxbdp(rx_queue, bdp, newskb);
2855 /* Update to the next pointer */
2856 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2858 /* update to point at the next skb */
2859 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2860 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2863 /* Update the current rxbd pointer to be the next one */
2864 rx_queue->cur_rx = bdp;
2869 static int gfar_poll_sq(struct napi_struct *napi, int budget)
2871 struct gfar_priv_grp *gfargrp =
2872 container_of(napi, struct gfar_priv_grp, napi);
2873 struct gfar __iomem *regs = gfargrp->regs;
2874 struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0];
2875 struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0];
2878 /* Clear IEVENT, so interrupts aren't called again
2879 * because of the packets that have already arrived
2881 gfar_write(®s->ievent, IEVENT_RTX_MASK);
2883 /* run Tx cleanup to completion */
2884 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2885 gfar_clean_tx_ring(tx_queue);
2887 work_done = gfar_clean_rx_ring(rx_queue, budget);
2889 if (work_done < budget) {
2890 napi_complete(napi);
2891 /* Clear the halt bit in RSTAT */
2892 gfar_write(®s->rstat, gfargrp->rstat);
2894 gfar_write(®s->imask, IMASK_DEFAULT);
2896 /* If we are coalescing interrupts, update the timer
2897 * Otherwise, clear it
2899 gfar_write(®s->txic, 0);
2900 if (likely(tx_queue->txcoalescing))
2901 gfar_write(®s->txic, tx_queue->txic);
2903 gfar_write(®s->rxic, 0);
2904 if (unlikely(rx_queue->rxcoalescing))
2905 gfar_write(®s->rxic, rx_queue->rxic);
2911 static int gfar_poll(struct napi_struct *napi, int budget)
2913 struct gfar_priv_grp *gfargrp =
2914 container_of(napi, struct gfar_priv_grp, napi);
2915 struct gfar_private *priv = gfargrp->priv;
2916 struct gfar __iomem *regs = gfargrp->regs;
2917 struct gfar_priv_tx_q *tx_queue = NULL;
2918 struct gfar_priv_rx_q *rx_queue = NULL;
2919 int work_done = 0, work_done_per_q = 0;
2920 int i, budget_per_q = 0;
2922 unsigned long rstat_rxf;
2925 /* Clear IEVENT, so interrupts aren't called again
2926 * because of the packets that have already arrived
2928 gfar_write(®s->ievent, IEVENT_RTX_MASK);
2930 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK;
2932 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2934 budget_per_q = budget/num_act_queues;
2938 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2939 tx_queue = priv->tx_queue[i];
2940 /* run Tx cleanup to completion */
2941 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2942 gfar_clean_tx_ring(tx_queue);
2947 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2948 /* skip queue if not active */
2949 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2952 rx_queue = priv->rx_queue[i];
2954 gfar_clean_rx_ring(rx_queue, budget_per_q);
2955 work_done += work_done_per_q;
2957 /* finished processing this queue */
2958 if (work_done_per_q < budget_per_q) {
2959 /* clear active queue hw indication */
2960 gfar_write(®s->rstat,
2961 RSTAT_CLEAR_RXF0 >> i);
2962 rstat_rxf &= ~(RSTAT_CLEAR_RXF0 >> i);
2965 if (!num_act_queues)
2967 /* recompute budget per Rx queue */
2969 (budget - work_done) / num_act_queues;
2973 if (work_done >= budget)
2976 if (!num_act_queues && !has_tx_work) {
2978 napi_complete(napi);
2980 /* Clear the halt bit in RSTAT */
2981 gfar_write(®s->rstat, gfargrp->rstat);
2983 gfar_write(®s->imask, IMASK_DEFAULT);
2985 /* If we are coalescing interrupts, update the timer
2986 * Otherwise, clear it
2988 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2989 gfargrp->tx_bit_map);
2997 #ifdef CONFIG_NET_POLL_CONTROLLER
2998 /* Polling 'interrupt' - used by things like netconsole to send skbs
2999 * without having to re-enable interrupts. It's not called while
3000 * the interrupt routine is executing.
3002 static void gfar_netpoll(struct net_device *dev)
3004 struct gfar_private *priv = netdev_priv(dev);
3007 /* If the device has multiple interrupts, run tx/rx */
3008 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3009 for (i = 0; i < priv->num_grps; i++) {
3010 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3012 disable_irq(gfar_irq(grp, TX)->irq);
3013 disable_irq(gfar_irq(grp, RX)->irq);
3014 disable_irq(gfar_irq(grp, ER)->irq);
3015 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3016 enable_irq(gfar_irq(grp, ER)->irq);
3017 enable_irq(gfar_irq(grp, RX)->irq);
3018 enable_irq(gfar_irq(grp, TX)->irq);
3021 for (i = 0; i < priv->num_grps; i++) {
3022 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3024 disable_irq(gfar_irq(grp, TX)->irq);
3025 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3026 enable_irq(gfar_irq(grp, TX)->irq);
3032 /* The interrupt handler for devices with one interrupt */
3033 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3035 struct gfar_priv_grp *gfargrp = grp_id;
3037 /* Save ievent for future reference */
3038 u32 events = gfar_read(&gfargrp->regs->ievent);
3040 /* Check for reception */
3041 if (events & IEVENT_RX_MASK)
3042 gfar_receive(irq, grp_id);
3044 /* Check for transmit completion */
3045 if (events & IEVENT_TX_MASK)
3046 gfar_transmit(irq, grp_id);
3048 /* Check for errors */
3049 if (events & IEVENT_ERR_MASK)
3050 gfar_error(irq, grp_id);
3055 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3057 struct phy_device *phydev = priv->phydev;
3060 if (!phydev->duplex)
3063 if (!priv->pause_aneg_en) {
3064 if (priv->tx_pause_en)
3065 val |= MACCFG1_TX_FLOW;
3066 if (priv->rx_pause_en)
3067 val |= MACCFG1_RX_FLOW;
3069 u16 lcl_adv, rmt_adv;
3071 /* get link partner capabilities */
3074 rmt_adv = LPA_PAUSE_CAP;
3075 if (phydev->asym_pause)
3076 rmt_adv |= LPA_PAUSE_ASYM;
3078 lcl_adv = mii_advertise_flowctrl(phydev->advertising);
3080 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3081 if (flowctrl & FLOW_CTRL_TX)
3082 val |= MACCFG1_TX_FLOW;
3083 if (flowctrl & FLOW_CTRL_RX)
3084 val |= MACCFG1_RX_FLOW;
3090 /* Called every time the controller might need to be made
3091 * aware of new link state. The PHY code conveys this
3092 * information through variables in the phydev structure, and this
3093 * function converts those variables into the appropriate
3094 * register values, and can bring down the device if needed.
3096 static void adjust_link(struct net_device *dev)
3098 struct gfar_private *priv = netdev_priv(dev);
3099 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3100 unsigned long flags;
3101 struct phy_device *phydev = priv->phydev;
3104 local_irq_save(flags);
3108 u32 tempval1 = gfar_read(®s->maccfg1);
3109 u32 tempval = gfar_read(®s->maccfg2);
3110 u32 ecntrl = gfar_read(®s->ecntrl);
3112 /* Now we make sure that we can be in full duplex mode.
3113 * If not, we operate in half-duplex mode.
3115 if (phydev->duplex != priv->oldduplex) {
3117 if (!(phydev->duplex))
3118 tempval &= ~(MACCFG2_FULL_DUPLEX);
3120 tempval |= MACCFG2_FULL_DUPLEX;
3122 priv->oldduplex = phydev->duplex;
3125 if (phydev->speed != priv->oldspeed) {
3127 switch (phydev->speed) {
3130 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3132 ecntrl &= ~(ECNTRL_R100);
3137 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3139 /* Reduced mode distinguishes
3140 * between 10 and 100
3142 if (phydev->speed == SPEED_100)
3143 ecntrl |= ECNTRL_R100;
3145 ecntrl &= ~(ECNTRL_R100);
3148 netif_warn(priv, link, dev,
3149 "Ack! Speed (%d) is not 10/100/1000!\n",
3154 priv->oldspeed = phydev->speed;
3157 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3158 tempval1 |= gfar_get_flowctrl_cfg(priv);
3160 gfar_write(®s->maccfg1, tempval1);
3161 gfar_write(®s->maccfg2, tempval);
3162 gfar_write(®s->ecntrl, ecntrl);
3164 if (!priv->oldlink) {
3168 } else if (priv->oldlink) {
3172 priv->oldduplex = -1;
3175 if (new_state && netif_msg_link(priv))
3176 phy_print_status(phydev);
3178 local_irq_restore(flags);
3181 /* Update the hash table based on the current list of multicast
3182 * addresses we subscribe to. Also, change the promiscuity of
3183 * the device based on the flags (this function is called
3184 * whenever dev->flags is changed
3186 static void gfar_set_multi(struct net_device *dev)
3188 struct netdev_hw_addr *ha;
3189 struct gfar_private *priv = netdev_priv(dev);
3190 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3193 if (dev->flags & IFF_PROMISC) {
3194 /* Set RCTRL to PROM */
3195 tempval = gfar_read(®s->rctrl);
3196 tempval |= RCTRL_PROM;
3197 gfar_write(®s->rctrl, tempval);
3199 /* Set RCTRL to not PROM */
3200 tempval = gfar_read(®s->rctrl);
3201 tempval &= ~(RCTRL_PROM);
3202 gfar_write(®s->rctrl, tempval);
3205 if (dev->flags & IFF_ALLMULTI) {
3206 /* Set the hash to rx all multicast frames */
3207 gfar_write(®s->igaddr0, 0xffffffff);
3208 gfar_write(®s->igaddr1, 0xffffffff);
3209 gfar_write(®s->igaddr2, 0xffffffff);
3210 gfar_write(®s->igaddr3, 0xffffffff);
3211 gfar_write(®s->igaddr4, 0xffffffff);
3212 gfar_write(®s->igaddr5, 0xffffffff);
3213 gfar_write(®s->igaddr6, 0xffffffff);
3214 gfar_write(®s->igaddr7, 0xffffffff);
3215 gfar_write(®s->gaddr0, 0xffffffff);
3216 gfar_write(®s->gaddr1, 0xffffffff);
3217 gfar_write(®s->gaddr2, 0xffffffff);
3218 gfar_write(®s->gaddr3, 0xffffffff);
3219 gfar_write(®s->gaddr4, 0xffffffff);
3220 gfar_write(®s->gaddr5, 0xffffffff);
3221 gfar_write(®s->gaddr6, 0xffffffff);
3222 gfar_write(®s->gaddr7, 0xffffffff);
3227 /* zero out the hash */
3228 gfar_write(®s->igaddr0, 0x0);
3229 gfar_write(®s->igaddr1, 0x0);
3230 gfar_write(®s->igaddr2, 0x0);
3231 gfar_write(®s->igaddr3, 0x0);
3232 gfar_write(®s->igaddr4, 0x0);
3233 gfar_write(®s->igaddr5, 0x0);
3234 gfar_write(®s->igaddr6, 0x0);
3235 gfar_write(®s->igaddr7, 0x0);
3236 gfar_write(®s->gaddr0, 0x0);
3237 gfar_write(®s->gaddr1, 0x0);
3238 gfar_write(®s->gaddr2, 0x0);
3239 gfar_write(®s->gaddr3, 0x0);
3240 gfar_write(®s->gaddr4, 0x0);
3241 gfar_write(®s->gaddr5, 0x0);
3242 gfar_write(®s->gaddr6, 0x0);
3243 gfar_write(®s->gaddr7, 0x0);
3245 /* If we have extended hash tables, we need to
3246 * clear the exact match registers to prepare for
3249 if (priv->extended_hash) {
3250 em_num = GFAR_EM_NUM + 1;
3251 gfar_clear_exact_match(dev);
3258 if (netdev_mc_empty(dev))
3261 /* Parse the list, and set the appropriate bits */
3262 netdev_for_each_mc_addr(ha, dev) {
3264 gfar_set_mac_for_addr(dev, idx, ha->addr);
3267 gfar_set_hash_for_addr(dev, ha->addr);
3273 /* Clears each of the exact match registers to zero, so they
3274 * don't interfere with normal reception
3276 static void gfar_clear_exact_match(struct net_device *dev)
3279 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3281 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3282 gfar_set_mac_for_addr(dev, idx, zero_arr);
3285 /* Set the appropriate hash bit for the given addr */
3286 /* The algorithm works like so:
3287 * 1) Take the Destination Address (ie the multicast address), and
3288 * do a CRC on it (little endian), and reverse the bits of the
3290 * 2) Use the 8 most significant bits as a hash into a 256-entry
3291 * table. The table is controlled through 8 32-bit registers:
3292 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3293 * gaddr7. This means that the 3 most significant bits in the
3294 * hash index which gaddr register to use, and the 5 other bits
3295 * indicate which bit (assuming an IBM numbering scheme, which
3296 * for PowerPC (tm) is usually the case) in the register holds
3299 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3302 struct gfar_private *priv = netdev_priv(dev);
3303 u32 result = ether_crc(ETH_ALEN, addr);
3304 int width = priv->hash_width;
3305 u8 whichbit = (result >> (32 - width)) & 0x1f;
3306 u8 whichreg = result >> (32 - width + 5);
3307 u32 value = (1 << (31-whichbit));
3309 tempval = gfar_read(priv->hash_regs[whichreg]);
3311 gfar_write(priv->hash_regs[whichreg], tempval);
3315 /* There are multiple MAC Address register pairs on some controllers
3316 * This function sets the numth pair to a given address
3318 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3321 struct gfar_private *priv = netdev_priv(dev);
3322 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3324 char tmpbuf[ETH_ALEN];
3326 u32 __iomem *macptr = ®s->macstnaddr1;
3330 /* Now copy it into the mac registers backwards, cuz
3331 * little endian is silly
3333 for (idx = 0; idx < ETH_ALEN; idx++)
3334 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3336 gfar_write(macptr, *((u32 *) (tmpbuf)));
3338 tempval = *((u32 *) (tmpbuf + 4));
3340 gfar_write(macptr+1, tempval);
3343 /* GFAR error interrupt handler */
3344 static irqreturn_t gfar_error(int irq, void *grp_id)
3346 struct gfar_priv_grp *gfargrp = grp_id;
3347 struct gfar __iomem *regs = gfargrp->regs;
3348 struct gfar_private *priv= gfargrp->priv;
3349 struct net_device *dev = priv->ndev;
3351 /* Save ievent for future reference */
3352 u32 events = gfar_read(®s->ievent);
3355 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
3357 /* Magic Packet is not an error. */
3358 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3359 (events & IEVENT_MAG))
3360 events &= ~IEVENT_MAG;
3363 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3365 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3366 events, gfar_read(®s->imask));
3368 /* Update the error counters */
3369 if (events & IEVENT_TXE) {
3370 dev->stats.tx_errors++;
3372 if (events & IEVENT_LC)
3373 dev->stats.tx_window_errors++;
3374 if (events & IEVENT_CRL)
3375 dev->stats.tx_aborted_errors++;
3376 if (events & IEVENT_XFUN) {
3377 unsigned long flags;
3379 netif_dbg(priv, tx_err, dev,
3380 "TX FIFO underrun, packet dropped\n");
3381 dev->stats.tx_dropped++;
3382 atomic64_inc(&priv->extra_stats.tx_underrun);
3384 local_irq_save(flags);
3387 /* Reactivate the Tx Queues */
3388 gfar_write(®s->tstat, gfargrp->tstat);
3391 local_irq_restore(flags);
3393 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3395 if (events & IEVENT_BSY) {
3396 dev->stats.rx_errors++;
3397 atomic64_inc(&priv->extra_stats.rx_bsy);
3399 gfar_receive(irq, grp_id);
3401 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3402 gfar_read(®s->rstat));
3404 if (events & IEVENT_BABR) {
3405 dev->stats.rx_errors++;
3406 atomic64_inc(&priv->extra_stats.rx_babr);
3408 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3410 if (events & IEVENT_EBERR) {
3411 atomic64_inc(&priv->extra_stats.eberr);
3412 netif_dbg(priv, rx_err, dev, "bus error\n");
3414 if (events & IEVENT_RXC)
3415 netif_dbg(priv, rx_status, dev, "control frame\n");
3417 if (events & IEVENT_BABT) {
3418 atomic64_inc(&priv->extra_stats.tx_babt);
3419 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3424 static struct of_device_id gfar_match[] =
3428 .compatible = "gianfar",
3431 .compatible = "fsl,etsec2",
3435 MODULE_DEVICE_TABLE(of, gfar_match);
3437 /* Structure for a device driver */
3438 static struct platform_driver gfar_driver = {
3440 .name = "fsl-gianfar",
3441 .owner = THIS_MODULE,
3443 .of_match_table = gfar_match,
3445 .probe = gfar_probe,
3446 .remove = gfar_remove,
3449 module_platform_driver(gfar_driver);