drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/of_mdio.h>
  82 #include <linux/of_platform.h>
  83 #include <linux/ip.h>
  84 #include <linux/tcp.h>
  85 #include <linux/udp.h>
  86 #include <linux/in.h>
  87 #include <linux/net_tstamp.h>
  88
  89 #include <asm/io.h>
  90 #include <asm/reg.h>
  91 #include <asm/irq.h>
  92 #include <asm/uaccess.h>
  93 #include <linux/module.h>
  94 #include <linux/dma-mapping.h>
  95 #include <linux/crc32.h>
  96 #include <linux/mii.h>
  97 #include <linux/phy.h>
  98 #include <linux/phy_fixed.h>
  99 #include <linux/of.h>
 100 #include <linux/of_net.h>
 101
 102 #include "gianfar.h"
 103
 104 #define TX_TIMEOUT      (1*HZ)
 105
 106 const char gfar_driver_version[] = "1.3";
 107
 108 static int gfar_enet_open(struct net_device *dev);
 109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 110 static void gfar_reset_task(struct work_struct *work);
 111 static void gfar_timeout(struct net_device *dev);
 112 static int gfar_close(struct net_device *dev);
 113 struct sk_buff *gfar_new_skb(struct net_device *dev);
 114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 115                            struct sk_buff *skb);
 116 static int gfar_set_mac_address(struct net_device *dev);
 117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 118 static irqreturn_t gfar_error(int irq, void *dev_id);
 119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 121 static void adjust_link(struct net_device *dev);
 122 static void init_registers(struct net_device *dev);
 123 static int init_phy(struct net_device *dev);
 124 static int gfar_probe(struct platform_device *ofdev);
 125 static int gfar_remove(struct platform_device *ofdev);
 126 static void free_skb_resources(struct gfar_private *priv);
 127 static void gfar_set_multi(struct net_device *dev);
 128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 129 static void gfar_configure_serdes(struct net_device *dev);
 130 static int gfar_poll(struct napi_struct *napi, int budget);
 131 #ifdef CONFIG_NET_POLL_CONTROLLER
 132 static void gfar_netpoll(struct net_device *dev);
 133 #endif
 134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 136 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 137                                int amount_pull, struct napi_struct *napi);
 138 void gfar_halt(struct net_device *dev);
 139 static void gfar_halt_nodisable(struct net_device *dev);
 140 void gfar_start(struct net_device *dev);
 141 static void gfar_clear_exact_match(struct net_device *dev);
 142 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 143                                   const u8 *addr);
 144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 145
 146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 148 MODULE_LICENSE("GPL");
 149
 150 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 151                             dma_addr_t buf)
 152 {
 153         u32 lstatus;
 154
 155         bdp->bufPtr = buf;
 156
 157         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 158         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 159                 lstatus |= BD_LFLAG(RXBD_WRAP);
 160
 161         eieio();
 162
 163         bdp->lstatus = lstatus;
 164 }
 165
 166 static int gfar_init_bds(struct net_device *ndev)
 167 {
 168         struct gfar_private *priv = netdev_priv(ndev);
 169         struct gfar_priv_tx_q *tx_queue = NULL;
 170         struct gfar_priv_rx_q *rx_queue = NULL;
 171         struct txbd8 *txbdp;
 172         struct rxbd8 *rxbdp;
 173         int i, j;
 174
 175         for (i = 0; i < priv->num_tx_queues; i++) {
 176                 tx_queue = priv->tx_queue[i];
 177                 /* Initialize some variables in our dev structure */
 178                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 179                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 180                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 181                 tx_queue->skb_curtx = 0;
 182                 tx_queue->skb_dirtytx = 0;
 183
 184                 /* Initialize Transmit Descriptor Ring */
 185                 txbdp = tx_queue->tx_bd_base;
 186                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 187                         txbdp->lstatus = 0;
 188                         txbdp->bufPtr = 0;
 189                         txbdp++;
 190                 }
 191
 192                 /* Set the last descriptor in the ring to indicate wrap */
 193                 txbdp--;
 194                 txbdp->status |= TXBD_WRAP;
 195         }
 196
 197         for (i = 0; i < priv->num_rx_queues; i++) {
 198                 rx_queue = priv->rx_queue[i];
 199                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 200                 rx_queue->skb_currx = 0;
 201                 rxbdp = rx_queue->rx_bd_base;
 202
 203                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 204                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 205
 206                         if (skb) {
 207                                 gfar_init_rxbdp(rx_queue, rxbdp,
 208                                                 rxbdp->bufPtr);
 209                         } else {
 210                                 skb = gfar_new_skb(ndev);
 211                                 if (!skb) {
 212                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 213                                         return -ENOMEM;
 214                                 }
 215                                 rx_queue->rx_skbuff[j] = skb;
 216
 217                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 218                         }
 219
 220                         rxbdp++;
 221                 }
 222
 223         }
 224
 225         return 0;
 226 }
 227
 228 static int gfar_alloc_skb_resources(struct net_device *ndev)
 229 {
 230         void *vaddr;
 231         dma_addr_t addr;
 232         int i, j, k;
 233         struct gfar_private *priv = netdev_priv(ndev);
 234         struct device *dev = priv->dev;
 235         struct gfar_priv_tx_q *tx_queue = NULL;
 236         struct gfar_priv_rx_q *rx_queue = NULL;
 237
 238         priv->total_tx_ring_size = 0;
 239         for (i = 0; i < priv->num_tx_queues; i++)
 240                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 241
 242         priv->total_rx_ring_size = 0;
 243         for (i = 0; i < priv->num_rx_queues; i++)
 244                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 245
 246         /* Allocate memory for the buffer descriptors */
 247         vaddr = dma_alloc_coherent(dev,
 248                         sizeof(struct txbd8) * priv->total_tx_ring_size +
 249                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
 250                         &addr, GFP_KERNEL);
 251         if (!vaddr) {
 252                 netif_err(priv, ifup, ndev,
 253                           "Could not allocate buffer descriptors!\n");
 254                 return -ENOMEM;
 255         }
 256
 257         for (i = 0; i < priv->num_tx_queues; i++) {
 258                 tx_queue = priv->tx_queue[i];
 259                 tx_queue->tx_bd_base = vaddr;
 260                 tx_queue->tx_bd_dma_base = addr;
 261                 tx_queue->dev = ndev;
 262                 /* enet DMA only understands physical addresses */
 263                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 264                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 265         }
 266
 267         /* Start the rx descriptor ring where the tx ring leaves off */
 268         for (i = 0; i < priv->num_rx_queues; i++) {
 269                 rx_queue = priv->rx_queue[i];
 270                 rx_queue->rx_bd_base = vaddr;
 271                 rx_queue->rx_bd_dma_base = addr;
 272                 rx_queue->dev = ndev;
 273                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 274                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 275         }
 276
 277         /* Setup the skbuff rings */
 278         for (i = 0; i < priv->num_tx_queues; i++) {
 279                 tx_queue = priv->tx_queue[i];
 280                 tx_queue->tx_skbuff =
 281                         kmalloc_array(tx_queue->tx_ring_size,
 282                                       sizeof(*tx_queue->tx_skbuff),
 283                                       GFP_KERNEL);
 284                 if (!tx_queue->tx_skbuff)
 285                         goto cleanup;
 286
 287                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 288                         tx_queue->tx_skbuff[k] = NULL;
 289         }
 290
 291         for (i = 0; i < priv->num_rx_queues; i++) {
 292                 rx_queue = priv->rx_queue[i];
 293                 rx_queue->rx_skbuff =
 294                         kmalloc_array(rx_queue->rx_ring_size,
 295                                       sizeof(*rx_queue->rx_skbuff),
 296                                       GFP_KERNEL);
 297                 if (!rx_queue->rx_skbuff)
 298                         goto cleanup;
 299
 300                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 301                         rx_queue->rx_skbuff[j] = NULL;
 302         }
 303
 304         if (gfar_init_bds(ndev))
 305                 goto cleanup;
 306
 307         return 0;
 308
 309 cleanup:
 310         free_skb_resources(priv);
 311         return -ENOMEM;
 312 }
 313
 314 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 315 {
 316         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 317         u32 __iomem *baddr;
 318         int i;
 319
 320         baddr = &regs->tbase0;
 321         for (i = 0; i < priv->num_tx_queues; i++) {
 322                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 323                 baddr += 2;
 324         }
 325
 326         baddr = &regs->rbase0;
 327         for (i = 0; i < priv->num_rx_queues; i++) {
 328                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 329                 baddr += 2;
 330         }
 331 }
 332
 333 static void gfar_init_mac(struct net_device *ndev)
 334 {
 335         struct gfar_private *priv = netdev_priv(ndev);
 336         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 337         u32 rctrl = 0;
 338         u32 tctrl = 0;
 339         u32 attrs = 0;
 340
 341         /* write the tx/rx base registers */
 342         gfar_init_tx_rx_base(priv);
 343
 344         /* Configure the coalescing support */
 345         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 346
 347         /* set this when rx hw offload (TOE) functions are being used */
 348         priv->uses_rxfcb = 0;
 349
 350         if (priv->rx_filer_enable) {
 351                 rctrl |= RCTRL_FILREN;
 352                 /* Program the RIR0 reg with the required distribution */
 353                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 354         }
 355
 356         /* Restore PROMISC mode */
 357         if (ndev->flags & IFF_PROMISC)
 358                 rctrl |= RCTRL_PROM;
 359
 360         if (ndev->features & NETIF_F_RXCSUM) {
 361                 rctrl |= RCTRL_CHECKSUMMING;
 362                 priv->uses_rxfcb = 1;
 363         }
 364
 365         if (priv->extended_hash) {
 366                 rctrl |= RCTRL_EXTHASH;
 367
 368                 gfar_clear_exact_match(ndev);
 369                 rctrl |= RCTRL_EMEN;
 370         }
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Insert receive time stamps into padding alignment bytes */
 378         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 379                 rctrl &= ~RCTRL_PAL_MASK;
 380                 rctrl |= RCTRL_PADDING(8);
 381                 priv->padding = 8;
 382         }
 383
 384         /* Enable HW time stamping if requested from user space */
 385         if (priv->hwts_rx_en) {
 386                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 387                 priv->uses_rxfcb = 1;
 388         }
 389
 390         if (ndev->features & NETIF_F_HW_VLAN_RX) {
 391                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 392                 priv->uses_rxfcb = 1;
 393         }
 394
 395         /* Init rctrl based on our settings */
 396         gfar_write(&regs->rctrl, rctrl);
 397
 398         if (ndev->features & NETIF_F_IP_CSUM)
 399                 tctrl |= TCTRL_INIT_CSUM;
 400
 401         if (priv->prio_sched_en)
 402                 tctrl |= TCTRL_TXSCHED_PRIO;
 403         else {
 404                 tctrl |= TCTRL_TXSCHED_WRRS;
 405                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 406                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 407         }
 408
 409         gfar_write(&regs->tctrl, tctrl);
 410
 411         /* Set the extraction length and index */
 412         attrs = ATTRELI_EL(priv->rx_stash_size) |
 413                 ATTRELI_EI(priv->rx_stash_index);
 414
 415         gfar_write(&regs->attreli, attrs);
 416
 417         /* Start with defaults, and add stashing or locking
 418          * depending on the approprate variables
 419          */
 420         attrs = ATTR_INIT_SETTINGS;
 421
 422         if (priv->bd_stash_en)
 423                 attrs |= ATTR_BDSTASH;
 424
 425         if (priv->rx_stash_size != 0)
 426                 attrs |= ATTR_BUFSTASH;
 427
 428         gfar_write(&regs->attr, attrs);
 429
 430         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 431         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 432         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 433 }
 434
 435 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 436 {
 437         struct gfar_private *priv = netdev_priv(dev);
 438         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 439         unsigned long tx_packets = 0, tx_bytes = 0;
 440         int i;
 441
 442         for (i = 0; i < priv->num_rx_queues; i++) {
 443                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 444                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 445                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 446         }
 447
 448         dev->stats.rx_packets = rx_packets;
 449         dev->stats.rx_bytes   = rx_bytes;
 450         dev->stats.rx_dropped = rx_dropped;
 451
 452         for (i = 0; i < priv->num_tx_queues; i++) {
 453                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 454                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 455         }
 456
 457         dev->stats.tx_bytes   = tx_bytes;
 458         dev->stats.tx_packets = tx_packets;
 459
 460         return &dev->stats;
 461 }
 462
 463 static const struct net_device_ops gfar_netdev_ops = {
 464         .ndo_open = gfar_enet_open,
 465         .ndo_start_xmit = gfar_start_xmit,
 466         .ndo_stop = gfar_close,
 467         .ndo_change_mtu = gfar_change_mtu,
 468         .ndo_set_features = gfar_set_features,
 469         .ndo_set_rx_mode = gfar_set_multi,
 470         .ndo_tx_timeout = gfar_timeout,
 471         .ndo_do_ioctl = gfar_ioctl,
 472         .ndo_get_stats = gfar_get_stats,
 473         .ndo_set_mac_address = eth_mac_addr,
 474         .ndo_validate_addr = eth_validate_addr,
 475 #ifdef CONFIG_NET_POLL_CONTROLLER
 476         .ndo_poll_controller = gfar_netpoll,
 477 #endif
 478 };
 479
 480 void lock_rx_qs(struct gfar_private *priv)
 481 {
 482         int i;
 483
 484         for (i = 0; i < priv->num_rx_queues; i++)
 485                 spin_lock(&priv->rx_queue[i]->rxlock);
 486 }
 487
 488 void lock_tx_qs(struct gfar_private *priv)
 489 {
 490         int i;
 491
 492         for (i = 0; i < priv->num_tx_queues; i++)
 493                 spin_lock(&priv->tx_queue[i]->txlock);
 494 }
 495
 496 void unlock_rx_qs(struct gfar_private *priv)
 497 {
 498         int i;
 499
 500         for (i = 0; i < priv->num_rx_queues; i++)
 501                 spin_unlock(&priv->rx_queue[i]->rxlock);
 502 }
 503
 504 void unlock_tx_qs(struct gfar_private *priv)
 505 {
 506         int i;
 507
 508         for (i = 0; i < priv->num_tx_queues; i++)
 509                 spin_unlock(&priv->tx_queue[i]->txlock);
 510 }
 511
 512 static void free_tx_pointers(struct gfar_private *priv)
 513 {
 514         int i;
 515
 516         for (i = 0; i < priv->num_tx_queues; i++)
 517                 kfree(priv->tx_queue[i]);
 518 }
 519
 520 static void free_rx_pointers(struct gfar_private *priv)
 521 {
 522         int i;
 523
 524         for (i = 0; i < priv->num_rx_queues; i++)
 525                 kfree(priv->rx_queue[i]);
 526 }
 527
 528 static void unmap_group_regs(struct gfar_private *priv)
 529 {
 530         int i;
 531
 532         for (i = 0; i < MAXGROUPS; i++)
 533                 if (priv->gfargrp[i].regs)
 534                         iounmap(priv->gfargrp[i].regs);
 535 }
 536
 537 static void free_gfar_dev(struct gfar_private *priv)
 538 {
 539         int i, j;
 540
 541         for (i = 0; i < priv->num_grps; i++)
 542                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 543                         kfree(priv->gfargrp[i].irqinfo[j]);
 544                         priv->gfargrp[i].irqinfo[j] = NULL;
 545                 }
 546
 547         free_netdev(priv->ndev);
 548 }
 549
 550 static void disable_napi(struct gfar_private *priv)
 551 {
 552         int i;
 553
 554         for (i = 0; i < priv->num_grps; i++)
 555                 napi_disable(&priv->gfargrp[i].napi);
 556 }
 557
 558 static void enable_napi(struct gfar_private *priv)
 559 {
 560         int i;
 561
 562         for (i = 0; i < priv->num_grps; i++)
 563                 napi_enable(&priv->gfargrp[i].napi);
 564 }
 565
 566 static int gfar_parse_group(struct device_node *np,
 567                             struct gfar_private *priv, const char *model)
 568 {
 569         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 570         u32 *queue_mask;
 571         int i;
 572
 573         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 574                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 575                                           GFP_KERNEL);
 576                 if (!grp->irqinfo[i])
 577                         return -ENOMEM;
 578         }
 579
 580         grp->regs = of_iomap(np, 0);
 581         if (!grp->regs)
 582                 return -ENOMEM;
 583
 584         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 585
 586         /* If we aren't the FEC we have multiple interrupts */
 587         if (model && strcasecmp(model, "FEC")) {
 588                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 589                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 590                 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
 591                     gfar_irq(grp, RX)->irq == NO_IRQ ||
 592                     gfar_irq(grp, ER)->irq == NO_IRQ)
 593                         return -EINVAL;
 594         }
 595
 596         grp->grp_id = priv->num_grps;
 597         grp->priv = priv;
 598         spin_lock_init(&grp->grplock);
 599         if (priv->mode == MQ_MG_MODE) {
 600                 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
 601                 grp->rx_bit_map = queue_mask ?
 602                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 603                 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
 604                 grp->tx_bit_map = queue_mask ?
 605                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 606         } else {
 607                 grp->rx_bit_map = 0xFF;
 608                 grp->tx_bit_map = 0xFF;
 609         }
 610         priv->num_grps++;
 611
 612         return 0;
 613 }
 614
 615 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 616 {
 617         const char *model;
 618         const char *ctype;
 619         const void *mac_addr;
 620         int err = 0, i;
 621         struct net_device *dev = NULL;
 622         struct gfar_private *priv = NULL;
 623         struct device_node *np = ofdev->dev.of_node;
 624         struct device_node *child = NULL;
 625         const u32 *stash;
 626         const u32 *stash_len;
 627         const u32 *stash_idx;
 628         unsigned int num_tx_qs, num_rx_qs;
 629         u32 *tx_queues, *rx_queues;
 630
 631         if (!np || !of_device_is_available(np))
 632                 return -ENODEV;
 633
 634         /* parse the num of tx and rx queues */
 635         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 636         num_tx_qs = tx_queues ? *tx_queues : 1;
 637
 638         if (num_tx_qs > MAX_TX_QS) {
 639                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 640                        num_tx_qs, MAX_TX_QS);
 641                 pr_err("Cannot do alloc_etherdev, aborting\n");
 642                 return -EINVAL;
 643         }
 644
 645         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 646         num_rx_qs = rx_queues ? *rx_queues : 1;
 647
 648         if (num_rx_qs > MAX_RX_QS) {
 649                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 650                        num_rx_qs, MAX_RX_QS);
 651                 pr_err("Cannot do alloc_etherdev, aborting\n");
 652                 return -EINVAL;
 653         }
 654
 655         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 656         dev = *pdev;
 657         if (NULL == dev)
 658                 return -ENOMEM;
 659
 660         priv = netdev_priv(dev);
 661         priv->ndev = dev;
 662
 663         priv->num_tx_queues = num_tx_qs;
 664         netif_set_real_num_rx_queues(dev, num_rx_qs);
 665         priv->num_rx_queues = num_rx_qs;
 666         priv->num_grps = 0x0;
 667
 668         /* Init Rx queue filer rule set linked list */
 669         INIT_LIST_HEAD(&priv->rx_list.list);
 670         priv->rx_list.count = 0;
 671         mutex_init(&priv->rx_queue_access);
 672
 673         model = of_get_property(np, "model", NULL);
 674
 675         for (i = 0; i < MAXGROUPS; i++)
 676                 priv->gfargrp[i].regs = NULL;
 677
 678         /* Parse and initialize group specific information */
 679         if (of_device_is_compatible(np, "fsl,etsec2")) {
 680                 priv->mode = MQ_MG_MODE;
 681                 for_each_child_of_node(np, child) {
 682                         err = gfar_parse_group(child, priv, model);
 683                         if (err)
 684                                 goto err_grp_init;
 685                 }
 686         } else {
 687                 priv->mode = SQ_SG_MODE;
 688                 err = gfar_parse_group(np, priv, model);
 689                 if (err)
 690                         goto err_grp_init;
 691         }
 692
 693         for (i = 0; i < priv->num_tx_queues; i++)
 694                priv->tx_queue[i] = NULL;
 695         for (i = 0; i < priv->num_rx_queues; i++)
 696                 priv->rx_queue[i] = NULL;
 697
 698         for (i = 0; i < priv->num_tx_queues; i++) {
 699                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 700                                             GFP_KERNEL);
 701                 if (!priv->tx_queue[i]) {
 702                         err = -ENOMEM;
 703                         goto tx_alloc_failed;
 704                 }
 705                 priv->tx_queue[i]->tx_skbuff = NULL;
 706                 priv->tx_queue[i]->qindex = i;
 707                 priv->tx_queue[i]->dev = dev;
 708                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 709         }
 710
 711         for (i = 0; i < priv->num_rx_queues; i++) {
 712                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 713                                             GFP_KERNEL);
 714                 if (!priv->rx_queue[i]) {
 715                         err = -ENOMEM;
 716                         goto rx_alloc_failed;
 717                 }
 718                 priv->rx_queue[i]->rx_skbuff = NULL;
 719                 priv->rx_queue[i]->qindex = i;
 720                 priv->rx_queue[i]->dev = dev;
 721                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 722         }
 723
 724
 725         stash = of_get_property(np, "bd-stash", NULL);
 726
 727         if (stash) {
 728                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 729                 priv->bd_stash_en = 1;
 730         }
 731
 732         stash_len = of_get_property(np, "rx-stash-len", NULL);
 733
 734         if (stash_len)
 735                 priv->rx_stash_size = *stash_len;
 736
 737         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 738
 739         if (stash_idx)
 740                 priv->rx_stash_index = *stash_idx;
 741
 742         if (stash_len || stash_idx)
 743                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 744
 745         mac_addr = of_get_mac_address(np);
 746
 747         if (mac_addr)
 748                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 749
 750         if (model && !strcasecmp(model, "TSEC"))
 751                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 752                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 753                                      FSL_GIANFAR_DEV_HAS_RMON |
 754                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 755
 756         if (model && !strcasecmp(model, "eTSEC"))
 757                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 758                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 759                                      FSL_GIANFAR_DEV_HAS_RMON |
 760                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 761                                      FSL_GIANFAR_DEV_HAS_PADDING |
 762                                      FSL_GIANFAR_DEV_HAS_CSUM |
 763                                      FSL_GIANFAR_DEV_HAS_VLAN |
 764                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 765                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 766                                      FSL_GIANFAR_DEV_HAS_TIMER;
 767
 768         ctype = of_get_property(np, "phy-connection-type", NULL);
 769
 770         /* We only care about rgmii-id.  The rest are autodetected */
 771         if (ctype && !strcmp(ctype, "rgmii-id"))
 772                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 773         else
 774                 priv->interface = PHY_INTERFACE_MODE_MII;
 775
 776         if (of_get_property(np, "fsl,magic-packet", NULL))
 777                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 778
 779         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 780
 781         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 782         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 783
 784         return 0;
 785
 786 rx_alloc_failed:
 787         free_rx_pointers(priv);
 788 tx_alloc_failed:
 789         free_tx_pointers(priv);
 790 err_grp_init:
 791         unmap_group_regs(priv);
 792         free_gfar_dev(priv);
 793         return err;
 794 }
 795
 796 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 797                                struct ifreq *ifr, int cmd)
 798 {
 799         struct hwtstamp_config config;
 800         struct gfar_private *priv = netdev_priv(netdev);
 801
 802         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 803                 return -EFAULT;
 804
 805         /* reserved for future extensions */
 806         if (config.flags)
 807                 return -EINVAL;
 808
 809         switch (config.tx_type) {
 810         case HWTSTAMP_TX_OFF:
 811                 priv->hwts_tx_en = 0;
 812                 break;
 813         case HWTSTAMP_TX_ON:
 814                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 815                         return -ERANGE;
 816                 priv->hwts_tx_en = 1;
 817                 break;
 818         default:
 819                 return -ERANGE;
 820         }
 821
 822         switch (config.rx_filter) {
 823         case HWTSTAMP_FILTER_NONE:
 824                 if (priv->hwts_rx_en) {
 825                         stop_gfar(netdev);
 826                         priv->hwts_rx_en = 0;
 827                         startup_gfar(netdev);
 828                 }
 829                 break;
 830         default:
 831                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 832                         return -ERANGE;
 833                 if (!priv->hwts_rx_en) {
 834                         stop_gfar(netdev);
 835                         priv->hwts_rx_en = 1;
 836                         startup_gfar(netdev);
 837                 }
 838                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 839                 break;
 840         }
 841
 842         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 843                 -EFAULT : 0;
 844 }
 845
 846 /* Ioctl MII Interface */
 847 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 848 {
 849         struct gfar_private *priv = netdev_priv(dev);
 850
 851         if (!netif_running(dev))
 852                 return -EINVAL;
 853
 854         if (cmd == SIOCSHWTSTAMP)
 855                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 856
 857         if (!priv->phydev)
 858                 return -ENODEV;
 859
 860         return phy_mii_ioctl(priv->phydev, rq, cmd);
 861 }
 862
 863 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 864 {
 865         unsigned int new_bit_map = 0x0;
 866         int mask = 0x1 << (max_qs - 1), i;
 867
 868         for (i = 0; i < max_qs; i++) {
 869                 if (bit_map & mask)
 870                         new_bit_map = new_bit_map + (1 << i);
 871                 mask = mask >> 0x1;
 872         }
 873         return new_bit_map;
 874 }
 875
 876 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 877                                    u32 class)
 878 {
 879         u32 rqfpr = FPR_FILER_MASK;
 880         u32 rqfcr = 0x0;
 881
 882         rqfar--;
 883         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 884         priv->ftp_rqfpr[rqfar] = rqfpr;
 885         priv->ftp_rqfcr[rqfar] = rqfcr;
 886         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 887
 888         rqfar--;
 889         rqfcr = RQFCR_CMP_NOMATCH;
 890         priv->ftp_rqfpr[rqfar] = rqfpr;
 891         priv->ftp_rqfcr[rqfar] = rqfcr;
 892         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 893
 894         rqfar--;
 895         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 896         rqfpr = class;
 897         priv->ftp_rqfcr[rqfar] = rqfcr;
 898         priv->ftp_rqfpr[rqfar] = rqfpr;
 899         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 900
 901         rqfar--;
 902         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 903         rqfpr = class;
 904         priv->ftp_rqfcr[rqfar] = rqfcr;
 905         priv->ftp_rqfpr[rqfar] = rqfpr;
 906         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 907
 908         return rqfar;
 909 }
 910
 911 static void gfar_init_filer_table(struct gfar_private *priv)
 912 {
 913         int i = 0x0;
 914         u32 rqfar = MAX_FILER_IDX;
 915         u32 rqfcr = 0x0;
 916         u32 rqfpr = FPR_FILER_MASK;
 917
 918         /* Default rule */
 919         rqfcr = RQFCR_CMP_MATCH;
 920         priv->ftp_rqfcr[rqfar] = rqfcr;
 921         priv->ftp_rqfpr[rqfar] = rqfpr;
 922         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 923
 924         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 925         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 926         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 927         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 928         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 929         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 930
 931         /* cur_filer_idx indicated the first non-masked rule */
 932         priv->cur_filer_idx = rqfar;
 933
 934         /* Rest are masked rules */
 935         rqfcr = RQFCR_CMP_NOMATCH;
 936         for (i = 0; i < rqfar; i++) {
 937                 priv->ftp_rqfcr[i] = rqfcr;
 938                 priv->ftp_rqfpr[i] = rqfpr;
 939                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 940         }
 941 }
 942
 943 static void gfar_detect_errata(struct gfar_private *priv)
 944 {
 945         struct device *dev = &priv->ofdev->dev;
 946         unsigned int pvr = mfspr(SPRN_PVR);
 947         unsigned int svr = mfspr(SPRN_SVR);
 948         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 949         unsigned int rev = svr & 0xffff;
 950
 951         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 952         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 953             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 954                 priv->errata |= GFAR_ERRATA_74;
 955
 956         /* MPC8313 and MPC837x all rev */
 957         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 958             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 959                 priv->errata |= GFAR_ERRATA_76;
 960
 961         /* MPC8313 and MPC837x all rev */
 962         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 963             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 964                 priv->errata |= GFAR_ERRATA_A002;
 965
 966         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
 967         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
 968             (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
 969                 priv->errata |= GFAR_ERRATA_12;
 970
 971         if (priv->errata)
 972                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 973                          priv->errata);
 974 }
 975
 976 /* Set up the ethernet device structure, private data,
 977  * and anything else we need before we start
 978  */
 979 static int gfar_probe(struct platform_device *ofdev)
 980 {
 981         u32 tempval;
 982         struct net_device *dev = NULL;
 983         struct gfar_private *priv = NULL;
 984         struct gfar __iomem *regs = NULL;
 985         int err = 0, i, grp_idx = 0;
 986         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 987         u32 isrg = 0;
 988         u32 __iomem *baddr;
 989
 990         err = gfar_of_init(ofdev, &dev);
 991
 992         if (err)
 993                 return err;
 994
 995         priv = netdev_priv(dev);
 996         priv->ndev = dev;
 997         priv->ofdev = ofdev;
 998         priv->dev = &ofdev->dev;
 999         SET_NETDEV_DEV(dev, &ofdev->dev);
1000
1001         spin_lock_init(&priv->bflock);
1002         INIT_WORK(&priv->reset_task, gfar_reset_task);
1003
1004         dev_set_drvdata(&ofdev->dev, priv);
1005         regs = priv->gfargrp[0].regs;
1006
1007         gfar_detect_errata(priv);
1008
1009         /* Stop the DMA engine now, in case it was running before
1010          * (The firmware could have used it, and left it running).
1011          */
1012         gfar_halt(dev);
1013
1014         /* Reset MAC layer */
1015         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1016
1017         /* We need to delay at least 3 TX clocks */
1018         udelay(2);
1019
1020         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1021         gfar_write(&regs->maccfg1, tempval);
1022
1023         /* Initialize MACCFG2. */
1024         tempval = MACCFG2_INIT_SETTINGS;
1025         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1026                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1027         gfar_write(&regs->maccfg2, tempval);
1028
1029         /* Initialize ECNTRL */
1030         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1031
1032         /* Set the dev->base_addr to the gfar reg region */
1033         dev->base_addr = (unsigned long) regs;
1034
1035         /* Fill in the dev structure */
1036         dev->watchdog_timeo = TX_TIMEOUT;
1037         dev->mtu = 1500;
1038         dev->netdev_ops = &gfar_netdev_ops;
1039         dev->ethtool_ops = &gfar_ethtool_ops;
1040
1041         /* Register for napi ...We are registering NAPI for each grp */
1042         for (i = 0; i < priv->num_grps; i++)
1043                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1044                                GFAR_DEV_WEIGHT);
1045
1046         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1047                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1048                                    NETIF_F_RXCSUM;
1049                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1050                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1051         }
1052
1053         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1054                 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1055                 dev->features |= NETIF_F_HW_VLAN_RX;
1056         }
1057
1058         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1059                 priv->extended_hash = 1;
1060                 priv->hash_width = 9;
1061
1062                 priv->hash_regs[0] = &regs->igaddr0;
1063                 priv->hash_regs[1] = &regs->igaddr1;
1064                 priv->hash_regs[2] = &regs->igaddr2;
1065                 priv->hash_regs[3] = &regs->igaddr3;
1066                 priv->hash_regs[4] = &regs->igaddr4;
1067                 priv->hash_regs[5] = &regs->igaddr5;
1068                 priv->hash_regs[6] = &regs->igaddr6;
1069                 priv->hash_regs[7] = &regs->igaddr7;
1070                 priv->hash_regs[8] = &regs->gaddr0;
1071                 priv->hash_regs[9] = &regs->gaddr1;
1072                 priv->hash_regs[10] = &regs->gaddr2;
1073                 priv->hash_regs[11] = &regs->gaddr3;
1074                 priv->hash_regs[12] = &regs->gaddr4;
1075                 priv->hash_regs[13] = &regs->gaddr5;
1076                 priv->hash_regs[14] = &regs->gaddr6;
1077                 priv->hash_regs[15] = &regs->gaddr7;
1078
1079         } else {
1080                 priv->extended_hash = 0;
1081                 priv->hash_width = 8;
1082
1083                 priv->hash_regs[0] = &regs->gaddr0;
1084                 priv->hash_regs[1] = &regs->gaddr1;
1085                 priv->hash_regs[2] = &regs->gaddr2;
1086                 priv->hash_regs[3] = &regs->gaddr3;
1087                 priv->hash_regs[4] = &regs->gaddr4;
1088                 priv->hash_regs[5] = &regs->gaddr5;
1089                 priv->hash_regs[6] = &regs->gaddr6;
1090                 priv->hash_regs[7] = &regs->gaddr7;
1091         }
1092
1093         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1094                 priv->padding = DEFAULT_PADDING;
1095         else
1096                 priv->padding = 0;
1097
1098         if (dev->features & NETIF_F_IP_CSUM ||
1099             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1100                 dev->needed_headroom = GMAC_FCB_LEN;
1101
1102         /* Program the isrg regs only if number of grps > 1 */
1103         if (priv->num_grps > 1) {
1104                 baddr = &regs->isrg0;
1105                 for (i = 0; i < priv->num_grps; i++) {
1106                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1107                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1108                         gfar_write(baddr, isrg);
1109                         baddr++;
1110                         isrg = 0x0;
1111                 }
1112         }
1113
1114         /* Need to reverse the bit maps as  bit_map's MSB is q0
1115          * but, for_each_set_bit parses from right to left, which
1116          * basically reverses the queue numbers
1117          */
1118         for (i = 0; i< priv->num_grps; i++) {
1119                 priv->gfargrp[i].tx_bit_map =
1120                         reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1121                 priv->gfargrp[i].rx_bit_map =
1122                         reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1123         }
1124
1125         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1126          * also assign queues to groups
1127          */
1128         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1129                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1130
1131                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1132                                  priv->num_rx_queues) {
1133                         priv->gfargrp[grp_idx].num_rx_queues++;
1134                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1135                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1136                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1137                 }
1138                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1139
1140                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1141                                  priv->num_tx_queues) {
1142                         priv->gfargrp[grp_idx].num_tx_queues++;
1143                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1144                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1145                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1146                 }
1147                 priv->gfargrp[grp_idx].rstat = rstat;
1148                 priv->gfargrp[grp_idx].tstat = tstat;
1149                 rstat = tstat =0;
1150         }
1151
1152         gfar_write(&regs->rqueue, rqueue);
1153         gfar_write(&regs->tqueue, tqueue);
1154
1155         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1156
1157         /* Initializing some of the rx/tx queue level parameters */
1158         for (i = 0; i < priv->num_tx_queues; i++) {
1159                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1160                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1161                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1162                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1163         }
1164
1165         for (i = 0; i < priv->num_rx_queues; i++) {
1166                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1167                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1168                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1169         }
1170
1171         /* always enable rx filer */
1172         priv->rx_filer_enable = 1;
1173         /* Enable most messages by default */
1174         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1175         /* use pritority h/w tx queue scheduling for single queue devices */
1176         if (priv->num_tx_queues == 1)
1177                 priv->prio_sched_en = 1;
1178
1179         /* Carrier starts down, phylib will bring it up */
1180         netif_carrier_off(dev);
1181
1182         err = register_netdev(dev);
1183
1184         if (err) {
1185                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1186                 goto register_fail;
1187         }
1188
1189         device_init_wakeup(&dev->dev,
1190                            priv->device_flags &
1191                            FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1192
1193         /* fill out IRQ number and name fields */
1194         for (i = 0; i < priv->num_grps; i++) {
1195                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1196                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1197                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1198                                 dev->name, "_g", '0' + i, "_tx");
1199                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1200                                 dev->name, "_g", '0' + i, "_rx");
1201                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1202                                 dev->name, "_g", '0' + i, "_er");
1203                 } else
1204                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1205         }
1206
1207         /* Initialize the filer table */
1208         gfar_init_filer_table(priv);
1209
1210         /* Create all the sysfs files */
1211         gfar_init_sysfs(dev);
1212
1213         /* Print out the device info */
1214         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1215
1216         /* Even more device info helps when determining which kernel
1217          * provided which set of benchmarks.
1218          */
1219         netdev_info(dev, "Running with NAPI enabled\n");
1220         for (i = 0; i < priv->num_rx_queues; i++)
1221                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1222                             i, priv->rx_queue[i]->rx_ring_size);
1223         for (i = 0; i < priv->num_tx_queues; i++)
1224                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1225                             i, priv->tx_queue[i]->tx_ring_size);
1226
1227         return 0;
1228
1229 register_fail:
1230         unmap_group_regs(priv);
1231         free_tx_pointers(priv);
1232         free_rx_pointers(priv);
1233         if (priv->phy_node)
1234                 of_node_put(priv->phy_node);
1235         if (priv->tbi_node)
1236                 of_node_put(priv->tbi_node);
1237         free_gfar_dev(priv);
1238         return err;
1239 }
1240
1241 static int gfar_remove(struct platform_device *ofdev)
1242 {
1243         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1244
1245         if (priv->phy_node)
1246                 of_node_put(priv->phy_node);
1247         if (priv->tbi_node)
1248                 of_node_put(priv->tbi_node);
1249
1250         dev_set_drvdata(&ofdev->dev, NULL);
1251
1252         unregister_netdev(priv->ndev);
1253         unmap_group_regs(priv);
1254         free_gfar_dev(priv);
1255
1256         return 0;
1257 }
1258
1259 #ifdef CONFIG_PM
1260
1261 static int gfar_suspend(struct device *dev)
1262 {
1263         struct gfar_private *priv = dev_get_drvdata(dev);
1264         struct net_device *ndev = priv->ndev;
1265         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1266         unsigned long flags;
1267         u32 tempval;
1268
1269         int magic_packet = priv->wol_en &&
1270                            (priv->device_flags &
1271                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1272
1273         netif_device_detach(ndev);
1274
1275         if (netif_running(ndev)) {
1276
1277                 local_irq_save(flags);
1278                 lock_tx_qs(priv);
1279                 lock_rx_qs(priv);
1280
1281                 gfar_halt_nodisable(ndev);
1282
1283                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1284                 tempval = gfar_read(&regs->maccfg1);
1285
1286                 tempval &= ~MACCFG1_TX_EN;
1287
1288                 if (!magic_packet)
1289                         tempval &= ~MACCFG1_RX_EN;
1290
1291                 gfar_write(&regs->maccfg1, tempval);
1292
1293                 unlock_rx_qs(priv);
1294                 unlock_tx_qs(priv);
1295                 local_irq_restore(flags);
1296
1297                 disable_napi(priv);
1298
1299                 if (magic_packet) {
1300                         /* Enable interrupt on Magic Packet */
1301                         gfar_write(&regs->imask, IMASK_MAG);
1302
1303                         /* Enable Magic Packet mode */
1304                         tempval = gfar_read(&regs->maccfg2);
1305                         tempval |= MACCFG2_MPEN;
1306                         gfar_write(&regs->maccfg2, tempval);
1307                 } else {
1308                         phy_stop(priv->phydev);
1309                 }
1310         }
1311
1312         return 0;
1313 }
1314
1315 static int gfar_resume(struct device *dev)
1316 {
1317         struct gfar_private *priv = dev_get_drvdata(dev);
1318         struct net_device *ndev = priv->ndev;
1319         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1320         unsigned long flags;
1321         u32 tempval;
1322         int magic_packet = priv->wol_en &&
1323                            (priv->device_flags &
1324                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1325
1326         if (!netif_running(ndev)) {
1327                 netif_device_attach(ndev);
1328                 return 0;
1329         }
1330
1331         if (!magic_packet && priv->phydev)
1332                 phy_start(priv->phydev);
1333
1334         /* Disable Magic Packet mode, in case something
1335          * else woke us up.
1336          */
1337         local_irq_save(flags);
1338         lock_tx_qs(priv);
1339         lock_rx_qs(priv);
1340
1341         tempval = gfar_read(&regs->maccfg2);
1342         tempval &= ~MACCFG2_MPEN;
1343         gfar_write(&regs->maccfg2, tempval);
1344
1345         gfar_start(ndev);
1346
1347         unlock_rx_qs(priv);
1348         unlock_tx_qs(priv);
1349         local_irq_restore(flags);
1350
1351         netif_device_attach(ndev);
1352
1353         enable_napi(priv);
1354
1355         return 0;
1356 }
1357
1358 static int gfar_restore(struct device *dev)
1359 {
1360         struct gfar_private *priv = dev_get_drvdata(dev);
1361         struct net_device *ndev = priv->ndev;
1362
1363         if (!netif_running(ndev)) {
1364                 netif_device_attach(ndev);
1365
1366                 return 0;
1367         }
1368
1369         if (gfar_init_bds(ndev)) {
1370                 free_skb_resources(priv);
1371                 return -ENOMEM;
1372         }
1373
1374         init_registers(ndev);
1375         gfar_set_mac_address(ndev);
1376         gfar_init_mac(ndev);
1377         gfar_start(ndev);
1378
1379         priv->oldlink = 0;
1380         priv->oldspeed = 0;
1381         priv->oldduplex = -1;
1382
1383         if (priv->phydev)
1384                 phy_start(priv->phydev);
1385
1386         netif_device_attach(ndev);
1387         enable_napi(priv);
1388
1389         return 0;
1390 }
1391
1392 static struct dev_pm_ops gfar_pm_ops = {
1393         .suspend = gfar_suspend,
1394         .resume = gfar_resume,
1395         .freeze = gfar_suspend,
1396         .thaw = gfar_resume,
1397         .restore = gfar_restore,
1398 };
1399
1400 #define GFAR_PM_OPS (&gfar_pm_ops)
1401
1402 #else
1403
1404 #define GFAR_PM_OPS NULL
1405
1406 #endif
1407
1408 /* Reads the controller's registers to determine what interface
1409  * connects it to the PHY.
1410  */
1411 static phy_interface_t gfar_get_interface(struct net_device *dev)
1412 {
1413         struct gfar_private *priv = netdev_priv(dev);
1414         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1415         u32 ecntrl;
1416
1417         ecntrl = gfar_read(&regs->ecntrl);
1418
1419         if (ecntrl & ECNTRL_SGMII_MODE)
1420                 return PHY_INTERFACE_MODE_SGMII;
1421
1422         if (ecntrl & ECNTRL_TBI_MODE) {
1423                 if (ecntrl & ECNTRL_REDUCED_MODE)
1424                         return PHY_INTERFACE_MODE_RTBI;
1425                 else
1426                         return PHY_INTERFACE_MODE_TBI;
1427         }
1428
1429         if (ecntrl & ECNTRL_REDUCED_MODE) {
1430                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1431                         return PHY_INTERFACE_MODE_RMII;
1432                 }
1433                 else {
1434                         phy_interface_t interface = priv->interface;
1435
1436                         /* This isn't autodetected right now, so it must
1437                          * be set by the device tree or platform code.
1438                          */
1439                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1440                                 return PHY_INTERFACE_MODE_RGMII_ID;
1441
1442                         return PHY_INTERFACE_MODE_RGMII;
1443                 }
1444         }
1445
1446         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1447                 return PHY_INTERFACE_MODE_GMII;
1448
1449         return PHY_INTERFACE_MODE_MII;
1450 }
1451
1452
1453 /* Initializes driver's PHY state, and attaches to the PHY.
1454  * Returns 0 on success.
1455  */
1456 static int init_phy(struct net_device *dev)
1457 {
1458         struct gfar_private *priv = netdev_priv(dev);
1459         uint gigabit_support =
1460                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1461                 SUPPORTED_1000baseT_Full : 0;
1462         phy_interface_t interface;
1463
1464         priv->oldlink = 0;
1465         priv->oldspeed = 0;
1466         priv->oldduplex = -1;
1467
1468         interface = gfar_get_interface(dev);
1469
1470         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1471                                       interface);
1472         if (!priv->phydev)
1473                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1474                                                          interface);
1475         if (!priv->phydev) {
1476                 dev_err(&dev->dev, "could not attach to PHY\n");
1477                 return -ENODEV;
1478         }
1479
1480         if (interface == PHY_INTERFACE_MODE_SGMII)
1481                 gfar_configure_serdes(dev);
1482
1483         /* Remove any features not supported by the controller */
1484         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1485         priv->phydev->advertising = priv->phydev->supported;
1486
1487         return 0;
1488 }
1489
1490 /* Initialize TBI PHY interface for communicating with the
1491  * SERDES lynx PHY on the chip.  We communicate with this PHY
1492  * through the MDIO bus on each controller, treating it as a
1493  * "normal" PHY at the address found in the TBIPA register.  We assume
1494  * that the TBIPA register is valid.  Either the MDIO bus code will set
1495  * it to a value that doesn't conflict with other PHYs on the bus, or the
1496  * value doesn't matter, as there are no other PHYs on the bus.
1497  */
1498 static void gfar_configure_serdes(struct net_device *dev)
1499 {
1500         struct gfar_private *priv = netdev_priv(dev);
1501         struct phy_device *tbiphy;
1502
1503         if (!priv->tbi_node) {
1504                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1505                                     "device tree specify a tbi-handle\n");
1506                 return;
1507         }
1508
1509         tbiphy = of_phy_find_device(priv->tbi_node);
1510         if (!tbiphy) {
1511                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1512                 return;
1513         }
1514
1515         /* If the link is already up, we must already be ok, and don't need to
1516          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1517          * everything for us?  Resetting it takes the link down and requires
1518          * several seconds for it to come back.
1519          */
1520         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1521                 return;
1522
1523         /* Single clk mode, mii mode off(for serdes communication) */
1524         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1525
1526         phy_write(tbiphy, MII_ADVERTISE,
1527                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1528                   ADVERTISE_1000XPSE_ASYM);
1529
1530         phy_write(tbiphy, MII_BMCR,
1531                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1532                   BMCR_SPEED1000);
1533 }
1534
1535 static void init_registers(struct net_device *dev)
1536 {
1537         struct gfar_private *priv = netdev_priv(dev);
1538         struct gfar __iomem *regs = NULL;
1539         int i;
1540
1541         for (i = 0; i < priv->num_grps; i++) {
1542                 regs = priv->gfargrp[i].regs;
1543                 /* Clear IEVENT */
1544                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1545
1546                 /* Initialize IMASK */
1547                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1548         }
1549
1550         regs = priv->gfargrp[0].regs;
1551         /* Init hash registers to zero */
1552         gfar_write(&regs->igaddr0, 0);
1553         gfar_write(&regs->igaddr1, 0);
1554         gfar_write(&regs->igaddr2, 0);
1555         gfar_write(&regs->igaddr3, 0);
1556         gfar_write(&regs->igaddr4, 0);
1557         gfar_write(&regs->igaddr5, 0);
1558         gfar_write(&regs->igaddr6, 0);
1559         gfar_write(&regs->igaddr7, 0);
1560
1561         gfar_write(&regs->gaddr0, 0);
1562         gfar_write(&regs->gaddr1, 0);
1563         gfar_write(&regs->gaddr2, 0);
1564         gfar_write(&regs->gaddr3, 0);
1565         gfar_write(&regs->gaddr4, 0);
1566         gfar_write(&regs->gaddr5, 0);
1567         gfar_write(&regs->gaddr6, 0);
1568         gfar_write(&regs->gaddr7, 0);
1569
1570         /* Zero out the rmon mib registers if it has them */
1571         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1572                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1573
1574                 /* Mask off the CAM interrupts */
1575                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1576                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1577         }
1578
1579         /* Initialize the max receive buffer length */
1580         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1581
1582         /* Initialize the Minimum Frame Length Register */
1583         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1584 }
1585
1586 static int __gfar_is_rx_idle(struct gfar_private *priv)
1587 {
1588         u32 res;
1589
1590         /* Normaly TSEC should not hang on GRS commands, so we should
1591          * actually wait for IEVENT_GRSC flag.
1592          */
1593         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1594                 return 0;
1595
1596         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1597          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1598          * and the Rx can be safely reset.
1599          */
1600         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1601         res &= 0x7f807f80;
1602         if ((res & 0xffff) == (res >> 16))
1603                 return 1;
1604
1605         return 0;
1606 }
1607
1608 /* Halt the receive and transmit queues */
1609 static void gfar_halt_nodisable(struct net_device *dev)
1610 {
1611         struct gfar_private *priv = netdev_priv(dev);
1612         struct gfar __iomem *regs = NULL;
1613         u32 tempval;
1614         int i;
1615
1616         for (i = 0; i < priv->num_grps; i++) {
1617                 regs = priv->gfargrp[i].regs;
1618                 /* Mask all interrupts */
1619                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1620
1621                 /* Clear all interrupts */
1622                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1623         }
1624
1625         regs = priv->gfargrp[0].regs;
1626         /* Stop the DMA, and wait for it to stop */
1627         tempval = gfar_read(&regs->dmactrl);
1628         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1629             (DMACTRL_GRS | DMACTRL_GTS)) {
1630                 int ret;
1631
1632                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1633                 gfar_write(&regs->dmactrl, tempval);
1634
1635                 do {
1636                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1637                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1638                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1639                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1640                                 ret = __gfar_is_rx_idle(priv);
1641                 } while (!ret);
1642         }
1643 }
1644
1645 /* Halt the receive and transmit queues */
1646 void gfar_halt(struct net_device *dev)
1647 {
1648         struct gfar_private *priv = netdev_priv(dev);
1649         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1650         u32 tempval;
1651
1652         gfar_halt_nodisable(dev);
1653
1654         /* Disable Rx and Tx */
1655         tempval = gfar_read(&regs->maccfg1);
1656         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1657         gfar_write(&regs->maccfg1, tempval);
1658 }
1659
1660 static void free_grp_irqs(struct gfar_priv_grp *grp)
1661 {
1662         free_irq(gfar_irq(grp, TX)->irq, grp);
1663         free_irq(gfar_irq(grp, RX)->irq, grp);
1664         free_irq(gfar_irq(grp, ER)->irq, grp);
1665 }
1666
1667 void stop_gfar(struct net_device *dev)
1668 {
1669         struct gfar_private *priv = netdev_priv(dev);
1670         unsigned long flags;
1671         int i;
1672
1673         phy_stop(priv->phydev);
1674
1675
1676         /* Lock it down */
1677         local_irq_save(flags);
1678         lock_tx_qs(priv);
1679         lock_rx_qs(priv);
1680
1681         gfar_halt(dev);
1682
1683         unlock_rx_qs(priv);
1684         unlock_tx_qs(priv);
1685         local_irq_restore(flags);
1686
1687         /* Free the IRQs */
1688         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1689                 for (i = 0; i < priv->num_grps; i++)
1690                         free_grp_irqs(&priv->gfargrp[i]);
1691         } else {
1692                 for (i = 0; i < priv->num_grps; i++)
1693                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1694                                  &priv->gfargrp[i]);
1695         }
1696
1697         free_skb_resources(priv);
1698 }
1699
1700 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1701 {
1702         struct txbd8 *txbdp;
1703         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1704         int i, j;
1705
1706         txbdp = tx_queue->tx_bd_base;
1707
1708         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1709                 if (!tx_queue->tx_skbuff[i])
1710                         continue;
1711
1712                 dma_unmap_single(priv->dev, txbdp->bufPtr,
1713                                  txbdp->length, DMA_TO_DEVICE);
1714                 txbdp->lstatus = 0;
1715                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1716                      j++) {
1717                         txbdp++;
1718                         dma_unmap_page(priv->dev, txbdp->bufPtr,
1719                                        txbdp->length, DMA_TO_DEVICE);
1720                 }
1721                 txbdp++;
1722                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1723                 tx_queue->tx_skbuff[i] = NULL;
1724         }
1725         kfree(tx_queue->tx_skbuff);
1726         tx_queue->tx_skbuff = NULL;
1727 }
1728
1729 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1730 {
1731         struct rxbd8 *rxbdp;
1732         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1733         int i;
1734
1735         rxbdp = rx_queue->rx_bd_base;
1736
1737         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1738                 if (rx_queue->rx_skbuff[i]) {
1739                         dma_unmap_single(priv->dev, rxbdp->bufPtr,
1740                                          priv->rx_buffer_size,
1741                                          DMA_FROM_DEVICE);
1742                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1743                         rx_queue->rx_skbuff[i] = NULL;
1744                 }
1745                 rxbdp->lstatus = 0;
1746                 rxbdp->bufPtr = 0;
1747                 rxbdp++;
1748         }
1749         kfree(rx_queue->rx_skbuff);
1750         rx_queue->rx_skbuff = NULL;
1751 }
1752
1753 /* If there are any tx skbs or rx skbs still around, free them.
1754  * Then free tx_skbuff and rx_skbuff
1755  */
1756 static void free_skb_resources(struct gfar_private *priv)
1757 {
1758         struct gfar_priv_tx_q *tx_queue = NULL;
1759         struct gfar_priv_rx_q *rx_queue = NULL;
1760         int i;
1761
1762         /* Go through all the buffer descriptors and free their data buffers */
1763         for (i = 0; i < priv->num_tx_queues; i++) {
1764                 struct netdev_queue *txq;
1765
1766                 tx_queue = priv->tx_queue[i];
1767                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1768                 if (tx_queue->tx_skbuff)
1769                         free_skb_tx_queue(tx_queue);
1770                 netdev_tx_reset_queue(txq);
1771         }
1772
1773         for (i = 0; i < priv->num_rx_queues; i++) {
1774                 rx_queue = priv->rx_queue[i];
1775                 if (rx_queue->rx_skbuff)
1776                         free_skb_rx_queue(rx_queue);
1777         }
1778
1779         dma_free_coherent(priv->dev,
1780                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1781                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1782                           priv->tx_queue[0]->tx_bd_base,
1783                           priv->tx_queue[0]->tx_bd_dma_base);
1784 }
1785
1786 void gfar_start(struct net_device *dev)
1787 {
1788         struct gfar_private *priv = netdev_priv(dev);
1789         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1790         u32 tempval;
1791         int i = 0;
1792
1793         /* Enable Rx and Tx in MACCFG1 */
1794         tempval = gfar_read(&regs->maccfg1);
1795         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1796         gfar_write(&regs->maccfg1, tempval);
1797
1798         /* Initialize DMACTRL to have WWR and WOP */
1799         tempval = gfar_read(&regs->dmactrl);
1800         tempval |= DMACTRL_INIT_SETTINGS;
1801         gfar_write(&regs->dmactrl, tempval);
1802
1803         /* Make sure we aren't stopped */
1804         tempval = gfar_read(&regs->dmactrl);
1805         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1806         gfar_write(&regs->dmactrl, tempval);
1807
1808         for (i = 0; i < priv->num_grps; i++) {
1809                 regs = priv->gfargrp[i].regs;
1810                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1811                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1812                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1813                 /* Unmask the interrupts we look for */
1814                 gfar_write(&regs->imask, IMASK_DEFAULT);
1815         }
1816
1817         dev->trans_start = jiffies; /* prevent tx timeout */
1818 }
1819
1820 void gfar_configure_coalescing(struct gfar_private *priv,
1821                                unsigned long tx_mask, unsigned long rx_mask)
1822 {
1823         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1824         u32 __iomem *baddr;
1825         int i = 0;
1826
1827         /* Backward compatible case ---- even if we enable
1828          * multiple queues, there's only single reg to program
1829          */
1830         gfar_write(&regs->txic, 0);
1831         if (likely(priv->tx_queue[0]->txcoalescing))
1832                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1833
1834         gfar_write(&regs->rxic, 0);
1835         if (unlikely(priv->rx_queue[0]->rxcoalescing))
1836                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1837
1838         if (priv->mode == MQ_MG_MODE) {
1839                 baddr = &regs->txic0;
1840                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1841                         gfar_write(baddr + i, 0);
1842                         if (likely(priv->tx_queue[i]->txcoalescing))
1843                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1844                 }
1845
1846                 baddr = &regs->rxic0;
1847                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1848                         gfar_write(baddr + i, 0);
1849                         if (likely(priv->rx_queue[i]->rxcoalescing))
1850                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1851                 }
1852         }
1853 }
1854
1855 static int register_grp_irqs(struct gfar_priv_grp *grp)
1856 {
1857         struct gfar_private *priv = grp->priv;
1858         struct net_device *dev = priv->ndev;
1859         int err;
1860
1861         /* If the device has multiple interrupts, register for
1862          * them.  Otherwise, only register for the one
1863          */
1864         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1865                 /* Install our interrupt handlers for Error,
1866                  * Transmit, and Receive
1867                  */
1868                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1869                                   gfar_irq(grp, ER)->name, grp);
1870                 if (err < 0) {
1871                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1872                                   gfar_irq(grp, ER)->irq);
1873
1874                         goto err_irq_fail;
1875                 }
1876                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1877                                   gfar_irq(grp, TX)->name, grp);
1878                 if (err < 0) {
1879                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1880                                   gfar_irq(grp, TX)->irq);
1881                         goto tx_irq_fail;
1882                 }
1883                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1884                                   gfar_irq(grp, RX)->name, grp);
1885                 if (err < 0) {
1886                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1887                                   gfar_irq(grp, RX)->irq);
1888                         goto rx_irq_fail;
1889                 }
1890         } else {
1891                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1892                                   gfar_irq(grp, TX)->name, grp);
1893                 if (err < 0) {
1894                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1895                                   gfar_irq(grp, TX)->irq);
1896                         goto err_irq_fail;
1897                 }
1898         }
1899
1900         return 0;
1901
1902 rx_irq_fail:
1903         free_irq(gfar_irq(grp, TX)->irq, grp);
1904 tx_irq_fail:
1905         free_irq(gfar_irq(grp, ER)->irq, grp);
1906 err_irq_fail:
1907         return err;
1908
1909 }
1910
1911 /* Bring the controller up and running */
1912 int startup_gfar(struct net_device *ndev)
1913 {
1914         struct gfar_private *priv = netdev_priv(ndev);
1915         struct gfar __iomem *regs = NULL;
1916         int err, i, j;
1917
1918         for (i = 0; i < priv->num_grps; i++) {
1919                 regs= priv->gfargrp[i].regs;
1920                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1921         }
1922
1923         regs= priv->gfargrp[0].regs;
1924         err = gfar_alloc_skb_resources(ndev);
1925         if (err)
1926                 return err;
1927
1928         gfar_init_mac(ndev);
1929
1930         for (i = 0; i < priv->num_grps; i++) {
1931                 err = register_grp_irqs(&priv->gfargrp[i]);
1932                 if (err) {
1933                         for (j = 0; j < i; j++)
1934                                 free_grp_irqs(&priv->gfargrp[j]);
1935                         goto irq_fail;
1936                 }
1937         }
1938
1939         /* Start the controller */
1940         gfar_start(ndev);
1941
1942         phy_start(priv->phydev);
1943
1944         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1945
1946         return 0;
1947
1948 irq_fail:
1949         free_skb_resources(priv);
1950         return err;
1951 }
1952
1953 /* Called when something needs to use the ethernet device
1954  * Returns 0 for success.
1955  */
1956 static int gfar_enet_open(struct net_device *dev)
1957 {
1958         struct gfar_private *priv = netdev_priv(dev);
1959         int err;
1960
1961         enable_napi(priv);
1962
1963         /* Initialize a bunch of registers */
1964         init_registers(dev);
1965
1966         gfar_set_mac_address(dev);
1967
1968         err = init_phy(dev);
1969
1970         if (err) {
1971                 disable_napi(priv);
1972                 return err;
1973         }
1974
1975         err = startup_gfar(dev);
1976         if (err) {
1977                 disable_napi(priv);
1978                 return err;
1979         }
1980
1981         netif_tx_start_all_queues(dev);
1982
1983         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1984
1985         return err;
1986 }
1987
1988 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1989 {
1990         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1991
1992         memset(fcb, 0, GMAC_FCB_LEN);
1993
1994         return fcb;
1995 }
1996
1997 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1998                                     int fcb_length)
1999 {
2000         /* If we're here, it's a IP packet with a TCP or UDP
2001          * payload.  We set it to checksum, using a pseudo-header
2002          * we provide
2003          */
2004         u8 flags = TXFCB_DEFAULT;
2005
2006         /* Tell the controller what the protocol is
2007          * And provide the already calculated phcs
2008          */
2009         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2010                 flags |= TXFCB_UDP;
2011                 fcb->phcs = udp_hdr(skb)->check;
2012         } else
2013                 fcb->phcs = tcp_hdr(skb)->check;
2014
2015         /* l3os is the distance between the start of the
2016          * frame (skb->data) and the start of the IP hdr.
2017          * l4os is the distance between the start of the
2018          * l3 hdr and the l4 hdr
2019          */
2020         fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2021         fcb->l4os = skb_network_header_len(skb);
2022
2023         fcb->flags = flags;
2024 }
2025
2026 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2027 {
2028         fcb->flags |= TXFCB_VLN;
2029         fcb->vlctl = vlan_tx_tag_get(skb);
2030 }
2031
2032 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2033                                       struct txbd8 *base, int ring_size)
2034 {
2035         struct txbd8 *new_bd = bdp + stride;
2036
2037         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2038 }
2039
2040 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2041                                       int ring_size)
2042 {
2043         return skip_txbd(bdp, 1, base, ring_size);
2044 }
2045
2046 /* This is called by the kernel when a frame is ready for transmission.
2047  * It is pointed to by the dev->hard_start_xmit function pointer
2048  */
2049 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2050 {
2051         struct gfar_private *priv = netdev_priv(dev);
2052         struct gfar_priv_tx_q *tx_queue = NULL;
2053         struct netdev_queue *txq;
2054         struct gfar __iomem *regs = NULL;
2055         struct txfcb *fcb = NULL;
2056         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2057         u32 lstatus;
2058         int i, rq = 0, do_tstamp = 0;
2059         u32 bufaddr;
2060         unsigned long flags;
2061         unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2062
2063         /* TOE=1 frames larger than 2500 bytes may see excess delays
2064          * before start of transmission.
2065          */
2066         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2067                      skb->ip_summed == CHECKSUM_PARTIAL &&
2068                      skb->len > 2500)) {
2069                 int ret;
2070
2071                 ret = skb_checksum_help(skb);
2072                 if (ret)
2073                         return ret;
2074         }
2075
2076         rq = skb->queue_mapping;
2077         tx_queue = priv->tx_queue[rq];
2078         txq = netdev_get_tx_queue(dev, rq);
2079         base = tx_queue->tx_bd_base;
2080         regs = tx_queue->grp->regs;
2081
2082         /* check if time stamp should be generated */
2083         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2084                      priv->hwts_tx_en)) {
2085                 do_tstamp = 1;
2086                 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2087         }
2088
2089         /* make space for additional header when fcb is needed */
2090         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2091              vlan_tx_tag_present(skb) ||
2092              unlikely(do_tstamp)) &&
2093             (skb_headroom(skb) < fcb_length)) {
2094                 struct sk_buff *skb_new;
2095
2096                 skb_new = skb_realloc_headroom(skb, fcb_length);
2097                 if (!skb_new) {
2098                         dev->stats.tx_errors++;
2099                         kfree_skb(skb);
2100                         return NETDEV_TX_OK;
2101                 }
2102
2103                 if (skb->sk)
2104                         skb_set_owner_w(skb_new, skb->sk);
2105                 consume_skb(skb);
2106                 skb = skb_new;
2107         }
2108
2109         /* total number of fragments in the SKB */
2110         nr_frags = skb_shinfo(skb)->nr_frags;
2111
2112         /* calculate the required number of TxBDs for this skb */
2113         if (unlikely(do_tstamp))
2114                 nr_txbds = nr_frags + 2;
2115         else
2116                 nr_txbds = nr_frags + 1;
2117
2118         /* check if there is space to queue this packet */
2119         if (nr_txbds > tx_queue->num_txbdfree) {
2120                 /* no space, stop the queue */
2121                 netif_tx_stop_queue(txq);
2122                 dev->stats.tx_fifo_errors++;
2123                 return NETDEV_TX_BUSY;
2124         }
2125
2126         /* Update transmit stats */
2127         tx_queue->stats.tx_bytes += skb->len;
2128         tx_queue->stats.tx_packets++;
2129
2130         txbdp = txbdp_start = tx_queue->cur_tx;
2131         lstatus = txbdp->lstatus;
2132
2133         /* Time stamp insertion requires one additional TxBD */
2134         if (unlikely(do_tstamp))
2135                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2136                                                  tx_queue->tx_ring_size);
2137
2138         if (nr_frags == 0) {
2139                 if (unlikely(do_tstamp))
2140                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2141                                                           TXBD_INTERRUPT);
2142                 else
2143                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2144         } else {
2145                 /* Place the fragment addresses and lengths into the TxBDs */
2146                 for (i = 0; i < nr_frags; i++) {
2147                         /* Point at the next BD, wrapping as needed */
2148                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2149
2150                         length = skb_shinfo(skb)->frags[i].size;
2151
2152                         lstatus = txbdp->lstatus | length |
2153                                   BD_LFLAG(TXBD_READY);
2154
2155                         /* Handle the last BD specially */
2156                         if (i == nr_frags - 1)
2157                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2158
2159                         bufaddr = skb_frag_dma_map(priv->dev,
2160                                                    &skb_shinfo(skb)->frags[i],
2161                                                    0,
2162                                                    length,
2163                                                    DMA_TO_DEVICE);
2164
2165                         /* set the TxBD length and buffer pointer */
2166                         txbdp->bufPtr = bufaddr;
2167                         txbdp->lstatus = lstatus;
2168                 }
2169
2170                 lstatus = txbdp_start->lstatus;
2171         }
2172
2173         /* Add TxPAL between FCB and frame if required */
2174         if (unlikely(do_tstamp)) {
2175                 skb_push(skb, GMAC_TXPAL_LEN);
2176                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2177         }
2178
2179         /* Set up checksumming */
2180         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2181                 fcb = gfar_add_fcb(skb);
2182                 /* as specified by errata */
2183                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2184                              ((unsigned long)fcb % 0x20) > 0x18)) {
2185                         __skb_pull(skb, GMAC_FCB_LEN);
2186                         skb_checksum_help(skb);
2187                 } else {
2188                         lstatus |= BD_LFLAG(TXBD_TOE);
2189                         gfar_tx_checksum(skb, fcb, fcb_length);
2190                 }
2191         }
2192
2193         if (vlan_tx_tag_present(skb)) {
2194                 if (unlikely(NULL == fcb)) {
2195                         fcb = gfar_add_fcb(skb);
2196                         lstatus |= BD_LFLAG(TXBD_TOE);
2197                 }
2198
2199                 gfar_tx_vlan(skb, fcb);
2200         }
2201
2202         /* Setup tx hardware time stamping if requested */
2203         if (unlikely(do_tstamp)) {
2204                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2205                 if (fcb == NULL)
2206                         fcb = gfar_add_fcb(skb);
2207                 fcb->ptp = 1;
2208                 lstatus |= BD_LFLAG(TXBD_TOE);
2209         }
2210
2211         txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
2212                                              skb_headlen(skb), DMA_TO_DEVICE);
2213
2214         /* If time stamping is requested one additional TxBD must be set up. The
2215          * first TxBD points to the FCB and must have a data length of
2216          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2217          * the full frame length.
2218          */
2219         if (unlikely(do_tstamp)) {
2220                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2221                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2222                                          (skb_headlen(skb) - fcb_length);
2223                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2224         } else {
2225                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2226         }
2227
2228         netdev_tx_sent_queue(txq, skb->len);
2229
2230         /* We can work in parallel with gfar_clean_tx_ring(), except
2231          * when modifying num_txbdfree. Note that we didn't grab the lock
2232          * when we were reading the num_txbdfree and checking for available
2233          * space, that's because outside of this function it can only grow,
2234          * and once we've got needed space, it cannot suddenly disappear.
2235          *
2236          * The lock also protects us from gfar_error(), which can modify
2237          * regs->tstat and thus retrigger the transfers, which is why we
2238          * also must grab the lock before setting ready bit for the first
2239          * to be transmitted BD.
2240          */
2241         spin_lock_irqsave(&tx_queue->txlock, flags);
2242
2243         /* The powerpc-specific eieio() is used, as wmb() has too strong
2244          * semantics (it requires synchronization between cacheable and
2245          * uncacheable mappings, which eieio doesn't provide and which we
2246          * don't need), thus requiring a more expensive sync instruction.  At
2247          * some point, the set of architecture-independent barrier functions
2248          * should be expanded to include weaker barriers.
2249          */
2250         eieio();
2251
2252         txbdp_start->lstatus = lstatus;
2253
2254         eieio(); /* force lstatus write before tx_skbuff */
2255
2256         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2257
2258         /* Update the current skb pointer to the next entry we will use
2259          * (wrapping if necessary)
2260          */
2261         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2262                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2263
2264         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2265
2266         /* reduce TxBD free count */
2267         tx_queue->num_txbdfree -= (nr_txbds);
2268
2269         /* If the next BD still needs to be cleaned up, then the bds
2270          * are full.  We need to tell the kernel to stop sending us stuff.
2271          */
2272         if (!tx_queue->num_txbdfree) {
2273                 netif_tx_stop_queue(txq);
2274
2275                 dev->stats.tx_fifo_errors++;
2276         }
2277
2278         /* Tell the DMA to go go go */
2279         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2280
2281         /* Unlock priv */
2282         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2283
2284         return NETDEV_TX_OK;
2285 }
2286
2287 /* Stops the kernel queue, and halts the controller */
2288 static int gfar_close(struct net_device *dev)
2289 {
2290         struct gfar_private *priv = netdev_priv(dev);
2291
2292         disable_napi(priv);
2293
2294         cancel_work_sync(&priv->reset_task);
2295         stop_gfar(dev);
2296
2297         /* Disconnect from the PHY */
2298         phy_disconnect(priv->phydev);
2299         priv->phydev = NULL;
2300
2301         netif_tx_stop_all_queues(dev);
2302
2303         return 0;
2304 }
2305
2306 /* Changes the mac address if the controller is not running. */
2307 static int gfar_set_mac_address(struct net_device *dev)
2308 {
2309         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2310
2311         return 0;
2312 }
2313
2314 /* Check if rx parser should be activated */
2315 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2316 {
2317         struct gfar __iomem *regs;
2318         u32 tempval;
2319
2320         regs = priv->gfargrp[0].regs;
2321
2322         tempval = gfar_read(&regs->rctrl);
2323         /* If parse is no longer required, then disable parser */
2324         if (tempval & RCTRL_REQ_PARSER) {
2325                 tempval |= RCTRL_PRSDEP_INIT;
2326                 priv->uses_rxfcb = 1;
2327         } else {
2328                 tempval &= ~RCTRL_PRSDEP_INIT;
2329                 priv->uses_rxfcb = 0;
2330         }
2331         gfar_write(&regs->rctrl, tempval);
2332 }
2333
2334 /* Enables and disables VLAN insertion/extraction */
2335 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2336 {
2337         struct gfar_private *priv = netdev_priv(dev);
2338         struct gfar __iomem *regs = NULL;
2339         unsigned long flags;
2340         u32 tempval;
2341
2342         regs = priv->gfargrp[0].regs;
2343         local_irq_save(flags);
2344         lock_rx_qs(priv);
2345
2346         if (features & NETIF_F_HW_VLAN_TX) {
2347                 /* Enable VLAN tag insertion */
2348                 tempval = gfar_read(&regs->tctrl);
2349                 tempval |= TCTRL_VLINS;
2350                 gfar_write(&regs->tctrl, tempval);
2351         } else {
2352                 /* Disable VLAN tag insertion */
2353                 tempval = gfar_read(&regs->tctrl);
2354                 tempval &= ~TCTRL_VLINS;
2355                 gfar_write(&regs->tctrl, tempval);
2356         }
2357
2358         if (features & NETIF_F_HW_VLAN_RX) {
2359                 /* Enable VLAN tag extraction */
2360                 tempval = gfar_read(&regs->rctrl);
2361                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2362                 gfar_write(&regs->rctrl, tempval);
2363                 priv->uses_rxfcb = 1;
2364         } else {
2365                 /* Disable VLAN tag extraction */
2366                 tempval = gfar_read(&regs->rctrl);
2367                 tempval &= ~RCTRL_VLEX;
2368                 gfar_write(&regs->rctrl, tempval);
2369
2370                 gfar_check_rx_parser_mode(priv);
2371         }
2372
2373         gfar_change_mtu(dev, dev->mtu);
2374
2375         unlock_rx_qs(priv);
2376         local_irq_restore(flags);
2377 }
2378
2379 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2380 {
2381         int tempsize, tempval;
2382         struct gfar_private *priv = netdev_priv(dev);
2383         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2384         int oldsize = priv->rx_buffer_size;
2385         int frame_size = new_mtu + ETH_HLEN;
2386
2387         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2388                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2389                 return -EINVAL;
2390         }
2391
2392         if (priv->uses_rxfcb)
2393                 frame_size += GMAC_FCB_LEN;
2394
2395         frame_size += priv->padding;
2396
2397         tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2398                    INCREMENTAL_BUFFER_SIZE;
2399
2400         /* Only stop and start the controller if it isn't already
2401          * stopped, and we changed something
2402          */
2403         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2404                 stop_gfar(dev);
2405
2406         priv->rx_buffer_size = tempsize;
2407
2408         dev->mtu = new_mtu;
2409
2410         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2411         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2412
2413         /* If the mtu is larger than the max size for standard
2414          * ethernet frames (ie, a jumbo frame), then set maccfg2
2415          * to allow huge frames, and to check the length
2416          */
2417         tempval = gfar_read(&regs->maccfg2);
2418
2419         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2420             gfar_has_errata(priv, GFAR_ERRATA_74))
2421                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2422         else
2423                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2424
2425         gfar_write(&regs->maccfg2, tempval);
2426
2427         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2428                 startup_gfar(dev);
2429
2430         return 0;
2431 }
2432
2433 /* gfar_reset_task gets scheduled when a packet has not been
2434  * transmitted after a set amount of time.
2435  * For now, assume that clearing out all the structures, and
2436  * starting over will fix the problem.
2437  */
2438 static void gfar_reset_task(struct work_struct *work)
2439 {
2440         struct gfar_private *priv = container_of(work, struct gfar_private,
2441                                                  reset_task);
2442         struct net_device *dev = priv->ndev;
2443
2444         if (dev->flags & IFF_UP) {
2445                 netif_tx_stop_all_queues(dev);
2446                 stop_gfar(dev);
2447                 startup_gfar(dev);
2448                 netif_tx_start_all_queues(dev);
2449         }
2450
2451         netif_tx_schedule_all(dev);
2452 }
2453
2454 static void gfar_timeout(struct net_device *dev)
2455 {
2456         struct gfar_private *priv = netdev_priv(dev);
2457
2458         dev->stats.tx_errors++;
2459         schedule_work(&priv->reset_task);
2460 }
2461
2462 static void gfar_align_skb(struct sk_buff *skb)
2463 {
2464         /* We need the data buffer to be aligned properly.  We will reserve
2465          * as many bytes as needed to align the data properly
2466          */
2467         skb_reserve(skb, RXBUF_ALIGNMENT -
2468                     (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2469 }
2470
2471 /* Interrupt Handler for Transmit complete */
2472 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2473 {
2474         struct net_device *dev = tx_queue->dev;
2475         struct netdev_queue *txq;
2476         struct gfar_private *priv = netdev_priv(dev);
2477         struct gfar_priv_rx_q *rx_queue = NULL;
2478         struct txbd8 *bdp, *next = NULL;
2479         struct txbd8 *lbdp = NULL;
2480         struct txbd8 *base = tx_queue->tx_bd_base;
2481         struct sk_buff *skb;
2482         int skb_dirtytx;
2483         int tx_ring_size = tx_queue->tx_ring_size;
2484         int frags = 0, nr_txbds = 0;
2485         int i;
2486         int howmany = 0;
2487         int tqi = tx_queue->qindex;
2488         unsigned int bytes_sent = 0;
2489         u32 lstatus;
2490         size_t buflen;
2491
2492         rx_queue = priv->rx_queue[tqi];
2493         txq = netdev_get_tx_queue(dev, tqi);
2494         bdp = tx_queue->dirty_tx;
2495         skb_dirtytx = tx_queue->skb_dirtytx;
2496
2497         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2498                 unsigned long flags;
2499
2500                 frags = skb_shinfo(skb)->nr_frags;
2501
2502                 /* When time stamping, one additional TxBD must be freed.
2503                  * Also, we need to dma_unmap_single() the TxPAL.
2504                  */
2505                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2506                         nr_txbds = frags + 2;
2507                 else
2508                         nr_txbds = frags + 1;
2509
2510                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2511
2512                 lstatus = lbdp->lstatus;
2513
2514                 /* Only clean completed frames */
2515                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2516                     (lstatus & BD_LENGTH_MASK))
2517                         break;
2518
2519                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2520                         next = next_txbd(bdp, base, tx_ring_size);
2521                         buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2522                 } else
2523                         buflen = bdp->length;
2524
2525                 dma_unmap_single(priv->dev, bdp->bufPtr,
2526                                  buflen, DMA_TO_DEVICE);
2527
2528                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2529                         struct skb_shared_hwtstamps shhwtstamps;
2530                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2531
2532                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2533                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2534                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2535                         skb_tstamp_tx(skb, &shhwtstamps);
2536                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2537                         bdp = next;
2538                 }
2539
2540                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2541                 bdp = next_txbd(bdp, base, tx_ring_size);
2542
2543                 for (i = 0; i < frags; i++) {
2544                         dma_unmap_page(priv->dev, bdp->bufPtr,
2545                                        bdp->length, DMA_TO_DEVICE);
2546                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2547                         bdp = next_txbd(bdp, base, tx_ring_size);
2548                 }
2549
2550                 bytes_sent += skb->len;
2551
2552                 dev_kfree_skb_any(skb);
2553
2554                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2555
2556                 skb_dirtytx = (skb_dirtytx + 1) &
2557                               TX_RING_MOD_MASK(tx_ring_size);
2558
2559                 howmany++;
2560                 spin_lock_irqsave(&tx_queue->txlock, flags);
2561                 tx_queue->num_txbdfree += nr_txbds;
2562                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2563         }
2564
2565         /* If we freed a buffer, we can restart transmission, if necessary */
2566         if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2567                 netif_wake_subqueue(dev, tqi);
2568
2569         /* Update dirty indicators */
2570         tx_queue->skb_dirtytx = skb_dirtytx;
2571         tx_queue->dirty_tx = bdp;
2572
2573         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2574
2575         return howmany;
2576 }
2577
2578 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2579 {
2580         unsigned long flags;
2581
2582         spin_lock_irqsave(&gfargrp->grplock, flags);
2583         if (napi_schedule_prep(&gfargrp->napi)) {
2584                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2585                 __napi_schedule(&gfargrp->napi);
2586         } else {
2587                 /* Clear IEVENT, so interrupts aren't called again
2588                  * because of the packets that have already arrived.
2589                  */
2590                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2591         }
2592         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2593
2594 }
2595
2596 /* Interrupt Handler for Transmit complete */
2597 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2598 {
2599         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2600         return IRQ_HANDLED;
2601 }
2602
2603 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2604                            struct sk_buff *skb)
2605 {
2606         struct net_device *dev = rx_queue->dev;
2607         struct gfar_private *priv = netdev_priv(dev);
2608         dma_addr_t buf;
2609
2610         buf = dma_map_single(priv->dev, skb->data,
2611                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2612         gfar_init_rxbdp(rx_queue, bdp, buf);
2613 }
2614
2615 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2616 {
2617         struct gfar_private *priv = netdev_priv(dev);
2618         struct sk_buff *skb;
2619
2620         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2621         if (!skb)
2622                 return NULL;
2623
2624         gfar_align_skb(skb);
2625
2626         return skb;
2627 }
2628
2629 struct sk_buff *gfar_new_skb(struct net_device *dev)
2630 {
2631         return gfar_alloc_skb(dev);
2632 }
2633
2634 static inline void count_errors(unsigned short status, struct net_device *dev)
2635 {
2636         struct gfar_private *priv = netdev_priv(dev);
2637         struct net_device_stats *stats = &dev->stats;
2638         struct gfar_extra_stats *estats = &priv->extra_stats;
2639
2640         /* If the packet was truncated, none of the other errors matter */
2641         if (status & RXBD_TRUNCATED) {
2642                 stats->rx_length_errors++;
2643
2644                 atomic64_inc(&estats->rx_trunc);
2645
2646                 return;
2647         }
2648         /* Count the errors, if there were any */
2649         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2650                 stats->rx_length_errors++;
2651
2652                 if (status & RXBD_LARGE)
2653                         atomic64_inc(&estats->rx_large);
2654                 else
2655                         atomic64_inc(&estats->rx_short);
2656         }
2657         if (status & RXBD_NONOCTET) {
2658                 stats->rx_frame_errors++;
2659                 atomic64_inc(&estats->rx_nonoctet);
2660         }
2661         if (status & RXBD_CRCERR) {
2662                 atomic64_inc(&estats->rx_crcerr);
2663                 stats->rx_crc_errors++;
2664         }
2665         if (status & RXBD_OVERRUN) {
2666                 atomic64_inc(&estats->rx_overrun);
2667                 stats->rx_crc_errors++;
2668         }
2669 }
2670
2671 irqreturn_t gfar_receive(int irq, void *grp_id)
2672 {
2673         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2674         return IRQ_HANDLED;
2675 }
2676
2677 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2678 {
2679         /* If valid headers were found, and valid sums
2680          * were verified, then we tell the kernel that no
2681          * checksumming is necessary.  Otherwise, it is [FIXME]
2682          */
2683         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2684                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2685         else
2686                 skb_checksum_none_assert(skb);
2687 }
2688
2689
2690 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2691 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2692                                int amount_pull, struct napi_struct *napi)
2693 {
2694         struct gfar_private *priv = netdev_priv(dev);
2695         struct rxfcb *fcb = NULL;
2696
2697         gro_result_t ret;
2698
2699         /* fcb is at the beginning if exists */
2700         fcb = (struct rxfcb *)skb->data;
2701
2702         /* Remove the FCB from the skb
2703          * Remove the padded bytes, if there are any
2704          */
2705         if (amount_pull) {
2706                 skb_record_rx_queue(skb, fcb->rq);
2707                 skb_pull(skb, amount_pull);
2708         }
2709
2710         /* Get receive timestamp from the skb */
2711         if (priv->hwts_rx_en) {
2712                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2713                 u64 *ns = (u64 *) skb->data;
2714
2715                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2716                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2717         }
2718
2719         if (priv->padding)
2720                 skb_pull(skb, priv->padding);
2721
2722         if (dev->features & NETIF_F_RXCSUM)
2723                 gfar_rx_checksum(skb, fcb);
2724
2725         /* Tell the skb what kind of packet this is */
2726         skb->protocol = eth_type_trans(skb, dev);
2727
2728         /* There's need to check for NETIF_F_HW_VLAN_RX here.
2729          * Even if vlan rx accel is disabled, on some chips
2730          * RXFCB_VLN is pseudo randomly set.
2731          */
2732         if (dev->features & NETIF_F_HW_VLAN_RX &&
2733             fcb->flags & RXFCB_VLN)
2734                 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2735
2736         /* Send the packet up the stack */
2737         ret = napi_gro_receive(napi, skb);
2738
2739         if (unlikely(GRO_DROP == ret))
2740                 atomic64_inc(&priv->extra_stats.kernel_dropped);
2741 }
2742
2743 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2744  * until the budget/quota has been reached. Returns the number
2745  * of frames handled
2746  */
2747 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2748 {
2749         struct net_device *dev = rx_queue->dev;
2750         struct rxbd8 *bdp, *base;
2751         struct sk_buff *skb;
2752         int pkt_len;
2753         int amount_pull;
2754         int howmany = 0;
2755         struct gfar_private *priv = netdev_priv(dev);
2756
2757         /* Get the first full descriptor */
2758         bdp = rx_queue->cur_rx;
2759         base = rx_queue->rx_bd_base;
2760
2761         amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2762
2763         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2764                 struct sk_buff *newskb;
2765
2766                 rmb();
2767
2768                 /* Add another skb for the future */
2769                 newskb = gfar_new_skb(dev);
2770
2771                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2772
2773                 dma_unmap_single(priv->dev, bdp->bufPtr,
2774                                  priv->rx_buffer_size, DMA_FROM_DEVICE);
2775
2776                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2777                              bdp->length > priv->rx_buffer_size))
2778                         bdp->status = RXBD_LARGE;
2779
2780                 /* We drop the frame if we failed to allocate a new buffer */
2781                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2782                              bdp->status & RXBD_ERR)) {
2783                         count_errors(bdp->status, dev);
2784
2785                         if (unlikely(!newskb))
2786                                 newskb = skb;
2787                         else if (skb)
2788                                 dev_kfree_skb(skb);
2789                 } else {
2790                         /* Increment the number of packets */
2791                         rx_queue->stats.rx_packets++;
2792                         howmany++;
2793
2794                         if (likely(skb)) {
2795                                 pkt_len = bdp->length - ETH_FCS_LEN;
2796                                 /* Remove the FCS from the packet length */
2797                                 skb_put(skb, pkt_len);
2798                                 rx_queue->stats.rx_bytes += pkt_len;
2799                                 skb_record_rx_queue(skb, rx_queue->qindex);
2800                                 gfar_process_frame(dev, skb, amount_pull,
2801                                                    &rx_queue->grp->napi);
2802
2803                         } else {
2804                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2805                                 rx_queue->stats.rx_dropped++;
2806                                 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2807                         }
2808
2809                 }
2810
2811                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2812
2813                 /* Setup the new bdp */
2814                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2815
2816                 /* Update to the next pointer */
2817                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2818
2819                 /* update to point at the next skb */
2820                 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2821                                       RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2822         }
2823
2824         /* Update the current rxbd pointer to be the next one */
2825         rx_queue->cur_rx = bdp;
2826
2827         return howmany;
2828 }
2829
2830 static int gfar_poll(struct napi_struct *napi, int budget)
2831 {
2832         struct gfar_priv_grp *gfargrp =
2833                 container_of(napi, struct gfar_priv_grp, napi);
2834         struct gfar_private *priv = gfargrp->priv;
2835         struct gfar __iomem *regs = gfargrp->regs;
2836         struct gfar_priv_tx_q *tx_queue = NULL;
2837         struct gfar_priv_rx_q *rx_queue = NULL;
2838         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2839         int tx_cleaned = 0, i, left_over_budget = budget;
2840         unsigned long serviced_queues = 0;
2841         int num_queues = 0;
2842
2843         num_queues = gfargrp->num_rx_queues;
2844         budget_per_queue = budget/num_queues;
2845
2846         /* Clear IEVENT, so interrupts aren't called again
2847          * because of the packets that have already arrived
2848          */
2849         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2850
2851         while (num_queues && left_over_budget) {
2852                 budget_per_queue = left_over_budget/num_queues;
2853                 left_over_budget = 0;
2854
2855                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2856                         if (test_bit(i, &serviced_queues))
2857                                 continue;
2858                         rx_queue = priv->rx_queue[i];
2859                         tx_queue = priv->tx_queue[rx_queue->qindex];
2860
2861                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2862                         rx_cleaned_per_queue =
2863                                 gfar_clean_rx_ring(rx_queue, budget_per_queue);
2864                         rx_cleaned += rx_cleaned_per_queue;
2865                         if (rx_cleaned_per_queue < budget_per_queue) {
2866                                 left_over_budget = left_over_budget +
2867                                         (budget_per_queue -
2868                                          rx_cleaned_per_queue);
2869                                 set_bit(i, &serviced_queues);
2870                                 num_queues--;
2871                         }
2872                 }
2873         }
2874
2875         if (tx_cleaned)
2876                 return budget;
2877
2878         if (rx_cleaned < budget) {
2879                 napi_complete(napi);
2880
2881                 /* Clear the halt bit in RSTAT */
2882                 gfar_write(&regs->rstat, gfargrp->rstat);
2883
2884                 gfar_write(&regs->imask, IMASK_DEFAULT);
2885
2886                 /* If we are coalescing interrupts, update the timer
2887                  * Otherwise, clear it
2888                  */
2889                 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2890                                           gfargrp->tx_bit_map);
2891         }
2892
2893         return rx_cleaned;
2894 }
2895
2896 #ifdef CONFIG_NET_POLL_CONTROLLER
2897 /* Polling 'interrupt' - used by things like netconsole to send skbs
2898  * without having to re-enable interrupts. It's not called while
2899  * the interrupt routine is executing.
2900  */
2901 static void gfar_netpoll(struct net_device *dev)
2902 {
2903         struct gfar_private *priv = netdev_priv(dev);
2904         int i;
2905
2906         /* If the device has multiple interrupts, run tx/rx */
2907         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2908                 for (i = 0; i < priv->num_grps; i++) {
2909                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
2910
2911                         disable_irq(gfar_irq(grp, TX)->irq);
2912                         disable_irq(gfar_irq(grp, RX)->irq);
2913                         disable_irq(gfar_irq(grp, ER)->irq);
2914                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2915                         enable_irq(gfar_irq(grp, ER)->irq);
2916                         enable_irq(gfar_irq(grp, RX)->irq);
2917                         enable_irq(gfar_irq(grp, TX)->irq);
2918                 }
2919         } else {
2920                 for (i = 0; i < priv->num_grps; i++) {
2921                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
2922
2923                         disable_irq(gfar_irq(grp, TX)->irq);
2924                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2925                         enable_irq(gfar_irq(grp, TX)->irq);
2926                 }
2927         }
2928 }
2929 #endif
2930
2931 /* The interrupt handler for devices with one interrupt */
2932 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2933 {
2934         struct gfar_priv_grp *gfargrp = grp_id;
2935
2936         /* Save ievent for future reference */
2937         u32 events = gfar_read(&gfargrp->regs->ievent);
2938
2939         /* Check for reception */
2940         if (events & IEVENT_RX_MASK)
2941                 gfar_receive(irq, grp_id);
2942
2943         /* Check for transmit completion */
2944         if (events & IEVENT_TX_MASK)
2945                 gfar_transmit(irq, grp_id);
2946
2947         /* Check for errors */
2948         if (events & IEVENT_ERR_MASK)
2949                 gfar_error(irq, grp_id);
2950
2951         return IRQ_HANDLED;
2952 }
2953
2954 /* Called every time the controller might need to be made
2955  * aware of new link state.  The PHY code conveys this
2956  * information through variables in the phydev structure, and this
2957  * function converts those variables into the appropriate
2958  * register values, and can bring down the device if needed.
2959  */
2960 static void adjust_link(struct net_device *dev)
2961 {
2962         struct gfar_private *priv = netdev_priv(dev);
2963         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2964         unsigned long flags;
2965         struct phy_device *phydev = priv->phydev;
2966         int new_state = 0;
2967
2968         local_irq_save(flags);
2969         lock_tx_qs(priv);
2970
2971         if (phydev->link) {
2972                 u32 tempval = gfar_read(&regs->maccfg2);
2973                 u32 ecntrl = gfar_read(&regs->ecntrl);
2974
2975                 /* Now we make sure that we can be in full duplex mode.
2976                  * If not, we operate in half-duplex mode.
2977                  */
2978                 if (phydev->duplex != priv->oldduplex) {
2979                         new_state = 1;
2980                         if (!(phydev->duplex))
2981                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2982                         else
2983                                 tempval |= MACCFG2_FULL_DUPLEX;
2984
2985                         priv->oldduplex = phydev->duplex;
2986                 }
2987
2988                 if (phydev->speed != priv->oldspeed) {
2989                         new_state = 1;
2990                         switch (phydev->speed) {
2991                         case 1000:
2992                                 tempval =
2993                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2994
2995                                 ecntrl &= ~(ECNTRL_R100);
2996                                 break;
2997                         case 100:
2998                         case 10:
2999                                 tempval =
3000                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3001
3002                                 /* Reduced mode distinguishes
3003                                  * between 10 and 100
3004                                  */
3005                                 if (phydev->speed == SPEED_100)
3006                                         ecntrl |= ECNTRL_R100;
3007                                 else
3008                                         ecntrl &= ~(ECNTRL_R100);
3009                                 break;
3010                         default:
3011                                 netif_warn(priv, link, dev,
3012                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3013                                            phydev->speed);
3014                                 break;
3015                         }
3016
3017                         priv->oldspeed = phydev->speed;
3018                 }
3019
3020                 gfar_write(&regs->maccfg2, tempval);
3021                 gfar_write(&regs->ecntrl, ecntrl);
3022
3023                 if (!priv->oldlink) {
3024                         new_state = 1;
3025                         priv->oldlink = 1;
3026                 }
3027         } else if (priv->oldlink) {
3028                 new_state = 1;
3029                 priv->oldlink = 0;
3030                 priv->oldspeed = 0;
3031                 priv->oldduplex = -1;
3032         }
3033
3034         if (new_state && netif_msg_link(priv))
3035                 phy_print_status(phydev);
3036         unlock_tx_qs(priv);
3037         local_irq_restore(flags);
3038 }
3039
3040 /* Update the hash table based on the current list of multicast
3041  * addresses we subscribe to.  Also, change the promiscuity of
3042  * the device based on the flags (this function is called
3043  * whenever dev->flags is changed
3044  */
3045 static void gfar_set_multi(struct net_device *dev)
3046 {
3047         struct netdev_hw_addr *ha;
3048         struct gfar_private *priv = netdev_priv(dev);
3049         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3050         u32 tempval;
3051
3052         if (dev->flags & IFF_PROMISC) {
3053                 /* Set RCTRL to PROM */
3054                 tempval = gfar_read(&regs->rctrl);
3055                 tempval |= RCTRL_PROM;
3056                 gfar_write(&regs->rctrl, tempval);
3057         } else {
3058                 /* Set RCTRL to not PROM */
3059                 tempval = gfar_read(&regs->rctrl);
3060                 tempval &= ~(RCTRL_PROM);
3061                 gfar_write(&regs->rctrl, tempval);
3062         }
3063
3064         if (dev->flags & IFF_ALLMULTI) {
3065                 /* Set the hash to rx all multicast frames */
3066                 gfar_write(&regs->igaddr0, 0xffffffff);
3067                 gfar_write(&regs->igaddr1, 0xffffffff);
3068                 gfar_write(&regs->igaddr2, 0xffffffff);
3069                 gfar_write(&regs->igaddr3, 0xffffffff);
3070                 gfar_write(&regs->igaddr4, 0xffffffff);
3071                 gfar_write(&regs->igaddr5, 0xffffffff);
3072                 gfar_write(&regs->igaddr6, 0xffffffff);
3073                 gfar_write(&regs->igaddr7, 0xffffffff);
3074                 gfar_write(&regs->gaddr0, 0xffffffff);
3075                 gfar_write(&regs->gaddr1, 0xffffffff);
3076                 gfar_write(&regs->gaddr2, 0xffffffff);
3077                 gfar_write(&regs->gaddr3, 0xffffffff);
3078                 gfar_write(&regs->gaddr4, 0xffffffff);
3079                 gfar_write(&regs->gaddr5, 0xffffffff);
3080                 gfar_write(&regs->gaddr6, 0xffffffff);
3081                 gfar_write(&regs->gaddr7, 0xffffffff);
3082         } else {
3083                 int em_num;
3084                 int idx;
3085
3086                 /* zero out the hash */
3087                 gfar_write(&regs->igaddr0, 0x0);
3088                 gfar_write(&regs->igaddr1, 0x0);
3089                 gfar_write(&regs->igaddr2, 0x0);
3090                 gfar_write(&regs->igaddr3, 0x0);
3091                 gfar_write(&regs->igaddr4, 0x0);
3092                 gfar_write(&regs->igaddr5, 0x0);
3093                 gfar_write(&regs->igaddr6, 0x0);
3094                 gfar_write(&regs->igaddr7, 0x0);
3095                 gfar_write(&regs->gaddr0, 0x0);
3096                 gfar_write(&regs->gaddr1, 0x0);
3097                 gfar_write(&regs->gaddr2, 0x0);
3098                 gfar_write(&regs->gaddr3, 0x0);
3099                 gfar_write(&regs->gaddr4, 0x0);
3100                 gfar_write(&regs->gaddr5, 0x0);
3101                 gfar_write(&regs->gaddr6, 0x0);
3102                 gfar_write(&regs->gaddr7, 0x0);
3103
3104                 /* If we have extended hash tables, we need to
3105                  * clear the exact match registers to prepare for
3106                  * setting them
3107                  */
3108                 if (priv->extended_hash) {
3109                         em_num = GFAR_EM_NUM + 1;
3110                         gfar_clear_exact_match(dev);
3111                         idx = 1;
3112                 } else {
3113                         idx = 0;
3114                         em_num = 0;
3115                 }
3116
3117                 if (netdev_mc_empty(dev))
3118                         return;
3119
3120                 /* Parse the list, and set the appropriate bits */
3121                 netdev_for_each_mc_addr(ha, dev) {
3122                         if (idx < em_num) {
3123                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3124                                 idx++;
3125                         } else
3126                                 gfar_set_hash_for_addr(dev, ha->addr);
3127                 }
3128         }
3129 }
3130
3131
3132 /* Clears each of the exact match registers to zero, so they
3133  * don't interfere with normal reception
3134  */
3135 static void gfar_clear_exact_match(struct net_device *dev)
3136 {
3137         int idx;
3138         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3139
3140         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3141                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3142 }
3143
3144 /* Set the appropriate hash bit for the given addr */
3145 /* The algorithm works like so:
3146  * 1) Take the Destination Address (ie the multicast address), and
3147  * do a CRC on it (little endian), and reverse the bits of the
3148  * result.
3149  * 2) Use the 8 most significant bits as a hash into a 256-entry
3150  * table.  The table is controlled through 8 32-bit registers:
3151  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3152  * gaddr7.  This means that the 3 most significant bits in the
3153  * hash index which gaddr register to use, and the 5 other bits
3154  * indicate which bit (assuming an IBM numbering scheme, which
3155  * for PowerPC (tm) is usually the case) in the register holds
3156  * the entry.
3157  */
3158 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3159 {
3160         u32 tempval;
3161         struct gfar_private *priv = netdev_priv(dev);
3162         u32 result = ether_crc(ETH_ALEN, addr);
3163         int width = priv->hash_width;
3164         u8 whichbit = (result >> (32 - width)) & 0x1f;
3165         u8 whichreg = result >> (32 - width + 5);
3166         u32 value = (1 << (31-whichbit));
3167
3168         tempval = gfar_read(priv->hash_regs[whichreg]);
3169         tempval |= value;
3170         gfar_write(priv->hash_regs[whichreg], tempval);
3171 }
3172
3173
3174 /* There are multiple MAC Address register pairs on some controllers
3175  * This function sets the numth pair to a given address
3176  */
3177 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3178                                   const u8 *addr)
3179 {
3180         struct gfar_private *priv = netdev_priv(dev);
3181         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3182         int idx;
3183         char tmpbuf[ETH_ALEN];
3184         u32 tempval;
3185         u32 __iomem *macptr = &regs->macstnaddr1;
3186
3187         macptr += num*2;
3188
3189         /* Now copy it into the mac registers backwards, cuz
3190          * little endian is silly
3191          */
3192         for (idx = 0; idx < ETH_ALEN; idx++)
3193                 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3194
3195         gfar_write(macptr, *((u32 *) (tmpbuf)));
3196
3197         tempval = *((u32 *) (tmpbuf + 4));
3198
3199         gfar_write(macptr+1, tempval);
3200 }
3201
3202 /* GFAR error interrupt handler */
3203 static irqreturn_t gfar_error(int irq, void *grp_id)
3204 {
3205         struct gfar_priv_grp *gfargrp = grp_id;
3206         struct gfar __iomem *regs = gfargrp->regs;
3207         struct gfar_private *priv= gfargrp->priv;
3208         struct net_device *dev = priv->ndev;
3209
3210         /* Save ievent for future reference */
3211         u32 events = gfar_read(&regs->ievent);
3212
3213         /* Clear IEVENT */
3214         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3215
3216         /* Magic Packet is not an error. */
3217         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3218             (events & IEVENT_MAG))
3219                 events &= ~IEVENT_MAG;
3220
3221         /* Hmm... */
3222         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3223                 netdev_dbg(dev,
3224                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3225                            events, gfar_read(&regs->imask));
3226
3227         /* Update the error counters */
3228         if (events & IEVENT_TXE) {
3229                 dev->stats.tx_errors++;
3230
3231                 if (events & IEVENT_LC)
3232                         dev->stats.tx_window_errors++;
3233                 if (events & IEVENT_CRL)
3234                         dev->stats.tx_aborted_errors++;
3235                 if (events & IEVENT_XFUN) {
3236                         unsigned long flags;
3237
3238                         netif_dbg(priv, tx_err, dev,
3239                                   "TX FIFO underrun, packet dropped\n");
3240                         dev->stats.tx_dropped++;
3241                         atomic64_inc(&priv->extra_stats.tx_underrun);
3242
3243                         local_irq_save(flags);
3244                         lock_tx_qs(priv);
3245
3246                         /* Reactivate the Tx Queues */
3247                         gfar_write(&regs->tstat, gfargrp->tstat);
3248
3249                         unlock_tx_qs(priv);
3250                         local_irq_restore(flags);
3251                 }
3252                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3253         }
3254         if (events & IEVENT_BSY) {
3255                 dev->stats.rx_errors++;
3256                 atomic64_inc(&priv->extra_stats.rx_bsy);
3257
3258                 gfar_receive(irq, grp_id);
3259
3260                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3261                           gfar_read(&regs->rstat));
3262         }
3263         if (events & IEVENT_BABR) {
3264                 dev->stats.rx_errors++;
3265                 atomic64_inc(&priv->extra_stats.rx_babr);
3266
3267                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3268         }
3269         if (events & IEVENT_EBERR) {
3270                 atomic64_inc(&priv->extra_stats.eberr);
3271                 netif_dbg(priv, rx_err, dev, "bus error\n");
3272         }
3273         if (events & IEVENT_RXC)
3274                 netif_dbg(priv, rx_status, dev, "control frame\n");
3275
3276         if (events & IEVENT_BABT) {
3277                 atomic64_inc(&priv->extra_stats.tx_babt);
3278                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3279         }
3280         return IRQ_HANDLED;
3281 }
3282
3283 static struct of_device_id gfar_match[] =
3284 {
3285         {
3286                 .type = "network",
3287                 .compatible = "gianfar",
3288         },
3289         {
3290                 .compatible = "fsl,etsec2",
3291         },
3292         {},
3293 };
3294 MODULE_DEVICE_TABLE(of, gfar_match);
3295
3296 /* Structure for a device driver */
3297 static struct platform_driver gfar_driver = {
3298         .driver = {
3299                 .name = "fsl-gianfar",
3300                 .owner = THIS_MODULE,
3301                 .pm = GFAR_PM_OPS,
3302                 .of_match_table = gfar_match,
3303         },
3304         .probe = gfar_probe,
3305         .remove = gfar_remove,
3306 };
3307
3308 module_platform_driver(gfar_driver);