drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/of_mdio.h>
  82 #include <linux/of_platform.h>
  83 #include <linux/ip.h>
  84 #include <linux/tcp.h>
  85 #include <linux/udp.h>
  86 #include <linux/in.h>
  87 #include <linux/net_tstamp.h>
  88
  89 #include <asm/io.h>
  90 #include <asm/reg.h>
  91 #include <asm/irq.h>
  92 #include <asm/uaccess.h>
  93 #include <linux/module.h>
  94 #include <linux/dma-mapping.h>
  95 #include <linux/crc32.h>
  96 #include <linux/mii.h>
  97 #include <linux/phy.h>
  98 #include <linux/phy_fixed.h>
  99 #include <linux/of.h>
 100 #include <linux/of_net.h>
 101
 102 #include "gianfar.h"
 103
 104 #define TX_TIMEOUT      (1*HZ)
 105
 106 const char gfar_driver_version[] = "1.3";
 107
 108 static int gfar_enet_open(struct net_device *dev);
 109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 110 static void gfar_reset_task(struct work_struct *work);
 111 static void gfar_timeout(struct net_device *dev);
 112 static int gfar_close(struct net_device *dev);
 113 struct sk_buff *gfar_new_skb(struct net_device *dev);
 114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 115                            struct sk_buff *skb);
 116 static int gfar_set_mac_address(struct net_device *dev);
 117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 118 static irqreturn_t gfar_error(int irq, void *dev_id);
 119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 121 static void adjust_link(struct net_device *dev);
 122 static void init_registers(struct net_device *dev);
 123 static int init_phy(struct net_device *dev);
 124 static int gfar_probe(struct platform_device *ofdev);
 125 static int gfar_remove(struct platform_device *ofdev);
 126 static void free_skb_resources(struct gfar_private *priv);
 127 static void gfar_set_multi(struct net_device *dev);
 128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 129 static void gfar_configure_serdes(struct net_device *dev);
 130 static int gfar_poll(struct napi_struct *napi, int budget);
 131 static int gfar_poll_sq(struct napi_struct *napi, int budget);
 132 #ifdef CONFIG_NET_POLL_CONTROLLER
 133 static void gfar_netpoll(struct net_device *dev);
 134 #endif
 135 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 136 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 137 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 138                                int amount_pull, struct napi_struct *napi);
 139 void gfar_halt(struct net_device *dev);
 140 static void gfar_halt_nodisable(struct net_device *dev);
 141 void gfar_start(struct net_device *dev);
 142 static void gfar_clear_exact_match(struct net_device *dev);
 143 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 144                                   const u8 *addr);
 145 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 146
 147 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 148 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 149 MODULE_LICENSE("GPL");
 150
 151 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 152                             dma_addr_t buf)
 153 {
 154         u32 lstatus;
 155
 156         bdp->bufPtr = buf;
 157
 158         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 159         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 160                 lstatus |= BD_LFLAG(RXBD_WRAP);
 161
 162         eieio();
 163
 164         bdp->lstatus = lstatus;
 165 }
 166
 167 static int gfar_init_bds(struct net_device *ndev)
 168 {
 169         struct gfar_private *priv = netdev_priv(ndev);
 170         struct gfar_priv_tx_q *tx_queue = NULL;
 171         struct gfar_priv_rx_q *rx_queue = NULL;
 172         struct txbd8 *txbdp;
 173         struct rxbd8 *rxbdp;
 174         int i, j;
 175
 176         for (i = 0; i < priv->num_tx_queues; i++) {
 177                 tx_queue = priv->tx_queue[i];
 178                 /* Initialize some variables in our dev structure */
 179                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 180                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 181                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 182                 tx_queue->skb_curtx = 0;
 183                 tx_queue->skb_dirtytx = 0;
 184
 185                 /* Initialize Transmit Descriptor Ring */
 186                 txbdp = tx_queue->tx_bd_base;
 187                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 188                         txbdp->lstatus = 0;
 189                         txbdp->bufPtr = 0;
 190                         txbdp++;
 191                 }
 192
 193                 /* Set the last descriptor in the ring to indicate wrap */
 194                 txbdp--;
 195                 txbdp->status |= TXBD_WRAP;
 196         }
 197
 198         for (i = 0; i < priv->num_rx_queues; i++) {
 199                 rx_queue = priv->rx_queue[i];
 200                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 201                 rx_queue->skb_currx = 0;
 202                 rxbdp = rx_queue->rx_bd_base;
 203
 204                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 205                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 206
 207                         if (skb) {
 208                                 gfar_init_rxbdp(rx_queue, rxbdp,
 209                                                 rxbdp->bufPtr);
 210                         } else {
 211                                 skb = gfar_new_skb(ndev);
 212                                 if (!skb) {
 213                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 214                                         return -ENOMEM;
 215                                 }
 216                                 rx_queue->rx_skbuff[j] = skb;
 217
 218                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 219                         }
 220
 221                         rxbdp++;
 222                 }
 223
 224         }
 225
 226         return 0;
 227 }
 228
 229 static int gfar_alloc_skb_resources(struct net_device *ndev)
 230 {
 231         void *vaddr;
 232         dma_addr_t addr;
 233         int i, j, k;
 234         struct gfar_private *priv = netdev_priv(ndev);
 235         struct device *dev = priv->dev;
 236         struct gfar_priv_tx_q *tx_queue = NULL;
 237         struct gfar_priv_rx_q *rx_queue = NULL;
 238
 239         priv->total_tx_ring_size = 0;
 240         for (i = 0; i < priv->num_tx_queues; i++)
 241                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 242
 243         priv->total_rx_ring_size = 0;
 244         for (i = 0; i < priv->num_rx_queues; i++)
 245                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 246
 247         /* Allocate memory for the buffer descriptors */
 248         vaddr = dma_alloc_coherent(dev,
 249                                    (priv->total_tx_ring_size *
 250                                     sizeof(struct txbd8)) +
 251                                    (priv->total_rx_ring_size *
 252                                     sizeof(struct rxbd8)),
 253                                    &addr, GFP_KERNEL);
 254         if (!vaddr)
 255                 return -ENOMEM;
 256
 257         for (i = 0; i < priv->num_tx_queues; i++) {
 258                 tx_queue = priv->tx_queue[i];
 259                 tx_queue->tx_bd_base = vaddr;
 260                 tx_queue->tx_bd_dma_base = addr;
 261                 tx_queue->dev = ndev;
 262                 /* enet DMA only understands physical addresses */
 263                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 264                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 265         }
 266
 267         /* Start the rx descriptor ring where the tx ring leaves off */
 268         for (i = 0; i < priv->num_rx_queues; i++) {
 269                 rx_queue = priv->rx_queue[i];
 270                 rx_queue->rx_bd_base = vaddr;
 271                 rx_queue->rx_bd_dma_base = addr;
 272                 rx_queue->dev = ndev;
 273                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 274                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 275         }
 276
 277         /* Setup the skbuff rings */
 278         for (i = 0; i < priv->num_tx_queues; i++) {
 279                 tx_queue = priv->tx_queue[i];
 280                 tx_queue->tx_skbuff =
 281                         kmalloc_array(tx_queue->tx_ring_size,
 282                                       sizeof(*tx_queue->tx_skbuff),
 283                                       GFP_KERNEL);
 284                 if (!tx_queue->tx_skbuff)
 285                         goto cleanup;
 286
 287                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 288                         tx_queue->tx_skbuff[k] = NULL;
 289         }
 290
 291         for (i = 0; i < priv->num_rx_queues; i++) {
 292                 rx_queue = priv->rx_queue[i];
 293                 rx_queue->rx_skbuff =
 294                         kmalloc_array(rx_queue->rx_ring_size,
 295                                       sizeof(*rx_queue->rx_skbuff),
 296                                       GFP_KERNEL);
 297                 if (!rx_queue->rx_skbuff)
 298                         goto cleanup;
 299
 300                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 301                         rx_queue->rx_skbuff[j] = NULL;
 302         }
 303
 304         if (gfar_init_bds(ndev))
 305                 goto cleanup;
 306
 307         return 0;
 308
 309 cleanup:
 310         free_skb_resources(priv);
 311         return -ENOMEM;
 312 }
 313
 314 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 315 {
 316         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 317         u32 __iomem *baddr;
 318         int i;
 319
 320         baddr = &regs->tbase0;
 321         for (i = 0; i < priv->num_tx_queues; i++) {
 322                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 323                 baddr += 2;
 324         }
 325
 326         baddr = &regs->rbase0;
 327         for (i = 0; i < priv->num_rx_queues; i++) {
 328                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 329                 baddr += 2;
 330         }
 331 }
 332
 333 static void gfar_init_mac(struct net_device *ndev)
 334 {
 335         struct gfar_private *priv = netdev_priv(ndev);
 336         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 337         u32 rctrl = 0;
 338         u32 tctrl = 0;
 339         u32 attrs = 0;
 340
 341         /* write the tx/rx base registers */
 342         gfar_init_tx_rx_base(priv);
 343
 344         /* Configure the coalescing support */
 345         gfar_configure_coalescing_all(priv);
 346
 347         /* set this when rx hw offload (TOE) functions are being used */
 348         priv->uses_rxfcb = 0;
 349
 350         if (priv->rx_filer_enable) {
 351                 rctrl |= RCTRL_FILREN;
 352                 /* Program the RIR0 reg with the required distribution */
 353                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 354         }
 355
 356         /* Restore PROMISC mode */
 357         if (ndev->flags & IFF_PROMISC)
 358                 rctrl |= RCTRL_PROM;
 359
 360         if (ndev->features & NETIF_F_RXCSUM) {
 361                 rctrl |= RCTRL_CHECKSUMMING;
 362                 priv->uses_rxfcb = 1;
 363         }
 364
 365         if (priv->extended_hash) {
 366                 rctrl |= RCTRL_EXTHASH;
 367
 368                 gfar_clear_exact_match(ndev);
 369                 rctrl |= RCTRL_EMEN;
 370         }
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Insert receive time stamps into padding alignment bytes */
 378         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 379                 rctrl &= ~RCTRL_PAL_MASK;
 380                 rctrl |= RCTRL_PADDING(8);
 381                 priv->padding = 8;
 382         }
 383
 384         /* Enable HW time stamping if requested from user space */
 385         if (priv->hwts_rx_en) {
 386                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 387                 priv->uses_rxfcb = 1;
 388         }
 389
 390         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) {
 391                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 392                 priv->uses_rxfcb = 1;
 393         }
 394
 395         /* Init rctrl based on our settings */
 396         gfar_write(&regs->rctrl, rctrl);
 397
 398         if (ndev->features & NETIF_F_IP_CSUM)
 399                 tctrl |= TCTRL_INIT_CSUM;
 400
 401         if (priv->prio_sched_en)
 402                 tctrl |= TCTRL_TXSCHED_PRIO;
 403         else {
 404                 tctrl |= TCTRL_TXSCHED_WRRS;
 405                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 406                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 407         }
 408
 409         gfar_write(&regs->tctrl, tctrl);
 410
 411         /* Set the extraction length and index */
 412         attrs = ATTRELI_EL(priv->rx_stash_size) |
 413                 ATTRELI_EI(priv->rx_stash_index);
 414
 415         gfar_write(&regs->attreli, attrs);
 416
 417         /* Start with defaults, and add stashing or locking
 418          * depending on the approprate variables
 419          */
 420         attrs = ATTR_INIT_SETTINGS;
 421
 422         if (priv->bd_stash_en)
 423                 attrs |= ATTR_BDSTASH;
 424
 425         if (priv->rx_stash_size != 0)
 426                 attrs |= ATTR_BUFSTASH;
 427
 428         gfar_write(&regs->attr, attrs);
 429
 430         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 431         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 432         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 433 }
 434
 435 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 436 {
 437         struct gfar_private *priv = netdev_priv(dev);
 438         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 439         unsigned long tx_packets = 0, tx_bytes = 0;
 440         int i;
 441
 442         for (i = 0; i < priv->num_rx_queues; i++) {
 443                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 444                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 445                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 446         }
 447
 448         dev->stats.rx_packets = rx_packets;
 449         dev->stats.rx_bytes   = rx_bytes;
 450         dev->stats.rx_dropped = rx_dropped;
 451
 452         for (i = 0; i < priv->num_tx_queues; i++) {
 453                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 454                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 455         }
 456
 457         dev->stats.tx_bytes   = tx_bytes;
 458         dev->stats.tx_packets = tx_packets;
 459
 460         return &dev->stats;
 461 }
 462
 463 static const struct net_device_ops gfar_netdev_ops = {
 464         .ndo_open = gfar_enet_open,
 465         .ndo_start_xmit = gfar_start_xmit,
 466         .ndo_stop = gfar_close,
 467         .ndo_change_mtu = gfar_change_mtu,
 468         .ndo_set_features = gfar_set_features,
 469         .ndo_set_rx_mode = gfar_set_multi,
 470         .ndo_tx_timeout = gfar_timeout,
 471         .ndo_do_ioctl = gfar_ioctl,
 472         .ndo_get_stats = gfar_get_stats,
 473         .ndo_set_mac_address = eth_mac_addr,
 474         .ndo_validate_addr = eth_validate_addr,
 475 #ifdef CONFIG_NET_POLL_CONTROLLER
 476         .ndo_poll_controller = gfar_netpoll,
 477 #endif
 478 };
 479
 480 void lock_rx_qs(struct gfar_private *priv)
 481 {
 482         int i;
 483
 484         for (i = 0; i < priv->num_rx_queues; i++)
 485                 spin_lock(&priv->rx_queue[i]->rxlock);
 486 }
 487
 488 void lock_tx_qs(struct gfar_private *priv)
 489 {
 490         int i;
 491
 492         for (i = 0; i < priv->num_tx_queues; i++)
 493                 spin_lock(&priv->tx_queue[i]->txlock);
 494 }
 495
 496 void unlock_rx_qs(struct gfar_private *priv)
 497 {
 498         int i;
 499
 500         for (i = 0; i < priv->num_rx_queues; i++)
 501                 spin_unlock(&priv->rx_queue[i]->rxlock);
 502 }
 503
 504 void unlock_tx_qs(struct gfar_private *priv)
 505 {
 506         int i;
 507
 508         for (i = 0; i < priv->num_tx_queues; i++)
 509                 spin_unlock(&priv->tx_queue[i]->txlock);
 510 }
 511
 512 static void free_tx_pointers(struct gfar_private *priv)
 513 {
 514         int i;
 515
 516         for (i = 0; i < priv->num_tx_queues; i++)
 517                 kfree(priv->tx_queue[i]);
 518 }
 519
 520 static void free_rx_pointers(struct gfar_private *priv)
 521 {
 522         int i;
 523
 524         for (i = 0; i < priv->num_rx_queues; i++)
 525                 kfree(priv->rx_queue[i]);
 526 }
 527
 528 static void unmap_group_regs(struct gfar_private *priv)
 529 {
 530         int i;
 531
 532         for (i = 0; i < MAXGROUPS; i++)
 533                 if (priv->gfargrp[i].regs)
 534                         iounmap(priv->gfargrp[i].regs);
 535 }
 536
 537 static void free_gfar_dev(struct gfar_private *priv)
 538 {
 539         int i, j;
 540
 541         for (i = 0; i < priv->num_grps; i++)
 542                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 543                         kfree(priv->gfargrp[i].irqinfo[j]);
 544                         priv->gfargrp[i].irqinfo[j] = NULL;
 545                 }
 546
 547         free_netdev(priv->ndev);
 548 }
 549
 550 static void disable_napi(struct gfar_private *priv)
 551 {
 552         int i;
 553
 554         for (i = 0; i < priv->num_grps; i++)
 555                 napi_disable(&priv->gfargrp[i].napi);
 556 }
 557
 558 static void enable_napi(struct gfar_private *priv)
 559 {
 560         int i;
 561
 562         for (i = 0; i < priv->num_grps; i++)
 563                 napi_enable(&priv->gfargrp[i].napi);
 564 }
 565
 566 static int gfar_parse_group(struct device_node *np,
 567                             struct gfar_private *priv, const char *model)
 568 {
 569         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 570         u32 *queue_mask;
 571         int i;
 572
 573         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 574                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 575                                           GFP_KERNEL);
 576                 if (!grp->irqinfo[i])
 577                         return -ENOMEM;
 578         }
 579
 580         grp->regs = of_iomap(np, 0);
 581         if (!grp->regs)
 582                 return -ENOMEM;
 583
 584         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 585
 586         /* If we aren't the FEC we have multiple interrupts */
 587         if (model && strcasecmp(model, "FEC")) {
 588                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 589                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 590                 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
 591                     gfar_irq(grp, RX)->irq == NO_IRQ ||
 592                     gfar_irq(grp, ER)->irq == NO_IRQ)
 593                         return -EINVAL;
 594         }
 595
 596         grp->priv = priv;
 597         spin_lock_init(&grp->grplock);
 598         if (priv->mode == MQ_MG_MODE) {
 599                 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
 600                 grp->rx_bit_map = queue_mask ?
 601                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 602                 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
 603                 grp->tx_bit_map = queue_mask ?
 604                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 605         } else {
 606                 grp->rx_bit_map = 0xFF;
 607                 grp->tx_bit_map = 0xFF;
 608         }
 609         priv->num_grps++;
 610
 611         return 0;
 612 }
 613
 614 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 615 {
 616         const char *model;
 617         const char *ctype;
 618         const void *mac_addr;
 619         int err = 0, i;
 620         struct net_device *dev = NULL;
 621         struct gfar_private *priv = NULL;
 622         struct device_node *np = ofdev->dev.of_node;
 623         struct device_node *child = NULL;
 624         const u32 *stash;
 625         const u32 *stash_len;
 626         const u32 *stash_idx;
 627         unsigned int num_tx_qs, num_rx_qs;
 628         u32 *tx_queues, *rx_queues;
 629
 630         if (!np || !of_device_is_available(np))
 631                 return -ENODEV;
 632
 633         /* parse the num of tx and rx queues */
 634         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 635         num_tx_qs = tx_queues ? *tx_queues : 1;
 636
 637         if (num_tx_qs > MAX_TX_QS) {
 638                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 639                        num_tx_qs, MAX_TX_QS);
 640                 pr_err("Cannot do alloc_etherdev, aborting\n");
 641                 return -EINVAL;
 642         }
 643
 644         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 645         num_rx_qs = rx_queues ? *rx_queues : 1;
 646
 647         if (num_rx_qs > MAX_RX_QS) {
 648                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 649                        num_rx_qs, MAX_RX_QS);
 650                 pr_err("Cannot do alloc_etherdev, aborting\n");
 651                 return -EINVAL;
 652         }
 653
 654         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 655         dev = *pdev;
 656         if (NULL == dev)
 657                 return -ENOMEM;
 658
 659         priv = netdev_priv(dev);
 660         priv->ndev = dev;
 661
 662         priv->num_tx_queues = num_tx_qs;
 663         netif_set_real_num_rx_queues(dev, num_rx_qs);
 664         priv->num_rx_queues = num_rx_qs;
 665         priv->num_grps = 0x0;
 666
 667         /* Init Rx queue filer rule set linked list */
 668         INIT_LIST_HEAD(&priv->rx_list.list);
 669         priv->rx_list.count = 0;
 670         mutex_init(&priv->rx_queue_access);
 671
 672         model = of_get_property(np, "model", NULL);
 673
 674         for (i = 0; i < MAXGROUPS; i++)
 675                 priv->gfargrp[i].regs = NULL;
 676
 677         /* Parse and initialize group specific information */
 678         if (of_device_is_compatible(np, "fsl,etsec2")) {
 679                 priv->mode = MQ_MG_MODE;
 680                 for_each_child_of_node(np, child) {
 681                         err = gfar_parse_group(child, priv, model);
 682                         if (err)
 683                                 goto err_grp_init;
 684                 }
 685         } else {
 686                 priv->mode = SQ_SG_MODE;
 687                 err = gfar_parse_group(np, priv, model);
 688                 if (err)
 689                         goto err_grp_init;
 690         }
 691
 692         for (i = 0; i < priv->num_tx_queues; i++)
 693                 priv->tx_queue[i] = NULL;
 694         for (i = 0; i < priv->num_rx_queues; i++)
 695                 priv->rx_queue[i] = NULL;
 696
 697         for (i = 0; i < priv->num_tx_queues; i++) {
 698                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 699                                             GFP_KERNEL);
 700                 if (!priv->tx_queue[i]) {
 701                         err = -ENOMEM;
 702                         goto tx_alloc_failed;
 703                 }
 704                 priv->tx_queue[i]->tx_skbuff = NULL;
 705                 priv->tx_queue[i]->qindex = i;
 706                 priv->tx_queue[i]->dev = dev;
 707                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 708         }
 709
 710         for (i = 0; i < priv->num_rx_queues; i++) {
 711                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 712                                             GFP_KERNEL);
 713                 if (!priv->rx_queue[i]) {
 714                         err = -ENOMEM;
 715                         goto rx_alloc_failed;
 716                 }
 717                 priv->rx_queue[i]->rx_skbuff = NULL;
 718                 priv->rx_queue[i]->qindex = i;
 719                 priv->rx_queue[i]->dev = dev;
 720                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 721         }
 722
 723
 724         stash = of_get_property(np, "bd-stash", NULL);
 725
 726         if (stash) {
 727                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 728                 priv->bd_stash_en = 1;
 729         }
 730
 731         stash_len = of_get_property(np, "rx-stash-len", NULL);
 732
 733         if (stash_len)
 734                 priv->rx_stash_size = *stash_len;
 735
 736         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 737
 738         if (stash_idx)
 739                 priv->rx_stash_index = *stash_idx;
 740
 741         if (stash_len || stash_idx)
 742                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 743
 744         mac_addr = of_get_mac_address(np);
 745
 746         if (mac_addr)
 747                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 748
 749         if (model && !strcasecmp(model, "TSEC"))
 750                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 751                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 752                                      FSL_GIANFAR_DEV_HAS_RMON |
 753                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 754
 755         if (model && !strcasecmp(model, "eTSEC"))
 756                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 757                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 758                                      FSL_GIANFAR_DEV_HAS_RMON |
 759                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 760                                      FSL_GIANFAR_DEV_HAS_PADDING |
 761                                      FSL_GIANFAR_DEV_HAS_CSUM |
 762                                      FSL_GIANFAR_DEV_HAS_VLAN |
 763                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 764                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 765                                      FSL_GIANFAR_DEV_HAS_TIMER;
 766
 767         ctype = of_get_property(np, "phy-connection-type", NULL);
 768
 769         /* We only care about rgmii-id.  The rest are autodetected */
 770         if (ctype && !strcmp(ctype, "rgmii-id"))
 771                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 772         else
 773                 priv->interface = PHY_INTERFACE_MODE_MII;
 774
 775         if (of_get_property(np, "fsl,magic-packet", NULL))
 776                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 777
 778         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 779
 780         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 781         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 782
 783         return 0;
 784
 785 rx_alloc_failed:
 786         free_rx_pointers(priv);
 787 tx_alloc_failed:
 788         free_tx_pointers(priv);
 789 err_grp_init:
 790         unmap_group_regs(priv);
 791         free_gfar_dev(priv);
 792         return err;
 793 }
 794
 795 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 796                                struct ifreq *ifr, int cmd)
 797 {
 798         struct hwtstamp_config config;
 799         struct gfar_private *priv = netdev_priv(netdev);
 800
 801         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 802                 return -EFAULT;
 803
 804         /* reserved for future extensions */
 805         if (config.flags)
 806                 return -EINVAL;
 807
 808         switch (config.tx_type) {
 809         case HWTSTAMP_TX_OFF:
 810                 priv->hwts_tx_en = 0;
 811                 break;
 812         case HWTSTAMP_TX_ON:
 813                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 814                         return -ERANGE;
 815                 priv->hwts_tx_en = 1;
 816                 break;
 817         default:
 818                 return -ERANGE;
 819         }
 820
 821         switch (config.rx_filter) {
 822         case HWTSTAMP_FILTER_NONE:
 823                 if (priv->hwts_rx_en) {
 824                         stop_gfar(netdev);
 825                         priv->hwts_rx_en = 0;
 826                         startup_gfar(netdev);
 827                 }
 828                 break;
 829         default:
 830                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 831                         return -ERANGE;
 832                 if (!priv->hwts_rx_en) {
 833                         stop_gfar(netdev);
 834                         priv->hwts_rx_en = 1;
 835                         startup_gfar(netdev);
 836                 }
 837                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 838                 break;
 839         }
 840
 841         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 842                 -EFAULT : 0;
 843 }
 844
 845 /* Ioctl MII Interface */
 846 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 847 {
 848         struct gfar_private *priv = netdev_priv(dev);
 849
 850         if (!netif_running(dev))
 851                 return -EINVAL;
 852
 853         if (cmd == SIOCSHWTSTAMP)
 854                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 855
 856         if (!priv->phydev)
 857                 return -ENODEV;
 858
 859         return phy_mii_ioctl(priv->phydev, rq, cmd);
 860 }
 861
 862 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 863 {
 864         unsigned int new_bit_map = 0x0;
 865         int mask = 0x1 << (max_qs - 1), i;
 866
 867         for (i = 0; i < max_qs; i++) {
 868                 if (bit_map & mask)
 869                         new_bit_map = new_bit_map + (1 << i);
 870                 mask = mask >> 0x1;
 871         }
 872         return new_bit_map;
 873 }
 874
 875 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 876                                    u32 class)
 877 {
 878         u32 rqfpr = FPR_FILER_MASK;
 879         u32 rqfcr = 0x0;
 880
 881         rqfar--;
 882         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 883         priv->ftp_rqfpr[rqfar] = rqfpr;
 884         priv->ftp_rqfcr[rqfar] = rqfcr;
 885         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 886
 887         rqfar--;
 888         rqfcr = RQFCR_CMP_NOMATCH;
 889         priv->ftp_rqfpr[rqfar] = rqfpr;
 890         priv->ftp_rqfcr[rqfar] = rqfcr;
 891         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 892
 893         rqfar--;
 894         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 895         rqfpr = class;
 896         priv->ftp_rqfcr[rqfar] = rqfcr;
 897         priv->ftp_rqfpr[rqfar] = rqfpr;
 898         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 899
 900         rqfar--;
 901         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 902         rqfpr = class;
 903         priv->ftp_rqfcr[rqfar] = rqfcr;
 904         priv->ftp_rqfpr[rqfar] = rqfpr;
 905         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 906
 907         return rqfar;
 908 }
 909
 910 static void gfar_init_filer_table(struct gfar_private *priv)
 911 {
 912         int i = 0x0;
 913         u32 rqfar = MAX_FILER_IDX;
 914         u32 rqfcr = 0x0;
 915         u32 rqfpr = FPR_FILER_MASK;
 916
 917         /* Default rule */
 918         rqfcr = RQFCR_CMP_MATCH;
 919         priv->ftp_rqfcr[rqfar] = rqfcr;
 920         priv->ftp_rqfpr[rqfar] = rqfpr;
 921         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 922
 923         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 924         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 925         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 926         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 927         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 928         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 929
 930         /* cur_filer_idx indicated the first non-masked rule */
 931         priv->cur_filer_idx = rqfar;
 932
 933         /* Rest are masked rules */
 934         rqfcr = RQFCR_CMP_NOMATCH;
 935         for (i = 0; i < rqfar; i++) {
 936                 priv->ftp_rqfcr[i] = rqfcr;
 937                 priv->ftp_rqfpr[i] = rqfpr;
 938                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 939         }
 940 }
 941
 942 static void gfar_detect_errata(struct gfar_private *priv)
 943 {
 944         struct device *dev = &priv->ofdev->dev;
 945         unsigned int pvr = mfspr(SPRN_PVR);
 946         unsigned int svr = mfspr(SPRN_SVR);
 947         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 948         unsigned int rev = svr & 0xffff;
 949
 950         /* no plans to fix */
 951         priv->errata |= GFAR_ERRATA_A002;
 952
 953         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 954         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 955             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 956                 priv->errata |= GFAR_ERRATA_74;
 957
 958         /* MPC8313 and MPC837x all rev */
 959         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 960             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 961                 priv->errata |= GFAR_ERRATA_76;
 962
 963         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
 964         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
 965             (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
 966                 priv->errata |= GFAR_ERRATA_12;
 967
 968         if (priv->errata)
 969                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 970                          priv->errata);
 971 }
 972
 973 /* Set up the ethernet device structure, private data,
 974  * and anything else we need before we start
 975  */
 976 static int gfar_probe(struct platform_device *ofdev)
 977 {
 978         u32 tempval;
 979         struct net_device *dev = NULL;
 980         struct gfar_private *priv = NULL;
 981         struct gfar __iomem *regs = NULL;
 982         int err = 0, i, grp_idx = 0;
 983         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 984         u32 isrg = 0;
 985         u32 __iomem *baddr;
 986
 987         err = gfar_of_init(ofdev, &dev);
 988
 989         if (err)
 990                 return err;
 991
 992         priv = netdev_priv(dev);
 993         priv->ndev = dev;
 994         priv->ofdev = ofdev;
 995         priv->dev = &ofdev->dev;
 996         SET_NETDEV_DEV(dev, &ofdev->dev);
 997
 998         spin_lock_init(&priv->bflock);
 999         INIT_WORK(&priv->reset_task, gfar_reset_task);
1000
1001         platform_set_drvdata(ofdev, priv);
1002         regs = priv->gfargrp[0].regs;
1003
1004         gfar_detect_errata(priv);
1005
1006         /* Stop the DMA engine now, in case it was running before
1007          * (The firmware could have used it, and left it running).
1008          */
1009         gfar_halt(dev);
1010
1011         /* Reset MAC layer */
1012         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1013
1014         /* We need to delay at least 3 TX clocks */
1015         udelay(2);
1016
1017         tempval = 0;
1018         if (!priv->pause_aneg_en && priv->tx_pause_en)
1019                 tempval |= MACCFG1_TX_FLOW;
1020         if (!priv->pause_aneg_en && priv->rx_pause_en)
1021                 tempval |= MACCFG1_RX_FLOW;
1022         /* the soft reset bit is not self-resetting, so we need to
1023          * clear it before resuming normal operation
1024          */
1025         gfar_write(&regs->maccfg1, tempval);
1026
1027         /* Initialize MACCFG2. */
1028         tempval = MACCFG2_INIT_SETTINGS;
1029         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1030                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1031         gfar_write(&regs->maccfg2, tempval);
1032
1033         /* Initialize ECNTRL */
1034         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1035
1036         /* Set the dev->base_addr to the gfar reg region */
1037         dev->base_addr = (unsigned long) regs;
1038
1039         /* Fill in the dev structure */
1040         dev->watchdog_timeo = TX_TIMEOUT;
1041         dev->mtu = 1500;
1042         dev->netdev_ops = &gfar_netdev_ops;
1043         dev->ethtool_ops = &gfar_ethtool_ops;
1044
1045         /* Register for napi ...We are registering NAPI for each grp */
1046         if (priv->mode == SQ_SG_MODE)
1047                 netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq,
1048                                GFAR_DEV_WEIGHT);
1049         else
1050                 for (i = 0; i < priv->num_grps; i++)
1051                         netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1052                                        GFAR_DEV_WEIGHT);
1053
1054         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1055                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1056                                    NETIF_F_RXCSUM;
1057                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1058                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1059         }
1060
1061         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1062                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1063                                     NETIF_F_HW_VLAN_CTAG_RX;
1064                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1065         }
1066
1067         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1068                 priv->extended_hash = 1;
1069                 priv->hash_width = 9;
1070
1071                 priv->hash_regs[0] = &regs->igaddr0;
1072                 priv->hash_regs[1] = &regs->igaddr1;
1073                 priv->hash_regs[2] = &regs->igaddr2;
1074                 priv->hash_regs[3] = &regs->igaddr3;
1075                 priv->hash_regs[4] = &regs->igaddr4;
1076                 priv->hash_regs[5] = &regs->igaddr5;
1077                 priv->hash_regs[6] = &regs->igaddr6;
1078                 priv->hash_regs[7] = &regs->igaddr7;
1079                 priv->hash_regs[8] = &regs->gaddr0;
1080                 priv->hash_regs[9] = &regs->gaddr1;
1081                 priv->hash_regs[10] = &regs->gaddr2;
1082                 priv->hash_regs[11] = &regs->gaddr3;
1083                 priv->hash_regs[12] = &regs->gaddr4;
1084                 priv->hash_regs[13] = &regs->gaddr5;
1085                 priv->hash_regs[14] = &regs->gaddr6;
1086                 priv->hash_regs[15] = &regs->gaddr7;
1087
1088         } else {
1089                 priv->extended_hash = 0;
1090                 priv->hash_width = 8;
1091
1092                 priv->hash_regs[0] = &regs->gaddr0;
1093                 priv->hash_regs[1] = &regs->gaddr1;
1094                 priv->hash_regs[2] = &regs->gaddr2;
1095                 priv->hash_regs[3] = &regs->gaddr3;
1096                 priv->hash_regs[4] = &regs->gaddr4;
1097                 priv->hash_regs[5] = &regs->gaddr5;
1098                 priv->hash_regs[6] = &regs->gaddr6;
1099                 priv->hash_regs[7] = &regs->gaddr7;
1100         }
1101
1102         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1103                 priv->padding = DEFAULT_PADDING;
1104         else
1105                 priv->padding = 0;
1106
1107         if (dev->features & NETIF_F_IP_CSUM ||
1108             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1109                 dev->needed_headroom = GMAC_FCB_LEN;
1110
1111         /* Program the isrg regs only if number of grps > 1 */
1112         if (priv->num_grps > 1) {
1113                 baddr = &regs->isrg0;
1114                 for (i = 0; i < priv->num_grps; i++) {
1115                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1116                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1117                         gfar_write(baddr, isrg);
1118                         baddr++;
1119                         isrg = 0x0;
1120                 }
1121         }
1122
1123         /* Need to reverse the bit maps as  bit_map's MSB is q0
1124          * but, for_each_set_bit parses from right to left, which
1125          * basically reverses the queue numbers
1126          */
1127         for (i = 0; i< priv->num_grps; i++) {
1128                 priv->gfargrp[i].tx_bit_map =
1129                         reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1130                 priv->gfargrp[i].rx_bit_map =
1131                         reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1132         }
1133
1134         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1135          * also assign queues to groups
1136          */
1137         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1138                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1139
1140                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1141                                  priv->num_rx_queues) {
1142                         priv->gfargrp[grp_idx].num_rx_queues++;
1143                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1144                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1145                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1146                 }
1147                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1148
1149                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1150                                  priv->num_tx_queues) {
1151                         priv->gfargrp[grp_idx].num_tx_queues++;
1152                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1153                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1154                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1155                 }
1156                 priv->gfargrp[grp_idx].rstat = rstat;
1157                 priv->gfargrp[grp_idx].tstat = tstat;
1158                 rstat = tstat =0;
1159         }
1160
1161         gfar_write(&regs->rqueue, rqueue);
1162         gfar_write(&regs->tqueue, tqueue);
1163
1164         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1165
1166         /* Initializing some of the rx/tx queue level parameters */
1167         for (i = 0; i < priv->num_tx_queues; i++) {
1168                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1169                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1170                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1171                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1172         }
1173
1174         for (i = 0; i < priv->num_rx_queues; i++) {
1175                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1176                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1177                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1178         }
1179
1180         /* always enable rx filer */
1181         priv->rx_filer_enable = 1;
1182         /* Enable most messages by default */
1183         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1184         /* use pritority h/w tx queue scheduling for single queue devices */
1185         if (priv->num_tx_queues == 1)
1186                 priv->prio_sched_en = 1;
1187
1188         /* Carrier starts down, phylib will bring it up */
1189         netif_carrier_off(dev);
1190
1191         err = register_netdev(dev);
1192
1193         if (err) {
1194                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1195                 goto register_fail;
1196         }
1197
1198         device_init_wakeup(&dev->dev,
1199                            priv->device_flags &
1200                            FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1201
1202         /* fill out IRQ number and name fields */
1203         for (i = 0; i < priv->num_grps; i++) {
1204                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1205                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1206                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1207                                 dev->name, "_g", '0' + i, "_tx");
1208                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1209                                 dev->name, "_g", '0' + i, "_rx");
1210                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1211                                 dev->name, "_g", '0' + i, "_er");
1212                 } else
1213                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1214         }
1215
1216         /* Initialize the filer table */
1217         gfar_init_filer_table(priv);
1218
1219         /* Create all the sysfs files */
1220         gfar_init_sysfs(dev);
1221
1222         /* Print out the device info */
1223         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1224
1225         /* Even more device info helps when determining which kernel
1226          * provided which set of benchmarks.
1227          */
1228         netdev_info(dev, "Running with NAPI enabled\n");
1229         for (i = 0; i < priv->num_rx_queues; i++)
1230                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1231                             i, priv->rx_queue[i]->rx_ring_size);
1232         for (i = 0; i < priv->num_tx_queues; i++)
1233                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1234                             i, priv->tx_queue[i]->tx_ring_size);
1235
1236         return 0;
1237
1238 register_fail:
1239         unmap_group_regs(priv);
1240         free_tx_pointers(priv);
1241         free_rx_pointers(priv);
1242         if (priv->phy_node)
1243                 of_node_put(priv->phy_node);
1244         if (priv->tbi_node)
1245                 of_node_put(priv->tbi_node);
1246         free_gfar_dev(priv);
1247         return err;
1248 }
1249
1250 static int gfar_remove(struct platform_device *ofdev)
1251 {
1252         struct gfar_private *priv = platform_get_drvdata(ofdev);
1253
1254         if (priv->phy_node)
1255                 of_node_put(priv->phy_node);
1256         if (priv->tbi_node)
1257                 of_node_put(priv->tbi_node);
1258
1259         unregister_netdev(priv->ndev);
1260         unmap_group_regs(priv);
1261         free_gfar_dev(priv);
1262
1263         return 0;
1264 }
1265
1266 #ifdef CONFIG_PM
1267
1268 static int gfar_suspend(struct device *dev)
1269 {
1270         struct gfar_private *priv = dev_get_drvdata(dev);
1271         struct net_device *ndev = priv->ndev;
1272         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1273         unsigned long flags;
1274         u32 tempval;
1275
1276         int magic_packet = priv->wol_en &&
1277                            (priv->device_flags &
1278                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1279
1280         netif_device_detach(ndev);
1281
1282         if (netif_running(ndev)) {
1283
1284                 local_irq_save(flags);
1285                 lock_tx_qs(priv);
1286                 lock_rx_qs(priv);
1287
1288                 gfar_halt_nodisable(ndev);
1289
1290                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1291                 tempval = gfar_read(&regs->maccfg1);
1292
1293                 tempval &= ~MACCFG1_TX_EN;
1294
1295                 if (!magic_packet)
1296                         tempval &= ~MACCFG1_RX_EN;
1297
1298                 gfar_write(&regs->maccfg1, tempval);
1299
1300                 unlock_rx_qs(priv);
1301                 unlock_tx_qs(priv);
1302                 local_irq_restore(flags);
1303
1304                 disable_napi(priv);
1305
1306                 if (magic_packet) {
1307                         /* Enable interrupt on Magic Packet */
1308                         gfar_write(&regs->imask, IMASK_MAG);
1309
1310                         /* Enable Magic Packet mode */
1311                         tempval = gfar_read(&regs->maccfg2);
1312                         tempval |= MACCFG2_MPEN;
1313                         gfar_write(&regs->maccfg2, tempval);
1314                 } else {
1315                         phy_stop(priv->phydev);
1316                 }
1317         }
1318
1319         return 0;
1320 }
1321
1322 static int gfar_resume(struct device *dev)
1323 {
1324         struct gfar_private *priv = dev_get_drvdata(dev);
1325         struct net_device *ndev = priv->ndev;
1326         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1327         unsigned long flags;
1328         u32 tempval;
1329         int magic_packet = priv->wol_en &&
1330                            (priv->device_flags &
1331                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1332
1333         if (!netif_running(ndev)) {
1334                 netif_device_attach(ndev);
1335                 return 0;
1336         }
1337
1338         if (!magic_packet && priv->phydev)
1339                 phy_start(priv->phydev);
1340
1341         /* Disable Magic Packet mode, in case something
1342          * else woke us up.
1343          */
1344         local_irq_save(flags);
1345         lock_tx_qs(priv);
1346         lock_rx_qs(priv);
1347
1348         tempval = gfar_read(&regs->maccfg2);
1349         tempval &= ~MACCFG2_MPEN;
1350         gfar_write(&regs->maccfg2, tempval);
1351
1352         gfar_start(ndev);
1353
1354         unlock_rx_qs(priv);
1355         unlock_tx_qs(priv);
1356         local_irq_restore(flags);
1357
1358         netif_device_attach(ndev);
1359
1360         enable_napi(priv);
1361
1362         return 0;
1363 }
1364
1365 static int gfar_restore(struct device *dev)
1366 {
1367         struct gfar_private *priv = dev_get_drvdata(dev);
1368         struct net_device *ndev = priv->ndev;
1369
1370         if (!netif_running(ndev)) {
1371                 netif_device_attach(ndev);
1372
1373                 return 0;
1374         }
1375
1376         if (gfar_init_bds(ndev)) {
1377                 free_skb_resources(priv);
1378                 return -ENOMEM;
1379         }
1380
1381         init_registers(ndev);
1382         gfar_set_mac_address(ndev);
1383         gfar_init_mac(ndev);
1384         gfar_start(ndev);
1385
1386         priv->oldlink = 0;
1387         priv->oldspeed = 0;
1388         priv->oldduplex = -1;
1389
1390         if (priv->phydev)
1391                 phy_start(priv->phydev);
1392
1393         netif_device_attach(ndev);
1394         enable_napi(priv);
1395
1396         return 0;
1397 }
1398
1399 static struct dev_pm_ops gfar_pm_ops = {
1400         .suspend = gfar_suspend,
1401         .resume = gfar_resume,
1402         .freeze = gfar_suspend,
1403         .thaw = gfar_resume,
1404         .restore = gfar_restore,
1405 };
1406
1407 #define GFAR_PM_OPS (&gfar_pm_ops)
1408
1409 #else
1410
1411 #define GFAR_PM_OPS NULL
1412
1413 #endif
1414
1415 /* Reads the controller's registers to determine what interface
1416  * connects it to the PHY.
1417  */
1418 static phy_interface_t gfar_get_interface(struct net_device *dev)
1419 {
1420         struct gfar_private *priv = netdev_priv(dev);
1421         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1422         u32 ecntrl;
1423
1424         ecntrl = gfar_read(&regs->ecntrl);
1425
1426         if (ecntrl & ECNTRL_SGMII_MODE)
1427                 return PHY_INTERFACE_MODE_SGMII;
1428
1429         if (ecntrl & ECNTRL_TBI_MODE) {
1430                 if (ecntrl & ECNTRL_REDUCED_MODE)
1431                         return PHY_INTERFACE_MODE_RTBI;
1432                 else
1433                         return PHY_INTERFACE_MODE_TBI;
1434         }
1435
1436         if (ecntrl & ECNTRL_REDUCED_MODE) {
1437                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1438                         return PHY_INTERFACE_MODE_RMII;
1439                 }
1440                 else {
1441                         phy_interface_t interface = priv->interface;
1442
1443                         /* This isn't autodetected right now, so it must
1444                          * be set by the device tree or platform code.
1445                          */
1446                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1447                                 return PHY_INTERFACE_MODE_RGMII_ID;
1448
1449                         return PHY_INTERFACE_MODE_RGMII;
1450                 }
1451         }
1452
1453         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1454                 return PHY_INTERFACE_MODE_GMII;
1455
1456         return PHY_INTERFACE_MODE_MII;
1457 }
1458
1459
1460 /* Initializes driver's PHY state, and attaches to the PHY.
1461  * Returns 0 on success.
1462  */
1463 static int init_phy(struct net_device *dev)
1464 {
1465         struct gfar_private *priv = netdev_priv(dev);
1466         uint gigabit_support =
1467                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1468                 GFAR_SUPPORTED_GBIT : 0;
1469         phy_interface_t interface;
1470
1471         priv->oldlink = 0;
1472         priv->oldspeed = 0;
1473         priv->oldduplex = -1;
1474
1475         interface = gfar_get_interface(dev);
1476
1477         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1478                                       interface);
1479         if (!priv->phydev)
1480                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1481                                                          interface);
1482         if (!priv->phydev) {
1483                 dev_err(&dev->dev, "could not attach to PHY\n");
1484                 return -ENODEV;
1485         }
1486
1487         if (interface == PHY_INTERFACE_MODE_SGMII)
1488                 gfar_configure_serdes(dev);
1489
1490         /* Remove any features not supported by the controller */
1491         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1492         priv->phydev->advertising = priv->phydev->supported;
1493
1494         return 0;
1495 }
1496
1497 /* Initialize TBI PHY interface for communicating with the
1498  * SERDES lynx PHY on the chip.  We communicate with this PHY
1499  * through the MDIO bus on each controller, treating it as a
1500  * "normal" PHY at the address found in the TBIPA register.  We assume
1501  * that the TBIPA register is valid.  Either the MDIO bus code will set
1502  * it to a value that doesn't conflict with other PHYs on the bus, or the
1503  * value doesn't matter, as there are no other PHYs on the bus.
1504  */
1505 static void gfar_configure_serdes(struct net_device *dev)
1506 {
1507         struct gfar_private *priv = netdev_priv(dev);
1508         struct phy_device *tbiphy;
1509
1510         if (!priv->tbi_node) {
1511                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1512                                     "device tree specify a tbi-handle\n");
1513                 return;
1514         }
1515
1516         tbiphy = of_phy_find_device(priv->tbi_node);
1517         if (!tbiphy) {
1518                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1519                 return;
1520         }
1521
1522         /* If the link is already up, we must already be ok, and don't need to
1523          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1524          * everything for us?  Resetting it takes the link down and requires
1525          * several seconds for it to come back.
1526          */
1527         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1528                 return;
1529
1530         /* Single clk mode, mii mode off(for serdes communication) */
1531         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1532
1533         phy_write(tbiphy, MII_ADVERTISE,
1534                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1535                   ADVERTISE_1000XPSE_ASYM);
1536
1537         phy_write(tbiphy, MII_BMCR,
1538                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1539                   BMCR_SPEED1000);
1540 }
1541
1542 static void init_registers(struct net_device *dev)
1543 {
1544         struct gfar_private *priv = netdev_priv(dev);
1545         struct gfar __iomem *regs = NULL;
1546         int i;
1547
1548         for (i = 0; i < priv->num_grps; i++) {
1549                 regs = priv->gfargrp[i].regs;
1550                 /* Clear IEVENT */
1551                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1552
1553                 /* Initialize IMASK */
1554                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1555         }
1556
1557         regs = priv->gfargrp[0].regs;
1558         /* Init hash registers to zero */
1559         gfar_write(&regs->igaddr0, 0);
1560         gfar_write(&regs->igaddr1, 0);
1561         gfar_write(&regs->igaddr2, 0);
1562         gfar_write(&regs->igaddr3, 0);
1563         gfar_write(&regs->igaddr4, 0);
1564         gfar_write(&regs->igaddr5, 0);
1565         gfar_write(&regs->igaddr6, 0);
1566         gfar_write(&regs->igaddr7, 0);
1567
1568         gfar_write(&regs->gaddr0, 0);
1569         gfar_write(&regs->gaddr1, 0);
1570         gfar_write(&regs->gaddr2, 0);
1571         gfar_write(&regs->gaddr3, 0);
1572         gfar_write(&regs->gaddr4, 0);
1573         gfar_write(&regs->gaddr5, 0);
1574         gfar_write(&regs->gaddr6, 0);
1575         gfar_write(&regs->gaddr7, 0);
1576
1577         /* Zero out the rmon mib registers if it has them */
1578         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1579                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1580
1581                 /* Mask off the CAM interrupts */
1582                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1583                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1584         }
1585
1586         /* Initialize the max receive buffer length */
1587         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1588
1589         /* Initialize the Minimum Frame Length Register */
1590         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1591 }
1592
1593 static int __gfar_is_rx_idle(struct gfar_private *priv)
1594 {
1595         u32 res;
1596
1597         /* Normaly TSEC should not hang on GRS commands, so we should
1598          * actually wait for IEVENT_GRSC flag.
1599          */
1600         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1601                 return 0;
1602
1603         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1604          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1605          * and the Rx can be safely reset.
1606          */
1607         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1608         res &= 0x7f807f80;
1609         if ((res & 0xffff) == (res >> 16))
1610                 return 1;
1611
1612         return 0;
1613 }
1614
1615 /* Halt the receive and transmit queues */
1616 static void gfar_halt_nodisable(struct net_device *dev)
1617 {
1618         struct gfar_private *priv = netdev_priv(dev);
1619         struct gfar __iomem *regs = NULL;
1620         u32 tempval;
1621         int i;
1622
1623         for (i = 0; i < priv->num_grps; i++) {
1624                 regs = priv->gfargrp[i].regs;
1625                 /* Mask all interrupts */
1626                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1627
1628                 /* Clear all interrupts */
1629                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1630         }
1631
1632         regs = priv->gfargrp[0].regs;
1633         /* Stop the DMA, and wait for it to stop */
1634         tempval = gfar_read(&regs->dmactrl);
1635         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1636             (DMACTRL_GRS | DMACTRL_GTS)) {
1637                 int ret;
1638
1639                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1640                 gfar_write(&regs->dmactrl, tempval);
1641
1642                 do {
1643                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1644                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1645                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1646                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1647                                 ret = __gfar_is_rx_idle(priv);
1648                 } while (!ret);
1649         }
1650 }
1651
1652 /* Halt the receive and transmit queues */
1653 void gfar_halt(struct net_device *dev)
1654 {
1655         struct gfar_private *priv = netdev_priv(dev);
1656         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1657         u32 tempval;
1658
1659         gfar_halt_nodisable(dev);
1660
1661         /* Disable Rx and Tx */
1662         tempval = gfar_read(&regs->maccfg1);
1663         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1664         gfar_write(&regs->maccfg1, tempval);
1665 }
1666
1667 static void free_grp_irqs(struct gfar_priv_grp *grp)
1668 {
1669         free_irq(gfar_irq(grp, TX)->irq, grp);
1670         free_irq(gfar_irq(grp, RX)->irq, grp);
1671         free_irq(gfar_irq(grp, ER)->irq, grp);
1672 }
1673
1674 void stop_gfar(struct net_device *dev)
1675 {
1676         struct gfar_private *priv = netdev_priv(dev);
1677         unsigned long flags;
1678         int i;
1679
1680         phy_stop(priv->phydev);
1681
1682
1683         /* Lock it down */
1684         local_irq_save(flags);
1685         lock_tx_qs(priv);
1686         lock_rx_qs(priv);
1687
1688         gfar_halt(dev);
1689
1690         unlock_rx_qs(priv);
1691         unlock_tx_qs(priv);
1692         local_irq_restore(flags);
1693
1694         /* Free the IRQs */
1695         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1696                 for (i = 0; i < priv->num_grps; i++)
1697                         free_grp_irqs(&priv->gfargrp[i]);
1698         } else {
1699                 for (i = 0; i < priv->num_grps; i++)
1700                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1701                                  &priv->gfargrp[i]);
1702         }
1703
1704         free_skb_resources(priv);
1705 }
1706
1707 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1708 {
1709         struct txbd8 *txbdp;
1710         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1711         int i, j;
1712
1713         txbdp = tx_queue->tx_bd_base;
1714
1715         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1716                 if (!tx_queue->tx_skbuff[i])
1717                         continue;
1718
1719                 dma_unmap_single(priv->dev, txbdp->bufPtr,
1720                                  txbdp->length, DMA_TO_DEVICE);
1721                 txbdp->lstatus = 0;
1722                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1723                      j++) {
1724                         txbdp++;
1725                         dma_unmap_page(priv->dev, txbdp->bufPtr,
1726                                        txbdp->length, DMA_TO_DEVICE);
1727                 }
1728                 txbdp++;
1729                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1730                 tx_queue->tx_skbuff[i] = NULL;
1731         }
1732         kfree(tx_queue->tx_skbuff);
1733         tx_queue->tx_skbuff = NULL;
1734 }
1735
1736 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1737 {
1738         struct rxbd8 *rxbdp;
1739         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1740         int i;
1741
1742         rxbdp = rx_queue->rx_bd_base;
1743
1744         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1745                 if (rx_queue->rx_skbuff[i]) {
1746                         dma_unmap_single(priv->dev, rxbdp->bufPtr,
1747                                          priv->rx_buffer_size,
1748                                          DMA_FROM_DEVICE);
1749                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1750                         rx_queue->rx_skbuff[i] = NULL;
1751                 }
1752                 rxbdp->lstatus = 0;
1753                 rxbdp->bufPtr = 0;
1754                 rxbdp++;
1755         }
1756         kfree(rx_queue->rx_skbuff);
1757         rx_queue->rx_skbuff = NULL;
1758 }
1759
1760 /* If there are any tx skbs or rx skbs still around, free them.
1761  * Then free tx_skbuff and rx_skbuff
1762  */
1763 static void free_skb_resources(struct gfar_private *priv)
1764 {
1765         struct gfar_priv_tx_q *tx_queue = NULL;
1766         struct gfar_priv_rx_q *rx_queue = NULL;
1767         int i;
1768
1769         /* Go through all the buffer descriptors and free their data buffers */
1770         for (i = 0; i < priv->num_tx_queues; i++) {
1771                 struct netdev_queue *txq;
1772
1773                 tx_queue = priv->tx_queue[i];
1774                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1775                 if (tx_queue->tx_skbuff)
1776                         free_skb_tx_queue(tx_queue);
1777                 netdev_tx_reset_queue(txq);
1778         }
1779
1780         for (i = 0; i < priv->num_rx_queues; i++) {
1781                 rx_queue = priv->rx_queue[i];
1782                 if (rx_queue->rx_skbuff)
1783                         free_skb_rx_queue(rx_queue);
1784         }
1785
1786         dma_free_coherent(priv->dev,
1787                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1788                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1789                           priv->tx_queue[0]->tx_bd_base,
1790                           priv->tx_queue[0]->tx_bd_dma_base);
1791 }
1792
1793 void gfar_start(struct net_device *dev)
1794 {
1795         struct gfar_private *priv = netdev_priv(dev);
1796         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1797         u32 tempval;
1798         int i = 0;
1799
1800         /* Enable Rx and Tx in MACCFG1 */
1801         tempval = gfar_read(&regs->maccfg1);
1802         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1803         gfar_write(&regs->maccfg1, tempval);
1804
1805         /* Initialize DMACTRL to have WWR and WOP */
1806         tempval = gfar_read(&regs->dmactrl);
1807         tempval |= DMACTRL_INIT_SETTINGS;
1808         gfar_write(&regs->dmactrl, tempval);
1809
1810         /* Make sure we aren't stopped */
1811         tempval = gfar_read(&regs->dmactrl);
1812         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1813         gfar_write(&regs->dmactrl, tempval);
1814
1815         for (i = 0; i < priv->num_grps; i++) {
1816                 regs = priv->gfargrp[i].regs;
1817                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1818                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1819                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1820                 /* Unmask the interrupts we look for */
1821                 gfar_write(&regs->imask, IMASK_DEFAULT);
1822         }
1823
1824         dev->trans_start = jiffies; /* prevent tx timeout */
1825 }
1826
1827 static void gfar_configure_coalescing(struct gfar_private *priv,
1828                                unsigned long tx_mask, unsigned long rx_mask)
1829 {
1830         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1831         u32 __iomem *baddr;
1832
1833         if (priv->mode == MQ_MG_MODE) {
1834                 int i = 0;
1835
1836                 baddr = &regs->txic0;
1837                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1838                         gfar_write(baddr + i, 0);
1839                         if (likely(priv->tx_queue[i]->txcoalescing))
1840                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1841                 }
1842
1843                 baddr = &regs->rxic0;
1844                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1845                         gfar_write(baddr + i, 0);
1846                         if (likely(priv->rx_queue[i]->rxcoalescing))
1847                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1848                 }
1849         } else {
1850                 /* Backward compatible case -- even if we enable
1851                  * multiple queues, there's only single reg to program
1852                  */
1853                 gfar_write(&regs->txic, 0);
1854                 if (likely(priv->tx_queue[0]->txcoalescing))
1855                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1856
1857                 gfar_write(&regs->rxic, 0);
1858                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1859                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1860         }
1861 }
1862
1863 void gfar_configure_coalescing_all(struct gfar_private *priv)
1864 {
1865         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1866 }
1867
1868 static int register_grp_irqs(struct gfar_priv_grp *grp)
1869 {
1870         struct gfar_private *priv = grp->priv;
1871         struct net_device *dev = priv->ndev;
1872         int err;
1873
1874         /* If the device has multiple interrupts, register for
1875          * them.  Otherwise, only register for the one
1876          */
1877         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1878                 /* Install our interrupt handlers for Error,
1879                  * Transmit, and Receive
1880                  */
1881                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1882                                   gfar_irq(grp, ER)->name, grp);
1883                 if (err < 0) {
1884                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1885                                   gfar_irq(grp, ER)->irq);
1886
1887                         goto err_irq_fail;
1888                 }
1889                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1890                                   gfar_irq(grp, TX)->name, grp);
1891                 if (err < 0) {
1892                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1893                                   gfar_irq(grp, TX)->irq);
1894                         goto tx_irq_fail;
1895                 }
1896                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1897                                   gfar_irq(grp, RX)->name, grp);
1898                 if (err < 0) {
1899                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1900                                   gfar_irq(grp, RX)->irq);
1901                         goto rx_irq_fail;
1902                 }
1903         } else {
1904                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1905                                   gfar_irq(grp, TX)->name, grp);
1906                 if (err < 0) {
1907                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1908                                   gfar_irq(grp, TX)->irq);
1909                         goto err_irq_fail;
1910                 }
1911         }
1912
1913         return 0;
1914
1915 rx_irq_fail:
1916         free_irq(gfar_irq(grp, TX)->irq, grp);
1917 tx_irq_fail:
1918         free_irq(gfar_irq(grp, ER)->irq, grp);
1919 err_irq_fail:
1920         return err;
1921
1922 }
1923
1924 /* Bring the controller up and running */
1925 int startup_gfar(struct net_device *ndev)
1926 {
1927         struct gfar_private *priv = netdev_priv(ndev);
1928         struct gfar __iomem *regs = NULL;
1929         int err, i, j;
1930
1931         for (i = 0; i < priv->num_grps; i++) {
1932                 regs= priv->gfargrp[i].regs;
1933                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1934         }
1935
1936         regs= priv->gfargrp[0].regs;
1937         err = gfar_alloc_skb_resources(ndev);
1938         if (err)
1939                 return err;
1940
1941         gfar_init_mac(ndev);
1942
1943         for (i = 0; i < priv->num_grps; i++) {
1944                 err = register_grp_irqs(&priv->gfargrp[i]);
1945                 if (err) {
1946                         for (j = 0; j < i; j++)
1947                                 free_grp_irqs(&priv->gfargrp[j]);
1948                         goto irq_fail;
1949                 }
1950         }
1951
1952         /* Start the controller */
1953         gfar_start(ndev);
1954
1955         phy_start(priv->phydev);
1956
1957         gfar_configure_coalescing_all(priv);
1958
1959         return 0;
1960
1961 irq_fail:
1962         free_skb_resources(priv);
1963         return err;
1964 }
1965
1966 /* Called when something needs to use the ethernet device
1967  * Returns 0 for success.
1968  */
1969 static int gfar_enet_open(struct net_device *dev)
1970 {
1971         struct gfar_private *priv = netdev_priv(dev);
1972         int err;
1973
1974         enable_napi(priv);
1975
1976         /* Initialize a bunch of registers */
1977         init_registers(dev);
1978
1979         gfar_set_mac_address(dev);
1980
1981         err = init_phy(dev);
1982
1983         if (err) {
1984                 disable_napi(priv);
1985                 return err;
1986         }
1987
1988         err = startup_gfar(dev);
1989         if (err) {
1990                 disable_napi(priv);
1991                 return err;
1992         }
1993
1994         netif_tx_start_all_queues(dev);
1995
1996         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1997
1998         return err;
1999 }
2000
2001 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2002 {
2003         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2004
2005         memset(fcb, 0, GMAC_FCB_LEN);
2006
2007         return fcb;
2008 }
2009
2010 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2011                                     int fcb_length)
2012 {
2013         /* If we're here, it's a IP packet with a TCP or UDP
2014          * payload.  We set it to checksum, using a pseudo-header
2015          * we provide
2016          */
2017         u8 flags = TXFCB_DEFAULT;
2018
2019         /* Tell the controller what the protocol is
2020          * And provide the already calculated phcs
2021          */
2022         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2023                 flags |= TXFCB_UDP;
2024                 fcb->phcs = udp_hdr(skb)->check;
2025         } else
2026                 fcb->phcs = tcp_hdr(skb)->check;
2027
2028         /* l3os is the distance between the start of the
2029          * frame (skb->data) and the start of the IP hdr.
2030          * l4os is the distance between the start of the
2031          * l3 hdr and the l4 hdr
2032          */
2033         fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2034         fcb->l4os = skb_network_header_len(skb);
2035
2036         fcb->flags = flags;
2037 }
2038
2039 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2040 {
2041         fcb->flags |= TXFCB_VLN;
2042         fcb->vlctl = vlan_tx_tag_get(skb);
2043 }
2044
2045 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2046                                       struct txbd8 *base, int ring_size)
2047 {
2048         struct txbd8 *new_bd = bdp + stride;
2049
2050         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2051 }
2052
2053 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2054                                       int ring_size)
2055 {
2056         return skip_txbd(bdp, 1, base, ring_size);
2057 }
2058
2059 /* eTSEC12: csum generation not supported for some fcb offsets */
2060 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2061                                        unsigned long fcb_addr)
2062 {
2063         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2064                (fcb_addr % 0x20) > 0x18);
2065 }
2066
2067 /* eTSEC76: csum generation for frames larger than 2500 may
2068  * cause excess delays before start of transmission
2069  */
2070 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2071                                        unsigned int len)
2072 {
2073         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2074                (len > 2500));
2075 }
2076
2077 /* This is called by the kernel when a frame is ready for transmission.
2078  * It is pointed to by the dev->hard_start_xmit function pointer
2079  */
2080 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2081 {
2082         struct gfar_private *priv = netdev_priv(dev);
2083         struct gfar_priv_tx_q *tx_queue = NULL;
2084         struct netdev_queue *txq;
2085         struct gfar __iomem *regs = NULL;
2086         struct txfcb *fcb = NULL;
2087         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2088         u32 lstatus;
2089         int i, rq = 0;
2090         int do_tstamp, do_csum, do_vlan;
2091         u32 bufaddr;
2092         unsigned long flags;
2093         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2094
2095         rq = skb->queue_mapping;
2096         tx_queue = priv->tx_queue[rq];
2097         txq = netdev_get_tx_queue(dev, rq);
2098         base = tx_queue->tx_bd_base;
2099         regs = tx_queue->grp->regs;
2100
2101         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2102         do_vlan = vlan_tx_tag_present(skb);
2103         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2104                     priv->hwts_tx_en;
2105
2106         if (do_csum || do_vlan)
2107                 fcb_len = GMAC_FCB_LEN;
2108
2109         /* check if time stamp should be generated */
2110         if (unlikely(do_tstamp))
2111                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2112
2113         /* make space for additional header when fcb is needed */
2114         if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2115                 struct sk_buff *skb_new;
2116
2117                 skb_new = skb_realloc_headroom(skb, fcb_len);
2118                 if (!skb_new) {
2119                         dev->stats.tx_errors++;
2120                         kfree_skb(skb);
2121                         return NETDEV_TX_OK;
2122                 }
2123
2124                 if (skb->sk)
2125                         skb_set_owner_w(skb_new, skb->sk);
2126                 consume_skb(skb);
2127                 skb = skb_new;
2128         }
2129
2130         /* total number of fragments in the SKB */
2131         nr_frags = skb_shinfo(skb)->nr_frags;
2132
2133         /* calculate the required number of TxBDs for this skb */
2134         if (unlikely(do_tstamp))
2135                 nr_txbds = nr_frags + 2;
2136         else
2137                 nr_txbds = nr_frags + 1;
2138
2139         /* check if there is space to queue this packet */
2140         if (nr_txbds > tx_queue->num_txbdfree) {
2141                 /* no space, stop the queue */
2142                 netif_tx_stop_queue(txq);
2143                 dev->stats.tx_fifo_errors++;
2144                 return NETDEV_TX_BUSY;
2145         }
2146
2147         /* Update transmit stats */
2148         bytes_sent = skb->len;
2149         tx_queue->stats.tx_bytes += bytes_sent;
2150         /* keep Tx bytes on wire for BQL accounting */
2151         GFAR_CB(skb)->bytes_sent = bytes_sent;
2152         tx_queue->stats.tx_packets++;
2153
2154         txbdp = txbdp_start = tx_queue->cur_tx;
2155         lstatus = txbdp->lstatus;
2156
2157         /* Time stamp insertion requires one additional TxBD */
2158         if (unlikely(do_tstamp))
2159                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2160                                                  tx_queue->tx_ring_size);
2161
2162         if (nr_frags == 0) {
2163                 if (unlikely(do_tstamp))
2164                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2165                                                           TXBD_INTERRUPT);
2166                 else
2167                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2168         } else {
2169                 /* Place the fragment addresses and lengths into the TxBDs */
2170                 for (i = 0; i < nr_frags; i++) {
2171                         unsigned int frag_len;
2172                         /* Point at the next BD, wrapping as needed */
2173                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2174
2175                         frag_len = skb_shinfo(skb)->frags[i].size;
2176
2177                         lstatus = txbdp->lstatus | frag_len |
2178                                   BD_LFLAG(TXBD_READY);
2179
2180                         /* Handle the last BD specially */
2181                         if (i == nr_frags - 1)
2182                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2183
2184                         bufaddr = skb_frag_dma_map(priv->dev,
2185                                                    &skb_shinfo(skb)->frags[i],
2186                                                    0,
2187                                                    frag_len,
2188                                                    DMA_TO_DEVICE);
2189
2190                         /* set the TxBD length and buffer pointer */
2191                         txbdp->bufPtr = bufaddr;
2192                         txbdp->lstatus = lstatus;
2193                 }
2194
2195                 lstatus = txbdp_start->lstatus;
2196         }
2197
2198         /* Add TxPAL between FCB and frame if required */
2199         if (unlikely(do_tstamp)) {
2200                 skb_push(skb, GMAC_TXPAL_LEN);
2201                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2202         }
2203
2204         /* Add TxFCB if required */
2205         if (fcb_len) {
2206                 fcb = gfar_add_fcb(skb);
2207                 lstatus |= BD_LFLAG(TXBD_TOE);
2208         }
2209
2210         /* Set up checksumming */
2211         if (do_csum) {
2212                 gfar_tx_checksum(skb, fcb, fcb_len);
2213
2214                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2215                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
2216                         __skb_pull(skb, GMAC_FCB_LEN);
2217                         skb_checksum_help(skb);
2218                         if (do_vlan || do_tstamp) {
2219                                 /* put back a new fcb for vlan/tstamp TOE */
2220                                 fcb = gfar_add_fcb(skb);
2221                         } else {
2222                                 /* Tx TOE not used */
2223                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2224                                 fcb = NULL;
2225                         }
2226                 }
2227         }
2228
2229         if (do_vlan)
2230                 gfar_tx_vlan(skb, fcb);
2231
2232         /* Setup tx hardware time stamping if requested */
2233         if (unlikely(do_tstamp)) {
2234                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2235                 fcb->ptp = 1;
2236         }
2237
2238         txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
2239                                              skb_headlen(skb), DMA_TO_DEVICE);
2240
2241         /* If time stamping is requested one additional TxBD must be set up. The
2242          * first TxBD points to the FCB and must have a data length of
2243          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2244          * the full frame length.
2245          */
2246         if (unlikely(do_tstamp)) {
2247                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len;
2248                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2249                                          (skb_headlen(skb) - fcb_len);
2250                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2251         } else {
2252                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2253         }
2254
2255         netdev_tx_sent_queue(txq, bytes_sent);
2256
2257         /* We can work in parallel with gfar_clean_tx_ring(), except
2258          * when modifying num_txbdfree. Note that we didn't grab the lock
2259          * when we were reading the num_txbdfree and checking for available
2260          * space, that's because outside of this function it can only grow,
2261          * and once we've got needed space, it cannot suddenly disappear.
2262          *
2263          * The lock also protects us from gfar_error(), which can modify
2264          * regs->tstat and thus retrigger the transfers, which is why we
2265          * also must grab the lock before setting ready bit for the first
2266          * to be transmitted BD.
2267          */
2268         spin_lock_irqsave(&tx_queue->txlock, flags);
2269
2270         /* The powerpc-specific eieio() is used, as wmb() has too strong
2271          * semantics (it requires synchronization between cacheable and
2272          * uncacheable mappings, which eieio doesn't provide and which we
2273          * don't need), thus requiring a more expensive sync instruction.  At
2274          * some point, the set of architecture-independent barrier functions
2275          * should be expanded to include weaker barriers.
2276          */
2277         eieio();
2278
2279         txbdp_start->lstatus = lstatus;
2280
2281         eieio(); /* force lstatus write before tx_skbuff */
2282
2283         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2284
2285         /* Update the current skb pointer to the next entry we will use
2286          * (wrapping if necessary)
2287          */
2288         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2289                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2290
2291         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2292
2293         /* reduce TxBD free count */
2294         tx_queue->num_txbdfree -= (nr_txbds);
2295
2296         /* If the next BD still needs to be cleaned up, then the bds
2297          * are full.  We need to tell the kernel to stop sending us stuff.
2298          */
2299         if (!tx_queue->num_txbdfree) {
2300                 netif_tx_stop_queue(txq);
2301
2302                 dev->stats.tx_fifo_errors++;
2303         }
2304
2305         /* Tell the DMA to go go go */
2306         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2307
2308         /* Unlock priv */
2309         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2310
2311         return NETDEV_TX_OK;
2312 }
2313
2314 /* Stops the kernel queue, and halts the controller */
2315 static int gfar_close(struct net_device *dev)
2316 {
2317         struct gfar_private *priv = netdev_priv(dev);
2318
2319         disable_napi(priv);
2320
2321         cancel_work_sync(&priv->reset_task);
2322         stop_gfar(dev);
2323
2324         /* Disconnect from the PHY */
2325         phy_disconnect(priv->phydev);
2326         priv->phydev = NULL;
2327
2328         netif_tx_stop_all_queues(dev);
2329
2330         return 0;
2331 }
2332
2333 /* Changes the mac address if the controller is not running. */
2334 static int gfar_set_mac_address(struct net_device *dev)
2335 {
2336         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2337
2338         return 0;
2339 }
2340
2341 /* Check if rx parser should be activated */
2342 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2343 {
2344         struct gfar __iomem *regs;
2345         u32 tempval;
2346
2347         regs = priv->gfargrp[0].regs;
2348
2349         tempval = gfar_read(&regs->rctrl);
2350         /* If parse is no longer required, then disable parser */
2351         if (tempval & RCTRL_REQ_PARSER) {
2352                 tempval |= RCTRL_PRSDEP_INIT;
2353                 priv->uses_rxfcb = 1;
2354         } else {
2355                 tempval &= ~RCTRL_PRSDEP_INIT;
2356                 priv->uses_rxfcb = 0;
2357         }
2358         gfar_write(&regs->rctrl, tempval);
2359 }
2360
2361 /* Enables and disables VLAN insertion/extraction */
2362 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2363 {
2364         struct gfar_private *priv = netdev_priv(dev);
2365         struct gfar __iomem *regs = NULL;
2366         unsigned long flags;
2367         u32 tempval;
2368
2369         regs = priv->gfargrp[0].regs;
2370         local_irq_save(flags);
2371         lock_rx_qs(priv);
2372
2373         if (features & NETIF_F_HW_VLAN_CTAG_TX) {
2374                 /* Enable VLAN tag insertion */
2375                 tempval = gfar_read(&regs->tctrl);
2376                 tempval |= TCTRL_VLINS;
2377                 gfar_write(&regs->tctrl, tempval);
2378         } else {
2379                 /* Disable VLAN tag insertion */
2380                 tempval = gfar_read(&regs->tctrl);
2381                 tempval &= ~TCTRL_VLINS;
2382                 gfar_write(&regs->tctrl, tempval);
2383         }
2384
2385         if (features & NETIF_F_HW_VLAN_CTAG_RX) {
2386                 /* Enable VLAN tag extraction */
2387                 tempval = gfar_read(&regs->rctrl);
2388                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2389                 gfar_write(&regs->rctrl, tempval);
2390                 priv->uses_rxfcb = 1;
2391         } else {
2392                 /* Disable VLAN tag extraction */
2393                 tempval = gfar_read(&regs->rctrl);
2394                 tempval &= ~RCTRL_VLEX;
2395                 gfar_write(&regs->rctrl, tempval);
2396
2397                 gfar_check_rx_parser_mode(priv);
2398         }
2399
2400         gfar_change_mtu(dev, dev->mtu);
2401
2402         unlock_rx_qs(priv);
2403         local_irq_restore(flags);
2404 }
2405
2406 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2407 {
2408         int tempsize, tempval;
2409         struct gfar_private *priv = netdev_priv(dev);
2410         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2411         int oldsize = priv->rx_buffer_size;
2412         int frame_size = new_mtu + ETH_HLEN;
2413
2414         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2415                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2416                 return -EINVAL;
2417         }
2418
2419         if (priv->uses_rxfcb)
2420                 frame_size += GMAC_FCB_LEN;
2421
2422         frame_size += priv->padding;
2423
2424         tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2425                    INCREMENTAL_BUFFER_SIZE;
2426
2427         /* Only stop and start the controller if it isn't already
2428          * stopped, and we changed something
2429          */
2430         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2431                 stop_gfar(dev);
2432
2433         priv->rx_buffer_size = tempsize;
2434
2435         dev->mtu = new_mtu;
2436
2437         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2438         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2439
2440         /* If the mtu is larger than the max size for standard
2441          * ethernet frames (ie, a jumbo frame), then set maccfg2
2442          * to allow huge frames, and to check the length
2443          */
2444         tempval = gfar_read(&regs->maccfg2);
2445
2446         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2447             gfar_has_errata(priv, GFAR_ERRATA_74))
2448                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2449         else
2450                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2451
2452         gfar_write(&regs->maccfg2, tempval);
2453
2454         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2455                 startup_gfar(dev);
2456
2457         return 0;
2458 }
2459
2460 /* gfar_reset_task gets scheduled when a packet has not been
2461  * transmitted after a set amount of time.
2462  * For now, assume that clearing out all the structures, and
2463  * starting over will fix the problem.
2464  */
2465 static void gfar_reset_task(struct work_struct *work)
2466 {
2467         struct gfar_private *priv = container_of(work, struct gfar_private,
2468                                                  reset_task);
2469         struct net_device *dev = priv->ndev;
2470
2471         if (dev->flags & IFF_UP) {
2472                 netif_tx_stop_all_queues(dev);
2473                 stop_gfar(dev);
2474                 startup_gfar(dev);
2475                 netif_tx_start_all_queues(dev);
2476         }
2477
2478         netif_tx_schedule_all(dev);
2479 }
2480
2481 static void gfar_timeout(struct net_device *dev)
2482 {
2483         struct gfar_private *priv = netdev_priv(dev);
2484
2485         dev->stats.tx_errors++;
2486         schedule_work(&priv->reset_task);
2487 }
2488
2489 static void gfar_align_skb(struct sk_buff *skb)
2490 {
2491         /* We need the data buffer to be aligned properly.  We will reserve
2492          * as many bytes as needed to align the data properly
2493          */
2494         skb_reserve(skb, RXBUF_ALIGNMENT -
2495                     (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2496 }
2497
2498 /* Interrupt Handler for Transmit complete */
2499 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2500 {
2501         struct net_device *dev = tx_queue->dev;
2502         struct netdev_queue *txq;
2503         struct gfar_private *priv = netdev_priv(dev);
2504         struct txbd8 *bdp, *next = NULL;
2505         struct txbd8 *lbdp = NULL;
2506         struct txbd8 *base = tx_queue->tx_bd_base;
2507         struct sk_buff *skb;
2508         int skb_dirtytx;
2509         int tx_ring_size = tx_queue->tx_ring_size;
2510         int frags = 0, nr_txbds = 0;
2511         int i;
2512         int howmany = 0;
2513         int tqi = tx_queue->qindex;
2514         unsigned int bytes_sent = 0;
2515         u32 lstatus;
2516         size_t buflen;
2517
2518         txq = netdev_get_tx_queue(dev, tqi);
2519         bdp = tx_queue->dirty_tx;
2520         skb_dirtytx = tx_queue->skb_dirtytx;
2521
2522         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2523                 unsigned long flags;
2524
2525                 frags = skb_shinfo(skb)->nr_frags;
2526
2527                 /* When time stamping, one additional TxBD must be freed.
2528                  * Also, we need to dma_unmap_single() the TxPAL.
2529                  */
2530                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2531                         nr_txbds = frags + 2;
2532                 else
2533                         nr_txbds = frags + 1;
2534
2535                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2536
2537                 lstatus = lbdp->lstatus;
2538
2539                 /* Only clean completed frames */
2540                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2541                     (lstatus & BD_LENGTH_MASK))
2542                         break;
2543
2544                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2545                         next = next_txbd(bdp, base, tx_ring_size);
2546                         buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2547                 } else
2548                         buflen = bdp->length;
2549
2550                 dma_unmap_single(priv->dev, bdp->bufPtr,
2551                                  buflen, DMA_TO_DEVICE);
2552
2553                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2554                         struct skb_shared_hwtstamps shhwtstamps;
2555                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2556
2557                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2558                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2559                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2560                         skb_tstamp_tx(skb, &shhwtstamps);
2561                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2562                         bdp = next;
2563                 }
2564
2565                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2566                 bdp = next_txbd(bdp, base, tx_ring_size);
2567
2568                 for (i = 0; i < frags; i++) {
2569                         dma_unmap_page(priv->dev, bdp->bufPtr,
2570                                        bdp->length, DMA_TO_DEVICE);
2571                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2572                         bdp = next_txbd(bdp, base, tx_ring_size);
2573                 }
2574
2575                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2576
2577                 dev_kfree_skb_any(skb);
2578
2579                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2580
2581                 skb_dirtytx = (skb_dirtytx + 1) &
2582                               TX_RING_MOD_MASK(tx_ring_size);
2583
2584                 howmany++;
2585                 spin_lock_irqsave(&tx_queue->txlock, flags);
2586                 tx_queue->num_txbdfree += nr_txbds;
2587                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2588         }
2589
2590         /* If we freed a buffer, we can restart transmission, if necessary */
2591         if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2592                 netif_wake_subqueue(dev, tqi);
2593
2594         /* Update dirty indicators */
2595         tx_queue->skb_dirtytx = skb_dirtytx;
2596         tx_queue->dirty_tx = bdp;
2597
2598         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2599 }
2600
2601 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2602 {
2603         unsigned long flags;
2604
2605         spin_lock_irqsave(&gfargrp->grplock, flags);
2606         if (napi_schedule_prep(&gfargrp->napi)) {
2607                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2608                 __napi_schedule(&gfargrp->napi);
2609         } else {
2610                 /* Clear IEVENT, so interrupts aren't called again
2611                  * because of the packets that have already arrived.
2612                  */
2613                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2614         }
2615         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2616
2617 }
2618
2619 /* Interrupt Handler for Transmit complete */
2620 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2621 {
2622         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2623         return IRQ_HANDLED;
2624 }
2625
2626 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2627                            struct sk_buff *skb)
2628 {
2629         struct net_device *dev = rx_queue->dev;
2630         struct gfar_private *priv = netdev_priv(dev);
2631         dma_addr_t buf;
2632
2633         buf = dma_map_single(priv->dev, skb->data,
2634                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2635         gfar_init_rxbdp(rx_queue, bdp, buf);
2636 }
2637
2638 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2639 {
2640         struct gfar_private *priv = netdev_priv(dev);
2641         struct sk_buff *skb;
2642
2643         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2644         if (!skb)
2645                 return NULL;
2646
2647         gfar_align_skb(skb);
2648
2649         return skb;
2650 }
2651
2652 struct sk_buff *gfar_new_skb(struct net_device *dev)
2653 {
2654         return gfar_alloc_skb(dev);
2655 }
2656
2657 static inline void count_errors(unsigned short status, struct net_device *dev)
2658 {
2659         struct gfar_private *priv = netdev_priv(dev);
2660         struct net_device_stats *stats = &dev->stats;
2661         struct gfar_extra_stats *estats = &priv->extra_stats;
2662
2663         /* If the packet was truncated, none of the other errors matter */
2664         if (status & RXBD_TRUNCATED) {
2665                 stats->rx_length_errors++;
2666
2667                 atomic64_inc(&estats->rx_trunc);
2668
2669                 return;
2670         }
2671         /* Count the errors, if there were any */
2672         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2673                 stats->rx_length_errors++;
2674
2675                 if (status & RXBD_LARGE)
2676                         atomic64_inc(&estats->rx_large);
2677                 else
2678                         atomic64_inc(&estats->rx_short);
2679         }
2680         if (status & RXBD_NONOCTET) {
2681                 stats->rx_frame_errors++;
2682                 atomic64_inc(&estats->rx_nonoctet);
2683         }
2684         if (status & RXBD_CRCERR) {
2685                 atomic64_inc(&estats->rx_crcerr);
2686                 stats->rx_crc_errors++;
2687         }
2688         if (status & RXBD_OVERRUN) {
2689                 atomic64_inc(&estats->rx_overrun);
2690                 stats->rx_crc_errors++;
2691         }
2692 }
2693
2694 irqreturn_t gfar_receive(int irq, void *grp_id)
2695 {
2696         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2697         return IRQ_HANDLED;
2698 }
2699
2700 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2701 {
2702         /* If valid headers were found, and valid sums
2703          * were verified, then we tell the kernel that no
2704          * checksumming is necessary.  Otherwise, it is [FIXME]
2705          */
2706         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2707                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2708         else
2709                 skb_checksum_none_assert(skb);
2710 }
2711
2712
2713 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2714 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2715                                int amount_pull, struct napi_struct *napi)
2716 {
2717         struct gfar_private *priv = netdev_priv(dev);
2718         struct rxfcb *fcb = NULL;
2719
2720         /* fcb is at the beginning if exists */
2721         fcb = (struct rxfcb *)skb->data;
2722
2723         /* Remove the FCB from the skb
2724          * Remove the padded bytes, if there are any
2725          */
2726         if (amount_pull) {
2727                 skb_record_rx_queue(skb, fcb->rq);
2728                 skb_pull(skb, amount_pull);
2729         }
2730
2731         /* Get receive timestamp from the skb */
2732         if (priv->hwts_rx_en) {
2733                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2734                 u64 *ns = (u64 *) skb->data;
2735
2736                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2737                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2738         }
2739
2740         if (priv->padding)
2741                 skb_pull(skb, priv->padding);
2742
2743         if (dev->features & NETIF_F_RXCSUM)
2744                 gfar_rx_checksum(skb, fcb);
2745
2746         /* Tell the skb what kind of packet this is */
2747         skb->protocol = eth_type_trans(skb, dev);
2748
2749         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2750          * Even if vlan rx accel is disabled, on some chips
2751          * RXFCB_VLN is pseudo randomly set.
2752          */
2753         if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2754             fcb->flags & RXFCB_VLN)
2755                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl);
2756
2757         /* Send the packet up the stack */
2758         napi_gro_receive(napi, skb);
2759
2760 }
2761
2762 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2763  * until the budget/quota has been reached. Returns the number
2764  * of frames handled
2765  */
2766 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2767 {
2768         struct net_device *dev = rx_queue->dev;
2769         struct rxbd8 *bdp, *base;
2770         struct sk_buff *skb;
2771         int pkt_len;
2772         int amount_pull;
2773         int howmany = 0;
2774         struct gfar_private *priv = netdev_priv(dev);
2775
2776         /* Get the first full descriptor */
2777         bdp = rx_queue->cur_rx;
2778         base = rx_queue->rx_bd_base;
2779
2780         amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2781
2782         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2783                 struct sk_buff *newskb;
2784
2785                 rmb();
2786
2787                 /* Add another skb for the future */
2788                 newskb = gfar_new_skb(dev);
2789
2790                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2791
2792                 dma_unmap_single(priv->dev, bdp->bufPtr,
2793                                  priv->rx_buffer_size, DMA_FROM_DEVICE);
2794
2795                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2796                              bdp->length > priv->rx_buffer_size))
2797                         bdp->status = RXBD_LARGE;
2798
2799                 /* We drop the frame if we failed to allocate a new buffer */
2800                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2801                              bdp->status & RXBD_ERR)) {
2802                         count_errors(bdp->status, dev);
2803
2804                         if (unlikely(!newskb))
2805                                 newskb = skb;
2806                         else if (skb)
2807                                 dev_kfree_skb(skb);
2808                 } else {
2809                         /* Increment the number of packets */
2810                         rx_queue->stats.rx_packets++;
2811                         howmany++;
2812
2813                         if (likely(skb)) {
2814                                 pkt_len = bdp->length - ETH_FCS_LEN;
2815                                 /* Remove the FCS from the packet length */
2816                                 skb_put(skb, pkt_len);
2817                                 rx_queue->stats.rx_bytes += pkt_len;
2818                                 skb_record_rx_queue(skb, rx_queue->qindex);
2819                                 gfar_process_frame(dev, skb, amount_pull,
2820                                                    &rx_queue->grp->napi);
2821
2822                         } else {
2823                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2824                                 rx_queue->stats.rx_dropped++;
2825                                 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2826                         }
2827
2828                 }
2829
2830                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2831
2832                 /* Setup the new bdp */
2833                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2834
2835                 /* Update to the next pointer */
2836                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2837
2838                 /* update to point at the next skb */
2839                 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2840                                       RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2841         }
2842
2843         /* Update the current rxbd pointer to be the next one */
2844         rx_queue->cur_rx = bdp;
2845
2846         return howmany;
2847 }
2848
2849 static int gfar_poll_sq(struct napi_struct *napi, int budget)
2850 {
2851         struct gfar_priv_grp *gfargrp =
2852                 container_of(napi, struct gfar_priv_grp, napi);
2853         struct gfar __iomem *regs = gfargrp->regs;
2854         struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0];
2855         struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0];
2856         int work_done = 0;
2857
2858         /* Clear IEVENT, so interrupts aren't called again
2859          * because of the packets that have already arrived
2860          */
2861         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2862
2863         /* run Tx cleanup to completion */
2864         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2865                 gfar_clean_tx_ring(tx_queue);
2866
2867         work_done = gfar_clean_rx_ring(rx_queue, budget);
2868
2869         if (work_done < budget) {
2870                 napi_complete(napi);
2871                 /* Clear the halt bit in RSTAT */
2872                 gfar_write(&regs->rstat, gfargrp->rstat);
2873
2874                 gfar_write(&regs->imask, IMASK_DEFAULT);
2875
2876                 /* If we are coalescing interrupts, update the timer
2877                  * Otherwise, clear it
2878                  */
2879                 gfar_write(&regs->txic, 0);
2880                 if (likely(tx_queue->txcoalescing))
2881                         gfar_write(&regs->txic, tx_queue->txic);
2882
2883                 gfar_write(&regs->rxic, 0);
2884                 if (unlikely(rx_queue->rxcoalescing))
2885                         gfar_write(&regs->rxic, rx_queue->rxic);
2886         }
2887
2888         return work_done;
2889 }
2890
2891 static int gfar_poll(struct napi_struct *napi, int budget)
2892 {
2893         struct gfar_priv_grp *gfargrp =
2894                 container_of(napi, struct gfar_priv_grp, napi);
2895         struct gfar_private *priv = gfargrp->priv;
2896         struct gfar __iomem *regs = gfargrp->regs;
2897         struct gfar_priv_tx_q *tx_queue = NULL;
2898         struct gfar_priv_rx_q *rx_queue = NULL;
2899         int work_done = 0, work_done_per_q = 0;
2900         int i, budget_per_q = 0;
2901         int has_tx_work;
2902         unsigned long rstat_rxf;
2903         int num_act_queues;
2904
2905         /* Clear IEVENT, so interrupts aren't called again
2906          * because of the packets that have already arrived
2907          */
2908         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2909
2910         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
2911
2912         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2913         if (num_act_queues)
2914                 budget_per_q = budget/num_act_queues;
2915
2916         while (1) {
2917                 has_tx_work = 0;
2918                 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2919                         tx_queue = priv->tx_queue[i];
2920                         /* run Tx cleanup to completion */
2921                         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2922                                 gfar_clean_tx_ring(tx_queue);
2923                                 has_tx_work = 1;
2924                         }
2925                 }
2926
2927                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2928                         /* skip queue if not active */
2929                         if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2930                                 continue;
2931
2932                         rx_queue = priv->rx_queue[i];
2933                         work_done_per_q =
2934                                 gfar_clean_rx_ring(rx_queue, budget_per_q);
2935                         work_done += work_done_per_q;
2936
2937                         /* finished processing this queue */
2938                         if (work_done_per_q < budget_per_q) {
2939                                 /* clear active queue hw indication */
2940                                 gfar_write(&regs->rstat,
2941                                            RSTAT_CLEAR_RXF0 >> i);
2942                                 rstat_rxf &= ~(RSTAT_CLEAR_RXF0 >> i);
2943                                 num_act_queues--;
2944
2945                                 if (!num_act_queues)
2946                                         break;
2947                                 /* recompute budget per Rx queue */
2948                                 budget_per_q =
2949                                         (budget - work_done) / num_act_queues;
2950                         }
2951                 }
2952
2953                 if (work_done >= budget)
2954                         break;
2955
2956                 if (!num_act_queues && !has_tx_work) {
2957
2958                         napi_complete(napi);
2959
2960                         /* Clear the halt bit in RSTAT */
2961                         gfar_write(&regs->rstat, gfargrp->rstat);
2962
2963                         gfar_write(&regs->imask, IMASK_DEFAULT);
2964
2965                         /* If we are coalescing interrupts, update the timer
2966                          * Otherwise, clear it
2967                          */
2968                         gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2969                                                   gfargrp->tx_bit_map);
2970                         break;
2971                 }
2972         }
2973
2974         return work_done;
2975 }
2976
2977 #ifdef CONFIG_NET_POLL_CONTROLLER
2978 /* Polling 'interrupt' - used by things like netconsole to send skbs
2979  * without having to re-enable interrupts. It's not called while
2980  * the interrupt routine is executing.
2981  */
2982 static void gfar_netpoll(struct net_device *dev)
2983 {
2984         struct gfar_private *priv = netdev_priv(dev);
2985         int i;
2986
2987         /* If the device has multiple interrupts, run tx/rx */
2988         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2989                 for (i = 0; i < priv->num_grps; i++) {
2990                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
2991
2992                         disable_irq(gfar_irq(grp, TX)->irq);
2993                         disable_irq(gfar_irq(grp, RX)->irq);
2994                         disable_irq(gfar_irq(grp, ER)->irq);
2995                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2996                         enable_irq(gfar_irq(grp, ER)->irq);
2997                         enable_irq(gfar_irq(grp, RX)->irq);
2998                         enable_irq(gfar_irq(grp, TX)->irq);
2999                 }
3000         } else {
3001                 for (i = 0; i < priv->num_grps; i++) {
3002                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3003
3004                         disable_irq(gfar_irq(grp, TX)->irq);
3005                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3006                         enable_irq(gfar_irq(grp, TX)->irq);
3007                 }
3008         }
3009 }
3010 #endif
3011
3012 /* The interrupt handler for devices with one interrupt */
3013 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3014 {
3015         struct gfar_priv_grp *gfargrp = grp_id;
3016
3017         /* Save ievent for future reference */
3018         u32 events = gfar_read(&gfargrp->regs->ievent);
3019
3020         /* Check for reception */
3021         if (events & IEVENT_RX_MASK)
3022                 gfar_receive(irq, grp_id);
3023
3024         /* Check for transmit completion */
3025         if (events & IEVENT_TX_MASK)
3026                 gfar_transmit(irq, grp_id);
3027
3028         /* Check for errors */
3029         if (events & IEVENT_ERR_MASK)
3030                 gfar_error(irq, grp_id);
3031
3032         return IRQ_HANDLED;
3033 }
3034
3035 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3036 {
3037         struct phy_device *phydev = priv->phydev;
3038         u32 val = 0;
3039
3040         if (!phydev->duplex)
3041                 return val;
3042
3043         if (!priv->pause_aneg_en) {
3044                 if (priv->tx_pause_en)
3045                         val |= MACCFG1_TX_FLOW;
3046                 if (priv->rx_pause_en)
3047                         val |= MACCFG1_RX_FLOW;
3048         } else {
3049                 u16 lcl_adv, rmt_adv;
3050                 u8 flowctrl;
3051                 /* get link partner capabilities */
3052                 rmt_adv = 0;
3053                 if (phydev->pause)
3054                         rmt_adv = LPA_PAUSE_CAP;
3055                 if (phydev->asym_pause)
3056                         rmt_adv |= LPA_PAUSE_ASYM;
3057
3058                 lcl_adv = mii_advertise_flowctrl(phydev->advertising);
3059
3060                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3061                 if (flowctrl & FLOW_CTRL_TX)
3062                         val |= MACCFG1_TX_FLOW;
3063                 if (flowctrl & FLOW_CTRL_RX)
3064                         val |= MACCFG1_RX_FLOW;
3065         }
3066
3067         return val;
3068 }
3069
3070 /* Called every time the controller might need to be made
3071  * aware of new link state.  The PHY code conveys this
3072  * information through variables in the phydev structure, and this
3073  * function converts those variables into the appropriate
3074  * register values, and can bring down the device if needed.
3075  */
3076 static void adjust_link(struct net_device *dev)
3077 {
3078         struct gfar_private *priv = netdev_priv(dev);
3079         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3080         unsigned long flags;
3081         struct phy_device *phydev = priv->phydev;
3082         int new_state = 0;
3083
3084         local_irq_save(flags);
3085         lock_tx_qs(priv);
3086
3087         if (phydev->link) {
3088                 u32 tempval1 = gfar_read(&regs->maccfg1);
3089                 u32 tempval = gfar_read(&regs->maccfg2);
3090                 u32 ecntrl = gfar_read(&regs->ecntrl);
3091
3092                 /* Now we make sure that we can be in full duplex mode.
3093                  * If not, we operate in half-duplex mode.
3094                  */
3095                 if (phydev->duplex != priv->oldduplex) {
3096                         new_state = 1;
3097                         if (!(phydev->duplex))
3098                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3099                         else
3100                                 tempval |= MACCFG2_FULL_DUPLEX;
3101
3102                         priv->oldduplex = phydev->duplex;
3103                 }
3104
3105                 if (phydev->speed != priv->oldspeed) {
3106                         new_state = 1;
3107                         switch (phydev->speed) {
3108                         case 1000:
3109                                 tempval =
3110                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3111
3112                                 ecntrl &= ~(ECNTRL_R100);
3113                                 break;
3114                         case 100:
3115                         case 10:
3116                                 tempval =
3117                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3118
3119                                 /* Reduced mode distinguishes
3120                                  * between 10 and 100
3121                                  */
3122                                 if (phydev->speed == SPEED_100)
3123                                         ecntrl |= ECNTRL_R100;
3124                                 else
3125                                         ecntrl &= ~(ECNTRL_R100);
3126                                 break;
3127                         default:
3128                                 netif_warn(priv, link, dev,
3129                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3130                                            phydev->speed);
3131                                 break;
3132                         }
3133
3134                         priv->oldspeed = phydev->speed;
3135                 }
3136
3137                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3138                 tempval1 |= gfar_get_flowctrl_cfg(priv);
3139
3140                 gfar_write(&regs->maccfg1, tempval1);
3141                 gfar_write(&regs->maccfg2, tempval);
3142                 gfar_write(&regs->ecntrl, ecntrl);
3143
3144                 if (!priv->oldlink) {
3145                         new_state = 1;
3146                         priv->oldlink = 1;
3147                 }
3148         } else if (priv->oldlink) {
3149                 new_state = 1;
3150                 priv->oldlink = 0;
3151                 priv->oldspeed = 0;
3152                 priv->oldduplex = -1;
3153         }
3154
3155         if (new_state && netif_msg_link(priv))
3156                 phy_print_status(phydev);
3157         unlock_tx_qs(priv);
3158         local_irq_restore(flags);
3159 }
3160
3161 /* Update the hash table based on the current list of multicast
3162  * addresses we subscribe to.  Also, change the promiscuity of
3163  * the device based on the flags (this function is called
3164  * whenever dev->flags is changed
3165  */
3166 static void gfar_set_multi(struct net_device *dev)
3167 {
3168         struct netdev_hw_addr *ha;
3169         struct gfar_private *priv = netdev_priv(dev);
3170         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3171         u32 tempval;
3172
3173         if (dev->flags & IFF_PROMISC) {
3174                 /* Set RCTRL to PROM */
3175                 tempval = gfar_read(&regs->rctrl);
3176                 tempval |= RCTRL_PROM;
3177                 gfar_write(&regs->rctrl, tempval);
3178         } else {
3179                 /* Set RCTRL to not PROM */
3180                 tempval = gfar_read(&regs->rctrl);
3181                 tempval &= ~(RCTRL_PROM);
3182                 gfar_write(&regs->rctrl, tempval);
3183         }
3184
3185         if (dev->flags & IFF_ALLMULTI) {
3186                 /* Set the hash to rx all multicast frames */
3187                 gfar_write(&regs->igaddr0, 0xffffffff);
3188                 gfar_write(&regs->igaddr1, 0xffffffff);
3189                 gfar_write(&regs->igaddr2, 0xffffffff);
3190                 gfar_write(&regs->igaddr3, 0xffffffff);
3191                 gfar_write(&regs->igaddr4, 0xffffffff);
3192                 gfar_write(&regs->igaddr5, 0xffffffff);
3193                 gfar_write(&regs->igaddr6, 0xffffffff);
3194                 gfar_write(&regs->igaddr7, 0xffffffff);
3195                 gfar_write(&regs->gaddr0, 0xffffffff);
3196                 gfar_write(&regs->gaddr1, 0xffffffff);
3197                 gfar_write(&regs->gaddr2, 0xffffffff);
3198                 gfar_write(&regs->gaddr3, 0xffffffff);
3199                 gfar_write(&regs->gaddr4, 0xffffffff);
3200                 gfar_write(&regs->gaddr5, 0xffffffff);
3201                 gfar_write(&regs->gaddr6, 0xffffffff);
3202                 gfar_write(&regs->gaddr7, 0xffffffff);
3203         } else {
3204                 int em_num;
3205                 int idx;
3206
3207                 /* zero out the hash */
3208                 gfar_write(&regs->igaddr0, 0x0);
3209                 gfar_write(&regs->igaddr1, 0x0);
3210                 gfar_write(&regs->igaddr2, 0x0);
3211                 gfar_write(&regs->igaddr3, 0x0);
3212                 gfar_write(&regs->igaddr4, 0x0);
3213                 gfar_write(&regs->igaddr5, 0x0);
3214                 gfar_write(&regs->igaddr6, 0x0);
3215                 gfar_write(&regs->igaddr7, 0x0);
3216                 gfar_write(&regs->gaddr0, 0x0);
3217                 gfar_write(&regs->gaddr1, 0x0);
3218                 gfar_write(&regs->gaddr2, 0x0);
3219                 gfar_write(&regs->gaddr3, 0x0);
3220                 gfar_write(&regs->gaddr4, 0x0);
3221                 gfar_write(&regs->gaddr5, 0x0);
3222                 gfar_write(&regs->gaddr6, 0x0);
3223                 gfar_write(&regs->gaddr7, 0x0);
3224
3225                 /* If we have extended hash tables, we need to
3226                  * clear the exact match registers to prepare for
3227                  * setting them
3228                  */
3229                 if (priv->extended_hash) {
3230                         em_num = GFAR_EM_NUM + 1;
3231                         gfar_clear_exact_match(dev);
3232                         idx = 1;
3233                 } else {
3234                         idx = 0;
3235                         em_num = 0;
3236                 }
3237
3238                 if (netdev_mc_empty(dev))
3239                         return;
3240
3241                 /* Parse the list, and set the appropriate bits */
3242                 netdev_for_each_mc_addr(ha, dev) {
3243                         if (idx < em_num) {
3244                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3245                                 idx++;
3246                         } else
3247                                 gfar_set_hash_for_addr(dev, ha->addr);
3248                 }
3249         }
3250 }
3251
3252
3253 /* Clears each of the exact match registers to zero, so they
3254  * don't interfere with normal reception
3255  */
3256 static void gfar_clear_exact_match(struct net_device *dev)
3257 {
3258         int idx;
3259         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3260
3261         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3262                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3263 }
3264
3265 /* Set the appropriate hash bit for the given addr */
3266 /* The algorithm works like so:
3267  * 1) Take the Destination Address (ie the multicast address), and
3268  * do a CRC on it (little endian), and reverse the bits of the
3269  * result.
3270  * 2) Use the 8 most significant bits as a hash into a 256-entry
3271  * table.  The table is controlled through 8 32-bit registers:
3272  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3273  * gaddr7.  This means that the 3 most significant bits in the
3274  * hash index which gaddr register to use, and the 5 other bits
3275  * indicate which bit (assuming an IBM numbering scheme, which
3276  * for PowerPC (tm) is usually the case) in the register holds
3277  * the entry.
3278  */
3279 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3280 {
3281         u32 tempval;
3282         struct gfar_private *priv = netdev_priv(dev);
3283         u32 result = ether_crc(ETH_ALEN, addr);
3284         int width = priv->hash_width;
3285         u8 whichbit = (result >> (32 - width)) & 0x1f;
3286         u8 whichreg = result >> (32 - width + 5);
3287         u32 value = (1 << (31-whichbit));
3288
3289         tempval = gfar_read(priv->hash_regs[whichreg]);
3290         tempval |= value;
3291         gfar_write(priv->hash_regs[whichreg], tempval);
3292 }
3293
3294
3295 /* There are multiple MAC Address register pairs on some controllers
3296  * This function sets the numth pair to a given address
3297  */
3298 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3299                                   const u8 *addr)
3300 {
3301         struct gfar_private *priv = netdev_priv(dev);
3302         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3303         int idx;
3304         char tmpbuf[ETH_ALEN];
3305         u32 tempval;
3306         u32 __iomem *macptr = &regs->macstnaddr1;
3307
3308         macptr += num*2;
3309
3310         /* Now copy it into the mac registers backwards, cuz
3311          * little endian is silly
3312          */
3313         for (idx = 0; idx < ETH_ALEN; idx++)
3314                 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3315
3316         gfar_write(macptr, *((u32 *) (tmpbuf)));
3317
3318         tempval = *((u32 *) (tmpbuf + 4));
3319
3320         gfar_write(macptr+1, tempval);
3321 }
3322
3323 /* GFAR error interrupt handler */
3324 static irqreturn_t gfar_error(int irq, void *grp_id)
3325 {
3326         struct gfar_priv_grp *gfargrp = grp_id;
3327         struct gfar __iomem *regs = gfargrp->regs;
3328         struct gfar_private *priv= gfargrp->priv;
3329         struct net_device *dev = priv->ndev;
3330
3331         /* Save ievent for future reference */
3332         u32 events = gfar_read(&regs->ievent);
3333
3334         /* Clear IEVENT */
3335         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3336
3337         /* Magic Packet is not an error. */
3338         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3339             (events & IEVENT_MAG))
3340                 events &= ~IEVENT_MAG;
3341
3342         /* Hmm... */
3343         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3344                 netdev_dbg(dev,
3345                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3346                            events, gfar_read(&regs->imask));
3347
3348         /* Update the error counters */
3349         if (events & IEVENT_TXE) {
3350                 dev->stats.tx_errors++;
3351
3352                 if (events & IEVENT_LC)
3353                         dev->stats.tx_window_errors++;
3354                 if (events & IEVENT_CRL)
3355                         dev->stats.tx_aborted_errors++;
3356                 if (events & IEVENT_XFUN) {
3357                         unsigned long flags;
3358
3359                         netif_dbg(priv, tx_err, dev,
3360                                   "TX FIFO underrun, packet dropped\n");
3361                         dev->stats.tx_dropped++;
3362                         atomic64_inc(&priv->extra_stats.tx_underrun);
3363
3364                         local_irq_save(flags);
3365                         lock_tx_qs(priv);
3366
3367                         /* Reactivate the Tx Queues */
3368                         gfar_write(&regs->tstat, gfargrp->tstat);
3369
3370                         unlock_tx_qs(priv);
3371                         local_irq_restore(flags);
3372                 }
3373                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3374         }
3375         if (events & IEVENT_BSY) {
3376                 dev->stats.rx_errors++;
3377                 atomic64_inc(&priv->extra_stats.rx_bsy);
3378
3379                 gfar_receive(irq, grp_id);
3380
3381                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3382                           gfar_read(&regs->rstat));
3383         }
3384         if (events & IEVENT_BABR) {
3385                 dev->stats.rx_errors++;
3386                 atomic64_inc(&priv->extra_stats.rx_babr);
3387
3388                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3389         }
3390         if (events & IEVENT_EBERR) {
3391                 atomic64_inc(&priv->extra_stats.eberr);
3392                 netif_dbg(priv, rx_err, dev, "bus error\n");
3393         }
3394         if (events & IEVENT_RXC)
3395                 netif_dbg(priv, rx_status, dev, "control frame\n");
3396
3397         if (events & IEVENT_BABT) {
3398                 atomic64_inc(&priv->extra_stats.tx_babt);
3399                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3400         }
3401         return IRQ_HANDLED;
3402 }
3403
3404 static struct of_device_id gfar_match[] =
3405 {
3406         {
3407                 .type = "network",
3408                 .compatible = "gianfar",
3409         },
3410         {
3411                 .compatible = "fsl,etsec2",
3412         },
3413         {},
3414 };
3415 MODULE_DEVICE_TABLE(of, gfar_match);
3416
3417 /* Structure for a device driver */
3418 static struct platform_driver gfar_driver = {
3419         .driver = {
3420                 .name = "fsl-gianfar",
3421                 .owner = THIS_MODULE,
3422                 .pm = GFAR_PM_OPS,
3423                 .of_match_table = gfar_match,
3424         },
3425         .probe = gfar_probe,
3426         .remove = gfar_remove,
3427 };
3428
3429 module_platform_driver(gfar_driver);