drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/of_mdio.h>
  82 #include <linux/of_platform.h>
  83 #include <linux/ip.h>
  84 #include <linux/tcp.h>
  85 #include <linux/udp.h>
  86 #include <linux/in.h>
  87 #include <linux/net_tstamp.h>
  88
  89 #include <asm/io.h>
  90 #include <asm/reg.h>
  91 #include <asm/irq.h>
  92 #include <asm/uaccess.h>
  93 #include <linux/module.h>
  94 #include <linux/dma-mapping.h>
  95 #include <linux/crc32.h>
  96 #include <linux/mii.h>
  97 #include <linux/phy.h>
  98 #include <linux/phy_fixed.h>
  99 #include <linux/of.h>
 100 #include <linux/of_net.h>
 101
 102 #include "gianfar.h"
 103
 104 #define TX_TIMEOUT      (1*HZ)
 105
 106 const char gfar_driver_version[] = "1.3";
 107
 108 static int gfar_enet_open(struct net_device *dev);
 109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 110 static void gfar_reset_task(struct work_struct *work);
 111 static void gfar_timeout(struct net_device *dev);
 112 static int gfar_close(struct net_device *dev);
 113 struct sk_buff *gfar_new_skb(struct net_device *dev);
 114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 115                            struct sk_buff *skb);
 116 static int gfar_set_mac_address(struct net_device *dev);
 117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 118 static irqreturn_t gfar_error(int irq, void *dev_id);
 119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 121 static void adjust_link(struct net_device *dev);
 122 static void init_registers(struct net_device *dev);
 123 static int init_phy(struct net_device *dev);
 124 static int gfar_probe(struct platform_device *ofdev);
 125 static int gfar_remove(struct platform_device *ofdev);
 126 static void free_skb_resources(struct gfar_private *priv);
 127 static void gfar_set_multi(struct net_device *dev);
 128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 129 static void gfar_configure_serdes(struct net_device *dev);
 130 static int gfar_poll(struct napi_struct *napi, int budget);
 131 #ifdef CONFIG_NET_POLL_CONTROLLER
 132 static void gfar_netpoll(struct net_device *dev);
 133 #endif
 134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 136 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 137                                int amount_pull, struct napi_struct *napi);
 138 void gfar_halt(struct net_device *dev);
 139 static void gfar_halt_nodisable(struct net_device *dev);
 140 void gfar_start(struct net_device *dev);
 141 static void gfar_clear_exact_match(struct net_device *dev);
 142 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 143                                   const u8 *addr);
 144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 145
 146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 148 MODULE_LICENSE("GPL");
 149
 150 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 151                             dma_addr_t buf)
 152 {
 153         u32 lstatus;
 154
 155         bdp->bufPtr = buf;
 156
 157         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 158         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 159                 lstatus |= BD_LFLAG(RXBD_WRAP);
 160
 161         eieio();
 162
 163         bdp->lstatus = lstatus;
 164 }
 165
 166 static int gfar_init_bds(struct net_device *ndev)
 167 {
 168         struct gfar_private *priv = netdev_priv(ndev);
 169         struct gfar_priv_tx_q *tx_queue = NULL;
 170         struct gfar_priv_rx_q *rx_queue = NULL;
 171         struct txbd8 *txbdp;
 172         struct rxbd8 *rxbdp;
 173         int i, j;
 174
 175         for (i = 0; i < priv->num_tx_queues; i++) {
 176                 tx_queue = priv->tx_queue[i];
 177                 /* Initialize some variables in our dev structure */
 178                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 179                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 180                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 181                 tx_queue->skb_curtx = 0;
 182                 tx_queue->skb_dirtytx = 0;
 183
 184                 /* Initialize Transmit Descriptor Ring */
 185                 txbdp = tx_queue->tx_bd_base;
 186                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 187                         txbdp->lstatus = 0;
 188                         txbdp->bufPtr = 0;
 189                         txbdp++;
 190                 }
 191
 192                 /* Set the last descriptor in the ring to indicate wrap */
 193                 txbdp--;
 194                 txbdp->status |= TXBD_WRAP;
 195         }
 196
 197         for (i = 0; i < priv->num_rx_queues; i++) {
 198                 rx_queue = priv->rx_queue[i];
 199                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 200                 rx_queue->skb_currx = 0;
 201                 rxbdp = rx_queue->rx_bd_base;
 202
 203                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 204                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 205
 206                         if (skb) {
 207                                 gfar_init_rxbdp(rx_queue, rxbdp,
 208                                                 rxbdp->bufPtr);
 209                         } else {
 210                                 skb = gfar_new_skb(ndev);
 211                                 if (!skb) {
 212                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 213                                         return -ENOMEM;
 214                                 }
 215                                 rx_queue->rx_skbuff[j] = skb;
 216
 217                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 218                         }
 219
 220                         rxbdp++;
 221                 }
 222
 223         }
 224
 225         return 0;
 226 }
 227
 228 static int gfar_alloc_skb_resources(struct net_device *ndev)
 229 {
 230         void *vaddr;
 231         dma_addr_t addr;
 232         int i, j, k;
 233         struct gfar_private *priv = netdev_priv(ndev);
 234         struct device *dev = priv->dev;
 235         struct gfar_priv_tx_q *tx_queue = NULL;
 236         struct gfar_priv_rx_q *rx_queue = NULL;
 237
 238         priv->total_tx_ring_size = 0;
 239         for (i = 0; i < priv->num_tx_queues; i++)
 240                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 241
 242         priv->total_rx_ring_size = 0;
 243         for (i = 0; i < priv->num_rx_queues; i++)
 244                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 245
 246         /* Allocate memory for the buffer descriptors */
 247         vaddr = dma_alloc_coherent(dev,
 248                         sizeof(struct txbd8) * priv->total_tx_ring_size +
 249                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
 250                         &addr, GFP_KERNEL);
 251         if (!vaddr) {
 252                 netif_err(priv, ifup, ndev,
 253                           "Could not allocate buffer descriptors!\n");
 254                 return -ENOMEM;
 255         }
 256
 257         for (i = 0; i < priv->num_tx_queues; i++) {
 258                 tx_queue = priv->tx_queue[i];
 259                 tx_queue->tx_bd_base = vaddr;
 260                 tx_queue->tx_bd_dma_base = addr;
 261                 tx_queue->dev = ndev;
 262                 /* enet DMA only understands physical addresses */
 263                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 264                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 265         }
 266
 267         /* Start the rx descriptor ring where the tx ring leaves off */
 268         for (i = 0; i < priv->num_rx_queues; i++) {
 269                 rx_queue = priv->rx_queue[i];
 270                 rx_queue->rx_bd_base = vaddr;
 271                 rx_queue->rx_bd_dma_base = addr;
 272                 rx_queue->dev = ndev;
 273                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 274                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 275         }
 276
 277         /* Setup the skbuff rings */
 278         for (i = 0; i < priv->num_tx_queues; i++) {
 279                 tx_queue = priv->tx_queue[i];
 280                 tx_queue->tx_skbuff =
 281                         kmalloc_array(tx_queue->tx_ring_size,
 282                                       sizeof(*tx_queue->tx_skbuff),
 283                                       GFP_KERNEL);
 284                 if (!tx_queue->tx_skbuff)
 285                         goto cleanup;
 286
 287                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 288                         tx_queue->tx_skbuff[k] = NULL;
 289         }
 290
 291         for (i = 0; i < priv->num_rx_queues; i++) {
 292                 rx_queue = priv->rx_queue[i];
 293                 rx_queue->rx_skbuff =
 294                         kmalloc_array(rx_queue->rx_ring_size,
 295                                       sizeof(*rx_queue->rx_skbuff),
 296                                       GFP_KERNEL);
 297                 if (!rx_queue->rx_skbuff)
 298                         goto cleanup;
 299
 300                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 301                         rx_queue->rx_skbuff[j] = NULL;
 302         }
 303
 304         if (gfar_init_bds(ndev))
 305                 goto cleanup;
 306
 307         return 0;
 308
 309 cleanup:
 310         free_skb_resources(priv);
 311         return -ENOMEM;
 312 }
 313
 314 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 315 {
 316         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 317         u32 __iomem *baddr;
 318         int i;
 319
 320         baddr = &regs->tbase0;
 321         for (i = 0; i < priv->num_tx_queues; i++) {
 322                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 323                 baddr += 2;
 324         }
 325
 326         baddr = &regs->rbase0;
 327         for (i = 0; i < priv->num_rx_queues; i++) {
 328                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 329                 baddr += 2;
 330         }
 331 }
 332
 333 static void gfar_init_mac(struct net_device *ndev)
 334 {
 335         struct gfar_private *priv = netdev_priv(ndev);
 336         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 337         u32 rctrl = 0;
 338         u32 tctrl = 0;
 339         u32 attrs = 0;
 340
 341         /* write the tx/rx base registers */
 342         gfar_init_tx_rx_base(priv);
 343
 344         /* Configure the coalescing support */
 345         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 346
 347         if (priv->rx_filer_enable) {
 348                 rctrl |= RCTRL_FILREN;
 349                 /* Program the RIR0 reg with the required distribution */
 350                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 351         }
 352
 353         /* Restore PROMISC mode */
 354         if (ndev->flags & IFF_PROMISC)
 355                 rctrl |= RCTRL_PROM;
 356
 357         if (ndev->features & NETIF_F_RXCSUM)
 358                 rctrl |= RCTRL_CHECKSUMMING;
 359
 360         if (priv->extended_hash) {
 361                 rctrl |= RCTRL_EXTHASH;
 362
 363                 gfar_clear_exact_match(ndev);
 364                 rctrl |= RCTRL_EMEN;
 365         }
 366
 367         if (priv->padding) {
 368                 rctrl &= ~RCTRL_PAL_MASK;
 369                 rctrl |= RCTRL_PADDING(priv->padding);
 370         }
 371
 372         /* Insert receive time stamps into padding alignment bytes */
 373         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 374                 rctrl &= ~RCTRL_PAL_MASK;
 375                 rctrl |= RCTRL_PADDING(8);
 376                 priv->padding = 8;
 377         }
 378
 379         /* Enable HW time stamping if requested from user space */
 380         if (priv->hwts_rx_en)
 381                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 382
 383         if (ndev->features & NETIF_F_HW_VLAN_RX)
 384                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 385
 386         /* Init rctrl based on our settings */
 387         gfar_write(&regs->rctrl, rctrl);
 388
 389         if (ndev->features & NETIF_F_IP_CSUM)
 390                 tctrl |= TCTRL_INIT_CSUM;
 391
 392         if (priv->prio_sched_en)
 393                 tctrl |= TCTRL_TXSCHED_PRIO;
 394         else {
 395                 tctrl |= TCTRL_TXSCHED_WRRS;
 396                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 397                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 398         }
 399
 400         gfar_write(&regs->tctrl, tctrl);
 401
 402         /* Set the extraction length and index */
 403         attrs = ATTRELI_EL(priv->rx_stash_size) |
 404                 ATTRELI_EI(priv->rx_stash_index);
 405
 406         gfar_write(&regs->attreli, attrs);
 407
 408         /* Start with defaults, and add stashing or locking
 409          * depending on the approprate variables
 410          */
 411         attrs = ATTR_INIT_SETTINGS;
 412
 413         if (priv->bd_stash_en)
 414                 attrs |= ATTR_BDSTASH;
 415
 416         if (priv->rx_stash_size != 0)
 417                 attrs |= ATTR_BUFSTASH;
 418
 419         gfar_write(&regs->attr, attrs);
 420
 421         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 422         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 423         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 424 }
 425
 426 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 427 {
 428         struct gfar_private *priv = netdev_priv(dev);
 429         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 430         unsigned long tx_packets = 0, tx_bytes = 0;
 431         int i;
 432
 433         for (i = 0; i < priv->num_rx_queues; i++) {
 434                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 435                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 436                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 437         }
 438
 439         dev->stats.rx_packets = rx_packets;
 440         dev->stats.rx_bytes   = rx_bytes;
 441         dev->stats.rx_dropped = rx_dropped;
 442
 443         for (i = 0; i < priv->num_tx_queues; i++) {
 444                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 445                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 446         }
 447
 448         dev->stats.tx_bytes   = tx_bytes;
 449         dev->stats.tx_packets = tx_packets;
 450
 451         return &dev->stats;
 452 }
 453
 454 static const struct net_device_ops gfar_netdev_ops = {
 455         .ndo_open = gfar_enet_open,
 456         .ndo_start_xmit = gfar_start_xmit,
 457         .ndo_stop = gfar_close,
 458         .ndo_change_mtu = gfar_change_mtu,
 459         .ndo_set_features = gfar_set_features,
 460         .ndo_set_rx_mode = gfar_set_multi,
 461         .ndo_tx_timeout = gfar_timeout,
 462         .ndo_do_ioctl = gfar_ioctl,
 463         .ndo_get_stats = gfar_get_stats,
 464         .ndo_set_mac_address = eth_mac_addr,
 465         .ndo_validate_addr = eth_validate_addr,
 466 #ifdef CONFIG_NET_POLL_CONTROLLER
 467         .ndo_poll_controller = gfar_netpoll,
 468 #endif
 469 };
 470
 471 void lock_rx_qs(struct gfar_private *priv)
 472 {
 473         int i;
 474
 475         for (i = 0; i < priv->num_rx_queues; i++)
 476                 spin_lock(&priv->rx_queue[i]->rxlock);
 477 }
 478
 479 void lock_tx_qs(struct gfar_private *priv)
 480 {
 481         int i;
 482
 483         for (i = 0; i < priv->num_tx_queues; i++)
 484                 spin_lock(&priv->tx_queue[i]->txlock);
 485 }
 486
 487 void unlock_rx_qs(struct gfar_private *priv)
 488 {
 489         int i;
 490
 491         for (i = 0; i < priv->num_rx_queues; i++)
 492                 spin_unlock(&priv->rx_queue[i]->rxlock);
 493 }
 494
 495 void unlock_tx_qs(struct gfar_private *priv)
 496 {
 497         int i;
 498
 499         for (i = 0; i < priv->num_tx_queues; i++)
 500                 spin_unlock(&priv->tx_queue[i]->txlock);
 501 }
 502
 503 static bool gfar_is_vlan_on(struct gfar_private *priv)
 504 {
 505         return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
 506                (priv->ndev->features & NETIF_F_HW_VLAN_TX);
 507 }
 508
 509 /* Returns 1 if incoming frames use an FCB */
 510 static inline int gfar_uses_fcb(struct gfar_private *priv)
 511 {
 512         return gfar_is_vlan_on(priv) ||
 513                (priv->ndev->features & NETIF_F_RXCSUM) ||
 514                (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
 515 }
 516
 517 static void free_tx_pointers(struct gfar_private *priv)
 518 {
 519         int i;
 520
 521         for (i = 0; i < priv->num_tx_queues; i++)
 522                 kfree(priv->tx_queue[i]);
 523 }
 524
 525 static void free_rx_pointers(struct gfar_private *priv)
 526 {
 527         int i;
 528
 529         for (i = 0; i < priv->num_rx_queues; i++)
 530                 kfree(priv->rx_queue[i]);
 531 }
 532
 533 static void unmap_group_regs(struct gfar_private *priv)
 534 {
 535         int i;
 536
 537         for (i = 0; i < MAXGROUPS; i++)
 538                 if (priv->gfargrp[i].regs)
 539                         iounmap(priv->gfargrp[i].regs);
 540 }
 541
 542 static void free_gfar_dev(struct gfar_private *priv)
 543 {
 544         int i, j;
 545
 546         for (i = 0; i < priv->num_grps; i++)
 547                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 548                         kfree(priv->gfargrp[i].irqinfo[j]);
 549                         priv->gfargrp[i].irqinfo[j] = NULL;
 550                 }
 551
 552         free_netdev(priv->ndev);
 553 }
 554
 555 static void disable_napi(struct gfar_private *priv)
 556 {
 557         int i;
 558
 559         for (i = 0; i < priv->num_grps; i++)
 560                 napi_disable(&priv->gfargrp[i].napi);
 561 }
 562
 563 static void enable_napi(struct gfar_private *priv)
 564 {
 565         int i;
 566
 567         for (i = 0; i < priv->num_grps; i++)
 568                 napi_enable(&priv->gfargrp[i].napi);
 569 }
 570
 571 static int gfar_parse_group(struct device_node *np,
 572                             struct gfar_private *priv, const char *model)
 573 {
 574         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 575         u32 *queue_mask;
 576         int i;
 577
 578         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 579                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 580                                           GFP_KERNEL);
 581                 if (!grp->irqinfo[i])
 582                         return -ENOMEM;
 583         }
 584
 585         grp->regs = of_iomap(np, 0);
 586         if (!grp->regs)
 587                 return -ENOMEM;
 588
 589         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 590
 591         /* If we aren't the FEC we have multiple interrupts */
 592         if (model && strcasecmp(model, "FEC")) {
 593                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 594                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 595                 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
 596                     gfar_irq(grp, RX)->irq == NO_IRQ ||
 597                     gfar_irq(grp, ER)->irq == NO_IRQ)
 598                         return -EINVAL;
 599         }
 600
 601         grp->grp_id = priv->num_grps;
 602         grp->priv = priv;
 603         spin_lock_init(&grp->grplock);
 604         if (priv->mode == MQ_MG_MODE) {
 605                 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
 606                 grp->rx_bit_map = queue_mask ?
 607                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 608                 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
 609                 grp->tx_bit_map = queue_mask ?
 610                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 611         } else {
 612                 grp->rx_bit_map = 0xFF;
 613                 grp->tx_bit_map = 0xFF;
 614         }
 615         priv->num_grps++;
 616
 617         return 0;
 618 }
 619
 620 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 621 {
 622         const char *model;
 623         const char *ctype;
 624         const void *mac_addr;
 625         int err = 0, i;
 626         struct net_device *dev = NULL;
 627         struct gfar_private *priv = NULL;
 628         struct device_node *np = ofdev->dev.of_node;
 629         struct device_node *child = NULL;
 630         const u32 *stash;
 631         const u32 *stash_len;
 632         const u32 *stash_idx;
 633         unsigned int num_tx_qs, num_rx_qs;
 634         u32 *tx_queues, *rx_queues;
 635
 636         if (!np || !of_device_is_available(np))
 637                 return -ENODEV;
 638
 639         /* parse the num of tx and rx queues */
 640         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 641         num_tx_qs = tx_queues ? *tx_queues : 1;
 642
 643         if (num_tx_qs > MAX_TX_QS) {
 644                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 645                        num_tx_qs, MAX_TX_QS);
 646                 pr_err("Cannot do alloc_etherdev, aborting\n");
 647                 return -EINVAL;
 648         }
 649
 650         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 651         num_rx_qs = rx_queues ? *rx_queues : 1;
 652
 653         if (num_rx_qs > MAX_RX_QS) {
 654                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 655                        num_rx_qs, MAX_RX_QS);
 656                 pr_err("Cannot do alloc_etherdev, aborting\n");
 657                 return -EINVAL;
 658         }
 659
 660         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 661         dev = *pdev;
 662         if (NULL == dev)
 663                 return -ENOMEM;
 664
 665         priv = netdev_priv(dev);
 666         priv->ndev = dev;
 667
 668         priv->num_tx_queues = num_tx_qs;
 669         netif_set_real_num_rx_queues(dev, num_rx_qs);
 670         priv->num_rx_queues = num_rx_qs;
 671         priv->num_grps = 0x0;
 672
 673         /* Init Rx queue filer rule set linked list */
 674         INIT_LIST_HEAD(&priv->rx_list.list);
 675         priv->rx_list.count = 0;
 676         mutex_init(&priv->rx_queue_access);
 677
 678         model = of_get_property(np, "model", NULL);
 679
 680         for (i = 0; i < MAXGROUPS; i++)
 681                 priv->gfargrp[i].regs = NULL;
 682
 683         /* Parse and initialize group specific information */
 684         if (of_device_is_compatible(np, "fsl,etsec2")) {
 685                 priv->mode = MQ_MG_MODE;
 686                 for_each_child_of_node(np, child) {
 687                         err = gfar_parse_group(child, priv, model);
 688                         if (err)
 689                                 goto err_grp_init;
 690                 }
 691         } else {
 692                 priv->mode = SQ_SG_MODE;
 693                 err = gfar_parse_group(np, priv, model);
 694                 if (err)
 695                         goto err_grp_init;
 696         }
 697
 698         for (i = 0; i < priv->num_tx_queues; i++)
 699                priv->tx_queue[i] = NULL;
 700         for (i = 0; i < priv->num_rx_queues; i++)
 701                 priv->rx_queue[i] = NULL;
 702
 703         for (i = 0; i < priv->num_tx_queues; i++) {
 704                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 705                                             GFP_KERNEL);
 706                 if (!priv->tx_queue[i]) {
 707                         err = -ENOMEM;
 708                         goto tx_alloc_failed;
 709                 }
 710                 priv->tx_queue[i]->tx_skbuff = NULL;
 711                 priv->tx_queue[i]->qindex = i;
 712                 priv->tx_queue[i]->dev = dev;
 713                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 714         }
 715
 716         for (i = 0; i < priv->num_rx_queues; i++) {
 717                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 718                                             GFP_KERNEL);
 719                 if (!priv->rx_queue[i]) {
 720                         err = -ENOMEM;
 721                         goto rx_alloc_failed;
 722                 }
 723                 priv->rx_queue[i]->rx_skbuff = NULL;
 724                 priv->rx_queue[i]->qindex = i;
 725                 priv->rx_queue[i]->dev = dev;
 726                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 727         }
 728
 729
 730         stash = of_get_property(np, "bd-stash", NULL);
 731
 732         if (stash) {
 733                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 734                 priv->bd_stash_en = 1;
 735         }
 736
 737         stash_len = of_get_property(np, "rx-stash-len", NULL);
 738
 739         if (stash_len)
 740                 priv->rx_stash_size = *stash_len;
 741
 742         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 743
 744         if (stash_idx)
 745                 priv->rx_stash_index = *stash_idx;
 746
 747         if (stash_len || stash_idx)
 748                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 749
 750         mac_addr = of_get_mac_address(np);
 751
 752         if (mac_addr)
 753                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 754
 755         if (model && !strcasecmp(model, "TSEC"))
 756                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 757                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 758                                      FSL_GIANFAR_DEV_HAS_RMON |
 759                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 760
 761         if (model && !strcasecmp(model, "eTSEC"))
 762                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 763                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 764                                      FSL_GIANFAR_DEV_HAS_RMON |
 765                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 766                                      FSL_GIANFAR_DEV_HAS_PADDING |
 767                                      FSL_GIANFAR_DEV_HAS_CSUM |
 768                                      FSL_GIANFAR_DEV_HAS_VLAN |
 769                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 770                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 771                                      FSL_GIANFAR_DEV_HAS_TIMER;
 772
 773         ctype = of_get_property(np, "phy-connection-type", NULL);
 774
 775         /* We only care about rgmii-id.  The rest are autodetected */
 776         if (ctype && !strcmp(ctype, "rgmii-id"))
 777                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 778         else
 779                 priv->interface = PHY_INTERFACE_MODE_MII;
 780
 781         if (of_get_property(np, "fsl,magic-packet", NULL))
 782                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 783
 784         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 785
 786         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 787         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 788
 789         return 0;
 790
 791 rx_alloc_failed:
 792         free_rx_pointers(priv);
 793 tx_alloc_failed:
 794         free_tx_pointers(priv);
 795 err_grp_init:
 796         unmap_group_regs(priv);
 797         free_gfar_dev(priv);
 798         return err;
 799 }
 800
 801 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 802                                struct ifreq *ifr, int cmd)
 803 {
 804         struct hwtstamp_config config;
 805         struct gfar_private *priv = netdev_priv(netdev);
 806
 807         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 808                 return -EFAULT;
 809
 810         /* reserved for future extensions */
 811         if (config.flags)
 812                 return -EINVAL;
 813
 814         switch (config.tx_type) {
 815         case HWTSTAMP_TX_OFF:
 816                 priv->hwts_tx_en = 0;
 817                 break;
 818         case HWTSTAMP_TX_ON:
 819                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 820                         return -ERANGE;
 821                 priv->hwts_tx_en = 1;
 822                 break;
 823         default:
 824                 return -ERANGE;
 825         }
 826
 827         switch (config.rx_filter) {
 828         case HWTSTAMP_FILTER_NONE:
 829                 if (priv->hwts_rx_en) {
 830                         stop_gfar(netdev);
 831                         priv->hwts_rx_en = 0;
 832                         startup_gfar(netdev);
 833                 }
 834                 break;
 835         default:
 836                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 837                         return -ERANGE;
 838                 if (!priv->hwts_rx_en) {
 839                         stop_gfar(netdev);
 840                         priv->hwts_rx_en = 1;
 841                         startup_gfar(netdev);
 842                 }
 843                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 844                 break;
 845         }
 846
 847         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 848                 -EFAULT : 0;
 849 }
 850
 851 /* Ioctl MII Interface */
 852 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 853 {
 854         struct gfar_private *priv = netdev_priv(dev);
 855
 856         if (!netif_running(dev))
 857                 return -EINVAL;
 858
 859         if (cmd == SIOCSHWTSTAMP)
 860                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 861
 862         if (!priv->phydev)
 863                 return -ENODEV;
 864
 865         return phy_mii_ioctl(priv->phydev, rq, cmd);
 866 }
 867
 868 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 869 {
 870         unsigned int new_bit_map = 0x0;
 871         int mask = 0x1 << (max_qs - 1), i;
 872
 873         for (i = 0; i < max_qs; i++) {
 874                 if (bit_map & mask)
 875                         new_bit_map = new_bit_map + (1 << i);
 876                 mask = mask >> 0x1;
 877         }
 878         return new_bit_map;
 879 }
 880
 881 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 882                                    u32 class)
 883 {
 884         u32 rqfpr = FPR_FILER_MASK;
 885         u32 rqfcr = 0x0;
 886
 887         rqfar--;
 888         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 889         priv->ftp_rqfpr[rqfar] = rqfpr;
 890         priv->ftp_rqfcr[rqfar] = rqfcr;
 891         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 892
 893         rqfar--;
 894         rqfcr = RQFCR_CMP_NOMATCH;
 895         priv->ftp_rqfpr[rqfar] = rqfpr;
 896         priv->ftp_rqfcr[rqfar] = rqfcr;
 897         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 898
 899         rqfar--;
 900         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 901         rqfpr = class;
 902         priv->ftp_rqfcr[rqfar] = rqfcr;
 903         priv->ftp_rqfpr[rqfar] = rqfpr;
 904         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 905
 906         rqfar--;
 907         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 908         rqfpr = class;
 909         priv->ftp_rqfcr[rqfar] = rqfcr;
 910         priv->ftp_rqfpr[rqfar] = rqfpr;
 911         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 912
 913         return rqfar;
 914 }
 915
 916 static void gfar_init_filer_table(struct gfar_private *priv)
 917 {
 918         int i = 0x0;
 919         u32 rqfar = MAX_FILER_IDX;
 920         u32 rqfcr = 0x0;
 921         u32 rqfpr = FPR_FILER_MASK;
 922
 923         /* Default rule */
 924         rqfcr = RQFCR_CMP_MATCH;
 925         priv->ftp_rqfcr[rqfar] = rqfcr;
 926         priv->ftp_rqfpr[rqfar] = rqfpr;
 927         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 928
 929         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 930         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 931         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 932         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 933         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 934         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 935
 936         /* cur_filer_idx indicated the first non-masked rule */
 937         priv->cur_filer_idx = rqfar;
 938
 939         /* Rest are masked rules */
 940         rqfcr = RQFCR_CMP_NOMATCH;
 941         for (i = 0; i < rqfar; i++) {
 942                 priv->ftp_rqfcr[i] = rqfcr;
 943                 priv->ftp_rqfpr[i] = rqfpr;
 944                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 945         }
 946 }
 947
 948 static void gfar_detect_errata(struct gfar_private *priv)
 949 {
 950         struct device *dev = &priv->ofdev->dev;
 951         unsigned int pvr = mfspr(SPRN_PVR);
 952         unsigned int svr = mfspr(SPRN_SVR);
 953         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 954         unsigned int rev = svr & 0xffff;
 955
 956         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 957         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 958             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 959                 priv->errata |= GFAR_ERRATA_74;
 960
 961         /* MPC8313 and MPC837x all rev */
 962         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 963             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 964                 priv->errata |= GFAR_ERRATA_76;
 965
 966         /* MPC8313 and MPC837x all rev */
 967         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 968             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 969                 priv->errata |= GFAR_ERRATA_A002;
 970
 971         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
 972         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
 973             (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
 974                 priv->errata |= GFAR_ERRATA_12;
 975
 976         if (priv->errata)
 977                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 978                          priv->errata);
 979 }
 980
 981 /* Set up the ethernet device structure, private data,
 982  * and anything else we need before we start
 983  */
 984 static int gfar_probe(struct platform_device *ofdev)
 985 {
 986         u32 tempval;
 987         struct net_device *dev = NULL;
 988         struct gfar_private *priv = NULL;
 989         struct gfar __iomem *regs = NULL;
 990         int err = 0, i, grp_idx = 0;
 991         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 992         u32 isrg = 0;
 993         u32 __iomem *baddr;
 994
 995         err = gfar_of_init(ofdev, &dev);
 996
 997         if (err)
 998                 return err;
 999
1000         priv = netdev_priv(dev);
1001         priv->ndev = dev;
1002         priv->ofdev = ofdev;
1003         priv->dev = &ofdev->dev;
1004         SET_NETDEV_DEV(dev, &ofdev->dev);
1005
1006         spin_lock_init(&priv->bflock);
1007         INIT_WORK(&priv->reset_task, gfar_reset_task);
1008
1009         dev_set_drvdata(&ofdev->dev, priv);
1010         regs = priv->gfargrp[0].regs;
1011
1012         gfar_detect_errata(priv);
1013
1014         /* Stop the DMA engine now, in case it was running before
1015          * (The firmware could have used it, and left it running).
1016          */
1017         gfar_halt(dev);
1018
1019         /* Reset MAC layer */
1020         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1021
1022         /* We need to delay at least 3 TX clocks */
1023         udelay(2);
1024
1025         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1026         gfar_write(&regs->maccfg1, tempval);
1027
1028         /* Initialize MACCFG2. */
1029         tempval = MACCFG2_INIT_SETTINGS;
1030         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1031                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1032         gfar_write(&regs->maccfg2, tempval);
1033
1034         /* Initialize ECNTRL */
1035         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1036
1037         /* Set the dev->base_addr to the gfar reg region */
1038         dev->base_addr = (unsigned long) regs;
1039
1040         /* Fill in the dev structure */
1041         dev->watchdog_timeo = TX_TIMEOUT;
1042         dev->mtu = 1500;
1043         dev->netdev_ops = &gfar_netdev_ops;
1044         dev->ethtool_ops = &gfar_ethtool_ops;
1045
1046         /* Register for napi ...We are registering NAPI for each grp */
1047         for (i = 0; i < priv->num_grps; i++)
1048                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1049                                GFAR_DEV_WEIGHT);
1050
1051         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1052                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1053                                    NETIF_F_RXCSUM;
1054                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1055                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1056         }
1057
1058         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1059                 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1060                 dev->features |= NETIF_F_HW_VLAN_RX;
1061         }
1062
1063         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1064                 priv->extended_hash = 1;
1065                 priv->hash_width = 9;
1066
1067                 priv->hash_regs[0] = &regs->igaddr0;
1068                 priv->hash_regs[1] = &regs->igaddr1;
1069                 priv->hash_regs[2] = &regs->igaddr2;
1070                 priv->hash_regs[3] = &regs->igaddr3;
1071                 priv->hash_regs[4] = &regs->igaddr4;
1072                 priv->hash_regs[5] = &regs->igaddr5;
1073                 priv->hash_regs[6] = &regs->igaddr6;
1074                 priv->hash_regs[7] = &regs->igaddr7;
1075                 priv->hash_regs[8] = &regs->gaddr0;
1076                 priv->hash_regs[9] = &regs->gaddr1;
1077                 priv->hash_regs[10] = &regs->gaddr2;
1078                 priv->hash_regs[11] = &regs->gaddr3;
1079                 priv->hash_regs[12] = &regs->gaddr4;
1080                 priv->hash_regs[13] = &regs->gaddr5;
1081                 priv->hash_regs[14] = &regs->gaddr6;
1082                 priv->hash_regs[15] = &regs->gaddr7;
1083
1084         } else {
1085                 priv->extended_hash = 0;
1086                 priv->hash_width = 8;
1087
1088                 priv->hash_regs[0] = &regs->gaddr0;
1089                 priv->hash_regs[1] = &regs->gaddr1;
1090                 priv->hash_regs[2] = &regs->gaddr2;
1091                 priv->hash_regs[3] = &regs->gaddr3;
1092                 priv->hash_regs[4] = &regs->gaddr4;
1093                 priv->hash_regs[5] = &regs->gaddr5;
1094                 priv->hash_regs[6] = &regs->gaddr6;
1095                 priv->hash_regs[7] = &regs->gaddr7;
1096         }
1097
1098         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1099                 priv->padding = DEFAULT_PADDING;
1100         else
1101                 priv->padding = 0;
1102
1103         if (dev->features & NETIF_F_IP_CSUM ||
1104             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1105                 dev->needed_headroom = GMAC_FCB_LEN;
1106
1107         /* Program the isrg regs only if number of grps > 1 */
1108         if (priv->num_grps > 1) {
1109                 baddr = &regs->isrg0;
1110                 for (i = 0; i < priv->num_grps; i++) {
1111                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1112                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1113                         gfar_write(baddr, isrg);
1114                         baddr++;
1115                         isrg = 0x0;
1116                 }
1117         }
1118
1119         /* Need to reverse the bit maps as  bit_map's MSB is q0
1120          * but, for_each_set_bit parses from right to left, which
1121          * basically reverses the queue numbers
1122          */
1123         for (i = 0; i< priv->num_grps; i++) {
1124                 priv->gfargrp[i].tx_bit_map =
1125                         reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1126                 priv->gfargrp[i].rx_bit_map =
1127                         reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1128         }
1129
1130         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1131          * also assign queues to groups
1132          */
1133         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1134                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1135
1136                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1137                                  priv->num_rx_queues) {
1138                         priv->gfargrp[grp_idx].num_rx_queues++;
1139                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1140                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1141                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1142                 }
1143                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1144
1145                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1146                                  priv->num_tx_queues) {
1147                         priv->gfargrp[grp_idx].num_tx_queues++;
1148                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1149                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1150                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1151                 }
1152                 priv->gfargrp[grp_idx].rstat = rstat;
1153                 priv->gfargrp[grp_idx].tstat = tstat;
1154                 rstat = tstat =0;
1155         }
1156
1157         gfar_write(&regs->rqueue, rqueue);
1158         gfar_write(&regs->tqueue, tqueue);
1159
1160         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1161
1162         /* Initializing some of the rx/tx queue level parameters */
1163         for (i = 0; i < priv->num_tx_queues; i++) {
1164                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1165                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1166                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1167                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1168         }
1169
1170         for (i = 0; i < priv->num_rx_queues; i++) {
1171                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1172                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1173                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1174         }
1175
1176         /* always enable rx filer */
1177         priv->rx_filer_enable = 1;
1178         /* Enable most messages by default */
1179         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1180         /* use pritority h/w tx queue scheduling for single queue devices */
1181         if (priv->num_tx_queues == 1)
1182                 priv->prio_sched_en = 1;
1183
1184         /* Carrier starts down, phylib will bring it up */
1185         netif_carrier_off(dev);
1186
1187         err = register_netdev(dev);
1188
1189         if (err) {
1190                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1191                 goto register_fail;
1192         }
1193
1194         device_init_wakeup(&dev->dev,
1195                            priv->device_flags &
1196                            FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1197
1198         /* fill out IRQ number and name fields */
1199         for (i = 0; i < priv->num_grps; i++) {
1200                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1201                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1202                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1203                                 dev->name, "_g", '0' + i, "_tx");
1204                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1205                                 dev->name, "_g", '0' + i, "_rx");
1206                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1207                                 dev->name, "_g", '0' + i, "_er");
1208                 } else
1209                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1210         }
1211
1212         /* Initialize the filer table */
1213         gfar_init_filer_table(priv);
1214
1215         /* Create all the sysfs files */
1216         gfar_init_sysfs(dev);
1217
1218         /* Print out the device info */
1219         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1220
1221         /* Even more device info helps when determining which kernel
1222          * provided which set of benchmarks.
1223          */
1224         netdev_info(dev, "Running with NAPI enabled\n");
1225         for (i = 0; i < priv->num_rx_queues; i++)
1226                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1227                             i, priv->rx_queue[i]->rx_ring_size);
1228         for (i = 0; i < priv->num_tx_queues; i++)
1229                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1230                             i, priv->tx_queue[i]->tx_ring_size);
1231
1232         return 0;
1233
1234 register_fail:
1235         unmap_group_regs(priv);
1236         free_tx_pointers(priv);
1237         free_rx_pointers(priv);
1238         if (priv->phy_node)
1239                 of_node_put(priv->phy_node);
1240         if (priv->tbi_node)
1241                 of_node_put(priv->tbi_node);
1242         free_gfar_dev(priv);
1243         return err;
1244 }
1245
1246 static int gfar_remove(struct platform_device *ofdev)
1247 {
1248         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1249
1250         if (priv->phy_node)
1251                 of_node_put(priv->phy_node);
1252         if (priv->tbi_node)
1253                 of_node_put(priv->tbi_node);
1254
1255         dev_set_drvdata(&ofdev->dev, NULL);
1256
1257         unregister_netdev(priv->ndev);
1258         unmap_group_regs(priv);
1259         free_gfar_dev(priv);
1260
1261         return 0;
1262 }
1263
1264 #ifdef CONFIG_PM
1265
1266 static int gfar_suspend(struct device *dev)
1267 {
1268         struct gfar_private *priv = dev_get_drvdata(dev);
1269         struct net_device *ndev = priv->ndev;
1270         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1271         unsigned long flags;
1272         u32 tempval;
1273
1274         int magic_packet = priv->wol_en &&
1275                            (priv->device_flags &
1276                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1277
1278         netif_device_detach(ndev);
1279
1280         if (netif_running(ndev)) {
1281
1282                 local_irq_save(flags);
1283                 lock_tx_qs(priv);
1284                 lock_rx_qs(priv);
1285
1286                 gfar_halt_nodisable(ndev);
1287
1288                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1289                 tempval = gfar_read(&regs->maccfg1);
1290
1291                 tempval &= ~MACCFG1_TX_EN;
1292
1293                 if (!magic_packet)
1294                         tempval &= ~MACCFG1_RX_EN;
1295
1296                 gfar_write(&regs->maccfg1, tempval);
1297
1298                 unlock_rx_qs(priv);
1299                 unlock_tx_qs(priv);
1300                 local_irq_restore(flags);
1301
1302                 disable_napi(priv);
1303
1304                 if (magic_packet) {
1305                         /* Enable interrupt on Magic Packet */
1306                         gfar_write(&regs->imask, IMASK_MAG);
1307
1308                         /* Enable Magic Packet mode */
1309                         tempval = gfar_read(&regs->maccfg2);
1310                         tempval |= MACCFG2_MPEN;
1311                         gfar_write(&regs->maccfg2, tempval);
1312                 } else {
1313                         phy_stop(priv->phydev);
1314                 }
1315         }
1316
1317         return 0;
1318 }
1319
1320 static int gfar_resume(struct device *dev)
1321 {
1322         struct gfar_private *priv = dev_get_drvdata(dev);
1323         struct net_device *ndev = priv->ndev;
1324         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1325         unsigned long flags;
1326         u32 tempval;
1327         int magic_packet = priv->wol_en &&
1328                            (priv->device_flags &
1329                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1330
1331         if (!netif_running(ndev)) {
1332                 netif_device_attach(ndev);
1333                 return 0;
1334         }
1335
1336         if (!magic_packet && priv->phydev)
1337                 phy_start(priv->phydev);
1338
1339         /* Disable Magic Packet mode, in case something
1340          * else woke us up.
1341          */
1342         local_irq_save(flags);
1343         lock_tx_qs(priv);
1344         lock_rx_qs(priv);
1345
1346         tempval = gfar_read(&regs->maccfg2);
1347         tempval &= ~MACCFG2_MPEN;
1348         gfar_write(&regs->maccfg2, tempval);
1349
1350         gfar_start(ndev);
1351
1352         unlock_rx_qs(priv);
1353         unlock_tx_qs(priv);
1354         local_irq_restore(flags);
1355
1356         netif_device_attach(ndev);
1357
1358         enable_napi(priv);
1359
1360         return 0;
1361 }
1362
1363 static int gfar_restore(struct device *dev)
1364 {
1365         struct gfar_private *priv = dev_get_drvdata(dev);
1366         struct net_device *ndev = priv->ndev;
1367
1368         if (!netif_running(ndev)) {
1369                 netif_device_attach(ndev);
1370
1371                 return 0;
1372         }
1373
1374         if (gfar_init_bds(ndev)) {
1375                 free_skb_resources(priv);
1376                 return -ENOMEM;
1377         }
1378
1379         init_registers(ndev);
1380         gfar_set_mac_address(ndev);
1381         gfar_init_mac(ndev);
1382         gfar_start(ndev);
1383
1384         priv->oldlink = 0;
1385         priv->oldspeed = 0;
1386         priv->oldduplex = -1;
1387
1388         if (priv->phydev)
1389                 phy_start(priv->phydev);
1390
1391         netif_device_attach(ndev);
1392         enable_napi(priv);
1393
1394         return 0;
1395 }
1396
1397 static struct dev_pm_ops gfar_pm_ops = {
1398         .suspend = gfar_suspend,
1399         .resume = gfar_resume,
1400         .freeze = gfar_suspend,
1401         .thaw = gfar_resume,
1402         .restore = gfar_restore,
1403 };
1404
1405 #define GFAR_PM_OPS (&gfar_pm_ops)
1406
1407 #else
1408
1409 #define GFAR_PM_OPS NULL
1410
1411 #endif
1412
1413 /* Reads the controller's registers to determine what interface
1414  * connects it to the PHY.
1415  */
1416 static phy_interface_t gfar_get_interface(struct net_device *dev)
1417 {
1418         struct gfar_private *priv = netdev_priv(dev);
1419         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1420         u32 ecntrl;
1421
1422         ecntrl = gfar_read(&regs->ecntrl);
1423
1424         if (ecntrl & ECNTRL_SGMII_MODE)
1425                 return PHY_INTERFACE_MODE_SGMII;
1426
1427         if (ecntrl & ECNTRL_TBI_MODE) {
1428                 if (ecntrl & ECNTRL_REDUCED_MODE)
1429                         return PHY_INTERFACE_MODE_RTBI;
1430                 else
1431                         return PHY_INTERFACE_MODE_TBI;
1432         }
1433
1434         if (ecntrl & ECNTRL_REDUCED_MODE) {
1435                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1436                         return PHY_INTERFACE_MODE_RMII;
1437                 }
1438                 else {
1439                         phy_interface_t interface = priv->interface;
1440
1441                         /* This isn't autodetected right now, so it must
1442                          * be set by the device tree or platform code.
1443                          */
1444                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1445                                 return PHY_INTERFACE_MODE_RGMII_ID;
1446
1447                         return PHY_INTERFACE_MODE_RGMII;
1448                 }
1449         }
1450
1451         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1452                 return PHY_INTERFACE_MODE_GMII;
1453
1454         return PHY_INTERFACE_MODE_MII;
1455 }
1456
1457
1458 /* Initializes driver's PHY state, and attaches to the PHY.
1459  * Returns 0 on success.
1460  */
1461 static int init_phy(struct net_device *dev)
1462 {
1463         struct gfar_private *priv = netdev_priv(dev);
1464         uint gigabit_support =
1465                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1466                 SUPPORTED_1000baseT_Full : 0;
1467         phy_interface_t interface;
1468
1469         priv->oldlink = 0;
1470         priv->oldspeed = 0;
1471         priv->oldduplex = -1;
1472
1473         interface = gfar_get_interface(dev);
1474
1475         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1476                                       interface);
1477         if (!priv->phydev)
1478                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1479                                                          interface);
1480         if (!priv->phydev) {
1481                 dev_err(&dev->dev, "could not attach to PHY\n");
1482                 return -ENODEV;
1483         }
1484
1485         if (interface == PHY_INTERFACE_MODE_SGMII)
1486                 gfar_configure_serdes(dev);
1487
1488         /* Remove any features not supported by the controller */
1489         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1490         priv->phydev->advertising = priv->phydev->supported;
1491
1492         return 0;
1493 }
1494
1495 /* Initialize TBI PHY interface for communicating with the
1496  * SERDES lynx PHY on the chip.  We communicate with this PHY
1497  * through the MDIO bus on each controller, treating it as a
1498  * "normal" PHY at the address found in the TBIPA register.  We assume
1499  * that the TBIPA register is valid.  Either the MDIO bus code will set
1500  * it to a value that doesn't conflict with other PHYs on the bus, or the
1501  * value doesn't matter, as there are no other PHYs on the bus.
1502  */
1503 static void gfar_configure_serdes(struct net_device *dev)
1504 {
1505         struct gfar_private *priv = netdev_priv(dev);
1506         struct phy_device *tbiphy;
1507
1508         if (!priv->tbi_node) {
1509                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1510                                     "device tree specify a tbi-handle\n");
1511                 return;
1512         }
1513
1514         tbiphy = of_phy_find_device(priv->tbi_node);
1515         if (!tbiphy) {
1516                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1517                 return;
1518         }
1519
1520         /* If the link is already up, we must already be ok, and don't need to
1521          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1522          * everything for us?  Resetting it takes the link down and requires
1523          * several seconds for it to come back.
1524          */
1525         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1526                 return;
1527
1528         /* Single clk mode, mii mode off(for serdes communication) */
1529         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1530
1531         phy_write(tbiphy, MII_ADVERTISE,
1532                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1533                   ADVERTISE_1000XPSE_ASYM);
1534
1535         phy_write(tbiphy, MII_BMCR,
1536                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1537                   BMCR_SPEED1000);
1538 }
1539
1540 static void init_registers(struct net_device *dev)
1541 {
1542         struct gfar_private *priv = netdev_priv(dev);
1543         struct gfar __iomem *regs = NULL;
1544         int i;
1545
1546         for (i = 0; i < priv->num_grps; i++) {
1547                 regs = priv->gfargrp[i].regs;
1548                 /* Clear IEVENT */
1549                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1550
1551                 /* Initialize IMASK */
1552                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1553         }
1554
1555         regs = priv->gfargrp[0].regs;
1556         /* Init hash registers to zero */
1557         gfar_write(&regs->igaddr0, 0);
1558         gfar_write(&regs->igaddr1, 0);
1559         gfar_write(&regs->igaddr2, 0);
1560         gfar_write(&regs->igaddr3, 0);
1561         gfar_write(&regs->igaddr4, 0);
1562         gfar_write(&regs->igaddr5, 0);
1563         gfar_write(&regs->igaddr6, 0);
1564         gfar_write(&regs->igaddr7, 0);
1565
1566         gfar_write(&regs->gaddr0, 0);
1567         gfar_write(&regs->gaddr1, 0);
1568         gfar_write(&regs->gaddr2, 0);
1569         gfar_write(&regs->gaddr3, 0);
1570         gfar_write(&regs->gaddr4, 0);
1571         gfar_write(&regs->gaddr5, 0);
1572         gfar_write(&regs->gaddr6, 0);
1573         gfar_write(&regs->gaddr7, 0);
1574
1575         /* Zero out the rmon mib registers if it has them */
1576         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1577                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1578
1579                 /* Mask off the CAM interrupts */
1580                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1581                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1582         }
1583
1584         /* Initialize the max receive buffer length */
1585         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1586
1587         /* Initialize the Minimum Frame Length Register */
1588         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1589 }
1590
1591 static int __gfar_is_rx_idle(struct gfar_private *priv)
1592 {
1593         u32 res;
1594
1595         /* Normaly TSEC should not hang on GRS commands, so we should
1596          * actually wait for IEVENT_GRSC flag.
1597          */
1598         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1599                 return 0;
1600
1601         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1602          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1603          * and the Rx can be safely reset.
1604          */
1605         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1606         res &= 0x7f807f80;
1607         if ((res & 0xffff) == (res >> 16))
1608                 return 1;
1609
1610         return 0;
1611 }
1612
1613 /* Halt the receive and transmit queues */
1614 static void gfar_halt_nodisable(struct net_device *dev)
1615 {
1616         struct gfar_private *priv = netdev_priv(dev);
1617         struct gfar __iomem *regs = NULL;
1618         u32 tempval;
1619         int i;
1620
1621         for (i = 0; i < priv->num_grps; i++) {
1622                 regs = priv->gfargrp[i].regs;
1623                 /* Mask all interrupts */
1624                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1625
1626                 /* Clear all interrupts */
1627                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1628         }
1629
1630         regs = priv->gfargrp[0].regs;
1631         /* Stop the DMA, and wait for it to stop */
1632         tempval = gfar_read(&regs->dmactrl);
1633         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1634             (DMACTRL_GRS | DMACTRL_GTS)) {
1635                 int ret;
1636
1637                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1638                 gfar_write(&regs->dmactrl, tempval);
1639
1640                 do {
1641                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1642                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1643                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1644                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1645                                 ret = __gfar_is_rx_idle(priv);
1646                 } while (!ret);
1647         }
1648 }
1649
1650 /* Halt the receive and transmit queues */
1651 void gfar_halt(struct net_device *dev)
1652 {
1653         struct gfar_private *priv = netdev_priv(dev);
1654         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1655         u32 tempval;
1656
1657         gfar_halt_nodisable(dev);
1658
1659         /* Disable Rx and Tx */
1660         tempval = gfar_read(&regs->maccfg1);
1661         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1662         gfar_write(&regs->maccfg1, tempval);
1663 }
1664
1665 static void free_grp_irqs(struct gfar_priv_grp *grp)
1666 {
1667         free_irq(gfar_irq(grp, TX)->irq, grp);
1668         free_irq(gfar_irq(grp, RX)->irq, grp);
1669         free_irq(gfar_irq(grp, ER)->irq, grp);
1670 }
1671
1672 void stop_gfar(struct net_device *dev)
1673 {
1674         struct gfar_private *priv = netdev_priv(dev);
1675         unsigned long flags;
1676         int i;
1677
1678         phy_stop(priv->phydev);
1679
1680
1681         /* Lock it down */
1682         local_irq_save(flags);
1683         lock_tx_qs(priv);
1684         lock_rx_qs(priv);
1685
1686         gfar_halt(dev);
1687
1688         unlock_rx_qs(priv);
1689         unlock_tx_qs(priv);
1690         local_irq_restore(flags);
1691
1692         /* Free the IRQs */
1693         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1694                 for (i = 0; i < priv->num_grps; i++)
1695                         free_grp_irqs(&priv->gfargrp[i]);
1696         } else {
1697                 for (i = 0; i < priv->num_grps; i++)
1698                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1699                                  &priv->gfargrp[i]);
1700         }
1701
1702         free_skb_resources(priv);
1703 }
1704
1705 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1706 {
1707         struct txbd8 *txbdp;
1708         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1709         int i, j;
1710
1711         txbdp = tx_queue->tx_bd_base;
1712
1713         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1714                 if (!tx_queue->tx_skbuff[i])
1715                         continue;
1716
1717                 dma_unmap_single(priv->dev, txbdp->bufPtr,
1718                                  txbdp->length, DMA_TO_DEVICE);
1719                 txbdp->lstatus = 0;
1720                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1721                      j++) {
1722                         txbdp++;
1723                         dma_unmap_page(priv->dev, txbdp->bufPtr,
1724                                        txbdp->length, DMA_TO_DEVICE);
1725                 }
1726                 txbdp++;
1727                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1728                 tx_queue->tx_skbuff[i] = NULL;
1729         }
1730         kfree(tx_queue->tx_skbuff);
1731         tx_queue->tx_skbuff = NULL;
1732 }
1733
1734 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1735 {
1736         struct rxbd8 *rxbdp;
1737         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1738         int i;
1739
1740         rxbdp = rx_queue->rx_bd_base;
1741
1742         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1743                 if (rx_queue->rx_skbuff[i]) {
1744                         dma_unmap_single(priv->dev, rxbdp->bufPtr,
1745                                          priv->rx_buffer_size,
1746                                          DMA_FROM_DEVICE);
1747                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1748                         rx_queue->rx_skbuff[i] = NULL;
1749                 }
1750                 rxbdp->lstatus = 0;
1751                 rxbdp->bufPtr = 0;
1752                 rxbdp++;
1753         }
1754         kfree(rx_queue->rx_skbuff);
1755         rx_queue->rx_skbuff = NULL;
1756 }
1757
1758 /* If there are any tx skbs or rx skbs still around, free them.
1759  * Then free tx_skbuff and rx_skbuff
1760  */
1761 static void free_skb_resources(struct gfar_private *priv)
1762 {
1763         struct gfar_priv_tx_q *tx_queue = NULL;
1764         struct gfar_priv_rx_q *rx_queue = NULL;
1765         int i;
1766
1767         /* Go through all the buffer descriptors and free their data buffers */
1768         for (i = 0; i < priv->num_tx_queues; i++) {
1769                 struct netdev_queue *txq;
1770
1771                 tx_queue = priv->tx_queue[i];
1772                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1773                 if (tx_queue->tx_skbuff)
1774                         free_skb_tx_queue(tx_queue);
1775                 netdev_tx_reset_queue(txq);
1776         }
1777
1778         for (i = 0; i < priv->num_rx_queues; i++) {
1779                 rx_queue = priv->rx_queue[i];
1780                 if (rx_queue->rx_skbuff)
1781                         free_skb_rx_queue(rx_queue);
1782         }
1783
1784         dma_free_coherent(priv->dev,
1785                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1786                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1787                           priv->tx_queue[0]->tx_bd_base,
1788                           priv->tx_queue[0]->tx_bd_dma_base);
1789 }
1790
1791 void gfar_start(struct net_device *dev)
1792 {
1793         struct gfar_private *priv = netdev_priv(dev);
1794         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1795         u32 tempval;
1796         int i = 0;
1797
1798         /* Enable Rx and Tx in MACCFG1 */
1799         tempval = gfar_read(&regs->maccfg1);
1800         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1801         gfar_write(&regs->maccfg1, tempval);
1802
1803         /* Initialize DMACTRL to have WWR and WOP */
1804         tempval = gfar_read(&regs->dmactrl);
1805         tempval |= DMACTRL_INIT_SETTINGS;
1806         gfar_write(&regs->dmactrl, tempval);
1807
1808         /* Make sure we aren't stopped */
1809         tempval = gfar_read(&regs->dmactrl);
1810         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1811         gfar_write(&regs->dmactrl, tempval);
1812
1813         for (i = 0; i < priv->num_grps; i++) {
1814                 regs = priv->gfargrp[i].regs;
1815                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1816                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1817                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1818                 /* Unmask the interrupts we look for */
1819                 gfar_write(&regs->imask, IMASK_DEFAULT);
1820         }
1821
1822         dev->trans_start = jiffies; /* prevent tx timeout */
1823 }
1824
1825 void gfar_configure_coalescing(struct gfar_private *priv,
1826                                unsigned long tx_mask, unsigned long rx_mask)
1827 {
1828         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1829         u32 __iomem *baddr;
1830         int i = 0;
1831
1832         /* Backward compatible case ---- even if we enable
1833          * multiple queues, there's only single reg to program
1834          */
1835         gfar_write(&regs->txic, 0);
1836         if (likely(priv->tx_queue[0]->txcoalescing))
1837                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1838
1839         gfar_write(&regs->rxic, 0);
1840         if (unlikely(priv->rx_queue[0]->rxcoalescing))
1841                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1842
1843         if (priv->mode == MQ_MG_MODE) {
1844                 baddr = &regs->txic0;
1845                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1846                         gfar_write(baddr + i, 0);
1847                         if (likely(priv->tx_queue[i]->txcoalescing))
1848                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1849                 }
1850
1851                 baddr = &regs->rxic0;
1852                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1853                         gfar_write(baddr + i, 0);
1854                         if (likely(priv->rx_queue[i]->rxcoalescing))
1855                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1856                 }
1857         }
1858 }
1859
1860 static int register_grp_irqs(struct gfar_priv_grp *grp)
1861 {
1862         struct gfar_private *priv = grp->priv;
1863         struct net_device *dev = priv->ndev;
1864         int err;
1865
1866         /* If the device has multiple interrupts, register for
1867          * them.  Otherwise, only register for the one
1868          */
1869         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1870                 /* Install our interrupt handlers for Error,
1871                  * Transmit, and Receive
1872                  */
1873                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1874                                   gfar_irq(grp, ER)->name, grp);
1875                 if (err < 0) {
1876                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1877                                   gfar_irq(grp, ER)->irq);
1878
1879                         goto err_irq_fail;
1880                 }
1881                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1882                                   gfar_irq(grp, TX)->name, grp);
1883                 if (err < 0) {
1884                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1885                                   gfar_irq(grp, TX)->irq);
1886                         goto tx_irq_fail;
1887                 }
1888                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1889                                   gfar_irq(grp, RX)->name, grp);
1890                 if (err < 0) {
1891                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1892                                   gfar_irq(grp, RX)->irq);
1893                         goto rx_irq_fail;
1894                 }
1895         } else {
1896                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1897                                   gfar_irq(grp, TX)->name, grp);
1898                 if (err < 0) {
1899                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1900                                   gfar_irq(grp, TX)->irq);
1901                         goto err_irq_fail;
1902                 }
1903         }
1904
1905         return 0;
1906
1907 rx_irq_fail:
1908         free_irq(gfar_irq(grp, TX)->irq, grp);
1909 tx_irq_fail:
1910         free_irq(gfar_irq(grp, ER)->irq, grp);
1911 err_irq_fail:
1912         return err;
1913
1914 }
1915
1916 /* Bring the controller up and running */
1917 int startup_gfar(struct net_device *ndev)
1918 {
1919         struct gfar_private *priv = netdev_priv(ndev);
1920         struct gfar __iomem *regs = NULL;
1921         int err, i, j;
1922
1923         for (i = 0; i < priv->num_grps; i++) {
1924                 regs= priv->gfargrp[i].regs;
1925                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1926         }
1927
1928         regs= priv->gfargrp[0].regs;
1929         err = gfar_alloc_skb_resources(ndev);
1930         if (err)
1931                 return err;
1932
1933         gfar_init_mac(ndev);
1934
1935         for (i = 0; i < priv->num_grps; i++) {
1936                 err = register_grp_irqs(&priv->gfargrp[i]);
1937                 if (err) {
1938                         for (j = 0; j < i; j++)
1939                                 free_grp_irqs(&priv->gfargrp[j]);
1940                         goto irq_fail;
1941                 }
1942         }
1943
1944         /* Start the controller */
1945         gfar_start(ndev);
1946
1947         phy_start(priv->phydev);
1948
1949         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1950
1951         return 0;
1952
1953 irq_fail:
1954         free_skb_resources(priv);
1955         return err;
1956 }
1957
1958 /* Called when something needs to use the ethernet device
1959  * Returns 0 for success.
1960  */
1961 static int gfar_enet_open(struct net_device *dev)
1962 {
1963         struct gfar_private *priv = netdev_priv(dev);
1964         int err;
1965
1966         enable_napi(priv);
1967
1968         /* Initialize a bunch of registers */
1969         init_registers(dev);
1970
1971         gfar_set_mac_address(dev);
1972
1973         err = init_phy(dev);
1974
1975         if (err) {
1976                 disable_napi(priv);
1977                 return err;
1978         }
1979
1980         err = startup_gfar(dev);
1981         if (err) {
1982                 disable_napi(priv);
1983                 return err;
1984         }
1985
1986         netif_tx_start_all_queues(dev);
1987
1988         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1989
1990         return err;
1991 }
1992
1993 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1994 {
1995         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1996
1997         memset(fcb, 0, GMAC_FCB_LEN);
1998
1999         return fcb;
2000 }
2001
2002 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2003                                     int fcb_length)
2004 {
2005         /* If we're here, it's a IP packet with a TCP or UDP
2006          * payload.  We set it to checksum, using a pseudo-header
2007          * we provide
2008          */
2009         u8 flags = TXFCB_DEFAULT;
2010
2011         /* Tell the controller what the protocol is
2012          * And provide the already calculated phcs
2013          */
2014         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2015                 flags |= TXFCB_UDP;
2016                 fcb->phcs = udp_hdr(skb)->check;
2017         } else
2018                 fcb->phcs = tcp_hdr(skb)->check;
2019
2020         /* l3os is the distance between the start of the
2021          * frame (skb->data) and the start of the IP hdr.
2022          * l4os is the distance between the start of the
2023          * l3 hdr and the l4 hdr
2024          */
2025         fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2026         fcb->l4os = skb_network_header_len(skb);
2027
2028         fcb->flags = flags;
2029 }
2030
2031 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2032 {
2033         fcb->flags |= TXFCB_VLN;
2034         fcb->vlctl = vlan_tx_tag_get(skb);
2035 }
2036
2037 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2038                                       struct txbd8 *base, int ring_size)
2039 {
2040         struct txbd8 *new_bd = bdp + stride;
2041
2042         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2043 }
2044
2045 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2046                                       int ring_size)
2047 {
2048         return skip_txbd(bdp, 1, base, ring_size);
2049 }
2050
2051 /* This is called by the kernel when a frame is ready for transmission.
2052  * It is pointed to by the dev->hard_start_xmit function pointer
2053  */
2054 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2055 {
2056         struct gfar_private *priv = netdev_priv(dev);
2057         struct gfar_priv_tx_q *tx_queue = NULL;
2058         struct netdev_queue *txq;
2059         struct gfar __iomem *regs = NULL;
2060         struct txfcb *fcb = NULL;
2061         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2062         u32 lstatus;
2063         int i, rq = 0, do_tstamp = 0;
2064         u32 bufaddr;
2065         unsigned long flags;
2066         unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2067
2068         /* TOE=1 frames larger than 2500 bytes may see excess delays
2069          * before start of transmission.
2070          */
2071         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2072                      skb->ip_summed == CHECKSUM_PARTIAL &&
2073                      skb->len > 2500)) {
2074                 int ret;
2075
2076                 ret = skb_checksum_help(skb);
2077                 if (ret)
2078                         return ret;
2079         }
2080
2081         rq = skb->queue_mapping;
2082         tx_queue = priv->tx_queue[rq];
2083         txq = netdev_get_tx_queue(dev, rq);
2084         base = tx_queue->tx_bd_base;
2085         regs = tx_queue->grp->regs;
2086
2087         /* check if time stamp should be generated */
2088         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2089                      priv->hwts_tx_en)) {
2090                 do_tstamp = 1;
2091                 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2092         }
2093
2094         /* make space for additional header when fcb is needed */
2095         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2096              vlan_tx_tag_present(skb) ||
2097              unlikely(do_tstamp)) &&
2098             (skb_headroom(skb) < fcb_length)) {
2099                 struct sk_buff *skb_new;
2100
2101                 skb_new = skb_realloc_headroom(skb, fcb_length);
2102                 if (!skb_new) {
2103                         dev->stats.tx_errors++;
2104                         kfree_skb(skb);
2105                         return NETDEV_TX_OK;
2106                 }
2107
2108                 if (skb->sk)
2109                         skb_set_owner_w(skb_new, skb->sk);
2110                 consume_skb(skb);
2111                 skb = skb_new;
2112         }
2113
2114         /* total number of fragments in the SKB */
2115         nr_frags = skb_shinfo(skb)->nr_frags;
2116
2117         /* calculate the required number of TxBDs for this skb */
2118         if (unlikely(do_tstamp))
2119                 nr_txbds = nr_frags + 2;
2120         else
2121                 nr_txbds = nr_frags + 1;
2122
2123         /* check if there is space to queue this packet */
2124         if (nr_txbds > tx_queue->num_txbdfree) {
2125                 /* no space, stop the queue */
2126                 netif_tx_stop_queue(txq);
2127                 dev->stats.tx_fifo_errors++;
2128                 return NETDEV_TX_BUSY;
2129         }
2130
2131         /* Update transmit stats */
2132         tx_queue->stats.tx_bytes += skb->len;
2133         tx_queue->stats.tx_packets++;
2134
2135         txbdp = txbdp_start = tx_queue->cur_tx;
2136         lstatus = txbdp->lstatus;
2137
2138         /* Time stamp insertion requires one additional TxBD */
2139         if (unlikely(do_tstamp))
2140                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2141                                                  tx_queue->tx_ring_size);
2142
2143         if (nr_frags == 0) {
2144                 if (unlikely(do_tstamp))
2145                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2146                                                           TXBD_INTERRUPT);
2147                 else
2148                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2149         } else {
2150                 /* Place the fragment addresses and lengths into the TxBDs */
2151                 for (i = 0; i < nr_frags; i++) {
2152                         /* Point at the next BD, wrapping as needed */
2153                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2154
2155                         length = skb_shinfo(skb)->frags[i].size;
2156
2157                         lstatus = txbdp->lstatus | length |
2158                                   BD_LFLAG(TXBD_READY);
2159
2160                         /* Handle the last BD specially */
2161                         if (i == nr_frags - 1)
2162                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2163
2164                         bufaddr = skb_frag_dma_map(priv->dev,
2165                                                    &skb_shinfo(skb)->frags[i],
2166                                                    0,
2167                                                    length,
2168                                                    DMA_TO_DEVICE);
2169
2170                         /* set the TxBD length and buffer pointer */
2171                         txbdp->bufPtr = bufaddr;
2172                         txbdp->lstatus = lstatus;
2173                 }
2174
2175                 lstatus = txbdp_start->lstatus;
2176         }
2177
2178         /* Add TxPAL between FCB and frame if required */
2179         if (unlikely(do_tstamp)) {
2180                 skb_push(skb, GMAC_TXPAL_LEN);
2181                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2182         }
2183
2184         /* Set up checksumming */
2185         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2186                 fcb = gfar_add_fcb(skb);
2187                 /* as specified by errata */
2188                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2189                              ((unsigned long)fcb % 0x20) > 0x18)) {
2190                         __skb_pull(skb, GMAC_FCB_LEN);
2191                         skb_checksum_help(skb);
2192                 } else {
2193                         lstatus |= BD_LFLAG(TXBD_TOE);
2194                         gfar_tx_checksum(skb, fcb, fcb_length);
2195                 }
2196         }
2197
2198         if (vlan_tx_tag_present(skb)) {
2199                 if (unlikely(NULL == fcb)) {
2200                         fcb = gfar_add_fcb(skb);
2201                         lstatus |= BD_LFLAG(TXBD_TOE);
2202                 }
2203
2204                 gfar_tx_vlan(skb, fcb);
2205         }
2206
2207         /* Setup tx hardware time stamping if requested */
2208         if (unlikely(do_tstamp)) {
2209                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2210                 if (fcb == NULL)
2211                         fcb = gfar_add_fcb(skb);
2212                 fcb->ptp = 1;
2213                 lstatus |= BD_LFLAG(TXBD_TOE);
2214         }
2215
2216         txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
2217                                              skb_headlen(skb), DMA_TO_DEVICE);
2218
2219         /* If time stamping is requested one additional TxBD must be set up. The
2220          * first TxBD points to the FCB and must have a data length of
2221          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2222          * the full frame length.
2223          */
2224         if (unlikely(do_tstamp)) {
2225                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2226                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2227                                          (skb_headlen(skb) - fcb_length);
2228                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2229         } else {
2230                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2231         }
2232
2233         netdev_tx_sent_queue(txq, skb->len);
2234
2235         /* We can work in parallel with gfar_clean_tx_ring(), except
2236          * when modifying num_txbdfree. Note that we didn't grab the lock
2237          * when we were reading the num_txbdfree and checking for available
2238          * space, that's because outside of this function it can only grow,
2239          * and once we've got needed space, it cannot suddenly disappear.
2240          *
2241          * The lock also protects us from gfar_error(), which can modify
2242          * regs->tstat and thus retrigger the transfers, which is why we
2243          * also must grab the lock before setting ready bit for the first
2244          * to be transmitted BD.
2245          */
2246         spin_lock_irqsave(&tx_queue->txlock, flags);
2247
2248         /* The powerpc-specific eieio() is used, as wmb() has too strong
2249          * semantics (it requires synchronization between cacheable and
2250          * uncacheable mappings, which eieio doesn't provide and which we
2251          * don't need), thus requiring a more expensive sync instruction.  At
2252          * some point, the set of architecture-independent barrier functions
2253          * should be expanded to include weaker barriers.
2254          */
2255         eieio();
2256
2257         txbdp_start->lstatus = lstatus;
2258
2259         eieio(); /* force lstatus write before tx_skbuff */
2260
2261         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2262
2263         /* Update the current skb pointer to the next entry we will use
2264          * (wrapping if necessary)
2265          */
2266         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2267                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2268
2269         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2270
2271         /* reduce TxBD free count */
2272         tx_queue->num_txbdfree -= (nr_txbds);
2273
2274         /* If the next BD still needs to be cleaned up, then the bds
2275          * are full.  We need to tell the kernel to stop sending us stuff.
2276          */
2277         if (!tx_queue->num_txbdfree) {
2278                 netif_tx_stop_queue(txq);
2279
2280                 dev->stats.tx_fifo_errors++;
2281         }
2282
2283         /* Tell the DMA to go go go */
2284         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2285
2286         /* Unlock priv */
2287         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2288
2289         return NETDEV_TX_OK;
2290 }
2291
2292 /* Stops the kernel queue, and halts the controller */
2293 static int gfar_close(struct net_device *dev)
2294 {
2295         struct gfar_private *priv = netdev_priv(dev);
2296
2297         disable_napi(priv);
2298
2299         cancel_work_sync(&priv->reset_task);
2300         stop_gfar(dev);
2301
2302         /* Disconnect from the PHY */
2303         phy_disconnect(priv->phydev);
2304         priv->phydev = NULL;
2305
2306         netif_tx_stop_all_queues(dev);
2307
2308         return 0;
2309 }
2310
2311 /* Changes the mac address if the controller is not running. */
2312 static int gfar_set_mac_address(struct net_device *dev)
2313 {
2314         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2315
2316         return 0;
2317 }
2318
2319 /* Check if rx parser should be activated */
2320 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2321 {
2322         struct gfar __iomem *regs;
2323         u32 tempval;
2324
2325         regs = priv->gfargrp[0].regs;
2326
2327         tempval = gfar_read(&regs->rctrl);
2328         /* If parse is no longer required, then disable parser */
2329         if (tempval & RCTRL_REQ_PARSER)
2330                 tempval |= RCTRL_PRSDEP_INIT;
2331         else
2332                 tempval &= ~RCTRL_PRSDEP_INIT;
2333         gfar_write(&regs->rctrl, tempval);
2334 }
2335
2336 /* Enables and disables VLAN insertion/extraction */
2337 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2338 {
2339         struct gfar_private *priv = netdev_priv(dev);
2340         struct gfar __iomem *regs = NULL;
2341         unsigned long flags;
2342         u32 tempval;
2343
2344         regs = priv->gfargrp[0].regs;
2345         local_irq_save(flags);
2346         lock_rx_qs(priv);
2347
2348         if (features & NETIF_F_HW_VLAN_TX) {
2349                 /* Enable VLAN tag insertion */
2350                 tempval = gfar_read(&regs->tctrl);
2351                 tempval |= TCTRL_VLINS;
2352                 gfar_write(&regs->tctrl, tempval);
2353         } else {
2354                 /* Disable VLAN tag insertion */
2355                 tempval = gfar_read(&regs->tctrl);
2356                 tempval &= ~TCTRL_VLINS;
2357                 gfar_write(&regs->tctrl, tempval);
2358         }
2359
2360         if (features & NETIF_F_HW_VLAN_RX) {
2361                 /* Enable VLAN tag extraction */
2362                 tempval = gfar_read(&regs->rctrl);
2363                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2364                 gfar_write(&regs->rctrl, tempval);
2365         } else {
2366                 /* Disable VLAN tag extraction */
2367                 tempval = gfar_read(&regs->rctrl);
2368                 tempval &= ~RCTRL_VLEX;
2369                 gfar_write(&regs->rctrl, tempval);
2370
2371                 gfar_check_rx_parser_mode(priv);
2372         }
2373
2374         gfar_change_mtu(dev, dev->mtu);
2375
2376         unlock_rx_qs(priv);
2377         local_irq_restore(flags);
2378 }
2379
2380 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2381 {
2382         int tempsize, tempval;
2383         struct gfar_private *priv = netdev_priv(dev);
2384         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2385         int oldsize = priv->rx_buffer_size;
2386         int frame_size = new_mtu + ETH_HLEN;
2387
2388         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2389                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2390                 return -EINVAL;
2391         }
2392
2393         if (gfar_uses_fcb(priv))
2394                 frame_size += GMAC_FCB_LEN;
2395
2396         frame_size += priv->padding;
2397
2398         tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2399                    INCREMENTAL_BUFFER_SIZE;
2400
2401         /* Only stop and start the controller if it isn't already
2402          * stopped, and we changed something
2403          */
2404         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2405                 stop_gfar(dev);
2406
2407         priv->rx_buffer_size = tempsize;
2408
2409         dev->mtu = new_mtu;
2410
2411         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2412         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2413
2414         /* If the mtu is larger than the max size for standard
2415          * ethernet frames (ie, a jumbo frame), then set maccfg2
2416          * to allow huge frames, and to check the length
2417          */
2418         tempval = gfar_read(&regs->maccfg2);
2419
2420         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2421             gfar_has_errata(priv, GFAR_ERRATA_74))
2422                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2423         else
2424                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2425
2426         gfar_write(&regs->maccfg2, tempval);
2427
2428         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2429                 startup_gfar(dev);
2430
2431         return 0;
2432 }
2433
2434 /* gfar_reset_task gets scheduled when a packet has not been
2435  * transmitted after a set amount of time.
2436  * For now, assume that clearing out all the structures, and
2437  * starting over will fix the problem.
2438  */
2439 static void gfar_reset_task(struct work_struct *work)
2440 {
2441         struct gfar_private *priv = container_of(work, struct gfar_private,
2442                                                  reset_task);
2443         struct net_device *dev = priv->ndev;
2444
2445         if (dev->flags & IFF_UP) {
2446                 netif_tx_stop_all_queues(dev);
2447                 stop_gfar(dev);
2448                 startup_gfar(dev);
2449                 netif_tx_start_all_queues(dev);
2450         }
2451
2452         netif_tx_schedule_all(dev);
2453 }
2454
2455 static void gfar_timeout(struct net_device *dev)
2456 {
2457         struct gfar_private *priv = netdev_priv(dev);
2458
2459         dev->stats.tx_errors++;
2460         schedule_work(&priv->reset_task);
2461 }
2462
2463 static void gfar_align_skb(struct sk_buff *skb)
2464 {
2465         /* We need the data buffer to be aligned properly.  We will reserve
2466          * as many bytes as needed to align the data properly
2467          */
2468         skb_reserve(skb, RXBUF_ALIGNMENT -
2469                     (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2470 }
2471
2472 /* Interrupt Handler for Transmit complete */
2473 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2474 {
2475         struct net_device *dev = tx_queue->dev;
2476         struct netdev_queue *txq;
2477         struct gfar_private *priv = netdev_priv(dev);
2478         struct gfar_priv_rx_q *rx_queue = NULL;
2479         struct txbd8 *bdp, *next = NULL;
2480         struct txbd8 *lbdp = NULL;
2481         struct txbd8 *base = tx_queue->tx_bd_base;
2482         struct sk_buff *skb;
2483         int skb_dirtytx;
2484         int tx_ring_size = tx_queue->tx_ring_size;
2485         int frags = 0, nr_txbds = 0;
2486         int i;
2487         int howmany = 0;
2488         int tqi = tx_queue->qindex;
2489         unsigned int bytes_sent = 0;
2490         u32 lstatus;
2491         size_t buflen;
2492
2493         rx_queue = priv->rx_queue[tqi];
2494         txq = netdev_get_tx_queue(dev, tqi);
2495         bdp = tx_queue->dirty_tx;
2496         skb_dirtytx = tx_queue->skb_dirtytx;
2497
2498         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2499                 unsigned long flags;
2500
2501                 frags = skb_shinfo(skb)->nr_frags;
2502
2503                 /* When time stamping, one additional TxBD must be freed.
2504                  * Also, we need to dma_unmap_single() the TxPAL.
2505                  */
2506                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2507                         nr_txbds = frags + 2;
2508                 else
2509                         nr_txbds = frags + 1;
2510
2511                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2512
2513                 lstatus = lbdp->lstatus;
2514
2515                 /* Only clean completed frames */
2516                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2517                     (lstatus & BD_LENGTH_MASK))
2518                         break;
2519
2520                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2521                         next = next_txbd(bdp, base, tx_ring_size);
2522                         buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2523                 } else
2524                         buflen = bdp->length;
2525
2526                 dma_unmap_single(priv->dev, bdp->bufPtr,
2527                                  buflen, DMA_TO_DEVICE);
2528
2529                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2530                         struct skb_shared_hwtstamps shhwtstamps;
2531                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2532
2533                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2534                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2535                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2536                         skb_tstamp_tx(skb, &shhwtstamps);
2537                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2538                         bdp = next;
2539                 }
2540
2541                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2542                 bdp = next_txbd(bdp, base, tx_ring_size);
2543
2544                 for (i = 0; i < frags; i++) {
2545                         dma_unmap_page(priv->dev, bdp->bufPtr,
2546                                        bdp->length, DMA_TO_DEVICE);
2547                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2548                         bdp = next_txbd(bdp, base, tx_ring_size);
2549                 }
2550
2551                 bytes_sent += skb->len;
2552
2553                 dev_kfree_skb_any(skb);
2554
2555                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2556
2557                 skb_dirtytx = (skb_dirtytx + 1) &
2558                               TX_RING_MOD_MASK(tx_ring_size);
2559
2560                 howmany++;
2561                 spin_lock_irqsave(&tx_queue->txlock, flags);
2562                 tx_queue->num_txbdfree += nr_txbds;
2563                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2564         }
2565
2566         /* If we freed a buffer, we can restart transmission, if necessary */
2567         if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2568                 netif_wake_subqueue(dev, tqi);
2569
2570         /* Update dirty indicators */
2571         tx_queue->skb_dirtytx = skb_dirtytx;
2572         tx_queue->dirty_tx = bdp;
2573
2574         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2575
2576         return howmany;
2577 }
2578
2579 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2580 {
2581         unsigned long flags;
2582
2583         spin_lock_irqsave(&gfargrp->grplock, flags);
2584         if (napi_schedule_prep(&gfargrp->napi)) {
2585                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2586                 __napi_schedule(&gfargrp->napi);
2587         } else {
2588                 /* Clear IEVENT, so interrupts aren't called again
2589                  * because of the packets that have already arrived.
2590                  */
2591                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2592         }
2593         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2594
2595 }
2596
2597 /* Interrupt Handler for Transmit complete */
2598 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2599 {
2600         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2601         return IRQ_HANDLED;
2602 }
2603
2604 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2605                            struct sk_buff *skb)
2606 {
2607         struct net_device *dev = rx_queue->dev;
2608         struct gfar_private *priv = netdev_priv(dev);
2609         dma_addr_t buf;
2610
2611         buf = dma_map_single(priv->dev, skb->data,
2612                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2613         gfar_init_rxbdp(rx_queue, bdp, buf);
2614 }
2615
2616 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2617 {
2618         struct gfar_private *priv = netdev_priv(dev);
2619         struct sk_buff *skb;
2620
2621         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2622         if (!skb)
2623                 return NULL;
2624
2625         gfar_align_skb(skb);
2626
2627         return skb;
2628 }
2629
2630 struct sk_buff *gfar_new_skb(struct net_device *dev)
2631 {
2632         return gfar_alloc_skb(dev);
2633 }
2634
2635 static inline void count_errors(unsigned short status, struct net_device *dev)
2636 {
2637         struct gfar_private *priv = netdev_priv(dev);
2638         struct net_device_stats *stats = &dev->stats;
2639         struct gfar_extra_stats *estats = &priv->extra_stats;
2640
2641         /* If the packet was truncated, none of the other errors matter */
2642         if (status & RXBD_TRUNCATED) {
2643                 stats->rx_length_errors++;
2644
2645                 atomic64_inc(&estats->rx_trunc);
2646
2647                 return;
2648         }
2649         /* Count the errors, if there were any */
2650         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2651                 stats->rx_length_errors++;
2652
2653                 if (status & RXBD_LARGE)
2654                         atomic64_inc(&estats->rx_large);
2655                 else
2656                         atomic64_inc(&estats->rx_short);
2657         }
2658         if (status & RXBD_NONOCTET) {
2659                 stats->rx_frame_errors++;
2660                 atomic64_inc(&estats->rx_nonoctet);
2661         }
2662         if (status & RXBD_CRCERR) {
2663                 atomic64_inc(&estats->rx_crcerr);
2664                 stats->rx_crc_errors++;
2665         }
2666         if (status & RXBD_OVERRUN) {
2667                 atomic64_inc(&estats->rx_overrun);
2668                 stats->rx_crc_errors++;
2669         }
2670 }
2671
2672 irqreturn_t gfar_receive(int irq, void *grp_id)
2673 {
2674         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2675         return IRQ_HANDLED;
2676 }
2677
2678 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2679 {
2680         /* If valid headers were found, and valid sums
2681          * were verified, then we tell the kernel that no
2682          * checksumming is necessary.  Otherwise, it is [FIXME]
2683          */
2684         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2685                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2686         else
2687                 skb_checksum_none_assert(skb);
2688 }
2689
2690
2691 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2692 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2693                                int amount_pull, struct napi_struct *napi)
2694 {
2695         struct gfar_private *priv = netdev_priv(dev);
2696         struct rxfcb *fcb = NULL;
2697
2698         gro_result_t ret;
2699
2700         /* fcb is at the beginning if exists */
2701         fcb = (struct rxfcb *)skb->data;
2702
2703         /* Remove the FCB from the skb
2704          * Remove the padded bytes, if there are any
2705          */
2706         if (amount_pull) {
2707                 skb_record_rx_queue(skb, fcb->rq);
2708                 skb_pull(skb, amount_pull);
2709         }
2710
2711         /* Get receive timestamp from the skb */
2712         if (priv->hwts_rx_en) {
2713                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2714                 u64 *ns = (u64 *) skb->data;
2715
2716                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2717                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2718         }
2719
2720         if (priv->padding)
2721                 skb_pull(skb, priv->padding);
2722
2723         if (dev->features & NETIF_F_RXCSUM)
2724                 gfar_rx_checksum(skb, fcb);
2725
2726         /* Tell the skb what kind of packet this is */
2727         skb->protocol = eth_type_trans(skb, dev);
2728
2729         /* There's need to check for NETIF_F_HW_VLAN_RX here.
2730          * Even if vlan rx accel is disabled, on some chips
2731          * RXFCB_VLN is pseudo randomly set.
2732          */
2733         if (dev->features & NETIF_F_HW_VLAN_RX &&
2734             fcb->flags & RXFCB_VLN)
2735                 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2736
2737         /* Send the packet up the stack */
2738         ret = napi_gro_receive(napi, skb);
2739
2740         if (unlikely(GRO_DROP == ret))
2741                 atomic64_inc(&priv->extra_stats.kernel_dropped);
2742 }
2743
2744 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2745  * until the budget/quota has been reached. Returns the number
2746  * of frames handled
2747  */
2748 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2749 {
2750         struct net_device *dev = rx_queue->dev;
2751         struct rxbd8 *bdp, *base;
2752         struct sk_buff *skb;
2753         int pkt_len;
2754         int amount_pull;
2755         int howmany = 0;
2756         struct gfar_private *priv = netdev_priv(dev);
2757
2758         /* Get the first full descriptor */
2759         bdp = rx_queue->cur_rx;
2760         base = rx_queue->rx_bd_base;
2761
2762         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2763
2764         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2765                 struct sk_buff *newskb;
2766
2767                 rmb();
2768
2769                 /* Add another skb for the future */
2770                 newskb = gfar_new_skb(dev);
2771
2772                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2773
2774                 dma_unmap_single(priv->dev, bdp->bufPtr,
2775                                  priv->rx_buffer_size, DMA_FROM_DEVICE);
2776
2777                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2778                              bdp->length > priv->rx_buffer_size))
2779                         bdp->status = RXBD_LARGE;
2780
2781                 /* We drop the frame if we failed to allocate a new buffer */
2782                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2783                              bdp->status & RXBD_ERR)) {
2784                         count_errors(bdp->status, dev);
2785
2786                         if (unlikely(!newskb))
2787                                 newskb = skb;
2788                         else if (skb)
2789                                 dev_kfree_skb(skb);
2790                 } else {
2791                         /* Increment the number of packets */
2792                         rx_queue->stats.rx_packets++;
2793                         howmany++;
2794
2795                         if (likely(skb)) {
2796                                 pkt_len = bdp->length - ETH_FCS_LEN;
2797                                 /* Remove the FCS from the packet length */
2798                                 skb_put(skb, pkt_len);
2799                                 rx_queue->stats.rx_bytes += pkt_len;
2800                                 skb_record_rx_queue(skb, rx_queue->qindex);
2801                                 gfar_process_frame(dev, skb, amount_pull,
2802                                                    &rx_queue->grp->napi);
2803
2804                         } else {
2805                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2806                                 rx_queue->stats.rx_dropped++;
2807                                 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2808                         }
2809
2810                 }
2811
2812                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2813
2814                 /* Setup the new bdp */
2815                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2816
2817                 /* Update to the next pointer */
2818                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2819
2820                 /* update to point at the next skb */
2821                 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2822                                       RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2823         }
2824
2825         /* Update the current rxbd pointer to be the next one */
2826         rx_queue->cur_rx = bdp;
2827
2828         return howmany;
2829 }
2830
2831 static int gfar_poll(struct napi_struct *napi, int budget)
2832 {
2833         struct gfar_priv_grp *gfargrp =
2834                 container_of(napi, struct gfar_priv_grp, napi);
2835         struct gfar_private *priv = gfargrp->priv;
2836         struct gfar __iomem *regs = gfargrp->regs;
2837         struct gfar_priv_tx_q *tx_queue = NULL;
2838         struct gfar_priv_rx_q *rx_queue = NULL;
2839         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2840         int tx_cleaned = 0, i, left_over_budget = budget;
2841         unsigned long serviced_queues = 0;
2842         int num_queues = 0;
2843
2844         num_queues = gfargrp->num_rx_queues;
2845         budget_per_queue = budget/num_queues;
2846
2847         /* Clear IEVENT, so interrupts aren't called again
2848          * because of the packets that have already arrived
2849          */
2850         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2851
2852         while (num_queues && left_over_budget) {
2853                 budget_per_queue = left_over_budget/num_queues;
2854                 left_over_budget = 0;
2855
2856                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2857                         if (test_bit(i, &serviced_queues))
2858                                 continue;
2859                         rx_queue = priv->rx_queue[i];
2860                         tx_queue = priv->tx_queue[rx_queue->qindex];
2861
2862                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2863                         rx_cleaned_per_queue =
2864                                 gfar_clean_rx_ring(rx_queue, budget_per_queue);
2865                         rx_cleaned += rx_cleaned_per_queue;
2866                         if (rx_cleaned_per_queue < budget_per_queue) {
2867                                 left_over_budget = left_over_budget +
2868                                         (budget_per_queue -
2869                                          rx_cleaned_per_queue);
2870                                 set_bit(i, &serviced_queues);
2871                                 num_queues--;
2872                         }
2873                 }
2874         }
2875
2876         if (tx_cleaned)
2877                 return budget;
2878
2879         if (rx_cleaned < budget) {
2880                 napi_complete(napi);
2881
2882                 /* Clear the halt bit in RSTAT */
2883                 gfar_write(&regs->rstat, gfargrp->rstat);
2884
2885                 gfar_write(&regs->imask, IMASK_DEFAULT);
2886
2887                 /* If we are coalescing interrupts, update the timer
2888                  * Otherwise, clear it
2889                  */
2890                 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2891                                           gfargrp->tx_bit_map);
2892         }
2893
2894         return rx_cleaned;
2895 }
2896
2897 #ifdef CONFIG_NET_POLL_CONTROLLER
2898 /* Polling 'interrupt' - used by things like netconsole to send skbs
2899  * without having to re-enable interrupts. It's not called while
2900  * the interrupt routine is executing.
2901  */
2902 static void gfar_netpoll(struct net_device *dev)
2903 {
2904         struct gfar_private *priv = netdev_priv(dev);
2905         int i;
2906
2907         /* If the device has multiple interrupts, run tx/rx */
2908         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2909                 for (i = 0; i < priv->num_grps; i++) {
2910                         disable_irq(priv->gfargrp[i].interruptTransmit);
2911                         disable_irq(priv->gfargrp[i].interruptReceive);
2912                         disable_irq(priv->gfargrp[i].interruptError);
2913                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2914                                        &priv->gfargrp[i]);
2915                         enable_irq(priv->gfargrp[i].interruptError);
2916                         enable_irq(priv->gfargrp[i].interruptReceive);
2917                         enable_irq(priv->gfargrp[i].interruptTransmit);
2918                 }
2919         } else {
2920                 for (i = 0; i < priv->num_grps; i++) {
2921                         disable_irq(priv->gfargrp[i].interruptTransmit);
2922                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2923                                        &priv->gfargrp[i]);
2924                         enable_irq(priv->gfargrp[i].interruptTransmit);
2925                 }
2926         }
2927 }
2928 #endif
2929
2930 /* The interrupt handler for devices with one interrupt */
2931 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2932 {
2933         struct gfar_priv_grp *gfargrp = grp_id;
2934
2935         /* Save ievent for future reference */
2936         u32 events = gfar_read(&gfargrp->regs->ievent);
2937
2938         /* Check for reception */
2939         if (events & IEVENT_RX_MASK)
2940                 gfar_receive(irq, grp_id);
2941
2942         /* Check for transmit completion */
2943         if (events & IEVENT_TX_MASK)
2944                 gfar_transmit(irq, grp_id);
2945
2946         /* Check for errors */
2947         if (events & IEVENT_ERR_MASK)
2948                 gfar_error(irq, grp_id);
2949
2950         return IRQ_HANDLED;
2951 }
2952
2953 /* Called every time the controller might need to be made
2954  * aware of new link state.  The PHY code conveys this
2955  * information through variables in the phydev structure, and this
2956  * function converts those variables into the appropriate
2957  * register values, and can bring down the device if needed.
2958  */
2959 static void adjust_link(struct net_device *dev)
2960 {
2961         struct gfar_private *priv = netdev_priv(dev);
2962         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2963         unsigned long flags;
2964         struct phy_device *phydev = priv->phydev;
2965         int new_state = 0;
2966
2967         local_irq_save(flags);
2968         lock_tx_qs(priv);
2969
2970         if (phydev->link) {
2971                 u32 tempval = gfar_read(&regs->maccfg2);
2972                 u32 ecntrl = gfar_read(&regs->ecntrl);
2973
2974                 /* Now we make sure that we can be in full duplex mode.
2975                  * If not, we operate in half-duplex mode.
2976                  */
2977                 if (phydev->duplex != priv->oldduplex) {
2978                         new_state = 1;
2979                         if (!(phydev->duplex))
2980                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2981                         else
2982                                 tempval |= MACCFG2_FULL_DUPLEX;
2983
2984                         priv->oldduplex = phydev->duplex;
2985                 }
2986
2987                 if (phydev->speed != priv->oldspeed) {
2988                         new_state = 1;
2989                         switch (phydev->speed) {
2990                         case 1000:
2991                                 tempval =
2992                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2993
2994                                 ecntrl &= ~(ECNTRL_R100);
2995                                 break;
2996                         case 100:
2997                         case 10:
2998                                 tempval =
2999                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3000
3001                                 /* Reduced mode distinguishes
3002                                  * between 10 and 100
3003                                  */
3004                                 if (phydev->speed == SPEED_100)
3005                                         ecntrl |= ECNTRL_R100;
3006                                 else
3007                                         ecntrl &= ~(ECNTRL_R100);
3008                                 break;
3009                         default:
3010                                 netif_warn(priv, link, dev,
3011                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3012                                            phydev->speed);
3013                                 break;
3014                         }
3015
3016                         priv->oldspeed = phydev->speed;
3017                 }
3018
3019                 gfar_write(&regs->maccfg2, tempval);
3020                 gfar_write(&regs->ecntrl, ecntrl);
3021
3022                 if (!priv->oldlink) {
3023                         new_state = 1;
3024                         priv->oldlink = 1;
3025                 }
3026         } else if (priv->oldlink) {
3027                 new_state = 1;
3028                 priv->oldlink = 0;
3029                 priv->oldspeed = 0;
3030                 priv->oldduplex = -1;
3031         }
3032
3033         if (new_state && netif_msg_link(priv))
3034                 phy_print_status(phydev);
3035         unlock_tx_qs(priv);
3036         local_irq_restore(flags);
3037 }
3038
3039 /* Update the hash table based on the current list of multicast
3040  * addresses we subscribe to.  Also, change the promiscuity of
3041  * the device based on the flags (this function is called
3042  * whenever dev->flags is changed
3043  */
3044 static void gfar_set_multi(struct net_device *dev)
3045 {
3046         struct netdev_hw_addr *ha;
3047         struct gfar_private *priv = netdev_priv(dev);
3048         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3049         u32 tempval;
3050
3051         if (dev->flags & IFF_PROMISC) {
3052                 /* Set RCTRL to PROM */
3053                 tempval = gfar_read(&regs->rctrl);
3054                 tempval |= RCTRL_PROM;
3055                 gfar_write(&regs->rctrl, tempval);
3056         } else {
3057                 /* Set RCTRL to not PROM */
3058                 tempval = gfar_read(&regs->rctrl);
3059                 tempval &= ~(RCTRL_PROM);
3060                 gfar_write(&regs->rctrl, tempval);
3061         }
3062
3063         if (dev->flags & IFF_ALLMULTI) {
3064                 /* Set the hash to rx all multicast frames */
3065                 gfar_write(&regs->igaddr0, 0xffffffff);
3066                 gfar_write(&regs->igaddr1, 0xffffffff);
3067                 gfar_write(&regs->igaddr2, 0xffffffff);
3068                 gfar_write(&regs->igaddr3, 0xffffffff);
3069                 gfar_write(&regs->igaddr4, 0xffffffff);
3070                 gfar_write(&regs->igaddr5, 0xffffffff);
3071                 gfar_write(&regs->igaddr6, 0xffffffff);
3072                 gfar_write(&regs->igaddr7, 0xffffffff);
3073                 gfar_write(&regs->gaddr0, 0xffffffff);
3074                 gfar_write(&regs->gaddr1, 0xffffffff);
3075                 gfar_write(&regs->gaddr2, 0xffffffff);
3076                 gfar_write(&regs->gaddr3, 0xffffffff);
3077                 gfar_write(&regs->gaddr4, 0xffffffff);
3078                 gfar_write(&regs->gaddr5, 0xffffffff);
3079                 gfar_write(&regs->gaddr6, 0xffffffff);
3080                 gfar_write(&regs->gaddr7, 0xffffffff);
3081         } else {
3082                 int em_num;
3083                 int idx;
3084
3085                 /* zero out the hash */
3086                 gfar_write(&regs->igaddr0, 0x0);
3087                 gfar_write(&regs->igaddr1, 0x0);
3088                 gfar_write(&regs->igaddr2, 0x0);
3089                 gfar_write(&regs->igaddr3, 0x0);
3090                 gfar_write(&regs->igaddr4, 0x0);
3091                 gfar_write(&regs->igaddr5, 0x0);
3092                 gfar_write(&regs->igaddr6, 0x0);
3093                 gfar_write(&regs->igaddr7, 0x0);
3094                 gfar_write(&regs->gaddr0, 0x0);
3095                 gfar_write(&regs->gaddr1, 0x0);
3096                 gfar_write(&regs->gaddr2, 0x0);
3097                 gfar_write(&regs->gaddr3, 0x0);
3098                 gfar_write(&regs->gaddr4, 0x0);
3099                 gfar_write(&regs->gaddr5, 0x0);
3100                 gfar_write(&regs->gaddr6, 0x0);
3101                 gfar_write(&regs->gaddr7, 0x0);
3102
3103                 /* If we have extended hash tables, we need to
3104                  * clear the exact match registers to prepare for
3105                  * setting them
3106                  */
3107                 if (priv->extended_hash) {
3108                         em_num = GFAR_EM_NUM + 1;
3109                         gfar_clear_exact_match(dev);
3110                         idx = 1;
3111                 } else {
3112                         idx = 0;
3113                         em_num = 0;
3114                 }
3115
3116                 if (netdev_mc_empty(dev))
3117                         return;
3118
3119                 /* Parse the list, and set the appropriate bits */
3120                 netdev_for_each_mc_addr(ha, dev) {
3121                         if (idx < em_num) {
3122                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3123                                 idx++;
3124                         } else
3125                                 gfar_set_hash_for_addr(dev, ha->addr);
3126                 }
3127         }
3128 }
3129
3130
3131 /* Clears each of the exact match registers to zero, so they
3132  * don't interfere with normal reception
3133  */
3134 static void gfar_clear_exact_match(struct net_device *dev)
3135 {
3136         int idx;
3137         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3138
3139         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3140                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3141 }
3142
3143 /* Set the appropriate hash bit for the given addr */
3144 /* The algorithm works like so:
3145  * 1) Take the Destination Address (ie the multicast address), and
3146  * do a CRC on it (little endian), and reverse the bits of the
3147  * result.
3148  * 2) Use the 8 most significant bits as a hash into a 256-entry
3149  * table.  The table is controlled through 8 32-bit registers:
3150  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3151  * gaddr7.  This means that the 3 most significant bits in the
3152  * hash index which gaddr register to use, and the 5 other bits
3153  * indicate which bit (assuming an IBM numbering scheme, which
3154  * for PowerPC (tm) is usually the case) in the register holds
3155  * the entry.
3156  */
3157 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3158 {
3159         u32 tempval;
3160         struct gfar_private *priv = netdev_priv(dev);
3161         u32 result = ether_crc(ETH_ALEN, addr);
3162         int width = priv->hash_width;
3163         u8 whichbit = (result >> (32 - width)) & 0x1f;
3164         u8 whichreg = result >> (32 - width + 5);
3165         u32 value = (1 << (31-whichbit));
3166
3167         tempval = gfar_read(priv->hash_regs[whichreg]);
3168         tempval |= value;
3169         gfar_write(priv->hash_regs[whichreg], tempval);
3170 }
3171
3172
3173 /* There are multiple MAC Address register pairs on some controllers
3174  * This function sets the numth pair to a given address
3175  */
3176 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3177                                   const u8 *addr)
3178 {
3179         struct gfar_private *priv = netdev_priv(dev);
3180         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3181         int idx;
3182         char tmpbuf[ETH_ALEN];
3183         u32 tempval;
3184         u32 __iomem *macptr = &regs->macstnaddr1;
3185
3186         macptr += num*2;
3187
3188         /* Now copy it into the mac registers backwards, cuz
3189          * little endian is silly
3190          */
3191         for (idx = 0; idx < ETH_ALEN; idx++)
3192                 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3193
3194         gfar_write(macptr, *((u32 *) (tmpbuf)));
3195
3196         tempval = *((u32 *) (tmpbuf + 4));
3197
3198         gfar_write(macptr+1, tempval);
3199 }
3200
3201 /* GFAR error interrupt handler */
3202 static irqreturn_t gfar_error(int irq, void *grp_id)
3203 {
3204         struct gfar_priv_grp *gfargrp = grp_id;
3205         struct gfar __iomem *regs = gfargrp->regs;
3206         struct gfar_private *priv= gfargrp->priv;
3207         struct net_device *dev = priv->ndev;
3208
3209         /* Save ievent for future reference */
3210         u32 events = gfar_read(&regs->ievent);
3211
3212         /* Clear IEVENT */
3213         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3214
3215         /* Magic Packet is not an error. */
3216         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3217             (events & IEVENT_MAG))
3218                 events &= ~IEVENT_MAG;
3219
3220         /* Hmm... */
3221         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3222                 netdev_dbg(dev,
3223                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3224                            events, gfar_read(&regs->imask));
3225
3226         /* Update the error counters */
3227         if (events & IEVENT_TXE) {
3228                 dev->stats.tx_errors++;
3229
3230                 if (events & IEVENT_LC)
3231                         dev->stats.tx_window_errors++;
3232                 if (events & IEVENT_CRL)
3233                         dev->stats.tx_aborted_errors++;
3234                 if (events & IEVENT_XFUN) {
3235                         unsigned long flags;
3236
3237                         netif_dbg(priv, tx_err, dev,
3238                                   "TX FIFO underrun, packet dropped\n");
3239                         dev->stats.tx_dropped++;
3240                         atomic64_inc(&priv->extra_stats.tx_underrun);
3241
3242                         local_irq_save(flags);
3243                         lock_tx_qs(priv);
3244
3245                         /* Reactivate the Tx Queues */
3246                         gfar_write(&regs->tstat, gfargrp->tstat);
3247
3248                         unlock_tx_qs(priv);
3249                         local_irq_restore(flags);
3250                 }
3251                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3252         }
3253         if (events & IEVENT_BSY) {
3254                 dev->stats.rx_errors++;
3255                 atomic64_inc(&priv->extra_stats.rx_bsy);
3256
3257                 gfar_receive(irq, grp_id);
3258
3259                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3260                           gfar_read(&regs->rstat));
3261         }
3262         if (events & IEVENT_BABR) {
3263                 dev->stats.rx_errors++;
3264                 atomic64_inc(&priv->extra_stats.rx_babr);
3265
3266                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3267         }
3268         if (events & IEVENT_EBERR) {
3269                 atomic64_inc(&priv->extra_stats.eberr);
3270                 netif_dbg(priv, rx_err, dev, "bus error\n");
3271         }
3272         if (events & IEVENT_RXC)
3273                 netif_dbg(priv, rx_status, dev, "control frame\n");
3274
3275         if (events & IEVENT_BABT) {
3276                 atomic64_inc(&priv->extra_stats.tx_babt);
3277                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3278         }
3279         return IRQ_HANDLED;
3280 }
3281
3282 static struct of_device_id gfar_match[] =
3283 {
3284         {
3285                 .type = "network",
3286                 .compatible = "gianfar",
3287         },
3288         {
3289                 .compatible = "fsl,etsec2",
3290         },
3291         {},
3292 };
3293 MODULE_DEVICE_TABLE(of, gfar_match);
3294
3295 /* Structure for a device driver */
3296 static struct platform_driver gfar_driver = {
3297         .driver = {
3298                 .name = "fsl-gianfar",
3299                 .owner = THIS_MODULE,
3300                 .pm = GFAR_PM_OPS,
3301                 .of_match_table = gfar_match,
3302         },
3303         .probe = gfar_probe,
3304         .remove = gfar_remove,
3305 };
3306
3307 module_platform_driver(gfar_driver);