drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/of_mdio.h>
  82 #include <linux/of_platform.h>
  83 #include <linux/ip.h>
  84 #include <linux/tcp.h>
  85 #include <linux/udp.h>
  86 #include <linux/in.h>
  87 #include <linux/net_tstamp.h>
  88
  89 #include <asm/io.h>
  90 #include <asm/reg.h>
  91 #include <asm/irq.h>
  92 #include <asm/uaccess.h>
  93 #include <linux/module.h>
  94 #include <linux/dma-mapping.h>
  95 #include <linux/crc32.h>
  96 #include <linux/mii.h>
  97 #include <linux/phy.h>
  98 #include <linux/phy_fixed.h>
  99 #include <linux/of.h>
 100 #include <linux/of_net.h>
 101
 102 #include "gianfar.h"
 103
 104 #define TX_TIMEOUT      (1*HZ)
 105
 106 const char gfar_driver_version[] = "1.3";
 107
 108 static int gfar_enet_open(struct net_device *dev);
 109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 110 static void gfar_reset_task(struct work_struct *work);
 111 static void gfar_timeout(struct net_device *dev);
 112 static int gfar_close(struct net_device *dev);
 113 struct sk_buff *gfar_new_skb(struct net_device *dev);
 114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 115                            struct sk_buff *skb);
 116 static int gfar_set_mac_address(struct net_device *dev);
 117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 118 static irqreturn_t gfar_error(int irq, void *dev_id);
 119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 121 static void adjust_link(struct net_device *dev);
 122 static void init_registers(struct net_device *dev);
 123 static int init_phy(struct net_device *dev);
 124 static int gfar_probe(struct platform_device *ofdev);
 125 static int gfar_remove(struct platform_device *ofdev);
 126 static void free_skb_resources(struct gfar_private *priv);
 127 static void gfar_set_multi(struct net_device *dev);
 128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 129 static void gfar_configure_serdes(struct net_device *dev);
 130 static int gfar_poll(struct napi_struct *napi, int budget);
 131 #ifdef CONFIG_NET_POLL_CONTROLLER
 132 static void gfar_netpoll(struct net_device *dev);
 133 #endif
 134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 136 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 137                               int amount_pull, struct napi_struct *napi);
 138 void gfar_halt(struct net_device *dev);
 139 static void gfar_halt_nodisable(struct net_device *dev);
 140 void gfar_start(struct net_device *dev);
 141 static void gfar_clear_exact_match(struct net_device *dev);
 142 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 143                                   const u8 *addr);
 144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 145
 146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 148 MODULE_LICENSE("GPL");
 149
 150 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 151                             dma_addr_t buf)
 152 {
 153         u32 lstatus;
 154
 155         bdp->bufPtr = buf;
 156
 157         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 158         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 159                 lstatus |= BD_LFLAG(RXBD_WRAP);
 160
 161         eieio();
 162
 163         bdp->lstatus = lstatus;
 164 }
 165
 166 static int gfar_init_bds(struct net_device *ndev)
 167 {
 168         struct gfar_private *priv = netdev_priv(ndev);
 169         struct gfar_priv_tx_q *tx_queue = NULL;
 170         struct gfar_priv_rx_q *rx_queue = NULL;
 171         struct txbd8 *txbdp;
 172         struct rxbd8 *rxbdp;
 173         int i, j;
 174
 175         for (i = 0; i < priv->num_tx_queues; i++) {
 176                 tx_queue = priv->tx_queue[i];
 177                 /* Initialize some variables in our dev structure */
 178                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 179                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 180                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 181                 tx_queue->skb_curtx = 0;
 182                 tx_queue->skb_dirtytx = 0;
 183
 184                 /* Initialize Transmit Descriptor Ring */
 185                 txbdp = tx_queue->tx_bd_base;
 186                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 187                         txbdp->lstatus = 0;
 188                         txbdp->bufPtr = 0;
 189                         txbdp++;
 190                 }
 191
 192                 /* Set the last descriptor in the ring to indicate wrap */
 193                 txbdp--;
 194                 txbdp->status |= TXBD_WRAP;
 195         }
 196
 197         for (i = 0; i < priv->num_rx_queues; i++) {
 198                 rx_queue = priv->rx_queue[i];
 199                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 200                 rx_queue->skb_currx = 0;
 201                 rxbdp = rx_queue->rx_bd_base;
 202
 203                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 204                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 205
 206                         if (skb) {
 207                                 gfar_init_rxbdp(rx_queue, rxbdp,
 208                                                 rxbdp->bufPtr);
 209                         } else {
 210                                 skb = gfar_new_skb(ndev);
 211                                 if (!skb) {
 212                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 213                                         return -ENOMEM;
 214                                 }
 215                                 rx_queue->rx_skbuff[j] = skb;
 216
 217                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 218                         }
 219
 220                         rxbdp++;
 221                 }
 222
 223         }
 224
 225         return 0;
 226 }
 227
 228 static int gfar_alloc_skb_resources(struct net_device *ndev)
 229 {
 230         void *vaddr;
 231         dma_addr_t addr;
 232         int i, j, k;
 233         struct gfar_private *priv = netdev_priv(ndev);
 234         struct device *dev = &priv->ofdev->dev;
 235         struct gfar_priv_tx_q *tx_queue = NULL;
 236         struct gfar_priv_rx_q *rx_queue = NULL;
 237
 238         priv->total_tx_ring_size = 0;
 239         for (i = 0; i < priv->num_tx_queues; i++)
 240                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 241
 242         priv->total_rx_ring_size = 0;
 243         for (i = 0; i < priv->num_rx_queues; i++)
 244                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 245
 246         /* Allocate memory for the buffer descriptors */
 247         vaddr = dma_alloc_coherent(dev,
 248                         sizeof(struct txbd8) * priv->total_tx_ring_size +
 249                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
 250                         &addr, GFP_KERNEL);
 251         if (!vaddr) {
 252                 netif_err(priv, ifup, ndev,
 253                           "Could not allocate buffer descriptors!\n");
 254                 return -ENOMEM;
 255         }
 256
 257         for (i = 0; i < priv->num_tx_queues; i++) {
 258                 tx_queue = priv->tx_queue[i];
 259                 tx_queue->tx_bd_base = vaddr;
 260                 tx_queue->tx_bd_dma_base = addr;
 261                 tx_queue->dev = ndev;
 262                 /* enet DMA only understands physical addresses */
 263                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 264                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 265         }
 266
 267         /* Start the rx descriptor ring where the tx ring leaves off */
 268         for (i = 0; i < priv->num_rx_queues; i++) {
 269                 rx_queue = priv->rx_queue[i];
 270                 rx_queue->rx_bd_base = vaddr;
 271                 rx_queue->rx_bd_dma_base = addr;
 272                 rx_queue->dev = ndev;
 273                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 274                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 275         }
 276
 277         /* Setup the skbuff rings */
 278         for (i = 0; i < priv->num_tx_queues; i++) {
 279                 tx_queue = priv->tx_queue[i];
 280                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
 281                                               tx_queue->tx_ring_size,
 282                                               GFP_KERNEL);
 283                 if (!tx_queue->tx_skbuff) {
 284                         netif_err(priv, ifup, ndev,
 285                                   "Could not allocate tx_skbuff\n");
 286                         goto cleanup;
 287                 }
 288
 289                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 290                         tx_queue->tx_skbuff[k] = NULL;
 291         }
 292
 293         for (i = 0; i < priv->num_rx_queues; i++) {
 294                 rx_queue = priv->rx_queue[i];
 295                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
 296                                               rx_queue->rx_ring_size,
 297                                               GFP_KERNEL);
 298
 299                 if (!rx_queue->rx_skbuff) {
 300                         netif_err(priv, ifup, ndev,
 301                                   "Could not allocate rx_skbuff\n");
 302                         goto cleanup;
 303                 }
 304
 305                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 306                         rx_queue->rx_skbuff[j] = NULL;
 307         }
 308
 309         if (gfar_init_bds(ndev))
 310                 goto cleanup;
 311
 312         return 0;
 313
 314 cleanup:
 315         free_skb_resources(priv);
 316         return -ENOMEM;
 317 }
 318
 319 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 320 {
 321         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 322         u32 __iomem *baddr;
 323         int i;
 324
 325         baddr = &regs->tbase0;
 326         for (i = 0; i < priv->num_tx_queues; i++) {
 327                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 328                 baddr += 2;
 329         }
 330
 331         baddr = &regs->rbase0;
 332         for (i = 0; i < priv->num_rx_queues; i++) {
 333                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 334                 baddr += 2;
 335         }
 336 }
 337
 338 static void gfar_init_mac(struct net_device *ndev)
 339 {
 340         struct gfar_private *priv = netdev_priv(ndev);
 341         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 342         u32 rctrl = 0;
 343         u32 tctrl = 0;
 344         u32 attrs = 0;
 345
 346         /* write the tx/rx base registers */
 347         gfar_init_tx_rx_base(priv);
 348
 349         /* Configure the coalescing support */
 350         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 351
 352         if (priv->rx_filer_enable) {
 353                 rctrl |= RCTRL_FILREN;
 354                 /* Program the RIR0 reg with the required distribution */
 355                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 356         }
 357
 358         /* Restore PROMISC mode */
 359         if (ndev->flags & IFF_PROMISC)
 360                 rctrl |= RCTRL_PROM;
 361
 362         if (ndev->features & NETIF_F_RXCSUM)
 363                 rctrl |= RCTRL_CHECKSUMMING;
 364
 365         if (priv->extended_hash) {
 366                 rctrl |= RCTRL_EXTHASH;
 367
 368                 gfar_clear_exact_match(ndev);
 369                 rctrl |= RCTRL_EMEN;
 370         }
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Insert receive time stamps into padding alignment bytes */
 378         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 379                 rctrl &= ~RCTRL_PAL_MASK;
 380                 rctrl |= RCTRL_PADDING(8);
 381                 priv->padding = 8;
 382         }
 383
 384         /* Enable HW time stamping if requested from user space */
 385         if (priv->hwts_rx_en)
 386                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 387
 388         if (ndev->features & NETIF_F_HW_VLAN_RX)
 389                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 390
 391         /* Init rctrl based on our settings */
 392         gfar_write(&regs->rctrl, rctrl);
 393
 394         if (ndev->features & NETIF_F_IP_CSUM)
 395                 tctrl |= TCTRL_INIT_CSUM;
 396
 397         if (priv->prio_sched_en)
 398                 tctrl |= TCTRL_TXSCHED_PRIO;
 399         else {
 400                 tctrl |= TCTRL_TXSCHED_WRRS;
 401                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 402                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 403         }
 404
 405         gfar_write(&regs->tctrl, tctrl);
 406
 407         /* Set the extraction length and index */
 408         attrs = ATTRELI_EL(priv->rx_stash_size) |
 409                 ATTRELI_EI(priv->rx_stash_index);
 410
 411         gfar_write(&regs->attreli, attrs);
 412
 413         /* Start with defaults, and add stashing or locking
 414          * depending on the approprate variables
 415          */
 416         attrs = ATTR_INIT_SETTINGS;
 417
 418         if (priv->bd_stash_en)
 419                 attrs |= ATTR_BDSTASH;
 420
 421         if (priv->rx_stash_size != 0)
 422                 attrs |= ATTR_BUFSTASH;
 423
 424         gfar_write(&regs->attr, attrs);
 425
 426         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 427         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 428         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 429 }
 430
 431 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 432 {
 433         struct gfar_private *priv = netdev_priv(dev);
 434         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 435         unsigned long tx_packets = 0, tx_bytes = 0;
 436         int i;
 437
 438         for (i = 0; i < priv->num_rx_queues; i++) {
 439                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 440                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 441                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 442         }
 443
 444         dev->stats.rx_packets = rx_packets;
 445         dev->stats.rx_bytes   = rx_bytes;
 446         dev->stats.rx_dropped = rx_dropped;
 447
 448         for (i = 0; i < priv->num_tx_queues; i++) {
 449                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 450                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 451         }
 452
 453         dev->stats.tx_bytes   = tx_bytes;
 454         dev->stats.tx_packets = tx_packets;
 455
 456         return &dev->stats;
 457 }
 458
 459 static const struct net_device_ops gfar_netdev_ops = {
 460         .ndo_open = gfar_enet_open,
 461         .ndo_start_xmit = gfar_start_xmit,
 462         .ndo_stop = gfar_close,
 463         .ndo_change_mtu = gfar_change_mtu,
 464         .ndo_set_features = gfar_set_features,
 465         .ndo_set_rx_mode = gfar_set_multi,
 466         .ndo_tx_timeout = gfar_timeout,
 467         .ndo_do_ioctl = gfar_ioctl,
 468         .ndo_get_stats = gfar_get_stats,
 469         .ndo_set_mac_address = eth_mac_addr,
 470         .ndo_validate_addr = eth_validate_addr,
 471 #ifdef CONFIG_NET_POLL_CONTROLLER
 472         .ndo_poll_controller = gfar_netpoll,
 473 #endif
 474 };
 475
 476 void lock_rx_qs(struct gfar_private *priv)
 477 {
 478         int i;
 479
 480         for (i = 0; i < priv->num_rx_queues; i++)
 481                 spin_lock(&priv->rx_queue[i]->rxlock);
 482 }
 483
 484 void lock_tx_qs(struct gfar_private *priv)
 485 {
 486         int i;
 487
 488         for (i = 0; i < priv->num_tx_queues; i++)
 489                 spin_lock(&priv->tx_queue[i]->txlock);
 490 }
 491
 492 void unlock_rx_qs(struct gfar_private *priv)
 493 {
 494         int i;
 495
 496         for (i = 0; i < priv->num_rx_queues; i++)
 497                 spin_unlock(&priv->rx_queue[i]->rxlock);
 498 }
 499
 500 void unlock_tx_qs(struct gfar_private *priv)
 501 {
 502         int i;
 503
 504         for (i = 0; i < priv->num_tx_queues; i++)
 505                 spin_unlock(&priv->tx_queue[i]->txlock);
 506 }
 507
 508 static bool gfar_is_vlan_on(struct gfar_private *priv)
 509 {
 510         return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
 511                (priv->ndev->features & NETIF_F_HW_VLAN_TX);
 512 }
 513
 514 /* Returns 1 if incoming frames use an FCB */
 515 static inline int gfar_uses_fcb(struct gfar_private *priv)
 516 {
 517         return gfar_is_vlan_on(priv) ||
 518                (priv->ndev->features & NETIF_F_RXCSUM) ||
 519                (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
 520 }
 521
 522 static void free_tx_pointers(struct gfar_private *priv)
 523 {
 524         int i;
 525
 526         for (i = 0; i < priv->num_tx_queues; i++)
 527                 kfree(priv->tx_queue[i]);
 528 }
 529
 530 static void free_rx_pointers(struct gfar_private *priv)
 531 {
 532         int i;
 533
 534         for (i = 0; i < priv->num_rx_queues; i++)
 535                 kfree(priv->rx_queue[i]);
 536 }
 537
 538 static void unmap_group_regs(struct gfar_private *priv)
 539 {
 540         int i;
 541
 542         for (i = 0; i < MAXGROUPS; i++)
 543                 if (priv->gfargrp[i].regs)
 544                         iounmap(priv->gfargrp[i].regs);
 545 }
 546
 547 static void free_gfar_dev(struct gfar_private *priv)
 548 {
 549         int i, j;
 550
 551         for (i = 0; i < priv->num_grps; i++)
 552                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 553                         kfree(priv->gfargrp[i].irqinfo[j]);
 554                         priv->gfargrp[i].irqinfo[j] = NULL;
 555                 }
 556
 557         free_netdev(priv->ndev);
 558 }
 559
 560 static void disable_napi(struct gfar_private *priv)
 561 {
 562         int i;
 563
 564         for (i = 0; i < priv->num_grps; i++)
 565                 napi_disable(&priv->gfargrp[i].napi);
 566 }
 567
 568 static void enable_napi(struct gfar_private *priv)
 569 {
 570         int i;
 571
 572         for (i = 0; i < priv->num_grps; i++)
 573                 napi_enable(&priv->gfargrp[i].napi);
 574 }
 575
 576 static int gfar_parse_group(struct device_node *np,
 577                             struct gfar_private *priv, const char *model)
 578 {
 579         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 580         u32 *queue_mask;
 581         int i;
 582
 583         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 584                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 585                                           GFP_KERNEL);
 586                 if (!grp->irqinfo[i])
 587                         return -ENOMEM;
 588         }
 589
 590         grp->regs = of_iomap(np, 0);
 591         if (!grp->regs)
 592                 return -ENOMEM;
 593
 594         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 595
 596         /* If we aren't the FEC we have multiple interrupts */
 597         if (model && strcasecmp(model, "FEC")) {
 598                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 599                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 600                 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
 601                     gfar_irq(grp, RX)->irq == NO_IRQ ||
 602                     gfar_irq(grp, ER)->irq == NO_IRQ)
 603                         return -EINVAL;
 604         }
 605
 606         grp->grp_id = priv->num_grps;
 607         grp->priv = priv;
 608         spin_lock_init(&grp->grplock);
 609         if (priv->mode == MQ_MG_MODE) {
 610                 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
 611                 grp->rx_bit_map = queue_mask ?
 612                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 613                 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
 614                 grp->tx_bit_map = queue_mask ?
 615                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 616         } else {
 617                 grp->rx_bit_map = 0xFF;
 618                 grp->tx_bit_map = 0xFF;
 619         }
 620         priv->num_grps++;
 621
 622         return 0;
 623 }
 624
 625 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 626 {
 627         const char *model;
 628         const char *ctype;
 629         const void *mac_addr;
 630         int err = 0, i;
 631         struct net_device *dev = NULL;
 632         struct gfar_private *priv = NULL;
 633         struct device_node *np = ofdev->dev.of_node;
 634         struct device_node *child = NULL;
 635         const u32 *stash;
 636         const u32 *stash_len;
 637         const u32 *stash_idx;
 638         unsigned int num_tx_qs, num_rx_qs;
 639         u32 *tx_queues, *rx_queues;
 640
 641         if (!np || !of_device_is_available(np))
 642                 return -ENODEV;
 643
 644         /* parse the num of tx and rx queues */
 645         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 646         num_tx_qs = tx_queues ? *tx_queues : 1;
 647
 648         if (num_tx_qs > MAX_TX_QS) {
 649                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 650                        num_tx_qs, MAX_TX_QS);
 651                 pr_err("Cannot do alloc_etherdev, aborting\n");
 652                 return -EINVAL;
 653         }
 654
 655         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 656         num_rx_qs = rx_queues ? *rx_queues : 1;
 657
 658         if (num_rx_qs > MAX_RX_QS) {
 659                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 660                        num_rx_qs, MAX_RX_QS);
 661                 pr_err("Cannot do alloc_etherdev, aborting\n");
 662                 return -EINVAL;
 663         }
 664
 665         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 666         dev = *pdev;
 667         if (NULL == dev)
 668                 return -ENOMEM;
 669
 670         priv = netdev_priv(dev);
 671         priv->node = ofdev->dev.of_node;
 672         priv->ndev = dev;
 673
 674         priv->num_tx_queues = num_tx_qs;
 675         netif_set_real_num_rx_queues(dev, num_rx_qs);
 676         priv->num_rx_queues = num_rx_qs;
 677         priv->num_grps = 0x0;
 678
 679         /* Init Rx queue filer rule set linked list */
 680         INIT_LIST_HEAD(&priv->rx_list.list);
 681         priv->rx_list.count = 0;
 682         mutex_init(&priv->rx_queue_access);
 683
 684         model = of_get_property(np, "model", NULL);
 685
 686         for (i = 0; i < MAXGROUPS; i++)
 687                 priv->gfargrp[i].regs = NULL;
 688
 689         /* Parse and initialize group specific information */
 690         if (of_device_is_compatible(np, "fsl,etsec2")) {
 691                 priv->mode = MQ_MG_MODE;
 692                 for_each_child_of_node(np, child) {
 693                         err = gfar_parse_group(child, priv, model);
 694                         if (err)
 695                                 goto err_grp_init;
 696                 }
 697         } else {
 698                 priv->mode = SQ_SG_MODE;
 699                 err = gfar_parse_group(np, priv, model);
 700                 if (err)
 701                         goto err_grp_init;
 702         }
 703
 704         for (i = 0; i < priv->num_tx_queues; i++)
 705                priv->tx_queue[i] = NULL;
 706         for (i = 0; i < priv->num_rx_queues; i++)
 707                 priv->rx_queue[i] = NULL;
 708
 709         for (i = 0; i < priv->num_tx_queues; i++) {
 710                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 711                                             GFP_KERNEL);
 712                 if (!priv->tx_queue[i]) {
 713                         err = -ENOMEM;
 714                         goto tx_alloc_failed;
 715                 }
 716                 priv->tx_queue[i]->tx_skbuff = NULL;
 717                 priv->tx_queue[i]->qindex = i;
 718                 priv->tx_queue[i]->dev = dev;
 719                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 720         }
 721
 722         for (i = 0; i < priv->num_rx_queues; i++) {
 723                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 724                                             GFP_KERNEL);
 725                 if (!priv->rx_queue[i]) {
 726                         err = -ENOMEM;
 727                         goto rx_alloc_failed;
 728                 }
 729                 priv->rx_queue[i]->rx_skbuff = NULL;
 730                 priv->rx_queue[i]->qindex = i;
 731                 priv->rx_queue[i]->dev = dev;
 732                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 733         }
 734
 735
 736         stash = of_get_property(np, "bd-stash", NULL);
 737
 738         if (stash) {
 739                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 740                 priv->bd_stash_en = 1;
 741         }
 742
 743         stash_len = of_get_property(np, "rx-stash-len", NULL);
 744
 745         if (stash_len)
 746                 priv->rx_stash_size = *stash_len;
 747
 748         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 749
 750         if (stash_idx)
 751                 priv->rx_stash_index = *stash_idx;
 752
 753         if (stash_len || stash_idx)
 754                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 755
 756         mac_addr = of_get_mac_address(np);
 757
 758         if (mac_addr)
 759                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 760
 761         if (model && !strcasecmp(model, "TSEC"))
 762                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 763                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 764                                      FSL_GIANFAR_DEV_HAS_RMON |
 765                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 766
 767         if (model && !strcasecmp(model, "eTSEC"))
 768                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 769                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 770                                      FSL_GIANFAR_DEV_HAS_RMON |
 771                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 772                                      FSL_GIANFAR_DEV_HAS_PADDING |
 773                                      FSL_GIANFAR_DEV_HAS_CSUM |
 774                                      FSL_GIANFAR_DEV_HAS_VLAN |
 775                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 776                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 777                                      FSL_GIANFAR_DEV_HAS_TIMER;
 778
 779         ctype = of_get_property(np, "phy-connection-type", NULL);
 780
 781         /* We only care about rgmii-id.  The rest are autodetected */
 782         if (ctype && !strcmp(ctype, "rgmii-id"))
 783                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 784         else
 785                 priv->interface = PHY_INTERFACE_MODE_MII;
 786
 787         if (of_get_property(np, "fsl,magic-packet", NULL))
 788                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 789
 790         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 791
 792         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 793         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 794
 795         return 0;
 796
 797 rx_alloc_failed:
 798         free_rx_pointers(priv);
 799 tx_alloc_failed:
 800         free_tx_pointers(priv);
 801 err_grp_init:
 802         unmap_group_regs(priv);
 803         free_gfar_dev(priv);
 804         return err;
 805 }
 806
 807 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 808                                struct ifreq *ifr, int cmd)
 809 {
 810         struct hwtstamp_config config;
 811         struct gfar_private *priv = netdev_priv(netdev);
 812
 813         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 814                 return -EFAULT;
 815
 816         /* reserved for future extensions */
 817         if (config.flags)
 818                 return -EINVAL;
 819
 820         switch (config.tx_type) {
 821         case HWTSTAMP_TX_OFF:
 822                 priv->hwts_tx_en = 0;
 823                 break;
 824         case HWTSTAMP_TX_ON:
 825                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 826                         return -ERANGE;
 827                 priv->hwts_tx_en = 1;
 828                 break;
 829         default:
 830                 return -ERANGE;
 831         }
 832
 833         switch (config.rx_filter) {
 834         case HWTSTAMP_FILTER_NONE:
 835                 if (priv->hwts_rx_en) {
 836                         stop_gfar(netdev);
 837                         priv->hwts_rx_en = 0;
 838                         startup_gfar(netdev);
 839                 }
 840                 break;
 841         default:
 842                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 843                         return -ERANGE;
 844                 if (!priv->hwts_rx_en) {
 845                         stop_gfar(netdev);
 846                         priv->hwts_rx_en = 1;
 847                         startup_gfar(netdev);
 848                 }
 849                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 850                 break;
 851         }
 852
 853         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 854                 -EFAULT : 0;
 855 }
 856
 857 /* Ioctl MII Interface */
 858 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 859 {
 860         struct gfar_private *priv = netdev_priv(dev);
 861
 862         if (!netif_running(dev))
 863                 return -EINVAL;
 864
 865         if (cmd == SIOCSHWTSTAMP)
 866                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 867
 868         if (!priv->phydev)
 869                 return -ENODEV;
 870
 871         return phy_mii_ioctl(priv->phydev, rq, cmd);
 872 }
 873
 874 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 875 {
 876         unsigned int new_bit_map = 0x0;
 877         int mask = 0x1 << (max_qs - 1), i;
 878
 879         for (i = 0; i < max_qs; i++) {
 880                 if (bit_map & mask)
 881                         new_bit_map = new_bit_map + (1 << i);
 882                 mask = mask >> 0x1;
 883         }
 884         return new_bit_map;
 885 }
 886
 887 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 888                                    u32 class)
 889 {
 890         u32 rqfpr = FPR_FILER_MASK;
 891         u32 rqfcr = 0x0;
 892
 893         rqfar--;
 894         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 895         priv->ftp_rqfpr[rqfar] = rqfpr;
 896         priv->ftp_rqfcr[rqfar] = rqfcr;
 897         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 898
 899         rqfar--;
 900         rqfcr = RQFCR_CMP_NOMATCH;
 901         priv->ftp_rqfpr[rqfar] = rqfpr;
 902         priv->ftp_rqfcr[rqfar] = rqfcr;
 903         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 904
 905         rqfar--;
 906         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 907         rqfpr = class;
 908         priv->ftp_rqfcr[rqfar] = rqfcr;
 909         priv->ftp_rqfpr[rqfar] = rqfpr;
 910         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 911
 912         rqfar--;
 913         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 914         rqfpr = class;
 915         priv->ftp_rqfcr[rqfar] = rqfcr;
 916         priv->ftp_rqfpr[rqfar] = rqfpr;
 917         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 918
 919         return rqfar;
 920 }
 921
 922 static void gfar_init_filer_table(struct gfar_private *priv)
 923 {
 924         int i = 0x0;
 925         u32 rqfar = MAX_FILER_IDX;
 926         u32 rqfcr = 0x0;
 927         u32 rqfpr = FPR_FILER_MASK;
 928
 929         /* Default rule */
 930         rqfcr = RQFCR_CMP_MATCH;
 931         priv->ftp_rqfcr[rqfar] = rqfcr;
 932         priv->ftp_rqfpr[rqfar] = rqfpr;
 933         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 934
 935         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 936         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 937         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 938         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 939         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 940         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 941
 942         /* cur_filer_idx indicated the first non-masked rule */
 943         priv->cur_filer_idx = rqfar;
 944
 945         /* Rest are masked rules */
 946         rqfcr = RQFCR_CMP_NOMATCH;
 947         for (i = 0; i < rqfar; i++) {
 948                 priv->ftp_rqfcr[i] = rqfcr;
 949                 priv->ftp_rqfpr[i] = rqfpr;
 950                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 951         }
 952 }
 953
 954 static void gfar_detect_errata(struct gfar_private *priv)
 955 {
 956         struct device *dev = &priv->ofdev->dev;
 957         unsigned int pvr = mfspr(SPRN_PVR);
 958         unsigned int svr = mfspr(SPRN_SVR);
 959         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 960         unsigned int rev = svr & 0xffff;
 961
 962         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 963         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 964             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 965                 priv->errata |= GFAR_ERRATA_74;
 966
 967         /* MPC8313 and MPC837x all rev */
 968         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 969             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 970                 priv->errata |= GFAR_ERRATA_76;
 971
 972         /* MPC8313 and MPC837x all rev */
 973         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 974             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 975                 priv->errata |= GFAR_ERRATA_A002;
 976
 977         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
 978         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
 979             (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
 980                 priv->errata |= GFAR_ERRATA_12;
 981
 982         if (priv->errata)
 983                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 984                          priv->errata);
 985 }
 986
 987 /* Set up the ethernet device structure, private data,
 988  * and anything else we need before we start
 989  */
 990 static int gfar_probe(struct platform_device *ofdev)
 991 {
 992         u32 tempval;
 993         struct net_device *dev = NULL;
 994         struct gfar_private *priv = NULL;
 995         struct gfar __iomem *regs = NULL;
 996         int err = 0, i, grp_idx = 0;
 997         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 998         u32 isrg = 0;
 999         u32 __iomem *baddr;
1000
1001         err = gfar_of_init(ofdev, &dev);
1002
1003         if (err)
1004                 return err;
1005
1006         priv = netdev_priv(dev);
1007         priv->ndev = dev;
1008         priv->ofdev = ofdev;
1009         priv->node = ofdev->dev.of_node;
1010         SET_NETDEV_DEV(dev, &ofdev->dev);
1011
1012         spin_lock_init(&priv->bflock);
1013         INIT_WORK(&priv->reset_task, gfar_reset_task);
1014
1015         dev_set_drvdata(&ofdev->dev, priv);
1016         regs = priv->gfargrp[0].regs;
1017
1018         gfar_detect_errata(priv);
1019
1020         /* Stop the DMA engine now, in case it was running before
1021          * (The firmware could have used it, and left it running).
1022          */
1023         gfar_halt(dev);
1024
1025         /* Reset MAC layer */
1026         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1027
1028         /* We need to delay at least 3 TX clocks */
1029         udelay(2);
1030
1031         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1032         gfar_write(&regs->maccfg1, tempval);
1033
1034         /* Initialize MACCFG2. */
1035         tempval = MACCFG2_INIT_SETTINGS;
1036         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1037                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1038         gfar_write(&regs->maccfg2, tempval);
1039
1040         /* Initialize ECNTRL */
1041         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1042
1043         /* Set the dev->base_addr to the gfar reg region */
1044         dev->base_addr = (unsigned long) regs;
1045
1046         SET_NETDEV_DEV(dev, &ofdev->dev);
1047
1048         /* Fill in the dev structure */
1049         dev->watchdog_timeo = TX_TIMEOUT;
1050         dev->mtu = 1500;
1051         dev->netdev_ops = &gfar_netdev_ops;
1052         dev->ethtool_ops = &gfar_ethtool_ops;
1053
1054         /* Register for napi ...We are registering NAPI for each grp */
1055         for (i = 0; i < priv->num_grps; i++)
1056                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1057                                GFAR_DEV_WEIGHT);
1058
1059         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1060                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1061                                    NETIF_F_RXCSUM;
1062                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1063                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1064         }
1065
1066         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1067                 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1068                 dev->features |= NETIF_F_HW_VLAN_RX;
1069         }
1070
1071         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1072                 priv->extended_hash = 1;
1073                 priv->hash_width = 9;
1074
1075                 priv->hash_regs[0] = &regs->igaddr0;
1076                 priv->hash_regs[1] = &regs->igaddr1;
1077                 priv->hash_regs[2] = &regs->igaddr2;
1078                 priv->hash_regs[3] = &regs->igaddr3;
1079                 priv->hash_regs[4] = &regs->igaddr4;
1080                 priv->hash_regs[5] = &regs->igaddr5;
1081                 priv->hash_regs[6] = &regs->igaddr6;
1082                 priv->hash_regs[7] = &regs->igaddr7;
1083                 priv->hash_regs[8] = &regs->gaddr0;
1084                 priv->hash_regs[9] = &regs->gaddr1;
1085                 priv->hash_regs[10] = &regs->gaddr2;
1086                 priv->hash_regs[11] = &regs->gaddr3;
1087                 priv->hash_regs[12] = &regs->gaddr4;
1088                 priv->hash_regs[13] = &regs->gaddr5;
1089                 priv->hash_regs[14] = &regs->gaddr6;
1090                 priv->hash_regs[15] = &regs->gaddr7;
1091
1092         } else {
1093                 priv->extended_hash = 0;
1094                 priv->hash_width = 8;
1095
1096                 priv->hash_regs[0] = &regs->gaddr0;
1097                 priv->hash_regs[1] = &regs->gaddr1;
1098                 priv->hash_regs[2] = &regs->gaddr2;
1099                 priv->hash_regs[3] = &regs->gaddr3;
1100                 priv->hash_regs[4] = &regs->gaddr4;
1101                 priv->hash_regs[5] = &regs->gaddr5;
1102                 priv->hash_regs[6] = &regs->gaddr6;
1103                 priv->hash_regs[7] = &regs->gaddr7;
1104         }
1105
1106         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1107                 priv->padding = DEFAULT_PADDING;
1108         else
1109                 priv->padding = 0;
1110
1111         if (dev->features & NETIF_F_IP_CSUM ||
1112             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1113                 dev->needed_headroom = GMAC_FCB_LEN;
1114
1115         /* Program the isrg regs only if number of grps > 1 */
1116         if (priv->num_grps > 1) {
1117                 baddr = &regs->isrg0;
1118                 for (i = 0; i < priv->num_grps; i++) {
1119                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1120                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1121                         gfar_write(baddr, isrg);
1122                         baddr++;
1123                         isrg = 0x0;
1124                 }
1125         }
1126
1127         /* Need to reverse the bit maps as  bit_map's MSB is q0
1128          * but, for_each_set_bit parses from right to left, which
1129          * basically reverses the queue numbers
1130          */
1131         for (i = 0; i< priv->num_grps; i++) {
1132                 priv->gfargrp[i].tx_bit_map =
1133                         reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1134                 priv->gfargrp[i].rx_bit_map =
1135                         reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1136         }
1137
1138         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1139          * also assign queues to groups
1140          */
1141         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1142                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1143
1144                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1145                                  priv->num_rx_queues) {
1146                         priv->gfargrp[grp_idx].num_rx_queues++;
1147                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1148                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1149                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1150                 }
1151                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1152
1153                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1154                                  priv->num_tx_queues) {
1155                         priv->gfargrp[grp_idx].num_tx_queues++;
1156                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1157                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1158                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1159                 }
1160                 priv->gfargrp[grp_idx].rstat = rstat;
1161                 priv->gfargrp[grp_idx].tstat = tstat;
1162                 rstat = tstat =0;
1163         }
1164
1165         gfar_write(&regs->rqueue, rqueue);
1166         gfar_write(&regs->tqueue, tqueue);
1167
1168         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1169
1170         /* Initializing some of the rx/tx queue level parameters */
1171         for (i = 0; i < priv->num_tx_queues; i++) {
1172                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1173                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1174                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1175                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1176         }
1177
1178         for (i = 0; i < priv->num_rx_queues; i++) {
1179                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1180                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1181                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1182         }
1183
1184         /* always enable rx filer */
1185         priv->rx_filer_enable = 1;
1186         /* Enable most messages by default */
1187         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1188         /* use pritority h/w tx queue scheduling for single queue devices */
1189         if (priv->num_tx_queues == 1)
1190                 priv->prio_sched_en = 1;
1191
1192         /* Carrier starts down, phylib will bring it up */
1193         netif_carrier_off(dev);
1194
1195         err = register_netdev(dev);
1196
1197         if (err) {
1198                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1199                 goto register_fail;
1200         }
1201
1202         device_init_wakeup(&dev->dev,
1203                            priv->device_flags &
1204                            FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1205
1206         /* fill out IRQ number and name fields */
1207         for (i = 0; i < priv->num_grps; i++) {
1208                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1209                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1210                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1211                                 dev->name, "_g", '0' + i, "_tx");
1212                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1213                                 dev->name, "_g", '0' + i, "_rx");
1214                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1215                                 dev->name, "_g", '0' + i, "_er");
1216                 } else
1217                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1218         }
1219
1220         /* Initialize the filer table */
1221         gfar_init_filer_table(priv);
1222
1223         /* Create all the sysfs files */
1224         gfar_init_sysfs(dev);
1225
1226         /* Print out the device info */
1227         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1228
1229         /* Even more device info helps when determining which kernel
1230          * provided which set of benchmarks.
1231          */
1232         netdev_info(dev, "Running with NAPI enabled\n");
1233         for (i = 0; i < priv->num_rx_queues; i++)
1234                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1235                             i, priv->rx_queue[i]->rx_ring_size);
1236         for (i = 0; i < priv->num_tx_queues; i++)
1237                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1238                             i, priv->tx_queue[i]->tx_ring_size);
1239
1240         return 0;
1241
1242 register_fail:
1243         unmap_group_regs(priv);
1244         free_tx_pointers(priv);
1245         free_rx_pointers(priv);
1246         if (priv->phy_node)
1247                 of_node_put(priv->phy_node);
1248         if (priv->tbi_node)
1249                 of_node_put(priv->tbi_node);
1250         free_gfar_dev(priv);
1251         return err;
1252 }
1253
1254 static int gfar_remove(struct platform_device *ofdev)
1255 {
1256         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1257
1258         if (priv->phy_node)
1259                 of_node_put(priv->phy_node);
1260         if (priv->tbi_node)
1261                 of_node_put(priv->tbi_node);
1262
1263         dev_set_drvdata(&ofdev->dev, NULL);
1264
1265         unregister_netdev(priv->ndev);
1266         unmap_group_regs(priv);
1267         free_gfar_dev(priv);
1268
1269         return 0;
1270 }
1271
1272 #ifdef CONFIG_PM
1273
1274 static int gfar_suspend(struct device *dev)
1275 {
1276         struct gfar_private *priv = dev_get_drvdata(dev);
1277         struct net_device *ndev = priv->ndev;
1278         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1279         unsigned long flags;
1280         u32 tempval;
1281
1282         int magic_packet = priv->wol_en &&
1283                            (priv->device_flags &
1284                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1285
1286         netif_device_detach(ndev);
1287
1288         if (netif_running(ndev)) {
1289
1290                 local_irq_save(flags);
1291                 lock_tx_qs(priv);
1292                 lock_rx_qs(priv);
1293
1294                 gfar_halt_nodisable(ndev);
1295
1296                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1297                 tempval = gfar_read(&regs->maccfg1);
1298
1299                 tempval &= ~MACCFG1_TX_EN;
1300
1301                 if (!magic_packet)
1302                         tempval &= ~MACCFG1_RX_EN;
1303
1304                 gfar_write(&regs->maccfg1, tempval);
1305
1306                 unlock_rx_qs(priv);
1307                 unlock_tx_qs(priv);
1308                 local_irq_restore(flags);
1309
1310                 disable_napi(priv);
1311
1312                 if (magic_packet) {
1313                         /* Enable interrupt on Magic Packet */
1314                         gfar_write(&regs->imask, IMASK_MAG);
1315
1316                         /* Enable Magic Packet mode */
1317                         tempval = gfar_read(&regs->maccfg2);
1318                         tempval |= MACCFG2_MPEN;
1319                         gfar_write(&regs->maccfg2, tempval);
1320                 } else {
1321                         phy_stop(priv->phydev);
1322                 }
1323         }
1324
1325         return 0;
1326 }
1327
1328 static int gfar_resume(struct device *dev)
1329 {
1330         struct gfar_private *priv = dev_get_drvdata(dev);
1331         struct net_device *ndev = priv->ndev;
1332         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1333         unsigned long flags;
1334         u32 tempval;
1335         int magic_packet = priv->wol_en &&
1336                            (priv->device_flags &
1337                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1338
1339         if (!netif_running(ndev)) {
1340                 netif_device_attach(ndev);
1341                 return 0;
1342         }
1343
1344         if (!magic_packet && priv->phydev)
1345                 phy_start(priv->phydev);
1346
1347         /* Disable Magic Packet mode, in case something
1348          * else woke us up.
1349          */
1350         local_irq_save(flags);
1351         lock_tx_qs(priv);
1352         lock_rx_qs(priv);
1353
1354         tempval = gfar_read(&regs->maccfg2);
1355         tempval &= ~MACCFG2_MPEN;
1356         gfar_write(&regs->maccfg2, tempval);
1357
1358         gfar_start(ndev);
1359
1360         unlock_rx_qs(priv);
1361         unlock_tx_qs(priv);
1362         local_irq_restore(flags);
1363
1364         netif_device_attach(ndev);
1365
1366         enable_napi(priv);
1367
1368         return 0;
1369 }
1370
1371 static int gfar_restore(struct device *dev)
1372 {
1373         struct gfar_private *priv = dev_get_drvdata(dev);
1374         struct net_device *ndev = priv->ndev;
1375
1376         if (!netif_running(ndev)) {
1377                 netif_device_attach(ndev);
1378
1379                 return 0;
1380         }
1381
1382         if (gfar_init_bds(ndev)) {
1383                 free_skb_resources(priv);
1384                 return -ENOMEM;
1385         }
1386
1387         init_registers(ndev);
1388         gfar_set_mac_address(ndev);
1389         gfar_init_mac(ndev);
1390         gfar_start(ndev);
1391
1392         priv->oldlink = 0;
1393         priv->oldspeed = 0;
1394         priv->oldduplex = -1;
1395
1396         if (priv->phydev)
1397                 phy_start(priv->phydev);
1398
1399         netif_device_attach(ndev);
1400         enable_napi(priv);
1401
1402         return 0;
1403 }
1404
1405 static struct dev_pm_ops gfar_pm_ops = {
1406         .suspend = gfar_suspend,
1407         .resume = gfar_resume,
1408         .freeze = gfar_suspend,
1409         .thaw = gfar_resume,
1410         .restore = gfar_restore,
1411 };
1412
1413 #define GFAR_PM_OPS (&gfar_pm_ops)
1414
1415 #else
1416
1417 #define GFAR_PM_OPS NULL
1418
1419 #endif
1420
1421 /* Reads the controller's registers to determine what interface
1422  * connects it to the PHY.
1423  */
1424 static phy_interface_t gfar_get_interface(struct net_device *dev)
1425 {
1426         struct gfar_private *priv = netdev_priv(dev);
1427         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1428         u32 ecntrl;
1429
1430         ecntrl = gfar_read(&regs->ecntrl);
1431
1432         if (ecntrl & ECNTRL_SGMII_MODE)
1433                 return PHY_INTERFACE_MODE_SGMII;
1434
1435         if (ecntrl & ECNTRL_TBI_MODE) {
1436                 if (ecntrl & ECNTRL_REDUCED_MODE)
1437                         return PHY_INTERFACE_MODE_RTBI;
1438                 else
1439                         return PHY_INTERFACE_MODE_TBI;
1440         }
1441
1442         if (ecntrl & ECNTRL_REDUCED_MODE) {
1443                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1444                         return PHY_INTERFACE_MODE_RMII;
1445                 }
1446                 else {
1447                         phy_interface_t interface = priv->interface;
1448
1449                         /* This isn't autodetected right now, so it must
1450                          * be set by the device tree or platform code.
1451                          */
1452                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1453                                 return PHY_INTERFACE_MODE_RGMII_ID;
1454
1455                         return PHY_INTERFACE_MODE_RGMII;
1456                 }
1457         }
1458
1459         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1460                 return PHY_INTERFACE_MODE_GMII;
1461
1462         return PHY_INTERFACE_MODE_MII;
1463 }
1464
1465
1466 /* Initializes driver's PHY state, and attaches to the PHY.
1467  * Returns 0 on success.
1468  */
1469 static int init_phy(struct net_device *dev)
1470 {
1471         struct gfar_private *priv = netdev_priv(dev);
1472         uint gigabit_support =
1473                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1474                 SUPPORTED_1000baseT_Full : 0;
1475         phy_interface_t interface;
1476
1477         priv->oldlink = 0;
1478         priv->oldspeed = 0;
1479         priv->oldduplex = -1;
1480
1481         interface = gfar_get_interface(dev);
1482
1483         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1484                                       interface);
1485         if (!priv->phydev)
1486                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1487                                                          interface);
1488         if (!priv->phydev) {
1489                 dev_err(&dev->dev, "could not attach to PHY\n");
1490                 return -ENODEV;
1491         }
1492
1493         if (interface == PHY_INTERFACE_MODE_SGMII)
1494                 gfar_configure_serdes(dev);
1495
1496         /* Remove any features not supported by the controller */
1497         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1498         priv->phydev->advertising = priv->phydev->supported;
1499
1500         return 0;
1501 }
1502
1503 /* Initialize TBI PHY interface for communicating with the
1504  * SERDES lynx PHY on the chip.  We communicate with this PHY
1505  * through the MDIO bus on each controller, treating it as a
1506  * "normal" PHY at the address found in the TBIPA register.  We assume
1507  * that the TBIPA register is valid.  Either the MDIO bus code will set
1508  * it to a value that doesn't conflict with other PHYs on the bus, or the
1509  * value doesn't matter, as there are no other PHYs on the bus.
1510  */
1511 static void gfar_configure_serdes(struct net_device *dev)
1512 {
1513         struct gfar_private *priv = netdev_priv(dev);
1514         struct phy_device *tbiphy;
1515
1516         if (!priv->tbi_node) {
1517                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1518                                     "device tree specify a tbi-handle\n");
1519                 return;
1520         }
1521
1522         tbiphy = of_phy_find_device(priv->tbi_node);
1523         if (!tbiphy) {
1524                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1525                 return;
1526         }
1527
1528         /* If the link is already up, we must already be ok, and don't need to
1529          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1530          * everything for us?  Resetting it takes the link down and requires
1531          * several seconds for it to come back.
1532          */
1533         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1534                 return;
1535
1536         /* Single clk mode, mii mode off(for serdes communication) */
1537         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1538
1539         phy_write(tbiphy, MII_ADVERTISE,
1540                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1541                   ADVERTISE_1000XPSE_ASYM);
1542
1543         phy_write(tbiphy, MII_BMCR,
1544                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1545                   BMCR_SPEED1000);
1546 }
1547
1548 static void init_registers(struct net_device *dev)
1549 {
1550         struct gfar_private *priv = netdev_priv(dev);
1551         struct gfar __iomem *regs = NULL;
1552         int i;
1553
1554         for (i = 0; i < priv->num_grps; i++) {
1555                 regs = priv->gfargrp[i].regs;
1556                 /* Clear IEVENT */
1557                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1558
1559                 /* Initialize IMASK */
1560                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1561         }
1562
1563         regs = priv->gfargrp[0].regs;
1564         /* Init hash registers to zero */
1565         gfar_write(&regs->igaddr0, 0);
1566         gfar_write(&regs->igaddr1, 0);
1567         gfar_write(&regs->igaddr2, 0);
1568         gfar_write(&regs->igaddr3, 0);
1569         gfar_write(&regs->igaddr4, 0);
1570         gfar_write(&regs->igaddr5, 0);
1571         gfar_write(&regs->igaddr6, 0);
1572         gfar_write(&regs->igaddr7, 0);
1573
1574         gfar_write(&regs->gaddr0, 0);
1575         gfar_write(&regs->gaddr1, 0);
1576         gfar_write(&regs->gaddr2, 0);
1577         gfar_write(&regs->gaddr3, 0);
1578         gfar_write(&regs->gaddr4, 0);
1579         gfar_write(&regs->gaddr5, 0);
1580         gfar_write(&regs->gaddr6, 0);
1581         gfar_write(&regs->gaddr7, 0);
1582
1583         /* Zero out the rmon mib registers if it has them */
1584         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1585                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1586
1587                 /* Mask off the CAM interrupts */
1588                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1589                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1590         }
1591
1592         /* Initialize the max receive buffer length */
1593         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1594
1595         /* Initialize the Minimum Frame Length Register */
1596         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1597 }
1598
1599 static int __gfar_is_rx_idle(struct gfar_private *priv)
1600 {
1601         u32 res;
1602
1603         /* Normaly TSEC should not hang on GRS commands, so we should
1604          * actually wait for IEVENT_GRSC flag.
1605          */
1606         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1607                 return 0;
1608
1609         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1610          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1611          * and the Rx can be safely reset.
1612          */
1613         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1614         res &= 0x7f807f80;
1615         if ((res & 0xffff) == (res >> 16))
1616                 return 1;
1617
1618         return 0;
1619 }
1620
1621 /* Halt the receive and transmit queues */
1622 static void gfar_halt_nodisable(struct net_device *dev)
1623 {
1624         struct gfar_private *priv = netdev_priv(dev);
1625         struct gfar __iomem *regs = NULL;
1626         u32 tempval;
1627         int i;
1628
1629         for (i = 0; i < priv->num_grps; i++) {
1630                 regs = priv->gfargrp[i].regs;
1631                 /* Mask all interrupts */
1632                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1633
1634                 /* Clear all interrupts */
1635                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1636         }
1637
1638         regs = priv->gfargrp[0].regs;
1639         /* Stop the DMA, and wait for it to stop */
1640         tempval = gfar_read(&regs->dmactrl);
1641         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1642             (DMACTRL_GRS | DMACTRL_GTS)) {
1643                 int ret;
1644
1645                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1646                 gfar_write(&regs->dmactrl, tempval);
1647
1648                 do {
1649                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1650                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1651                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1652                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1653                                 ret = __gfar_is_rx_idle(priv);
1654                 } while (!ret);
1655         }
1656 }
1657
1658 /* Halt the receive and transmit queues */
1659 void gfar_halt(struct net_device *dev)
1660 {
1661         struct gfar_private *priv = netdev_priv(dev);
1662         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1663         u32 tempval;
1664
1665         gfar_halt_nodisable(dev);
1666
1667         /* Disable Rx and Tx */
1668         tempval = gfar_read(&regs->maccfg1);
1669         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1670         gfar_write(&regs->maccfg1, tempval);
1671 }
1672
1673 static void free_grp_irqs(struct gfar_priv_grp *grp)
1674 {
1675         free_irq(gfar_irq(grp, TX)->irq, grp);
1676         free_irq(gfar_irq(grp, RX)->irq, grp);
1677         free_irq(gfar_irq(grp, ER)->irq, grp);
1678 }
1679
1680 void stop_gfar(struct net_device *dev)
1681 {
1682         struct gfar_private *priv = netdev_priv(dev);
1683         unsigned long flags;
1684         int i;
1685
1686         phy_stop(priv->phydev);
1687
1688
1689         /* Lock it down */
1690         local_irq_save(flags);
1691         lock_tx_qs(priv);
1692         lock_rx_qs(priv);
1693
1694         gfar_halt(dev);
1695
1696         unlock_rx_qs(priv);
1697         unlock_tx_qs(priv);
1698         local_irq_restore(flags);
1699
1700         /* Free the IRQs */
1701         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1702                 for (i = 0; i < priv->num_grps; i++)
1703                         free_grp_irqs(&priv->gfargrp[i]);
1704         } else {
1705                 for (i = 0; i < priv->num_grps; i++)
1706                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1707                                  &priv->gfargrp[i]);
1708         }
1709
1710         free_skb_resources(priv);
1711 }
1712
1713 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1714 {
1715         struct txbd8 *txbdp;
1716         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1717         int i, j;
1718
1719         txbdp = tx_queue->tx_bd_base;
1720
1721         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1722                 if (!tx_queue->tx_skbuff[i])
1723                         continue;
1724
1725                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1726                                  txbdp->length, DMA_TO_DEVICE);
1727                 txbdp->lstatus = 0;
1728                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1729                      j++) {
1730                         txbdp++;
1731                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1732                                        txbdp->length, DMA_TO_DEVICE);
1733                 }
1734                 txbdp++;
1735                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1736                 tx_queue->tx_skbuff[i] = NULL;
1737         }
1738         kfree(tx_queue->tx_skbuff);
1739         tx_queue->tx_skbuff = NULL;
1740 }
1741
1742 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1743 {
1744         struct rxbd8 *rxbdp;
1745         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1746         int i;
1747
1748         rxbdp = rx_queue->rx_bd_base;
1749
1750         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1751                 if (rx_queue->rx_skbuff[i]) {
1752                         dma_unmap_single(&priv->ofdev->dev,
1753                                          rxbdp->bufPtr, priv->rx_buffer_size,
1754                                          DMA_FROM_DEVICE);
1755                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1756                         rx_queue->rx_skbuff[i] = NULL;
1757                 }
1758                 rxbdp->lstatus = 0;
1759                 rxbdp->bufPtr = 0;
1760                 rxbdp++;
1761         }
1762         kfree(rx_queue->rx_skbuff);
1763         rx_queue->rx_skbuff = NULL;
1764 }
1765
1766 /* If there are any tx skbs or rx skbs still around, free them.
1767  * Then free tx_skbuff and rx_skbuff
1768  */
1769 static void free_skb_resources(struct gfar_private *priv)
1770 {
1771         struct gfar_priv_tx_q *tx_queue = NULL;
1772         struct gfar_priv_rx_q *rx_queue = NULL;
1773         int i;
1774
1775         /* Go through all the buffer descriptors and free their data buffers */
1776         for (i = 0; i < priv->num_tx_queues; i++) {
1777                 struct netdev_queue *txq;
1778
1779                 tx_queue = priv->tx_queue[i];
1780                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1781                 if (tx_queue->tx_skbuff)
1782                         free_skb_tx_queue(tx_queue);
1783                 netdev_tx_reset_queue(txq);
1784         }
1785
1786         for (i = 0; i < priv->num_rx_queues; i++) {
1787                 rx_queue = priv->rx_queue[i];
1788                 if (rx_queue->rx_skbuff)
1789                         free_skb_rx_queue(rx_queue);
1790         }
1791
1792         dma_free_coherent(&priv->ofdev->dev,
1793                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1794                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1795                           priv->tx_queue[0]->tx_bd_base,
1796                           priv->tx_queue[0]->tx_bd_dma_base);
1797 }
1798
1799 void gfar_start(struct net_device *dev)
1800 {
1801         struct gfar_private *priv = netdev_priv(dev);
1802         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1803         u32 tempval;
1804         int i = 0;
1805
1806         /* Enable Rx and Tx in MACCFG1 */
1807         tempval = gfar_read(&regs->maccfg1);
1808         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1809         gfar_write(&regs->maccfg1, tempval);
1810
1811         /* Initialize DMACTRL to have WWR and WOP */
1812         tempval = gfar_read(&regs->dmactrl);
1813         tempval |= DMACTRL_INIT_SETTINGS;
1814         gfar_write(&regs->dmactrl, tempval);
1815
1816         /* Make sure we aren't stopped */
1817         tempval = gfar_read(&regs->dmactrl);
1818         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1819         gfar_write(&regs->dmactrl, tempval);
1820
1821         for (i = 0; i < priv->num_grps; i++) {
1822                 regs = priv->gfargrp[i].regs;
1823                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1824                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1825                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1826                 /* Unmask the interrupts we look for */
1827                 gfar_write(&regs->imask, IMASK_DEFAULT);
1828         }
1829
1830         dev->trans_start = jiffies; /* prevent tx timeout */
1831 }
1832
1833 void gfar_configure_coalescing(struct gfar_private *priv,
1834                                unsigned long tx_mask, unsigned long rx_mask)
1835 {
1836         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1837         u32 __iomem *baddr;
1838         int i = 0;
1839
1840         /* Backward compatible case ---- even if we enable
1841          * multiple queues, there's only single reg to program
1842          */
1843         gfar_write(&regs->txic, 0);
1844         if (likely(priv->tx_queue[0]->txcoalescing))
1845                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1846
1847         gfar_write(&regs->rxic, 0);
1848         if (unlikely(priv->rx_queue[0]->rxcoalescing))
1849                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1850
1851         if (priv->mode == MQ_MG_MODE) {
1852                 baddr = &regs->txic0;
1853                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1854                         gfar_write(baddr + i, 0);
1855                         if (likely(priv->tx_queue[i]->txcoalescing))
1856                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1857                 }
1858
1859                 baddr = &regs->rxic0;
1860                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1861                         gfar_write(baddr + i, 0);
1862                         if (likely(priv->rx_queue[i]->rxcoalescing))
1863                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1864                 }
1865         }
1866 }
1867
1868 static int register_grp_irqs(struct gfar_priv_grp *grp)
1869 {
1870         struct gfar_private *priv = grp->priv;
1871         struct net_device *dev = priv->ndev;
1872         int err;
1873
1874         /* If the device has multiple interrupts, register for
1875          * them.  Otherwise, only register for the one
1876          */
1877         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1878                 /* Install our interrupt handlers for Error,
1879                  * Transmit, and Receive
1880                  */
1881                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1882                                   gfar_irq(grp, ER)->name, grp);
1883                 if (err < 0) {
1884                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1885                                   gfar_irq(grp, ER)->irq);
1886
1887                         goto err_irq_fail;
1888                 }
1889                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1890                                   gfar_irq(grp, TX)->name, grp);
1891                 if (err < 0) {
1892                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1893                                   gfar_irq(grp, TX)->irq);
1894                         goto tx_irq_fail;
1895                 }
1896                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1897                                   gfar_irq(grp, RX)->name, grp);
1898                 if (err < 0) {
1899                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1900                                   gfar_irq(grp, RX)->irq);
1901                         goto rx_irq_fail;
1902                 }
1903         } else {
1904                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1905                                   gfar_irq(grp, TX)->name, grp);
1906                 if (err < 0) {
1907                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1908                                   gfar_irq(grp, TX)->irq);
1909                         goto err_irq_fail;
1910                 }
1911         }
1912
1913         return 0;
1914
1915 rx_irq_fail:
1916         free_irq(gfar_irq(grp, TX)->irq, grp);
1917 tx_irq_fail:
1918         free_irq(gfar_irq(grp, ER)->irq, grp);
1919 err_irq_fail:
1920         return err;
1921
1922 }
1923
1924 /* Bring the controller up and running */
1925 int startup_gfar(struct net_device *ndev)
1926 {
1927         struct gfar_private *priv = netdev_priv(ndev);
1928         struct gfar __iomem *regs = NULL;
1929         int err, i, j;
1930
1931         for (i = 0; i < priv->num_grps; i++) {
1932                 regs= priv->gfargrp[i].regs;
1933                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1934         }
1935
1936         regs= priv->gfargrp[0].regs;
1937         err = gfar_alloc_skb_resources(ndev);
1938         if (err)
1939                 return err;
1940
1941         gfar_init_mac(ndev);
1942
1943         for (i = 0; i < priv->num_grps; i++) {
1944                 err = register_grp_irqs(&priv->gfargrp[i]);
1945                 if (err) {
1946                         for (j = 0; j < i; j++)
1947                                 free_grp_irqs(&priv->gfargrp[j]);
1948                         goto irq_fail;
1949                 }
1950         }
1951
1952         /* Start the controller */
1953         gfar_start(ndev);
1954
1955         phy_start(priv->phydev);
1956
1957         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1958
1959         return 0;
1960
1961 irq_fail:
1962         free_skb_resources(priv);
1963         return err;
1964 }
1965
1966 /* Called when something needs to use the ethernet device
1967  * Returns 0 for success.
1968  */
1969 static int gfar_enet_open(struct net_device *dev)
1970 {
1971         struct gfar_private *priv = netdev_priv(dev);
1972         int err;
1973
1974         enable_napi(priv);
1975
1976         /* Initialize a bunch of registers */
1977         init_registers(dev);
1978
1979         gfar_set_mac_address(dev);
1980
1981         err = init_phy(dev);
1982
1983         if (err) {
1984                 disable_napi(priv);
1985                 return err;
1986         }
1987
1988         err = startup_gfar(dev);
1989         if (err) {
1990                 disable_napi(priv);
1991                 return err;
1992         }
1993
1994         netif_tx_start_all_queues(dev);
1995
1996         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1997
1998         return err;
1999 }
2000
2001 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2002 {
2003         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2004
2005         memset(fcb, 0, GMAC_FCB_LEN);
2006
2007         return fcb;
2008 }
2009
2010 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2011                                     int fcb_length)
2012 {
2013         /* If we're here, it's a IP packet with a TCP or UDP
2014          * payload.  We set it to checksum, using a pseudo-header
2015          * we provide
2016          */
2017         u8 flags = TXFCB_DEFAULT;
2018
2019         /* Tell the controller what the protocol is
2020          * And provide the already calculated phcs
2021          */
2022         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2023                 flags |= TXFCB_UDP;
2024                 fcb->phcs = udp_hdr(skb)->check;
2025         } else
2026                 fcb->phcs = tcp_hdr(skb)->check;
2027
2028         /* l3os is the distance between the start of the
2029          * frame (skb->data) and the start of the IP hdr.
2030          * l4os is the distance between the start of the
2031          * l3 hdr and the l4 hdr
2032          */
2033         fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2034         fcb->l4os = skb_network_header_len(skb);
2035
2036         fcb->flags = flags;
2037 }
2038
2039 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2040 {
2041         fcb->flags |= TXFCB_VLN;
2042         fcb->vlctl = vlan_tx_tag_get(skb);
2043 }
2044
2045 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2046                                       struct txbd8 *base, int ring_size)
2047 {
2048         struct txbd8 *new_bd = bdp + stride;
2049
2050         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2051 }
2052
2053 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2054                                       int ring_size)
2055 {
2056         return skip_txbd(bdp, 1, base, ring_size);
2057 }
2058
2059 /* This is called by the kernel when a frame is ready for transmission.
2060  * It is pointed to by the dev->hard_start_xmit function pointer
2061  */
2062 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2063 {
2064         struct gfar_private *priv = netdev_priv(dev);
2065         struct gfar_priv_tx_q *tx_queue = NULL;
2066         struct netdev_queue *txq;
2067         struct gfar __iomem *regs = NULL;
2068         struct txfcb *fcb = NULL;
2069         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2070         u32 lstatus;
2071         int i, rq = 0, do_tstamp = 0;
2072         u32 bufaddr;
2073         unsigned long flags;
2074         unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2075
2076         /* TOE=1 frames larger than 2500 bytes may see excess delays
2077          * before start of transmission.
2078          */
2079         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2080                      skb->ip_summed == CHECKSUM_PARTIAL &&
2081                      skb->len > 2500)) {
2082                 int ret;
2083
2084                 ret = skb_checksum_help(skb);
2085                 if (ret)
2086                         return ret;
2087         }
2088
2089         rq = skb->queue_mapping;
2090         tx_queue = priv->tx_queue[rq];
2091         txq = netdev_get_tx_queue(dev, rq);
2092         base = tx_queue->tx_bd_base;
2093         regs = tx_queue->grp->regs;
2094
2095         /* check if time stamp should be generated */
2096         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2097                      priv->hwts_tx_en)) {
2098                 do_tstamp = 1;
2099                 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2100         }
2101
2102         /* make space for additional header when fcb is needed */
2103         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2104              vlan_tx_tag_present(skb) ||
2105              unlikely(do_tstamp)) &&
2106             (skb_headroom(skb) < fcb_length)) {
2107                 struct sk_buff *skb_new;
2108
2109                 skb_new = skb_realloc_headroom(skb, fcb_length);
2110                 if (!skb_new) {
2111                         dev->stats.tx_errors++;
2112                         kfree_skb(skb);
2113                         return NETDEV_TX_OK;
2114                 }
2115
2116                 if (skb->sk)
2117                         skb_set_owner_w(skb_new, skb->sk);
2118                 consume_skb(skb);
2119                 skb = skb_new;
2120         }
2121
2122         /* total number of fragments in the SKB */
2123         nr_frags = skb_shinfo(skb)->nr_frags;
2124
2125         /* calculate the required number of TxBDs for this skb */
2126         if (unlikely(do_tstamp))
2127                 nr_txbds = nr_frags + 2;
2128         else
2129                 nr_txbds = nr_frags + 1;
2130
2131         /* check if there is space to queue this packet */
2132         if (nr_txbds > tx_queue->num_txbdfree) {
2133                 /* no space, stop the queue */
2134                 netif_tx_stop_queue(txq);
2135                 dev->stats.tx_fifo_errors++;
2136                 return NETDEV_TX_BUSY;
2137         }
2138
2139         /* Update transmit stats */
2140         tx_queue->stats.tx_bytes += skb->len;
2141         tx_queue->stats.tx_packets++;
2142
2143         txbdp = txbdp_start = tx_queue->cur_tx;
2144         lstatus = txbdp->lstatus;
2145
2146         /* Time stamp insertion requires one additional TxBD */
2147         if (unlikely(do_tstamp))
2148                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2149                                                  tx_queue->tx_ring_size);
2150
2151         if (nr_frags == 0) {
2152                 if (unlikely(do_tstamp))
2153                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2154                                                           TXBD_INTERRUPT);
2155                 else
2156                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2157         } else {
2158                 /* Place the fragment addresses and lengths into the TxBDs */
2159                 for (i = 0; i < nr_frags; i++) {
2160                         /* Point at the next BD, wrapping as needed */
2161                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2162
2163                         length = skb_shinfo(skb)->frags[i].size;
2164
2165                         lstatus = txbdp->lstatus | length |
2166                                   BD_LFLAG(TXBD_READY);
2167
2168                         /* Handle the last BD specially */
2169                         if (i == nr_frags - 1)
2170                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2171
2172                         bufaddr = skb_frag_dma_map(&priv->ofdev->dev,
2173                                                    &skb_shinfo(skb)->frags[i],
2174                                                    0,
2175                                                    length,
2176                                                    DMA_TO_DEVICE);
2177
2178                         /* set the TxBD length and buffer pointer */
2179                         txbdp->bufPtr = bufaddr;
2180                         txbdp->lstatus = lstatus;
2181                 }
2182
2183                 lstatus = txbdp_start->lstatus;
2184         }
2185
2186         /* Add TxPAL between FCB and frame if required */
2187         if (unlikely(do_tstamp)) {
2188                 skb_push(skb, GMAC_TXPAL_LEN);
2189                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2190         }
2191
2192         /* Set up checksumming */
2193         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2194                 fcb = gfar_add_fcb(skb);
2195                 /* as specified by errata */
2196                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2197                              ((unsigned long)fcb % 0x20) > 0x18)) {
2198                         __skb_pull(skb, GMAC_FCB_LEN);
2199                         skb_checksum_help(skb);
2200                 } else {
2201                         lstatus |= BD_LFLAG(TXBD_TOE);
2202                         gfar_tx_checksum(skb, fcb, fcb_length);
2203                 }
2204         }
2205
2206         if (vlan_tx_tag_present(skb)) {
2207                 if (unlikely(NULL == fcb)) {
2208                         fcb = gfar_add_fcb(skb);
2209                         lstatus |= BD_LFLAG(TXBD_TOE);
2210                 }
2211
2212                 gfar_tx_vlan(skb, fcb);
2213         }
2214
2215         /* Setup tx hardware time stamping if requested */
2216         if (unlikely(do_tstamp)) {
2217                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2218                 if (fcb == NULL)
2219                         fcb = gfar_add_fcb(skb);
2220                 fcb->ptp = 1;
2221                 lstatus |= BD_LFLAG(TXBD_TOE);
2222         }
2223
2224         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2225                                              skb_headlen(skb), DMA_TO_DEVICE);
2226
2227         /* If time stamping is requested one additional TxBD must be set up. The
2228          * first TxBD points to the FCB and must have a data length of
2229          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2230          * the full frame length.
2231          */
2232         if (unlikely(do_tstamp)) {
2233                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2234                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2235                                          (skb_headlen(skb) - fcb_length);
2236                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2237         } else {
2238                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2239         }
2240
2241         netdev_tx_sent_queue(txq, skb->len);
2242
2243         /* We can work in parallel with gfar_clean_tx_ring(), except
2244          * when modifying num_txbdfree. Note that we didn't grab the lock
2245          * when we were reading the num_txbdfree and checking for available
2246          * space, that's because outside of this function it can only grow,
2247          * and once we've got needed space, it cannot suddenly disappear.
2248          *
2249          * The lock also protects us from gfar_error(), which can modify
2250          * regs->tstat and thus retrigger the transfers, which is why we
2251          * also must grab the lock before setting ready bit for the first
2252          * to be transmitted BD.
2253          */
2254         spin_lock_irqsave(&tx_queue->txlock, flags);
2255
2256         /* The powerpc-specific eieio() is used, as wmb() has too strong
2257          * semantics (it requires synchronization between cacheable and
2258          * uncacheable mappings, which eieio doesn't provide and which we
2259          * don't need), thus requiring a more expensive sync instruction.  At
2260          * some point, the set of architecture-independent barrier functions
2261          * should be expanded to include weaker barriers.
2262          */
2263         eieio();
2264
2265         txbdp_start->lstatus = lstatus;
2266
2267         eieio(); /* force lstatus write before tx_skbuff */
2268
2269         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2270
2271         /* Update the current skb pointer to the next entry we will use
2272          * (wrapping if necessary)
2273          */
2274         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2275                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2276
2277         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2278
2279         /* reduce TxBD free count */
2280         tx_queue->num_txbdfree -= (nr_txbds);
2281
2282         /* If the next BD still needs to be cleaned up, then the bds
2283          * are full.  We need to tell the kernel to stop sending us stuff.
2284          */
2285         if (!tx_queue->num_txbdfree) {
2286                 netif_tx_stop_queue(txq);
2287
2288                 dev->stats.tx_fifo_errors++;
2289         }
2290
2291         /* Tell the DMA to go go go */
2292         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2293
2294         /* Unlock priv */
2295         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2296
2297         return NETDEV_TX_OK;
2298 }
2299
2300 /* Stops the kernel queue, and halts the controller */
2301 static int gfar_close(struct net_device *dev)
2302 {
2303         struct gfar_private *priv = netdev_priv(dev);
2304
2305         disable_napi(priv);
2306
2307         cancel_work_sync(&priv->reset_task);
2308         stop_gfar(dev);
2309
2310         /* Disconnect from the PHY */
2311         phy_disconnect(priv->phydev);
2312         priv->phydev = NULL;
2313
2314         netif_tx_stop_all_queues(dev);
2315
2316         return 0;
2317 }
2318
2319 /* Changes the mac address if the controller is not running. */
2320 static int gfar_set_mac_address(struct net_device *dev)
2321 {
2322         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2323
2324         return 0;
2325 }
2326
2327 /* Check if rx parser should be activated */
2328 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2329 {
2330         struct gfar __iomem *regs;
2331         u32 tempval;
2332
2333         regs = priv->gfargrp[0].regs;
2334
2335         tempval = gfar_read(&regs->rctrl);
2336         /* If parse is no longer required, then disable parser */
2337         if (tempval & RCTRL_REQ_PARSER)
2338                 tempval |= RCTRL_PRSDEP_INIT;
2339         else
2340                 tempval &= ~RCTRL_PRSDEP_INIT;
2341         gfar_write(&regs->rctrl, tempval);
2342 }
2343
2344 /* Enables and disables VLAN insertion/extraction */
2345 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2346 {
2347         struct gfar_private *priv = netdev_priv(dev);
2348         struct gfar __iomem *regs = NULL;
2349         unsigned long flags;
2350         u32 tempval;
2351
2352         regs = priv->gfargrp[0].regs;
2353         local_irq_save(flags);
2354         lock_rx_qs(priv);
2355
2356         if (features & NETIF_F_HW_VLAN_TX) {
2357                 /* Enable VLAN tag insertion */
2358                 tempval = gfar_read(&regs->tctrl);
2359                 tempval |= TCTRL_VLINS;
2360                 gfar_write(&regs->tctrl, tempval);
2361         } else {
2362                 /* Disable VLAN tag insertion */
2363                 tempval = gfar_read(&regs->tctrl);
2364                 tempval &= ~TCTRL_VLINS;
2365                 gfar_write(&regs->tctrl, tempval);
2366         }
2367
2368         if (features & NETIF_F_HW_VLAN_RX) {
2369                 /* Enable VLAN tag extraction */
2370                 tempval = gfar_read(&regs->rctrl);
2371                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2372                 gfar_write(&regs->rctrl, tempval);
2373         } else {
2374                 /* Disable VLAN tag extraction */
2375                 tempval = gfar_read(&regs->rctrl);
2376                 tempval &= ~RCTRL_VLEX;
2377                 gfar_write(&regs->rctrl, tempval);
2378
2379                 gfar_check_rx_parser_mode(priv);
2380         }
2381
2382         gfar_change_mtu(dev, dev->mtu);
2383
2384         unlock_rx_qs(priv);
2385         local_irq_restore(flags);
2386 }
2387
2388 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2389 {
2390         int tempsize, tempval;
2391         struct gfar_private *priv = netdev_priv(dev);
2392         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2393         int oldsize = priv->rx_buffer_size;
2394         int frame_size = new_mtu + ETH_HLEN;
2395
2396         if (gfar_is_vlan_on(priv))
2397                 frame_size += VLAN_HLEN;
2398
2399         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2400                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2401                 return -EINVAL;
2402         }
2403
2404         if (gfar_uses_fcb(priv))
2405                 frame_size += GMAC_FCB_LEN;
2406
2407         frame_size += priv->padding;
2408
2409         tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2410                    INCREMENTAL_BUFFER_SIZE;
2411
2412         /* Only stop and start the controller if it isn't already
2413          * stopped, and we changed something
2414          */
2415         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2416                 stop_gfar(dev);
2417
2418         priv->rx_buffer_size = tempsize;
2419
2420         dev->mtu = new_mtu;
2421
2422         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2423         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2424
2425         /* If the mtu is larger than the max size for standard
2426          * ethernet frames (ie, a jumbo frame), then set maccfg2
2427          * to allow huge frames, and to check the length
2428          */
2429         tempval = gfar_read(&regs->maccfg2);
2430
2431         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2432             gfar_has_errata(priv, GFAR_ERRATA_74))
2433                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2434         else
2435                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2436
2437         gfar_write(&regs->maccfg2, tempval);
2438
2439         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2440                 startup_gfar(dev);
2441
2442         return 0;
2443 }
2444
2445 /* gfar_reset_task gets scheduled when a packet has not been
2446  * transmitted after a set amount of time.
2447  * For now, assume that clearing out all the structures, and
2448  * starting over will fix the problem.
2449  */
2450 static void gfar_reset_task(struct work_struct *work)
2451 {
2452         struct gfar_private *priv = container_of(work, struct gfar_private,
2453                                                  reset_task);
2454         struct net_device *dev = priv->ndev;
2455
2456         if (dev->flags & IFF_UP) {
2457                 netif_tx_stop_all_queues(dev);
2458                 stop_gfar(dev);
2459                 startup_gfar(dev);
2460                 netif_tx_start_all_queues(dev);
2461         }
2462
2463         netif_tx_schedule_all(dev);
2464 }
2465
2466 static void gfar_timeout(struct net_device *dev)
2467 {
2468         struct gfar_private *priv = netdev_priv(dev);
2469
2470         dev->stats.tx_errors++;
2471         schedule_work(&priv->reset_task);
2472 }
2473
2474 static void gfar_align_skb(struct sk_buff *skb)
2475 {
2476         /* We need the data buffer to be aligned properly.  We will reserve
2477          * as many bytes as needed to align the data properly
2478          */
2479         skb_reserve(skb, RXBUF_ALIGNMENT -
2480                     (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2481 }
2482
2483 /* Interrupt Handler for Transmit complete */
2484 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2485 {
2486         struct net_device *dev = tx_queue->dev;
2487         struct netdev_queue *txq;
2488         struct gfar_private *priv = netdev_priv(dev);
2489         struct gfar_priv_rx_q *rx_queue = NULL;
2490         struct txbd8 *bdp, *next = NULL;
2491         struct txbd8 *lbdp = NULL;
2492         struct txbd8 *base = tx_queue->tx_bd_base;
2493         struct sk_buff *skb;
2494         int skb_dirtytx;
2495         int tx_ring_size = tx_queue->tx_ring_size;
2496         int frags = 0, nr_txbds = 0;
2497         int i;
2498         int howmany = 0;
2499         int tqi = tx_queue->qindex;
2500         unsigned int bytes_sent = 0;
2501         u32 lstatus;
2502         size_t buflen;
2503
2504         rx_queue = priv->rx_queue[tqi];
2505         txq = netdev_get_tx_queue(dev, tqi);
2506         bdp = tx_queue->dirty_tx;
2507         skb_dirtytx = tx_queue->skb_dirtytx;
2508
2509         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2510                 unsigned long flags;
2511
2512                 frags = skb_shinfo(skb)->nr_frags;
2513
2514                 /* When time stamping, one additional TxBD must be freed.
2515                  * Also, we need to dma_unmap_single() the TxPAL.
2516                  */
2517                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2518                         nr_txbds = frags + 2;
2519                 else
2520                         nr_txbds = frags + 1;
2521
2522                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2523
2524                 lstatus = lbdp->lstatus;
2525
2526                 /* Only clean completed frames */
2527                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2528                     (lstatus & BD_LENGTH_MASK))
2529                         break;
2530
2531                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2532                         next = next_txbd(bdp, base, tx_ring_size);
2533                         buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2534                 } else
2535                         buflen = bdp->length;
2536
2537                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2538                                  buflen, DMA_TO_DEVICE);
2539
2540                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2541                         struct skb_shared_hwtstamps shhwtstamps;
2542                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2543
2544                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2545                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2546                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2547                         skb_tstamp_tx(skb, &shhwtstamps);
2548                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2549                         bdp = next;
2550                 }
2551
2552                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2553                 bdp = next_txbd(bdp, base, tx_ring_size);
2554
2555                 for (i = 0; i < frags; i++) {
2556                         dma_unmap_page(&priv->ofdev->dev, bdp->bufPtr,
2557                                        bdp->length, DMA_TO_DEVICE);
2558                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2559                         bdp = next_txbd(bdp, base, tx_ring_size);
2560                 }
2561
2562                 bytes_sent += skb->len;
2563
2564                 dev_kfree_skb_any(skb);
2565
2566                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2567
2568                 skb_dirtytx = (skb_dirtytx + 1) &
2569                               TX_RING_MOD_MASK(tx_ring_size);
2570
2571                 howmany++;
2572                 spin_lock_irqsave(&tx_queue->txlock, flags);
2573                 tx_queue->num_txbdfree += nr_txbds;
2574                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2575         }
2576
2577         /* If we freed a buffer, we can restart transmission, if necessary */
2578         if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2579                 netif_wake_subqueue(dev, tqi);
2580
2581         /* Update dirty indicators */
2582         tx_queue->skb_dirtytx = skb_dirtytx;
2583         tx_queue->dirty_tx = bdp;
2584
2585         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2586
2587         return howmany;
2588 }
2589
2590 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2591 {
2592         unsigned long flags;
2593
2594         spin_lock_irqsave(&gfargrp->grplock, flags);
2595         if (napi_schedule_prep(&gfargrp->napi)) {
2596                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2597                 __napi_schedule(&gfargrp->napi);
2598         } else {
2599                 /* Clear IEVENT, so interrupts aren't called again
2600                  * because of the packets that have already arrived.
2601                  */
2602                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2603         }
2604         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2605
2606 }
2607
2608 /* Interrupt Handler for Transmit complete */
2609 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2610 {
2611         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2612         return IRQ_HANDLED;
2613 }
2614
2615 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2616                            struct sk_buff *skb)
2617 {
2618         struct net_device *dev = rx_queue->dev;
2619         struct gfar_private *priv = netdev_priv(dev);
2620         dma_addr_t buf;
2621
2622         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2623                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2624         gfar_init_rxbdp(rx_queue, bdp, buf);
2625 }
2626
2627 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2628 {
2629         struct gfar_private *priv = netdev_priv(dev);
2630         struct sk_buff *skb;
2631
2632         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2633         if (!skb)
2634                 return NULL;
2635
2636         gfar_align_skb(skb);
2637
2638         return skb;
2639 }
2640
2641 struct sk_buff *gfar_new_skb(struct net_device *dev)
2642 {
2643         return gfar_alloc_skb(dev);
2644 }
2645
2646 static inline void count_errors(unsigned short status, struct net_device *dev)
2647 {
2648         struct gfar_private *priv = netdev_priv(dev);
2649         struct net_device_stats *stats = &dev->stats;
2650         struct gfar_extra_stats *estats = &priv->extra_stats;
2651
2652         /* If the packet was truncated, none of the other errors matter */
2653         if (status & RXBD_TRUNCATED) {
2654                 stats->rx_length_errors++;
2655
2656                 estats->rx_trunc++;
2657
2658                 return;
2659         }
2660         /* Count the errors, if there were any */
2661         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2662                 stats->rx_length_errors++;
2663
2664                 if (status & RXBD_LARGE)
2665                         estats->rx_large++;
2666                 else
2667                         estats->rx_short++;
2668         }
2669         if (status & RXBD_NONOCTET) {
2670                 stats->rx_frame_errors++;
2671                 estats->rx_nonoctet++;
2672         }
2673         if (status & RXBD_CRCERR) {
2674                 estats->rx_crcerr++;
2675                 stats->rx_crc_errors++;
2676         }
2677         if (status & RXBD_OVERRUN) {
2678                 estats->rx_overrun++;
2679                 stats->rx_crc_errors++;
2680         }
2681 }
2682
2683 irqreturn_t gfar_receive(int irq, void *grp_id)
2684 {
2685         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2686         return IRQ_HANDLED;
2687 }
2688
2689 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2690 {
2691         /* If valid headers were found, and valid sums
2692          * were verified, then we tell the kernel that no
2693          * checksumming is necessary.  Otherwise, it is [FIXME]
2694          */
2695         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2696                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2697         else
2698                 skb_checksum_none_assert(skb);
2699 }
2700
2701
2702 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2703 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2704                               int amount_pull, struct napi_struct *napi)
2705 {
2706         struct gfar_private *priv = netdev_priv(dev);
2707         struct rxfcb *fcb = NULL;
2708
2709         gro_result_t ret;
2710
2711         /* fcb is at the beginning if exists */
2712         fcb = (struct rxfcb *)skb->data;
2713
2714         /* Remove the FCB from the skb
2715          * Remove the padded bytes, if there are any
2716          */
2717         if (amount_pull) {
2718                 skb_record_rx_queue(skb, fcb->rq);
2719                 skb_pull(skb, amount_pull);
2720         }
2721
2722         /* Get receive timestamp from the skb */
2723         if (priv->hwts_rx_en) {
2724                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2725                 u64 *ns = (u64 *) skb->data;
2726
2727                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2728                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2729         }
2730
2731         if (priv->padding)
2732                 skb_pull(skb, priv->padding);
2733
2734         if (dev->features & NETIF_F_RXCSUM)
2735                 gfar_rx_checksum(skb, fcb);
2736
2737         /* Tell the skb what kind of packet this is */
2738         skb->protocol = eth_type_trans(skb, dev);
2739
2740         /* There's need to check for NETIF_F_HW_VLAN_RX here.
2741          * Even if vlan rx accel is disabled, on some chips
2742          * RXFCB_VLN is pseudo randomly set.
2743          */
2744         if (dev->features & NETIF_F_HW_VLAN_RX &&
2745             fcb->flags & RXFCB_VLN)
2746                 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2747
2748         /* Send the packet up the stack */
2749         ret = napi_gro_receive(napi, skb);
2750
2751         if (GRO_DROP == ret)
2752                 priv->extra_stats.kernel_dropped++;
2753
2754         return 0;
2755 }
2756
2757 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2758  * until the budget/quota has been reached. Returns the number
2759  * of frames handled
2760  */
2761 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2762 {
2763         struct net_device *dev = rx_queue->dev;
2764         struct rxbd8 *bdp, *base;
2765         struct sk_buff *skb;
2766         int pkt_len;
2767         int amount_pull;
2768         int howmany = 0;
2769         struct gfar_private *priv = netdev_priv(dev);
2770
2771         /* Get the first full descriptor */
2772         bdp = rx_queue->cur_rx;
2773         base = rx_queue->rx_bd_base;
2774
2775         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2776
2777         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2778                 struct sk_buff *newskb;
2779
2780                 rmb();
2781
2782                 /* Add another skb for the future */
2783                 newskb = gfar_new_skb(dev);
2784
2785                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2786
2787                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2788                                  priv->rx_buffer_size, DMA_FROM_DEVICE);
2789
2790                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2791                              bdp->length > priv->rx_buffer_size))
2792                         bdp->status = RXBD_LARGE;
2793
2794                 /* We drop the frame if we failed to allocate a new buffer */
2795                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2796                              bdp->status & RXBD_ERR)) {
2797                         count_errors(bdp->status, dev);
2798
2799                         if (unlikely(!newskb))
2800                                 newskb = skb;
2801                         else if (skb)
2802                                 dev_kfree_skb(skb);
2803                 } else {
2804                         /* Increment the number of packets */
2805                         rx_queue->stats.rx_packets++;
2806                         howmany++;
2807
2808                         if (likely(skb)) {
2809                                 pkt_len = bdp->length - ETH_FCS_LEN;
2810                                 /* Remove the FCS from the packet length */
2811                                 skb_put(skb, pkt_len);
2812                                 rx_queue->stats.rx_bytes += pkt_len;
2813                                 skb_record_rx_queue(skb, rx_queue->qindex);
2814                                 gfar_process_frame(dev, skb, amount_pull,
2815                                                    &rx_queue->grp->napi);
2816
2817                         } else {
2818                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2819                                 rx_queue->stats.rx_dropped++;
2820                                 priv->extra_stats.rx_skbmissing++;
2821                         }
2822
2823                 }
2824
2825                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2826
2827                 /* Setup the new bdp */
2828                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2829
2830                 /* Update to the next pointer */
2831                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2832
2833                 /* update to point at the next skb */
2834                 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2835                                       RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2836         }
2837
2838         /* Update the current rxbd pointer to be the next one */
2839         rx_queue->cur_rx = bdp;
2840
2841         return howmany;
2842 }
2843
2844 static int gfar_poll(struct napi_struct *napi, int budget)
2845 {
2846         struct gfar_priv_grp *gfargrp =
2847                 container_of(napi, struct gfar_priv_grp, napi);
2848         struct gfar_private *priv = gfargrp->priv;
2849         struct gfar __iomem *regs = gfargrp->regs;
2850         struct gfar_priv_tx_q *tx_queue = NULL;
2851         struct gfar_priv_rx_q *rx_queue = NULL;
2852         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2853         int tx_cleaned = 0, i, left_over_budget = budget;
2854         unsigned long serviced_queues = 0;
2855         int num_queues = 0;
2856
2857         num_queues = gfargrp->num_rx_queues;
2858         budget_per_queue = budget/num_queues;
2859
2860         /* Clear IEVENT, so interrupts aren't called again
2861          * because of the packets that have already arrived
2862          */
2863         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2864
2865         while (num_queues && left_over_budget) {
2866                 budget_per_queue = left_over_budget/num_queues;
2867                 left_over_budget = 0;
2868
2869                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2870                         if (test_bit(i, &serviced_queues))
2871                                 continue;
2872                         rx_queue = priv->rx_queue[i];
2873                         tx_queue = priv->tx_queue[rx_queue->qindex];
2874
2875                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2876                         rx_cleaned_per_queue =
2877                                 gfar_clean_rx_ring(rx_queue, budget_per_queue);
2878                         rx_cleaned += rx_cleaned_per_queue;
2879                         if (rx_cleaned_per_queue < budget_per_queue) {
2880                                 left_over_budget = left_over_budget +
2881                                         (budget_per_queue -
2882                                          rx_cleaned_per_queue);
2883                                 set_bit(i, &serviced_queues);
2884                                 num_queues--;
2885                         }
2886                 }
2887         }
2888
2889         if (tx_cleaned)
2890                 return budget;
2891
2892         if (rx_cleaned < budget) {
2893                 napi_complete(napi);
2894
2895                 /* Clear the halt bit in RSTAT */
2896                 gfar_write(&regs->rstat, gfargrp->rstat);
2897
2898                 gfar_write(&regs->imask, IMASK_DEFAULT);
2899
2900                 /* If we are coalescing interrupts, update the timer
2901                  * Otherwise, clear it
2902                  */
2903                 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2904                                           gfargrp->tx_bit_map);
2905         }
2906
2907         return rx_cleaned;
2908 }
2909
2910 #ifdef CONFIG_NET_POLL_CONTROLLER
2911 /* Polling 'interrupt' - used by things like netconsole to send skbs
2912  * without having to re-enable interrupts. It's not called while
2913  * the interrupt routine is executing.
2914  */
2915 static void gfar_netpoll(struct net_device *dev)
2916 {
2917         struct gfar_private *priv = netdev_priv(dev);
2918         int i;
2919
2920         /* If the device has multiple interrupts, run tx/rx */
2921         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2922                 for (i = 0; i < priv->num_grps; i++) {
2923                         disable_irq(priv->gfargrp[i].interruptTransmit);
2924                         disable_irq(priv->gfargrp[i].interruptReceive);
2925                         disable_irq(priv->gfargrp[i].interruptError);
2926                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2927                                        &priv->gfargrp[i]);
2928                         enable_irq(priv->gfargrp[i].interruptError);
2929                         enable_irq(priv->gfargrp[i].interruptReceive);
2930                         enable_irq(priv->gfargrp[i].interruptTransmit);
2931                 }
2932         } else {
2933                 for (i = 0; i < priv->num_grps; i++) {
2934                         disable_irq(priv->gfargrp[i].interruptTransmit);
2935                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2936                                        &priv->gfargrp[i]);
2937                         enable_irq(priv->gfargrp[i].interruptTransmit);
2938                 }
2939         }
2940 }
2941 #endif
2942
2943 /* The interrupt handler for devices with one interrupt */
2944 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2945 {
2946         struct gfar_priv_grp *gfargrp = grp_id;
2947
2948         /* Save ievent for future reference */
2949         u32 events = gfar_read(&gfargrp->regs->ievent);
2950
2951         /* Check for reception */
2952         if (events & IEVENT_RX_MASK)
2953                 gfar_receive(irq, grp_id);
2954
2955         /* Check for transmit completion */
2956         if (events & IEVENT_TX_MASK)
2957                 gfar_transmit(irq, grp_id);
2958
2959         /* Check for errors */
2960         if (events & IEVENT_ERR_MASK)
2961                 gfar_error(irq, grp_id);
2962
2963         return IRQ_HANDLED;
2964 }
2965
2966 /* Called every time the controller might need to be made
2967  * aware of new link state.  The PHY code conveys this
2968  * information through variables in the phydev structure, and this
2969  * function converts those variables into the appropriate
2970  * register values, and can bring down the device if needed.
2971  */
2972 static void adjust_link(struct net_device *dev)
2973 {
2974         struct gfar_private *priv = netdev_priv(dev);
2975         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2976         unsigned long flags;
2977         struct phy_device *phydev = priv->phydev;
2978         int new_state = 0;
2979
2980         local_irq_save(flags);
2981         lock_tx_qs(priv);
2982
2983         if (phydev->link) {
2984                 u32 tempval = gfar_read(&regs->maccfg2);
2985                 u32 ecntrl = gfar_read(&regs->ecntrl);
2986
2987                 /* Now we make sure that we can be in full duplex mode.
2988                  * If not, we operate in half-duplex mode.
2989                  */
2990                 if (phydev->duplex != priv->oldduplex) {
2991                         new_state = 1;
2992                         if (!(phydev->duplex))
2993                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2994                         else
2995                                 tempval |= MACCFG2_FULL_DUPLEX;
2996
2997                         priv->oldduplex = phydev->duplex;
2998                 }
2999
3000                 if (phydev->speed != priv->oldspeed) {
3001                         new_state = 1;
3002                         switch (phydev->speed) {
3003                         case 1000:
3004                                 tempval =
3005                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3006
3007                                 ecntrl &= ~(ECNTRL_R100);
3008                                 break;
3009                         case 100:
3010                         case 10:
3011                                 tempval =
3012                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3013
3014                                 /* Reduced mode distinguishes
3015                                  * between 10 and 100
3016                                  */
3017                                 if (phydev->speed == SPEED_100)
3018                                         ecntrl |= ECNTRL_R100;
3019                                 else
3020                                         ecntrl &= ~(ECNTRL_R100);
3021                                 break;
3022                         default:
3023                                 netif_warn(priv, link, dev,
3024                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3025                                            phydev->speed);
3026                                 break;
3027                         }
3028
3029                         priv->oldspeed = phydev->speed;
3030                 }
3031
3032                 gfar_write(&regs->maccfg2, tempval);
3033                 gfar_write(&regs->ecntrl, ecntrl);
3034
3035                 if (!priv->oldlink) {
3036                         new_state = 1;
3037                         priv->oldlink = 1;
3038                 }
3039         } else if (priv->oldlink) {
3040                 new_state = 1;
3041                 priv->oldlink = 0;
3042                 priv->oldspeed = 0;
3043                 priv->oldduplex = -1;
3044         }
3045
3046         if (new_state && netif_msg_link(priv))
3047                 phy_print_status(phydev);
3048         unlock_tx_qs(priv);
3049         local_irq_restore(flags);
3050 }
3051
3052 /* Update the hash table based on the current list of multicast
3053  * addresses we subscribe to.  Also, change the promiscuity of
3054  * the device based on the flags (this function is called
3055  * whenever dev->flags is changed
3056  */
3057 static void gfar_set_multi(struct net_device *dev)
3058 {
3059         struct netdev_hw_addr *ha;
3060         struct gfar_private *priv = netdev_priv(dev);
3061         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3062         u32 tempval;
3063
3064         if (dev->flags & IFF_PROMISC) {
3065                 /* Set RCTRL to PROM */
3066                 tempval = gfar_read(&regs->rctrl);
3067                 tempval |= RCTRL_PROM;
3068                 gfar_write(&regs->rctrl, tempval);
3069         } else {
3070                 /* Set RCTRL to not PROM */
3071                 tempval = gfar_read(&regs->rctrl);
3072                 tempval &= ~(RCTRL_PROM);
3073                 gfar_write(&regs->rctrl, tempval);
3074         }
3075
3076         if (dev->flags & IFF_ALLMULTI) {
3077                 /* Set the hash to rx all multicast frames */
3078                 gfar_write(&regs->igaddr0, 0xffffffff);
3079                 gfar_write(&regs->igaddr1, 0xffffffff);
3080                 gfar_write(&regs->igaddr2, 0xffffffff);
3081                 gfar_write(&regs->igaddr3, 0xffffffff);
3082                 gfar_write(&regs->igaddr4, 0xffffffff);
3083                 gfar_write(&regs->igaddr5, 0xffffffff);
3084                 gfar_write(&regs->igaddr6, 0xffffffff);
3085                 gfar_write(&regs->igaddr7, 0xffffffff);
3086                 gfar_write(&regs->gaddr0, 0xffffffff);
3087                 gfar_write(&regs->gaddr1, 0xffffffff);
3088                 gfar_write(&regs->gaddr2, 0xffffffff);
3089                 gfar_write(&regs->gaddr3, 0xffffffff);
3090                 gfar_write(&regs->gaddr4, 0xffffffff);
3091                 gfar_write(&regs->gaddr5, 0xffffffff);
3092                 gfar_write(&regs->gaddr6, 0xffffffff);
3093                 gfar_write(&regs->gaddr7, 0xffffffff);
3094         } else {
3095                 int em_num;
3096                 int idx;
3097
3098                 /* zero out the hash */
3099                 gfar_write(&regs->igaddr0, 0x0);
3100                 gfar_write(&regs->igaddr1, 0x0);
3101                 gfar_write(&regs->igaddr2, 0x0);
3102                 gfar_write(&regs->igaddr3, 0x0);
3103                 gfar_write(&regs->igaddr4, 0x0);
3104                 gfar_write(&regs->igaddr5, 0x0);
3105                 gfar_write(&regs->igaddr6, 0x0);
3106                 gfar_write(&regs->igaddr7, 0x0);
3107                 gfar_write(&regs->gaddr0, 0x0);
3108                 gfar_write(&regs->gaddr1, 0x0);
3109                 gfar_write(&regs->gaddr2, 0x0);
3110                 gfar_write(&regs->gaddr3, 0x0);
3111                 gfar_write(&regs->gaddr4, 0x0);
3112                 gfar_write(&regs->gaddr5, 0x0);
3113                 gfar_write(&regs->gaddr6, 0x0);
3114                 gfar_write(&regs->gaddr7, 0x0);
3115
3116                 /* If we have extended hash tables, we need to
3117                  * clear the exact match registers to prepare for
3118                  * setting them
3119                  */
3120                 if (priv->extended_hash) {
3121                         em_num = GFAR_EM_NUM + 1;
3122                         gfar_clear_exact_match(dev);
3123                         idx = 1;
3124                 } else {
3125                         idx = 0;
3126                         em_num = 0;
3127                 }
3128
3129                 if (netdev_mc_empty(dev))
3130                         return;
3131
3132                 /* Parse the list, and set the appropriate bits */
3133                 netdev_for_each_mc_addr(ha, dev) {
3134                         if (idx < em_num) {
3135                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3136                                 idx++;
3137                         } else
3138                                 gfar_set_hash_for_addr(dev, ha->addr);
3139                 }
3140         }
3141 }
3142
3143
3144 /* Clears each of the exact match registers to zero, so they
3145  * don't interfere with normal reception
3146  */
3147 static void gfar_clear_exact_match(struct net_device *dev)
3148 {
3149         int idx;
3150         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3151
3152         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3153                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3154 }
3155
3156 /* Set the appropriate hash bit for the given addr */
3157 /* The algorithm works like so:
3158  * 1) Take the Destination Address (ie the multicast address), and
3159  * do a CRC on it (little endian), and reverse the bits of the
3160  * result.
3161  * 2) Use the 8 most significant bits as a hash into a 256-entry
3162  * table.  The table is controlled through 8 32-bit registers:
3163  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3164  * gaddr7.  This means that the 3 most significant bits in the
3165  * hash index which gaddr register to use, and the 5 other bits
3166  * indicate which bit (assuming an IBM numbering scheme, which
3167  * for PowerPC (tm) is usually the case) in the register holds
3168  * the entry.
3169  */
3170 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3171 {
3172         u32 tempval;
3173         struct gfar_private *priv = netdev_priv(dev);
3174         u32 result = ether_crc(ETH_ALEN, addr);
3175         int width = priv->hash_width;
3176         u8 whichbit = (result >> (32 - width)) & 0x1f;
3177         u8 whichreg = result >> (32 - width + 5);
3178         u32 value = (1 << (31-whichbit));
3179
3180         tempval = gfar_read(priv->hash_regs[whichreg]);
3181         tempval |= value;
3182         gfar_write(priv->hash_regs[whichreg], tempval);
3183 }
3184
3185
3186 /* There are multiple MAC Address register pairs on some controllers
3187  * This function sets the numth pair to a given address
3188  */
3189 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3190                                   const u8 *addr)
3191 {
3192         struct gfar_private *priv = netdev_priv(dev);
3193         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3194         int idx;
3195         char tmpbuf[ETH_ALEN];
3196         u32 tempval;
3197         u32 __iomem *macptr = &regs->macstnaddr1;
3198
3199         macptr += num*2;
3200
3201         /* Now copy it into the mac registers backwards, cuz
3202          * little endian is silly
3203          */
3204         for (idx = 0; idx < ETH_ALEN; idx++)
3205                 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3206
3207         gfar_write(macptr, *((u32 *) (tmpbuf)));
3208
3209         tempval = *((u32 *) (tmpbuf + 4));
3210
3211         gfar_write(macptr+1, tempval);
3212 }
3213
3214 /* GFAR error interrupt handler */
3215 static irqreturn_t gfar_error(int irq, void *grp_id)
3216 {
3217         struct gfar_priv_grp *gfargrp = grp_id;
3218         struct gfar __iomem *regs = gfargrp->regs;
3219         struct gfar_private *priv= gfargrp->priv;
3220         struct net_device *dev = priv->ndev;
3221
3222         /* Save ievent for future reference */
3223         u32 events = gfar_read(&regs->ievent);
3224
3225         /* Clear IEVENT */
3226         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3227
3228         /* Magic Packet is not an error. */
3229         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3230             (events & IEVENT_MAG))
3231                 events &= ~IEVENT_MAG;
3232
3233         /* Hmm... */
3234         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3235                 netdev_dbg(dev,
3236                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3237                            events, gfar_read(&regs->imask));
3238
3239         /* Update the error counters */
3240         if (events & IEVENT_TXE) {
3241                 dev->stats.tx_errors++;
3242
3243                 if (events & IEVENT_LC)
3244                         dev->stats.tx_window_errors++;
3245                 if (events & IEVENT_CRL)
3246                         dev->stats.tx_aborted_errors++;
3247                 if (events & IEVENT_XFUN) {
3248                         unsigned long flags;
3249
3250                         netif_dbg(priv, tx_err, dev,
3251                                   "TX FIFO underrun, packet dropped\n");
3252                         dev->stats.tx_dropped++;
3253                         priv->extra_stats.tx_underrun++;
3254
3255                         local_irq_save(flags);
3256                         lock_tx_qs(priv);
3257
3258                         /* Reactivate the Tx Queues */
3259                         gfar_write(&regs->tstat, gfargrp->tstat);
3260
3261                         unlock_tx_qs(priv);
3262                         local_irq_restore(flags);
3263                 }
3264                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3265         }
3266         if (events & IEVENT_BSY) {
3267                 dev->stats.rx_errors++;
3268                 priv->extra_stats.rx_bsy++;
3269
3270                 gfar_receive(irq, grp_id);
3271
3272                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3273                           gfar_read(&regs->rstat));
3274         }
3275         if (events & IEVENT_BABR) {
3276                 dev->stats.rx_errors++;
3277                 priv->extra_stats.rx_babr++;
3278
3279                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3280         }
3281         if (events & IEVENT_EBERR) {
3282                 priv->extra_stats.eberr++;
3283                 netif_dbg(priv, rx_err, dev, "bus error\n");
3284         }
3285         if (events & IEVENT_RXC)
3286                 netif_dbg(priv, rx_status, dev, "control frame\n");
3287
3288         if (events & IEVENT_BABT) {
3289                 priv->extra_stats.tx_babt++;
3290                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3291         }
3292         return IRQ_HANDLED;
3293 }
3294
3295 static struct of_device_id gfar_match[] =
3296 {
3297         {
3298                 .type = "network",
3299                 .compatible = "gianfar",
3300         },
3301         {
3302                 .compatible = "fsl,etsec2",
3303         },
3304         {},
3305 };
3306 MODULE_DEVICE_TABLE(of, gfar_match);
3307
3308 /* Structure for a device driver */
3309 static struct platform_driver gfar_driver = {
3310         .driver = {
3311                 .name = "fsl-gianfar",
3312                 .owner = THIS_MODULE,
3313                 .pm = GFAR_PM_OPS,
3314                 .of_match_table = gfar_match,
3315         },
3316         .probe = gfar_probe,
3317         .remove = gfar_remove,
3318 };
3319
3320 module_platform_driver(gfar_driver);