1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
81 #include <linux/of_mdio.h>
82 #include <linux/of_platform.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
87 #include <linux/net_tstamp.h>
92 #include <asm/uaccess.h>
93 #include <linux/module.h>
94 #include <linux/dma-mapping.h>
95 #include <linux/crc32.h>
96 #include <linux/mii.h>
97 #include <linux/phy.h>
98 #include <linux/phy_fixed.h>
100 #include <linux/of_net.h>
104 #define TX_TIMEOUT (1*HZ)
106 const char gfar_driver_version[] = "1.3";
108 static int gfar_enet_open(struct net_device *dev);
109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
110 static void gfar_reset_task(struct work_struct *work);
111 static void gfar_timeout(struct net_device *dev);
112 static int gfar_close(struct net_device *dev);
113 struct sk_buff *gfar_new_skb(struct net_device *dev);
114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
115 struct sk_buff *skb);
116 static int gfar_set_mac_address(struct net_device *dev);
117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
118 static irqreturn_t gfar_error(int irq, void *dev_id);
119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
121 static void adjust_link(struct net_device *dev);
122 static void init_registers(struct net_device *dev);
123 static int init_phy(struct net_device *dev);
124 static int gfar_probe(struct platform_device *ofdev);
125 static int gfar_remove(struct platform_device *ofdev);
126 static void free_skb_resources(struct gfar_private *priv);
127 static void gfar_set_multi(struct net_device *dev);
128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
129 static void gfar_configure_serdes(struct net_device *dev);
130 static int gfar_poll(struct napi_struct *napi, int budget);
131 #ifdef CONFIG_NET_POLL_CONTROLLER
132 static void gfar_netpoll(struct net_device *dev);
134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
135 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
136 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137 int amount_pull, struct napi_struct *napi);
138 void gfar_halt(struct net_device *dev);
139 static void gfar_halt_nodisable(struct net_device *dev);
140 void gfar_start(struct net_device *dev);
141 static void gfar_clear_exact_match(struct net_device *dev);
142 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
157 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
158 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
159 lstatus |= BD_LFLAG(RXBD_WRAP);
163 bdp->lstatus = lstatus;
166 static int gfar_init_bds(struct net_device *ndev)
168 struct gfar_private *priv = netdev_priv(ndev);
169 struct gfar_priv_tx_q *tx_queue = NULL;
170 struct gfar_priv_rx_q *rx_queue = NULL;
175 for (i = 0; i < priv->num_tx_queues; i++) {
176 tx_queue = priv->tx_queue[i];
177 /* Initialize some variables in our dev structure */
178 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
179 tx_queue->dirty_tx = tx_queue->tx_bd_base;
180 tx_queue->cur_tx = tx_queue->tx_bd_base;
181 tx_queue->skb_curtx = 0;
182 tx_queue->skb_dirtytx = 0;
184 /* Initialize Transmit Descriptor Ring */
185 txbdp = tx_queue->tx_bd_base;
186 for (j = 0; j < tx_queue->tx_ring_size; j++) {
192 /* Set the last descriptor in the ring to indicate wrap */
194 txbdp->status |= TXBD_WRAP;
197 for (i = 0; i < priv->num_rx_queues; i++) {
198 rx_queue = priv->rx_queue[i];
199 rx_queue->cur_rx = rx_queue->rx_bd_base;
200 rx_queue->skb_currx = 0;
201 rxbdp = rx_queue->rx_bd_base;
203 for (j = 0; j < rx_queue->rx_ring_size; j++) {
204 struct sk_buff *skb = rx_queue->rx_skbuff[j];
207 gfar_init_rxbdp(rx_queue, rxbdp,
210 skb = gfar_new_skb(ndev);
212 netdev_err(ndev, "Can't allocate RX buffers\n");
215 rx_queue->rx_skbuff[j] = skb;
217 gfar_new_rxbdp(rx_queue, rxbdp, skb);
228 static int gfar_alloc_skb_resources(struct net_device *ndev)
233 struct gfar_private *priv = netdev_priv(ndev);
234 struct device *dev = priv->dev;
235 struct gfar_priv_tx_q *tx_queue = NULL;
236 struct gfar_priv_rx_q *rx_queue = NULL;
238 priv->total_tx_ring_size = 0;
239 for (i = 0; i < priv->num_tx_queues; i++)
240 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
242 priv->total_rx_ring_size = 0;
243 for (i = 0; i < priv->num_rx_queues; i++)
244 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
246 /* Allocate memory for the buffer descriptors */
247 vaddr = dma_alloc_coherent(dev,
248 (priv->total_tx_ring_size *
249 sizeof(struct txbd8)) +
250 (priv->total_rx_ring_size *
251 sizeof(struct rxbd8)),
256 for (i = 0; i < priv->num_tx_queues; i++) {
257 tx_queue = priv->tx_queue[i];
258 tx_queue->tx_bd_base = vaddr;
259 tx_queue->tx_bd_dma_base = addr;
260 tx_queue->dev = ndev;
261 /* enet DMA only understands physical addresses */
262 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
263 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
266 /* Start the rx descriptor ring where the tx ring leaves off */
267 for (i = 0; i < priv->num_rx_queues; i++) {
268 rx_queue = priv->rx_queue[i];
269 rx_queue->rx_bd_base = vaddr;
270 rx_queue->rx_bd_dma_base = addr;
271 rx_queue->dev = ndev;
272 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
273 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
276 /* Setup the skbuff rings */
277 for (i = 0; i < priv->num_tx_queues; i++) {
278 tx_queue = priv->tx_queue[i];
279 tx_queue->tx_skbuff =
280 kmalloc_array(tx_queue->tx_ring_size,
281 sizeof(*tx_queue->tx_skbuff),
283 if (!tx_queue->tx_skbuff)
286 for (k = 0; k < tx_queue->tx_ring_size; k++)
287 tx_queue->tx_skbuff[k] = NULL;
290 for (i = 0; i < priv->num_rx_queues; i++) {
291 rx_queue = priv->rx_queue[i];
292 rx_queue->rx_skbuff =
293 kmalloc_array(rx_queue->rx_ring_size,
294 sizeof(*rx_queue->rx_skbuff),
296 if (!rx_queue->rx_skbuff)
299 for (j = 0; j < rx_queue->rx_ring_size; j++)
300 rx_queue->rx_skbuff[j] = NULL;
303 if (gfar_init_bds(ndev))
309 free_skb_resources(priv);
313 static void gfar_init_tx_rx_base(struct gfar_private *priv)
315 struct gfar __iomem *regs = priv->gfargrp[0].regs;
319 baddr = ®s->tbase0;
320 for (i = 0; i < priv->num_tx_queues; i++) {
321 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
325 baddr = ®s->rbase0;
326 for (i = 0; i < priv->num_rx_queues; i++) {
327 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
332 static void gfar_init_mac(struct net_device *ndev)
334 struct gfar_private *priv = netdev_priv(ndev);
335 struct gfar __iomem *regs = priv->gfargrp[0].regs;
340 /* write the tx/rx base registers */
341 gfar_init_tx_rx_base(priv);
343 /* Configure the coalescing support */
344 gfar_configure_coalescing_all(priv);
346 /* set this when rx hw offload (TOE) functions are being used */
347 priv->uses_rxfcb = 0;
349 if (priv->rx_filer_enable) {
350 rctrl |= RCTRL_FILREN;
351 /* Program the RIR0 reg with the required distribution */
352 gfar_write(®s->rir0, DEFAULT_RIR0);
355 /* Restore PROMISC mode */
356 if (ndev->flags & IFF_PROMISC)
359 if (ndev->features & NETIF_F_RXCSUM) {
360 rctrl |= RCTRL_CHECKSUMMING;
361 priv->uses_rxfcb = 1;
364 if (priv->extended_hash) {
365 rctrl |= RCTRL_EXTHASH;
367 gfar_clear_exact_match(ndev);
372 rctrl &= ~RCTRL_PAL_MASK;
373 rctrl |= RCTRL_PADDING(priv->padding);
376 /* Insert receive time stamps into padding alignment bytes */
377 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
378 rctrl &= ~RCTRL_PAL_MASK;
379 rctrl |= RCTRL_PADDING(8);
383 /* Enable HW time stamping if requested from user space */
384 if (priv->hwts_rx_en) {
385 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
386 priv->uses_rxfcb = 1;
389 if (ndev->features & NETIF_F_HW_VLAN_RX) {
390 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
391 priv->uses_rxfcb = 1;
394 /* Init rctrl based on our settings */
395 gfar_write(®s->rctrl, rctrl);
397 if (ndev->features & NETIF_F_IP_CSUM)
398 tctrl |= TCTRL_INIT_CSUM;
400 if (priv->prio_sched_en)
401 tctrl |= TCTRL_TXSCHED_PRIO;
403 tctrl |= TCTRL_TXSCHED_WRRS;
404 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
405 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
408 gfar_write(®s->tctrl, tctrl);
410 /* Set the extraction length and index */
411 attrs = ATTRELI_EL(priv->rx_stash_size) |
412 ATTRELI_EI(priv->rx_stash_index);
414 gfar_write(®s->attreli, attrs);
416 /* Start with defaults, and add stashing or locking
417 * depending on the approprate variables
419 attrs = ATTR_INIT_SETTINGS;
421 if (priv->bd_stash_en)
422 attrs |= ATTR_BDSTASH;
424 if (priv->rx_stash_size != 0)
425 attrs |= ATTR_BUFSTASH;
427 gfar_write(®s->attr, attrs);
429 gfar_write(®s->fifo_tx_thr, priv->fifo_threshold);
430 gfar_write(®s->fifo_tx_starve, priv->fifo_starve);
431 gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off);
434 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
436 struct gfar_private *priv = netdev_priv(dev);
437 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
438 unsigned long tx_packets = 0, tx_bytes = 0;
441 for (i = 0; i < priv->num_rx_queues; i++) {
442 rx_packets += priv->rx_queue[i]->stats.rx_packets;
443 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
444 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
447 dev->stats.rx_packets = rx_packets;
448 dev->stats.rx_bytes = rx_bytes;
449 dev->stats.rx_dropped = rx_dropped;
451 for (i = 0; i < priv->num_tx_queues; i++) {
452 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
453 tx_packets += priv->tx_queue[i]->stats.tx_packets;
456 dev->stats.tx_bytes = tx_bytes;
457 dev->stats.tx_packets = tx_packets;
462 static const struct net_device_ops gfar_netdev_ops = {
463 .ndo_open = gfar_enet_open,
464 .ndo_start_xmit = gfar_start_xmit,
465 .ndo_stop = gfar_close,
466 .ndo_change_mtu = gfar_change_mtu,
467 .ndo_set_features = gfar_set_features,
468 .ndo_set_rx_mode = gfar_set_multi,
469 .ndo_tx_timeout = gfar_timeout,
470 .ndo_do_ioctl = gfar_ioctl,
471 .ndo_get_stats = gfar_get_stats,
472 .ndo_set_mac_address = eth_mac_addr,
473 .ndo_validate_addr = eth_validate_addr,
474 #ifdef CONFIG_NET_POLL_CONTROLLER
475 .ndo_poll_controller = gfar_netpoll,
479 void lock_rx_qs(struct gfar_private *priv)
483 for (i = 0; i < priv->num_rx_queues; i++)
484 spin_lock(&priv->rx_queue[i]->rxlock);
487 void lock_tx_qs(struct gfar_private *priv)
491 for (i = 0; i < priv->num_tx_queues; i++)
492 spin_lock(&priv->tx_queue[i]->txlock);
495 void unlock_rx_qs(struct gfar_private *priv)
499 for (i = 0; i < priv->num_rx_queues; i++)
500 spin_unlock(&priv->rx_queue[i]->rxlock);
503 void unlock_tx_qs(struct gfar_private *priv)
507 for (i = 0; i < priv->num_tx_queues; i++)
508 spin_unlock(&priv->tx_queue[i]->txlock);
511 static void free_tx_pointers(struct gfar_private *priv)
515 for (i = 0; i < priv->num_tx_queues; i++)
516 kfree(priv->tx_queue[i]);
519 static void free_rx_pointers(struct gfar_private *priv)
523 for (i = 0; i < priv->num_rx_queues; i++)
524 kfree(priv->rx_queue[i]);
527 static void unmap_group_regs(struct gfar_private *priv)
531 for (i = 0; i < MAXGROUPS; i++)
532 if (priv->gfargrp[i].regs)
533 iounmap(priv->gfargrp[i].regs);
536 static void free_gfar_dev(struct gfar_private *priv)
540 for (i = 0; i < priv->num_grps; i++)
541 for (j = 0; j < GFAR_NUM_IRQS; j++) {
542 kfree(priv->gfargrp[i].irqinfo[j]);
543 priv->gfargrp[i].irqinfo[j] = NULL;
546 free_netdev(priv->ndev);
549 static void disable_napi(struct gfar_private *priv)
553 for (i = 0; i < priv->num_grps; i++)
554 napi_disable(&priv->gfargrp[i].napi);
557 static void enable_napi(struct gfar_private *priv)
561 for (i = 0; i < priv->num_grps; i++)
562 napi_enable(&priv->gfargrp[i].napi);
565 static int gfar_parse_group(struct device_node *np,
566 struct gfar_private *priv, const char *model)
568 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
572 for (i = 0; i < GFAR_NUM_IRQS; i++) {
573 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
575 if (!grp->irqinfo[i])
579 grp->regs = of_iomap(np, 0);
583 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
585 /* If we aren't the FEC we have multiple interrupts */
586 if (model && strcasecmp(model, "FEC")) {
587 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
588 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
589 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
590 gfar_irq(grp, RX)->irq == NO_IRQ ||
591 gfar_irq(grp, ER)->irq == NO_IRQ)
595 grp->grp_id = priv->num_grps;
597 spin_lock_init(&grp->grplock);
598 if (priv->mode == MQ_MG_MODE) {
599 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
600 grp->rx_bit_map = queue_mask ?
601 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
602 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
603 grp->tx_bit_map = queue_mask ?
604 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
606 grp->rx_bit_map = 0xFF;
607 grp->tx_bit_map = 0xFF;
614 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
618 const void *mac_addr;
620 struct net_device *dev = NULL;
621 struct gfar_private *priv = NULL;
622 struct device_node *np = ofdev->dev.of_node;
623 struct device_node *child = NULL;
625 const u32 *stash_len;
626 const u32 *stash_idx;
627 unsigned int num_tx_qs, num_rx_qs;
628 u32 *tx_queues, *rx_queues;
630 if (!np || !of_device_is_available(np))
633 /* parse the num of tx and rx queues */
634 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
635 num_tx_qs = tx_queues ? *tx_queues : 1;
637 if (num_tx_qs > MAX_TX_QS) {
638 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
639 num_tx_qs, MAX_TX_QS);
640 pr_err("Cannot do alloc_etherdev, aborting\n");
644 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
645 num_rx_qs = rx_queues ? *rx_queues : 1;
647 if (num_rx_qs > MAX_RX_QS) {
648 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
649 num_rx_qs, MAX_RX_QS);
650 pr_err("Cannot do alloc_etherdev, aborting\n");
654 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
659 priv = netdev_priv(dev);
662 priv->num_tx_queues = num_tx_qs;
663 netif_set_real_num_rx_queues(dev, num_rx_qs);
664 priv->num_rx_queues = num_rx_qs;
665 priv->num_grps = 0x0;
667 /* Init Rx queue filer rule set linked list */
668 INIT_LIST_HEAD(&priv->rx_list.list);
669 priv->rx_list.count = 0;
670 mutex_init(&priv->rx_queue_access);
672 model = of_get_property(np, "model", NULL);
674 for (i = 0; i < MAXGROUPS; i++)
675 priv->gfargrp[i].regs = NULL;
677 /* Parse and initialize group specific information */
678 if (of_device_is_compatible(np, "fsl,etsec2")) {
679 priv->mode = MQ_MG_MODE;
680 for_each_child_of_node(np, child) {
681 err = gfar_parse_group(child, priv, model);
686 priv->mode = SQ_SG_MODE;
687 err = gfar_parse_group(np, priv, model);
692 for (i = 0; i < priv->num_tx_queues; i++)
693 priv->tx_queue[i] = NULL;
694 for (i = 0; i < priv->num_rx_queues; i++)
695 priv->rx_queue[i] = NULL;
697 for (i = 0; i < priv->num_tx_queues; i++) {
698 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
700 if (!priv->tx_queue[i]) {
702 goto tx_alloc_failed;
704 priv->tx_queue[i]->tx_skbuff = NULL;
705 priv->tx_queue[i]->qindex = i;
706 priv->tx_queue[i]->dev = dev;
707 spin_lock_init(&(priv->tx_queue[i]->txlock));
710 for (i = 0; i < priv->num_rx_queues; i++) {
711 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
713 if (!priv->rx_queue[i]) {
715 goto rx_alloc_failed;
717 priv->rx_queue[i]->rx_skbuff = NULL;
718 priv->rx_queue[i]->qindex = i;
719 priv->rx_queue[i]->dev = dev;
720 spin_lock_init(&(priv->rx_queue[i]->rxlock));
724 stash = of_get_property(np, "bd-stash", NULL);
727 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
728 priv->bd_stash_en = 1;
731 stash_len = of_get_property(np, "rx-stash-len", NULL);
734 priv->rx_stash_size = *stash_len;
736 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
739 priv->rx_stash_index = *stash_idx;
741 if (stash_len || stash_idx)
742 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
744 mac_addr = of_get_mac_address(np);
747 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
749 if (model && !strcasecmp(model, "TSEC"))
750 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
751 FSL_GIANFAR_DEV_HAS_COALESCE |
752 FSL_GIANFAR_DEV_HAS_RMON |
753 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
755 if (model && !strcasecmp(model, "eTSEC"))
756 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
757 FSL_GIANFAR_DEV_HAS_COALESCE |
758 FSL_GIANFAR_DEV_HAS_RMON |
759 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
760 FSL_GIANFAR_DEV_HAS_PADDING |
761 FSL_GIANFAR_DEV_HAS_CSUM |
762 FSL_GIANFAR_DEV_HAS_VLAN |
763 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
764 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
765 FSL_GIANFAR_DEV_HAS_TIMER;
767 ctype = of_get_property(np, "phy-connection-type", NULL);
769 /* We only care about rgmii-id. The rest are autodetected */
770 if (ctype && !strcmp(ctype, "rgmii-id"))
771 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
773 priv->interface = PHY_INTERFACE_MODE_MII;
775 if (of_get_property(np, "fsl,magic-packet", NULL))
776 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
778 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
780 /* Find the TBI PHY. If it's not there, we don't support SGMII */
781 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
786 free_rx_pointers(priv);
788 free_tx_pointers(priv);
790 unmap_group_regs(priv);
795 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
796 struct ifreq *ifr, int cmd)
798 struct hwtstamp_config config;
799 struct gfar_private *priv = netdev_priv(netdev);
801 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
804 /* reserved for future extensions */
808 switch (config.tx_type) {
809 case HWTSTAMP_TX_OFF:
810 priv->hwts_tx_en = 0;
813 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
815 priv->hwts_tx_en = 1;
821 switch (config.rx_filter) {
822 case HWTSTAMP_FILTER_NONE:
823 if (priv->hwts_rx_en) {
825 priv->hwts_rx_en = 0;
826 startup_gfar(netdev);
830 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
832 if (!priv->hwts_rx_en) {
834 priv->hwts_rx_en = 1;
835 startup_gfar(netdev);
837 config.rx_filter = HWTSTAMP_FILTER_ALL;
841 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
845 /* Ioctl MII Interface */
846 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
848 struct gfar_private *priv = netdev_priv(dev);
850 if (!netif_running(dev))
853 if (cmd == SIOCSHWTSTAMP)
854 return gfar_hwtstamp_ioctl(dev, rq, cmd);
859 return phy_mii_ioctl(priv->phydev, rq, cmd);
862 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
864 unsigned int new_bit_map = 0x0;
865 int mask = 0x1 << (max_qs - 1), i;
867 for (i = 0; i < max_qs; i++) {
869 new_bit_map = new_bit_map + (1 << i);
875 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
878 u32 rqfpr = FPR_FILER_MASK;
882 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
883 priv->ftp_rqfpr[rqfar] = rqfpr;
884 priv->ftp_rqfcr[rqfar] = rqfcr;
885 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
888 rqfcr = RQFCR_CMP_NOMATCH;
889 priv->ftp_rqfpr[rqfar] = rqfpr;
890 priv->ftp_rqfcr[rqfar] = rqfcr;
891 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
894 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
896 priv->ftp_rqfcr[rqfar] = rqfcr;
897 priv->ftp_rqfpr[rqfar] = rqfpr;
898 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
901 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
903 priv->ftp_rqfcr[rqfar] = rqfcr;
904 priv->ftp_rqfpr[rqfar] = rqfpr;
905 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
910 static void gfar_init_filer_table(struct gfar_private *priv)
913 u32 rqfar = MAX_FILER_IDX;
915 u32 rqfpr = FPR_FILER_MASK;
918 rqfcr = RQFCR_CMP_MATCH;
919 priv->ftp_rqfcr[rqfar] = rqfcr;
920 priv->ftp_rqfpr[rqfar] = rqfpr;
921 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
923 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
924 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
925 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
926 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
927 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
928 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
930 /* cur_filer_idx indicated the first non-masked rule */
931 priv->cur_filer_idx = rqfar;
933 /* Rest are masked rules */
934 rqfcr = RQFCR_CMP_NOMATCH;
935 for (i = 0; i < rqfar; i++) {
936 priv->ftp_rqfcr[i] = rqfcr;
937 priv->ftp_rqfpr[i] = rqfpr;
938 gfar_write_filer(priv, i, rqfcr, rqfpr);
942 static void gfar_detect_errata(struct gfar_private *priv)
944 struct device *dev = &priv->ofdev->dev;
945 unsigned int pvr = mfspr(SPRN_PVR);
946 unsigned int svr = mfspr(SPRN_SVR);
947 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
948 unsigned int rev = svr & 0xffff;
950 /* MPC8313 Rev 2.0 and higher; All MPC837x */
951 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
952 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
953 priv->errata |= GFAR_ERRATA_74;
955 /* MPC8313 and MPC837x all rev */
956 if ((pvr == 0x80850010 && mod == 0x80b0) ||
957 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
958 priv->errata |= GFAR_ERRATA_76;
960 /* MPC8313 and MPC837x all rev */
961 if ((pvr == 0x80850010 && mod == 0x80b0) ||
962 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
963 priv->errata |= GFAR_ERRATA_A002;
965 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
966 if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
967 (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
968 priv->errata |= GFAR_ERRATA_12;
971 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
975 /* Set up the ethernet device structure, private data,
976 * and anything else we need before we start
978 static int gfar_probe(struct platform_device *ofdev)
981 struct net_device *dev = NULL;
982 struct gfar_private *priv = NULL;
983 struct gfar __iomem *regs = NULL;
984 int err = 0, i, grp_idx = 0;
985 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
989 err = gfar_of_init(ofdev, &dev);
994 priv = netdev_priv(dev);
997 priv->dev = &ofdev->dev;
998 SET_NETDEV_DEV(dev, &ofdev->dev);
1000 spin_lock_init(&priv->bflock);
1001 INIT_WORK(&priv->reset_task, gfar_reset_task);
1003 dev_set_drvdata(&ofdev->dev, priv);
1004 regs = priv->gfargrp[0].regs;
1006 gfar_detect_errata(priv);
1008 /* Stop the DMA engine now, in case it was running before
1009 * (The firmware could have used it, and left it running).
1013 /* Reset MAC layer */
1014 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
1016 /* We need to delay at least 3 TX clocks */
1019 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1020 gfar_write(®s->maccfg1, tempval);
1022 /* Initialize MACCFG2. */
1023 tempval = MACCFG2_INIT_SETTINGS;
1024 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1025 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1026 gfar_write(®s->maccfg2, tempval);
1028 /* Initialize ECNTRL */
1029 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
1031 /* Set the dev->base_addr to the gfar reg region */
1032 dev->base_addr = (unsigned long) regs;
1034 /* Fill in the dev structure */
1035 dev->watchdog_timeo = TX_TIMEOUT;
1037 dev->netdev_ops = &gfar_netdev_ops;
1038 dev->ethtool_ops = &gfar_ethtool_ops;
1040 /* Register for napi ...We are registering NAPI for each grp */
1041 for (i = 0; i < priv->num_grps; i++)
1042 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1045 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1046 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1048 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1049 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1052 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1053 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1054 dev->features |= NETIF_F_HW_VLAN_RX;
1057 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1058 priv->extended_hash = 1;
1059 priv->hash_width = 9;
1061 priv->hash_regs[0] = ®s->igaddr0;
1062 priv->hash_regs[1] = ®s->igaddr1;
1063 priv->hash_regs[2] = ®s->igaddr2;
1064 priv->hash_regs[3] = ®s->igaddr3;
1065 priv->hash_regs[4] = ®s->igaddr4;
1066 priv->hash_regs[5] = ®s->igaddr5;
1067 priv->hash_regs[6] = ®s->igaddr6;
1068 priv->hash_regs[7] = ®s->igaddr7;
1069 priv->hash_regs[8] = ®s->gaddr0;
1070 priv->hash_regs[9] = ®s->gaddr1;
1071 priv->hash_regs[10] = ®s->gaddr2;
1072 priv->hash_regs[11] = ®s->gaddr3;
1073 priv->hash_regs[12] = ®s->gaddr4;
1074 priv->hash_regs[13] = ®s->gaddr5;
1075 priv->hash_regs[14] = ®s->gaddr6;
1076 priv->hash_regs[15] = ®s->gaddr7;
1079 priv->extended_hash = 0;
1080 priv->hash_width = 8;
1082 priv->hash_regs[0] = ®s->gaddr0;
1083 priv->hash_regs[1] = ®s->gaddr1;
1084 priv->hash_regs[2] = ®s->gaddr2;
1085 priv->hash_regs[3] = ®s->gaddr3;
1086 priv->hash_regs[4] = ®s->gaddr4;
1087 priv->hash_regs[5] = ®s->gaddr5;
1088 priv->hash_regs[6] = ®s->gaddr6;
1089 priv->hash_regs[7] = ®s->gaddr7;
1092 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1093 priv->padding = DEFAULT_PADDING;
1097 if (dev->features & NETIF_F_IP_CSUM ||
1098 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1099 dev->needed_headroom = GMAC_FCB_LEN;
1101 /* Program the isrg regs only if number of grps > 1 */
1102 if (priv->num_grps > 1) {
1103 baddr = ®s->isrg0;
1104 for (i = 0; i < priv->num_grps; i++) {
1105 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1106 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1107 gfar_write(baddr, isrg);
1113 /* Need to reverse the bit maps as bit_map's MSB is q0
1114 * but, for_each_set_bit parses from right to left, which
1115 * basically reverses the queue numbers
1117 for (i = 0; i< priv->num_grps; i++) {
1118 priv->gfargrp[i].tx_bit_map =
1119 reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1120 priv->gfargrp[i].rx_bit_map =
1121 reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1124 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1125 * also assign queues to groups
1127 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1128 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1130 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1131 priv->num_rx_queues) {
1132 priv->gfargrp[grp_idx].num_rx_queues++;
1133 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1134 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1135 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1137 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1139 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1140 priv->num_tx_queues) {
1141 priv->gfargrp[grp_idx].num_tx_queues++;
1142 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1143 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1144 tqueue = tqueue | (TQUEUE_EN0 >> i);
1146 priv->gfargrp[grp_idx].rstat = rstat;
1147 priv->gfargrp[grp_idx].tstat = tstat;
1151 gfar_write(®s->rqueue, rqueue);
1152 gfar_write(®s->tqueue, tqueue);
1154 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1156 /* Initializing some of the rx/tx queue level parameters */
1157 for (i = 0; i < priv->num_tx_queues; i++) {
1158 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1159 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1160 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1161 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1164 for (i = 0; i < priv->num_rx_queues; i++) {
1165 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1166 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1167 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1170 /* always enable rx filer */
1171 priv->rx_filer_enable = 1;
1172 /* Enable most messages by default */
1173 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1174 /* use pritority h/w tx queue scheduling for single queue devices */
1175 if (priv->num_tx_queues == 1)
1176 priv->prio_sched_en = 1;
1178 /* Carrier starts down, phylib will bring it up */
1179 netif_carrier_off(dev);
1181 err = register_netdev(dev);
1184 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1188 device_init_wakeup(&dev->dev,
1189 priv->device_flags &
1190 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1192 /* fill out IRQ number and name fields */
1193 for (i = 0; i < priv->num_grps; i++) {
1194 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1195 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1196 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1197 dev->name, "_g", '0' + i, "_tx");
1198 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1199 dev->name, "_g", '0' + i, "_rx");
1200 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1201 dev->name, "_g", '0' + i, "_er");
1203 strcpy(gfar_irq(grp, TX)->name, dev->name);
1206 /* Initialize the filer table */
1207 gfar_init_filer_table(priv);
1209 /* Create all the sysfs files */
1210 gfar_init_sysfs(dev);
1212 /* Print out the device info */
1213 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1215 /* Even more device info helps when determining which kernel
1216 * provided which set of benchmarks.
1218 netdev_info(dev, "Running with NAPI enabled\n");
1219 for (i = 0; i < priv->num_rx_queues; i++)
1220 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1221 i, priv->rx_queue[i]->rx_ring_size);
1222 for (i = 0; i < priv->num_tx_queues; i++)
1223 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1224 i, priv->tx_queue[i]->tx_ring_size);
1229 unmap_group_regs(priv);
1230 free_tx_pointers(priv);
1231 free_rx_pointers(priv);
1233 of_node_put(priv->phy_node);
1235 of_node_put(priv->tbi_node);
1236 free_gfar_dev(priv);
1240 static int gfar_remove(struct platform_device *ofdev)
1242 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1245 of_node_put(priv->phy_node);
1247 of_node_put(priv->tbi_node);
1249 dev_set_drvdata(&ofdev->dev, NULL);
1251 unregister_netdev(priv->ndev);
1252 unmap_group_regs(priv);
1253 free_gfar_dev(priv);
1260 static int gfar_suspend(struct device *dev)
1262 struct gfar_private *priv = dev_get_drvdata(dev);
1263 struct net_device *ndev = priv->ndev;
1264 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1265 unsigned long flags;
1268 int magic_packet = priv->wol_en &&
1269 (priv->device_flags &
1270 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1272 netif_device_detach(ndev);
1274 if (netif_running(ndev)) {
1276 local_irq_save(flags);
1280 gfar_halt_nodisable(ndev);
1282 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1283 tempval = gfar_read(®s->maccfg1);
1285 tempval &= ~MACCFG1_TX_EN;
1288 tempval &= ~MACCFG1_RX_EN;
1290 gfar_write(®s->maccfg1, tempval);
1294 local_irq_restore(flags);
1299 /* Enable interrupt on Magic Packet */
1300 gfar_write(®s->imask, IMASK_MAG);
1302 /* Enable Magic Packet mode */
1303 tempval = gfar_read(®s->maccfg2);
1304 tempval |= MACCFG2_MPEN;
1305 gfar_write(®s->maccfg2, tempval);
1307 phy_stop(priv->phydev);
1314 static int gfar_resume(struct device *dev)
1316 struct gfar_private *priv = dev_get_drvdata(dev);
1317 struct net_device *ndev = priv->ndev;
1318 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1319 unsigned long flags;
1321 int magic_packet = priv->wol_en &&
1322 (priv->device_flags &
1323 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1325 if (!netif_running(ndev)) {
1326 netif_device_attach(ndev);
1330 if (!magic_packet && priv->phydev)
1331 phy_start(priv->phydev);
1333 /* Disable Magic Packet mode, in case something
1336 local_irq_save(flags);
1340 tempval = gfar_read(®s->maccfg2);
1341 tempval &= ~MACCFG2_MPEN;
1342 gfar_write(®s->maccfg2, tempval);
1348 local_irq_restore(flags);
1350 netif_device_attach(ndev);
1357 static int gfar_restore(struct device *dev)
1359 struct gfar_private *priv = dev_get_drvdata(dev);
1360 struct net_device *ndev = priv->ndev;
1362 if (!netif_running(ndev)) {
1363 netif_device_attach(ndev);
1368 if (gfar_init_bds(ndev)) {
1369 free_skb_resources(priv);
1373 init_registers(ndev);
1374 gfar_set_mac_address(ndev);
1375 gfar_init_mac(ndev);
1380 priv->oldduplex = -1;
1383 phy_start(priv->phydev);
1385 netif_device_attach(ndev);
1391 static struct dev_pm_ops gfar_pm_ops = {
1392 .suspend = gfar_suspend,
1393 .resume = gfar_resume,
1394 .freeze = gfar_suspend,
1395 .thaw = gfar_resume,
1396 .restore = gfar_restore,
1399 #define GFAR_PM_OPS (&gfar_pm_ops)
1403 #define GFAR_PM_OPS NULL
1407 /* Reads the controller's registers to determine what interface
1408 * connects it to the PHY.
1410 static phy_interface_t gfar_get_interface(struct net_device *dev)
1412 struct gfar_private *priv = netdev_priv(dev);
1413 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1416 ecntrl = gfar_read(®s->ecntrl);
1418 if (ecntrl & ECNTRL_SGMII_MODE)
1419 return PHY_INTERFACE_MODE_SGMII;
1421 if (ecntrl & ECNTRL_TBI_MODE) {
1422 if (ecntrl & ECNTRL_REDUCED_MODE)
1423 return PHY_INTERFACE_MODE_RTBI;
1425 return PHY_INTERFACE_MODE_TBI;
1428 if (ecntrl & ECNTRL_REDUCED_MODE) {
1429 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1430 return PHY_INTERFACE_MODE_RMII;
1433 phy_interface_t interface = priv->interface;
1435 /* This isn't autodetected right now, so it must
1436 * be set by the device tree or platform code.
1438 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1439 return PHY_INTERFACE_MODE_RGMII_ID;
1441 return PHY_INTERFACE_MODE_RGMII;
1445 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1446 return PHY_INTERFACE_MODE_GMII;
1448 return PHY_INTERFACE_MODE_MII;
1452 /* Initializes driver's PHY state, and attaches to the PHY.
1453 * Returns 0 on success.
1455 static int init_phy(struct net_device *dev)
1457 struct gfar_private *priv = netdev_priv(dev);
1458 uint gigabit_support =
1459 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1460 SUPPORTED_1000baseT_Full : 0;
1461 phy_interface_t interface;
1465 priv->oldduplex = -1;
1467 interface = gfar_get_interface(dev);
1469 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1472 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1474 if (!priv->phydev) {
1475 dev_err(&dev->dev, "could not attach to PHY\n");
1479 if (interface == PHY_INTERFACE_MODE_SGMII)
1480 gfar_configure_serdes(dev);
1482 /* Remove any features not supported by the controller */
1483 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1484 priv->phydev->advertising = priv->phydev->supported;
1489 /* Initialize TBI PHY interface for communicating with the
1490 * SERDES lynx PHY on the chip. We communicate with this PHY
1491 * through the MDIO bus on each controller, treating it as a
1492 * "normal" PHY at the address found in the TBIPA register. We assume
1493 * that the TBIPA register is valid. Either the MDIO bus code will set
1494 * it to a value that doesn't conflict with other PHYs on the bus, or the
1495 * value doesn't matter, as there are no other PHYs on the bus.
1497 static void gfar_configure_serdes(struct net_device *dev)
1499 struct gfar_private *priv = netdev_priv(dev);
1500 struct phy_device *tbiphy;
1502 if (!priv->tbi_node) {
1503 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1504 "device tree specify a tbi-handle\n");
1508 tbiphy = of_phy_find_device(priv->tbi_node);
1510 dev_err(&dev->dev, "error: Could not get TBI device\n");
1514 /* If the link is already up, we must already be ok, and don't need to
1515 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1516 * everything for us? Resetting it takes the link down and requires
1517 * several seconds for it to come back.
1519 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1522 /* Single clk mode, mii mode off(for serdes communication) */
1523 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1525 phy_write(tbiphy, MII_ADVERTISE,
1526 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1527 ADVERTISE_1000XPSE_ASYM);
1529 phy_write(tbiphy, MII_BMCR,
1530 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1534 static void init_registers(struct net_device *dev)
1536 struct gfar_private *priv = netdev_priv(dev);
1537 struct gfar __iomem *regs = NULL;
1540 for (i = 0; i < priv->num_grps; i++) {
1541 regs = priv->gfargrp[i].regs;
1543 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
1545 /* Initialize IMASK */
1546 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1549 regs = priv->gfargrp[0].regs;
1550 /* Init hash registers to zero */
1551 gfar_write(®s->igaddr0, 0);
1552 gfar_write(®s->igaddr1, 0);
1553 gfar_write(®s->igaddr2, 0);
1554 gfar_write(®s->igaddr3, 0);
1555 gfar_write(®s->igaddr4, 0);
1556 gfar_write(®s->igaddr5, 0);
1557 gfar_write(®s->igaddr6, 0);
1558 gfar_write(®s->igaddr7, 0);
1560 gfar_write(®s->gaddr0, 0);
1561 gfar_write(®s->gaddr1, 0);
1562 gfar_write(®s->gaddr2, 0);
1563 gfar_write(®s->gaddr3, 0);
1564 gfar_write(®s->gaddr4, 0);
1565 gfar_write(®s->gaddr5, 0);
1566 gfar_write(®s->gaddr6, 0);
1567 gfar_write(®s->gaddr7, 0);
1569 /* Zero out the rmon mib registers if it has them */
1570 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1571 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1573 /* Mask off the CAM interrupts */
1574 gfar_write(®s->rmon.cam1, 0xffffffff);
1575 gfar_write(®s->rmon.cam2, 0xffffffff);
1578 /* Initialize the max receive buffer length */
1579 gfar_write(®s->mrblr, priv->rx_buffer_size);
1581 /* Initialize the Minimum Frame Length Register */
1582 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
1585 static int __gfar_is_rx_idle(struct gfar_private *priv)
1589 /* Normaly TSEC should not hang on GRS commands, so we should
1590 * actually wait for IEVENT_GRSC flag.
1592 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1595 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1596 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1597 * and the Rx can be safely reset.
1599 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1601 if ((res & 0xffff) == (res >> 16))
1607 /* Halt the receive and transmit queues */
1608 static void gfar_halt_nodisable(struct net_device *dev)
1610 struct gfar_private *priv = netdev_priv(dev);
1611 struct gfar __iomem *regs = NULL;
1615 for (i = 0; i < priv->num_grps; i++) {
1616 regs = priv->gfargrp[i].regs;
1617 /* Mask all interrupts */
1618 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1620 /* Clear all interrupts */
1621 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
1624 regs = priv->gfargrp[0].regs;
1625 /* Stop the DMA, and wait for it to stop */
1626 tempval = gfar_read(®s->dmactrl);
1627 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1628 (DMACTRL_GRS | DMACTRL_GTS)) {
1631 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1632 gfar_write(®s->dmactrl, tempval);
1635 ret = spin_event_timeout(((gfar_read(®s->ievent) &
1636 (IEVENT_GRSC | IEVENT_GTSC)) ==
1637 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1638 if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC))
1639 ret = __gfar_is_rx_idle(priv);
1644 /* Halt the receive and transmit queues */
1645 void gfar_halt(struct net_device *dev)
1647 struct gfar_private *priv = netdev_priv(dev);
1648 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1651 gfar_halt_nodisable(dev);
1653 /* Disable Rx and Tx */
1654 tempval = gfar_read(®s->maccfg1);
1655 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1656 gfar_write(®s->maccfg1, tempval);
1659 static void free_grp_irqs(struct gfar_priv_grp *grp)
1661 free_irq(gfar_irq(grp, TX)->irq, grp);
1662 free_irq(gfar_irq(grp, RX)->irq, grp);
1663 free_irq(gfar_irq(grp, ER)->irq, grp);
1666 void stop_gfar(struct net_device *dev)
1668 struct gfar_private *priv = netdev_priv(dev);
1669 unsigned long flags;
1672 phy_stop(priv->phydev);
1676 local_irq_save(flags);
1684 local_irq_restore(flags);
1687 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1688 for (i = 0; i < priv->num_grps; i++)
1689 free_grp_irqs(&priv->gfargrp[i]);
1691 for (i = 0; i < priv->num_grps; i++)
1692 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1696 free_skb_resources(priv);
1699 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1701 struct txbd8 *txbdp;
1702 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1705 txbdp = tx_queue->tx_bd_base;
1707 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1708 if (!tx_queue->tx_skbuff[i])
1711 dma_unmap_single(priv->dev, txbdp->bufPtr,
1712 txbdp->length, DMA_TO_DEVICE);
1714 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1717 dma_unmap_page(priv->dev, txbdp->bufPtr,
1718 txbdp->length, DMA_TO_DEVICE);
1721 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1722 tx_queue->tx_skbuff[i] = NULL;
1724 kfree(tx_queue->tx_skbuff);
1725 tx_queue->tx_skbuff = NULL;
1728 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1730 struct rxbd8 *rxbdp;
1731 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1734 rxbdp = rx_queue->rx_bd_base;
1736 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1737 if (rx_queue->rx_skbuff[i]) {
1738 dma_unmap_single(priv->dev, rxbdp->bufPtr,
1739 priv->rx_buffer_size,
1741 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1742 rx_queue->rx_skbuff[i] = NULL;
1748 kfree(rx_queue->rx_skbuff);
1749 rx_queue->rx_skbuff = NULL;
1752 /* If there are any tx skbs or rx skbs still around, free them.
1753 * Then free tx_skbuff and rx_skbuff
1755 static void free_skb_resources(struct gfar_private *priv)
1757 struct gfar_priv_tx_q *tx_queue = NULL;
1758 struct gfar_priv_rx_q *rx_queue = NULL;
1761 /* Go through all the buffer descriptors and free their data buffers */
1762 for (i = 0; i < priv->num_tx_queues; i++) {
1763 struct netdev_queue *txq;
1765 tx_queue = priv->tx_queue[i];
1766 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1767 if (tx_queue->tx_skbuff)
1768 free_skb_tx_queue(tx_queue);
1769 netdev_tx_reset_queue(txq);
1772 for (i = 0; i < priv->num_rx_queues; i++) {
1773 rx_queue = priv->rx_queue[i];
1774 if (rx_queue->rx_skbuff)
1775 free_skb_rx_queue(rx_queue);
1778 dma_free_coherent(priv->dev,
1779 sizeof(struct txbd8) * priv->total_tx_ring_size +
1780 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1781 priv->tx_queue[0]->tx_bd_base,
1782 priv->tx_queue[0]->tx_bd_dma_base);
1785 void gfar_start(struct net_device *dev)
1787 struct gfar_private *priv = netdev_priv(dev);
1788 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1792 /* Enable Rx and Tx in MACCFG1 */
1793 tempval = gfar_read(®s->maccfg1);
1794 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1795 gfar_write(®s->maccfg1, tempval);
1797 /* Initialize DMACTRL to have WWR and WOP */
1798 tempval = gfar_read(®s->dmactrl);
1799 tempval |= DMACTRL_INIT_SETTINGS;
1800 gfar_write(®s->dmactrl, tempval);
1802 /* Make sure we aren't stopped */
1803 tempval = gfar_read(®s->dmactrl);
1804 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1805 gfar_write(®s->dmactrl, tempval);
1807 for (i = 0; i < priv->num_grps; i++) {
1808 regs = priv->gfargrp[i].regs;
1809 /* Clear THLT/RHLT, so that the DMA starts polling now */
1810 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
1811 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1812 /* Unmask the interrupts we look for */
1813 gfar_write(®s->imask, IMASK_DEFAULT);
1816 dev->trans_start = jiffies; /* prevent tx timeout */
1819 static void gfar_configure_coalescing(struct gfar_private *priv,
1820 unsigned long tx_mask, unsigned long rx_mask)
1822 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1825 if (priv->mode == MQ_MG_MODE) {
1827 baddr = ®s->txic0;
1828 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1829 gfar_write(baddr + i, 0);
1830 if (likely(priv->tx_queue[i]->txcoalescing))
1831 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1834 baddr = ®s->rxic0;
1835 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1836 gfar_write(baddr + i, 0);
1837 if (likely(priv->rx_queue[i]->rxcoalescing))
1838 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1841 /* Backward compatible case ---- even if we enable
1842 * multiple queues, there's only single reg to program
1844 gfar_write(®s->txic, 0);
1845 if (likely(priv->tx_queue[0]->txcoalescing))
1846 gfar_write(®s->txic, priv->tx_queue[0]->txic);
1848 gfar_write(®s->rxic, 0);
1849 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1850 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
1854 void gfar_configure_coalescing_all(struct gfar_private *priv)
1856 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1859 static int register_grp_irqs(struct gfar_priv_grp *grp)
1861 struct gfar_private *priv = grp->priv;
1862 struct net_device *dev = priv->ndev;
1865 /* If the device has multiple interrupts, register for
1866 * them. Otherwise, only register for the one
1868 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1869 /* Install our interrupt handlers for Error,
1870 * Transmit, and Receive
1872 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1873 gfar_irq(grp, ER)->name, grp);
1875 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1876 gfar_irq(grp, ER)->irq);
1880 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1881 gfar_irq(grp, TX)->name, grp);
1883 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1884 gfar_irq(grp, TX)->irq);
1887 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1888 gfar_irq(grp, RX)->name, grp);
1890 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1891 gfar_irq(grp, RX)->irq);
1895 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1896 gfar_irq(grp, TX)->name, grp);
1898 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1899 gfar_irq(grp, TX)->irq);
1907 free_irq(gfar_irq(grp, TX)->irq, grp);
1909 free_irq(gfar_irq(grp, ER)->irq, grp);
1915 /* Bring the controller up and running */
1916 int startup_gfar(struct net_device *ndev)
1918 struct gfar_private *priv = netdev_priv(ndev);
1919 struct gfar __iomem *regs = NULL;
1922 for (i = 0; i < priv->num_grps; i++) {
1923 regs= priv->gfargrp[i].regs;
1924 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1927 regs= priv->gfargrp[0].regs;
1928 err = gfar_alloc_skb_resources(ndev);
1932 gfar_init_mac(ndev);
1934 for (i = 0; i < priv->num_grps; i++) {
1935 err = register_grp_irqs(&priv->gfargrp[i]);
1937 for (j = 0; j < i; j++)
1938 free_grp_irqs(&priv->gfargrp[j]);
1943 /* Start the controller */
1946 phy_start(priv->phydev);
1948 gfar_configure_coalescing_all(priv);
1953 free_skb_resources(priv);
1957 /* Called when something needs to use the ethernet device
1958 * Returns 0 for success.
1960 static int gfar_enet_open(struct net_device *dev)
1962 struct gfar_private *priv = netdev_priv(dev);
1967 /* Initialize a bunch of registers */
1968 init_registers(dev);
1970 gfar_set_mac_address(dev);
1972 err = init_phy(dev);
1979 err = startup_gfar(dev);
1985 netif_tx_start_all_queues(dev);
1987 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1992 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1994 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1996 memset(fcb, 0, GMAC_FCB_LEN);
2001 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2004 /* If we're here, it's a IP packet with a TCP or UDP
2005 * payload. We set it to checksum, using a pseudo-header
2008 u8 flags = TXFCB_DEFAULT;
2010 /* Tell the controller what the protocol is
2011 * And provide the already calculated phcs
2013 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2015 fcb->phcs = udp_hdr(skb)->check;
2017 fcb->phcs = tcp_hdr(skb)->check;
2019 /* l3os is the distance between the start of the
2020 * frame (skb->data) and the start of the IP hdr.
2021 * l4os is the distance between the start of the
2022 * l3 hdr and the l4 hdr
2024 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2025 fcb->l4os = skb_network_header_len(skb);
2030 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2032 fcb->flags |= TXFCB_VLN;
2033 fcb->vlctl = vlan_tx_tag_get(skb);
2036 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2037 struct txbd8 *base, int ring_size)
2039 struct txbd8 *new_bd = bdp + stride;
2041 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2044 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2047 return skip_txbd(bdp, 1, base, ring_size);
2050 /* This is called by the kernel when a frame is ready for transmission.
2051 * It is pointed to by the dev->hard_start_xmit function pointer
2053 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2055 struct gfar_private *priv = netdev_priv(dev);
2056 struct gfar_priv_tx_q *tx_queue = NULL;
2057 struct netdev_queue *txq;
2058 struct gfar __iomem *regs = NULL;
2059 struct txfcb *fcb = NULL;
2060 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2062 int i, rq = 0, do_tstamp = 0;
2064 unsigned long flags;
2065 unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2067 /* TOE=1 frames larger than 2500 bytes may see excess delays
2068 * before start of transmission.
2070 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2071 skb->ip_summed == CHECKSUM_PARTIAL &&
2075 ret = skb_checksum_help(skb);
2080 rq = skb->queue_mapping;
2081 tx_queue = priv->tx_queue[rq];
2082 txq = netdev_get_tx_queue(dev, rq);
2083 base = tx_queue->tx_bd_base;
2084 regs = tx_queue->grp->regs;
2086 /* check if time stamp should be generated */
2087 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2088 priv->hwts_tx_en)) {
2090 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2093 /* make space for additional header when fcb is needed */
2094 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2095 vlan_tx_tag_present(skb) ||
2096 unlikely(do_tstamp)) &&
2097 (skb_headroom(skb) < fcb_length)) {
2098 struct sk_buff *skb_new;
2100 skb_new = skb_realloc_headroom(skb, fcb_length);
2102 dev->stats.tx_errors++;
2104 return NETDEV_TX_OK;
2108 skb_set_owner_w(skb_new, skb->sk);
2113 /* total number of fragments in the SKB */
2114 nr_frags = skb_shinfo(skb)->nr_frags;
2116 /* calculate the required number of TxBDs for this skb */
2117 if (unlikely(do_tstamp))
2118 nr_txbds = nr_frags + 2;
2120 nr_txbds = nr_frags + 1;
2122 /* check if there is space to queue this packet */
2123 if (nr_txbds > tx_queue->num_txbdfree) {
2124 /* no space, stop the queue */
2125 netif_tx_stop_queue(txq);
2126 dev->stats.tx_fifo_errors++;
2127 return NETDEV_TX_BUSY;
2130 /* Update transmit stats */
2131 tx_queue->stats.tx_bytes += skb->len;
2132 tx_queue->stats.tx_packets++;
2134 txbdp = txbdp_start = tx_queue->cur_tx;
2135 lstatus = txbdp->lstatus;
2137 /* Time stamp insertion requires one additional TxBD */
2138 if (unlikely(do_tstamp))
2139 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2140 tx_queue->tx_ring_size);
2142 if (nr_frags == 0) {
2143 if (unlikely(do_tstamp))
2144 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2147 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2149 /* Place the fragment addresses and lengths into the TxBDs */
2150 for (i = 0; i < nr_frags; i++) {
2151 /* Point at the next BD, wrapping as needed */
2152 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2154 length = skb_shinfo(skb)->frags[i].size;
2156 lstatus = txbdp->lstatus | length |
2157 BD_LFLAG(TXBD_READY);
2159 /* Handle the last BD specially */
2160 if (i == nr_frags - 1)
2161 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2163 bufaddr = skb_frag_dma_map(priv->dev,
2164 &skb_shinfo(skb)->frags[i],
2169 /* set the TxBD length and buffer pointer */
2170 txbdp->bufPtr = bufaddr;
2171 txbdp->lstatus = lstatus;
2174 lstatus = txbdp_start->lstatus;
2177 /* Add TxPAL between FCB and frame if required */
2178 if (unlikely(do_tstamp)) {
2179 skb_push(skb, GMAC_TXPAL_LEN);
2180 memset(skb->data, 0, GMAC_TXPAL_LEN);
2183 /* Set up checksumming */
2184 if (CHECKSUM_PARTIAL == skb->ip_summed) {
2185 fcb = gfar_add_fcb(skb);
2186 /* as specified by errata */
2187 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2188 ((unsigned long)fcb % 0x20) > 0x18)) {
2189 __skb_pull(skb, GMAC_FCB_LEN);
2190 skb_checksum_help(skb);
2192 lstatus |= BD_LFLAG(TXBD_TOE);
2193 gfar_tx_checksum(skb, fcb, fcb_length);
2197 if (vlan_tx_tag_present(skb)) {
2198 if (unlikely(NULL == fcb)) {
2199 fcb = gfar_add_fcb(skb);
2200 lstatus |= BD_LFLAG(TXBD_TOE);
2203 gfar_tx_vlan(skb, fcb);
2206 /* Setup tx hardware time stamping if requested */
2207 if (unlikely(do_tstamp)) {
2208 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2210 fcb = gfar_add_fcb(skb);
2212 lstatus |= BD_LFLAG(TXBD_TOE);
2215 txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
2216 skb_headlen(skb), DMA_TO_DEVICE);
2218 /* If time stamping is requested one additional TxBD must be set up. The
2219 * first TxBD points to the FCB and must have a data length of
2220 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2221 * the full frame length.
2223 if (unlikely(do_tstamp)) {
2224 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2225 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2226 (skb_headlen(skb) - fcb_length);
2227 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2229 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2232 netdev_tx_sent_queue(txq, skb->len);
2234 /* We can work in parallel with gfar_clean_tx_ring(), except
2235 * when modifying num_txbdfree. Note that we didn't grab the lock
2236 * when we were reading the num_txbdfree and checking for available
2237 * space, that's because outside of this function it can only grow,
2238 * and once we've got needed space, it cannot suddenly disappear.
2240 * The lock also protects us from gfar_error(), which can modify
2241 * regs->tstat and thus retrigger the transfers, which is why we
2242 * also must grab the lock before setting ready bit for the first
2243 * to be transmitted BD.
2245 spin_lock_irqsave(&tx_queue->txlock, flags);
2247 /* The powerpc-specific eieio() is used, as wmb() has too strong
2248 * semantics (it requires synchronization between cacheable and
2249 * uncacheable mappings, which eieio doesn't provide and which we
2250 * don't need), thus requiring a more expensive sync instruction. At
2251 * some point, the set of architecture-independent barrier functions
2252 * should be expanded to include weaker barriers.
2256 txbdp_start->lstatus = lstatus;
2258 eieio(); /* force lstatus write before tx_skbuff */
2260 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2262 /* Update the current skb pointer to the next entry we will use
2263 * (wrapping if necessary)
2265 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2266 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2268 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2270 /* reduce TxBD free count */
2271 tx_queue->num_txbdfree -= (nr_txbds);
2273 /* If the next BD still needs to be cleaned up, then the bds
2274 * are full. We need to tell the kernel to stop sending us stuff.
2276 if (!tx_queue->num_txbdfree) {
2277 netif_tx_stop_queue(txq);
2279 dev->stats.tx_fifo_errors++;
2282 /* Tell the DMA to go go go */
2283 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2286 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2288 return NETDEV_TX_OK;
2291 /* Stops the kernel queue, and halts the controller */
2292 static int gfar_close(struct net_device *dev)
2294 struct gfar_private *priv = netdev_priv(dev);
2298 cancel_work_sync(&priv->reset_task);
2301 /* Disconnect from the PHY */
2302 phy_disconnect(priv->phydev);
2303 priv->phydev = NULL;
2305 netif_tx_stop_all_queues(dev);
2310 /* Changes the mac address if the controller is not running. */
2311 static int gfar_set_mac_address(struct net_device *dev)
2313 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2318 /* Check if rx parser should be activated */
2319 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2321 struct gfar __iomem *regs;
2324 regs = priv->gfargrp[0].regs;
2326 tempval = gfar_read(®s->rctrl);
2327 /* If parse is no longer required, then disable parser */
2328 if (tempval & RCTRL_REQ_PARSER) {
2329 tempval |= RCTRL_PRSDEP_INIT;
2330 priv->uses_rxfcb = 1;
2332 tempval &= ~RCTRL_PRSDEP_INIT;
2333 priv->uses_rxfcb = 0;
2335 gfar_write(®s->rctrl, tempval);
2338 /* Enables and disables VLAN insertion/extraction */
2339 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2341 struct gfar_private *priv = netdev_priv(dev);
2342 struct gfar __iomem *regs = NULL;
2343 unsigned long flags;
2346 regs = priv->gfargrp[0].regs;
2347 local_irq_save(flags);
2350 if (features & NETIF_F_HW_VLAN_TX) {
2351 /* Enable VLAN tag insertion */
2352 tempval = gfar_read(®s->tctrl);
2353 tempval |= TCTRL_VLINS;
2354 gfar_write(®s->tctrl, tempval);
2356 /* Disable VLAN tag insertion */
2357 tempval = gfar_read(®s->tctrl);
2358 tempval &= ~TCTRL_VLINS;
2359 gfar_write(®s->tctrl, tempval);
2362 if (features & NETIF_F_HW_VLAN_RX) {
2363 /* Enable VLAN tag extraction */
2364 tempval = gfar_read(®s->rctrl);
2365 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2366 gfar_write(®s->rctrl, tempval);
2367 priv->uses_rxfcb = 1;
2369 /* Disable VLAN tag extraction */
2370 tempval = gfar_read(®s->rctrl);
2371 tempval &= ~RCTRL_VLEX;
2372 gfar_write(®s->rctrl, tempval);
2374 gfar_check_rx_parser_mode(priv);
2377 gfar_change_mtu(dev, dev->mtu);
2380 local_irq_restore(flags);
2383 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2385 int tempsize, tempval;
2386 struct gfar_private *priv = netdev_priv(dev);
2387 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2388 int oldsize = priv->rx_buffer_size;
2389 int frame_size = new_mtu + ETH_HLEN;
2391 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2392 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2396 if (priv->uses_rxfcb)
2397 frame_size += GMAC_FCB_LEN;
2399 frame_size += priv->padding;
2401 tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2402 INCREMENTAL_BUFFER_SIZE;
2404 /* Only stop and start the controller if it isn't already
2405 * stopped, and we changed something
2407 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2410 priv->rx_buffer_size = tempsize;
2414 gfar_write(®s->mrblr, priv->rx_buffer_size);
2415 gfar_write(®s->maxfrm, priv->rx_buffer_size);
2417 /* If the mtu is larger than the max size for standard
2418 * ethernet frames (ie, a jumbo frame), then set maccfg2
2419 * to allow huge frames, and to check the length
2421 tempval = gfar_read(®s->maccfg2);
2423 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2424 gfar_has_errata(priv, GFAR_ERRATA_74))
2425 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2427 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2429 gfar_write(®s->maccfg2, tempval);
2431 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2437 /* gfar_reset_task gets scheduled when a packet has not been
2438 * transmitted after a set amount of time.
2439 * For now, assume that clearing out all the structures, and
2440 * starting over will fix the problem.
2442 static void gfar_reset_task(struct work_struct *work)
2444 struct gfar_private *priv = container_of(work, struct gfar_private,
2446 struct net_device *dev = priv->ndev;
2448 if (dev->flags & IFF_UP) {
2449 netif_tx_stop_all_queues(dev);
2452 netif_tx_start_all_queues(dev);
2455 netif_tx_schedule_all(dev);
2458 static void gfar_timeout(struct net_device *dev)
2460 struct gfar_private *priv = netdev_priv(dev);
2462 dev->stats.tx_errors++;
2463 schedule_work(&priv->reset_task);
2466 static void gfar_align_skb(struct sk_buff *skb)
2468 /* We need the data buffer to be aligned properly. We will reserve
2469 * as many bytes as needed to align the data properly
2471 skb_reserve(skb, RXBUF_ALIGNMENT -
2472 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2475 /* Interrupt Handler for Transmit complete */
2476 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2478 struct net_device *dev = tx_queue->dev;
2479 struct netdev_queue *txq;
2480 struct gfar_private *priv = netdev_priv(dev);
2481 struct gfar_priv_rx_q *rx_queue = NULL;
2482 struct txbd8 *bdp, *next = NULL;
2483 struct txbd8 *lbdp = NULL;
2484 struct txbd8 *base = tx_queue->tx_bd_base;
2485 struct sk_buff *skb;
2487 int tx_ring_size = tx_queue->tx_ring_size;
2488 int frags = 0, nr_txbds = 0;
2491 int tqi = tx_queue->qindex;
2492 unsigned int bytes_sent = 0;
2496 rx_queue = priv->rx_queue[tqi];
2497 txq = netdev_get_tx_queue(dev, tqi);
2498 bdp = tx_queue->dirty_tx;
2499 skb_dirtytx = tx_queue->skb_dirtytx;
2501 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2502 unsigned long flags;
2504 frags = skb_shinfo(skb)->nr_frags;
2506 /* When time stamping, one additional TxBD must be freed.
2507 * Also, we need to dma_unmap_single() the TxPAL.
2509 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2510 nr_txbds = frags + 2;
2512 nr_txbds = frags + 1;
2514 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2516 lstatus = lbdp->lstatus;
2518 /* Only clean completed frames */
2519 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2520 (lstatus & BD_LENGTH_MASK))
2523 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2524 next = next_txbd(bdp, base, tx_ring_size);
2525 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2527 buflen = bdp->length;
2529 dma_unmap_single(priv->dev, bdp->bufPtr,
2530 buflen, DMA_TO_DEVICE);
2532 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2533 struct skb_shared_hwtstamps shhwtstamps;
2534 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2536 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2537 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2538 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2539 skb_tstamp_tx(skb, &shhwtstamps);
2540 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2544 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2545 bdp = next_txbd(bdp, base, tx_ring_size);
2547 for (i = 0; i < frags; i++) {
2548 dma_unmap_page(priv->dev, bdp->bufPtr,
2549 bdp->length, DMA_TO_DEVICE);
2550 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2551 bdp = next_txbd(bdp, base, tx_ring_size);
2554 bytes_sent += skb->len;
2556 dev_kfree_skb_any(skb);
2558 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2560 skb_dirtytx = (skb_dirtytx + 1) &
2561 TX_RING_MOD_MASK(tx_ring_size);
2564 spin_lock_irqsave(&tx_queue->txlock, flags);
2565 tx_queue->num_txbdfree += nr_txbds;
2566 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2569 /* If we freed a buffer, we can restart transmission, if necessary */
2570 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2571 netif_wake_subqueue(dev, tqi);
2573 /* Update dirty indicators */
2574 tx_queue->skb_dirtytx = skb_dirtytx;
2575 tx_queue->dirty_tx = bdp;
2577 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2580 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2582 unsigned long flags;
2584 spin_lock_irqsave(&gfargrp->grplock, flags);
2585 if (napi_schedule_prep(&gfargrp->napi)) {
2586 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2587 __napi_schedule(&gfargrp->napi);
2589 /* Clear IEVENT, so interrupts aren't called again
2590 * because of the packets that have already arrived.
2592 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2594 spin_unlock_irqrestore(&gfargrp->grplock, flags);
2598 /* Interrupt Handler for Transmit complete */
2599 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2601 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2605 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2606 struct sk_buff *skb)
2608 struct net_device *dev = rx_queue->dev;
2609 struct gfar_private *priv = netdev_priv(dev);
2612 buf = dma_map_single(priv->dev, skb->data,
2613 priv->rx_buffer_size, DMA_FROM_DEVICE);
2614 gfar_init_rxbdp(rx_queue, bdp, buf);
2617 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2619 struct gfar_private *priv = netdev_priv(dev);
2620 struct sk_buff *skb;
2622 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2626 gfar_align_skb(skb);
2631 struct sk_buff *gfar_new_skb(struct net_device *dev)
2633 return gfar_alloc_skb(dev);
2636 static inline void count_errors(unsigned short status, struct net_device *dev)
2638 struct gfar_private *priv = netdev_priv(dev);
2639 struct net_device_stats *stats = &dev->stats;
2640 struct gfar_extra_stats *estats = &priv->extra_stats;
2642 /* If the packet was truncated, none of the other errors matter */
2643 if (status & RXBD_TRUNCATED) {
2644 stats->rx_length_errors++;
2646 atomic64_inc(&estats->rx_trunc);
2650 /* Count the errors, if there were any */
2651 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2652 stats->rx_length_errors++;
2654 if (status & RXBD_LARGE)
2655 atomic64_inc(&estats->rx_large);
2657 atomic64_inc(&estats->rx_short);
2659 if (status & RXBD_NONOCTET) {
2660 stats->rx_frame_errors++;
2661 atomic64_inc(&estats->rx_nonoctet);
2663 if (status & RXBD_CRCERR) {
2664 atomic64_inc(&estats->rx_crcerr);
2665 stats->rx_crc_errors++;
2667 if (status & RXBD_OVERRUN) {
2668 atomic64_inc(&estats->rx_overrun);
2669 stats->rx_crc_errors++;
2673 irqreturn_t gfar_receive(int irq, void *grp_id)
2675 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2679 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2681 /* If valid headers were found, and valid sums
2682 * were verified, then we tell the kernel that no
2683 * checksumming is necessary. Otherwise, it is [FIXME]
2685 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2686 skb->ip_summed = CHECKSUM_UNNECESSARY;
2688 skb_checksum_none_assert(skb);
2692 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2693 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2694 int amount_pull, struct napi_struct *napi)
2696 struct gfar_private *priv = netdev_priv(dev);
2697 struct rxfcb *fcb = NULL;
2701 /* fcb is at the beginning if exists */
2702 fcb = (struct rxfcb *)skb->data;
2704 /* Remove the FCB from the skb
2705 * Remove the padded bytes, if there are any
2708 skb_record_rx_queue(skb, fcb->rq);
2709 skb_pull(skb, amount_pull);
2712 /* Get receive timestamp from the skb */
2713 if (priv->hwts_rx_en) {
2714 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2715 u64 *ns = (u64 *) skb->data;
2717 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2718 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2722 skb_pull(skb, priv->padding);
2724 if (dev->features & NETIF_F_RXCSUM)
2725 gfar_rx_checksum(skb, fcb);
2727 /* Tell the skb what kind of packet this is */
2728 skb->protocol = eth_type_trans(skb, dev);
2730 /* There's need to check for NETIF_F_HW_VLAN_RX here.
2731 * Even if vlan rx accel is disabled, on some chips
2732 * RXFCB_VLN is pseudo randomly set.
2734 if (dev->features & NETIF_F_HW_VLAN_RX &&
2735 fcb->flags & RXFCB_VLN)
2736 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2738 /* Send the packet up the stack */
2739 ret = napi_gro_receive(napi, skb);
2741 if (unlikely(GRO_DROP == ret))
2742 atomic64_inc(&priv->extra_stats.kernel_dropped);
2745 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2746 * until the budget/quota has been reached. Returns the number
2749 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2751 struct net_device *dev = rx_queue->dev;
2752 struct rxbd8 *bdp, *base;
2753 struct sk_buff *skb;
2757 struct gfar_private *priv = netdev_priv(dev);
2759 /* Get the first full descriptor */
2760 bdp = rx_queue->cur_rx;
2761 base = rx_queue->rx_bd_base;
2763 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2765 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2766 struct sk_buff *newskb;
2770 /* Add another skb for the future */
2771 newskb = gfar_new_skb(dev);
2773 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2775 dma_unmap_single(priv->dev, bdp->bufPtr,
2776 priv->rx_buffer_size, DMA_FROM_DEVICE);
2778 if (unlikely(!(bdp->status & RXBD_ERR) &&
2779 bdp->length > priv->rx_buffer_size))
2780 bdp->status = RXBD_LARGE;
2782 /* We drop the frame if we failed to allocate a new buffer */
2783 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2784 bdp->status & RXBD_ERR)) {
2785 count_errors(bdp->status, dev);
2787 if (unlikely(!newskb))
2792 /* Increment the number of packets */
2793 rx_queue->stats.rx_packets++;
2797 pkt_len = bdp->length - ETH_FCS_LEN;
2798 /* Remove the FCS from the packet length */
2799 skb_put(skb, pkt_len);
2800 rx_queue->stats.rx_bytes += pkt_len;
2801 skb_record_rx_queue(skb, rx_queue->qindex);
2802 gfar_process_frame(dev, skb, amount_pull,
2803 &rx_queue->grp->napi);
2806 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2807 rx_queue->stats.rx_dropped++;
2808 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2813 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2815 /* Setup the new bdp */
2816 gfar_new_rxbdp(rx_queue, bdp, newskb);
2818 /* Update to the next pointer */
2819 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2821 /* update to point at the next skb */
2822 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2823 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2826 /* Update the current rxbd pointer to be the next one */
2827 rx_queue->cur_rx = bdp;
2832 static int gfar_poll(struct napi_struct *napi, int budget)
2834 struct gfar_priv_grp *gfargrp =
2835 container_of(napi, struct gfar_priv_grp, napi);
2836 struct gfar_private *priv = gfargrp->priv;
2837 struct gfar __iomem *regs = gfargrp->regs;
2838 struct gfar_priv_tx_q *tx_queue = NULL;
2839 struct gfar_priv_rx_q *rx_queue = NULL;
2840 int work_done = 0, work_done_per_q = 0;
2841 int i, budget_per_q = 0;
2843 unsigned long rstat_rxf;
2846 /* Clear IEVENT, so interrupts aren't called again
2847 * because of the packets that have already arrived
2849 gfar_write(®s->ievent, IEVENT_RTX_MASK);
2851 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK;
2853 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2855 budget_per_q = budget/num_act_queues;
2859 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2860 tx_queue = priv->tx_queue[i];
2861 /* run Tx cleanup to completion */
2862 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2863 gfar_clean_tx_ring(tx_queue);
2868 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2869 /* skip queue if not active */
2870 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2873 rx_queue = priv->rx_queue[i];
2875 gfar_clean_rx_ring(rx_queue, budget_per_q);
2876 work_done += work_done_per_q;
2878 /* finished processing this queue */
2879 if (work_done_per_q < budget_per_q) {
2880 /* clear active queue hw indication */
2881 gfar_write(®s->rstat,
2882 RSTAT_CLEAR_RXF0 >> i);
2883 rstat_rxf &= ~(RSTAT_CLEAR_RXF0 >> i);
2886 if (!num_act_queues)
2888 /* recompute budget per Rx queue */
2890 (budget - work_done) / num_act_queues;
2894 if (work_done >= budget)
2897 if (!num_act_queues && !has_tx_work) {
2899 napi_complete(napi);
2901 /* Clear the halt bit in RSTAT */
2902 gfar_write(®s->rstat, gfargrp->rstat);
2904 gfar_write(®s->imask, IMASK_DEFAULT);
2906 /* If we are coalescing interrupts, update the timer
2907 * Otherwise, clear it
2909 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2910 gfargrp->tx_bit_map);
2918 #ifdef CONFIG_NET_POLL_CONTROLLER
2919 /* Polling 'interrupt' - used by things like netconsole to send skbs
2920 * without having to re-enable interrupts. It's not called while
2921 * the interrupt routine is executing.
2923 static void gfar_netpoll(struct net_device *dev)
2925 struct gfar_private *priv = netdev_priv(dev);
2928 /* If the device has multiple interrupts, run tx/rx */
2929 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2930 for (i = 0; i < priv->num_grps; i++) {
2931 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2933 disable_irq(gfar_irq(grp, TX)->irq);
2934 disable_irq(gfar_irq(grp, RX)->irq);
2935 disable_irq(gfar_irq(grp, ER)->irq);
2936 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2937 enable_irq(gfar_irq(grp, ER)->irq);
2938 enable_irq(gfar_irq(grp, RX)->irq);
2939 enable_irq(gfar_irq(grp, TX)->irq);
2942 for (i = 0; i < priv->num_grps; i++) {
2943 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2945 disable_irq(gfar_irq(grp, TX)->irq);
2946 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2947 enable_irq(gfar_irq(grp, TX)->irq);
2953 /* The interrupt handler for devices with one interrupt */
2954 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2956 struct gfar_priv_grp *gfargrp = grp_id;
2958 /* Save ievent for future reference */
2959 u32 events = gfar_read(&gfargrp->regs->ievent);
2961 /* Check for reception */
2962 if (events & IEVENT_RX_MASK)
2963 gfar_receive(irq, grp_id);
2965 /* Check for transmit completion */
2966 if (events & IEVENT_TX_MASK)
2967 gfar_transmit(irq, grp_id);
2969 /* Check for errors */
2970 if (events & IEVENT_ERR_MASK)
2971 gfar_error(irq, grp_id);
2976 /* Called every time the controller might need to be made
2977 * aware of new link state. The PHY code conveys this
2978 * information through variables in the phydev structure, and this
2979 * function converts those variables into the appropriate
2980 * register values, and can bring down the device if needed.
2982 static void adjust_link(struct net_device *dev)
2984 struct gfar_private *priv = netdev_priv(dev);
2985 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2986 unsigned long flags;
2987 struct phy_device *phydev = priv->phydev;
2990 local_irq_save(flags);
2994 u32 tempval = gfar_read(®s->maccfg2);
2995 u32 ecntrl = gfar_read(®s->ecntrl);
2997 /* Now we make sure that we can be in full duplex mode.
2998 * If not, we operate in half-duplex mode.
3000 if (phydev->duplex != priv->oldduplex) {
3002 if (!(phydev->duplex))
3003 tempval &= ~(MACCFG2_FULL_DUPLEX);
3005 tempval |= MACCFG2_FULL_DUPLEX;
3007 priv->oldduplex = phydev->duplex;
3010 if (phydev->speed != priv->oldspeed) {
3012 switch (phydev->speed) {
3015 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3017 ecntrl &= ~(ECNTRL_R100);
3022 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3024 /* Reduced mode distinguishes
3025 * between 10 and 100
3027 if (phydev->speed == SPEED_100)
3028 ecntrl |= ECNTRL_R100;
3030 ecntrl &= ~(ECNTRL_R100);
3033 netif_warn(priv, link, dev,
3034 "Ack! Speed (%d) is not 10/100/1000!\n",
3039 priv->oldspeed = phydev->speed;
3042 gfar_write(®s->maccfg2, tempval);
3043 gfar_write(®s->ecntrl, ecntrl);
3045 if (!priv->oldlink) {
3049 } else if (priv->oldlink) {
3053 priv->oldduplex = -1;
3056 if (new_state && netif_msg_link(priv))
3057 phy_print_status(phydev);
3059 local_irq_restore(flags);
3062 /* Update the hash table based on the current list of multicast
3063 * addresses we subscribe to. Also, change the promiscuity of
3064 * the device based on the flags (this function is called
3065 * whenever dev->flags is changed
3067 static void gfar_set_multi(struct net_device *dev)
3069 struct netdev_hw_addr *ha;
3070 struct gfar_private *priv = netdev_priv(dev);
3071 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3074 if (dev->flags & IFF_PROMISC) {
3075 /* Set RCTRL to PROM */
3076 tempval = gfar_read(®s->rctrl);
3077 tempval |= RCTRL_PROM;
3078 gfar_write(®s->rctrl, tempval);
3080 /* Set RCTRL to not PROM */
3081 tempval = gfar_read(®s->rctrl);
3082 tempval &= ~(RCTRL_PROM);
3083 gfar_write(®s->rctrl, tempval);
3086 if (dev->flags & IFF_ALLMULTI) {
3087 /* Set the hash to rx all multicast frames */
3088 gfar_write(®s->igaddr0, 0xffffffff);
3089 gfar_write(®s->igaddr1, 0xffffffff);
3090 gfar_write(®s->igaddr2, 0xffffffff);
3091 gfar_write(®s->igaddr3, 0xffffffff);
3092 gfar_write(®s->igaddr4, 0xffffffff);
3093 gfar_write(®s->igaddr5, 0xffffffff);
3094 gfar_write(®s->igaddr6, 0xffffffff);
3095 gfar_write(®s->igaddr7, 0xffffffff);
3096 gfar_write(®s->gaddr0, 0xffffffff);
3097 gfar_write(®s->gaddr1, 0xffffffff);
3098 gfar_write(®s->gaddr2, 0xffffffff);
3099 gfar_write(®s->gaddr3, 0xffffffff);
3100 gfar_write(®s->gaddr4, 0xffffffff);
3101 gfar_write(®s->gaddr5, 0xffffffff);
3102 gfar_write(®s->gaddr6, 0xffffffff);
3103 gfar_write(®s->gaddr7, 0xffffffff);
3108 /* zero out the hash */
3109 gfar_write(®s->igaddr0, 0x0);
3110 gfar_write(®s->igaddr1, 0x0);
3111 gfar_write(®s->igaddr2, 0x0);
3112 gfar_write(®s->igaddr3, 0x0);
3113 gfar_write(®s->igaddr4, 0x0);
3114 gfar_write(®s->igaddr5, 0x0);
3115 gfar_write(®s->igaddr6, 0x0);
3116 gfar_write(®s->igaddr7, 0x0);
3117 gfar_write(®s->gaddr0, 0x0);
3118 gfar_write(®s->gaddr1, 0x0);
3119 gfar_write(®s->gaddr2, 0x0);
3120 gfar_write(®s->gaddr3, 0x0);
3121 gfar_write(®s->gaddr4, 0x0);
3122 gfar_write(®s->gaddr5, 0x0);
3123 gfar_write(®s->gaddr6, 0x0);
3124 gfar_write(®s->gaddr7, 0x0);
3126 /* If we have extended hash tables, we need to
3127 * clear the exact match registers to prepare for
3130 if (priv->extended_hash) {
3131 em_num = GFAR_EM_NUM + 1;
3132 gfar_clear_exact_match(dev);
3139 if (netdev_mc_empty(dev))
3142 /* Parse the list, and set the appropriate bits */
3143 netdev_for_each_mc_addr(ha, dev) {
3145 gfar_set_mac_for_addr(dev, idx, ha->addr);
3148 gfar_set_hash_for_addr(dev, ha->addr);
3154 /* Clears each of the exact match registers to zero, so they
3155 * don't interfere with normal reception
3157 static void gfar_clear_exact_match(struct net_device *dev)
3160 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3162 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3163 gfar_set_mac_for_addr(dev, idx, zero_arr);
3166 /* Set the appropriate hash bit for the given addr */
3167 /* The algorithm works like so:
3168 * 1) Take the Destination Address (ie the multicast address), and
3169 * do a CRC on it (little endian), and reverse the bits of the
3171 * 2) Use the 8 most significant bits as a hash into a 256-entry
3172 * table. The table is controlled through 8 32-bit registers:
3173 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3174 * gaddr7. This means that the 3 most significant bits in the
3175 * hash index which gaddr register to use, and the 5 other bits
3176 * indicate which bit (assuming an IBM numbering scheme, which
3177 * for PowerPC (tm) is usually the case) in the register holds
3180 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3183 struct gfar_private *priv = netdev_priv(dev);
3184 u32 result = ether_crc(ETH_ALEN, addr);
3185 int width = priv->hash_width;
3186 u8 whichbit = (result >> (32 - width)) & 0x1f;
3187 u8 whichreg = result >> (32 - width + 5);
3188 u32 value = (1 << (31-whichbit));
3190 tempval = gfar_read(priv->hash_regs[whichreg]);
3192 gfar_write(priv->hash_regs[whichreg], tempval);
3196 /* There are multiple MAC Address register pairs on some controllers
3197 * This function sets the numth pair to a given address
3199 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3202 struct gfar_private *priv = netdev_priv(dev);
3203 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3205 char tmpbuf[ETH_ALEN];
3207 u32 __iomem *macptr = ®s->macstnaddr1;
3211 /* Now copy it into the mac registers backwards, cuz
3212 * little endian is silly
3214 for (idx = 0; idx < ETH_ALEN; idx++)
3215 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3217 gfar_write(macptr, *((u32 *) (tmpbuf)));
3219 tempval = *((u32 *) (tmpbuf + 4));
3221 gfar_write(macptr+1, tempval);
3224 /* GFAR error interrupt handler */
3225 static irqreturn_t gfar_error(int irq, void *grp_id)
3227 struct gfar_priv_grp *gfargrp = grp_id;
3228 struct gfar __iomem *regs = gfargrp->regs;
3229 struct gfar_private *priv= gfargrp->priv;
3230 struct net_device *dev = priv->ndev;
3232 /* Save ievent for future reference */
3233 u32 events = gfar_read(®s->ievent);
3236 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
3238 /* Magic Packet is not an error. */
3239 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3240 (events & IEVENT_MAG))
3241 events &= ~IEVENT_MAG;
3244 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3246 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3247 events, gfar_read(®s->imask));
3249 /* Update the error counters */
3250 if (events & IEVENT_TXE) {
3251 dev->stats.tx_errors++;
3253 if (events & IEVENT_LC)
3254 dev->stats.tx_window_errors++;
3255 if (events & IEVENT_CRL)
3256 dev->stats.tx_aborted_errors++;
3257 if (events & IEVENT_XFUN) {
3258 unsigned long flags;
3260 netif_dbg(priv, tx_err, dev,
3261 "TX FIFO underrun, packet dropped\n");
3262 dev->stats.tx_dropped++;
3263 atomic64_inc(&priv->extra_stats.tx_underrun);
3265 local_irq_save(flags);
3268 /* Reactivate the Tx Queues */
3269 gfar_write(®s->tstat, gfargrp->tstat);
3272 local_irq_restore(flags);
3274 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3276 if (events & IEVENT_BSY) {
3277 dev->stats.rx_errors++;
3278 atomic64_inc(&priv->extra_stats.rx_bsy);
3280 gfar_receive(irq, grp_id);
3282 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3283 gfar_read(®s->rstat));
3285 if (events & IEVENT_BABR) {
3286 dev->stats.rx_errors++;
3287 atomic64_inc(&priv->extra_stats.rx_babr);
3289 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3291 if (events & IEVENT_EBERR) {
3292 atomic64_inc(&priv->extra_stats.eberr);
3293 netif_dbg(priv, rx_err, dev, "bus error\n");
3295 if (events & IEVENT_RXC)
3296 netif_dbg(priv, rx_status, dev, "control frame\n");
3298 if (events & IEVENT_BABT) {
3299 atomic64_inc(&priv->extra_stats.tx_babt);
3300 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3305 static struct of_device_id gfar_match[] =
3309 .compatible = "gianfar",
3312 .compatible = "fsl,etsec2",
3316 MODULE_DEVICE_TABLE(of, gfar_match);
3318 /* Structure for a device driver */
3319 static struct platform_driver gfar_driver = {
3321 .name = "fsl-gianfar",
3322 .owner = THIS_MODULE,
3324 .of_match_table = gfar_match,
3326 .probe = gfar_probe,
3327 .remove = gfar_remove,
3330 module_platform_driver(gfar_driver);