drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/of_mdio.h>
  82 #include <linux/of_platform.h>
  83 #include <linux/ip.h>
  84 #include <linux/tcp.h>
  85 #include <linux/udp.h>
  86 #include <linux/in.h>
  87 #include <linux/net_tstamp.h>
  88
  89 #include <asm/io.h>
  90 #include <asm/reg.h>
  91 #include <asm/irq.h>
  92 #include <asm/uaccess.h>
  93 #include <linux/module.h>
  94 #include <linux/dma-mapping.h>
  95 #include <linux/crc32.h>
  96 #include <linux/mii.h>
  97 #include <linux/phy.h>
  98 #include <linux/phy_fixed.h>
  99 #include <linux/of.h>
 100 #include <linux/of_net.h>
 101
 102 #include "gianfar.h"
 103
 104 #define TX_TIMEOUT      (1*HZ)
 105
 106 const char gfar_driver_version[] = "1.3";
 107
 108 static int gfar_enet_open(struct net_device *dev);
 109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 110 static void gfar_reset_task(struct work_struct *work);
 111 static void gfar_timeout(struct net_device *dev);
 112 static int gfar_close(struct net_device *dev);
 113 struct sk_buff *gfar_new_skb(struct net_device *dev);
 114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 115                            struct sk_buff *skb);
 116 static int gfar_set_mac_address(struct net_device *dev);
 117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 118 static irqreturn_t gfar_error(int irq, void *dev_id);
 119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 121 static void adjust_link(struct net_device *dev);
 122 static void init_registers(struct net_device *dev);
 123 static int init_phy(struct net_device *dev);
 124 static int gfar_probe(struct platform_device *ofdev);
 125 static int gfar_remove(struct platform_device *ofdev);
 126 static void free_skb_resources(struct gfar_private *priv);
 127 static void gfar_set_multi(struct net_device *dev);
 128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 129 static void gfar_configure_serdes(struct net_device *dev);
 130 static int gfar_poll(struct napi_struct *napi, int budget);
 131 #ifdef CONFIG_NET_POLL_CONTROLLER
 132 static void gfar_netpoll(struct net_device *dev);
 133 #endif
 134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 136 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 137                               int amount_pull, struct napi_struct *napi);
 138 void gfar_halt(struct net_device *dev);
 139 static void gfar_halt_nodisable(struct net_device *dev);
 140 void gfar_start(struct net_device *dev);
 141 static void gfar_clear_exact_match(struct net_device *dev);
 142 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 143                                   const u8 *addr);
 144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 145
 146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 148 MODULE_LICENSE("GPL");
 149
 150 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 151                             dma_addr_t buf)
 152 {
 153         u32 lstatus;
 154
 155         bdp->bufPtr = buf;
 156
 157         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 158         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 159                 lstatus |= BD_LFLAG(RXBD_WRAP);
 160
 161         eieio();
 162
 163         bdp->lstatus = lstatus;
 164 }
 165
 166 static int gfar_init_bds(struct net_device *ndev)
 167 {
 168         struct gfar_private *priv = netdev_priv(ndev);
 169         struct gfar_priv_tx_q *tx_queue = NULL;
 170         struct gfar_priv_rx_q *rx_queue = NULL;
 171         struct txbd8 *txbdp;
 172         struct rxbd8 *rxbdp;
 173         int i, j;
 174
 175         for (i = 0; i < priv->num_tx_queues; i++) {
 176                 tx_queue = priv->tx_queue[i];
 177                 /* Initialize some variables in our dev structure */
 178                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 179                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 180                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 181                 tx_queue->skb_curtx = 0;
 182                 tx_queue->skb_dirtytx = 0;
 183
 184                 /* Initialize Transmit Descriptor Ring */
 185                 txbdp = tx_queue->tx_bd_base;
 186                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 187                         txbdp->lstatus = 0;
 188                         txbdp->bufPtr = 0;
 189                         txbdp++;
 190                 }
 191
 192                 /* Set the last descriptor in the ring to indicate wrap */
 193                 txbdp--;
 194                 txbdp->status |= TXBD_WRAP;
 195         }
 196
 197         for (i = 0; i < priv->num_rx_queues; i++) {
 198                 rx_queue = priv->rx_queue[i];
 199                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 200                 rx_queue->skb_currx = 0;
 201                 rxbdp = rx_queue->rx_bd_base;
 202
 203                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 204                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 205
 206                         if (skb) {
 207                                 gfar_init_rxbdp(rx_queue, rxbdp,
 208                                                 rxbdp->bufPtr);
 209                         } else {
 210                                 skb = gfar_new_skb(ndev);
 211                                 if (!skb) {
 212                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 213                                         return -ENOMEM;
 214                                 }
 215                                 rx_queue->rx_skbuff[j] = skb;
 216
 217                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 218                         }
 219
 220                         rxbdp++;
 221                 }
 222
 223         }
 224
 225         return 0;
 226 }
 227
 228 static int gfar_alloc_skb_resources(struct net_device *ndev)
 229 {
 230         void *vaddr;
 231         dma_addr_t addr;
 232         int i, j, k;
 233         struct gfar_private *priv = netdev_priv(ndev);
 234         struct device *dev = &priv->ofdev->dev;
 235         struct gfar_priv_tx_q *tx_queue = NULL;
 236         struct gfar_priv_rx_q *rx_queue = NULL;
 237
 238         priv->total_tx_ring_size = 0;
 239         for (i = 0; i < priv->num_tx_queues; i++)
 240                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 241
 242         priv->total_rx_ring_size = 0;
 243         for (i = 0; i < priv->num_rx_queues; i++)
 244                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 245
 246         /* Allocate memory for the buffer descriptors */
 247         vaddr = dma_alloc_coherent(dev,
 248                         sizeof(struct txbd8) * priv->total_tx_ring_size +
 249                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
 250                         &addr, GFP_KERNEL);
 251         if (!vaddr) {
 252                 netif_err(priv, ifup, ndev,
 253                           "Could not allocate buffer descriptors!\n");
 254                 return -ENOMEM;
 255         }
 256
 257         for (i = 0; i < priv->num_tx_queues; i++) {
 258                 tx_queue = priv->tx_queue[i];
 259                 tx_queue->tx_bd_base = vaddr;
 260                 tx_queue->tx_bd_dma_base = addr;
 261                 tx_queue->dev = ndev;
 262                 /* enet DMA only understands physical addresses */
 263                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 264                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 265         }
 266
 267         /* Start the rx descriptor ring where the tx ring leaves off */
 268         for (i = 0; i < priv->num_rx_queues; i++) {
 269                 rx_queue = priv->rx_queue[i];
 270                 rx_queue->rx_bd_base = vaddr;
 271                 rx_queue->rx_bd_dma_base = addr;
 272                 rx_queue->dev = ndev;
 273                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 274                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 275         }
 276
 277         /* Setup the skbuff rings */
 278         for (i = 0; i < priv->num_tx_queues; i++) {
 279                 tx_queue = priv->tx_queue[i];
 280                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
 281                                               tx_queue->tx_ring_size,
 282                                               GFP_KERNEL);
 283                 if (!tx_queue->tx_skbuff) {
 284                         netif_err(priv, ifup, ndev,
 285                                   "Could not allocate tx_skbuff\n");
 286                         goto cleanup;
 287                 }
 288
 289                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 290                         tx_queue->tx_skbuff[k] = NULL;
 291         }
 292
 293         for (i = 0; i < priv->num_rx_queues; i++) {
 294                 rx_queue = priv->rx_queue[i];
 295                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
 296                                               rx_queue->rx_ring_size,
 297                                               GFP_KERNEL);
 298
 299                 if (!rx_queue->rx_skbuff) {
 300                         netif_err(priv, ifup, ndev,
 301                                   "Could not allocate rx_skbuff\n");
 302                         goto cleanup;
 303                 }
 304
 305                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 306                         rx_queue->rx_skbuff[j] = NULL;
 307         }
 308
 309         if (gfar_init_bds(ndev))
 310                 goto cleanup;
 311
 312         return 0;
 313
 314 cleanup:
 315         free_skb_resources(priv);
 316         return -ENOMEM;
 317 }
 318
 319 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 320 {
 321         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 322         u32 __iomem *baddr;
 323         int i;
 324
 325         baddr = &regs->tbase0;
 326         for (i = 0; i < priv->num_tx_queues; i++) {
 327                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 328                 baddr += 2;
 329         }
 330
 331         baddr = &regs->rbase0;
 332         for (i = 0; i < priv->num_rx_queues; i++) {
 333                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 334                 baddr += 2;
 335         }
 336 }
 337
 338 static void gfar_init_mac(struct net_device *ndev)
 339 {
 340         struct gfar_private *priv = netdev_priv(ndev);
 341         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 342         u32 rctrl = 0;
 343         u32 tctrl = 0;
 344         u32 attrs = 0;
 345
 346         /* write the tx/rx base registers */
 347         gfar_init_tx_rx_base(priv);
 348
 349         /* Configure the coalescing support */
 350         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 351
 352         if (priv->rx_filer_enable) {
 353                 rctrl |= RCTRL_FILREN;
 354                 /* Program the RIR0 reg with the required distribution */
 355                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 356         }
 357
 358         /* Restore PROMISC mode */
 359         if (ndev->flags & IFF_PROMISC)
 360                 rctrl |= RCTRL_PROM;
 361
 362         if (ndev->features & NETIF_F_RXCSUM)
 363                 rctrl |= RCTRL_CHECKSUMMING;
 364
 365         if (priv->extended_hash) {
 366                 rctrl |= RCTRL_EXTHASH;
 367
 368                 gfar_clear_exact_match(ndev);
 369                 rctrl |= RCTRL_EMEN;
 370         }
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Insert receive time stamps into padding alignment bytes */
 378         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 379                 rctrl &= ~RCTRL_PAL_MASK;
 380                 rctrl |= RCTRL_PADDING(8);
 381                 priv->padding = 8;
 382         }
 383
 384         /* Enable HW time stamping if requested from user space */
 385         if (priv->hwts_rx_en)
 386                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 387
 388         if (ndev->features & NETIF_F_HW_VLAN_RX)
 389                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 390
 391         /* Init rctrl based on our settings */
 392         gfar_write(&regs->rctrl, rctrl);
 393
 394         if (ndev->features & NETIF_F_IP_CSUM)
 395                 tctrl |= TCTRL_INIT_CSUM;
 396
 397         if (priv->prio_sched_en)
 398                 tctrl |= TCTRL_TXSCHED_PRIO;
 399         else {
 400                 tctrl |= TCTRL_TXSCHED_WRRS;
 401                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 402                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 403         }
 404
 405         gfar_write(&regs->tctrl, tctrl);
 406
 407         /* Set the extraction length and index */
 408         attrs = ATTRELI_EL(priv->rx_stash_size) |
 409                 ATTRELI_EI(priv->rx_stash_index);
 410
 411         gfar_write(&regs->attreli, attrs);
 412
 413         /* Start with defaults, and add stashing or locking
 414          * depending on the approprate variables
 415          */
 416         attrs = ATTR_INIT_SETTINGS;
 417
 418         if (priv->bd_stash_en)
 419                 attrs |= ATTR_BDSTASH;
 420
 421         if (priv->rx_stash_size != 0)
 422                 attrs |= ATTR_BUFSTASH;
 423
 424         gfar_write(&regs->attr, attrs);
 425
 426         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 427         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 428         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 429 }
 430
 431 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 432 {
 433         struct gfar_private *priv = netdev_priv(dev);
 434         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 435         unsigned long tx_packets = 0, tx_bytes = 0;
 436         int i;
 437
 438         for (i = 0; i < priv->num_rx_queues; i++) {
 439                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 440                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 441                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 442         }
 443
 444         dev->stats.rx_packets = rx_packets;
 445         dev->stats.rx_bytes   = rx_bytes;
 446         dev->stats.rx_dropped = rx_dropped;
 447
 448         for (i = 0; i < priv->num_tx_queues; i++) {
 449                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 450                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 451         }
 452
 453         dev->stats.tx_bytes   = tx_bytes;
 454         dev->stats.tx_packets = tx_packets;
 455
 456         return &dev->stats;
 457 }
 458
 459 static const struct net_device_ops gfar_netdev_ops = {
 460         .ndo_open = gfar_enet_open,
 461         .ndo_start_xmit = gfar_start_xmit,
 462         .ndo_stop = gfar_close,
 463         .ndo_change_mtu = gfar_change_mtu,
 464         .ndo_set_features = gfar_set_features,
 465         .ndo_set_rx_mode = gfar_set_multi,
 466         .ndo_tx_timeout = gfar_timeout,
 467         .ndo_do_ioctl = gfar_ioctl,
 468         .ndo_get_stats = gfar_get_stats,
 469         .ndo_set_mac_address = eth_mac_addr,
 470         .ndo_validate_addr = eth_validate_addr,
 471 #ifdef CONFIG_NET_POLL_CONTROLLER
 472         .ndo_poll_controller = gfar_netpoll,
 473 #endif
 474 };
 475
 476 void lock_rx_qs(struct gfar_private *priv)
 477 {
 478         int i;
 479
 480         for (i = 0; i < priv->num_rx_queues; i++)
 481                 spin_lock(&priv->rx_queue[i]->rxlock);
 482 }
 483
 484 void lock_tx_qs(struct gfar_private *priv)
 485 {
 486         int i;
 487
 488         for (i = 0; i < priv->num_tx_queues; i++)
 489                 spin_lock(&priv->tx_queue[i]->txlock);
 490 }
 491
 492 void unlock_rx_qs(struct gfar_private *priv)
 493 {
 494         int i;
 495
 496         for (i = 0; i < priv->num_rx_queues; i++)
 497                 spin_unlock(&priv->rx_queue[i]->rxlock);
 498 }
 499
 500 void unlock_tx_qs(struct gfar_private *priv)
 501 {
 502         int i;
 503
 504         for (i = 0; i < priv->num_tx_queues; i++)
 505                 spin_unlock(&priv->tx_queue[i]->txlock);
 506 }
 507
 508 static bool gfar_is_vlan_on(struct gfar_private *priv)
 509 {
 510         return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
 511                (priv->ndev->features & NETIF_F_HW_VLAN_TX);
 512 }
 513
 514 /* Returns 1 if incoming frames use an FCB */
 515 static inline int gfar_uses_fcb(struct gfar_private *priv)
 516 {
 517         return gfar_is_vlan_on(priv) ||
 518                (priv->ndev->features & NETIF_F_RXCSUM) ||
 519                (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
 520 }
 521
 522 static void free_tx_pointers(struct gfar_private *priv)
 523 {
 524         int i;
 525
 526         for (i = 0; i < priv->num_tx_queues; i++)
 527                 kfree(priv->tx_queue[i]);
 528 }
 529
 530 static void free_rx_pointers(struct gfar_private *priv)
 531 {
 532         int i;
 533
 534         for (i = 0; i < priv->num_rx_queues; i++)
 535                 kfree(priv->rx_queue[i]);
 536 }
 537
 538 static void unmap_group_regs(struct gfar_private *priv)
 539 {
 540         int i;
 541
 542         for (i = 0; i < MAXGROUPS; i++)
 543                 if (priv->gfargrp[i].regs)
 544                         iounmap(priv->gfargrp[i].regs);
 545 }
 546
 547 static void disable_napi(struct gfar_private *priv)
 548 {
 549         int i;
 550
 551         for (i = 0; i < priv->num_grps; i++)
 552                 napi_disable(&priv->gfargrp[i].napi);
 553 }
 554
 555 static void enable_napi(struct gfar_private *priv)
 556 {
 557         int i;
 558
 559         for (i = 0; i < priv->num_grps; i++)
 560                 napi_enable(&priv->gfargrp[i].napi);
 561 }
 562
 563 static int gfar_parse_group(struct device_node *np,
 564                             struct gfar_private *priv, const char *model)
 565 {
 566         u32 *queue_mask;
 567
 568         priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
 569         if (!priv->gfargrp[priv->num_grps].regs)
 570                 return -ENOMEM;
 571
 572         priv->gfargrp[priv->num_grps].interruptTransmit =
 573                         irq_of_parse_and_map(np, 0);
 574
 575         /* If we aren't the FEC we have multiple interrupts */
 576         if (model && strcasecmp(model, "FEC")) {
 577                 priv->gfargrp[priv->num_grps].interruptReceive =
 578                         irq_of_parse_and_map(np, 1);
 579                 priv->gfargrp[priv->num_grps].interruptError =
 580                         irq_of_parse_and_map(np,2);
 581                 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
 582                     priv->gfargrp[priv->num_grps].interruptReceive  == NO_IRQ ||
 583                     priv->gfargrp[priv->num_grps].interruptError    == NO_IRQ)
 584                         return -EINVAL;
 585         }
 586
 587         priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
 588         priv->gfargrp[priv->num_grps].priv = priv;
 589         spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
 590         if (priv->mode == MQ_MG_MODE) {
 591                 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
 592                 priv->gfargrp[priv->num_grps].rx_bit_map = queue_mask ?
 593                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 594                 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
 595                 priv->gfargrp[priv->num_grps].tx_bit_map = queue_mask ?
 596                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 597         } else {
 598                 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
 599                 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
 600         }
 601         priv->num_grps++;
 602
 603         return 0;
 604 }
 605
 606 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 607 {
 608         const char *model;
 609         const char *ctype;
 610         const void *mac_addr;
 611         int err = 0, i;
 612         struct net_device *dev = NULL;
 613         struct gfar_private *priv = NULL;
 614         struct device_node *np = ofdev->dev.of_node;
 615         struct device_node *child = NULL;
 616         const u32 *stash;
 617         const u32 *stash_len;
 618         const u32 *stash_idx;
 619         unsigned int num_tx_qs, num_rx_qs;
 620         u32 *tx_queues, *rx_queues;
 621
 622         if (!np || !of_device_is_available(np))
 623                 return -ENODEV;
 624
 625         /* parse the num of tx and rx queues */
 626         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 627         num_tx_qs = tx_queues ? *tx_queues : 1;
 628
 629         if (num_tx_qs > MAX_TX_QS) {
 630                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 631                        num_tx_qs, MAX_TX_QS);
 632                 pr_err("Cannot do alloc_etherdev, aborting\n");
 633                 return -EINVAL;
 634         }
 635
 636         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 637         num_rx_qs = rx_queues ? *rx_queues : 1;
 638
 639         if (num_rx_qs > MAX_RX_QS) {
 640                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 641                        num_rx_qs, MAX_RX_QS);
 642                 pr_err("Cannot do alloc_etherdev, aborting\n");
 643                 return -EINVAL;
 644         }
 645
 646         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 647         dev = *pdev;
 648         if (NULL == dev)
 649                 return -ENOMEM;
 650
 651         priv = netdev_priv(dev);
 652         priv->node = ofdev->dev.of_node;
 653         priv->ndev = dev;
 654
 655         priv->num_tx_queues = num_tx_qs;
 656         netif_set_real_num_rx_queues(dev, num_rx_qs);
 657         priv->num_rx_queues = num_rx_qs;
 658         priv->num_grps = 0x0;
 659
 660         /* Init Rx queue filer rule set linked list */
 661         INIT_LIST_HEAD(&priv->rx_list.list);
 662         priv->rx_list.count = 0;
 663         mutex_init(&priv->rx_queue_access);
 664
 665         model = of_get_property(np, "model", NULL);
 666
 667         for (i = 0; i < MAXGROUPS; i++)
 668                 priv->gfargrp[i].regs = NULL;
 669
 670         /* Parse and initialize group specific information */
 671         if (of_device_is_compatible(np, "fsl,etsec2")) {
 672                 priv->mode = MQ_MG_MODE;
 673                 for_each_child_of_node(np, child) {
 674                         err = gfar_parse_group(child, priv, model);
 675                         if (err)
 676                                 goto err_grp_init;
 677                 }
 678         } else {
 679                 priv->mode = SQ_SG_MODE;
 680                 err = gfar_parse_group(np, priv, model);
 681                 if (err)
 682                         goto err_grp_init;
 683         }
 684
 685         for (i = 0; i < priv->num_tx_queues; i++)
 686                priv->tx_queue[i] = NULL;
 687         for (i = 0; i < priv->num_rx_queues; i++)
 688                 priv->rx_queue[i] = NULL;
 689
 690         for (i = 0; i < priv->num_tx_queues; i++) {
 691                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 692                                             GFP_KERNEL);
 693                 if (!priv->tx_queue[i]) {
 694                         err = -ENOMEM;
 695                         goto tx_alloc_failed;
 696                 }
 697                 priv->tx_queue[i]->tx_skbuff = NULL;
 698                 priv->tx_queue[i]->qindex = i;
 699                 priv->tx_queue[i]->dev = dev;
 700                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 701         }
 702
 703         for (i = 0; i < priv->num_rx_queues; i++) {
 704                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 705                                             GFP_KERNEL);
 706                 if (!priv->rx_queue[i]) {
 707                         err = -ENOMEM;
 708                         goto rx_alloc_failed;
 709                 }
 710                 priv->rx_queue[i]->rx_skbuff = NULL;
 711                 priv->rx_queue[i]->qindex = i;
 712                 priv->rx_queue[i]->dev = dev;
 713                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 714         }
 715
 716
 717         stash = of_get_property(np, "bd-stash", NULL);
 718
 719         if (stash) {
 720                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 721                 priv->bd_stash_en = 1;
 722         }
 723
 724         stash_len = of_get_property(np, "rx-stash-len", NULL);
 725
 726         if (stash_len)
 727                 priv->rx_stash_size = *stash_len;
 728
 729         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 730
 731         if (stash_idx)
 732                 priv->rx_stash_index = *stash_idx;
 733
 734         if (stash_len || stash_idx)
 735                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 736
 737         mac_addr = of_get_mac_address(np);
 738
 739         if (mac_addr)
 740                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 741
 742         if (model && !strcasecmp(model, "TSEC"))
 743                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 744                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 745                                      FSL_GIANFAR_DEV_HAS_RMON |
 746                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 747
 748         if (model && !strcasecmp(model, "eTSEC"))
 749                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 750                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 751                                      FSL_GIANFAR_DEV_HAS_RMON |
 752                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 753                                      FSL_GIANFAR_DEV_HAS_PADDING |
 754                                      FSL_GIANFAR_DEV_HAS_CSUM |
 755                                      FSL_GIANFAR_DEV_HAS_VLAN |
 756                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 757                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 758                                      FSL_GIANFAR_DEV_HAS_TIMER;
 759
 760         ctype = of_get_property(np, "phy-connection-type", NULL);
 761
 762         /* We only care about rgmii-id.  The rest are autodetected */
 763         if (ctype && !strcmp(ctype, "rgmii-id"))
 764                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 765         else
 766                 priv->interface = PHY_INTERFACE_MODE_MII;
 767
 768         if (of_get_property(np, "fsl,magic-packet", NULL))
 769                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 770
 771         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 772
 773         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 774         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 775
 776         return 0;
 777
 778 rx_alloc_failed:
 779         free_rx_pointers(priv);
 780 tx_alloc_failed:
 781         free_tx_pointers(priv);
 782 err_grp_init:
 783         unmap_group_regs(priv);
 784         free_netdev(dev);
 785         return err;
 786 }
 787
 788 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 789                                struct ifreq *ifr, int cmd)
 790 {
 791         struct hwtstamp_config config;
 792         struct gfar_private *priv = netdev_priv(netdev);
 793
 794         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 795                 return -EFAULT;
 796
 797         /* reserved for future extensions */
 798         if (config.flags)
 799                 return -EINVAL;
 800
 801         switch (config.tx_type) {
 802         case HWTSTAMP_TX_OFF:
 803                 priv->hwts_tx_en = 0;
 804                 break;
 805         case HWTSTAMP_TX_ON:
 806                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 807                         return -ERANGE;
 808                 priv->hwts_tx_en = 1;
 809                 break;
 810         default:
 811                 return -ERANGE;
 812         }
 813
 814         switch (config.rx_filter) {
 815         case HWTSTAMP_FILTER_NONE:
 816                 if (priv->hwts_rx_en) {
 817                         stop_gfar(netdev);
 818                         priv->hwts_rx_en = 0;
 819                         startup_gfar(netdev);
 820                 }
 821                 break;
 822         default:
 823                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 824                         return -ERANGE;
 825                 if (!priv->hwts_rx_en) {
 826                         stop_gfar(netdev);
 827                         priv->hwts_rx_en = 1;
 828                         startup_gfar(netdev);
 829                 }
 830                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 831                 break;
 832         }
 833
 834         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 835                 -EFAULT : 0;
 836 }
 837
 838 /* Ioctl MII Interface */
 839 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 840 {
 841         struct gfar_private *priv = netdev_priv(dev);
 842
 843         if (!netif_running(dev))
 844                 return -EINVAL;
 845
 846         if (cmd == SIOCSHWTSTAMP)
 847                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 848
 849         if (!priv->phydev)
 850                 return -ENODEV;
 851
 852         return phy_mii_ioctl(priv->phydev, rq, cmd);
 853 }
 854
 855 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 856 {
 857         unsigned int new_bit_map = 0x0;
 858         int mask = 0x1 << (max_qs - 1), i;
 859
 860         for (i = 0; i < max_qs; i++) {
 861                 if (bit_map & mask)
 862                         new_bit_map = new_bit_map + (1 << i);
 863                 mask = mask >> 0x1;
 864         }
 865         return new_bit_map;
 866 }
 867
 868 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 869                                    u32 class)
 870 {
 871         u32 rqfpr = FPR_FILER_MASK;
 872         u32 rqfcr = 0x0;
 873
 874         rqfar--;
 875         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 876         priv->ftp_rqfpr[rqfar] = rqfpr;
 877         priv->ftp_rqfcr[rqfar] = rqfcr;
 878         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 879
 880         rqfar--;
 881         rqfcr = RQFCR_CMP_NOMATCH;
 882         priv->ftp_rqfpr[rqfar] = rqfpr;
 883         priv->ftp_rqfcr[rqfar] = rqfcr;
 884         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 885
 886         rqfar--;
 887         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 888         rqfpr = class;
 889         priv->ftp_rqfcr[rqfar] = rqfcr;
 890         priv->ftp_rqfpr[rqfar] = rqfpr;
 891         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 892
 893         rqfar--;
 894         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 895         rqfpr = class;
 896         priv->ftp_rqfcr[rqfar] = rqfcr;
 897         priv->ftp_rqfpr[rqfar] = rqfpr;
 898         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 899
 900         return rqfar;
 901 }
 902
 903 static void gfar_init_filer_table(struct gfar_private *priv)
 904 {
 905         int i = 0x0;
 906         u32 rqfar = MAX_FILER_IDX;
 907         u32 rqfcr = 0x0;
 908         u32 rqfpr = FPR_FILER_MASK;
 909
 910         /* Default rule */
 911         rqfcr = RQFCR_CMP_MATCH;
 912         priv->ftp_rqfcr[rqfar] = rqfcr;
 913         priv->ftp_rqfpr[rqfar] = rqfpr;
 914         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 915
 916         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 917         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 918         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 919         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 920         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 921         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 922
 923         /* cur_filer_idx indicated the first non-masked rule */
 924         priv->cur_filer_idx = rqfar;
 925
 926         /* Rest are masked rules */
 927         rqfcr = RQFCR_CMP_NOMATCH;
 928         for (i = 0; i < rqfar; i++) {
 929                 priv->ftp_rqfcr[i] = rqfcr;
 930                 priv->ftp_rqfpr[i] = rqfpr;
 931                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 932         }
 933 }
 934
 935 static void gfar_detect_errata(struct gfar_private *priv)
 936 {
 937         struct device *dev = &priv->ofdev->dev;
 938         unsigned int pvr = mfspr(SPRN_PVR);
 939         unsigned int svr = mfspr(SPRN_SVR);
 940         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 941         unsigned int rev = svr & 0xffff;
 942
 943         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 944         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 945             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 946                 priv->errata |= GFAR_ERRATA_74;
 947
 948         /* MPC8313 and MPC837x all rev */
 949         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 950             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 951                 priv->errata |= GFAR_ERRATA_76;
 952
 953         /* MPC8313 and MPC837x all rev */
 954         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 955             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 956                 priv->errata |= GFAR_ERRATA_A002;
 957
 958         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
 959         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
 960             (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
 961                 priv->errata |= GFAR_ERRATA_12;
 962
 963         if (priv->errata)
 964                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 965                          priv->errata);
 966 }
 967
 968 /* Set up the ethernet device structure, private data,
 969  * and anything else we need before we start
 970  */
 971 static int gfar_probe(struct platform_device *ofdev)
 972 {
 973         u32 tempval;
 974         struct net_device *dev = NULL;
 975         struct gfar_private *priv = NULL;
 976         struct gfar __iomem *regs = NULL;
 977         int err = 0, i, grp_idx = 0;
 978         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 979         u32 isrg = 0;
 980         u32 __iomem *baddr;
 981
 982         err = gfar_of_init(ofdev, &dev);
 983
 984         if (err)
 985                 return err;
 986
 987         priv = netdev_priv(dev);
 988         priv->ndev = dev;
 989         priv->ofdev = ofdev;
 990         priv->node = ofdev->dev.of_node;
 991         SET_NETDEV_DEV(dev, &ofdev->dev);
 992
 993         spin_lock_init(&priv->bflock);
 994         INIT_WORK(&priv->reset_task, gfar_reset_task);
 995
 996         dev_set_drvdata(&ofdev->dev, priv);
 997         regs = priv->gfargrp[0].regs;
 998
 999         gfar_detect_errata(priv);
1000
1001         /* Stop the DMA engine now, in case it was running before
1002          * (The firmware could have used it, and left it running).
1003          */
1004         gfar_halt(dev);
1005
1006         /* Reset MAC layer */
1007         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1008
1009         /* We need to delay at least 3 TX clocks */
1010         udelay(2);
1011
1012         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1013         gfar_write(&regs->maccfg1, tempval);
1014
1015         /* Initialize MACCFG2. */
1016         tempval = MACCFG2_INIT_SETTINGS;
1017         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1018                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1019         gfar_write(&regs->maccfg2, tempval);
1020
1021         /* Initialize ECNTRL */
1022         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1023
1024         /* Set the dev->base_addr to the gfar reg region */
1025         dev->base_addr = (unsigned long) regs;
1026
1027         SET_NETDEV_DEV(dev, &ofdev->dev);
1028
1029         /* Fill in the dev structure */
1030         dev->watchdog_timeo = TX_TIMEOUT;
1031         dev->mtu = 1500;
1032         dev->netdev_ops = &gfar_netdev_ops;
1033         dev->ethtool_ops = &gfar_ethtool_ops;
1034
1035         /* Register for napi ...We are registering NAPI for each grp */
1036         for (i = 0; i < priv->num_grps; i++)
1037                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1038                                GFAR_DEV_WEIGHT);
1039
1040         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1041                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1042                                    NETIF_F_RXCSUM;
1043                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1044                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1045         }
1046
1047         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1048                 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1049                 dev->features |= NETIF_F_HW_VLAN_RX;
1050         }
1051
1052         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1053                 priv->extended_hash = 1;
1054                 priv->hash_width = 9;
1055
1056                 priv->hash_regs[0] = &regs->igaddr0;
1057                 priv->hash_regs[1] = &regs->igaddr1;
1058                 priv->hash_regs[2] = &regs->igaddr2;
1059                 priv->hash_regs[3] = &regs->igaddr3;
1060                 priv->hash_regs[4] = &regs->igaddr4;
1061                 priv->hash_regs[5] = &regs->igaddr5;
1062                 priv->hash_regs[6] = &regs->igaddr6;
1063                 priv->hash_regs[7] = &regs->igaddr7;
1064                 priv->hash_regs[8] = &regs->gaddr0;
1065                 priv->hash_regs[9] = &regs->gaddr1;
1066                 priv->hash_regs[10] = &regs->gaddr2;
1067                 priv->hash_regs[11] = &regs->gaddr3;
1068                 priv->hash_regs[12] = &regs->gaddr4;
1069                 priv->hash_regs[13] = &regs->gaddr5;
1070                 priv->hash_regs[14] = &regs->gaddr6;
1071                 priv->hash_regs[15] = &regs->gaddr7;
1072
1073         } else {
1074                 priv->extended_hash = 0;
1075                 priv->hash_width = 8;
1076
1077                 priv->hash_regs[0] = &regs->gaddr0;
1078                 priv->hash_regs[1] = &regs->gaddr1;
1079                 priv->hash_regs[2] = &regs->gaddr2;
1080                 priv->hash_regs[3] = &regs->gaddr3;
1081                 priv->hash_regs[4] = &regs->gaddr4;
1082                 priv->hash_regs[5] = &regs->gaddr5;
1083                 priv->hash_regs[6] = &regs->gaddr6;
1084                 priv->hash_regs[7] = &regs->gaddr7;
1085         }
1086
1087         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1088                 priv->padding = DEFAULT_PADDING;
1089         else
1090                 priv->padding = 0;
1091
1092         if (dev->features & NETIF_F_IP_CSUM ||
1093             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1094                 dev->needed_headroom = GMAC_FCB_LEN;
1095
1096         /* Program the isrg regs only if number of grps > 1 */
1097         if (priv->num_grps > 1) {
1098                 baddr = &regs->isrg0;
1099                 for (i = 0; i < priv->num_grps; i++) {
1100                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1101                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1102                         gfar_write(baddr, isrg);
1103                         baddr++;
1104                         isrg = 0x0;
1105                 }
1106         }
1107
1108         /* Need to reverse the bit maps as  bit_map's MSB is q0
1109          * but, for_each_set_bit parses from right to left, which
1110          * basically reverses the queue numbers
1111          */
1112         for (i = 0; i< priv->num_grps; i++) {
1113                 priv->gfargrp[i].tx_bit_map =
1114                         reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1115                 priv->gfargrp[i].rx_bit_map =
1116                         reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1117         }
1118
1119         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1120          * also assign queues to groups
1121          */
1122         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1123                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1124
1125                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1126                                  priv->num_rx_queues) {
1127                         priv->gfargrp[grp_idx].num_rx_queues++;
1128                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1129                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1130                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1131                 }
1132                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1133
1134                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1135                                  priv->num_tx_queues) {
1136                         priv->gfargrp[grp_idx].num_tx_queues++;
1137                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1138                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1139                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1140                 }
1141                 priv->gfargrp[grp_idx].rstat = rstat;
1142                 priv->gfargrp[grp_idx].tstat = tstat;
1143                 rstat = tstat =0;
1144         }
1145
1146         gfar_write(&regs->rqueue, rqueue);
1147         gfar_write(&regs->tqueue, tqueue);
1148
1149         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1150
1151         /* Initializing some of the rx/tx queue level parameters */
1152         for (i = 0; i < priv->num_tx_queues; i++) {
1153                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1154                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1155                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1156                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1157         }
1158
1159         for (i = 0; i < priv->num_rx_queues; i++) {
1160                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1161                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1162                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1163         }
1164
1165         /* always enable rx filer */
1166         priv->rx_filer_enable = 1;
1167         /* Enable most messages by default */
1168         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1169         /* use pritority h/w tx queue scheduling for single queue devices */
1170         if (priv->num_tx_queues == 1)
1171                 priv->prio_sched_en = 1;
1172
1173         /* Carrier starts down, phylib will bring it up */
1174         netif_carrier_off(dev);
1175
1176         err = register_netdev(dev);
1177
1178         if (err) {
1179                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1180                 goto register_fail;
1181         }
1182
1183         device_init_wakeup(&dev->dev,
1184                            priv->device_flags &
1185                            FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1186
1187         /* fill out IRQ number and name fields */
1188         for (i = 0; i < priv->num_grps; i++) {
1189                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1190                         sprintf(priv->gfargrp[i].int_name_tx, "%s%s%c%s",
1191                                 dev->name, "_g", '0' + i, "_tx");
1192                         sprintf(priv->gfargrp[i].int_name_rx, "%s%s%c%s",
1193                                 dev->name, "_g", '0' + i, "_rx");
1194                         sprintf(priv->gfargrp[i].int_name_er, "%s%s%c%s",
1195                                 dev->name, "_g", '0' + i, "_er");
1196                 } else
1197                         strcpy(priv->gfargrp[i].int_name_tx, dev->name);
1198         }
1199
1200         /* Initialize the filer table */
1201         gfar_init_filer_table(priv);
1202
1203         /* Create all the sysfs files */
1204         gfar_init_sysfs(dev);
1205
1206         /* Print out the device info */
1207         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1208
1209         /* Even more device info helps when determining which kernel
1210          * provided which set of benchmarks.
1211          */
1212         netdev_info(dev, "Running with NAPI enabled\n");
1213         for (i = 0; i < priv->num_rx_queues; i++)
1214                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1215                             i, priv->rx_queue[i]->rx_ring_size);
1216         for (i = 0; i < priv->num_tx_queues; i++)
1217                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1218                             i, priv->tx_queue[i]->tx_ring_size);
1219
1220         return 0;
1221
1222 register_fail:
1223         unmap_group_regs(priv);
1224         free_tx_pointers(priv);
1225         free_rx_pointers(priv);
1226         if (priv->phy_node)
1227                 of_node_put(priv->phy_node);
1228         if (priv->tbi_node)
1229                 of_node_put(priv->tbi_node);
1230         free_netdev(dev);
1231         return err;
1232 }
1233
1234 static int gfar_remove(struct platform_device *ofdev)
1235 {
1236         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1237
1238         if (priv->phy_node)
1239                 of_node_put(priv->phy_node);
1240         if (priv->tbi_node)
1241                 of_node_put(priv->tbi_node);
1242
1243         dev_set_drvdata(&ofdev->dev, NULL);
1244
1245         unregister_netdev(priv->ndev);
1246         unmap_group_regs(priv);
1247         free_netdev(priv->ndev);
1248
1249         return 0;
1250 }
1251
1252 #ifdef CONFIG_PM
1253
1254 static int gfar_suspend(struct device *dev)
1255 {
1256         struct gfar_private *priv = dev_get_drvdata(dev);
1257         struct net_device *ndev = priv->ndev;
1258         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1259         unsigned long flags;
1260         u32 tempval;
1261
1262         int magic_packet = priv->wol_en &&
1263                            (priv->device_flags &
1264                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1265
1266         netif_device_detach(ndev);
1267
1268         if (netif_running(ndev)) {
1269
1270                 local_irq_save(flags);
1271                 lock_tx_qs(priv);
1272                 lock_rx_qs(priv);
1273
1274                 gfar_halt_nodisable(ndev);
1275
1276                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1277                 tempval = gfar_read(&regs->maccfg1);
1278
1279                 tempval &= ~MACCFG1_TX_EN;
1280
1281                 if (!magic_packet)
1282                         tempval &= ~MACCFG1_RX_EN;
1283
1284                 gfar_write(&regs->maccfg1, tempval);
1285
1286                 unlock_rx_qs(priv);
1287                 unlock_tx_qs(priv);
1288                 local_irq_restore(flags);
1289
1290                 disable_napi(priv);
1291
1292                 if (magic_packet) {
1293                         /* Enable interrupt on Magic Packet */
1294                         gfar_write(&regs->imask, IMASK_MAG);
1295
1296                         /* Enable Magic Packet mode */
1297                         tempval = gfar_read(&regs->maccfg2);
1298                         tempval |= MACCFG2_MPEN;
1299                         gfar_write(&regs->maccfg2, tempval);
1300                 } else {
1301                         phy_stop(priv->phydev);
1302                 }
1303         }
1304
1305         return 0;
1306 }
1307
1308 static int gfar_resume(struct device *dev)
1309 {
1310         struct gfar_private *priv = dev_get_drvdata(dev);
1311         struct net_device *ndev = priv->ndev;
1312         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1313         unsigned long flags;
1314         u32 tempval;
1315         int magic_packet = priv->wol_en &&
1316                            (priv->device_flags &
1317                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1318
1319         if (!netif_running(ndev)) {
1320                 netif_device_attach(ndev);
1321                 return 0;
1322         }
1323
1324         if (!magic_packet && priv->phydev)
1325                 phy_start(priv->phydev);
1326
1327         /* Disable Magic Packet mode, in case something
1328          * else woke us up.
1329          */
1330         local_irq_save(flags);
1331         lock_tx_qs(priv);
1332         lock_rx_qs(priv);
1333
1334         tempval = gfar_read(&regs->maccfg2);
1335         tempval &= ~MACCFG2_MPEN;
1336         gfar_write(&regs->maccfg2, tempval);
1337
1338         gfar_start(ndev);
1339
1340         unlock_rx_qs(priv);
1341         unlock_tx_qs(priv);
1342         local_irq_restore(flags);
1343
1344         netif_device_attach(ndev);
1345
1346         enable_napi(priv);
1347
1348         return 0;
1349 }
1350
1351 static int gfar_restore(struct device *dev)
1352 {
1353         struct gfar_private *priv = dev_get_drvdata(dev);
1354         struct net_device *ndev = priv->ndev;
1355
1356         if (!netif_running(ndev)) {
1357                 netif_device_attach(ndev);
1358
1359                 return 0;
1360         }
1361
1362         if (gfar_init_bds(ndev)) {
1363                 free_skb_resources(priv);
1364                 return -ENOMEM;
1365         }
1366
1367         init_registers(ndev);
1368         gfar_set_mac_address(ndev);
1369         gfar_init_mac(ndev);
1370         gfar_start(ndev);
1371
1372         priv->oldlink = 0;
1373         priv->oldspeed = 0;
1374         priv->oldduplex = -1;
1375
1376         if (priv->phydev)
1377                 phy_start(priv->phydev);
1378
1379         netif_device_attach(ndev);
1380         enable_napi(priv);
1381
1382         return 0;
1383 }
1384
1385 static struct dev_pm_ops gfar_pm_ops = {
1386         .suspend = gfar_suspend,
1387         .resume = gfar_resume,
1388         .freeze = gfar_suspend,
1389         .thaw = gfar_resume,
1390         .restore = gfar_restore,
1391 };
1392
1393 #define GFAR_PM_OPS (&gfar_pm_ops)
1394
1395 #else
1396
1397 #define GFAR_PM_OPS NULL
1398
1399 #endif
1400
1401 /* Reads the controller's registers to determine what interface
1402  * connects it to the PHY.
1403  */
1404 static phy_interface_t gfar_get_interface(struct net_device *dev)
1405 {
1406         struct gfar_private *priv = netdev_priv(dev);
1407         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1408         u32 ecntrl;
1409
1410         ecntrl = gfar_read(&regs->ecntrl);
1411
1412         if (ecntrl & ECNTRL_SGMII_MODE)
1413                 return PHY_INTERFACE_MODE_SGMII;
1414
1415         if (ecntrl & ECNTRL_TBI_MODE) {
1416                 if (ecntrl & ECNTRL_REDUCED_MODE)
1417                         return PHY_INTERFACE_MODE_RTBI;
1418                 else
1419                         return PHY_INTERFACE_MODE_TBI;
1420         }
1421
1422         if (ecntrl & ECNTRL_REDUCED_MODE) {
1423                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1424                         return PHY_INTERFACE_MODE_RMII;
1425                 }
1426                 else {
1427                         phy_interface_t interface = priv->interface;
1428
1429                         /* This isn't autodetected right now, so it must
1430                          * be set by the device tree or platform code.
1431                          */
1432                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1433                                 return PHY_INTERFACE_MODE_RGMII_ID;
1434
1435                         return PHY_INTERFACE_MODE_RGMII;
1436                 }
1437         }
1438
1439         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1440                 return PHY_INTERFACE_MODE_GMII;
1441
1442         return PHY_INTERFACE_MODE_MII;
1443 }
1444
1445
1446 /* Initializes driver's PHY state, and attaches to the PHY.
1447  * Returns 0 on success.
1448  */
1449 static int init_phy(struct net_device *dev)
1450 {
1451         struct gfar_private *priv = netdev_priv(dev);
1452         uint gigabit_support =
1453                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1454                 SUPPORTED_1000baseT_Full : 0;
1455         phy_interface_t interface;
1456
1457         priv->oldlink = 0;
1458         priv->oldspeed = 0;
1459         priv->oldduplex = -1;
1460
1461         interface = gfar_get_interface(dev);
1462
1463         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1464                                       interface);
1465         if (!priv->phydev)
1466                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1467                                                          interface);
1468         if (!priv->phydev) {
1469                 dev_err(&dev->dev, "could not attach to PHY\n");
1470                 return -ENODEV;
1471         }
1472
1473         if (interface == PHY_INTERFACE_MODE_SGMII)
1474                 gfar_configure_serdes(dev);
1475
1476         /* Remove any features not supported by the controller */
1477         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1478         priv->phydev->advertising = priv->phydev->supported;
1479
1480         return 0;
1481 }
1482
1483 /* Initialize TBI PHY interface for communicating with the
1484  * SERDES lynx PHY on the chip.  We communicate with this PHY
1485  * through the MDIO bus on each controller, treating it as a
1486  * "normal" PHY at the address found in the TBIPA register.  We assume
1487  * that the TBIPA register is valid.  Either the MDIO bus code will set
1488  * it to a value that doesn't conflict with other PHYs on the bus, or the
1489  * value doesn't matter, as there are no other PHYs on the bus.
1490  */
1491 static void gfar_configure_serdes(struct net_device *dev)
1492 {
1493         struct gfar_private *priv = netdev_priv(dev);
1494         struct phy_device *tbiphy;
1495
1496         if (!priv->tbi_node) {
1497                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1498                                     "device tree specify a tbi-handle\n");
1499                 return;
1500         }
1501
1502         tbiphy = of_phy_find_device(priv->tbi_node);
1503         if (!tbiphy) {
1504                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1505                 return;
1506         }
1507
1508         /* If the link is already up, we must already be ok, and don't need to
1509          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1510          * everything for us?  Resetting it takes the link down and requires
1511          * several seconds for it to come back.
1512          */
1513         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1514                 return;
1515
1516         /* Single clk mode, mii mode off(for serdes communication) */
1517         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1518
1519         phy_write(tbiphy, MII_ADVERTISE,
1520                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1521                   ADVERTISE_1000XPSE_ASYM);
1522
1523         phy_write(tbiphy, MII_BMCR,
1524                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1525                   BMCR_SPEED1000);
1526 }
1527
1528 static void init_registers(struct net_device *dev)
1529 {
1530         struct gfar_private *priv = netdev_priv(dev);
1531         struct gfar __iomem *regs = NULL;
1532         int i;
1533
1534         for (i = 0; i < priv->num_grps; i++) {
1535                 regs = priv->gfargrp[i].regs;
1536                 /* Clear IEVENT */
1537                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1538
1539                 /* Initialize IMASK */
1540                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1541         }
1542
1543         regs = priv->gfargrp[0].regs;
1544         /* Init hash registers to zero */
1545         gfar_write(&regs->igaddr0, 0);
1546         gfar_write(&regs->igaddr1, 0);
1547         gfar_write(&regs->igaddr2, 0);
1548         gfar_write(&regs->igaddr3, 0);
1549         gfar_write(&regs->igaddr4, 0);
1550         gfar_write(&regs->igaddr5, 0);
1551         gfar_write(&regs->igaddr6, 0);
1552         gfar_write(&regs->igaddr7, 0);
1553
1554         gfar_write(&regs->gaddr0, 0);
1555         gfar_write(&regs->gaddr1, 0);
1556         gfar_write(&regs->gaddr2, 0);
1557         gfar_write(&regs->gaddr3, 0);
1558         gfar_write(&regs->gaddr4, 0);
1559         gfar_write(&regs->gaddr5, 0);
1560         gfar_write(&regs->gaddr6, 0);
1561         gfar_write(&regs->gaddr7, 0);
1562
1563         /* Zero out the rmon mib registers if it has them */
1564         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1565                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1566
1567                 /* Mask off the CAM interrupts */
1568                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1569                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1570         }
1571
1572         /* Initialize the max receive buffer length */
1573         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1574
1575         /* Initialize the Minimum Frame Length Register */
1576         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1577 }
1578
1579 static int __gfar_is_rx_idle(struct gfar_private *priv)
1580 {
1581         u32 res;
1582
1583         /* Normaly TSEC should not hang on GRS commands, so we should
1584          * actually wait for IEVENT_GRSC flag.
1585          */
1586         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1587                 return 0;
1588
1589         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1590          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1591          * and the Rx can be safely reset.
1592          */
1593         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1594         res &= 0x7f807f80;
1595         if ((res & 0xffff) == (res >> 16))
1596                 return 1;
1597
1598         return 0;
1599 }
1600
1601 /* Halt the receive and transmit queues */
1602 static void gfar_halt_nodisable(struct net_device *dev)
1603 {
1604         struct gfar_private *priv = netdev_priv(dev);
1605         struct gfar __iomem *regs = NULL;
1606         u32 tempval;
1607         int i;
1608
1609         for (i = 0; i < priv->num_grps; i++) {
1610                 regs = priv->gfargrp[i].regs;
1611                 /* Mask all interrupts */
1612                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1613
1614                 /* Clear all interrupts */
1615                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1616         }
1617
1618         regs = priv->gfargrp[0].regs;
1619         /* Stop the DMA, and wait for it to stop */
1620         tempval = gfar_read(&regs->dmactrl);
1621         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1622             (DMACTRL_GRS | DMACTRL_GTS)) {
1623                 int ret;
1624
1625                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1626                 gfar_write(&regs->dmactrl, tempval);
1627
1628                 do {
1629                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1630                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1631                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1632                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1633                                 ret = __gfar_is_rx_idle(priv);
1634                 } while (!ret);
1635         }
1636 }
1637
1638 /* Halt the receive and transmit queues */
1639 void gfar_halt(struct net_device *dev)
1640 {
1641         struct gfar_private *priv = netdev_priv(dev);
1642         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1643         u32 tempval;
1644
1645         gfar_halt_nodisable(dev);
1646
1647         /* Disable Rx and Tx */
1648         tempval = gfar_read(&regs->maccfg1);
1649         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1650         gfar_write(&regs->maccfg1, tempval);
1651 }
1652
1653 static void free_grp_irqs(struct gfar_priv_grp *grp)
1654 {
1655         free_irq(grp->interruptError, grp);
1656         free_irq(grp->interruptTransmit, grp);
1657         free_irq(grp->interruptReceive, grp);
1658 }
1659
1660 void stop_gfar(struct net_device *dev)
1661 {
1662         struct gfar_private *priv = netdev_priv(dev);
1663         unsigned long flags;
1664         int i;
1665
1666         phy_stop(priv->phydev);
1667
1668
1669         /* Lock it down */
1670         local_irq_save(flags);
1671         lock_tx_qs(priv);
1672         lock_rx_qs(priv);
1673
1674         gfar_halt(dev);
1675
1676         unlock_rx_qs(priv);
1677         unlock_tx_qs(priv);
1678         local_irq_restore(flags);
1679
1680         /* Free the IRQs */
1681         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1682                 for (i = 0; i < priv->num_grps; i++)
1683                         free_grp_irqs(&priv->gfargrp[i]);
1684         } else {
1685                 for (i = 0; i < priv->num_grps; i++)
1686                         free_irq(priv->gfargrp[i].interruptTransmit,
1687                                  &priv->gfargrp[i]);
1688         }
1689
1690         free_skb_resources(priv);
1691 }
1692
1693 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1694 {
1695         struct txbd8 *txbdp;
1696         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1697         int i, j;
1698
1699         txbdp = tx_queue->tx_bd_base;
1700
1701         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1702                 if (!tx_queue->tx_skbuff[i])
1703                         continue;
1704
1705                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1706                                  txbdp->length, DMA_TO_DEVICE);
1707                 txbdp->lstatus = 0;
1708                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1709                      j++) {
1710                         txbdp++;
1711                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1712                                        txbdp->length, DMA_TO_DEVICE);
1713                 }
1714                 txbdp++;
1715                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1716                 tx_queue->tx_skbuff[i] = NULL;
1717         }
1718         kfree(tx_queue->tx_skbuff);
1719         tx_queue->tx_skbuff = NULL;
1720 }
1721
1722 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1723 {
1724         struct rxbd8 *rxbdp;
1725         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1726         int i;
1727
1728         rxbdp = rx_queue->rx_bd_base;
1729
1730         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1731                 if (rx_queue->rx_skbuff[i]) {
1732                         dma_unmap_single(&priv->ofdev->dev,
1733                                          rxbdp->bufPtr, priv->rx_buffer_size,
1734                                          DMA_FROM_DEVICE);
1735                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1736                         rx_queue->rx_skbuff[i] = NULL;
1737                 }
1738                 rxbdp->lstatus = 0;
1739                 rxbdp->bufPtr = 0;
1740                 rxbdp++;
1741         }
1742         kfree(rx_queue->rx_skbuff);
1743         rx_queue->rx_skbuff = NULL;
1744 }
1745
1746 /* If there are any tx skbs or rx skbs still around, free them.
1747  * Then free tx_skbuff and rx_skbuff
1748  */
1749 static void free_skb_resources(struct gfar_private *priv)
1750 {
1751         struct gfar_priv_tx_q *tx_queue = NULL;
1752         struct gfar_priv_rx_q *rx_queue = NULL;
1753         int i;
1754
1755         /* Go through all the buffer descriptors and free their data buffers */
1756         for (i = 0; i < priv->num_tx_queues; i++) {
1757                 struct netdev_queue *txq;
1758
1759                 tx_queue = priv->tx_queue[i];
1760                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1761                 if (tx_queue->tx_skbuff)
1762                         free_skb_tx_queue(tx_queue);
1763                 netdev_tx_reset_queue(txq);
1764         }
1765
1766         for (i = 0; i < priv->num_rx_queues; i++) {
1767                 rx_queue = priv->rx_queue[i];
1768                 if (rx_queue->rx_skbuff)
1769                         free_skb_rx_queue(rx_queue);
1770         }
1771
1772         dma_free_coherent(&priv->ofdev->dev,
1773                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1774                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1775                           priv->tx_queue[0]->tx_bd_base,
1776                           priv->tx_queue[0]->tx_bd_dma_base);
1777 }
1778
1779 void gfar_start(struct net_device *dev)
1780 {
1781         struct gfar_private *priv = netdev_priv(dev);
1782         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1783         u32 tempval;
1784         int i = 0;
1785
1786         /* Enable Rx and Tx in MACCFG1 */
1787         tempval = gfar_read(&regs->maccfg1);
1788         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1789         gfar_write(&regs->maccfg1, tempval);
1790
1791         /* Initialize DMACTRL to have WWR and WOP */
1792         tempval = gfar_read(&regs->dmactrl);
1793         tempval |= DMACTRL_INIT_SETTINGS;
1794         gfar_write(&regs->dmactrl, tempval);
1795
1796         /* Make sure we aren't stopped */
1797         tempval = gfar_read(&regs->dmactrl);
1798         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1799         gfar_write(&regs->dmactrl, tempval);
1800
1801         for (i = 0; i < priv->num_grps; i++) {
1802                 regs = priv->gfargrp[i].regs;
1803                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1804                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1805                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1806                 /* Unmask the interrupts we look for */
1807                 gfar_write(&regs->imask, IMASK_DEFAULT);
1808         }
1809
1810         dev->trans_start = jiffies; /* prevent tx timeout */
1811 }
1812
1813 void gfar_configure_coalescing(struct gfar_private *priv,
1814                                unsigned long tx_mask, unsigned long rx_mask)
1815 {
1816         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1817         u32 __iomem *baddr;
1818         int i = 0;
1819
1820         /* Backward compatible case ---- even if we enable
1821          * multiple queues, there's only single reg to program
1822          */
1823         gfar_write(&regs->txic, 0);
1824         if (likely(priv->tx_queue[0]->txcoalescing))
1825                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1826
1827         gfar_write(&regs->rxic, 0);
1828         if (unlikely(priv->rx_queue[0]->rxcoalescing))
1829                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1830
1831         if (priv->mode == MQ_MG_MODE) {
1832                 baddr = &regs->txic0;
1833                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1834                         gfar_write(baddr + i, 0);
1835                         if (likely(priv->tx_queue[i]->txcoalescing))
1836                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1837                 }
1838
1839                 baddr = &regs->rxic0;
1840                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1841                         gfar_write(baddr + i, 0);
1842                         if (likely(priv->rx_queue[i]->rxcoalescing))
1843                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1844                 }
1845         }
1846 }
1847
1848 static int register_grp_irqs(struct gfar_priv_grp *grp)
1849 {
1850         struct gfar_private *priv = grp->priv;
1851         struct net_device *dev = priv->ndev;
1852         int err;
1853
1854         /* If the device has multiple interrupts, register for
1855          * them.  Otherwise, only register for the one
1856          */
1857         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1858                 /* Install our interrupt handlers for Error,
1859                  * Transmit, and Receive
1860                  */
1861                 if ((err = request_irq(grp->interruptError, gfar_error,
1862                                        0, grp->int_name_er, grp)) < 0) {
1863                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1864                                   grp->interruptError);
1865
1866                         goto err_irq_fail;
1867                 }
1868
1869                 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1870                                        0, grp->int_name_tx, grp)) < 0) {
1871                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1872                                   grp->interruptTransmit);
1873                         goto tx_irq_fail;
1874                 }
1875
1876                 if ((err = request_irq(grp->interruptReceive, gfar_receive,
1877                                        0, grp->int_name_rx, grp)) < 0) {
1878                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1879                                   grp->interruptReceive);
1880                         goto rx_irq_fail;
1881                 }
1882         } else {
1883                 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt,
1884                                        0, grp->int_name_tx, grp)) < 0) {
1885                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1886                                   grp->interruptTransmit);
1887                         goto err_irq_fail;
1888                 }
1889         }
1890
1891         return 0;
1892
1893 rx_irq_fail:
1894         free_irq(grp->interruptTransmit, grp);
1895 tx_irq_fail:
1896         free_irq(grp->interruptError, grp);
1897 err_irq_fail:
1898         return err;
1899
1900 }
1901
1902 /* Bring the controller up and running */
1903 int startup_gfar(struct net_device *ndev)
1904 {
1905         struct gfar_private *priv = netdev_priv(ndev);
1906         struct gfar __iomem *regs = NULL;
1907         int err, i, j;
1908
1909         for (i = 0; i < priv->num_grps; i++) {
1910                 regs= priv->gfargrp[i].regs;
1911                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1912         }
1913
1914         regs= priv->gfargrp[0].regs;
1915         err = gfar_alloc_skb_resources(ndev);
1916         if (err)
1917                 return err;
1918
1919         gfar_init_mac(ndev);
1920
1921         for (i = 0; i < priv->num_grps; i++) {
1922                 err = register_grp_irqs(&priv->gfargrp[i]);
1923                 if (err) {
1924                         for (j = 0; j < i; j++)
1925                                 free_grp_irqs(&priv->gfargrp[j]);
1926                         goto irq_fail;
1927                 }
1928         }
1929
1930         /* Start the controller */
1931         gfar_start(ndev);
1932
1933         phy_start(priv->phydev);
1934
1935         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1936
1937         return 0;
1938
1939 irq_fail:
1940         free_skb_resources(priv);
1941         return err;
1942 }
1943
1944 /* Called when something needs to use the ethernet device
1945  * Returns 0 for success.
1946  */
1947 static int gfar_enet_open(struct net_device *dev)
1948 {
1949         struct gfar_private *priv = netdev_priv(dev);
1950         int err;
1951
1952         enable_napi(priv);
1953
1954         /* Initialize a bunch of registers */
1955         init_registers(dev);
1956
1957         gfar_set_mac_address(dev);
1958
1959         err = init_phy(dev);
1960
1961         if (err) {
1962                 disable_napi(priv);
1963                 return err;
1964         }
1965
1966         err = startup_gfar(dev);
1967         if (err) {
1968                 disable_napi(priv);
1969                 return err;
1970         }
1971
1972         netif_tx_start_all_queues(dev);
1973
1974         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1975
1976         return err;
1977 }
1978
1979 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1980 {
1981         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1982
1983         memset(fcb, 0, GMAC_FCB_LEN);
1984
1985         return fcb;
1986 }
1987
1988 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1989                                     int fcb_length)
1990 {
1991         /* If we're here, it's a IP packet with a TCP or UDP
1992          * payload.  We set it to checksum, using a pseudo-header
1993          * we provide
1994          */
1995         u8 flags = TXFCB_DEFAULT;
1996
1997         /* Tell the controller what the protocol is
1998          * And provide the already calculated phcs
1999          */
2000         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2001                 flags |= TXFCB_UDP;
2002                 fcb->phcs = udp_hdr(skb)->check;
2003         } else
2004                 fcb->phcs = tcp_hdr(skb)->check;
2005
2006         /* l3os is the distance between the start of the
2007          * frame (skb->data) and the start of the IP hdr.
2008          * l4os is the distance between the start of the
2009          * l3 hdr and the l4 hdr
2010          */
2011         fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2012         fcb->l4os = skb_network_header_len(skb);
2013
2014         fcb->flags = flags;
2015 }
2016
2017 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2018 {
2019         fcb->flags |= TXFCB_VLN;
2020         fcb->vlctl = vlan_tx_tag_get(skb);
2021 }
2022
2023 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2024                                       struct txbd8 *base, int ring_size)
2025 {
2026         struct txbd8 *new_bd = bdp + stride;
2027
2028         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2029 }
2030
2031 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2032                                       int ring_size)
2033 {
2034         return skip_txbd(bdp, 1, base, ring_size);
2035 }
2036
2037 /* This is called by the kernel when a frame is ready for transmission.
2038  * It is pointed to by the dev->hard_start_xmit function pointer
2039  */
2040 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2041 {
2042         struct gfar_private *priv = netdev_priv(dev);
2043         struct gfar_priv_tx_q *tx_queue = NULL;
2044         struct netdev_queue *txq;
2045         struct gfar __iomem *regs = NULL;
2046         struct txfcb *fcb = NULL;
2047         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2048         u32 lstatus;
2049         int i, rq = 0, do_tstamp = 0;
2050         u32 bufaddr;
2051         unsigned long flags;
2052         unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2053
2054         /* TOE=1 frames larger than 2500 bytes may see excess delays
2055          * before start of transmission.
2056          */
2057         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2058                      skb->ip_summed == CHECKSUM_PARTIAL &&
2059                      skb->len > 2500)) {
2060                 int ret;
2061
2062                 ret = skb_checksum_help(skb);
2063                 if (ret)
2064                         return ret;
2065         }
2066
2067         rq = skb->queue_mapping;
2068         tx_queue = priv->tx_queue[rq];
2069         txq = netdev_get_tx_queue(dev, rq);
2070         base = tx_queue->tx_bd_base;
2071         regs = tx_queue->grp->regs;
2072
2073         /* check if time stamp should be generated */
2074         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2075                      priv->hwts_tx_en)) {
2076                 do_tstamp = 1;
2077                 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2078         }
2079
2080         /* make space for additional header when fcb is needed */
2081         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2082              vlan_tx_tag_present(skb) ||
2083              unlikely(do_tstamp)) &&
2084             (skb_headroom(skb) < fcb_length)) {
2085                 struct sk_buff *skb_new;
2086
2087                 skb_new = skb_realloc_headroom(skb, fcb_length);
2088                 if (!skb_new) {
2089                         dev->stats.tx_errors++;
2090                         kfree_skb(skb);
2091                         return NETDEV_TX_OK;
2092                 }
2093
2094                 if (skb->sk)
2095                         skb_set_owner_w(skb_new, skb->sk);
2096                 consume_skb(skb);
2097                 skb = skb_new;
2098         }
2099
2100         /* total number of fragments in the SKB */
2101         nr_frags = skb_shinfo(skb)->nr_frags;
2102
2103         /* calculate the required number of TxBDs for this skb */
2104         if (unlikely(do_tstamp))
2105                 nr_txbds = nr_frags + 2;
2106         else
2107                 nr_txbds = nr_frags + 1;
2108
2109         /* check if there is space to queue this packet */
2110         if (nr_txbds > tx_queue->num_txbdfree) {
2111                 /* no space, stop the queue */
2112                 netif_tx_stop_queue(txq);
2113                 dev->stats.tx_fifo_errors++;
2114                 return NETDEV_TX_BUSY;
2115         }
2116
2117         /* Update transmit stats */
2118         tx_queue->stats.tx_bytes += skb->len;
2119         tx_queue->stats.tx_packets++;
2120
2121         txbdp = txbdp_start = tx_queue->cur_tx;
2122         lstatus = txbdp->lstatus;
2123
2124         /* Time stamp insertion requires one additional TxBD */
2125         if (unlikely(do_tstamp))
2126                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2127                                                  tx_queue->tx_ring_size);
2128
2129         if (nr_frags == 0) {
2130                 if (unlikely(do_tstamp))
2131                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2132                                                           TXBD_INTERRUPT);
2133                 else
2134                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2135         } else {
2136                 /* Place the fragment addresses and lengths into the TxBDs */
2137                 for (i = 0; i < nr_frags; i++) {
2138                         /* Point at the next BD, wrapping as needed */
2139                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2140
2141                         length = skb_shinfo(skb)->frags[i].size;
2142
2143                         lstatus = txbdp->lstatus | length |
2144                                   BD_LFLAG(TXBD_READY);
2145
2146                         /* Handle the last BD specially */
2147                         if (i == nr_frags - 1)
2148                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2149
2150                         bufaddr = skb_frag_dma_map(&priv->ofdev->dev,
2151                                                    &skb_shinfo(skb)->frags[i],
2152                                                    0,
2153                                                    length,
2154                                                    DMA_TO_DEVICE);
2155
2156                         /* set the TxBD length and buffer pointer */
2157                         txbdp->bufPtr = bufaddr;
2158                         txbdp->lstatus = lstatus;
2159                 }
2160
2161                 lstatus = txbdp_start->lstatus;
2162         }
2163
2164         /* Add TxPAL between FCB and frame if required */
2165         if (unlikely(do_tstamp)) {
2166                 skb_push(skb, GMAC_TXPAL_LEN);
2167                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2168         }
2169
2170         /* Set up checksumming */
2171         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2172                 fcb = gfar_add_fcb(skb);
2173                 /* as specified by errata */
2174                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2175                              ((unsigned long)fcb % 0x20) > 0x18)) {
2176                         __skb_pull(skb, GMAC_FCB_LEN);
2177                         skb_checksum_help(skb);
2178                 } else {
2179                         lstatus |= BD_LFLAG(TXBD_TOE);
2180                         gfar_tx_checksum(skb, fcb, fcb_length);
2181                 }
2182         }
2183
2184         if (vlan_tx_tag_present(skb)) {
2185                 if (unlikely(NULL == fcb)) {
2186                         fcb = gfar_add_fcb(skb);
2187                         lstatus |= BD_LFLAG(TXBD_TOE);
2188                 }
2189
2190                 gfar_tx_vlan(skb, fcb);
2191         }
2192
2193         /* Setup tx hardware time stamping if requested */
2194         if (unlikely(do_tstamp)) {
2195                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2196                 if (fcb == NULL)
2197                         fcb = gfar_add_fcb(skb);
2198                 fcb->ptp = 1;
2199                 lstatus |= BD_LFLAG(TXBD_TOE);
2200         }
2201
2202         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2203                                              skb_headlen(skb), DMA_TO_DEVICE);
2204
2205         /* If time stamping is requested one additional TxBD must be set up. The
2206          * first TxBD points to the FCB and must have a data length of
2207          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2208          * the full frame length.
2209          */
2210         if (unlikely(do_tstamp)) {
2211                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2212                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2213                                          (skb_headlen(skb) - fcb_length);
2214                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2215         } else {
2216                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2217         }
2218
2219         netdev_tx_sent_queue(txq, skb->len);
2220
2221         /* We can work in parallel with gfar_clean_tx_ring(), except
2222          * when modifying num_txbdfree. Note that we didn't grab the lock
2223          * when we were reading the num_txbdfree and checking for available
2224          * space, that's because outside of this function it can only grow,
2225          * and once we've got needed space, it cannot suddenly disappear.
2226          *
2227          * The lock also protects us from gfar_error(), which can modify
2228          * regs->tstat and thus retrigger the transfers, which is why we
2229          * also must grab the lock before setting ready bit for the first
2230          * to be transmitted BD.
2231          */
2232         spin_lock_irqsave(&tx_queue->txlock, flags);
2233
2234         /* The powerpc-specific eieio() is used, as wmb() has too strong
2235          * semantics (it requires synchronization between cacheable and
2236          * uncacheable mappings, which eieio doesn't provide and which we
2237          * don't need), thus requiring a more expensive sync instruction.  At
2238          * some point, the set of architecture-independent barrier functions
2239          * should be expanded to include weaker barriers.
2240          */
2241         eieio();
2242
2243         txbdp_start->lstatus = lstatus;
2244
2245         eieio(); /* force lstatus write before tx_skbuff */
2246
2247         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2248
2249         /* Update the current skb pointer to the next entry we will use
2250          * (wrapping if necessary)
2251          */
2252         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2253                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2254
2255         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2256
2257         /* reduce TxBD free count */
2258         tx_queue->num_txbdfree -= (nr_txbds);
2259
2260         /* If the next BD still needs to be cleaned up, then the bds
2261          * are full.  We need to tell the kernel to stop sending us stuff.
2262          */
2263         if (!tx_queue->num_txbdfree) {
2264                 netif_tx_stop_queue(txq);
2265
2266                 dev->stats.tx_fifo_errors++;
2267         }
2268
2269         /* Tell the DMA to go go go */
2270         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2271
2272         /* Unlock priv */
2273         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2274
2275         return NETDEV_TX_OK;
2276 }
2277
2278 /* Stops the kernel queue, and halts the controller */
2279 static int gfar_close(struct net_device *dev)
2280 {
2281         struct gfar_private *priv = netdev_priv(dev);
2282
2283         disable_napi(priv);
2284
2285         cancel_work_sync(&priv->reset_task);
2286         stop_gfar(dev);
2287
2288         /* Disconnect from the PHY */
2289         phy_disconnect(priv->phydev);
2290         priv->phydev = NULL;
2291
2292         netif_tx_stop_all_queues(dev);
2293
2294         return 0;
2295 }
2296
2297 /* Changes the mac address if the controller is not running. */
2298 static int gfar_set_mac_address(struct net_device *dev)
2299 {
2300         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2301
2302         return 0;
2303 }
2304
2305 /* Check if rx parser should be activated */
2306 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2307 {
2308         struct gfar __iomem *regs;
2309         u32 tempval;
2310
2311         regs = priv->gfargrp[0].regs;
2312
2313         tempval = gfar_read(&regs->rctrl);
2314         /* If parse is no longer required, then disable parser */
2315         if (tempval & RCTRL_REQ_PARSER)
2316                 tempval |= RCTRL_PRSDEP_INIT;
2317         else
2318                 tempval &= ~RCTRL_PRSDEP_INIT;
2319         gfar_write(&regs->rctrl, tempval);
2320 }
2321
2322 /* Enables and disables VLAN insertion/extraction */
2323 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2324 {
2325         struct gfar_private *priv = netdev_priv(dev);
2326         struct gfar __iomem *regs = NULL;
2327         unsigned long flags;
2328         u32 tempval;
2329
2330         regs = priv->gfargrp[0].regs;
2331         local_irq_save(flags);
2332         lock_rx_qs(priv);
2333
2334         if (features & NETIF_F_HW_VLAN_TX) {
2335                 /* Enable VLAN tag insertion */
2336                 tempval = gfar_read(&regs->tctrl);
2337                 tempval |= TCTRL_VLINS;
2338                 gfar_write(&regs->tctrl, tempval);
2339         } else {
2340                 /* Disable VLAN tag insertion */
2341                 tempval = gfar_read(&regs->tctrl);
2342                 tempval &= ~TCTRL_VLINS;
2343                 gfar_write(&regs->tctrl, tempval);
2344         }
2345
2346         if (features & NETIF_F_HW_VLAN_RX) {
2347                 /* Enable VLAN tag extraction */
2348                 tempval = gfar_read(&regs->rctrl);
2349                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2350                 gfar_write(&regs->rctrl, tempval);
2351         } else {
2352                 /* Disable VLAN tag extraction */
2353                 tempval = gfar_read(&regs->rctrl);
2354                 tempval &= ~RCTRL_VLEX;
2355                 gfar_write(&regs->rctrl, tempval);
2356
2357                 gfar_check_rx_parser_mode(priv);
2358         }
2359
2360         gfar_change_mtu(dev, dev->mtu);
2361
2362         unlock_rx_qs(priv);
2363         local_irq_restore(flags);
2364 }
2365
2366 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2367 {
2368         int tempsize, tempval;
2369         struct gfar_private *priv = netdev_priv(dev);
2370         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2371         int oldsize = priv->rx_buffer_size;
2372         int frame_size = new_mtu + ETH_HLEN;
2373
2374         if (gfar_is_vlan_on(priv))
2375                 frame_size += VLAN_HLEN;
2376
2377         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2378                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2379                 return -EINVAL;
2380         }
2381
2382         if (gfar_uses_fcb(priv))
2383                 frame_size += GMAC_FCB_LEN;
2384
2385         frame_size += priv->padding;
2386
2387         tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2388                    INCREMENTAL_BUFFER_SIZE;
2389
2390         /* Only stop and start the controller if it isn't already
2391          * stopped, and we changed something
2392          */
2393         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2394                 stop_gfar(dev);
2395
2396         priv->rx_buffer_size = tempsize;
2397
2398         dev->mtu = new_mtu;
2399
2400         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2401         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2402
2403         /* If the mtu is larger than the max size for standard
2404          * ethernet frames (ie, a jumbo frame), then set maccfg2
2405          * to allow huge frames, and to check the length
2406          */
2407         tempval = gfar_read(&regs->maccfg2);
2408
2409         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2410             gfar_has_errata(priv, GFAR_ERRATA_74))
2411                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2412         else
2413                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2414
2415         gfar_write(&regs->maccfg2, tempval);
2416
2417         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2418                 startup_gfar(dev);
2419
2420         return 0;
2421 }
2422
2423 /* gfar_reset_task gets scheduled when a packet has not been
2424  * transmitted after a set amount of time.
2425  * For now, assume that clearing out all the structures, and
2426  * starting over will fix the problem.
2427  */
2428 static void gfar_reset_task(struct work_struct *work)
2429 {
2430         struct gfar_private *priv = container_of(work, struct gfar_private,
2431                                                  reset_task);
2432         struct net_device *dev = priv->ndev;
2433
2434         if (dev->flags & IFF_UP) {
2435                 netif_tx_stop_all_queues(dev);
2436                 stop_gfar(dev);
2437                 startup_gfar(dev);
2438                 netif_tx_start_all_queues(dev);
2439         }
2440
2441         netif_tx_schedule_all(dev);
2442 }
2443
2444 static void gfar_timeout(struct net_device *dev)
2445 {
2446         struct gfar_private *priv = netdev_priv(dev);
2447
2448         dev->stats.tx_errors++;
2449         schedule_work(&priv->reset_task);
2450 }
2451
2452 static void gfar_align_skb(struct sk_buff *skb)
2453 {
2454         /* We need the data buffer to be aligned properly.  We will reserve
2455          * as many bytes as needed to align the data properly
2456          */
2457         skb_reserve(skb, RXBUF_ALIGNMENT -
2458                     (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2459 }
2460
2461 /* Interrupt Handler for Transmit complete */
2462 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2463 {
2464         struct net_device *dev = tx_queue->dev;
2465         struct netdev_queue *txq;
2466         struct gfar_private *priv = netdev_priv(dev);
2467         struct gfar_priv_rx_q *rx_queue = NULL;
2468         struct txbd8 *bdp, *next = NULL;
2469         struct txbd8 *lbdp = NULL;
2470         struct txbd8 *base = tx_queue->tx_bd_base;
2471         struct sk_buff *skb;
2472         int skb_dirtytx;
2473         int tx_ring_size = tx_queue->tx_ring_size;
2474         int frags = 0, nr_txbds = 0;
2475         int i;
2476         int howmany = 0;
2477         int tqi = tx_queue->qindex;
2478         unsigned int bytes_sent = 0;
2479         u32 lstatus;
2480         size_t buflen;
2481
2482         rx_queue = priv->rx_queue[tqi];
2483         txq = netdev_get_tx_queue(dev, tqi);
2484         bdp = tx_queue->dirty_tx;
2485         skb_dirtytx = tx_queue->skb_dirtytx;
2486
2487         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2488                 unsigned long flags;
2489
2490                 frags = skb_shinfo(skb)->nr_frags;
2491
2492                 /* When time stamping, one additional TxBD must be freed.
2493                  * Also, we need to dma_unmap_single() the TxPAL.
2494                  */
2495                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2496                         nr_txbds = frags + 2;
2497                 else
2498                         nr_txbds = frags + 1;
2499
2500                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2501
2502                 lstatus = lbdp->lstatus;
2503
2504                 /* Only clean completed frames */
2505                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2506                     (lstatus & BD_LENGTH_MASK))
2507                         break;
2508
2509                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2510                         next = next_txbd(bdp, base, tx_ring_size);
2511                         buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2512                 } else
2513                         buflen = bdp->length;
2514
2515                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2516                                  buflen, DMA_TO_DEVICE);
2517
2518                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2519                         struct skb_shared_hwtstamps shhwtstamps;
2520                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2521
2522                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2523                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2524                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2525                         skb_tstamp_tx(skb, &shhwtstamps);
2526                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2527                         bdp = next;
2528                 }
2529
2530                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2531                 bdp = next_txbd(bdp, base, tx_ring_size);
2532
2533                 for (i = 0; i < frags; i++) {
2534                         dma_unmap_page(&priv->ofdev->dev, bdp->bufPtr,
2535                                        bdp->length, DMA_TO_DEVICE);
2536                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2537                         bdp = next_txbd(bdp, base, tx_ring_size);
2538                 }
2539
2540                 bytes_sent += skb->len;
2541
2542                 dev_kfree_skb_any(skb);
2543
2544                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2545
2546                 skb_dirtytx = (skb_dirtytx + 1) &
2547                               TX_RING_MOD_MASK(tx_ring_size);
2548
2549                 howmany++;
2550                 spin_lock_irqsave(&tx_queue->txlock, flags);
2551                 tx_queue->num_txbdfree += nr_txbds;
2552                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2553         }
2554
2555         /* If we freed a buffer, we can restart transmission, if necessary */
2556         if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2557                 netif_wake_subqueue(dev, tqi);
2558
2559         /* Update dirty indicators */
2560         tx_queue->skb_dirtytx = skb_dirtytx;
2561         tx_queue->dirty_tx = bdp;
2562
2563         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2564
2565         return howmany;
2566 }
2567
2568 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2569 {
2570         unsigned long flags;
2571
2572         spin_lock_irqsave(&gfargrp->grplock, flags);
2573         if (napi_schedule_prep(&gfargrp->napi)) {
2574                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2575                 __napi_schedule(&gfargrp->napi);
2576         } else {
2577                 /* Clear IEVENT, so interrupts aren't called again
2578                  * because of the packets that have already arrived.
2579                  */
2580                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2581         }
2582         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2583
2584 }
2585
2586 /* Interrupt Handler for Transmit complete */
2587 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2588 {
2589         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2590         return IRQ_HANDLED;
2591 }
2592
2593 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2594                            struct sk_buff *skb)
2595 {
2596         struct net_device *dev = rx_queue->dev;
2597         struct gfar_private *priv = netdev_priv(dev);
2598         dma_addr_t buf;
2599
2600         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2601                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2602         gfar_init_rxbdp(rx_queue, bdp, buf);
2603 }
2604
2605 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2606 {
2607         struct gfar_private *priv = netdev_priv(dev);
2608         struct sk_buff *skb;
2609
2610         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2611         if (!skb)
2612                 return NULL;
2613
2614         gfar_align_skb(skb);
2615
2616         return skb;
2617 }
2618
2619 struct sk_buff *gfar_new_skb(struct net_device *dev)
2620 {
2621         return gfar_alloc_skb(dev);
2622 }
2623
2624 static inline void count_errors(unsigned short status, struct net_device *dev)
2625 {
2626         struct gfar_private *priv = netdev_priv(dev);
2627         struct net_device_stats *stats = &dev->stats;
2628         struct gfar_extra_stats *estats = &priv->extra_stats;
2629
2630         /* If the packet was truncated, none of the other errors matter */
2631         if (status & RXBD_TRUNCATED) {
2632                 stats->rx_length_errors++;
2633
2634                 estats->rx_trunc++;
2635
2636                 return;
2637         }
2638         /* Count the errors, if there were any */
2639         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2640                 stats->rx_length_errors++;
2641
2642                 if (status & RXBD_LARGE)
2643                         estats->rx_large++;
2644                 else
2645                         estats->rx_short++;
2646         }
2647         if (status & RXBD_NONOCTET) {
2648                 stats->rx_frame_errors++;
2649                 estats->rx_nonoctet++;
2650         }
2651         if (status & RXBD_CRCERR) {
2652                 estats->rx_crcerr++;
2653                 stats->rx_crc_errors++;
2654         }
2655         if (status & RXBD_OVERRUN) {
2656                 estats->rx_overrun++;
2657                 stats->rx_crc_errors++;
2658         }
2659 }
2660
2661 irqreturn_t gfar_receive(int irq, void *grp_id)
2662 {
2663         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2664         return IRQ_HANDLED;
2665 }
2666
2667 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2668 {
2669         /* If valid headers were found, and valid sums
2670          * were verified, then we tell the kernel that no
2671          * checksumming is necessary.  Otherwise, it is [FIXME]
2672          */
2673         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2674                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2675         else
2676                 skb_checksum_none_assert(skb);
2677 }
2678
2679
2680 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2681 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2682                               int amount_pull, struct napi_struct *napi)
2683 {
2684         struct gfar_private *priv = netdev_priv(dev);
2685         struct rxfcb *fcb = NULL;
2686
2687         gro_result_t ret;
2688
2689         /* fcb is at the beginning if exists */
2690         fcb = (struct rxfcb *)skb->data;
2691
2692         /* Remove the FCB from the skb
2693          * Remove the padded bytes, if there are any
2694          */
2695         if (amount_pull) {
2696                 skb_record_rx_queue(skb, fcb->rq);
2697                 skb_pull(skb, amount_pull);
2698         }
2699
2700         /* Get receive timestamp from the skb */
2701         if (priv->hwts_rx_en) {
2702                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2703                 u64 *ns = (u64 *) skb->data;
2704
2705                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2706                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2707         }
2708
2709         if (priv->padding)
2710                 skb_pull(skb, priv->padding);
2711
2712         if (dev->features & NETIF_F_RXCSUM)
2713                 gfar_rx_checksum(skb, fcb);
2714
2715         /* Tell the skb what kind of packet this is */
2716         skb->protocol = eth_type_trans(skb, dev);
2717
2718         /* There's need to check for NETIF_F_HW_VLAN_RX here.
2719          * Even if vlan rx accel is disabled, on some chips
2720          * RXFCB_VLN is pseudo randomly set.
2721          */
2722         if (dev->features & NETIF_F_HW_VLAN_RX &&
2723             fcb->flags & RXFCB_VLN)
2724                 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2725
2726         /* Send the packet up the stack */
2727         ret = napi_gro_receive(napi, skb);
2728
2729         if (GRO_DROP == ret)
2730                 priv->extra_stats.kernel_dropped++;
2731
2732         return 0;
2733 }
2734
2735 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2736  * until the budget/quota has been reached. Returns the number
2737  * of frames handled
2738  */
2739 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2740 {
2741         struct net_device *dev = rx_queue->dev;
2742         struct rxbd8 *bdp, *base;
2743         struct sk_buff *skb;
2744         int pkt_len;
2745         int amount_pull;
2746         int howmany = 0;
2747         struct gfar_private *priv = netdev_priv(dev);
2748
2749         /* Get the first full descriptor */
2750         bdp = rx_queue->cur_rx;
2751         base = rx_queue->rx_bd_base;
2752
2753         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2754
2755         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2756                 struct sk_buff *newskb;
2757
2758                 rmb();
2759
2760                 /* Add another skb for the future */
2761                 newskb = gfar_new_skb(dev);
2762
2763                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2764
2765                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2766                                  priv->rx_buffer_size, DMA_FROM_DEVICE);
2767
2768                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2769                              bdp->length > priv->rx_buffer_size))
2770                         bdp->status = RXBD_LARGE;
2771
2772                 /* We drop the frame if we failed to allocate a new buffer */
2773                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2774                              bdp->status & RXBD_ERR)) {
2775                         count_errors(bdp->status, dev);
2776
2777                         if (unlikely(!newskb))
2778                                 newskb = skb;
2779                         else if (skb)
2780                                 dev_kfree_skb(skb);
2781                 } else {
2782                         /* Increment the number of packets */
2783                         rx_queue->stats.rx_packets++;
2784                         howmany++;
2785
2786                         if (likely(skb)) {
2787                                 pkt_len = bdp->length - ETH_FCS_LEN;
2788                                 /* Remove the FCS from the packet length */
2789                                 skb_put(skb, pkt_len);
2790                                 rx_queue->stats.rx_bytes += pkt_len;
2791                                 skb_record_rx_queue(skb, rx_queue->qindex);
2792                                 gfar_process_frame(dev, skb, amount_pull,
2793                                                    &rx_queue->grp->napi);
2794
2795                         } else {
2796                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2797                                 rx_queue->stats.rx_dropped++;
2798                                 priv->extra_stats.rx_skbmissing++;
2799                         }
2800
2801                 }
2802
2803                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2804
2805                 /* Setup the new bdp */
2806                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2807
2808                 /* Update to the next pointer */
2809                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2810
2811                 /* update to point at the next skb */
2812                 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2813                                       RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2814         }
2815
2816         /* Update the current rxbd pointer to be the next one */
2817         rx_queue->cur_rx = bdp;
2818
2819         return howmany;
2820 }
2821
2822 static int gfar_poll(struct napi_struct *napi, int budget)
2823 {
2824         struct gfar_priv_grp *gfargrp =
2825                 container_of(napi, struct gfar_priv_grp, napi);
2826         struct gfar_private *priv = gfargrp->priv;
2827         struct gfar __iomem *regs = gfargrp->regs;
2828         struct gfar_priv_tx_q *tx_queue = NULL;
2829         struct gfar_priv_rx_q *rx_queue = NULL;
2830         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2831         int tx_cleaned = 0, i, left_over_budget = budget;
2832         unsigned long serviced_queues = 0;
2833         int num_queues = 0;
2834
2835         num_queues = gfargrp->num_rx_queues;
2836         budget_per_queue = budget/num_queues;
2837
2838         /* Clear IEVENT, so interrupts aren't called again
2839          * because of the packets that have already arrived
2840          */
2841         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2842
2843         while (num_queues && left_over_budget) {
2844                 budget_per_queue = left_over_budget/num_queues;
2845                 left_over_budget = 0;
2846
2847                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2848                         if (test_bit(i, &serviced_queues))
2849                                 continue;
2850                         rx_queue = priv->rx_queue[i];
2851                         tx_queue = priv->tx_queue[rx_queue->qindex];
2852
2853                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2854                         rx_cleaned_per_queue =
2855                                 gfar_clean_rx_ring(rx_queue, budget_per_queue);
2856                         rx_cleaned += rx_cleaned_per_queue;
2857                         if (rx_cleaned_per_queue < budget_per_queue) {
2858                                 left_over_budget = left_over_budget +
2859                                         (budget_per_queue -
2860                                          rx_cleaned_per_queue);
2861                                 set_bit(i, &serviced_queues);
2862                                 num_queues--;
2863                         }
2864                 }
2865         }
2866
2867         if (tx_cleaned)
2868                 return budget;
2869
2870         if (rx_cleaned < budget) {
2871                 napi_complete(napi);
2872
2873                 /* Clear the halt bit in RSTAT */
2874                 gfar_write(&regs->rstat, gfargrp->rstat);
2875
2876                 gfar_write(&regs->imask, IMASK_DEFAULT);
2877
2878                 /* If we are coalescing interrupts, update the timer
2879                  * Otherwise, clear it
2880                  */
2881                 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2882                                           gfargrp->tx_bit_map);
2883         }
2884
2885         return rx_cleaned;
2886 }
2887
2888 #ifdef CONFIG_NET_POLL_CONTROLLER
2889 /* Polling 'interrupt' - used by things like netconsole to send skbs
2890  * without having to re-enable interrupts. It's not called while
2891  * the interrupt routine is executing.
2892  */
2893 static void gfar_netpoll(struct net_device *dev)
2894 {
2895         struct gfar_private *priv = netdev_priv(dev);
2896         int i;
2897
2898         /* If the device has multiple interrupts, run tx/rx */
2899         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2900                 for (i = 0; i < priv->num_grps; i++) {
2901                         disable_irq(priv->gfargrp[i].interruptTransmit);
2902                         disable_irq(priv->gfargrp[i].interruptReceive);
2903                         disable_irq(priv->gfargrp[i].interruptError);
2904                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2905                                        &priv->gfargrp[i]);
2906                         enable_irq(priv->gfargrp[i].interruptError);
2907                         enable_irq(priv->gfargrp[i].interruptReceive);
2908                         enable_irq(priv->gfargrp[i].interruptTransmit);
2909                 }
2910         } else {
2911                 for (i = 0; i < priv->num_grps; i++) {
2912                         disable_irq(priv->gfargrp[i].interruptTransmit);
2913                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2914                                        &priv->gfargrp[i]);
2915                         enable_irq(priv->gfargrp[i].interruptTransmit);
2916                 }
2917         }
2918 }
2919 #endif
2920
2921 /* The interrupt handler for devices with one interrupt */
2922 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2923 {
2924         struct gfar_priv_grp *gfargrp = grp_id;
2925
2926         /* Save ievent for future reference */
2927         u32 events = gfar_read(&gfargrp->regs->ievent);
2928
2929         /* Check for reception */
2930         if (events & IEVENT_RX_MASK)
2931                 gfar_receive(irq, grp_id);
2932
2933         /* Check for transmit completion */
2934         if (events & IEVENT_TX_MASK)
2935                 gfar_transmit(irq, grp_id);
2936
2937         /* Check for errors */
2938         if (events & IEVENT_ERR_MASK)
2939                 gfar_error(irq, grp_id);
2940
2941         return IRQ_HANDLED;
2942 }
2943
2944 /* Called every time the controller might need to be made
2945  * aware of new link state.  The PHY code conveys this
2946  * information through variables in the phydev structure, and this
2947  * function converts those variables into the appropriate
2948  * register values, and can bring down the device if needed.
2949  */
2950 static void adjust_link(struct net_device *dev)
2951 {
2952         struct gfar_private *priv = netdev_priv(dev);
2953         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2954         unsigned long flags;
2955         struct phy_device *phydev = priv->phydev;
2956         int new_state = 0;
2957
2958         local_irq_save(flags);
2959         lock_tx_qs(priv);
2960
2961         if (phydev->link) {
2962                 u32 tempval = gfar_read(&regs->maccfg2);
2963                 u32 ecntrl = gfar_read(&regs->ecntrl);
2964
2965                 /* Now we make sure that we can be in full duplex mode.
2966                  * If not, we operate in half-duplex mode.
2967                  */
2968                 if (phydev->duplex != priv->oldduplex) {
2969                         new_state = 1;
2970                         if (!(phydev->duplex))
2971                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2972                         else
2973                                 tempval |= MACCFG2_FULL_DUPLEX;
2974
2975                         priv->oldduplex = phydev->duplex;
2976                 }
2977
2978                 if (phydev->speed != priv->oldspeed) {
2979                         new_state = 1;
2980                         switch (phydev->speed) {
2981                         case 1000:
2982                                 tempval =
2983                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2984
2985                                 ecntrl &= ~(ECNTRL_R100);
2986                                 break;
2987                         case 100:
2988                         case 10:
2989                                 tempval =
2990                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2991
2992                                 /* Reduced mode distinguishes
2993                                  * between 10 and 100
2994                                  */
2995                                 if (phydev->speed == SPEED_100)
2996                                         ecntrl |= ECNTRL_R100;
2997                                 else
2998                                         ecntrl &= ~(ECNTRL_R100);
2999                                 break;
3000                         default:
3001                                 netif_warn(priv, link, dev,
3002                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3003                                            phydev->speed);
3004                                 break;
3005                         }
3006
3007                         priv->oldspeed = phydev->speed;
3008                 }
3009
3010                 gfar_write(&regs->maccfg2, tempval);
3011                 gfar_write(&regs->ecntrl, ecntrl);
3012
3013                 if (!priv->oldlink) {
3014                         new_state = 1;
3015                         priv->oldlink = 1;
3016                 }
3017         } else if (priv->oldlink) {
3018                 new_state = 1;
3019                 priv->oldlink = 0;
3020                 priv->oldspeed = 0;
3021                 priv->oldduplex = -1;
3022         }
3023
3024         if (new_state && netif_msg_link(priv))
3025                 phy_print_status(phydev);
3026         unlock_tx_qs(priv);
3027         local_irq_restore(flags);
3028 }
3029
3030 /* Update the hash table based on the current list of multicast
3031  * addresses we subscribe to.  Also, change the promiscuity of
3032  * the device based on the flags (this function is called
3033  * whenever dev->flags is changed
3034  */
3035 static void gfar_set_multi(struct net_device *dev)
3036 {
3037         struct netdev_hw_addr *ha;
3038         struct gfar_private *priv = netdev_priv(dev);
3039         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3040         u32 tempval;
3041
3042         if (dev->flags & IFF_PROMISC) {
3043                 /* Set RCTRL to PROM */
3044                 tempval = gfar_read(&regs->rctrl);
3045                 tempval |= RCTRL_PROM;
3046                 gfar_write(&regs->rctrl, tempval);
3047         } else {
3048                 /* Set RCTRL to not PROM */
3049                 tempval = gfar_read(&regs->rctrl);
3050                 tempval &= ~(RCTRL_PROM);
3051                 gfar_write(&regs->rctrl, tempval);
3052         }
3053
3054         if (dev->flags & IFF_ALLMULTI) {
3055                 /* Set the hash to rx all multicast frames */
3056                 gfar_write(&regs->igaddr0, 0xffffffff);
3057                 gfar_write(&regs->igaddr1, 0xffffffff);
3058                 gfar_write(&regs->igaddr2, 0xffffffff);
3059                 gfar_write(&regs->igaddr3, 0xffffffff);
3060                 gfar_write(&regs->igaddr4, 0xffffffff);
3061                 gfar_write(&regs->igaddr5, 0xffffffff);
3062                 gfar_write(&regs->igaddr6, 0xffffffff);
3063                 gfar_write(&regs->igaddr7, 0xffffffff);
3064                 gfar_write(&regs->gaddr0, 0xffffffff);
3065                 gfar_write(&regs->gaddr1, 0xffffffff);
3066                 gfar_write(&regs->gaddr2, 0xffffffff);
3067                 gfar_write(&regs->gaddr3, 0xffffffff);
3068                 gfar_write(&regs->gaddr4, 0xffffffff);
3069                 gfar_write(&regs->gaddr5, 0xffffffff);
3070                 gfar_write(&regs->gaddr6, 0xffffffff);
3071                 gfar_write(&regs->gaddr7, 0xffffffff);
3072         } else {
3073                 int em_num;
3074                 int idx;
3075
3076                 /* zero out the hash */
3077                 gfar_write(&regs->igaddr0, 0x0);
3078                 gfar_write(&regs->igaddr1, 0x0);
3079                 gfar_write(&regs->igaddr2, 0x0);
3080                 gfar_write(&regs->igaddr3, 0x0);
3081                 gfar_write(&regs->igaddr4, 0x0);
3082                 gfar_write(&regs->igaddr5, 0x0);
3083                 gfar_write(&regs->igaddr6, 0x0);
3084                 gfar_write(&regs->igaddr7, 0x0);
3085                 gfar_write(&regs->gaddr0, 0x0);
3086                 gfar_write(&regs->gaddr1, 0x0);
3087                 gfar_write(&regs->gaddr2, 0x0);
3088                 gfar_write(&regs->gaddr3, 0x0);
3089                 gfar_write(&regs->gaddr4, 0x0);
3090                 gfar_write(&regs->gaddr5, 0x0);
3091                 gfar_write(&regs->gaddr6, 0x0);
3092                 gfar_write(&regs->gaddr7, 0x0);
3093
3094                 /* If we have extended hash tables, we need to
3095                  * clear the exact match registers to prepare for
3096                  * setting them
3097                  */
3098                 if (priv->extended_hash) {
3099                         em_num = GFAR_EM_NUM + 1;
3100                         gfar_clear_exact_match(dev);
3101                         idx = 1;
3102                 } else {
3103                         idx = 0;
3104                         em_num = 0;
3105                 }
3106
3107                 if (netdev_mc_empty(dev))
3108                         return;
3109
3110                 /* Parse the list, and set the appropriate bits */
3111                 netdev_for_each_mc_addr(ha, dev) {
3112                         if (idx < em_num) {
3113                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3114                                 idx++;
3115                         } else
3116                                 gfar_set_hash_for_addr(dev, ha->addr);
3117                 }
3118         }
3119 }
3120
3121
3122 /* Clears each of the exact match registers to zero, so they
3123  * don't interfere with normal reception
3124  */
3125 static void gfar_clear_exact_match(struct net_device *dev)
3126 {
3127         int idx;
3128         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3129
3130         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3131                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3132 }
3133
3134 /* Set the appropriate hash bit for the given addr */
3135 /* The algorithm works like so:
3136  * 1) Take the Destination Address (ie the multicast address), and
3137  * do a CRC on it (little endian), and reverse the bits of the
3138  * result.
3139  * 2) Use the 8 most significant bits as a hash into a 256-entry
3140  * table.  The table is controlled through 8 32-bit registers:
3141  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3142  * gaddr7.  This means that the 3 most significant bits in the
3143  * hash index which gaddr register to use, and the 5 other bits
3144  * indicate which bit (assuming an IBM numbering scheme, which
3145  * for PowerPC (tm) is usually the case) in the register holds
3146  * the entry.
3147  */
3148 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3149 {
3150         u32 tempval;
3151         struct gfar_private *priv = netdev_priv(dev);
3152         u32 result = ether_crc(ETH_ALEN, addr);
3153         int width = priv->hash_width;
3154         u8 whichbit = (result >> (32 - width)) & 0x1f;
3155         u8 whichreg = result >> (32 - width + 5);
3156         u32 value = (1 << (31-whichbit));
3157
3158         tempval = gfar_read(priv->hash_regs[whichreg]);
3159         tempval |= value;
3160         gfar_write(priv->hash_regs[whichreg], tempval);
3161 }
3162
3163
3164 /* There are multiple MAC Address register pairs on some controllers
3165  * This function sets the numth pair to a given address
3166  */
3167 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3168                                   const u8 *addr)
3169 {
3170         struct gfar_private *priv = netdev_priv(dev);
3171         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3172         int idx;
3173         char tmpbuf[ETH_ALEN];
3174         u32 tempval;
3175         u32 __iomem *macptr = &regs->macstnaddr1;
3176
3177         macptr += num*2;
3178
3179         /* Now copy it into the mac registers backwards, cuz
3180          * little endian is silly
3181          */
3182         for (idx = 0; idx < ETH_ALEN; idx++)
3183                 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3184
3185         gfar_write(macptr, *((u32 *) (tmpbuf)));
3186
3187         tempval = *((u32 *) (tmpbuf + 4));
3188
3189         gfar_write(macptr+1, tempval);
3190 }
3191
3192 /* GFAR error interrupt handler */
3193 static irqreturn_t gfar_error(int irq, void *grp_id)
3194 {
3195         struct gfar_priv_grp *gfargrp = grp_id;
3196         struct gfar __iomem *regs = gfargrp->regs;
3197         struct gfar_private *priv= gfargrp->priv;
3198         struct net_device *dev = priv->ndev;
3199
3200         /* Save ievent for future reference */
3201         u32 events = gfar_read(&regs->ievent);
3202
3203         /* Clear IEVENT */
3204         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3205
3206         /* Magic Packet is not an error. */
3207         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3208             (events & IEVENT_MAG))
3209                 events &= ~IEVENT_MAG;
3210
3211         /* Hmm... */
3212         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3213                 netdev_dbg(dev,
3214                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3215                            events, gfar_read(&regs->imask));
3216
3217         /* Update the error counters */
3218         if (events & IEVENT_TXE) {
3219                 dev->stats.tx_errors++;
3220
3221                 if (events & IEVENT_LC)
3222                         dev->stats.tx_window_errors++;
3223                 if (events & IEVENT_CRL)
3224                         dev->stats.tx_aborted_errors++;
3225                 if (events & IEVENT_XFUN) {
3226                         unsigned long flags;
3227
3228                         netif_dbg(priv, tx_err, dev,
3229                                   "TX FIFO underrun, packet dropped\n");
3230                         dev->stats.tx_dropped++;
3231                         priv->extra_stats.tx_underrun++;
3232
3233                         local_irq_save(flags);
3234                         lock_tx_qs(priv);
3235
3236                         /* Reactivate the Tx Queues */
3237                         gfar_write(&regs->tstat, gfargrp->tstat);
3238
3239                         unlock_tx_qs(priv);
3240                         local_irq_restore(flags);
3241                 }
3242                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3243         }
3244         if (events & IEVENT_BSY) {
3245                 dev->stats.rx_errors++;
3246                 priv->extra_stats.rx_bsy++;
3247
3248                 gfar_receive(irq, grp_id);
3249
3250                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3251                           gfar_read(&regs->rstat));
3252         }
3253         if (events & IEVENT_BABR) {
3254                 dev->stats.rx_errors++;
3255                 priv->extra_stats.rx_babr++;
3256
3257                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3258         }
3259         if (events & IEVENT_EBERR) {
3260                 priv->extra_stats.eberr++;
3261                 netif_dbg(priv, rx_err, dev, "bus error\n");
3262         }
3263         if (events & IEVENT_RXC)
3264                 netif_dbg(priv, rx_status, dev, "control frame\n");
3265
3266         if (events & IEVENT_BABT) {
3267                 priv->extra_stats.tx_babt++;
3268                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3269         }
3270         return IRQ_HANDLED;
3271 }
3272
3273 static struct of_device_id gfar_match[] =
3274 {
3275         {
3276                 .type = "network",
3277                 .compatible = "gianfar",
3278         },
3279         {
3280                 .compatible = "fsl,etsec2",
3281         },
3282         {},
3283 };
3284 MODULE_DEVICE_TABLE(of, gfar_match);
3285
3286 /* Structure for a device driver */
3287 static struct platform_driver gfar_driver = {
3288         .driver = {
3289                 .name = "fsl-gianfar",
3290                 .owner = THIS_MODULE,
3291                 .pm = GFAR_PM_OPS,
3292                 .of_match_table = gfar_match,
3293         },
3294         .probe = gfar_probe,
3295         .remove = gfar_remove,
3296 };
3297
3298 module_platform_driver(gfar_driver);