drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/of_mdio.h>
  82 #include <linux/of_platform.h>
  83 #include <linux/ip.h>
  84 #include <linux/tcp.h>
  85 #include <linux/udp.h>
  86 #include <linux/in.h>
  87 #include <linux/net_tstamp.h>
  88
  89 #include <asm/io.h>
  90 #include <asm/reg.h>
  91 #include <asm/irq.h>
  92 #include <asm/uaccess.h>
  93 #include <linux/module.h>
  94 #include <linux/dma-mapping.h>
  95 #include <linux/crc32.h>
  96 #include <linux/mii.h>
  97 #include <linux/phy.h>
  98 #include <linux/phy_fixed.h>
  99 #include <linux/of.h>
 100 #include <linux/of_net.h>
 101
 102 #include "gianfar.h"
 103
 104 #define TX_TIMEOUT      (1*HZ)
 105
 106 const char gfar_driver_version[] = "1.3";
 107
 108 static int gfar_enet_open(struct net_device *dev);
 109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 110 static void gfar_reset_task(struct work_struct *work);
 111 static void gfar_timeout(struct net_device *dev);
 112 static int gfar_close(struct net_device *dev);
 113 struct sk_buff *gfar_new_skb(struct net_device *dev);
 114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 115                            struct sk_buff *skb);
 116 static int gfar_set_mac_address(struct net_device *dev);
 117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 118 static irqreturn_t gfar_error(int irq, void *dev_id);
 119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 121 static void adjust_link(struct net_device *dev);
 122 static void init_registers(struct net_device *dev);
 123 static int init_phy(struct net_device *dev);
 124 static int gfar_probe(struct platform_device *ofdev);
 125 static int gfar_remove(struct platform_device *ofdev);
 126 static void free_skb_resources(struct gfar_private *priv);
 127 static void gfar_set_multi(struct net_device *dev);
 128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 129 static void gfar_configure_serdes(struct net_device *dev);
 130 static int gfar_poll(struct napi_struct *napi, int budget);
 131 #ifdef CONFIG_NET_POLL_CONTROLLER
 132 static void gfar_netpoll(struct net_device *dev);
 133 #endif
 134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 136 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 137                               int amount_pull, struct napi_struct *napi);
 138 void gfar_halt(struct net_device *dev);
 139 static void gfar_halt_nodisable(struct net_device *dev);
 140 void gfar_start(struct net_device *dev);
 141 static void gfar_clear_exact_match(struct net_device *dev);
 142 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 143                                   const u8 *addr);
 144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 145
 146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 148 MODULE_LICENSE("GPL");
 149
 150 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 151                             dma_addr_t buf)
 152 {
 153         u32 lstatus;
 154
 155         bdp->bufPtr = buf;
 156
 157         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 158         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 159                 lstatus |= BD_LFLAG(RXBD_WRAP);
 160
 161         eieio();
 162
 163         bdp->lstatus = lstatus;
 164 }
 165
 166 static int gfar_init_bds(struct net_device *ndev)
 167 {
 168         struct gfar_private *priv = netdev_priv(ndev);
 169         struct gfar_priv_tx_q *tx_queue = NULL;
 170         struct gfar_priv_rx_q *rx_queue = NULL;
 171         struct txbd8 *txbdp;
 172         struct rxbd8 *rxbdp;
 173         int i, j;
 174
 175         for (i = 0; i < priv->num_tx_queues; i++) {
 176                 tx_queue = priv->tx_queue[i];
 177                 /* Initialize some variables in our dev structure */
 178                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 179                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 180                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 181                 tx_queue->skb_curtx = 0;
 182                 tx_queue->skb_dirtytx = 0;
 183
 184                 /* Initialize Transmit Descriptor Ring */
 185                 txbdp = tx_queue->tx_bd_base;
 186                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 187                         txbdp->lstatus = 0;
 188                         txbdp->bufPtr = 0;
 189                         txbdp++;
 190                 }
 191
 192                 /* Set the last descriptor in the ring to indicate wrap */
 193                 txbdp--;
 194                 txbdp->status |= TXBD_WRAP;
 195         }
 196
 197         for (i = 0; i < priv->num_rx_queues; i++) {
 198                 rx_queue = priv->rx_queue[i];
 199                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 200                 rx_queue->skb_currx = 0;
 201                 rxbdp = rx_queue->rx_bd_base;
 202
 203                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 204                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 205
 206                         if (skb) {
 207                                 gfar_init_rxbdp(rx_queue, rxbdp,
 208                                                 rxbdp->bufPtr);
 209                         } else {
 210                                 skb = gfar_new_skb(ndev);
 211                                 if (!skb) {
 212                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 213                                         return -ENOMEM;
 214                                 }
 215                                 rx_queue->rx_skbuff[j] = skb;
 216
 217                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 218                         }
 219
 220                         rxbdp++;
 221                 }
 222
 223         }
 224
 225         return 0;
 226 }
 227
 228 static int gfar_alloc_skb_resources(struct net_device *ndev)
 229 {
 230         void *vaddr;
 231         dma_addr_t addr;
 232         int i, j, k;
 233         struct gfar_private *priv = netdev_priv(ndev);
 234         struct device *dev = &priv->ofdev->dev;
 235         struct gfar_priv_tx_q *tx_queue = NULL;
 236         struct gfar_priv_rx_q *rx_queue = NULL;
 237
 238         priv->total_tx_ring_size = 0;
 239         for (i = 0; i < priv->num_tx_queues; i++)
 240                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 241
 242         priv->total_rx_ring_size = 0;
 243         for (i = 0; i < priv->num_rx_queues; i++)
 244                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 245
 246         /* Allocate memory for the buffer descriptors */
 247         vaddr = dma_alloc_coherent(dev,
 248                         sizeof(struct txbd8) * priv->total_tx_ring_size +
 249                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
 250                         &addr, GFP_KERNEL);
 251         if (!vaddr) {
 252                 netif_err(priv, ifup, ndev,
 253                           "Could not allocate buffer descriptors!\n");
 254                 return -ENOMEM;
 255         }
 256
 257         for (i = 0; i < priv->num_tx_queues; i++) {
 258                 tx_queue = priv->tx_queue[i];
 259                 tx_queue->tx_bd_base = vaddr;
 260                 tx_queue->tx_bd_dma_base = addr;
 261                 tx_queue->dev = ndev;
 262                 /* enet DMA only understands physical addresses */
 263                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 264                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 265         }
 266
 267         /* Start the rx descriptor ring where the tx ring leaves off */
 268         for (i = 0; i < priv->num_rx_queues; i++) {
 269                 rx_queue = priv->rx_queue[i];
 270                 rx_queue->rx_bd_base = vaddr;
 271                 rx_queue->rx_bd_dma_base = addr;
 272                 rx_queue->dev = ndev;
 273                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 274                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 275         }
 276
 277         /* Setup the skbuff rings */
 278         for (i = 0; i < priv->num_tx_queues; i++) {
 279                 tx_queue = priv->tx_queue[i];
 280                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
 281                                               tx_queue->tx_ring_size,
 282                                               GFP_KERNEL);
 283                 if (!tx_queue->tx_skbuff) {
 284                         netif_err(priv, ifup, ndev,
 285                                   "Could not allocate tx_skbuff\n");
 286                         goto cleanup;
 287                 }
 288
 289                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 290                         tx_queue->tx_skbuff[k] = NULL;
 291         }
 292
 293         for (i = 0; i < priv->num_rx_queues; i++) {
 294                 rx_queue = priv->rx_queue[i];
 295                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
 296                                               rx_queue->rx_ring_size,
 297                                               GFP_KERNEL);
 298
 299                 if (!rx_queue->rx_skbuff) {
 300                         netif_err(priv, ifup, ndev,
 301                                   "Could not allocate rx_skbuff\n");
 302                         goto cleanup;
 303                 }
 304
 305                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 306                         rx_queue->rx_skbuff[j] = NULL;
 307         }
 308
 309         if (gfar_init_bds(ndev))
 310                 goto cleanup;
 311
 312         return 0;
 313
 314 cleanup:
 315         free_skb_resources(priv);
 316         return -ENOMEM;
 317 }
 318
 319 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 320 {
 321         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 322         u32 __iomem *baddr;
 323         int i;
 324
 325         baddr = &regs->tbase0;
 326         for (i = 0; i < priv->num_tx_queues; i++) {
 327                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 328                 baddr += 2;
 329         }
 330
 331         baddr = &regs->rbase0;
 332         for (i = 0; i < priv->num_rx_queues; i++) {
 333                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 334                 baddr += 2;
 335         }
 336 }
 337
 338 static void gfar_init_mac(struct net_device *ndev)
 339 {
 340         struct gfar_private *priv = netdev_priv(ndev);
 341         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 342         u32 rctrl = 0;
 343         u32 tctrl = 0;
 344         u32 attrs = 0;
 345
 346         /* write the tx/rx base registers */
 347         gfar_init_tx_rx_base(priv);
 348
 349         /* Configure the coalescing support */
 350         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 351
 352         if (priv->rx_filer_enable) {
 353                 rctrl |= RCTRL_FILREN;
 354                 /* Program the RIR0 reg with the required distribution */
 355                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 356         }
 357
 358         /* Restore PROMISC mode */
 359         if (ndev->flags & IFF_PROMISC)
 360                 rctrl |= RCTRL_PROM;
 361
 362         if (ndev->features & NETIF_F_RXCSUM)
 363                 rctrl |= RCTRL_CHECKSUMMING;
 364
 365         if (priv->extended_hash) {
 366                 rctrl |= RCTRL_EXTHASH;
 367
 368                 gfar_clear_exact_match(ndev);
 369                 rctrl |= RCTRL_EMEN;
 370         }
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Insert receive time stamps into padding alignment bytes */
 378         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 379                 rctrl &= ~RCTRL_PAL_MASK;
 380                 rctrl |= RCTRL_PADDING(8);
 381                 priv->padding = 8;
 382         }
 383
 384         /* Enable HW time stamping if requested from user space */
 385         if (priv->hwts_rx_en)
 386                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 387
 388         if (ndev->features & NETIF_F_HW_VLAN_RX)
 389                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 390
 391         /* Init rctrl based on our settings */
 392         gfar_write(&regs->rctrl, rctrl);
 393
 394         if (ndev->features & NETIF_F_IP_CSUM)
 395                 tctrl |= TCTRL_INIT_CSUM;
 396
 397         if (priv->prio_sched_en)
 398                 tctrl |= TCTRL_TXSCHED_PRIO;
 399         else {
 400                 tctrl |= TCTRL_TXSCHED_WRRS;
 401                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 402                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 403         }
 404
 405         gfar_write(&regs->tctrl, tctrl);
 406
 407         /* Set the extraction length and index */
 408         attrs = ATTRELI_EL(priv->rx_stash_size) |
 409                 ATTRELI_EI(priv->rx_stash_index);
 410
 411         gfar_write(&regs->attreli, attrs);
 412
 413         /* Start with defaults, and add stashing or locking
 414          * depending on the approprate variables
 415          */
 416         attrs = ATTR_INIT_SETTINGS;
 417
 418         if (priv->bd_stash_en)
 419                 attrs |= ATTR_BDSTASH;
 420
 421         if (priv->rx_stash_size != 0)
 422                 attrs |= ATTR_BUFSTASH;
 423
 424         gfar_write(&regs->attr, attrs);
 425
 426         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 427         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 428         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 429 }
 430
 431 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 432 {
 433         struct gfar_private *priv = netdev_priv(dev);
 434         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 435         unsigned long tx_packets = 0, tx_bytes = 0;
 436         int i;
 437
 438         for (i = 0; i < priv->num_rx_queues; i++) {
 439                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 440                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 441                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 442         }
 443
 444         dev->stats.rx_packets = rx_packets;
 445         dev->stats.rx_bytes   = rx_bytes;
 446         dev->stats.rx_dropped = rx_dropped;
 447
 448         for (i = 0; i < priv->num_tx_queues; i++) {
 449                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 450                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 451         }
 452
 453         dev->stats.tx_bytes   = tx_bytes;
 454         dev->stats.tx_packets = tx_packets;
 455
 456         return &dev->stats;
 457 }
 458
 459 static const struct net_device_ops gfar_netdev_ops = {
 460         .ndo_open = gfar_enet_open,
 461         .ndo_start_xmit = gfar_start_xmit,
 462         .ndo_stop = gfar_close,
 463         .ndo_change_mtu = gfar_change_mtu,
 464         .ndo_set_features = gfar_set_features,
 465         .ndo_set_rx_mode = gfar_set_multi,
 466         .ndo_tx_timeout = gfar_timeout,
 467         .ndo_do_ioctl = gfar_ioctl,
 468         .ndo_get_stats = gfar_get_stats,
 469         .ndo_set_mac_address = eth_mac_addr,
 470         .ndo_validate_addr = eth_validate_addr,
 471 #ifdef CONFIG_NET_POLL_CONTROLLER
 472         .ndo_poll_controller = gfar_netpoll,
 473 #endif
 474 };
 475
 476 void lock_rx_qs(struct gfar_private *priv)
 477 {
 478         int i;
 479
 480         for (i = 0; i < priv->num_rx_queues; i++)
 481                 spin_lock(&priv->rx_queue[i]->rxlock);
 482 }
 483
 484 void lock_tx_qs(struct gfar_private *priv)
 485 {
 486         int i;
 487
 488         for (i = 0; i < priv->num_tx_queues; i++)
 489                 spin_lock(&priv->tx_queue[i]->txlock);
 490 }
 491
 492 void unlock_rx_qs(struct gfar_private *priv)
 493 {
 494         int i;
 495
 496         for (i = 0; i < priv->num_rx_queues; i++)
 497                 spin_unlock(&priv->rx_queue[i]->rxlock);
 498 }
 499
 500 void unlock_tx_qs(struct gfar_private *priv)
 501 {
 502         int i;
 503
 504         for (i = 0; i < priv->num_tx_queues; i++)
 505                 spin_unlock(&priv->tx_queue[i]->txlock);
 506 }
 507
 508 static bool gfar_is_vlan_on(struct gfar_private *priv)
 509 {
 510         return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
 511                (priv->ndev->features & NETIF_F_HW_VLAN_TX);
 512 }
 513
 514 /* Returns 1 if incoming frames use an FCB */
 515 static inline int gfar_uses_fcb(struct gfar_private *priv)
 516 {
 517         return gfar_is_vlan_on(priv) ||
 518                (priv->ndev->features & NETIF_F_RXCSUM) ||
 519                (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
 520 }
 521
 522 static void free_tx_pointers(struct gfar_private *priv)
 523 {
 524         int i;
 525
 526         for (i = 0; i < priv->num_tx_queues; i++)
 527                 kfree(priv->tx_queue[i]);
 528 }
 529
 530 static void free_rx_pointers(struct gfar_private *priv)
 531 {
 532         int i;
 533
 534         for (i = 0; i < priv->num_rx_queues; i++)
 535                 kfree(priv->rx_queue[i]);
 536 }
 537
 538 static void unmap_group_regs(struct gfar_private *priv)
 539 {
 540         int i;
 541
 542         for (i = 0; i < MAXGROUPS; i++)
 543                 if (priv->gfargrp[i].regs)
 544                         iounmap(priv->gfargrp[i].regs);
 545 }
 546
 547 static void free_gfar_dev(struct gfar_private *priv)
 548 {
 549         int i, j;
 550
 551         for (i = 0; i < priv->num_grps; i++)
 552                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 553                         kfree(priv->gfargrp[i].irqinfo[j]);
 554                         priv->gfargrp[i].irqinfo[j] = NULL;
 555                 }
 556
 557         free_netdev(priv->ndev);
 558 }
 559
 560 static void disable_napi(struct gfar_private *priv)
 561 {
 562         int i;
 563
 564         for (i = 0; i < priv->num_grps; i++)
 565                 napi_disable(&priv->gfargrp[i].napi);
 566 }
 567
 568 static void enable_napi(struct gfar_private *priv)
 569 {
 570         int i;
 571
 572         for (i = 0; i < priv->num_grps; i++)
 573                 napi_enable(&priv->gfargrp[i].napi);
 574 }
 575
 576 static int gfar_parse_group(struct device_node *np,
 577                             struct gfar_private *priv, const char *model)
 578 {
 579         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 580         u32 *queue_mask;
 581         int i;
 582
 583         if (priv->mode == MQ_MG_MODE) {
 584                 for (i = 0; i < GFAR_NUM_IRQS; i++) {
 585                         grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 586                                                   GFP_KERNEL);
 587                         if (!grp->irqinfo[i])
 588                                 return -ENOMEM;
 589                 }
 590         } else {
 591                 grp->irqinfo[GFAR_TX] = kzalloc(sizeof(struct gfar_irqinfo),
 592                                                 GFP_KERNEL);
 593                 if (!grp->irqinfo[GFAR_TX])
 594                         return -ENOMEM;
 595                 grp->irqinfo[GFAR_RX] = grp->irqinfo[GFAR_ER] = NULL;
 596         }
 597
 598         grp->regs = of_iomap(np, 0);
 599         if (!grp->regs)
 600                 return -ENOMEM;
 601
 602         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 603
 604         /* If we aren't the FEC we have multiple interrupts */
 605         if (model && strcasecmp(model, "FEC")) {
 606                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 607                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 608                 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
 609                     gfar_irq(grp, RX)->irq == NO_IRQ ||
 610                     gfar_irq(grp, ER)->irq == NO_IRQ)
 611                         return -EINVAL;
 612         }
 613
 614         grp->grp_id = priv->num_grps;
 615         grp->priv = priv;
 616         spin_lock_init(&grp->grplock);
 617         if (priv->mode == MQ_MG_MODE) {
 618                 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
 619                 grp->rx_bit_map = queue_mask ?
 620                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 621                 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
 622                 grp->tx_bit_map = queue_mask ?
 623                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 624         } else {
 625                 grp->rx_bit_map = 0xFF;
 626                 grp->tx_bit_map = 0xFF;
 627         }
 628         priv->num_grps++;
 629
 630         return 0;
 631 }
 632
 633 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 634 {
 635         const char *model;
 636         const char *ctype;
 637         const void *mac_addr;
 638         int err = 0, i;
 639         struct net_device *dev = NULL;
 640         struct gfar_private *priv = NULL;
 641         struct device_node *np = ofdev->dev.of_node;
 642         struct device_node *child = NULL;
 643         const u32 *stash;
 644         const u32 *stash_len;
 645         const u32 *stash_idx;
 646         unsigned int num_tx_qs, num_rx_qs;
 647         u32 *tx_queues, *rx_queues;
 648
 649         if (!np || !of_device_is_available(np))
 650                 return -ENODEV;
 651
 652         /* parse the num of tx and rx queues */
 653         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 654         num_tx_qs = tx_queues ? *tx_queues : 1;
 655
 656         if (num_tx_qs > MAX_TX_QS) {
 657                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 658                        num_tx_qs, MAX_TX_QS);
 659                 pr_err("Cannot do alloc_etherdev, aborting\n");
 660                 return -EINVAL;
 661         }
 662
 663         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 664         num_rx_qs = rx_queues ? *rx_queues : 1;
 665
 666         if (num_rx_qs > MAX_RX_QS) {
 667                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 668                        num_rx_qs, MAX_RX_QS);
 669                 pr_err("Cannot do alloc_etherdev, aborting\n");
 670                 return -EINVAL;
 671         }
 672
 673         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 674         dev = *pdev;
 675         if (NULL == dev)
 676                 return -ENOMEM;
 677
 678         priv = netdev_priv(dev);
 679         priv->node = ofdev->dev.of_node;
 680         priv->ndev = dev;
 681
 682         priv->num_tx_queues = num_tx_qs;
 683         netif_set_real_num_rx_queues(dev, num_rx_qs);
 684         priv->num_rx_queues = num_rx_qs;
 685         priv->num_grps = 0x0;
 686
 687         /* Init Rx queue filer rule set linked list */
 688         INIT_LIST_HEAD(&priv->rx_list.list);
 689         priv->rx_list.count = 0;
 690         mutex_init(&priv->rx_queue_access);
 691
 692         model = of_get_property(np, "model", NULL);
 693
 694         for (i = 0; i < MAXGROUPS; i++)
 695                 priv->gfargrp[i].regs = NULL;
 696
 697         /* Parse and initialize group specific information */
 698         if (of_device_is_compatible(np, "fsl,etsec2")) {
 699                 priv->mode = MQ_MG_MODE;
 700                 for_each_child_of_node(np, child) {
 701                         err = gfar_parse_group(child, priv, model);
 702                         if (err)
 703                                 goto err_grp_init;
 704                 }
 705         } else {
 706                 priv->mode = SQ_SG_MODE;
 707                 err = gfar_parse_group(np, priv, model);
 708                 if (err)
 709                         goto err_grp_init;
 710         }
 711
 712         for (i = 0; i < priv->num_tx_queues; i++)
 713                priv->tx_queue[i] = NULL;
 714         for (i = 0; i < priv->num_rx_queues; i++)
 715                 priv->rx_queue[i] = NULL;
 716
 717         for (i = 0; i < priv->num_tx_queues; i++) {
 718                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 719                                             GFP_KERNEL);
 720                 if (!priv->tx_queue[i]) {
 721                         err = -ENOMEM;
 722                         goto tx_alloc_failed;
 723                 }
 724                 priv->tx_queue[i]->tx_skbuff = NULL;
 725                 priv->tx_queue[i]->qindex = i;
 726                 priv->tx_queue[i]->dev = dev;
 727                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 728         }
 729
 730         for (i = 0; i < priv->num_rx_queues; i++) {
 731                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 732                                             GFP_KERNEL);
 733                 if (!priv->rx_queue[i]) {
 734                         err = -ENOMEM;
 735                         goto rx_alloc_failed;
 736                 }
 737                 priv->rx_queue[i]->rx_skbuff = NULL;
 738                 priv->rx_queue[i]->qindex = i;
 739                 priv->rx_queue[i]->dev = dev;
 740                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 741         }
 742
 743
 744         stash = of_get_property(np, "bd-stash", NULL);
 745
 746         if (stash) {
 747                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 748                 priv->bd_stash_en = 1;
 749         }
 750
 751         stash_len = of_get_property(np, "rx-stash-len", NULL);
 752
 753         if (stash_len)
 754                 priv->rx_stash_size = *stash_len;
 755
 756         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 757
 758         if (stash_idx)
 759                 priv->rx_stash_index = *stash_idx;
 760
 761         if (stash_len || stash_idx)
 762                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 763
 764         mac_addr = of_get_mac_address(np);
 765
 766         if (mac_addr)
 767                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 768
 769         if (model && !strcasecmp(model, "TSEC"))
 770                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 771                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 772                                      FSL_GIANFAR_DEV_HAS_RMON |
 773                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 774
 775         if (model && !strcasecmp(model, "eTSEC"))
 776                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 777                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 778                                      FSL_GIANFAR_DEV_HAS_RMON |
 779                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 780                                      FSL_GIANFAR_DEV_HAS_PADDING |
 781                                      FSL_GIANFAR_DEV_HAS_CSUM |
 782                                      FSL_GIANFAR_DEV_HAS_VLAN |
 783                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 784                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 785                                      FSL_GIANFAR_DEV_HAS_TIMER;
 786
 787         ctype = of_get_property(np, "phy-connection-type", NULL);
 788
 789         /* We only care about rgmii-id.  The rest are autodetected */
 790         if (ctype && !strcmp(ctype, "rgmii-id"))
 791                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 792         else
 793                 priv->interface = PHY_INTERFACE_MODE_MII;
 794
 795         if (of_get_property(np, "fsl,magic-packet", NULL))
 796                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 797
 798         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 799
 800         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 801         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 802
 803         return 0;
 804
 805 rx_alloc_failed:
 806         free_rx_pointers(priv);
 807 tx_alloc_failed:
 808         free_tx_pointers(priv);
 809 err_grp_init:
 810         unmap_group_regs(priv);
 811         free_gfar_dev(priv);
 812         return err;
 813 }
 814
 815 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 816                                struct ifreq *ifr, int cmd)
 817 {
 818         struct hwtstamp_config config;
 819         struct gfar_private *priv = netdev_priv(netdev);
 820
 821         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 822                 return -EFAULT;
 823
 824         /* reserved for future extensions */
 825         if (config.flags)
 826                 return -EINVAL;
 827
 828         switch (config.tx_type) {
 829         case HWTSTAMP_TX_OFF:
 830                 priv->hwts_tx_en = 0;
 831                 break;
 832         case HWTSTAMP_TX_ON:
 833                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 834                         return -ERANGE;
 835                 priv->hwts_tx_en = 1;
 836                 break;
 837         default:
 838                 return -ERANGE;
 839         }
 840
 841         switch (config.rx_filter) {
 842         case HWTSTAMP_FILTER_NONE:
 843                 if (priv->hwts_rx_en) {
 844                         stop_gfar(netdev);
 845                         priv->hwts_rx_en = 0;
 846                         startup_gfar(netdev);
 847                 }
 848                 break;
 849         default:
 850                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 851                         return -ERANGE;
 852                 if (!priv->hwts_rx_en) {
 853                         stop_gfar(netdev);
 854                         priv->hwts_rx_en = 1;
 855                         startup_gfar(netdev);
 856                 }
 857                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 858                 break;
 859         }
 860
 861         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 862                 -EFAULT : 0;
 863 }
 864
 865 /* Ioctl MII Interface */
 866 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 867 {
 868         struct gfar_private *priv = netdev_priv(dev);
 869
 870         if (!netif_running(dev))
 871                 return -EINVAL;
 872
 873         if (cmd == SIOCSHWTSTAMP)
 874                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 875
 876         if (!priv->phydev)
 877                 return -ENODEV;
 878
 879         return phy_mii_ioctl(priv->phydev, rq, cmd);
 880 }
 881
 882 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 883 {
 884         unsigned int new_bit_map = 0x0;
 885         int mask = 0x1 << (max_qs - 1), i;
 886
 887         for (i = 0; i < max_qs; i++) {
 888                 if (bit_map & mask)
 889                         new_bit_map = new_bit_map + (1 << i);
 890                 mask = mask >> 0x1;
 891         }
 892         return new_bit_map;
 893 }
 894
 895 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 896                                    u32 class)
 897 {
 898         u32 rqfpr = FPR_FILER_MASK;
 899         u32 rqfcr = 0x0;
 900
 901         rqfar--;
 902         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 903         priv->ftp_rqfpr[rqfar] = rqfpr;
 904         priv->ftp_rqfcr[rqfar] = rqfcr;
 905         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 906
 907         rqfar--;
 908         rqfcr = RQFCR_CMP_NOMATCH;
 909         priv->ftp_rqfpr[rqfar] = rqfpr;
 910         priv->ftp_rqfcr[rqfar] = rqfcr;
 911         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 912
 913         rqfar--;
 914         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 915         rqfpr = class;
 916         priv->ftp_rqfcr[rqfar] = rqfcr;
 917         priv->ftp_rqfpr[rqfar] = rqfpr;
 918         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 919
 920         rqfar--;
 921         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 922         rqfpr = class;
 923         priv->ftp_rqfcr[rqfar] = rqfcr;
 924         priv->ftp_rqfpr[rqfar] = rqfpr;
 925         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 926
 927         return rqfar;
 928 }
 929
 930 static void gfar_init_filer_table(struct gfar_private *priv)
 931 {
 932         int i = 0x0;
 933         u32 rqfar = MAX_FILER_IDX;
 934         u32 rqfcr = 0x0;
 935         u32 rqfpr = FPR_FILER_MASK;
 936
 937         /* Default rule */
 938         rqfcr = RQFCR_CMP_MATCH;
 939         priv->ftp_rqfcr[rqfar] = rqfcr;
 940         priv->ftp_rqfpr[rqfar] = rqfpr;
 941         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 942
 943         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 944         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 945         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 946         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 947         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 948         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 949
 950         /* cur_filer_idx indicated the first non-masked rule */
 951         priv->cur_filer_idx = rqfar;
 952
 953         /* Rest are masked rules */
 954         rqfcr = RQFCR_CMP_NOMATCH;
 955         for (i = 0; i < rqfar; i++) {
 956                 priv->ftp_rqfcr[i] = rqfcr;
 957                 priv->ftp_rqfpr[i] = rqfpr;
 958                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 959         }
 960 }
 961
 962 static void gfar_detect_errata(struct gfar_private *priv)
 963 {
 964         struct device *dev = &priv->ofdev->dev;
 965         unsigned int pvr = mfspr(SPRN_PVR);
 966         unsigned int svr = mfspr(SPRN_SVR);
 967         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 968         unsigned int rev = svr & 0xffff;
 969
 970         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 971         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 972             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 973                 priv->errata |= GFAR_ERRATA_74;
 974
 975         /* MPC8313 and MPC837x all rev */
 976         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 977             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 978                 priv->errata |= GFAR_ERRATA_76;
 979
 980         /* MPC8313 and MPC837x all rev */
 981         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 982             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 983                 priv->errata |= GFAR_ERRATA_A002;
 984
 985         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
 986         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
 987             (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
 988                 priv->errata |= GFAR_ERRATA_12;
 989
 990         if (priv->errata)
 991                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 992                          priv->errata);
 993 }
 994
 995 /* Set up the ethernet device structure, private data,
 996  * and anything else we need before we start
 997  */
 998 static int gfar_probe(struct platform_device *ofdev)
 999 {
1000         u32 tempval;
1001         struct net_device *dev = NULL;
1002         struct gfar_private *priv = NULL;
1003         struct gfar __iomem *regs = NULL;
1004         int err = 0, i, grp_idx = 0;
1005         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
1006         u32 isrg = 0;
1007         u32 __iomem *baddr;
1008
1009         err = gfar_of_init(ofdev, &dev);
1010
1011         if (err)
1012                 return err;
1013
1014         priv = netdev_priv(dev);
1015         priv->ndev = dev;
1016         priv->ofdev = ofdev;
1017         priv->node = ofdev->dev.of_node;
1018         SET_NETDEV_DEV(dev, &ofdev->dev);
1019
1020         spin_lock_init(&priv->bflock);
1021         INIT_WORK(&priv->reset_task, gfar_reset_task);
1022
1023         dev_set_drvdata(&ofdev->dev, priv);
1024         regs = priv->gfargrp[0].regs;
1025
1026         gfar_detect_errata(priv);
1027
1028         /* Stop the DMA engine now, in case it was running before
1029          * (The firmware could have used it, and left it running).
1030          */
1031         gfar_halt(dev);
1032
1033         /* Reset MAC layer */
1034         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1035
1036         /* We need to delay at least 3 TX clocks */
1037         udelay(2);
1038
1039         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1040         gfar_write(&regs->maccfg1, tempval);
1041
1042         /* Initialize MACCFG2. */
1043         tempval = MACCFG2_INIT_SETTINGS;
1044         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1045                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1046         gfar_write(&regs->maccfg2, tempval);
1047
1048         /* Initialize ECNTRL */
1049         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1050
1051         /* Set the dev->base_addr to the gfar reg region */
1052         dev->base_addr = (unsigned long) regs;
1053
1054         SET_NETDEV_DEV(dev, &ofdev->dev);
1055
1056         /* Fill in the dev structure */
1057         dev->watchdog_timeo = TX_TIMEOUT;
1058         dev->mtu = 1500;
1059         dev->netdev_ops = &gfar_netdev_ops;
1060         dev->ethtool_ops = &gfar_ethtool_ops;
1061
1062         /* Register for napi ...We are registering NAPI for each grp */
1063         for (i = 0; i < priv->num_grps; i++)
1064                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1065                                GFAR_DEV_WEIGHT);
1066
1067         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1068                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1069                                    NETIF_F_RXCSUM;
1070                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1071                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1072         }
1073
1074         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1075                 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1076                 dev->features |= NETIF_F_HW_VLAN_RX;
1077         }
1078
1079         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1080                 priv->extended_hash = 1;
1081                 priv->hash_width = 9;
1082
1083                 priv->hash_regs[0] = &regs->igaddr0;
1084                 priv->hash_regs[1] = &regs->igaddr1;
1085                 priv->hash_regs[2] = &regs->igaddr2;
1086                 priv->hash_regs[3] = &regs->igaddr3;
1087                 priv->hash_regs[4] = &regs->igaddr4;
1088                 priv->hash_regs[5] = &regs->igaddr5;
1089                 priv->hash_regs[6] = &regs->igaddr6;
1090                 priv->hash_regs[7] = &regs->igaddr7;
1091                 priv->hash_regs[8] = &regs->gaddr0;
1092                 priv->hash_regs[9] = &regs->gaddr1;
1093                 priv->hash_regs[10] = &regs->gaddr2;
1094                 priv->hash_regs[11] = &regs->gaddr3;
1095                 priv->hash_regs[12] = &regs->gaddr4;
1096                 priv->hash_regs[13] = &regs->gaddr5;
1097                 priv->hash_regs[14] = &regs->gaddr6;
1098                 priv->hash_regs[15] = &regs->gaddr7;
1099
1100         } else {
1101                 priv->extended_hash = 0;
1102                 priv->hash_width = 8;
1103
1104                 priv->hash_regs[0] = &regs->gaddr0;
1105                 priv->hash_regs[1] = &regs->gaddr1;
1106                 priv->hash_regs[2] = &regs->gaddr2;
1107                 priv->hash_regs[3] = &regs->gaddr3;
1108                 priv->hash_regs[4] = &regs->gaddr4;
1109                 priv->hash_regs[5] = &regs->gaddr5;
1110                 priv->hash_regs[6] = &regs->gaddr6;
1111                 priv->hash_regs[7] = &regs->gaddr7;
1112         }
1113
1114         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1115                 priv->padding = DEFAULT_PADDING;
1116         else
1117                 priv->padding = 0;
1118
1119         if (dev->features & NETIF_F_IP_CSUM ||
1120             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1121                 dev->needed_headroom = GMAC_FCB_LEN;
1122
1123         /* Program the isrg regs only if number of grps > 1 */
1124         if (priv->num_grps > 1) {
1125                 baddr = &regs->isrg0;
1126                 for (i = 0; i < priv->num_grps; i++) {
1127                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1128                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1129                         gfar_write(baddr, isrg);
1130                         baddr++;
1131                         isrg = 0x0;
1132                 }
1133         }
1134
1135         /* Need to reverse the bit maps as  bit_map's MSB is q0
1136          * but, for_each_set_bit parses from right to left, which
1137          * basically reverses the queue numbers
1138          */
1139         for (i = 0; i< priv->num_grps; i++) {
1140                 priv->gfargrp[i].tx_bit_map =
1141                         reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1142                 priv->gfargrp[i].rx_bit_map =
1143                         reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1144         }
1145
1146         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1147          * also assign queues to groups
1148          */
1149         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1150                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1151
1152                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1153                                  priv->num_rx_queues) {
1154                         priv->gfargrp[grp_idx].num_rx_queues++;
1155                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1156                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1157                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1158                 }
1159                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1160
1161                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1162                                  priv->num_tx_queues) {
1163                         priv->gfargrp[grp_idx].num_tx_queues++;
1164                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1165                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1166                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1167                 }
1168                 priv->gfargrp[grp_idx].rstat = rstat;
1169                 priv->gfargrp[grp_idx].tstat = tstat;
1170                 rstat = tstat =0;
1171         }
1172
1173         gfar_write(&regs->rqueue, rqueue);
1174         gfar_write(&regs->tqueue, tqueue);
1175
1176         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1177
1178         /* Initializing some of the rx/tx queue level parameters */
1179         for (i = 0; i < priv->num_tx_queues; i++) {
1180                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1181                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1182                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1183                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1184         }
1185
1186         for (i = 0; i < priv->num_rx_queues; i++) {
1187                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1188                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1189                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1190         }
1191
1192         /* always enable rx filer */
1193         priv->rx_filer_enable = 1;
1194         /* Enable most messages by default */
1195         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1196         /* use pritority h/w tx queue scheduling for single queue devices */
1197         if (priv->num_tx_queues == 1)
1198                 priv->prio_sched_en = 1;
1199
1200         /* Carrier starts down, phylib will bring it up */
1201         netif_carrier_off(dev);
1202
1203         err = register_netdev(dev);
1204
1205         if (err) {
1206                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1207                 goto register_fail;
1208         }
1209
1210         device_init_wakeup(&dev->dev,
1211                            priv->device_flags &
1212                            FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1213
1214         /* fill out IRQ number and name fields */
1215         for (i = 0; i < priv->num_grps; i++) {
1216                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1217                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1218                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1219                                 dev->name, "_g", '0' + i, "_tx");
1220                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1221                                 dev->name, "_g", '0' + i, "_rx");
1222                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1223                                 dev->name, "_g", '0' + i, "_er");
1224                 } else
1225                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1226         }
1227
1228         /* Initialize the filer table */
1229         gfar_init_filer_table(priv);
1230
1231         /* Create all the sysfs files */
1232         gfar_init_sysfs(dev);
1233
1234         /* Print out the device info */
1235         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1236
1237         /* Even more device info helps when determining which kernel
1238          * provided which set of benchmarks.
1239          */
1240         netdev_info(dev, "Running with NAPI enabled\n");
1241         for (i = 0; i < priv->num_rx_queues; i++)
1242                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1243                             i, priv->rx_queue[i]->rx_ring_size);
1244         for (i = 0; i < priv->num_tx_queues; i++)
1245                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1246                             i, priv->tx_queue[i]->tx_ring_size);
1247
1248         return 0;
1249
1250 register_fail:
1251         unmap_group_regs(priv);
1252         free_tx_pointers(priv);
1253         free_rx_pointers(priv);
1254         if (priv->phy_node)
1255                 of_node_put(priv->phy_node);
1256         if (priv->tbi_node)
1257                 of_node_put(priv->tbi_node);
1258         free_gfar_dev(priv);
1259         return err;
1260 }
1261
1262 static int gfar_remove(struct platform_device *ofdev)
1263 {
1264         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1265
1266         if (priv->phy_node)
1267                 of_node_put(priv->phy_node);
1268         if (priv->tbi_node)
1269                 of_node_put(priv->tbi_node);
1270
1271         dev_set_drvdata(&ofdev->dev, NULL);
1272
1273         unregister_netdev(priv->ndev);
1274         unmap_group_regs(priv);
1275         free_gfar_dev(priv);
1276
1277         return 0;
1278 }
1279
1280 #ifdef CONFIG_PM
1281
1282 static int gfar_suspend(struct device *dev)
1283 {
1284         struct gfar_private *priv = dev_get_drvdata(dev);
1285         struct net_device *ndev = priv->ndev;
1286         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1287         unsigned long flags;
1288         u32 tempval;
1289
1290         int magic_packet = priv->wol_en &&
1291                            (priv->device_flags &
1292                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1293
1294         netif_device_detach(ndev);
1295
1296         if (netif_running(ndev)) {
1297
1298                 local_irq_save(flags);
1299                 lock_tx_qs(priv);
1300                 lock_rx_qs(priv);
1301
1302                 gfar_halt_nodisable(ndev);
1303
1304                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1305                 tempval = gfar_read(&regs->maccfg1);
1306
1307                 tempval &= ~MACCFG1_TX_EN;
1308
1309                 if (!magic_packet)
1310                         tempval &= ~MACCFG1_RX_EN;
1311
1312                 gfar_write(&regs->maccfg1, tempval);
1313
1314                 unlock_rx_qs(priv);
1315                 unlock_tx_qs(priv);
1316                 local_irq_restore(flags);
1317
1318                 disable_napi(priv);
1319
1320                 if (magic_packet) {
1321                         /* Enable interrupt on Magic Packet */
1322                         gfar_write(&regs->imask, IMASK_MAG);
1323
1324                         /* Enable Magic Packet mode */
1325                         tempval = gfar_read(&regs->maccfg2);
1326                         tempval |= MACCFG2_MPEN;
1327                         gfar_write(&regs->maccfg2, tempval);
1328                 } else {
1329                         phy_stop(priv->phydev);
1330                 }
1331         }
1332
1333         return 0;
1334 }
1335
1336 static int gfar_resume(struct device *dev)
1337 {
1338         struct gfar_private *priv = dev_get_drvdata(dev);
1339         struct net_device *ndev = priv->ndev;
1340         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1341         unsigned long flags;
1342         u32 tempval;
1343         int magic_packet = priv->wol_en &&
1344                            (priv->device_flags &
1345                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1346
1347         if (!netif_running(ndev)) {
1348                 netif_device_attach(ndev);
1349                 return 0;
1350         }
1351
1352         if (!magic_packet && priv->phydev)
1353                 phy_start(priv->phydev);
1354
1355         /* Disable Magic Packet mode, in case something
1356          * else woke us up.
1357          */
1358         local_irq_save(flags);
1359         lock_tx_qs(priv);
1360         lock_rx_qs(priv);
1361
1362         tempval = gfar_read(&regs->maccfg2);
1363         tempval &= ~MACCFG2_MPEN;
1364         gfar_write(&regs->maccfg2, tempval);
1365
1366         gfar_start(ndev);
1367
1368         unlock_rx_qs(priv);
1369         unlock_tx_qs(priv);
1370         local_irq_restore(flags);
1371
1372         netif_device_attach(ndev);
1373
1374         enable_napi(priv);
1375
1376         return 0;
1377 }
1378
1379 static int gfar_restore(struct device *dev)
1380 {
1381         struct gfar_private *priv = dev_get_drvdata(dev);
1382         struct net_device *ndev = priv->ndev;
1383
1384         if (!netif_running(ndev)) {
1385                 netif_device_attach(ndev);
1386
1387                 return 0;
1388         }
1389
1390         if (gfar_init_bds(ndev)) {
1391                 free_skb_resources(priv);
1392                 return -ENOMEM;
1393         }
1394
1395         init_registers(ndev);
1396         gfar_set_mac_address(ndev);
1397         gfar_init_mac(ndev);
1398         gfar_start(ndev);
1399
1400         priv->oldlink = 0;
1401         priv->oldspeed = 0;
1402         priv->oldduplex = -1;
1403
1404         if (priv->phydev)
1405                 phy_start(priv->phydev);
1406
1407         netif_device_attach(ndev);
1408         enable_napi(priv);
1409
1410         return 0;
1411 }
1412
1413 static struct dev_pm_ops gfar_pm_ops = {
1414         .suspend = gfar_suspend,
1415         .resume = gfar_resume,
1416         .freeze = gfar_suspend,
1417         .thaw = gfar_resume,
1418         .restore = gfar_restore,
1419 };
1420
1421 #define GFAR_PM_OPS (&gfar_pm_ops)
1422
1423 #else
1424
1425 #define GFAR_PM_OPS NULL
1426
1427 #endif
1428
1429 /* Reads the controller's registers to determine what interface
1430  * connects it to the PHY.
1431  */
1432 static phy_interface_t gfar_get_interface(struct net_device *dev)
1433 {
1434         struct gfar_private *priv = netdev_priv(dev);
1435         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1436         u32 ecntrl;
1437
1438         ecntrl = gfar_read(&regs->ecntrl);
1439
1440         if (ecntrl & ECNTRL_SGMII_MODE)
1441                 return PHY_INTERFACE_MODE_SGMII;
1442
1443         if (ecntrl & ECNTRL_TBI_MODE) {
1444                 if (ecntrl & ECNTRL_REDUCED_MODE)
1445                         return PHY_INTERFACE_MODE_RTBI;
1446                 else
1447                         return PHY_INTERFACE_MODE_TBI;
1448         }
1449
1450         if (ecntrl & ECNTRL_REDUCED_MODE) {
1451                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1452                         return PHY_INTERFACE_MODE_RMII;
1453                 }
1454                 else {
1455                         phy_interface_t interface = priv->interface;
1456
1457                         /* This isn't autodetected right now, so it must
1458                          * be set by the device tree or platform code.
1459                          */
1460                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1461                                 return PHY_INTERFACE_MODE_RGMII_ID;
1462
1463                         return PHY_INTERFACE_MODE_RGMII;
1464                 }
1465         }
1466
1467         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1468                 return PHY_INTERFACE_MODE_GMII;
1469
1470         return PHY_INTERFACE_MODE_MII;
1471 }
1472
1473
1474 /* Initializes driver's PHY state, and attaches to the PHY.
1475  * Returns 0 on success.
1476  */
1477 static int init_phy(struct net_device *dev)
1478 {
1479         struct gfar_private *priv = netdev_priv(dev);
1480         uint gigabit_support =
1481                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1482                 SUPPORTED_1000baseT_Full : 0;
1483         phy_interface_t interface;
1484
1485         priv->oldlink = 0;
1486         priv->oldspeed = 0;
1487         priv->oldduplex = -1;
1488
1489         interface = gfar_get_interface(dev);
1490
1491         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1492                                       interface);
1493         if (!priv->phydev)
1494                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1495                                                          interface);
1496         if (!priv->phydev) {
1497                 dev_err(&dev->dev, "could not attach to PHY\n");
1498                 return -ENODEV;
1499         }
1500
1501         if (interface == PHY_INTERFACE_MODE_SGMII)
1502                 gfar_configure_serdes(dev);
1503
1504         /* Remove any features not supported by the controller */
1505         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1506         priv->phydev->advertising = priv->phydev->supported;
1507
1508         return 0;
1509 }
1510
1511 /* Initialize TBI PHY interface for communicating with the
1512  * SERDES lynx PHY on the chip.  We communicate with this PHY
1513  * through the MDIO bus on each controller, treating it as a
1514  * "normal" PHY at the address found in the TBIPA register.  We assume
1515  * that the TBIPA register is valid.  Either the MDIO bus code will set
1516  * it to a value that doesn't conflict with other PHYs on the bus, or the
1517  * value doesn't matter, as there are no other PHYs on the bus.
1518  */
1519 static void gfar_configure_serdes(struct net_device *dev)
1520 {
1521         struct gfar_private *priv = netdev_priv(dev);
1522         struct phy_device *tbiphy;
1523
1524         if (!priv->tbi_node) {
1525                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1526                                     "device tree specify a tbi-handle\n");
1527                 return;
1528         }
1529
1530         tbiphy = of_phy_find_device(priv->tbi_node);
1531         if (!tbiphy) {
1532                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1533                 return;
1534         }
1535
1536         /* If the link is already up, we must already be ok, and don't need to
1537          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1538          * everything for us?  Resetting it takes the link down and requires
1539          * several seconds for it to come back.
1540          */
1541         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1542                 return;
1543
1544         /* Single clk mode, mii mode off(for serdes communication) */
1545         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1546
1547         phy_write(tbiphy, MII_ADVERTISE,
1548                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1549                   ADVERTISE_1000XPSE_ASYM);
1550
1551         phy_write(tbiphy, MII_BMCR,
1552                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1553                   BMCR_SPEED1000);
1554 }
1555
1556 static void init_registers(struct net_device *dev)
1557 {
1558         struct gfar_private *priv = netdev_priv(dev);
1559         struct gfar __iomem *regs = NULL;
1560         int i;
1561
1562         for (i = 0; i < priv->num_grps; i++) {
1563                 regs = priv->gfargrp[i].regs;
1564                 /* Clear IEVENT */
1565                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1566
1567                 /* Initialize IMASK */
1568                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1569         }
1570
1571         regs = priv->gfargrp[0].regs;
1572         /* Init hash registers to zero */
1573         gfar_write(&regs->igaddr0, 0);
1574         gfar_write(&regs->igaddr1, 0);
1575         gfar_write(&regs->igaddr2, 0);
1576         gfar_write(&regs->igaddr3, 0);
1577         gfar_write(&regs->igaddr4, 0);
1578         gfar_write(&regs->igaddr5, 0);
1579         gfar_write(&regs->igaddr6, 0);
1580         gfar_write(&regs->igaddr7, 0);
1581
1582         gfar_write(&regs->gaddr0, 0);
1583         gfar_write(&regs->gaddr1, 0);
1584         gfar_write(&regs->gaddr2, 0);
1585         gfar_write(&regs->gaddr3, 0);
1586         gfar_write(&regs->gaddr4, 0);
1587         gfar_write(&regs->gaddr5, 0);
1588         gfar_write(&regs->gaddr6, 0);
1589         gfar_write(&regs->gaddr7, 0);
1590
1591         /* Zero out the rmon mib registers if it has them */
1592         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1593                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1594
1595                 /* Mask off the CAM interrupts */
1596                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1597                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1598         }
1599
1600         /* Initialize the max receive buffer length */
1601         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1602
1603         /* Initialize the Minimum Frame Length Register */
1604         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1605 }
1606
1607 static int __gfar_is_rx_idle(struct gfar_private *priv)
1608 {
1609         u32 res;
1610
1611         /* Normaly TSEC should not hang on GRS commands, so we should
1612          * actually wait for IEVENT_GRSC flag.
1613          */
1614         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1615                 return 0;
1616
1617         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1618          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1619          * and the Rx can be safely reset.
1620          */
1621         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1622         res &= 0x7f807f80;
1623         if ((res & 0xffff) == (res >> 16))
1624                 return 1;
1625
1626         return 0;
1627 }
1628
1629 /* Halt the receive and transmit queues */
1630 static void gfar_halt_nodisable(struct net_device *dev)
1631 {
1632         struct gfar_private *priv = netdev_priv(dev);
1633         struct gfar __iomem *regs = NULL;
1634         u32 tempval;
1635         int i;
1636
1637         for (i = 0; i < priv->num_grps; i++) {
1638                 regs = priv->gfargrp[i].regs;
1639                 /* Mask all interrupts */
1640                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1641
1642                 /* Clear all interrupts */
1643                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1644         }
1645
1646         regs = priv->gfargrp[0].regs;
1647         /* Stop the DMA, and wait for it to stop */
1648         tempval = gfar_read(&regs->dmactrl);
1649         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1650             (DMACTRL_GRS | DMACTRL_GTS)) {
1651                 int ret;
1652
1653                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1654                 gfar_write(&regs->dmactrl, tempval);
1655
1656                 do {
1657                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1658                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1659                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1660                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1661                                 ret = __gfar_is_rx_idle(priv);
1662                 } while (!ret);
1663         }
1664 }
1665
1666 /* Halt the receive and transmit queues */
1667 void gfar_halt(struct net_device *dev)
1668 {
1669         struct gfar_private *priv = netdev_priv(dev);
1670         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1671         u32 tempval;
1672
1673         gfar_halt_nodisable(dev);
1674
1675         /* Disable Rx and Tx */
1676         tempval = gfar_read(&regs->maccfg1);
1677         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1678         gfar_write(&regs->maccfg1, tempval);
1679 }
1680
1681 static void free_grp_irqs(struct gfar_priv_grp *grp)
1682 {
1683         free_irq(gfar_irq(grp, TX)->irq, grp);
1684         free_irq(gfar_irq(grp, RX)->irq, grp);
1685         free_irq(gfar_irq(grp, ER)->irq, grp);
1686 }
1687
1688 void stop_gfar(struct net_device *dev)
1689 {
1690         struct gfar_private *priv = netdev_priv(dev);
1691         unsigned long flags;
1692         int i;
1693
1694         phy_stop(priv->phydev);
1695
1696
1697         /* Lock it down */
1698         local_irq_save(flags);
1699         lock_tx_qs(priv);
1700         lock_rx_qs(priv);
1701
1702         gfar_halt(dev);
1703
1704         unlock_rx_qs(priv);
1705         unlock_tx_qs(priv);
1706         local_irq_restore(flags);
1707
1708         /* Free the IRQs */
1709         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1710                 for (i = 0; i < priv->num_grps; i++)
1711                         free_grp_irqs(&priv->gfargrp[i]);
1712         } else {
1713                 for (i = 0; i < priv->num_grps; i++)
1714                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1715                                  &priv->gfargrp[i]);
1716         }
1717
1718         free_skb_resources(priv);
1719 }
1720
1721 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1722 {
1723         struct txbd8 *txbdp;
1724         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1725         int i, j;
1726
1727         txbdp = tx_queue->tx_bd_base;
1728
1729         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1730                 if (!tx_queue->tx_skbuff[i])
1731                         continue;
1732
1733                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1734                                  txbdp->length, DMA_TO_DEVICE);
1735                 txbdp->lstatus = 0;
1736                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1737                      j++) {
1738                         txbdp++;
1739                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1740                                        txbdp->length, DMA_TO_DEVICE);
1741                 }
1742                 txbdp++;
1743                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1744                 tx_queue->tx_skbuff[i] = NULL;
1745         }
1746         kfree(tx_queue->tx_skbuff);
1747         tx_queue->tx_skbuff = NULL;
1748 }
1749
1750 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1751 {
1752         struct rxbd8 *rxbdp;
1753         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1754         int i;
1755
1756         rxbdp = rx_queue->rx_bd_base;
1757
1758         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1759                 if (rx_queue->rx_skbuff[i]) {
1760                         dma_unmap_single(&priv->ofdev->dev,
1761                                          rxbdp->bufPtr, priv->rx_buffer_size,
1762                                          DMA_FROM_DEVICE);
1763                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1764                         rx_queue->rx_skbuff[i] = NULL;
1765                 }
1766                 rxbdp->lstatus = 0;
1767                 rxbdp->bufPtr = 0;
1768                 rxbdp++;
1769         }
1770         kfree(rx_queue->rx_skbuff);
1771         rx_queue->rx_skbuff = NULL;
1772 }
1773
1774 /* If there are any tx skbs or rx skbs still around, free them.
1775  * Then free tx_skbuff and rx_skbuff
1776  */
1777 static void free_skb_resources(struct gfar_private *priv)
1778 {
1779         struct gfar_priv_tx_q *tx_queue = NULL;
1780         struct gfar_priv_rx_q *rx_queue = NULL;
1781         int i;
1782
1783         /* Go through all the buffer descriptors and free their data buffers */
1784         for (i = 0; i < priv->num_tx_queues; i++) {
1785                 struct netdev_queue *txq;
1786
1787                 tx_queue = priv->tx_queue[i];
1788                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1789                 if (tx_queue->tx_skbuff)
1790                         free_skb_tx_queue(tx_queue);
1791                 netdev_tx_reset_queue(txq);
1792         }
1793
1794         for (i = 0; i < priv->num_rx_queues; i++) {
1795                 rx_queue = priv->rx_queue[i];
1796                 if (rx_queue->rx_skbuff)
1797                         free_skb_rx_queue(rx_queue);
1798         }
1799
1800         dma_free_coherent(&priv->ofdev->dev,
1801                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1802                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1803                           priv->tx_queue[0]->tx_bd_base,
1804                           priv->tx_queue[0]->tx_bd_dma_base);
1805 }
1806
1807 void gfar_start(struct net_device *dev)
1808 {
1809         struct gfar_private *priv = netdev_priv(dev);
1810         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1811         u32 tempval;
1812         int i = 0;
1813
1814         /* Enable Rx and Tx in MACCFG1 */
1815         tempval = gfar_read(&regs->maccfg1);
1816         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1817         gfar_write(&regs->maccfg1, tempval);
1818
1819         /* Initialize DMACTRL to have WWR and WOP */
1820         tempval = gfar_read(&regs->dmactrl);
1821         tempval |= DMACTRL_INIT_SETTINGS;
1822         gfar_write(&regs->dmactrl, tempval);
1823
1824         /* Make sure we aren't stopped */
1825         tempval = gfar_read(&regs->dmactrl);
1826         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1827         gfar_write(&regs->dmactrl, tempval);
1828
1829         for (i = 0; i < priv->num_grps; i++) {
1830                 regs = priv->gfargrp[i].regs;
1831                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1832                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1833                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1834                 /* Unmask the interrupts we look for */
1835                 gfar_write(&regs->imask, IMASK_DEFAULT);
1836         }
1837
1838         dev->trans_start = jiffies; /* prevent tx timeout */
1839 }
1840
1841 void gfar_configure_coalescing(struct gfar_private *priv,
1842                                unsigned long tx_mask, unsigned long rx_mask)
1843 {
1844         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1845         u32 __iomem *baddr;
1846         int i = 0;
1847
1848         /* Backward compatible case ---- even if we enable
1849          * multiple queues, there's only single reg to program
1850          */
1851         gfar_write(&regs->txic, 0);
1852         if (likely(priv->tx_queue[0]->txcoalescing))
1853                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1854
1855         gfar_write(&regs->rxic, 0);
1856         if (unlikely(priv->rx_queue[0]->rxcoalescing))
1857                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1858
1859         if (priv->mode == MQ_MG_MODE) {
1860                 baddr = &regs->txic0;
1861                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1862                         gfar_write(baddr + i, 0);
1863                         if (likely(priv->tx_queue[i]->txcoalescing))
1864                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1865                 }
1866
1867                 baddr = &regs->rxic0;
1868                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1869                         gfar_write(baddr + i, 0);
1870                         if (likely(priv->rx_queue[i]->rxcoalescing))
1871                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1872                 }
1873         }
1874 }
1875
1876 static int register_grp_irqs(struct gfar_priv_grp *grp)
1877 {
1878         struct gfar_private *priv = grp->priv;
1879         struct net_device *dev = priv->ndev;
1880         int err;
1881
1882         /* If the device has multiple interrupts, register for
1883          * them.  Otherwise, only register for the one
1884          */
1885         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1886                 /* Install our interrupt handlers for Error,
1887                  * Transmit, and Receive
1888                  */
1889                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1890                                   gfar_irq(grp, ER)->name, grp);
1891                 if (err < 0) {
1892                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1893                                   gfar_irq(grp, ER)->irq);
1894
1895                         goto err_irq_fail;
1896                 }
1897                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1898                                   gfar_irq(grp, TX)->name, grp);
1899                 if (err < 0) {
1900                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1901                                   gfar_irq(grp, TX)->irq);
1902                         goto tx_irq_fail;
1903                 }
1904                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1905                                   gfar_irq(grp, RX)->name, grp);
1906                 if (err < 0) {
1907                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1908                                   gfar_irq(grp, RX)->irq);
1909                         goto rx_irq_fail;
1910                 }
1911         } else {
1912                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1913                                   gfar_irq(grp, TX)->name, grp);
1914                 if (err < 0) {
1915                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1916                                   gfar_irq(grp, TX)->irq);
1917                         goto err_irq_fail;
1918                 }
1919         }
1920
1921         return 0;
1922
1923 rx_irq_fail:
1924         free_irq(gfar_irq(grp, TX)->irq, grp);
1925 tx_irq_fail:
1926         free_irq(gfar_irq(grp, ER)->irq, grp);
1927 err_irq_fail:
1928         return err;
1929
1930 }
1931
1932 /* Bring the controller up and running */
1933 int startup_gfar(struct net_device *ndev)
1934 {
1935         struct gfar_private *priv = netdev_priv(ndev);
1936         struct gfar __iomem *regs = NULL;
1937         int err, i, j;
1938
1939         for (i = 0; i < priv->num_grps; i++) {
1940                 regs= priv->gfargrp[i].regs;
1941                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1942         }
1943
1944         regs= priv->gfargrp[0].regs;
1945         err = gfar_alloc_skb_resources(ndev);
1946         if (err)
1947                 return err;
1948
1949         gfar_init_mac(ndev);
1950
1951         for (i = 0; i < priv->num_grps; i++) {
1952                 err = register_grp_irqs(&priv->gfargrp[i]);
1953                 if (err) {
1954                         for (j = 0; j < i; j++)
1955                                 free_grp_irqs(&priv->gfargrp[j]);
1956                         goto irq_fail;
1957                 }
1958         }
1959
1960         /* Start the controller */
1961         gfar_start(ndev);
1962
1963         phy_start(priv->phydev);
1964
1965         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1966
1967         return 0;
1968
1969 irq_fail:
1970         free_skb_resources(priv);
1971         return err;
1972 }
1973
1974 /* Called when something needs to use the ethernet device
1975  * Returns 0 for success.
1976  */
1977 static int gfar_enet_open(struct net_device *dev)
1978 {
1979         struct gfar_private *priv = netdev_priv(dev);
1980         int err;
1981
1982         enable_napi(priv);
1983
1984         /* Initialize a bunch of registers */
1985         init_registers(dev);
1986
1987         gfar_set_mac_address(dev);
1988
1989         err = init_phy(dev);
1990
1991         if (err) {
1992                 disable_napi(priv);
1993                 return err;
1994         }
1995
1996         err = startup_gfar(dev);
1997         if (err) {
1998                 disable_napi(priv);
1999                 return err;
2000         }
2001
2002         netif_tx_start_all_queues(dev);
2003
2004         device_set_wakeup_enable(&dev->dev, priv->wol_en);
2005
2006         return err;
2007 }
2008
2009 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2010 {
2011         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2012
2013         memset(fcb, 0, GMAC_FCB_LEN);
2014
2015         return fcb;
2016 }
2017
2018 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2019                                     int fcb_length)
2020 {
2021         /* If we're here, it's a IP packet with a TCP or UDP
2022          * payload.  We set it to checksum, using a pseudo-header
2023          * we provide
2024          */
2025         u8 flags = TXFCB_DEFAULT;
2026
2027         /* Tell the controller what the protocol is
2028          * And provide the already calculated phcs
2029          */
2030         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2031                 flags |= TXFCB_UDP;
2032                 fcb->phcs = udp_hdr(skb)->check;
2033         } else
2034                 fcb->phcs = tcp_hdr(skb)->check;
2035
2036         /* l3os is the distance between the start of the
2037          * frame (skb->data) and the start of the IP hdr.
2038          * l4os is the distance between the start of the
2039          * l3 hdr and the l4 hdr
2040          */
2041         fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2042         fcb->l4os = skb_network_header_len(skb);
2043
2044         fcb->flags = flags;
2045 }
2046
2047 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2048 {
2049         fcb->flags |= TXFCB_VLN;
2050         fcb->vlctl = vlan_tx_tag_get(skb);
2051 }
2052
2053 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2054                                       struct txbd8 *base, int ring_size)
2055 {
2056         struct txbd8 *new_bd = bdp + stride;
2057
2058         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2059 }
2060
2061 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2062                                       int ring_size)
2063 {
2064         return skip_txbd(bdp, 1, base, ring_size);
2065 }
2066
2067 /* This is called by the kernel when a frame is ready for transmission.
2068  * It is pointed to by the dev->hard_start_xmit function pointer
2069  */
2070 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2071 {
2072         struct gfar_private *priv = netdev_priv(dev);
2073         struct gfar_priv_tx_q *tx_queue = NULL;
2074         struct netdev_queue *txq;
2075         struct gfar __iomem *regs = NULL;
2076         struct txfcb *fcb = NULL;
2077         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2078         u32 lstatus;
2079         int i, rq = 0, do_tstamp = 0;
2080         u32 bufaddr;
2081         unsigned long flags;
2082         unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2083
2084         /* TOE=1 frames larger than 2500 bytes may see excess delays
2085          * before start of transmission.
2086          */
2087         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2088                      skb->ip_summed == CHECKSUM_PARTIAL &&
2089                      skb->len > 2500)) {
2090                 int ret;
2091
2092                 ret = skb_checksum_help(skb);
2093                 if (ret)
2094                         return ret;
2095         }
2096
2097         rq = skb->queue_mapping;
2098         tx_queue = priv->tx_queue[rq];
2099         txq = netdev_get_tx_queue(dev, rq);
2100         base = tx_queue->tx_bd_base;
2101         regs = tx_queue->grp->regs;
2102
2103         /* check if time stamp should be generated */
2104         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2105                      priv->hwts_tx_en)) {
2106                 do_tstamp = 1;
2107                 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2108         }
2109
2110         /* make space for additional header when fcb is needed */
2111         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2112              vlan_tx_tag_present(skb) ||
2113              unlikely(do_tstamp)) &&
2114             (skb_headroom(skb) < fcb_length)) {
2115                 struct sk_buff *skb_new;
2116
2117                 skb_new = skb_realloc_headroom(skb, fcb_length);
2118                 if (!skb_new) {
2119                         dev->stats.tx_errors++;
2120                         kfree_skb(skb);
2121                         return NETDEV_TX_OK;
2122                 }
2123
2124                 if (skb->sk)
2125                         skb_set_owner_w(skb_new, skb->sk);
2126                 consume_skb(skb);
2127                 skb = skb_new;
2128         }
2129
2130         /* total number of fragments in the SKB */
2131         nr_frags = skb_shinfo(skb)->nr_frags;
2132
2133         /* calculate the required number of TxBDs for this skb */
2134         if (unlikely(do_tstamp))
2135                 nr_txbds = nr_frags + 2;
2136         else
2137                 nr_txbds = nr_frags + 1;
2138
2139         /* check if there is space to queue this packet */
2140         if (nr_txbds > tx_queue->num_txbdfree) {
2141                 /* no space, stop the queue */
2142                 netif_tx_stop_queue(txq);
2143                 dev->stats.tx_fifo_errors++;
2144                 return NETDEV_TX_BUSY;
2145         }
2146
2147         /* Update transmit stats */
2148         tx_queue->stats.tx_bytes += skb->len;
2149         tx_queue->stats.tx_packets++;
2150
2151         txbdp = txbdp_start = tx_queue->cur_tx;
2152         lstatus = txbdp->lstatus;
2153
2154         /* Time stamp insertion requires one additional TxBD */
2155         if (unlikely(do_tstamp))
2156                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2157                                                  tx_queue->tx_ring_size);
2158
2159         if (nr_frags == 0) {
2160                 if (unlikely(do_tstamp))
2161                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2162                                                           TXBD_INTERRUPT);
2163                 else
2164                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2165         } else {
2166                 /* Place the fragment addresses and lengths into the TxBDs */
2167                 for (i = 0; i < nr_frags; i++) {
2168                         /* Point at the next BD, wrapping as needed */
2169                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2170
2171                         length = skb_shinfo(skb)->frags[i].size;
2172
2173                         lstatus = txbdp->lstatus | length |
2174                                   BD_LFLAG(TXBD_READY);
2175
2176                         /* Handle the last BD specially */
2177                         if (i == nr_frags - 1)
2178                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2179
2180                         bufaddr = skb_frag_dma_map(&priv->ofdev->dev,
2181                                                    &skb_shinfo(skb)->frags[i],
2182                                                    0,
2183                                                    length,
2184                                                    DMA_TO_DEVICE);
2185
2186                         /* set the TxBD length and buffer pointer */
2187                         txbdp->bufPtr = bufaddr;
2188                         txbdp->lstatus = lstatus;
2189                 }
2190
2191                 lstatus = txbdp_start->lstatus;
2192         }
2193
2194         /* Add TxPAL between FCB and frame if required */
2195         if (unlikely(do_tstamp)) {
2196                 skb_push(skb, GMAC_TXPAL_LEN);
2197                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2198         }
2199
2200         /* Set up checksumming */
2201         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2202                 fcb = gfar_add_fcb(skb);
2203                 /* as specified by errata */
2204                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2205                              ((unsigned long)fcb % 0x20) > 0x18)) {
2206                         __skb_pull(skb, GMAC_FCB_LEN);
2207                         skb_checksum_help(skb);
2208                 } else {
2209                         lstatus |= BD_LFLAG(TXBD_TOE);
2210                         gfar_tx_checksum(skb, fcb, fcb_length);
2211                 }
2212         }
2213
2214         if (vlan_tx_tag_present(skb)) {
2215                 if (unlikely(NULL == fcb)) {
2216                         fcb = gfar_add_fcb(skb);
2217                         lstatus |= BD_LFLAG(TXBD_TOE);
2218                 }
2219
2220                 gfar_tx_vlan(skb, fcb);
2221         }
2222
2223         /* Setup tx hardware time stamping if requested */
2224         if (unlikely(do_tstamp)) {
2225                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2226                 if (fcb == NULL)
2227                         fcb = gfar_add_fcb(skb);
2228                 fcb->ptp = 1;
2229                 lstatus |= BD_LFLAG(TXBD_TOE);
2230         }
2231
2232         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2233                                              skb_headlen(skb), DMA_TO_DEVICE);
2234
2235         /* If time stamping is requested one additional TxBD must be set up. The
2236          * first TxBD points to the FCB and must have a data length of
2237          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2238          * the full frame length.
2239          */
2240         if (unlikely(do_tstamp)) {
2241                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2242                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2243                                          (skb_headlen(skb) - fcb_length);
2244                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2245         } else {
2246                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2247         }
2248
2249         netdev_tx_sent_queue(txq, skb->len);
2250
2251         /* We can work in parallel with gfar_clean_tx_ring(), except
2252          * when modifying num_txbdfree. Note that we didn't grab the lock
2253          * when we were reading the num_txbdfree and checking for available
2254          * space, that's because outside of this function it can only grow,
2255          * and once we've got needed space, it cannot suddenly disappear.
2256          *
2257          * The lock also protects us from gfar_error(), which can modify
2258          * regs->tstat and thus retrigger the transfers, which is why we
2259          * also must grab the lock before setting ready bit for the first
2260          * to be transmitted BD.
2261          */
2262         spin_lock_irqsave(&tx_queue->txlock, flags);
2263
2264         /* The powerpc-specific eieio() is used, as wmb() has too strong
2265          * semantics (it requires synchronization between cacheable and
2266          * uncacheable mappings, which eieio doesn't provide and which we
2267          * don't need), thus requiring a more expensive sync instruction.  At
2268          * some point, the set of architecture-independent barrier functions
2269          * should be expanded to include weaker barriers.
2270          */
2271         eieio();
2272
2273         txbdp_start->lstatus = lstatus;
2274
2275         eieio(); /* force lstatus write before tx_skbuff */
2276
2277         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2278
2279         /* Update the current skb pointer to the next entry we will use
2280          * (wrapping if necessary)
2281          */
2282         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2283                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2284
2285         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2286
2287         /* reduce TxBD free count */
2288         tx_queue->num_txbdfree -= (nr_txbds);
2289
2290         /* If the next BD still needs to be cleaned up, then the bds
2291          * are full.  We need to tell the kernel to stop sending us stuff.
2292          */
2293         if (!tx_queue->num_txbdfree) {
2294                 netif_tx_stop_queue(txq);
2295
2296                 dev->stats.tx_fifo_errors++;
2297         }
2298
2299         /* Tell the DMA to go go go */
2300         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2301
2302         /* Unlock priv */
2303         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2304
2305         return NETDEV_TX_OK;
2306 }
2307
2308 /* Stops the kernel queue, and halts the controller */
2309 static int gfar_close(struct net_device *dev)
2310 {
2311         struct gfar_private *priv = netdev_priv(dev);
2312
2313         disable_napi(priv);
2314
2315         cancel_work_sync(&priv->reset_task);
2316         stop_gfar(dev);
2317
2318         /* Disconnect from the PHY */
2319         phy_disconnect(priv->phydev);
2320         priv->phydev = NULL;
2321
2322         netif_tx_stop_all_queues(dev);
2323
2324         return 0;
2325 }
2326
2327 /* Changes the mac address if the controller is not running. */
2328 static int gfar_set_mac_address(struct net_device *dev)
2329 {
2330         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2331
2332         return 0;
2333 }
2334
2335 /* Check if rx parser should be activated */
2336 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2337 {
2338         struct gfar __iomem *regs;
2339         u32 tempval;
2340
2341         regs = priv->gfargrp[0].regs;
2342
2343         tempval = gfar_read(&regs->rctrl);
2344         /* If parse is no longer required, then disable parser */
2345         if (tempval & RCTRL_REQ_PARSER)
2346                 tempval |= RCTRL_PRSDEP_INIT;
2347         else
2348                 tempval &= ~RCTRL_PRSDEP_INIT;
2349         gfar_write(&regs->rctrl, tempval);
2350 }
2351
2352 /* Enables and disables VLAN insertion/extraction */
2353 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2354 {
2355         struct gfar_private *priv = netdev_priv(dev);
2356         struct gfar __iomem *regs = NULL;
2357         unsigned long flags;
2358         u32 tempval;
2359
2360         regs = priv->gfargrp[0].regs;
2361         local_irq_save(flags);
2362         lock_rx_qs(priv);
2363
2364         if (features & NETIF_F_HW_VLAN_TX) {
2365                 /* Enable VLAN tag insertion */
2366                 tempval = gfar_read(&regs->tctrl);
2367                 tempval |= TCTRL_VLINS;
2368                 gfar_write(&regs->tctrl, tempval);
2369         } else {
2370                 /* Disable VLAN tag insertion */
2371                 tempval = gfar_read(&regs->tctrl);
2372                 tempval &= ~TCTRL_VLINS;
2373                 gfar_write(&regs->tctrl, tempval);
2374         }
2375
2376         if (features & NETIF_F_HW_VLAN_RX) {
2377                 /* Enable VLAN tag extraction */
2378                 tempval = gfar_read(&regs->rctrl);
2379                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2380                 gfar_write(&regs->rctrl, tempval);
2381         } else {
2382                 /* Disable VLAN tag extraction */
2383                 tempval = gfar_read(&regs->rctrl);
2384                 tempval &= ~RCTRL_VLEX;
2385                 gfar_write(&regs->rctrl, tempval);
2386
2387                 gfar_check_rx_parser_mode(priv);
2388         }
2389
2390         gfar_change_mtu(dev, dev->mtu);
2391
2392         unlock_rx_qs(priv);
2393         local_irq_restore(flags);
2394 }
2395
2396 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2397 {
2398         int tempsize, tempval;
2399         struct gfar_private *priv = netdev_priv(dev);
2400         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2401         int oldsize = priv->rx_buffer_size;
2402         int frame_size = new_mtu + ETH_HLEN;
2403
2404         if (gfar_is_vlan_on(priv))
2405                 frame_size += VLAN_HLEN;
2406
2407         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2408                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2409                 return -EINVAL;
2410         }
2411
2412         if (gfar_uses_fcb(priv))
2413                 frame_size += GMAC_FCB_LEN;
2414
2415         frame_size += priv->padding;
2416
2417         tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2418                    INCREMENTAL_BUFFER_SIZE;
2419
2420         /* Only stop and start the controller if it isn't already
2421          * stopped, and we changed something
2422          */
2423         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2424                 stop_gfar(dev);
2425
2426         priv->rx_buffer_size = tempsize;
2427
2428         dev->mtu = new_mtu;
2429
2430         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2431         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2432
2433         /* If the mtu is larger than the max size for standard
2434          * ethernet frames (ie, a jumbo frame), then set maccfg2
2435          * to allow huge frames, and to check the length
2436          */
2437         tempval = gfar_read(&regs->maccfg2);
2438
2439         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2440             gfar_has_errata(priv, GFAR_ERRATA_74))
2441                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2442         else
2443                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2444
2445         gfar_write(&regs->maccfg2, tempval);
2446
2447         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2448                 startup_gfar(dev);
2449
2450         return 0;
2451 }
2452
2453 /* gfar_reset_task gets scheduled when a packet has not been
2454  * transmitted after a set amount of time.
2455  * For now, assume that clearing out all the structures, and
2456  * starting over will fix the problem.
2457  */
2458 static void gfar_reset_task(struct work_struct *work)
2459 {
2460         struct gfar_private *priv = container_of(work, struct gfar_private,
2461                                                  reset_task);
2462         struct net_device *dev = priv->ndev;
2463
2464         if (dev->flags & IFF_UP) {
2465                 netif_tx_stop_all_queues(dev);
2466                 stop_gfar(dev);
2467                 startup_gfar(dev);
2468                 netif_tx_start_all_queues(dev);
2469         }
2470
2471         netif_tx_schedule_all(dev);
2472 }
2473
2474 static void gfar_timeout(struct net_device *dev)
2475 {
2476         struct gfar_private *priv = netdev_priv(dev);
2477
2478         dev->stats.tx_errors++;
2479         schedule_work(&priv->reset_task);
2480 }
2481
2482 static void gfar_align_skb(struct sk_buff *skb)
2483 {
2484         /* We need the data buffer to be aligned properly.  We will reserve
2485          * as many bytes as needed to align the data properly
2486          */
2487         skb_reserve(skb, RXBUF_ALIGNMENT -
2488                     (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2489 }
2490
2491 /* Interrupt Handler for Transmit complete */
2492 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2493 {
2494         struct net_device *dev = tx_queue->dev;
2495         struct netdev_queue *txq;
2496         struct gfar_private *priv = netdev_priv(dev);
2497         struct gfar_priv_rx_q *rx_queue = NULL;
2498         struct txbd8 *bdp, *next = NULL;
2499         struct txbd8 *lbdp = NULL;
2500         struct txbd8 *base = tx_queue->tx_bd_base;
2501         struct sk_buff *skb;
2502         int skb_dirtytx;
2503         int tx_ring_size = tx_queue->tx_ring_size;
2504         int frags = 0, nr_txbds = 0;
2505         int i;
2506         int howmany = 0;
2507         int tqi = tx_queue->qindex;
2508         unsigned int bytes_sent = 0;
2509         u32 lstatus;
2510         size_t buflen;
2511
2512         rx_queue = priv->rx_queue[tqi];
2513         txq = netdev_get_tx_queue(dev, tqi);
2514         bdp = tx_queue->dirty_tx;
2515         skb_dirtytx = tx_queue->skb_dirtytx;
2516
2517         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2518                 unsigned long flags;
2519
2520                 frags = skb_shinfo(skb)->nr_frags;
2521
2522                 /* When time stamping, one additional TxBD must be freed.
2523                  * Also, we need to dma_unmap_single() the TxPAL.
2524                  */
2525                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2526                         nr_txbds = frags + 2;
2527                 else
2528                         nr_txbds = frags + 1;
2529
2530                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2531
2532                 lstatus = lbdp->lstatus;
2533
2534                 /* Only clean completed frames */
2535                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2536                     (lstatus & BD_LENGTH_MASK))
2537                         break;
2538
2539                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2540                         next = next_txbd(bdp, base, tx_ring_size);
2541                         buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2542                 } else
2543                         buflen = bdp->length;
2544
2545                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2546                                  buflen, DMA_TO_DEVICE);
2547
2548                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2549                         struct skb_shared_hwtstamps shhwtstamps;
2550                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2551
2552                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2553                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2554                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2555                         skb_tstamp_tx(skb, &shhwtstamps);
2556                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2557                         bdp = next;
2558                 }
2559
2560                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2561                 bdp = next_txbd(bdp, base, tx_ring_size);
2562
2563                 for (i = 0; i < frags; i++) {
2564                         dma_unmap_page(&priv->ofdev->dev, bdp->bufPtr,
2565                                        bdp->length, DMA_TO_DEVICE);
2566                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2567                         bdp = next_txbd(bdp, base, tx_ring_size);
2568                 }
2569
2570                 bytes_sent += skb->len;
2571
2572                 dev_kfree_skb_any(skb);
2573
2574                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2575
2576                 skb_dirtytx = (skb_dirtytx + 1) &
2577                               TX_RING_MOD_MASK(tx_ring_size);
2578
2579                 howmany++;
2580                 spin_lock_irqsave(&tx_queue->txlock, flags);
2581                 tx_queue->num_txbdfree += nr_txbds;
2582                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2583         }
2584
2585         /* If we freed a buffer, we can restart transmission, if necessary */
2586         if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2587                 netif_wake_subqueue(dev, tqi);
2588
2589         /* Update dirty indicators */
2590         tx_queue->skb_dirtytx = skb_dirtytx;
2591         tx_queue->dirty_tx = bdp;
2592
2593         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2594
2595         return howmany;
2596 }
2597
2598 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2599 {
2600         unsigned long flags;
2601
2602         spin_lock_irqsave(&gfargrp->grplock, flags);
2603         if (napi_schedule_prep(&gfargrp->napi)) {
2604                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2605                 __napi_schedule(&gfargrp->napi);
2606         } else {
2607                 /* Clear IEVENT, so interrupts aren't called again
2608                  * because of the packets that have already arrived.
2609                  */
2610                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2611         }
2612         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2613
2614 }
2615
2616 /* Interrupt Handler for Transmit complete */
2617 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2618 {
2619         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2620         return IRQ_HANDLED;
2621 }
2622
2623 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2624                            struct sk_buff *skb)
2625 {
2626         struct net_device *dev = rx_queue->dev;
2627         struct gfar_private *priv = netdev_priv(dev);
2628         dma_addr_t buf;
2629
2630         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2631                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2632         gfar_init_rxbdp(rx_queue, bdp, buf);
2633 }
2634
2635 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2636 {
2637         struct gfar_private *priv = netdev_priv(dev);
2638         struct sk_buff *skb;
2639
2640         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2641         if (!skb)
2642                 return NULL;
2643
2644         gfar_align_skb(skb);
2645
2646         return skb;
2647 }
2648
2649 struct sk_buff *gfar_new_skb(struct net_device *dev)
2650 {
2651         return gfar_alloc_skb(dev);
2652 }
2653
2654 static inline void count_errors(unsigned short status, struct net_device *dev)
2655 {
2656         struct gfar_private *priv = netdev_priv(dev);
2657         struct net_device_stats *stats = &dev->stats;
2658         struct gfar_extra_stats *estats = &priv->extra_stats;
2659
2660         /* If the packet was truncated, none of the other errors matter */
2661         if (status & RXBD_TRUNCATED) {
2662                 stats->rx_length_errors++;
2663
2664                 estats->rx_trunc++;
2665
2666                 return;
2667         }
2668         /* Count the errors, if there were any */
2669         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2670                 stats->rx_length_errors++;
2671
2672                 if (status & RXBD_LARGE)
2673                         estats->rx_large++;
2674                 else
2675                         estats->rx_short++;
2676         }
2677         if (status & RXBD_NONOCTET) {
2678                 stats->rx_frame_errors++;
2679                 estats->rx_nonoctet++;
2680         }
2681         if (status & RXBD_CRCERR) {
2682                 estats->rx_crcerr++;
2683                 stats->rx_crc_errors++;
2684         }
2685         if (status & RXBD_OVERRUN) {
2686                 estats->rx_overrun++;
2687                 stats->rx_crc_errors++;
2688         }
2689 }
2690
2691 irqreturn_t gfar_receive(int irq, void *grp_id)
2692 {
2693         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2694         return IRQ_HANDLED;
2695 }
2696
2697 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2698 {
2699         /* If valid headers were found, and valid sums
2700          * were verified, then we tell the kernel that no
2701          * checksumming is necessary.  Otherwise, it is [FIXME]
2702          */
2703         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2704                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2705         else
2706                 skb_checksum_none_assert(skb);
2707 }
2708
2709
2710 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2711 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2712                               int amount_pull, struct napi_struct *napi)
2713 {
2714         struct gfar_private *priv = netdev_priv(dev);
2715         struct rxfcb *fcb = NULL;
2716
2717         gro_result_t ret;
2718
2719         /* fcb is at the beginning if exists */
2720         fcb = (struct rxfcb *)skb->data;
2721
2722         /* Remove the FCB from the skb
2723          * Remove the padded bytes, if there are any
2724          */
2725         if (amount_pull) {
2726                 skb_record_rx_queue(skb, fcb->rq);
2727                 skb_pull(skb, amount_pull);
2728         }
2729
2730         /* Get receive timestamp from the skb */
2731         if (priv->hwts_rx_en) {
2732                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2733                 u64 *ns = (u64 *) skb->data;
2734
2735                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2736                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2737         }
2738
2739         if (priv->padding)
2740                 skb_pull(skb, priv->padding);
2741
2742         if (dev->features & NETIF_F_RXCSUM)
2743                 gfar_rx_checksum(skb, fcb);
2744
2745         /* Tell the skb what kind of packet this is */
2746         skb->protocol = eth_type_trans(skb, dev);
2747
2748         /* There's need to check for NETIF_F_HW_VLAN_RX here.
2749          * Even if vlan rx accel is disabled, on some chips
2750          * RXFCB_VLN is pseudo randomly set.
2751          */
2752         if (dev->features & NETIF_F_HW_VLAN_RX &&
2753             fcb->flags & RXFCB_VLN)
2754                 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2755
2756         /* Send the packet up the stack */
2757         ret = napi_gro_receive(napi, skb);
2758
2759         if (GRO_DROP == ret)
2760                 priv->extra_stats.kernel_dropped++;
2761
2762         return 0;
2763 }
2764
2765 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2766  * until the budget/quota has been reached. Returns the number
2767  * of frames handled
2768  */
2769 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2770 {
2771         struct net_device *dev = rx_queue->dev;
2772         struct rxbd8 *bdp, *base;
2773         struct sk_buff *skb;
2774         int pkt_len;
2775         int amount_pull;
2776         int howmany = 0;
2777         struct gfar_private *priv = netdev_priv(dev);
2778
2779         /* Get the first full descriptor */
2780         bdp = rx_queue->cur_rx;
2781         base = rx_queue->rx_bd_base;
2782
2783         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2784
2785         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2786                 struct sk_buff *newskb;
2787
2788                 rmb();
2789
2790                 /* Add another skb for the future */
2791                 newskb = gfar_new_skb(dev);
2792
2793                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2794
2795                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2796                                  priv->rx_buffer_size, DMA_FROM_DEVICE);
2797
2798                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2799                              bdp->length > priv->rx_buffer_size))
2800                         bdp->status = RXBD_LARGE;
2801
2802                 /* We drop the frame if we failed to allocate a new buffer */
2803                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2804                              bdp->status & RXBD_ERR)) {
2805                         count_errors(bdp->status, dev);
2806
2807                         if (unlikely(!newskb))
2808                                 newskb = skb;
2809                         else if (skb)
2810                                 dev_kfree_skb(skb);
2811                 } else {
2812                         /* Increment the number of packets */
2813                         rx_queue->stats.rx_packets++;
2814                         howmany++;
2815
2816                         if (likely(skb)) {
2817                                 pkt_len = bdp->length - ETH_FCS_LEN;
2818                                 /* Remove the FCS from the packet length */
2819                                 skb_put(skb, pkt_len);
2820                                 rx_queue->stats.rx_bytes += pkt_len;
2821                                 skb_record_rx_queue(skb, rx_queue->qindex);
2822                                 gfar_process_frame(dev, skb, amount_pull,
2823                                                    &rx_queue->grp->napi);
2824
2825                         } else {
2826                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2827                                 rx_queue->stats.rx_dropped++;
2828                                 priv->extra_stats.rx_skbmissing++;
2829                         }
2830
2831                 }
2832
2833                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2834
2835                 /* Setup the new bdp */
2836                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2837
2838                 /* Update to the next pointer */
2839                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2840
2841                 /* update to point at the next skb */
2842                 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2843                                       RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2844         }
2845
2846         /* Update the current rxbd pointer to be the next one */
2847         rx_queue->cur_rx = bdp;
2848
2849         return howmany;
2850 }
2851
2852 static int gfar_poll(struct napi_struct *napi, int budget)
2853 {
2854         struct gfar_priv_grp *gfargrp =
2855                 container_of(napi, struct gfar_priv_grp, napi);
2856         struct gfar_private *priv = gfargrp->priv;
2857         struct gfar __iomem *regs = gfargrp->regs;
2858         struct gfar_priv_tx_q *tx_queue = NULL;
2859         struct gfar_priv_rx_q *rx_queue = NULL;
2860         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2861         int tx_cleaned = 0, i, left_over_budget = budget;
2862         unsigned long serviced_queues = 0;
2863         int num_queues = 0;
2864
2865         num_queues = gfargrp->num_rx_queues;
2866         budget_per_queue = budget/num_queues;
2867
2868         /* Clear IEVENT, so interrupts aren't called again
2869          * because of the packets that have already arrived
2870          */
2871         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2872
2873         while (num_queues && left_over_budget) {
2874                 budget_per_queue = left_over_budget/num_queues;
2875                 left_over_budget = 0;
2876
2877                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2878                         if (test_bit(i, &serviced_queues))
2879                                 continue;
2880                         rx_queue = priv->rx_queue[i];
2881                         tx_queue = priv->tx_queue[rx_queue->qindex];
2882
2883                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2884                         rx_cleaned_per_queue =
2885                                 gfar_clean_rx_ring(rx_queue, budget_per_queue);
2886                         rx_cleaned += rx_cleaned_per_queue;
2887                         if (rx_cleaned_per_queue < budget_per_queue) {
2888                                 left_over_budget = left_over_budget +
2889                                         (budget_per_queue -
2890                                          rx_cleaned_per_queue);
2891                                 set_bit(i, &serviced_queues);
2892                                 num_queues--;
2893                         }
2894                 }
2895         }
2896
2897         if (tx_cleaned)
2898                 return budget;
2899
2900         if (rx_cleaned < budget) {
2901                 napi_complete(napi);
2902
2903                 /* Clear the halt bit in RSTAT */
2904                 gfar_write(&regs->rstat, gfargrp->rstat);
2905
2906                 gfar_write(&regs->imask, IMASK_DEFAULT);
2907
2908                 /* If we are coalescing interrupts, update the timer
2909                  * Otherwise, clear it
2910                  */
2911                 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2912                                           gfargrp->tx_bit_map);
2913         }
2914
2915         return rx_cleaned;
2916 }
2917
2918 #ifdef CONFIG_NET_POLL_CONTROLLER
2919 /* Polling 'interrupt' - used by things like netconsole to send skbs
2920  * without having to re-enable interrupts. It's not called while
2921  * the interrupt routine is executing.
2922  */
2923 static void gfar_netpoll(struct net_device *dev)
2924 {
2925         struct gfar_private *priv = netdev_priv(dev);
2926         int i;
2927
2928         /* If the device has multiple interrupts, run tx/rx */
2929         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2930                 for (i = 0; i < priv->num_grps; i++) {
2931                         disable_irq(priv->gfargrp[i].interruptTransmit);
2932                         disable_irq(priv->gfargrp[i].interruptReceive);
2933                         disable_irq(priv->gfargrp[i].interruptError);
2934                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2935                                        &priv->gfargrp[i]);
2936                         enable_irq(priv->gfargrp[i].interruptError);
2937                         enable_irq(priv->gfargrp[i].interruptReceive);
2938                         enable_irq(priv->gfargrp[i].interruptTransmit);
2939                 }
2940         } else {
2941                 for (i = 0; i < priv->num_grps; i++) {
2942                         disable_irq(priv->gfargrp[i].interruptTransmit);
2943                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2944                                        &priv->gfargrp[i]);
2945                         enable_irq(priv->gfargrp[i].interruptTransmit);
2946                 }
2947         }
2948 }
2949 #endif
2950
2951 /* The interrupt handler for devices with one interrupt */
2952 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2953 {
2954         struct gfar_priv_grp *gfargrp = grp_id;
2955
2956         /* Save ievent for future reference */
2957         u32 events = gfar_read(&gfargrp->regs->ievent);
2958
2959         /* Check for reception */
2960         if (events & IEVENT_RX_MASK)
2961                 gfar_receive(irq, grp_id);
2962
2963         /* Check for transmit completion */
2964         if (events & IEVENT_TX_MASK)
2965                 gfar_transmit(irq, grp_id);
2966
2967         /* Check for errors */
2968         if (events & IEVENT_ERR_MASK)
2969                 gfar_error(irq, grp_id);
2970
2971         return IRQ_HANDLED;
2972 }
2973
2974 /* Called every time the controller might need to be made
2975  * aware of new link state.  The PHY code conveys this
2976  * information through variables in the phydev structure, and this
2977  * function converts those variables into the appropriate
2978  * register values, and can bring down the device if needed.
2979  */
2980 static void adjust_link(struct net_device *dev)
2981 {
2982         struct gfar_private *priv = netdev_priv(dev);
2983         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2984         unsigned long flags;
2985         struct phy_device *phydev = priv->phydev;
2986         int new_state = 0;
2987
2988         local_irq_save(flags);
2989         lock_tx_qs(priv);
2990
2991         if (phydev->link) {
2992                 u32 tempval = gfar_read(&regs->maccfg2);
2993                 u32 ecntrl = gfar_read(&regs->ecntrl);
2994
2995                 /* Now we make sure that we can be in full duplex mode.
2996                  * If not, we operate in half-duplex mode.
2997                  */
2998                 if (phydev->duplex != priv->oldduplex) {
2999                         new_state = 1;
3000                         if (!(phydev->duplex))
3001                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3002                         else
3003                                 tempval |= MACCFG2_FULL_DUPLEX;
3004
3005                         priv->oldduplex = phydev->duplex;
3006                 }
3007
3008                 if (phydev->speed != priv->oldspeed) {
3009                         new_state = 1;
3010                         switch (phydev->speed) {
3011                         case 1000:
3012                                 tempval =
3013                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3014
3015                                 ecntrl &= ~(ECNTRL_R100);
3016                                 break;
3017                         case 100:
3018                         case 10:
3019                                 tempval =
3020                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3021
3022                                 /* Reduced mode distinguishes
3023                                  * between 10 and 100
3024                                  */
3025                                 if (phydev->speed == SPEED_100)
3026                                         ecntrl |= ECNTRL_R100;
3027                                 else
3028                                         ecntrl &= ~(ECNTRL_R100);
3029                                 break;
3030                         default:
3031                                 netif_warn(priv, link, dev,
3032                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3033                                            phydev->speed);
3034                                 break;
3035                         }
3036
3037                         priv->oldspeed = phydev->speed;
3038                 }
3039
3040                 gfar_write(&regs->maccfg2, tempval);
3041                 gfar_write(&regs->ecntrl, ecntrl);
3042
3043                 if (!priv->oldlink) {
3044                         new_state = 1;
3045                         priv->oldlink = 1;
3046                 }
3047         } else if (priv->oldlink) {
3048                 new_state = 1;
3049                 priv->oldlink = 0;
3050                 priv->oldspeed = 0;
3051                 priv->oldduplex = -1;
3052         }
3053
3054         if (new_state && netif_msg_link(priv))
3055                 phy_print_status(phydev);
3056         unlock_tx_qs(priv);
3057         local_irq_restore(flags);
3058 }
3059
3060 /* Update the hash table based on the current list of multicast
3061  * addresses we subscribe to.  Also, change the promiscuity of
3062  * the device based on the flags (this function is called
3063  * whenever dev->flags is changed
3064  */
3065 static void gfar_set_multi(struct net_device *dev)
3066 {
3067         struct netdev_hw_addr *ha;
3068         struct gfar_private *priv = netdev_priv(dev);
3069         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3070         u32 tempval;
3071
3072         if (dev->flags & IFF_PROMISC) {
3073                 /* Set RCTRL to PROM */
3074                 tempval = gfar_read(&regs->rctrl);
3075                 tempval |= RCTRL_PROM;
3076                 gfar_write(&regs->rctrl, tempval);
3077         } else {
3078                 /* Set RCTRL to not PROM */
3079                 tempval = gfar_read(&regs->rctrl);
3080                 tempval &= ~(RCTRL_PROM);
3081                 gfar_write(&regs->rctrl, tempval);
3082         }
3083
3084         if (dev->flags & IFF_ALLMULTI) {
3085                 /* Set the hash to rx all multicast frames */
3086                 gfar_write(&regs->igaddr0, 0xffffffff);
3087                 gfar_write(&regs->igaddr1, 0xffffffff);
3088                 gfar_write(&regs->igaddr2, 0xffffffff);
3089                 gfar_write(&regs->igaddr3, 0xffffffff);
3090                 gfar_write(&regs->igaddr4, 0xffffffff);
3091                 gfar_write(&regs->igaddr5, 0xffffffff);
3092                 gfar_write(&regs->igaddr6, 0xffffffff);
3093                 gfar_write(&regs->igaddr7, 0xffffffff);
3094                 gfar_write(&regs->gaddr0, 0xffffffff);
3095                 gfar_write(&regs->gaddr1, 0xffffffff);
3096                 gfar_write(&regs->gaddr2, 0xffffffff);
3097                 gfar_write(&regs->gaddr3, 0xffffffff);
3098                 gfar_write(&regs->gaddr4, 0xffffffff);
3099                 gfar_write(&regs->gaddr5, 0xffffffff);
3100                 gfar_write(&regs->gaddr6, 0xffffffff);
3101                 gfar_write(&regs->gaddr7, 0xffffffff);
3102         } else {
3103                 int em_num;
3104                 int idx;
3105
3106                 /* zero out the hash */
3107                 gfar_write(&regs->igaddr0, 0x0);
3108                 gfar_write(&regs->igaddr1, 0x0);
3109                 gfar_write(&regs->igaddr2, 0x0);
3110                 gfar_write(&regs->igaddr3, 0x0);
3111                 gfar_write(&regs->igaddr4, 0x0);
3112                 gfar_write(&regs->igaddr5, 0x0);
3113                 gfar_write(&regs->igaddr6, 0x0);
3114                 gfar_write(&regs->igaddr7, 0x0);
3115                 gfar_write(&regs->gaddr0, 0x0);
3116                 gfar_write(&regs->gaddr1, 0x0);
3117                 gfar_write(&regs->gaddr2, 0x0);
3118                 gfar_write(&regs->gaddr3, 0x0);
3119                 gfar_write(&regs->gaddr4, 0x0);
3120                 gfar_write(&regs->gaddr5, 0x0);
3121                 gfar_write(&regs->gaddr6, 0x0);
3122                 gfar_write(&regs->gaddr7, 0x0);
3123
3124                 /* If we have extended hash tables, we need to
3125                  * clear the exact match registers to prepare for
3126                  * setting them
3127                  */
3128                 if (priv->extended_hash) {
3129                         em_num = GFAR_EM_NUM + 1;
3130                         gfar_clear_exact_match(dev);
3131                         idx = 1;
3132                 } else {
3133                         idx = 0;
3134                         em_num = 0;
3135                 }
3136
3137                 if (netdev_mc_empty(dev))
3138                         return;
3139
3140                 /* Parse the list, and set the appropriate bits */
3141                 netdev_for_each_mc_addr(ha, dev) {
3142                         if (idx < em_num) {
3143                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3144                                 idx++;
3145                         } else
3146                                 gfar_set_hash_for_addr(dev, ha->addr);
3147                 }
3148         }
3149 }
3150
3151
3152 /* Clears each of the exact match registers to zero, so they
3153  * don't interfere with normal reception
3154  */
3155 static void gfar_clear_exact_match(struct net_device *dev)
3156 {
3157         int idx;
3158         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3159
3160         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3161                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3162 }
3163
3164 /* Set the appropriate hash bit for the given addr */
3165 /* The algorithm works like so:
3166  * 1) Take the Destination Address (ie the multicast address), and
3167  * do a CRC on it (little endian), and reverse the bits of the
3168  * result.
3169  * 2) Use the 8 most significant bits as a hash into a 256-entry
3170  * table.  The table is controlled through 8 32-bit registers:
3171  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3172  * gaddr7.  This means that the 3 most significant bits in the
3173  * hash index which gaddr register to use, and the 5 other bits
3174  * indicate which bit (assuming an IBM numbering scheme, which
3175  * for PowerPC (tm) is usually the case) in the register holds
3176  * the entry.
3177  */
3178 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3179 {
3180         u32 tempval;
3181         struct gfar_private *priv = netdev_priv(dev);
3182         u32 result = ether_crc(ETH_ALEN, addr);
3183         int width = priv->hash_width;
3184         u8 whichbit = (result >> (32 - width)) & 0x1f;
3185         u8 whichreg = result >> (32 - width + 5);
3186         u32 value = (1 << (31-whichbit));
3187
3188         tempval = gfar_read(priv->hash_regs[whichreg]);
3189         tempval |= value;
3190         gfar_write(priv->hash_regs[whichreg], tempval);
3191 }
3192
3193
3194 /* There are multiple MAC Address register pairs on some controllers
3195  * This function sets the numth pair to a given address
3196  */
3197 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3198                                   const u8 *addr)
3199 {
3200         struct gfar_private *priv = netdev_priv(dev);
3201         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3202         int idx;
3203         char tmpbuf[ETH_ALEN];
3204         u32 tempval;
3205         u32 __iomem *macptr = &regs->macstnaddr1;
3206
3207         macptr += num*2;
3208
3209         /* Now copy it into the mac registers backwards, cuz
3210          * little endian is silly
3211          */
3212         for (idx = 0; idx < ETH_ALEN; idx++)
3213                 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3214
3215         gfar_write(macptr, *((u32 *) (tmpbuf)));
3216
3217         tempval = *((u32 *) (tmpbuf + 4));
3218
3219         gfar_write(macptr+1, tempval);
3220 }
3221
3222 /* GFAR error interrupt handler */
3223 static irqreturn_t gfar_error(int irq, void *grp_id)
3224 {
3225         struct gfar_priv_grp *gfargrp = grp_id;
3226         struct gfar __iomem *regs = gfargrp->regs;
3227         struct gfar_private *priv= gfargrp->priv;
3228         struct net_device *dev = priv->ndev;
3229
3230         /* Save ievent for future reference */
3231         u32 events = gfar_read(&regs->ievent);
3232
3233         /* Clear IEVENT */
3234         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3235
3236         /* Magic Packet is not an error. */
3237         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3238             (events & IEVENT_MAG))
3239                 events &= ~IEVENT_MAG;
3240
3241         /* Hmm... */
3242         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3243                 netdev_dbg(dev,
3244                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3245                            events, gfar_read(&regs->imask));
3246
3247         /* Update the error counters */
3248         if (events & IEVENT_TXE) {
3249                 dev->stats.tx_errors++;
3250
3251                 if (events & IEVENT_LC)
3252                         dev->stats.tx_window_errors++;
3253                 if (events & IEVENT_CRL)
3254                         dev->stats.tx_aborted_errors++;
3255                 if (events & IEVENT_XFUN) {
3256                         unsigned long flags;
3257
3258                         netif_dbg(priv, tx_err, dev,
3259                                   "TX FIFO underrun, packet dropped\n");
3260                         dev->stats.tx_dropped++;
3261                         priv->extra_stats.tx_underrun++;
3262
3263                         local_irq_save(flags);
3264                         lock_tx_qs(priv);
3265
3266                         /* Reactivate the Tx Queues */
3267                         gfar_write(&regs->tstat, gfargrp->tstat);
3268
3269                         unlock_tx_qs(priv);
3270                         local_irq_restore(flags);
3271                 }
3272                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3273         }
3274         if (events & IEVENT_BSY) {
3275                 dev->stats.rx_errors++;
3276                 priv->extra_stats.rx_bsy++;
3277
3278                 gfar_receive(irq, grp_id);
3279
3280                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3281                           gfar_read(&regs->rstat));
3282         }
3283         if (events & IEVENT_BABR) {
3284                 dev->stats.rx_errors++;
3285                 priv->extra_stats.rx_babr++;
3286
3287                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3288         }
3289         if (events & IEVENT_EBERR) {
3290                 priv->extra_stats.eberr++;
3291                 netif_dbg(priv, rx_err, dev, "bus error\n");
3292         }
3293         if (events & IEVENT_RXC)
3294                 netif_dbg(priv, rx_status, dev, "control frame\n");
3295
3296         if (events & IEVENT_BABT) {
3297                 priv->extra_stats.tx_babt++;
3298                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3299         }
3300         return IRQ_HANDLED;
3301 }
3302
3303 static struct of_device_id gfar_match[] =
3304 {
3305         {
3306                 .type = "network",
3307                 .compatible = "gianfar",
3308         },
3309         {
3310                 .compatible = "fsl,etsec2",
3311         },
3312         {},
3313 };
3314 MODULE_DEVICE_TABLE(of, gfar_match);
3315
3316 /* Structure for a device driver */
3317 static struct platform_driver gfar_driver = {
3318         .driver = {
3319                 .name = "fsl-gianfar",
3320                 .owner = THIS_MODULE,
3321                 .pm = GFAR_PM_OPS,
3322                 .of_match_table = gfar_match,
3323         },
3324         .probe = gfar_probe,
3325         .remove = gfar_remove,
3326 };
3327
3328 module_platform_driver(gfar_driver);