2 * QorIQ 10G MDIO Controller
4 * Copyright 2012 Freescale Semiconductor, Inc.
6 * Authors: Andy Fleming <afleming@freescale.com>
7 * Timur Tabi <timur@freescale.com>
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/phy.h>
19 #include <linux/mdio.h>
20 #include <linux/of_address.h>
21 #include <linux/of_platform.h>
22 #include <linux/of_mdio.h>
24 /* Number of microseconds to wait for a register to respond */
27 struct tgec_mdio_controller {
29 __be32 mdio_stat; /* MDIO configuration and status */
30 __be32 mdio_ctl; /* MDIO control */
31 __be32 mdio_data; /* MDIO data */
32 __be32 mdio_addr; /* MDIO address */
35 #define MDIO_STAT_ENC BIT(6)
36 #define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
37 #define MDIO_STAT_BSY BIT(0)
38 #define MDIO_STAT_RD_ER BIT(1)
39 #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
40 #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
41 #define MDIO_CTL_PRE_DIS BIT(10)
42 #define MDIO_CTL_SCAN_EN BIT(11)
43 #define MDIO_CTL_POST_INC BIT(14)
44 #define MDIO_CTL_READ BIT(15)
46 #define MDIO_DATA(x) (x & 0xffff)
47 #define MDIO_DATA_BSY BIT(31)
50 * Wait until the MDIO bus is free
52 static int xgmac_wait_until_free(struct device *dev,
53 struct tgec_mdio_controller __iomem *regs)
57 /* Wait till the bus is free */
59 while ((ioread32be(®s->mdio_stat) & MDIO_STAT_BSY) && timeout) {
65 dev_err(dev, "timeout waiting for bus to be free\n");
73 * Wait till the MDIO read or write operation is complete
75 static int xgmac_wait_until_done(struct device *dev,
76 struct tgec_mdio_controller __iomem *regs)
80 /* Wait till the MDIO write is complete */
82 while ((ioread32be(®s->mdio_data) & MDIO_DATA_BSY) && timeout) {
88 dev_err(dev, "timeout waiting for operation to complete\n");
96 * Write value to the PHY for this device to the register at regnum,waiting
97 * until the write is done before it returns. All PHY configuration has to be
98 * done through the TSEC1 MIIM regs.
100 static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)
102 struct tgec_mdio_controller __iomem *regs = bus->priv;
104 u32 mdio_ctl, mdio_stat;
107 mdio_stat = ioread32be(®s->mdio_stat);
108 if (regnum & MII_ADDR_C45) {
109 /* Clause 45 (ie 10G) */
110 dev_addr = (regnum >> 16) & 0x1f;
111 mdio_stat |= MDIO_STAT_ENC;
113 /* Clause 22 (ie 1G) */
114 dev_addr = regnum & 0x1f;
115 mdio_stat &= ~MDIO_STAT_ENC;
118 iowrite32be(mdio_stat, ®s->mdio_stat);
120 ret = xgmac_wait_until_free(&bus->dev, regs);
124 /* Set the port and dev addr */
125 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
126 iowrite32be(mdio_ctl, ®s->mdio_ctl);
128 /* Set the register address */
129 if (regnum & MII_ADDR_C45) {
130 iowrite32be(regnum & 0xffff, ®s->mdio_addr);
132 ret = xgmac_wait_until_free(&bus->dev, regs);
137 /* Write the value to the register */
138 iowrite32be(MDIO_DATA(value), ®s->mdio_data);
140 ret = xgmac_wait_until_done(&bus->dev, regs);
148 * Reads from register regnum in the PHY for device dev, returning the value.
149 * Clears miimcom first. All PHY configuration has to be done through the
152 static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
154 struct tgec_mdio_controller __iomem *regs = bus->priv;
161 mdio_stat = ioread32be(®s->mdio_stat);
162 if (regnum & MII_ADDR_C45) {
163 dev_addr = (regnum >> 16) & 0x1f;
164 mdio_stat |= MDIO_STAT_ENC;
166 dev_addr = regnum & 0x1f;
167 mdio_stat &= ~MDIO_STAT_ENC;
170 iowrite32be(mdio_stat, ®s->mdio_stat);
172 ret = xgmac_wait_until_free(&bus->dev, regs);
176 /* Set the Port and Device Addrs */
177 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
178 iowrite32be(mdio_ctl, ®s->mdio_ctl);
180 /* Set the register address */
181 if (regnum & MII_ADDR_C45) {
182 iowrite32be(regnum & 0xffff, ®s->mdio_addr);
184 ret = xgmac_wait_until_free(&bus->dev, regs);
189 /* Initiate the read */
190 iowrite32be(mdio_ctl | MDIO_CTL_READ, ®s->mdio_ctl);
192 ret = xgmac_wait_until_done(&bus->dev, regs);
196 /* Return all Fs if nothing was there */
197 if (ioread32be(®s->mdio_stat) & MDIO_STAT_RD_ER) {
199 "Error while reading PHY%d reg at %d.%hhu\n",
200 phy_id, dev_addr, regnum);
204 value = ioread32be(®s->mdio_data) & 0xffff;
205 dev_dbg(&bus->dev, "read %04x\n", value);
210 static int xgmac_mdio_probe(struct platform_device *pdev)
212 struct device_node *np = pdev->dev.of_node;
217 ret = of_address_to_resource(np, 0, &res);
219 dev_err(&pdev->dev, "could not obtain address\n");
223 bus = mdiobus_alloc();
227 bus->name = "Freescale XGMAC MDIO Bus";
228 bus->read = xgmac_mdio_read;
229 bus->write = xgmac_mdio_write;
230 bus->parent = &pdev->dev;
231 snprintf(bus->id, MII_BUS_ID_SIZE, "%llx", (unsigned long long)res.start);
233 /* Set the PHY base address */
234 bus->priv = of_iomap(np, 0);
240 ret = of_mdiobus_register(bus, np);
242 dev_err(&pdev->dev, "cannot register MDIO bus\n");
243 goto err_registration;
246 platform_set_drvdata(pdev, bus);
259 static int xgmac_mdio_remove(struct platform_device *pdev)
261 struct mii_bus *bus = platform_get_drvdata(pdev);
263 mdiobus_unregister(bus);
270 static struct of_device_id xgmac_mdio_match[] = {
272 .compatible = "fsl,fman-xmdio",
275 .compatible = "fsl,fman-memac-mdio",
279 MODULE_DEVICE_TABLE(of, xgmac_mdio_match);
281 static struct platform_driver xgmac_mdio_driver = {
283 .name = "fsl-fman_xmdio",
284 .of_match_table = xgmac_mdio_match,
286 .probe = xgmac_mdio_probe,
287 .remove = xgmac_mdio_remove,
290 module_platform_driver(xgmac_mdio_driver);
292 MODULE_DESCRIPTION("Freescale QorIQ 10G MDIO Controller");
293 MODULE_LICENSE("GPL v2");