drivers/net/ethernet/intel/e1000e/80003es2lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
  30  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  31  */
  32
  33 #include "e1000.h"
  34
  35 /* A table for the GG82563 cable length where the range is defined
  36  * with a lower bound at "index" and the upper bound at
  37  * "index + 5".
  38  */
  39 static const u16 e1000_gg82563_cable_length_table[] = {
  40          0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
  41 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
  42                 ARRAY_SIZE(e1000_gg82563_cable_length_table)
  43
  44 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
  45 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  46 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  47 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
  48 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
  49 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
  50 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
  51 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  52                                            u16 *data);
  53 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  54                                             u16 data);
  55 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
  56
  57 /**
  58  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
  59  *  @hw: pointer to the HW structure
  60  **/
  61 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
  62 {
  63         struct e1000_phy_info *phy = &hw->phy;
  64         s32 ret_val;
  65
  66         if (hw->phy.media_type != e1000_media_type_copper) {
  67                 phy->type       = e1000_phy_none;
  68                 return 0;
  69         } else {
  70                 phy->ops.power_up = e1000_power_up_phy_copper;
  71                 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
  72         }
  73
  74         phy->addr               = 1;
  75         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  76         phy->reset_delay_us      = 100;
  77         phy->type               = e1000_phy_gg82563;
  78
  79         /* This can only be done after all function pointers are setup. */
  80         ret_val = e1000e_get_phy_id(hw);
  81
  82         /* Verify phy id */
  83         if (phy->id != GG82563_E_PHY_ID)
  84                 return -E1000_ERR_PHY;
  85
  86         return ret_val;
  87 }
  88
  89 /**
  90  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
  91  *  @hw: pointer to the HW structure
  92  **/
  93 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
  94 {
  95         struct e1000_nvm_info *nvm = &hw->nvm;
  96         u32 eecd = er32(EECD);
  97         u16 size;
  98
  99         nvm->opcode_bits        = 8;
 100         nvm->delay_usec  = 1;
 101         switch (nvm->override) {
 102         case e1000_nvm_override_spi_large:
 103                 nvm->page_size    = 32;
 104                 nvm->address_bits = 16;
 105                 break;
 106         case e1000_nvm_override_spi_small:
 107                 nvm->page_size    = 8;
 108                 nvm->address_bits = 8;
 109                 break;
 110         default:
 111                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 112                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 113                 break;
 114         }
 115
 116         nvm->type = e1000_nvm_eeprom_spi;
 117
 118         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 119                      E1000_EECD_SIZE_EX_SHIFT);
 120
 121         /* Added to a constant, "size" becomes the left-shift value
 122          * for setting word_size.
 123          */
 124         size += NVM_WORD_SIZE_BASE_SHIFT;
 125
 126         /* EEPROM access above 16k is unsupported */
 127         if (size > 14)
 128                 size = 14;
 129         nvm->word_size  = 1 << size;
 130
 131         return 0;
 132 }
 133
 134 /**
 135  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 136  *  @hw: pointer to the HW structure
 137  **/
 138 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
 139 {
 140         struct e1000_mac_info *mac = &hw->mac;
 141
 142         /* Set media type and media-dependent function pointers */
 143         switch (hw->adapter->pdev->device) {
 144         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 145                 hw->phy.media_type = e1000_media_type_internal_serdes;
 146                 mac->ops.check_for_link = e1000e_check_for_serdes_link;
 147                 mac->ops.setup_physical_interface =
 148                     e1000e_setup_fiber_serdes_link;
 149                 break;
 150         default:
 151                 hw->phy.media_type = e1000_media_type_copper;
 152                 mac->ops.check_for_link = e1000e_check_for_copper_link;
 153                 mac->ops.setup_physical_interface =
 154                     e1000_setup_copper_link_80003es2lan;
 155                 break;
 156         }
 157
 158         /* Set mta register count */
 159         mac->mta_reg_count = 128;
 160         /* Set rar entry count */
 161         mac->rar_entry_count = E1000_RAR_ENTRIES;
 162         /* FWSM register */
 163         mac->has_fwsm = true;
 164         /* ARC supported; valid only if manageability features are enabled. */
 165         mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
 166         /* Adaptive IFS not supported */
 167         mac->adaptive_ifs = false;
 168
 169         /* set lan id for port to determine which phy lock to use */
 170         hw->mac.ops.set_lan_id(hw);
 171
 172         return 0;
 173 }
 174
 175 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
 176 {
 177         struct e1000_hw *hw = &adapter->hw;
 178         s32 rc;
 179
 180         rc = e1000_init_mac_params_80003es2lan(hw);
 181         if (rc)
 182                 return rc;
 183
 184         rc = e1000_init_nvm_params_80003es2lan(hw);
 185         if (rc)
 186                 return rc;
 187
 188         rc = e1000_init_phy_params_80003es2lan(hw);
 189         if (rc)
 190                 return rc;
 191
 192         return 0;
 193 }
 194
 195 /**
 196  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 197  *  @hw: pointer to the HW structure
 198  *
 199  *  A wrapper to acquire access rights to the correct PHY.
 200  **/
 201 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 202 {
 203         u16 mask;
 204
 205         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 206         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 207 }
 208
 209 /**
 210  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 211  *  @hw: pointer to the HW structure
 212  *
 213  *  A wrapper to release access rights to the correct PHY.
 214  **/
 215 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 216 {
 217         u16 mask;
 218
 219         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 220         e1000_release_swfw_sync_80003es2lan(hw, mask);
 221 }
 222
 223 /**
 224  *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
 225  *  @hw: pointer to the HW structure
 226  *
 227  *  Acquire the semaphore to access the Kumeran interface.
 228  *
 229  **/
 230 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 231 {
 232         u16 mask;
 233
 234         mask = E1000_SWFW_CSR_SM;
 235
 236         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 237 }
 238
 239 /**
 240  *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
 241  *  @hw: pointer to the HW structure
 242  *
 243  *  Release the semaphore used to access the Kumeran interface
 244  **/
 245 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 246 {
 247         u16 mask;
 248
 249         mask = E1000_SWFW_CSR_SM;
 250
 251         e1000_release_swfw_sync_80003es2lan(hw, mask);
 252 }
 253
 254 /**
 255  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 256  *  @hw: pointer to the HW structure
 257  *
 258  *  Acquire the semaphore to access the EEPROM.
 259  **/
 260 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 261 {
 262         s32 ret_val;
 263
 264         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 265         if (ret_val)
 266                 return ret_val;
 267
 268         ret_val = e1000e_acquire_nvm(hw);
 269
 270         if (ret_val)
 271                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 272
 273         return ret_val;
 274 }
 275
 276 /**
 277  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 278  *  @hw: pointer to the HW structure
 279  *
 280  *  Release the semaphore used to access the EEPROM.
 281  **/
 282 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 283 {
 284         e1000e_release_nvm(hw);
 285         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 286 }
 287
 288 /**
 289  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 290  *  @hw: pointer to the HW structure
 291  *  @mask: specifies which semaphore to acquire
 292  *
 293  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 294  *  will also specify which port we're acquiring the lock for.
 295  **/
 296 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 297 {
 298         u32 swfw_sync;
 299         u32 swmask = mask;
 300         u32 fwmask = mask << 16;
 301         s32 i = 0;
 302         s32 timeout = 50;
 303
 304         while (i < timeout) {
 305                 if (e1000e_get_hw_semaphore(hw))
 306                         return -E1000_ERR_SWFW_SYNC;
 307
 308                 swfw_sync = er32(SW_FW_SYNC);
 309                 if (!(swfw_sync & (fwmask | swmask)))
 310                         break;
 311
 312                 /* Firmware currently using resource (fwmask)
 313                  * or other software thread using resource (swmask)
 314                  */
 315                 e1000e_put_hw_semaphore(hw);
 316                 mdelay(5);
 317                 i++;
 318         }
 319
 320         if (i == timeout) {
 321                 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
 322                 return -E1000_ERR_SWFW_SYNC;
 323         }
 324
 325         swfw_sync |= swmask;
 326         ew32(SW_FW_SYNC, swfw_sync);
 327
 328         e1000e_put_hw_semaphore(hw);
 329
 330         return 0;
 331 }
 332
 333 /**
 334  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 335  *  @hw: pointer to the HW structure
 336  *  @mask: specifies which semaphore to acquire
 337  *
 338  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 339  *  will also specify which port we're releasing the lock for.
 340  **/
 341 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 342 {
 343         u32 swfw_sync;
 344
 345         while (e1000e_get_hw_semaphore(hw) != 0)
 346                 ; /* Empty */
 347
 348         swfw_sync = er32(SW_FW_SYNC);
 349         swfw_sync &= ~mask;
 350         ew32(SW_FW_SYNC, swfw_sync);
 351
 352         e1000e_put_hw_semaphore(hw);
 353 }
 354
 355 /**
 356  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 357  *  @hw: pointer to the HW structure
 358  *  @offset: offset of the register to read
 359  *  @data: pointer to the data returned from the operation
 360  *
 361  *  Read the GG82563 PHY register.
 362  **/
 363 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 364                                                   u32 offset, u16 *data)
 365 {
 366         s32 ret_val;
 367         u32 page_select;
 368         u16 temp;
 369
 370         ret_val = e1000_acquire_phy_80003es2lan(hw);
 371         if (ret_val)
 372                 return ret_val;
 373
 374         /* Select Configuration Page */
 375         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 376                 page_select = GG82563_PHY_PAGE_SELECT;
 377         } else {
 378                 /* Use Alternative Page Select register to access
 379                  * registers 30 and 31
 380                  */
 381                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 382         }
 383
 384         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 385         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 386         if (ret_val) {
 387                 e1000_release_phy_80003es2lan(hw);
 388                 return ret_val;
 389         }
 390
 391         if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
 392                 /* The "ready" bit in the MDIC register may be incorrectly set
 393                  * before the device has completed the "Page Select" MDI
 394                  * transaction.  So we wait 200us after each MDI command...
 395                  */
 396                 udelay(200);
 397
 398                 /* ...and verify the command was successful. */
 399                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 400
 401                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 402                         e1000_release_phy_80003es2lan(hw);
 403                         return -E1000_ERR_PHY;
 404                 }
 405
 406                 udelay(200);
 407
 408                 ret_val = e1000e_read_phy_reg_mdic(hw,
 409                                                    MAX_PHY_REG_ADDRESS & offset,
 410                                                    data);
 411
 412                 udelay(200);
 413         } else {
 414                 ret_val = e1000e_read_phy_reg_mdic(hw,
 415                                                    MAX_PHY_REG_ADDRESS & offset,
 416                                                    data);
 417         }
 418
 419         e1000_release_phy_80003es2lan(hw);
 420
 421         return ret_val;
 422 }
 423
 424 /**
 425  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 426  *  @hw: pointer to the HW structure
 427  *  @offset: offset of the register to read
 428  *  @data: value to write to the register
 429  *
 430  *  Write to the GG82563 PHY register.
 431  **/
 432 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 433                                                    u32 offset, u16 data)
 434 {
 435         s32 ret_val;
 436         u32 page_select;
 437         u16 temp;
 438
 439         ret_val = e1000_acquire_phy_80003es2lan(hw);
 440         if (ret_val)
 441                 return ret_val;
 442
 443         /* Select Configuration Page */
 444         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 445                 page_select = GG82563_PHY_PAGE_SELECT;
 446         } else {
 447                 /* Use Alternative Page Select register to access
 448                  * registers 30 and 31
 449                  */
 450                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 451         }
 452
 453         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 454         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 455         if (ret_val) {
 456                 e1000_release_phy_80003es2lan(hw);
 457                 return ret_val;
 458         }
 459
 460         if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
 461                 /* The "ready" bit in the MDIC register may be incorrectly set
 462                  * before the device has completed the "Page Select" MDI
 463                  * transaction.  So we wait 200us after each MDI command...
 464                  */
 465                 udelay(200);
 466
 467                 /* ...and verify the command was successful. */
 468                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 469
 470                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 471                         e1000_release_phy_80003es2lan(hw);
 472                         return -E1000_ERR_PHY;
 473                 }
 474
 475                 udelay(200);
 476
 477                 ret_val = e1000e_write_phy_reg_mdic(hw,
 478                                                     MAX_PHY_REG_ADDRESS &
 479                                                     offset, data);
 480
 481                 udelay(200);
 482         } else {
 483                 ret_val = e1000e_write_phy_reg_mdic(hw,
 484                                                     MAX_PHY_REG_ADDRESS &
 485                                                     offset, data);
 486         }
 487
 488         e1000_release_phy_80003es2lan(hw);
 489
 490         return ret_val;
 491 }
 492
 493 /**
 494  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 495  *  @hw: pointer to the HW structure
 496  *  @offset: offset of the register to read
 497  *  @words: number of words to write
 498  *  @data: buffer of data to write to the NVM
 499  *
 500  *  Write "words" of data to the ESB2 NVM.
 501  **/
 502 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 503                                        u16 words, u16 *data)
 504 {
 505         return e1000e_write_nvm_spi(hw, offset, words, data);
 506 }
 507
 508 /**
 509  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 510  *  @hw: pointer to the HW structure
 511  *
 512  *  Wait a specific amount of time for manageability processes to complete.
 513  *  This is a function pointer entry point called by the phy module.
 514  **/
 515 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 516 {
 517         s32 timeout = PHY_CFG_TIMEOUT;
 518         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 519
 520         if (hw->bus.func == 1)
 521                 mask = E1000_NVM_CFG_DONE_PORT_1;
 522
 523         while (timeout) {
 524                 if (er32(EEMNGCTL) & mask)
 525                         break;
 526                 usleep_range(1000, 2000);
 527                 timeout--;
 528         }
 529         if (!timeout) {
 530                 e_dbg("MNG configuration cycle has not completed.\n");
 531                 return -E1000_ERR_RESET;
 532         }
 533
 534         return 0;
 535 }
 536
 537 /**
 538  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 539  *  @hw: pointer to the HW structure
 540  *
 541  *  Force the speed and duplex settings onto the PHY.  This is a
 542  *  function pointer entry point called by the phy module.
 543  **/
 544 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 545 {
 546         s32 ret_val;
 547         u16 phy_data;
 548         bool link;
 549
 550         /* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 551          * forced whenever speed and duplex are forced.
 552          */
 553         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 554         if (ret_val)
 555                 return ret_val;
 556
 557         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 558         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 559         if (ret_val)
 560                 return ret_val;
 561
 562         e_dbg("GG82563 PSCR: %X\n", phy_data);
 563
 564         ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
 565         if (ret_val)
 566                 return ret_val;
 567
 568         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 569
 570         /* Reset the phy to commit changes. */
 571         phy_data |= BMCR_RESET;
 572
 573         ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
 574         if (ret_val)
 575                 return ret_val;
 576
 577         udelay(1);
 578
 579         if (hw->phy.autoneg_wait_to_complete) {
 580                 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
 581
 582                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 583                                                       100000, &link);
 584                 if (ret_val)
 585                         return ret_val;
 586
 587                 if (!link) {
 588                         /* We didn't get link.
 589                          * Reset the DSP and cross our fingers.
 590                          */
 591                         ret_val = e1000e_phy_reset_dsp(hw);
 592                         if (ret_val)
 593                                 return ret_val;
 594                 }
 595
 596                 /* Try once more */
 597                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 598                                                       100000, &link);
 599                 if (ret_val)
 600                         return ret_val;
 601         }
 602
 603         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 604         if (ret_val)
 605                 return ret_val;
 606
 607         /* Resetting the phy means we need to verify the TX_CLK corresponds
 608          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 609          */
 610         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 611         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 612                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 613         else
 614                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 615
 616         /* In addition, we must re-enable CRS on Tx for both half and full
 617          * duplex.
 618          */
 619         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 620         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 621
 622         return ret_val;
 623 }
 624
 625 /**
 626  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 627  *  @hw: pointer to the HW structure
 628  *
 629  *  Find the approximate cable length as measured by the GG82563 PHY.
 630  *  This is a function pointer entry point called by the phy module.
 631  **/
 632 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 633 {
 634         struct e1000_phy_info *phy = &hw->phy;
 635         s32 ret_val;
 636         u16 phy_data, index;
 637
 638         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 639         if (ret_val)
 640                 return ret_val;
 641
 642         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 643
 644         if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
 645                 return -E1000_ERR_PHY;
 646
 647         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 648         phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
 649
 650         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 651
 652         return 0;
 653 }
 654
 655 /**
 656  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 657  *  @hw: pointer to the HW structure
 658  *  @speed: pointer to speed buffer
 659  *  @duplex: pointer to duplex buffer
 660  *
 661  *  Retrieve the current speed and duplex configuration.
 662  **/
 663 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 664                                               u16 *duplex)
 665 {
 666         s32 ret_val;
 667
 668         if (hw->phy.media_type == e1000_media_type_copper) {
 669                 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
 670                 hw->phy.ops.cfg_on_link_up(hw);
 671         } else {
 672                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
 673                                                                    speed,
 674                                                                    duplex);
 675         }
 676
 677         return ret_val;
 678 }
 679
 680 /**
 681  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 682  *  @hw: pointer to the HW structure
 683  *
 684  *  Perform a global reset to the ESB2 controller.
 685  **/
 686 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 687 {
 688         u32 ctrl;
 689         s32 ret_val;
 690         u16 kum_reg_data;
 691
 692         /* Prevent the PCI-E bus from sticking if there is no TLP connection
 693          * on the last TLP read/write transaction when MAC is reset.
 694          */
 695         ret_val = e1000e_disable_pcie_master(hw);
 696         if (ret_val)
 697                 e_dbg("PCI-E Master disable polling has failed.\n");
 698
 699         e_dbg("Masking off all interrupts\n");
 700         ew32(IMC, 0xffffffff);
 701
 702         ew32(RCTL, 0);
 703         ew32(TCTL, E1000_TCTL_PSP);
 704         e1e_flush();
 705
 706         usleep_range(10000, 20000);
 707
 708         ctrl = er32(CTRL);
 709
 710         ret_val = e1000_acquire_phy_80003es2lan(hw);
 711         if (ret_val)
 712                 return ret_val;
 713
 714         e_dbg("Issuing a global reset to MAC\n");
 715         ew32(CTRL, ctrl | E1000_CTRL_RST);
 716         e1000_release_phy_80003es2lan(hw);
 717
 718         /* Disable IBIST slave mode (far-end loopback) */
 719         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 720                                         &kum_reg_data);
 721         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 722         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 723                                          kum_reg_data);
 724
 725         ret_val = e1000e_get_auto_rd_done(hw);
 726         if (ret_val)
 727                 /* We don't want to continue accessing MAC registers. */
 728                 return ret_val;
 729
 730         /* Clear any pending interrupt events. */
 731         ew32(IMC, 0xffffffff);
 732         er32(ICR);
 733
 734         return e1000_check_alt_mac_addr_generic(hw);
 735 }
 736
 737 /**
 738  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 739  *  @hw: pointer to the HW structure
 740  *
 741  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 742  **/
 743 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 744 {
 745         struct e1000_mac_info *mac = &hw->mac;
 746         u32 reg_data;
 747         s32 ret_val;
 748         u16 kum_reg_data;
 749         u16 i;
 750
 751         e1000_initialize_hw_bits_80003es2lan(hw);
 752
 753         /* Initialize identification LED */
 754         ret_val = mac->ops.id_led_init(hw);
 755         if (ret_val)
 756                 e_dbg("Error initializing identification LED\n");
 757                 /* This is not fatal and we should not stop init due to this */
 758
 759         /* Disabling VLAN filtering */
 760         e_dbg("Initializing the IEEE VLAN\n");
 761         mac->ops.clear_vfta(hw);
 762
 763         /* Setup the receive address. */
 764         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 765
 766         /* Zero out the Multicast HASH table */
 767         e_dbg("Zeroing the MTA\n");
 768         for (i = 0; i < mac->mta_reg_count; i++)
 769                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 770
 771         /* Setup link and flow control */
 772         ret_val = mac->ops.setup_link(hw);
 773         if (ret_val)
 774                 return ret_val;
 775
 776         /* Disable IBIST slave mode (far-end loopback) */
 777         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 778                                         &kum_reg_data);
 779         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 780         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 781                                          kum_reg_data);
 782
 783         /* Set the transmit descriptor write-back policy */
 784         reg_data = er32(TXDCTL(0));
 785         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
 786                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
 787         ew32(TXDCTL(0), reg_data);
 788
 789         /* ...for both queues. */
 790         reg_data = er32(TXDCTL(1));
 791         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
 792                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
 793         ew32(TXDCTL(1), reg_data);
 794
 795         /* Enable retransmit on late collisions */
 796         reg_data = er32(TCTL);
 797         reg_data |= E1000_TCTL_RTLC;
 798         ew32(TCTL, reg_data);
 799
 800         /* Configure Gigabit Carry Extend Padding */
 801         reg_data = er32(TCTL_EXT);
 802         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 803         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 804         ew32(TCTL_EXT, reg_data);
 805
 806         /* Configure Transmit Inter-Packet Gap */
 807         reg_data = er32(TIPG);
 808         reg_data &= ~E1000_TIPG_IPGT_MASK;
 809         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 810         ew32(TIPG, reg_data);
 811
 812         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 813         reg_data &= ~0x00100000;
 814         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 815
 816         /* default to true to enable the MDIC W/A */
 817         hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
 818
 819         ret_val =
 820             e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
 821                                             E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
 822         if (!ret_val) {
 823                 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
 824                     E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
 825                         hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
 826         }
 827
 828         /* Clear all of the statistics registers (clear on read).  It is
 829          * important that we do this after we have tried to establish link
 830          * because the symbol error count will increment wildly if there
 831          * is no link.
 832          */
 833         e1000_clear_hw_cntrs_80003es2lan(hw);
 834
 835         return ret_val;
 836 }
 837
 838 /**
 839  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 840  *  @hw: pointer to the HW structure
 841  *
 842  *  Initializes required hardware-dependent bits needed for normal operation.
 843  **/
 844 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 845 {
 846         u32 reg;
 847
 848         /* Transmit Descriptor Control 0 */
 849         reg = er32(TXDCTL(0));
 850         reg |= (1 << 22);
 851         ew32(TXDCTL(0), reg);
 852
 853         /* Transmit Descriptor Control 1 */
 854         reg = er32(TXDCTL(1));
 855         reg |= (1 << 22);
 856         ew32(TXDCTL(1), reg);
 857
 858         /* Transmit Arbitration Control 0 */
 859         reg = er32(TARC(0));
 860         reg &= ~(0xF << 27); /* 30:27 */
 861         if (hw->phy.media_type != e1000_media_type_copper)
 862                 reg &= ~(1 << 20);
 863         ew32(TARC(0), reg);
 864
 865         /* Transmit Arbitration Control 1 */
 866         reg = er32(TARC(1));
 867         if (er32(TCTL) & E1000_TCTL_MULR)
 868                 reg &= ~(1 << 28);
 869         else
 870                 reg |= (1 << 28);
 871         ew32(TARC(1), reg);
 872
 873         /* Disable IPv6 extension header parsing because some malformed
 874          * IPv6 headers can hang the Rx.
 875          */
 876         reg = er32(RFCTL);
 877         reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
 878         ew32(RFCTL, reg);
 879 }
 880
 881 /**
 882  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
 883  *  @hw: pointer to the HW structure
 884  *
 885  *  Setup some GG82563 PHY registers for obtaining link
 886  **/
 887 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 888 {
 889         struct e1000_phy_info *phy = &hw->phy;
 890         s32 ret_val;
 891         u32 reg;
 892         u16 data;
 893
 894         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
 895         if (ret_val)
 896                 return ret_val;
 897
 898         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 899         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 900         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 901
 902         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
 903         if (ret_val)
 904                 return ret_val;
 905
 906         /* Options:
 907          *   MDI/MDI-X = 0 (default)
 908          *   0 - Auto for all speeds
 909          *   1 - MDI mode
 910          *   2 - MDI-X mode
 911          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 912          */
 913         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
 914         if (ret_val)
 915                 return ret_val;
 916
 917         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 918
 919         switch (phy->mdix) {
 920         case 1:
 921                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 922                 break;
 923         case 2:
 924                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 925                 break;
 926         case 0:
 927         default:
 928                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
 929                 break;
 930         }
 931
 932         /* Options:
 933          *   disable_polarity_correction = 0 (default)
 934          *       Automatic Correction for Reversed Cable Polarity
 935          *   0 - Disabled
 936          *   1 - Enabled
 937          */
 938         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 939         if (phy->disable_polarity_correction)
 940                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 941
 942         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
 943         if (ret_val)
 944                 return ret_val;
 945
 946         /* SW Reset the PHY so all changes take effect */
 947         ret_val = hw->phy.ops.commit(hw);
 948         if (ret_val) {
 949                 e_dbg("Error Resetting the PHY\n");
 950                 return ret_val;
 951         }
 952
 953         /* Bypass Rx and Tx FIFO's */
 954         reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
 955         data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
 956                 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
 957         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
 958         if (ret_val)
 959                 return ret_val;
 960
 961         reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
 962         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
 963         if (ret_val)
 964                 return ret_val;
 965         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
 966         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
 967         if (ret_val)
 968                 return ret_val;
 969
 970         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
 971         if (ret_val)
 972                 return ret_val;
 973
 974         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
 975         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
 976         if (ret_val)
 977                 return ret_val;
 978
 979         reg = er32(CTRL_EXT);
 980         reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
 981         ew32(CTRL_EXT, reg);
 982
 983         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
 984         if (ret_val)
 985                 return ret_val;
 986
 987         /* Do not init these registers when the HW is in IAMT mode, since the
 988          * firmware will have already initialized them.  We only initialize
 989          * them if the HW is not in IAMT mode.
 990          */
 991         if (!hw->mac.ops.check_mng_mode(hw)) {
 992                 /* Enable Electrical Idle on the PHY */
 993                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
 994                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
 995                 if (ret_val)
 996                         return ret_val;
 997
 998                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
 999                 if (ret_val)
1000                         return ret_val;
1001
1002                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1003                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1004                 if (ret_val)
1005                         return ret_val;
1006         }
1007
1008         /* Workaround: Disable padding in Kumeran interface in the MAC
1009          * and in the PHY to avoid CRC errors.
1010          */
1011         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1012         if (ret_val)
1013                 return ret_val;
1014
1015         data |= GG82563_ICR_DIS_PADDING;
1016         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1017         if (ret_val)
1018                 return ret_val;
1019
1020         return 0;
1021 }
1022
1023 /**
1024  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1025  *  @hw: pointer to the HW structure
1026  *
1027  *  Essentially a wrapper for setting up all things "copper" related.
1028  *  This is a function pointer entry point called by the mac module.
1029  **/
1030 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1031 {
1032         u32 ctrl;
1033         s32 ret_val;
1034         u16 reg_data;
1035
1036         ctrl = er32(CTRL);
1037         ctrl |= E1000_CTRL_SLU;
1038         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1039         ew32(CTRL, ctrl);
1040
1041         /* Set the mac to wait the maximum time between each
1042          * iteration and increase the max iterations when
1043          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1044          */
1045         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1046                                                    0xFFFF);
1047         if (ret_val)
1048                 return ret_val;
1049         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1050                                                   &reg_data);
1051         if (ret_val)
1052                 return ret_val;
1053         reg_data |= 0x3F;
1054         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1055                                                    reg_data);
1056         if (ret_val)
1057                 return ret_val;
1058         ret_val =
1059             e1000_read_kmrn_reg_80003es2lan(hw,
1060                                             E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1061                                             &reg_data);
1062         if (ret_val)
1063                 return ret_val;
1064         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1065         ret_val =
1066             e1000_write_kmrn_reg_80003es2lan(hw,
1067                                              E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1068                                              reg_data);
1069         if (ret_val)
1070                 return ret_val;
1071
1072         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1073         if (ret_val)
1074                 return ret_val;
1075
1076         return e1000e_setup_copper_link(hw);
1077 }
1078
1079 /**
1080  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1081  *  @hw: pointer to the HW structure
1082  *  @duplex: current duplex setting
1083  *
1084  *  Configure the KMRN interface by applying last minute quirks for
1085  *  10/100 operation.
1086  **/
1087 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1088 {
1089         s32 ret_val = 0;
1090         u16 speed;
1091         u16 duplex;
1092
1093         if (hw->phy.media_type == e1000_media_type_copper) {
1094                 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1095                                                              &duplex);
1096                 if (ret_val)
1097                         return ret_val;
1098
1099                 if (speed == SPEED_1000)
1100                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1101                 else
1102                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1103         }
1104
1105         return ret_val;
1106 }
1107
1108 /**
1109  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1110  *  @hw: pointer to the HW structure
1111  *  @duplex: current duplex setting
1112  *
1113  *  Configure the KMRN interface by applying last minute quirks for
1114  *  10/100 operation.
1115  **/
1116 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1117 {
1118         s32 ret_val;
1119         u32 tipg;
1120         u32 i = 0;
1121         u16 reg_data, reg_data2;
1122
1123         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1124         ret_val =
1125             e1000_write_kmrn_reg_80003es2lan(hw,
1126                                              E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1127                                              reg_data);
1128         if (ret_val)
1129                 return ret_val;
1130
1131         /* Configure Transmit Inter-Packet Gap */
1132         tipg = er32(TIPG);
1133         tipg &= ~E1000_TIPG_IPGT_MASK;
1134         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1135         ew32(TIPG, tipg);
1136
1137         do {
1138                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1139                 if (ret_val)
1140                         return ret_val;
1141
1142                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1143                 if (ret_val)
1144                         return ret_val;
1145                 i++;
1146         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1147
1148         if (duplex == HALF_DUPLEX)
1149                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1150         else
1151                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1152
1153         return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1154 }
1155
1156 /**
1157  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1158  *  @hw: pointer to the HW structure
1159  *
1160  *  Configure the KMRN interface by applying last minute quirks for
1161  *  gigabit operation.
1162  **/
1163 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1164 {
1165         s32 ret_val;
1166         u16 reg_data, reg_data2;
1167         u32 tipg;
1168         u32 i = 0;
1169
1170         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1171         ret_val =
1172             e1000_write_kmrn_reg_80003es2lan(hw,
1173                                              E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1174                                              reg_data);
1175         if (ret_val)
1176                 return ret_val;
1177
1178         /* Configure Transmit Inter-Packet Gap */
1179         tipg = er32(TIPG);
1180         tipg &= ~E1000_TIPG_IPGT_MASK;
1181         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1182         ew32(TIPG, tipg);
1183
1184         do {
1185                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1186                 if (ret_val)
1187                         return ret_val;
1188
1189                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1190                 if (ret_val)
1191                         return ret_val;
1192                 i++;
1193         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1194
1195         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1196
1197         return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1198 }
1199
1200 /**
1201  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1202  *  @hw: pointer to the HW structure
1203  *  @offset: register offset to be read
1204  *  @data: pointer to the read data
1205  *
1206  *  Acquire semaphore, then read the PHY register at offset
1207  *  using the kumeran interface.  The information retrieved is stored in data.
1208  *  Release the semaphore before exiting.
1209  **/
1210 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1211                                            u16 *data)
1212 {
1213         u32 kmrnctrlsta;
1214         s32 ret_val;
1215
1216         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1217         if (ret_val)
1218                 return ret_val;
1219
1220         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1221                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1222         ew32(KMRNCTRLSTA, kmrnctrlsta);
1223         e1e_flush();
1224
1225         udelay(2);
1226
1227         kmrnctrlsta = er32(KMRNCTRLSTA);
1228         *data = (u16)kmrnctrlsta;
1229
1230         e1000_release_mac_csr_80003es2lan(hw);
1231
1232         return ret_val;
1233 }
1234
1235 /**
1236  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1237  *  @hw: pointer to the HW structure
1238  *  @offset: register offset to write to
1239  *  @data: data to write at register offset
1240  *
1241  *  Acquire semaphore, then write the data to PHY register
1242  *  at the offset using the kumeran interface.  Release semaphore
1243  *  before exiting.
1244  **/
1245 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1246                                             u16 data)
1247 {
1248         u32 kmrnctrlsta;
1249         s32 ret_val;
1250
1251         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1252         if (ret_val)
1253                 return ret_val;
1254
1255         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1256                        E1000_KMRNCTRLSTA_OFFSET) | data;
1257         ew32(KMRNCTRLSTA, kmrnctrlsta);
1258         e1e_flush();
1259
1260         udelay(2);
1261
1262         e1000_release_mac_csr_80003es2lan(hw);
1263
1264         return ret_val;
1265 }
1266
1267 /**
1268  *  e1000_read_mac_addr_80003es2lan - Read device MAC address
1269  *  @hw: pointer to the HW structure
1270  **/
1271 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1272 {
1273         s32 ret_val;
1274
1275         /* If there's an alternate MAC address place it in RAR0
1276          * so that it will override the Si installed default perm
1277          * address.
1278          */
1279         ret_val = e1000_check_alt_mac_addr_generic(hw);
1280         if (ret_val)
1281                 return ret_val;
1282
1283         return e1000_read_mac_addr_generic(hw);
1284 }
1285
1286 /**
1287  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1288  * @hw: pointer to the HW structure
1289  *
1290  * In the case of a PHY power down to save power, or to turn off link during a
1291  * driver unload, or wake on lan is not enabled, remove the link.
1292  **/
1293 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1294 {
1295         /* If the management interface is not enabled, then power down */
1296         if (!(hw->mac.ops.check_mng_mode(hw) ||
1297               hw->phy.ops.check_reset_block(hw)))
1298                 e1000_power_down_phy_copper(hw);
1299 }
1300
1301 /**
1302  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1303  *  @hw: pointer to the HW structure
1304  *
1305  *  Clears the hardware counters by reading the counter registers.
1306  **/
1307 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1308 {
1309         e1000e_clear_hw_cntrs_base(hw);
1310
1311         er32(PRC64);
1312         er32(PRC127);
1313         er32(PRC255);
1314         er32(PRC511);
1315         er32(PRC1023);
1316         er32(PRC1522);
1317         er32(PTC64);
1318         er32(PTC127);
1319         er32(PTC255);
1320         er32(PTC511);
1321         er32(PTC1023);
1322         er32(PTC1522);
1323
1324         er32(ALGNERRC);
1325         er32(RXERRC);
1326         er32(TNCRS);
1327         er32(CEXTERR);
1328         er32(TSCTC);
1329         er32(TSCTFC);
1330
1331         er32(MGTPRC);
1332         er32(MGTPDC);
1333         er32(MGTPTC);
1334
1335         er32(IAC);
1336         er32(ICRXOC);
1337
1338         er32(ICRXPTC);
1339         er32(ICRXATC);
1340         er32(ICTXPTC);
1341         er32(ICTXATC);
1342         er32(ICTXQEC);
1343         er32(ICTXQMTC);
1344         er32(ICRXDMTC);
1345 }
1346
1347 static const struct e1000_mac_operations es2_mac_ops = {
1348         .read_mac_addr          = e1000_read_mac_addr_80003es2lan,
1349         .id_led_init            = e1000e_id_led_init_generic,
1350         .blink_led              = e1000e_blink_led_generic,
1351         .check_mng_mode         = e1000e_check_mng_mode_generic,
1352         /* check_for_link dependent on media type */
1353         .cleanup_led            = e1000e_cleanup_led_generic,
1354         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1355         .get_bus_info           = e1000e_get_bus_info_pcie,
1356         .set_lan_id             = e1000_set_lan_id_multi_port_pcie,
1357         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1358         .led_on                 = e1000e_led_on_generic,
1359         .led_off                = e1000e_led_off_generic,
1360         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1361         .write_vfta             = e1000_write_vfta_generic,
1362         .clear_vfta             = e1000_clear_vfta_generic,
1363         .reset_hw               = e1000_reset_hw_80003es2lan,
1364         .init_hw                = e1000_init_hw_80003es2lan,
1365         .setup_link             = e1000e_setup_link_generic,
1366         /* setup_physical_interface dependent on media type */
1367         .setup_led              = e1000e_setup_led_generic,
1368         .config_collision_dist  = e1000e_config_collision_dist_generic,
1369         .rar_set                = e1000e_rar_set_generic,
1370 };
1371
1372 static const struct e1000_phy_operations es2_phy_ops = {
1373         .acquire                = e1000_acquire_phy_80003es2lan,
1374         .check_polarity         = e1000_check_polarity_m88,
1375         .check_reset_block      = e1000e_check_reset_block_generic,
1376         .commit                 = e1000e_phy_sw_reset,
1377         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1378         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1379         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1380         .get_info               = e1000e_get_phy_info_m88,
1381         .read_reg               = e1000_read_phy_reg_gg82563_80003es2lan,
1382         .release                = e1000_release_phy_80003es2lan,
1383         .reset                  = e1000e_phy_hw_reset_generic,
1384         .set_d0_lplu_state      = NULL,
1385         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1386         .write_reg              = e1000_write_phy_reg_gg82563_80003es2lan,
1387         .cfg_on_link_up         = e1000_cfg_on_link_up_80003es2lan,
1388 };
1389
1390 static const struct e1000_nvm_operations es2_nvm_ops = {
1391         .acquire                = e1000_acquire_nvm_80003es2lan,
1392         .read                   = e1000e_read_nvm_eerd,
1393         .release                = e1000_release_nvm_80003es2lan,
1394         .reload                 = e1000e_reload_nvm_generic,
1395         .update                 = e1000e_update_nvm_checksum_generic,
1396         .valid_led_default      = e1000e_valid_led_default,
1397         .validate               = e1000e_validate_nvm_checksum_generic,
1398         .write                  = e1000_write_nvm_80003es2lan,
1399 };
1400
1401 const struct e1000_info e1000_es2_info = {
1402         .mac                    = e1000_80003es2lan,
1403         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1404                                   | FLAG_HAS_JUMBO_FRAMES
1405                                   | FLAG_HAS_WOL
1406                                   | FLAG_APME_IN_CTRL3
1407                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1408                                   | FLAG_RX_NEEDS_RESTART /* errata */
1409                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1410                                   | FLAG_APME_CHECK_PORT_B
1411                                   | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
1412         .flags2                 = FLAG2_DMA_BURST,
1413         .pba                    = 38,
1414         .max_hw_frame_size      = DEFAULT_JUMBO,
1415         .get_variants           = e1000_get_variants_80003es2lan,
1416         .mac_ops                = &es2_mac_ops,
1417         .phy_ops                = &es2_phy_ops,
1418         .nvm_ops                = &es2_nvm_ops,
1419 };
1420