drivers/net/ethernet/intel/e1000e/80003es2lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
  30  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  31  */
  32
  33 #include "e1000.h"
  34
  35 /* A table for the GG82563 cable length where the range is defined
  36  * with a lower bound at "index" and the upper bound at
  37  * "index + 5".
  38  */
  39 static const u16 e1000_gg82563_cable_length_table[] = {
  40          0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
  41
  42 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
  43                 ARRAY_SIZE(e1000_gg82563_cable_length_table)
  44
  45 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
  46 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  47 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  48 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
  49 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
  50 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
  51 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
  52 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  53                                            u16 *data);
  54 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  55                                             u16 data);
  56 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
  57
  58 /**
  59  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
  60  *  @hw: pointer to the HW structure
  61  **/
  62 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
  63 {
  64         struct e1000_phy_info *phy = &hw->phy;
  65         s32 ret_val;
  66
  67         if (hw->phy.media_type != e1000_media_type_copper) {
  68                 phy->type       = e1000_phy_none;
  69                 return 0;
  70         } else {
  71                 phy->ops.power_up = e1000_power_up_phy_copper;
  72                 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
  73         }
  74
  75         phy->addr               = 1;
  76         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  77         phy->reset_delay_us      = 100;
  78         phy->type               = e1000_phy_gg82563;
  79
  80         /* This can only be done after all function pointers are setup. */
  81         ret_val = e1000e_get_phy_id(hw);
  82
  83         /* Verify phy id */
  84         if (phy->id != GG82563_E_PHY_ID)
  85                 return -E1000_ERR_PHY;
  86
  87         return ret_val;
  88 }
  89
  90 /**
  91  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
  92  *  @hw: pointer to the HW structure
  93  **/
  94 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
  95 {
  96         struct e1000_nvm_info *nvm = &hw->nvm;
  97         u32 eecd = er32(EECD);
  98         u16 size;
  99
 100         nvm->opcode_bits        = 8;
 101         nvm->delay_usec  = 1;
 102         switch (nvm->override) {
 103         case e1000_nvm_override_spi_large:
 104                 nvm->page_size    = 32;
 105                 nvm->address_bits = 16;
 106                 break;
 107         case e1000_nvm_override_spi_small:
 108                 nvm->page_size    = 8;
 109                 nvm->address_bits = 8;
 110                 break;
 111         default:
 112                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 113                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 114                 break;
 115         }
 116
 117         nvm->type = e1000_nvm_eeprom_spi;
 118
 119         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 120                      E1000_EECD_SIZE_EX_SHIFT);
 121
 122         /* Added to a constant, "size" becomes the left-shift value
 123          * for setting word_size.
 124          */
 125         size += NVM_WORD_SIZE_BASE_SHIFT;
 126
 127         /* EEPROM access above 16k is unsupported */
 128         if (size > 14)
 129                 size = 14;
 130         nvm->word_size  = 1 << size;
 131
 132         return 0;
 133 }
 134
 135 /**
 136  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 137  *  @hw: pointer to the HW structure
 138  **/
 139 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
 140 {
 141         struct e1000_mac_info *mac = &hw->mac;
 142
 143         /* Set media type and media-dependent function pointers */
 144         switch (hw->adapter->pdev->device) {
 145         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 146                 hw->phy.media_type = e1000_media_type_internal_serdes;
 147                 mac->ops.check_for_link = e1000e_check_for_serdes_link;
 148                 mac->ops.setup_physical_interface =
 149                     e1000e_setup_fiber_serdes_link;
 150                 break;
 151         default:
 152                 hw->phy.media_type = e1000_media_type_copper;
 153                 mac->ops.check_for_link = e1000e_check_for_copper_link;
 154                 mac->ops.setup_physical_interface =
 155                     e1000_setup_copper_link_80003es2lan;
 156                 break;
 157         }
 158
 159         /* Set mta register count */
 160         mac->mta_reg_count = 128;
 161         /* Set rar entry count */
 162         mac->rar_entry_count = E1000_RAR_ENTRIES;
 163         /* FWSM register */
 164         mac->has_fwsm = true;
 165         /* ARC supported; valid only if manageability features are enabled. */
 166         mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
 167         /* Adaptive IFS not supported */
 168         mac->adaptive_ifs = false;
 169
 170         /* set lan id for port to determine which phy lock to use */
 171         hw->mac.ops.set_lan_id(hw);
 172
 173         return 0;
 174 }
 175
 176 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
 177 {
 178         struct e1000_hw *hw = &adapter->hw;
 179         s32 rc;
 180
 181         rc = e1000_init_mac_params_80003es2lan(hw);
 182         if (rc)
 183                 return rc;
 184
 185         rc = e1000_init_nvm_params_80003es2lan(hw);
 186         if (rc)
 187                 return rc;
 188
 189         rc = e1000_init_phy_params_80003es2lan(hw);
 190         if (rc)
 191                 return rc;
 192
 193         return 0;
 194 }
 195
 196 /**
 197  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 198  *  @hw: pointer to the HW structure
 199  *
 200  *  A wrapper to acquire access rights to the correct PHY.
 201  **/
 202 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 203 {
 204         u16 mask;
 205
 206         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 207         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 208 }
 209
 210 /**
 211  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 212  *  @hw: pointer to the HW structure
 213  *
 214  *  A wrapper to release access rights to the correct PHY.
 215  **/
 216 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 217 {
 218         u16 mask;
 219
 220         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 221         e1000_release_swfw_sync_80003es2lan(hw, mask);
 222 }
 223
 224 /**
 225  *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
 226  *  @hw: pointer to the HW structure
 227  *
 228  *  Acquire the semaphore to access the Kumeran interface.
 229  *
 230  **/
 231 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 232 {
 233         u16 mask;
 234
 235         mask = E1000_SWFW_CSR_SM;
 236
 237         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 238 }
 239
 240 /**
 241  *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
 242  *  @hw: pointer to the HW structure
 243  *
 244  *  Release the semaphore used to access the Kumeran interface
 245  **/
 246 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 247 {
 248         u16 mask;
 249
 250         mask = E1000_SWFW_CSR_SM;
 251
 252         e1000_release_swfw_sync_80003es2lan(hw, mask);
 253 }
 254
 255 /**
 256  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 257  *  @hw: pointer to the HW structure
 258  *
 259  *  Acquire the semaphore to access the EEPROM.
 260  **/
 261 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 262 {
 263         s32 ret_val;
 264
 265         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 266         if (ret_val)
 267                 return ret_val;
 268
 269         ret_val = e1000e_acquire_nvm(hw);
 270
 271         if (ret_val)
 272                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 273
 274         return ret_val;
 275 }
 276
 277 /**
 278  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 279  *  @hw: pointer to the HW structure
 280  *
 281  *  Release the semaphore used to access the EEPROM.
 282  **/
 283 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 284 {
 285         e1000e_release_nvm(hw);
 286         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 287 }
 288
 289 /**
 290  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 291  *  @hw: pointer to the HW structure
 292  *  @mask: specifies which semaphore to acquire
 293  *
 294  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 295  *  will also specify which port we're acquiring the lock for.
 296  **/
 297 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 298 {
 299         u32 swfw_sync;
 300         u32 swmask = mask;
 301         u32 fwmask = mask << 16;
 302         s32 i = 0;
 303         s32 timeout = 50;
 304
 305         while (i < timeout) {
 306                 if (e1000e_get_hw_semaphore(hw))
 307                         return -E1000_ERR_SWFW_SYNC;
 308
 309                 swfw_sync = er32(SW_FW_SYNC);
 310                 if (!(swfw_sync & (fwmask | swmask)))
 311                         break;
 312
 313                 /* Firmware currently using resource (fwmask)
 314                  * or other software thread using resource (swmask)
 315                  */
 316                 e1000e_put_hw_semaphore(hw);
 317                 mdelay(5);
 318                 i++;
 319         }
 320
 321         if (i == timeout) {
 322                 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
 323                 return -E1000_ERR_SWFW_SYNC;
 324         }
 325
 326         swfw_sync |= swmask;
 327         ew32(SW_FW_SYNC, swfw_sync);
 328
 329         e1000e_put_hw_semaphore(hw);
 330
 331         return 0;
 332 }
 333
 334 /**
 335  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 336  *  @hw: pointer to the HW structure
 337  *  @mask: specifies which semaphore to acquire
 338  *
 339  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 340  *  will also specify which port we're releasing the lock for.
 341  **/
 342 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 343 {
 344         u32 swfw_sync;
 345
 346         while (e1000e_get_hw_semaphore(hw) != 0)
 347                 ; /* Empty */
 348
 349         swfw_sync = er32(SW_FW_SYNC);
 350         swfw_sync &= ~mask;
 351         ew32(SW_FW_SYNC, swfw_sync);
 352
 353         e1000e_put_hw_semaphore(hw);
 354 }
 355
 356 /**
 357  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 358  *  @hw: pointer to the HW structure
 359  *  @offset: offset of the register to read
 360  *  @data: pointer to the data returned from the operation
 361  *
 362  *  Read the GG82563 PHY register.
 363  **/
 364 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 365                                                   u32 offset, u16 *data)
 366 {
 367         s32 ret_val;
 368         u32 page_select;
 369         u16 temp;
 370
 371         ret_val = e1000_acquire_phy_80003es2lan(hw);
 372         if (ret_val)
 373                 return ret_val;
 374
 375         /* Select Configuration Page */
 376         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 377                 page_select = GG82563_PHY_PAGE_SELECT;
 378         } else {
 379                 /* Use Alternative Page Select register to access
 380                  * registers 30 and 31
 381                  */
 382                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 383         }
 384
 385         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 386         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 387         if (ret_val) {
 388                 e1000_release_phy_80003es2lan(hw);
 389                 return ret_val;
 390         }
 391
 392         if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
 393                 /* The "ready" bit in the MDIC register may be incorrectly set
 394                  * before the device has completed the "Page Select" MDI
 395                  * transaction.  So we wait 200us after each MDI command...
 396                  */
 397                 udelay(200);
 398
 399                 /* ...and verify the command was successful. */
 400                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 401
 402                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 403                         e1000_release_phy_80003es2lan(hw);
 404                         return -E1000_ERR_PHY;
 405                 }
 406
 407                 udelay(200);
 408
 409                 ret_val = e1000e_read_phy_reg_mdic(hw,
 410                                                    MAX_PHY_REG_ADDRESS & offset,
 411                                                    data);
 412
 413                 udelay(200);
 414         } else {
 415                 ret_val = e1000e_read_phy_reg_mdic(hw,
 416                                                    MAX_PHY_REG_ADDRESS & offset,
 417                                                    data);
 418         }
 419
 420         e1000_release_phy_80003es2lan(hw);
 421
 422         return ret_val;
 423 }
 424
 425 /**
 426  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 427  *  @hw: pointer to the HW structure
 428  *  @offset: offset of the register to read
 429  *  @data: value to write to the register
 430  *
 431  *  Write to the GG82563 PHY register.
 432  **/
 433 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 434                                                    u32 offset, u16 data)
 435 {
 436         s32 ret_val;
 437         u32 page_select;
 438         u16 temp;
 439
 440         ret_val = e1000_acquire_phy_80003es2lan(hw);
 441         if (ret_val)
 442                 return ret_val;
 443
 444         /* Select Configuration Page */
 445         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 446                 page_select = GG82563_PHY_PAGE_SELECT;
 447         } else {
 448                 /* Use Alternative Page Select register to access
 449                  * registers 30 and 31
 450                  */
 451                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 452         }
 453
 454         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 455         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 456         if (ret_val) {
 457                 e1000_release_phy_80003es2lan(hw);
 458                 return ret_val;
 459         }
 460
 461         if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
 462                 /* The "ready" bit in the MDIC register may be incorrectly set
 463                  * before the device has completed the "Page Select" MDI
 464                  * transaction.  So we wait 200us after each MDI command...
 465                  */
 466                 udelay(200);
 467
 468                 /* ...and verify the command was successful. */
 469                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 470
 471                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 472                         e1000_release_phy_80003es2lan(hw);
 473                         return -E1000_ERR_PHY;
 474                 }
 475
 476                 udelay(200);
 477
 478                 ret_val = e1000e_write_phy_reg_mdic(hw,
 479                                                     MAX_PHY_REG_ADDRESS &
 480                                                     offset, data);
 481
 482                 udelay(200);
 483         } else {
 484                 ret_val = e1000e_write_phy_reg_mdic(hw,
 485                                                     MAX_PHY_REG_ADDRESS &
 486                                                     offset, data);
 487         }
 488
 489         e1000_release_phy_80003es2lan(hw);
 490
 491         return ret_val;
 492 }
 493
 494 /**
 495  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 496  *  @hw: pointer to the HW structure
 497  *  @offset: offset of the register to read
 498  *  @words: number of words to write
 499  *  @data: buffer of data to write to the NVM
 500  *
 501  *  Write "words" of data to the ESB2 NVM.
 502  **/
 503 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 504                                        u16 words, u16 *data)
 505 {
 506         return e1000e_write_nvm_spi(hw, offset, words, data);
 507 }
 508
 509 /**
 510  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 511  *  @hw: pointer to the HW structure
 512  *
 513  *  Wait a specific amount of time for manageability processes to complete.
 514  *  This is a function pointer entry point called by the phy module.
 515  **/
 516 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 517 {
 518         s32 timeout = PHY_CFG_TIMEOUT;
 519         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 520
 521         if (hw->bus.func == 1)
 522                 mask = E1000_NVM_CFG_DONE_PORT_1;
 523
 524         while (timeout) {
 525                 if (er32(EEMNGCTL) & mask)
 526                         break;
 527                 usleep_range(1000, 2000);
 528                 timeout--;
 529         }
 530         if (!timeout) {
 531                 e_dbg("MNG configuration cycle has not completed.\n");
 532                 return -E1000_ERR_RESET;
 533         }
 534
 535         return 0;
 536 }
 537
 538 /**
 539  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 540  *  @hw: pointer to the HW structure
 541  *
 542  *  Force the speed and duplex settings onto the PHY.  This is a
 543  *  function pointer entry point called by the phy module.
 544  **/
 545 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 546 {
 547         s32 ret_val;
 548         u16 phy_data;
 549         bool link;
 550
 551         /* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 552          * forced whenever speed and duplex are forced.
 553          */
 554         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 555         if (ret_val)
 556                 return ret_val;
 557
 558         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 559         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 560         if (ret_val)
 561                 return ret_val;
 562
 563         e_dbg("GG82563 PSCR: %X\n", phy_data);
 564
 565         ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
 566         if (ret_val)
 567                 return ret_val;
 568
 569         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 570
 571         /* Reset the phy to commit changes. */
 572         phy_data |= BMCR_RESET;
 573
 574         ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
 575         if (ret_val)
 576                 return ret_val;
 577
 578         udelay(1);
 579
 580         if (hw->phy.autoneg_wait_to_complete) {
 581                 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
 582
 583                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 584                                                       100000, &link);
 585                 if (ret_val)
 586                         return ret_val;
 587
 588                 if (!link) {
 589                         /* We didn't get link.
 590                          * Reset the DSP and cross our fingers.
 591                          */
 592                         ret_val = e1000e_phy_reset_dsp(hw);
 593                         if (ret_val)
 594                                 return ret_val;
 595                 }
 596
 597                 /* Try once more */
 598                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 599                                                       100000, &link);
 600                 if (ret_val)
 601                         return ret_val;
 602         }
 603
 604         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 605         if (ret_val)
 606                 return ret_val;
 607
 608         /* Resetting the phy means we need to verify the TX_CLK corresponds
 609          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 610          */
 611         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 612         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 613                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 614         else
 615                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 616
 617         /* In addition, we must re-enable CRS on Tx for both half and full
 618          * duplex.
 619          */
 620         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 621         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 622
 623         return ret_val;
 624 }
 625
 626 /**
 627  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 628  *  @hw: pointer to the HW structure
 629  *
 630  *  Find the approximate cable length as measured by the GG82563 PHY.
 631  *  This is a function pointer entry point called by the phy module.
 632  **/
 633 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 634 {
 635         struct e1000_phy_info *phy = &hw->phy;
 636         s32 ret_val;
 637         u16 phy_data, index;
 638
 639         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 640         if (ret_val)
 641                 return ret_val;
 642
 643         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 644
 645         if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
 646                 return -E1000_ERR_PHY;
 647
 648         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 649         phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
 650
 651         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 652
 653         return 0;
 654 }
 655
 656 /**
 657  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 658  *  @hw: pointer to the HW structure
 659  *  @speed: pointer to speed buffer
 660  *  @duplex: pointer to duplex buffer
 661  *
 662  *  Retrieve the current speed and duplex configuration.
 663  **/
 664 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 665                                               u16 *duplex)
 666 {
 667         s32 ret_val;
 668
 669         if (hw->phy.media_type == e1000_media_type_copper) {
 670                 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
 671                 hw->phy.ops.cfg_on_link_up(hw);
 672         } else {
 673                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
 674                                                                    speed,
 675                                                                    duplex);
 676         }
 677
 678         return ret_val;
 679 }
 680
 681 /**
 682  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 683  *  @hw: pointer to the HW structure
 684  *
 685  *  Perform a global reset to the ESB2 controller.
 686  **/
 687 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 688 {
 689         u32 ctrl;
 690         s32 ret_val;
 691         u16 kum_reg_data;
 692
 693         /* Prevent the PCI-E bus from sticking if there is no TLP connection
 694          * on the last TLP read/write transaction when MAC is reset.
 695          */
 696         ret_val = e1000e_disable_pcie_master(hw);
 697         if (ret_val)
 698                 e_dbg("PCI-E Master disable polling has failed.\n");
 699
 700         e_dbg("Masking off all interrupts\n");
 701         ew32(IMC, 0xffffffff);
 702
 703         ew32(RCTL, 0);
 704         ew32(TCTL, E1000_TCTL_PSP);
 705         e1e_flush();
 706
 707         usleep_range(10000, 20000);
 708
 709         ctrl = er32(CTRL);
 710
 711         ret_val = e1000_acquire_phy_80003es2lan(hw);
 712         if (ret_val)
 713                 return ret_val;
 714
 715         e_dbg("Issuing a global reset to MAC\n");
 716         ew32(CTRL, ctrl | E1000_CTRL_RST);
 717         e1000_release_phy_80003es2lan(hw);
 718
 719         /* Disable IBIST slave mode (far-end loopback) */
 720         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 721                                         &kum_reg_data);
 722         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 723         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 724                                          kum_reg_data);
 725
 726         ret_val = e1000e_get_auto_rd_done(hw);
 727         if (ret_val)
 728                 /* We don't want to continue accessing MAC registers. */
 729                 return ret_val;
 730
 731         /* Clear any pending interrupt events. */
 732         ew32(IMC, 0xffffffff);
 733         er32(ICR);
 734
 735         return e1000_check_alt_mac_addr_generic(hw);
 736 }
 737
 738 /**
 739  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 740  *  @hw: pointer to the HW structure
 741  *
 742  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 743  **/
 744 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 745 {
 746         struct e1000_mac_info *mac = &hw->mac;
 747         u32 reg_data;
 748         s32 ret_val;
 749         u16 kum_reg_data;
 750         u16 i;
 751
 752         e1000_initialize_hw_bits_80003es2lan(hw);
 753
 754         /* Initialize identification LED */
 755         ret_val = mac->ops.id_led_init(hw);
 756         /* An error is not fatal and we should not stop init due to this */
 757         if (ret_val)
 758                 e_dbg("Error initializing identification LED\n");
 759
 760         /* Disabling VLAN filtering */
 761         e_dbg("Initializing the IEEE VLAN\n");
 762         mac->ops.clear_vfta(hw);
 763
 764         /* Setup the receive address. */
 765         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 766
 767         /* Zero out the Multicast HASH table */
 768         e_dbg("Zeroing the MTA\n");
 769         for (i = 0; i < mac->mta_reg_count; i++)
 770                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 771
 772         /* Setup link and flow control */
 773         ret_val = mac->ops.setup_link(hw);
 774         if (ret_val)
 775                 return ret_val;
 776
 777         /* Disable IBIST slave mode (far-end loopback) */
 778         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 779                                         &kum_reg_data);
 780         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 781         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 782                                          kum_reg_data);
 783
 784         /* Set the transmit descriptor write-back policy */
 785         reg_data = er32(TXDCTL(0));
 786         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
 787                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
 788         ew32(TXDCTL(0), reg_data);
 789
 790         /* ...for both queues. */
 791         reg_data = er32(TXDCTL(1));
 792         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
 793                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
 794         ew32(TXDCTL(1), reg_data);
 795
 796         /* Enable retransmit on late collisions */
 797         reg_data = er32(TCTL);
 798         reg_data |= E1000_TCTL_RTLC;
 799         ew32(TCTL, reg_data);
 800
 801         /* Configure Gigabit Carry Extend Padding */
 802         reg_data = er32(TCTL_EXT);
 803         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 804         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 805         ew32(TCTL_EXT, reg_data);
 806
 807         /* Configure Transmit Inter-Packet Gap */
 808         reg_data = er32(TIPG);
 809         reg_data &= ~E1000_TIPG_IPGT_MASK;
 810         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 811         ew32(TIPG, reg_data);
 812
 813         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 814         reg_data &= ~0x00100000;
 815         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 816
 817         /* default to true to enable the MDIC W/A */
 818         hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
 819
 820         ret_val =
 821             e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
 822                                             E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
 823         if (!ret_val) {
 824                 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
 825                     E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
 826                         hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
 827         }
 828
 829         /* Clear all of the statistics registers (clear on read).  It is
 830          * important that we do this after we have tried to establish link
 831          * because the symbol error count will increment wildly if there
 832          * is no link.
 833          */
 834         e1000_clear_hw_cntrs_80003es2lan(hw);
 835
 836         return ret_val;
 837 }
 838
 839 /**
 840  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 841  *  @hw: pointer to the HW structure
 842  *
 843  *  Initializes required hardware-dependent bits needed for normal operation.
 844  **/
 845 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 846 {
 847         u32 reg;
 848
 849         /* Transmit Descriptor Control 0 */
 850         reg = er32(TXDCTL(0));
 851         reg |= (1 << 22);
 852         ew32(TXDCTL(0), reg);
 853
 854         /* Transmit Descriptor Control 1 */
 855         reg = er32(TXDCTL(1));
 856         reg |= (1 << 22);
 857         ew32(TXDCTL(1), reg);
 858
 859         /* Transmit Arbitration Control 0 */
 860         reg = er32(TARC(0));
 861         reg &= ~(0xF << 27); /* 30:27 */
 862         if (hw->phy.media_type != e1000_media_type_copper)
 863                 reg &= ~(1 << 20);
 864         ew32(TARC(0), reg);
 865
 866         /* Transmit Arbitration Control 1 */
 867         reg = er32(TARC(1));
 868         if (er32(TCTL) & E1000_TCTL_MULR)
 869                 reg &= ~(1 << 28);
 870         else
 871                 reg |= (1 << 28);
 872         ew32(TARC(1), reg);
 873
 874         /* Disable IPv6 extension header parsing because some malformed
 875          * IPv6 headers can hang the Rx.
 876          */
 877         reg = er32(RFCTL);
 878         reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
 879         ew32(RFCTL, reg);
 880 }
 881
 882 /**
 883  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
 884  *  @hw: pointer to the HW structure
 885  *
 886  *  Setup some GG82563 PHY registers for obtaining link
 887  **/
 888 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 889 {
 890         struct e1000_phy_info *phy = &hw->phy;
 891         s32 ret_val;
 892         u32 reg;
 893         u16 data;
 894
 895         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
 896         if (ret_val)
 897                 return ret_val;
 898
 899         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 900         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 901         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 902
 903         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
 904         if (ret_val)
 905                 return ret_val;
 906
 907         /* Options:
 908          *   MDI/MDI-X = 0 (default)
 909          *   0 - Auto for all speeds
 910          *   1 - MDI mode
 911          *   2 - MDI-X mode
 912          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 913          */
 914         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
 915         if (ret_val)
 916                 return ret_val;
 917
 918         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 919
 920         switch (phy->mdix) {
 921         case 1:
 922                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 923                 break;
 924         case 2:
 925                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 926                 break;
 927         case 0:
 928         default:
 929                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
 930                 break;
 931         }
 932
 933         /* Options:
 934          *   disable_polarity_correction = 0 (default)
 935          *       Automatic Correction for Reversed Cable Polarity
 936          *   0 - Disabled
 937          *   1 - Enabled
 938          */
 939         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 940         if (phy->disable_polarity_correction)
 941                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 942
 943         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
 944         if (ret_val)
 945                 return ret_val;
 946
 947         /* SW Reset the PHY so all changes take effect */
 948         ret_val = hw->phy.ops.commit(hw);
 949         if (ret_val) {
 950                 e_dbg("Error Resetting the PHY\n");
 951                 return ret_val;
 952         }
 953
 954         /* Bypass Rx and Tx FIFO's */
 955         reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
 956         data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
 957                 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
 958         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
 959         if (ret_val)
 960                 return ret_val;
 961
 962         reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
 963         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
 964         if (ret_val)
 965                 return ret_val;
 966         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
 967         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
 968         if (ret_val)
 969                 return ret_val;
 970
 971         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
 972         if (ret_val)
 973                 return ret_val;
 974
 975         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
 976         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
 977         if (ret_val)
 978                 return ret_val;
 979
 980         reg = er32(CTRL_EXT);
 981         reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
 982         ew32(CTRL_EXT, reg);
 983
 984         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
 985         if (ret_val)
 986                 return ret_val;
 987
 988         /* Do not init these registers when the HW is in IAMT mode, since the
 989          * firmware will have already initialized them.  We only initialize
 990          * them if the HW is not in IAMT mode.
 991          */
 992         if (!hw->mac.ops.check_mng_mode(hw)) {
 993                 /* Enable Electrical Idle on the PHY */
 994                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
 995                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
 996                 if (ret_val)
 997                         return ret_val;
 998
 999                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1000                 if (ret_val)
1001                         return ret_val;
1002
1003                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1004                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1005                 if (ret_val)
1006                         return ret_val;
1007         }
1008
1009         /* Workaround: Disable padding in Kumeran interface in the MAC
1010          * and in the PHY to avoid CRC errors.
1011          */
1012         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1013         if (ret_val)
1014                 return ret_val;
1015
1016         data |= GG82563_ICR_DIS_PADDING;
1017         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1018         if (ret_val)
1019                 return ret_val;
1020
1021         return 0;
1022 }
1023
1024 /**
1025  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1026  *  @hw: pointer to the HW structure
1027  *
1028  *  Essentially a wrapper for setting up all things "copper" related.
1029  *  This is a function pointer entry point called by the mac module.
1030  **/
1031 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1032 {
1033         u32 ctrl;
1034         s32 ret_val;
1035         u16 reg_data;
1036
1037         ctrl = er32(CTRL);
1038         ctrl |= E1000_CTRL_SLU;
1039         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1040         ew32(CTRL, ctrl);
1041
1042         /* Set the mac to wait the maximum time between each
1043          * iteration and increase the max iterations when
1044          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1045          */
1046         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1047                                                    0xFFFF);
1048         if (ret_val)
1049                 return ret_val;
1050         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1051                                                   &reg_data);
1052         if (ret_val)
1053                 return ret_val;
1054         reg_data |= 0x3F;
1055         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1056                                                    reg_data);
1057         if (ret_val)
1058                 return ret_val;
1059         ret_val =
1060             e1000_read_kmrn_reg_80003es2lan(hw,
1061                                             E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1062                                             &reg_data);
1063         if (ret_val)
1064                 return ret_val;
1065         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1066         ret_val =
1067             e1000_write_kmrn_reg_80003es2lan(hw,
1068                                              E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1069                                              reg_data);
1070         if (ret_val)
1071                 return ret_val;
1072
1073         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1074         if (ret_val)
1075                 return ret_val;
1076
1077         return e1000e_setup_copper_link(hw);
1078 }
1079
1080 /**
1081  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1082  *  @hw: pointer to the HW structure
1083  *  @duplex: current duplex setting
1084  *
1085  *  Configure the KMRN interface by applying last minute quirks for
1086  *  10/100 operation.
1087  **/
1088 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1089 {
1090         s32 ret_val = 0;
1091         u16 speed;
1092         u16 duplex;
1093
1094         if (hw->phy.media_type == e1000_media_type_copper) {
1095                 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1096                                                              &duplex);
1097                 if (ret_val)
1098                         return ret_val;
1099
1100                 if (speed == SPEED_1000)
1101                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1102                 else
1103                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1104         }
1105
1106         return ret_val;
1107 }
1108
1109 /**
1110  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1111  *  @hw: pointer to the HW structure
1112  *  @duplex: current duplex setting
1113  *
1114  *  Configure the KMRN interface by applying last minute quirks for
1115  *  10/100 operation.
1116  **/
1117 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1118 {
1119         s32 ret_val;
1120         u32 tipg;
1121         u32 i = 0;
1122         u16 reg_data, reg_data2;
1123
1124         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1125         ret_val =
1126             e1000_write_kmrn_reg_80003es2lan(hw,
1127                                              E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1128                                              reg_data);
1129         if (ret_val)
1130                 return ret_val;
1131
1132         /* Configure Transmit Inter-Packet Gap */
1133         tipg = er32(TIPG);
1134         tipg &= ~E1000_TIPG_IPGT_MASK;
1135         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1136         ew32(TIPG, tipg);
1137
1138         do {
1139                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1140                 if (ret_val)
1141                         return ret_val;
1142
1143                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1144                 if (ret_val)
1145                         return ret_val;
1146                 i++;
1147         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1148
1149         if (duplex == HALF_DUPLEX)
1150                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1151         else
1152                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1153
1154         return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1155 }
1156
1157 /**
1158  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1159  *  @hw: pointer to the HW structure
1160  *
1161  *  Configure the KMRN interface by applying last minute quirks for
1162  *  gigabit operation.
1163  **/
1164 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1165 {
1166         s32 ret_val;
1167         u16 reg_data, reg_data2;
1168         u32 tipg;
1169         u32 i = 0;
1170
1171         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1172         ret_val =
1173             e1000_write_kmrn_reg_80003es2lan(hw,
1174                                              E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1175                                              reg_data);
1176         if (ret_val)
1177                 return ret_val;
1178
1179         /* Configure Transmit Inter-Packet Gap */
1180         tipg = er32(TIPG);
1181         tipg &= ~E1000_TIPG_IPGT_MASK;
1182         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1183         ew32(TIPG, tipg);
1184
1185         do {
1186                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1187                 if (ret_val)
1188                         return ret_val;
1189
1190                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1191                 if (ret_val)
1192                         return ret_val;
1193                 i++;
1194         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1195
1196         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1197
1198         return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1199 }
1200
1201 /**
1202  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1203  *  @hw: pointer to the HW structure
1204  *  @offset: register offset to be read
1205  *  @data: pointer to the read data
1206  *
1207  *  Acquire semaphore, then read the PHY register at offset
1208  *  using the kumeran interface.  The information retrieved is stored in data.
1209  *  Release the semaphore before exiting.
1210  **/
1211 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1212                                            u16 *data)
1213 {
1214         u32 kmrnctrlsta;
1215         s32 ret_val;
1216
1217         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1218         if (ret_val)
1219                 return ret_val;
1220
1221         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1222                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1223         ew32(KMRNCTRLSTA, kmrnctrlsta);
1224         e1e_flush();
1225
1226         udelay(2);
1227
1228         kmrnctrlsta = er32(KMRNCTRLSTA);
1229         *data = (u16)kmrnctrlsta;
1230
1231         e1000_release_mac_csr_80003es2lan(hw);
1232
1233         return ret_val;
1234 }
1235
1236 /**
1237  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1238  *  @hw: pointer to the HW structure
1239  *  @offset: register offset to write to
1240  *  @data: data to write at register offset
1241  *
1242  *  Acquire semaphore, then write the data to PHY register
1243  *  at the offset using the kumeran interface.  Release semaphore
1244  *  before exiting.
1245  **/
1246 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1247                                             u16 data)
1248 {
1249         u32 kmrnctrlsta;
1250         s32 ret_val;
1251
1252         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1253         if (ret_val)
1254                 return ret_val;
1255
1256         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1257                        E1000_KMRNCTRLSTA_OFFSET) | data;
1258         ew32(KMRNCTRLSTA, kmrnctrlsta);
1259         e1e_flush();
1260
1261         udelay(2);
1262
1263         e1000_release_mac_csr_80003es2lan(hw);
1264
1265         return ret_val;
1266 }
1267
1268 /**
1269  *  e1000_read_mac_addr_80003es2lan - Read device MAC address
1270  *  @hw: pointer to the HW structure
1271  **/
1272 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1273 {
1274         s32 ret_val;
1275
1276         /* If there's an alternate MAC address place it in RAR0
1277          * so that it will override the Si installed default perm
1278          * address.
1279          */
1280         ret_val = e1000_check_alt_mac_addr_generic(hw);
1281         if (ret_val)
1282                 return ret_val;
1283
1284         return e1000_read_mac_addr_generic(hw);
1285 }
1286
1287 /**
1288  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1289  * @hw: pointer to the HW structure
1290  *
1291  * In the case of a PHY power down to save power, or to turn off link during a
1292  * driver unload, or wake on lan is not enabled, remove the link.
1293  **/
1294 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1295 {
1296         /* If the management interface is not enabled, then power down */
1297         if (!(hw->mac.ops.check_mng_mode(hw) ||
1298               hw->phy.ops.check_reset_block(hw)))
1299                 e1000_power_down_phy_copper(hw);
1300 }
1301
1302 /**
1303  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1304  *  @hw: pointer to the HW structure
1305  *
1306  *  Clears the hardware counters by reading the counter registers.
1307  **/
1308 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1309 {
1310         e1000e_clear_hw_cntrs_base(hw);
1311
1312         er32(PRC64);
1313         er32(PRC127);
1314         er32(PRC255);
1315         er32(PRC511);
1316         er32(PRC1023);
1317         er32(PRC1522);
1318         er32(PTC64);
1319         er32(PTC127);
1320         er32(PTC255);
1321         er32(PTC511);
1322         er32(PTC1023);
1323         er32(PTC1522);
1324
1325         er32(ALGNERRC);
1326         er32(RXERRC);
1327         er32(TNCRS);
1328         er32(CEXTERR);
1329         er32(TSCTC);
1330         er32(TSCTFC);
1331
1332         er32(MGTPRC);
1333         er32(MGTPDC);
1334         er32(MGTPTC);
1335
1336         er32(IAC);
1337         er32(ICRXOC);
1338
1339         er32(ICRXPTC);
1340         er32(ICRXATC);
1341         er32(ICTXPTC);
1342         er32(ICTXATC);
1343         er32(ICTXQEC);
1344         er32(ICTXQMTC);
1345         er32(ICRXDMTC);
1346 }
1347
1348 static const struct e1000_mac_operations es2_mac_ops = {
1349         .read_mac_addr          = e1000_read_mac_addr_80003es2lan,
1350         .id_led_init            = e1000e_id_led_init_generic,
1351         .blink_led              = e1000e_blink_led_generic,
1352         .check_mng_mode         = e1000e_check_mng_mode_generic,
1353         /* check_for_link dependent on media type */
1354         .cleanup_led            = e1000e_cleanup_led_generic,
1355         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1356         .get_bus_info           = e1000e_get_bus_info_pcie,
1357         .set_lan_id             = e1000_set_lan_id_multi_port_pcie,
1358         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1359         .led_on                 = e1000e_led_on_generic,
1360         .led_off                = e1000e_led_off_generic,
1361         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1362         .write_vfta             = e1000_write_vfta_generic,
1363         .clear_vfta             = e1000_clear_vfta_generic,
1364         .reset_hw               = e1000_reset_hw_80003es2lan,
1365         .init_hw                = e1000_init_hw_80003es2lan,
1366         .setup_link             = e1000e_setup_link_generic,
1367         /* setup_physical_interface dependent on media type */
1368         .setup_led              = e1000e_setup_led_generic,
1369         .config_collision_dist  = e1000e_config_collision_dist_generic,
1370         .rar_set                = e1000e_rar_set_generic,
1371 };
1372
1373 static const struct e1000_phy_operations es2_phy_ops = {
1374         .acquire                = e1000_acquire_phy_80003es2lan,
1375         .check_polarity         = e1000_check_polarity_m88,
1376         .check_reset_block      = e1000e_check_reset_block_generic,
1377         .commit                 = e1000e_phy_sw_reset,
1378         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1379         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1380         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1381         .get_info               = e1000e_get_phy_info_m88,
1382         .read_reg               = e1000_read_phy_reg_gg82563_80003es2lan,
1383         .release                = e1000_release_phy_80003es2lan,
1384         .reset                  = e1000e_phy_hw_reset_generic,
1385         .set_d0_lplu_state      = NULL,
1386         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1387         .write_reg              = e1000_write_phy_reg_gg82563_80003es2lan,
1388         .cfg_on_link_up         = e1000_cfg_on_link_up_80003es2lan,
1389 };
1390
1391 static const struct e1000_nvm_operations es2_nvm_ops = {
1392         .acquire                = e1000_acquire_nvm_80003es2lan,
1393         .read                   = e1000e_read_nvm_eerd,
1394         .release                = e1000_release_nvm_80003es2lan,
1395         .reload                 = e1000e_reload_nvm_generic,
1396         .update                 = e1000e_update_nvm_checksum_generic,
1397         .valid_led_default      = e1000e_valid_led_default,
1398         .validate               = e1000e_validate_nvm_checksum_generic,
1399         .write                  = e1000_write_nvm_80003es2lan,
1400 };
1401
1402 const struct e1000_info e1000_es2_info = {
1403         .mac                    = e1000_80003es2lan,
1404         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1405                                   | FLAG_HAS_JUMBO_FRAMES
1406                                   | FLAG_HAS_WOL
1407                                   | FLAG_APME_IN_CTRL3
1408                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1409                                   | FLAG_RX_NEEDS_RESTART /* errata */
1410                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1411                                   | FLAG_APME_CHECK_PORT_B
1412                                   | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
1413         .flags2                 = FLAG2_DMA_BURST,
1414         .pba                    = 38,
1415         .max_hw_frame_size      = DEFAULT_JUMBO,
1416         .get_variants           = e1000_get_variants_80003es2lan,
1417         .mac_ops                = &es2_mac_ops,
1418         .phy_ops                = &es2_phy_ops,
1419         .nvm_ops                = &es2_nvm_ops,
1420 };