1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 /* 82562G 10/100 Network Connection
30 * 82562G-2 10/100 Network Connection
31 * 82562GT 10/100 Network Connection
32 * 82562GT-2 10/100 Network Connection
33 * 82562V 10/100 Network Connection
34 * 82562V-2 10/100 Network Connection
35 * 82566DC-2 Gigabit Network Connection
36 * 82566DC Gigabit Network Connection
37 * 82566DM-2 Gigabit Network Connection
38 * 82566DM Gigabit Network Connection
39 * 82566MC Gigabit Network Connection
40 * 82566MM Gigabit Network Connection
41 * 82567LM Gigabit Network Connection
42 * 82567LF Gigabit Network Connection
43 * 82567V Gigabit Network Connection
44 * 82567LM-2 Gigabit Network Connection
45 * 82567LF-2 Gigabit Network Connection
46 * 82567V-2 Gigabit Network Connection
47 * 82567LF-3 Gigabit Network Connection
48 * 82567LM-3 Gigabit Network Connection
49 * 82567LM-4 Gigabit Network Connection
50 * 82577LM Gigabit Network Connection
51 * 82577LC Gigabit Network Connection
52 * 82578DM Gigabit Network Connection
53 * 82578DC Gigabit Network Connection
54 * 82579LM Gigabit Network Connection
55 * 82579V Gigabit Network Connection
60 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
61 /* Offset 04h HSFSTS */
62 union ich8_hws_flash_status {
64 u16 flcdone:1; /* bit 0 Flash Cycle Done */
65 u16 flcerr:1; /* bit 1 Flash Cycle Error */
66 u16 dael:1; /* bit 2 Direct Access error Log */
67 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
68 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
69 u16 reserved1:2; /* bit 13:6 Reserved */
70 u16 reserved2:6; /* bit 13:6 Reserved */
71 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
72 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
77 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
78 /* Offset 06h FLCTL */
79 union ich8_hws_flash_ctrl {
81 u16 flcgo:1; /* 0 Flash Cycle Go */
82 u16 flcycle:2; /* 2:1 Flash Cycle */
83 u16 reserved:5; /* 7:3 Reserved */
84 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
85 u16 flockdn:6; /* 15:10 Reserved */
90 /* ICH Flash Region Access Permissions */
91 union ich8_hws_flash_regacc {
93 u32 grra:8; /* 0:7 GbE region Read Access */
94 u32 grwa:8; /* 8:15 GbE region Write Access */
95 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
96 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
101 /* ICH Flash Protected Region */
102 union ich8_flash_protected_range {
104 u32 base:13; /* 0:12 Protected Range Base */
105 u32 reserved1:2; /* 13:14 Reserved */
106 u32 rpe:1; /* 15 Read Protection Enable */
107 u32 limit:13; /* 16:28 Protected Range Limit */
108 u32 reserved2:2; /* 29:30 Reserved */
109 u32 wpe:1; /* 31 Write Protection Enable */
114 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
115 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
116 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
117 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
118 u32 offset, u8 byte);
119 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
121 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
123 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
125 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
126 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
127 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
128 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
129 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
130 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
131 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
132 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
133 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
134 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
135 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
136 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
137 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
138 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
139 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
140 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
141 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
142 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
143 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
144 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
145 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
147 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
149 return readw(hw->flash_address + reg);
152 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
154 return readl(hw->flash_address + reg);
157 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
159 writew(val, hw->flash_address + reg);
162 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
164 writel(val, hw->flash_address + reg);
167 #define er16flash(reg) __er16flash(hw, (reg))
168 #define er32flash(reg) __er32flash(hw, (reg))
169 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
170 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
173 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
174 * @hw: pointer to the HW structure
176 * Test access to the PHY registers by reading the PHY ID registers. If
177 * the PHY ID is already known (e.g. resume path) compare it with known ID,
178 * otherwise assume the read PHY ID is correct if it is valid.
180 * Assumes the sw/fw/hw semaphore is already acquired.
182 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
190 for (retry_count = 0; retry_count < 2; retry_count++) {
191 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
192 if (ret_val || (phy_reg == 0xFFFF))
194 phy_id = (u32)(phy_reg << 16);
196 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
197 if (ret_val || (phy_reg == 0xFFFF)) {
201 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
206 if (hw->phy.id == phy_id)
210 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
214 /* In case the PHY needs to be in mdio slow mode,
215 * set slow mode and try to get the PHY id again.
217 hw->phy.ops.release(hw);
218 ret_val = e1000_set_mdio_slow_mode_hv(hw);
220 ret_val = e1000e_get_phy_id(hw);
221 hw->phy.ops.acquire(hw);
226 if (hw->mac.type == e1000_pch_lpt) {
227 /* Unforce SMBus mode in PHY */
228 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
229 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
230 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
232 /* Unforce SMBus mode in MAC */
233 mac_reg = er32(CTRL_EXT);
234 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
235 ew32(CTRL_EXT, mac_reg);
242 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
243 * @hw: pointer to the HW structure
245 * Workarounds/flow necessary for PHY initialization during driver load
248 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
250 u32 mac_reg, fwsm = er32(FWSM);
253 /* Gate automatic PHY configuration by hardware on managed and
254 * non-managed 82579 and newer adapters.
256 e1000_gate_hw_phy_config_ich8lan(hw, true);
258 ret_val = hw->phy.ops.acquire(hw);
260 e_dbg("Failed to initialize PHY flow\n");
264 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
265 * inaccessible and resetting the PHY is not blocked, toggle the
266 * LANPHYPC Value bit to force the interconnect to PCIe mode.
268 switch (hw->mac.type) {
270 if (e1000_phy_is_accessible_pchlan(hw))
273 /* Before toggling LANPHYPC, see if PHY is accessible by
274 * forcing MAC to SMBus mode first.
276 mac_reg = er32(CTRL_EXT);
277 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
278 ew32(CTRL_EXT, mac_reg);
280 /* Wait 50 milliseconds for MAC to finish any retries
281 * that it might be trying to perform from previous
282 * attempts to acknowledge any phy read requests.
288 if (e1000_phy_is_accessible_pchlan(hw))
293 if ((hw->mac.type == e1000_pchlan) &&
294 (fwsm & E1000_ICH_FWSM_FW_VALID))
297 if (hw->phy.ops.check_reset_block(hw)) {
298 e_dbg("Required LANPHYPC toggle blocked by ME\n");
299 ret_val = -E1000_ERR_PHY;
303 e_dbg("Toggling LANPHYPC\n");
305 /* Set Phy Config Counter to 50msec */
306 mac_reg = er32(FEXTNVM3);
307 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
308 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
309 ew32(FEXTNVM3, mac_reg);
311 /* Toggle LANPHYPC Value bit */
312 mac_reg = er32(CTRL);
313 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
314 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
317 usleep_range(10, 20);
318 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
321 if (hw->mac.type < e1000_pch_lpt) {
326 usleep_range(5000, 10000);
327 } while (!(er32(CTRL_EXT) &
328 E1000_CTRL_EXT_LPCD) && count--);
329 usleep_range(30000, 60000);
330 if (e1000_phy_is_accessible_pchlan(hw))
333 /* Toggling LANPHYPC brings the PHY out of SMBus mode
334 * so ensure that the MAC is also out of SMBus mode
336 mac_reg = er32(CTRL_EXT);
337 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
338 ew32(CTRL_EXT, mac_reg);
340 if (e1000_phy_is_accessible_pchlan(hw))
343 ret_val = -E1000_ERR_PHY;
350 hw->phy.ops.release(hw);
352 /* Reset the PHY before any access to it. Doing so, ensures
353 * that the PHY is in a known good state before we read/write
354 * PHY registers. The generic reset is sufficient here,
355 * because we haven't determined the PHY type yet.
357 ret_val = e1000e_phy_hw_reset_generic(hw);
361 /* Ungate automatic PHY configuration on non-managed 82579 */
362 if ((hw->mac.type == e1000_pch2lan) &&
363 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
364 usleep_range(10000, 20000);
365 e1000_gate_hw_phy_config_ich8lan(hw, false);
372 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
373 * @hw: pointer to the HW structure
375 * Initialize family-specific PHY parameters and function pointers.
377 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
379 struct e1000_phy_info *phy = &hw->phy;
383 phy->reset_delay_us = 100;
385 phy->ops.set_page = e1000_set_page_igp;
386 phy->ops.read_reg = e1000_read_phy_reg_hv;
387 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
388 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
389 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
390 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
391 phy->ops.write_reg = e1000_write_phy_reg_hv;
392 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
393 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
394 phy->ops.power_up = e1000_power_up_phy_copper;
395 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
396 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
398 phy->id = e1000_phy_unknown;
400 ret_val = e1000_init_phy_workarounds_pchlan(hw);
404 if (phy->id == e1000_phy_unknown)
405 switch (hw->mac.type) {
407 ret_val = e1000e_get_phy_id(hw);
410 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
415 /* In case the PHY needs to be in mdio slow mode,
416 * set slow mode and try to get the PHY id again.
418 ret_val = e1000_set_mdio_slow_mode_hv(hw);
421 ret_val = e1000e_get_phy_id(hw);
426 phy->type = e1000e_get_phy_type_from_id(phy->id);
429 case e1000_phy_82577:
430 case e1000_phy_82579:
432 phy->ops.check_polarity = e1000_check_polarity_82577;
433 phy->ops.force_speed_duplex =
434 e1000_phy_force_speed_duplex_82577;
435 phy->ops.get_cable_length = e1000_get_cable_length_82577;
436 phy->ops.get_info = e1000_get_phy_info_82577;
437 phy->ops.commit = e1000e_phy_sw_reset;
439 case e1000_phy_82578:
440 phy->ops.check_polarity = e1000_check_polarity_m88;
441 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
442 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
443 phy->ops.get_info = e1000e_get_phy_info_m88;
446 ret_val = -E1000_ERR_PHY;
454 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
455 * @hw: pointer to the HW structure
457 * Initialize family-specific PHY parameters and function pointers.
459 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
461 struct e1000_phy_info *phy = &hw->phy;
466 phy->reset_delay_us = 100;
468 phy->ops.power_up = e1000_power_up_phy_copper;
469 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
471 /* We may need to do this twice - once for IGP and if that fails,
472 * we'll set BM func pointers and try again
474 ret_val = e1000e_determine_phy_address(hw);
476 phy->ops.write_reg = e1000e_write_phy_reg_bm;
477 phy->ops.read_reg = e1000e_read_phy_reg_bm;
478 ret_val = e1000e_determine_phy_address(hw);
480 e_dbg("Cannot determine PHY addr. Erroring out\n");
486 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
488 usleep_range(1000, 2000);
489 ret_val = e1000e_get_phy_id(hw);
496 case IGP03E1000_E_PHY_ID:
497 phy->type = e1000_phy_igp_3;
498 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
499 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
500 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
501 phy->ops.get_info = e1000e_get_phy_info_igp;
502 phy->ops.check_polarity = e1000_check_polarity_igp;
503 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
506 case IFE_PLUS_E_PHY_ID:
508 phy->type = e1000_phy_ife;
509 phy->autoneg_mask = E1000_ALL_NOT_GIG;
510 phy->ops.get_info = e1000_get_phy_info_ife;
511 phy->ops.check_polarity = e1000_check_polarity_ife;
512 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
514 case BME1000_E_PHY_ID:
515 phy->type = e1000_phy_bm;
516 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
517 phy->ops.read_reg = e1000e_read_phy_reg_bm;
518 phy->ops.write_reg = e1000e_write_phy_reg_bm;
519 phy->ops.commit = e1000e_phy_sw_reset;
520 phy->ops.get_info = e1000e_get_phy_info_m88;
521 phy->ops.check_polarity = e1000_check_polarity_m88;
522 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
525 return -E1000_ERR_PHY;
533 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
534 * @hw: pointer to the HW structure
536 * Initialize family-specific NVM parameters and function
539 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
541 struct e1000_nvm_info *nvm = &hw->nvm;
542 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
543 u32 gfpreg, sector_base_addr, sector_end_addr;
546 /* Can't read flash registers if the register set isn't mapped. */
547 if (!hw->flash_address) {
548 e_dbg("ERROR: Flash registers not mapped\n");
549 return -E1000_ERR_CONFIG;
552 nvm->type = e1000_nvm_flash_sw;
554 gfpreg = er32flash(ICH_FLASH_GFPREG);
556 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
557 * Add 1 to sector_end_addr since this sector is included in
560 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
561 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
563 /* flash_base_addr is byte-aligned */
564 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
566 /* find total size of the NVM, then cut in half since the total
567 * size represents two separate NVM banks.
569 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
570 << FLASH_SECTOR_ADDR_SHIFT);
571 nvm->flash_bank_size /= 2;
572 /* Adjust to word count */
573 nvm->flash_bank_size /= sizeof(u16);
575 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
577 /* Clear shadow ram */
578 for (i = 0; i < nvm->word_size; i++) {
579 dev_spec->shadow_ram[i].modified = false;
580 dev_spec->shadow_ram[i].value = 0xFFFF;
587 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
588 * @hw: pointer to the HW structure
590 * Initialize family-specific MAC parameters and function
593 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
595 struct e1000_mac_info *mac = &hw->mac;
597 /* Set media type function pointer */
598 hw->phy.media_type = e1000_media_type_copper;
600 /* Set mta register count */
601 mac->mta_reg_count = 32;
602 /* Set rar entry count */
603 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
604 if (mac->type == e1000_ich8lan)
605 mac->rar_entry_count--;
607 mac->has_fwsm = true;
608 /* ARC subsystem not supported */
609 mac->arc_subsystem_valid = false;
610 /* Adaptive IFS supported */
611 mac->adaptive_ifs = true;
613 /* LED and other operations */
618 /* check management mode */
619 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
621 mac->ops.id_led_init = e1000e_id_led_init_generic;
623 mac->ops.blink_led = e1000e_blink_led_generic;
625 mac->ops.setup_led = e1000e_setup_led_generic;
627 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
628 /* turn on/off LED */
629 mac->ops.led_on = e1000_led_on_ich8lan;
630 mac->ops.led_off = e1000_led_off_ich8lan;
633 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
634 mac->ops.rar_set = e1000_rar_set_pch2lan;
638 /* check management mode */
639 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
641 mac->ops.id_led_init = e1000_id_led_init_pchlan;
643 mac->ops.setup_led = e1000_setup_led_pchlan;
645 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
646 /* turn on/off LED */
647 mac->ops.led_on = e1000_led_on_pchlan;
648 mac->ops.led_off = e1000_led_off_pchlan;
654 if (mac->type == e1000_pch_lpt) {
655 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
656 mac->ops.rar_set = e1000_rar_set_pch_lpt;
657 mac->ops.setup_physical_interface =
658 e1000_setup_copper_link_pch_lpt;
661 /* Enable PCS Lock-loss workaround for ICH8 */
662 if (mac->type == e1000_ich8lan)
663 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
669 * __e1000_access_emi_reg_locked - Read/write EMI register
670 * @hw: pointer to the HW structure
671 * @addr: EMI address to program
672 * @data: pointer to value to read/write from/to the EMI address
673 * @read: boolean flag to indicate read or write
675 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
677 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
678 u16 *data, bool read)
682 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
687 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
689 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
695 * e1000_read_emi_reg_locked - Read Extended Management Interface register
696 * @hw: pointer to the HW structure
697 * @addr: EMI address to program
698 * @data: value to be read from the EMI address
700 * Assumes the SW/FW/HW Semaphore is already acquired.
702 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
704 return __e1000_access_emi_reg_locked(hw, addr, data, true);
708 * e1000_write_emi_reg_locked - Write Extended Management Interface register
709 * @hw: pointer to the HW structure
710 * @addr: EMI address to program
711 * @data: value to be written to the EMI address
713 * Assumes the SW/FW/HW Semaphore is already acquired.
715 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
717 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
721 * e1000_set_eee_pchlan - Enable/disable EEE support
722 * @hw: pointer to the HW structure
724 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
725 * the link and the EEE capabilities of the link partner. The LPI Control
726 * register bits will remain set only if/when link is up.
728 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
730 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
732 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
734 switch (hw->phy.type) {
735 case e1000_phy_82579:
736 lpa = I82579_EEE_LP_ABILITY;
737 pcs_status = I82579_EEE_PCS_STATUS;
738 adv_addr = I82579_EEE_ADVERTISEMENT;
741 lpa = I217_EEE_LP_ABILITY;
742 pcs_status = I217_EEE_PCS_STATUS;
743 adv_addr = I217_EEE_ADVERTISEMENT;
749 ret_val = hw->phy.ops.acquire(hw);
753 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
757 /* Clear bits that enable EEE in various speeds */
758 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
760 /* Enable EEE if not disabled by user */
761 if (!dev_spec->eee_disable) {
762 /* Save off link partner's EEE ability */
763 ret_val = e1000_read_emi_reg_locked(hw, lpa,
764 &dev_spec->eee_lp_ability);
768 /* Read EEE advertisement */
769 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
773 /* Enable EEE only for speeds in which the link partner is
774 * EEE capable and for which we advertise EEE.
776 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
777 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
779 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
780 e1e_rphy_locked(hw, MII_LPA, &data);
781 if (data & LPA_100FULL)
782 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
784 /* EEE is not supported in 100Half, so ignore
785 * partner's EEE in 100 ability if full-duplex
788 dev_spec->eee_lp_ability &=
789 ~I82579_EEE_100_SUPPORTED;
793 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
794 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
798 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
800 hw->phy.ops.release(hw);
806 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
807 * @hw: pointer to the HW structure
808 * @link: link up bool flag
810 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
811 * preventing further DMA write requests. Workaround the issue by disabling
812 * the de-assertion of the clock request when in 1Gpbs mode.
813 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
814 * speeds in order to avoid Tx hangs.
816 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
818 u32 fextnvm6 = er32(FEXTNVM6);
819 u32 status = er32(STATUS);
823 if (link && (status & E1000_STATUS_SPEED_1000)) {
824 ret_val = hw->phy.ops.acquire(hw);
829 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
835 e1000e_write_kmrn_reg_locked(hw,
836 E1000_KMRNCTRLSTA_K1_CONFIG,
838 ~E1000_KMRNCTRLSTA_K1_ENABLE);
842 usleep_range(10, 20);
844 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
847 e1000e_write_kmrn_reg_locked(hw,
848 E1000_KMRNCTRLSTA_K1_CONFIG,
851 hw->phy.ops.release(hw);
853 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
854 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
856 if (!link || ((status & E1000_STATUS_SPEED_100) &&
857 (status & E1000_STATUS_FD)))
858 goto update_fextnvm6;
860 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®);
864 /* Clear link status transmit timeout */
865 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
867 if (status & E1000_STATUS_SPEED_100) {
868 /* Set inband Tx timeout to 5x10us for 100Half */
869 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
871 /* Do not extend the K1 entry latency for 100Half */
872 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
874 /* Set inband Tx timeout to 50x10us for 10Full/Half */
876 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
878 /* Extend the K1 entry latency for 10 Mbps */
879 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
882 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
887 ew32(FEXTNVM6, fextnvm6);
894 * e1000_platform_pm_pch_lpt - Set platform power management values
895 * @hw: pointer to the HW structure
896 * @link: bool indicating link status
898 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
899 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
900 * when link is up (which must not exceed the maximum latency supported
901 * by the platform), otherwise specify there is no LTR requirement.
902 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
903 * latencies in the LTR Extended Capability Structure in the PCIe Extended
904 * Capability register set, on this device LTR is set by writing the
905 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
906 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
907 * message to the PMC.
909 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
911 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
912 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
913 u16 lat_enc = 0; /* latency encoded */
916 u16 speed, duplex, scale = 0;
917 u16 max_snoop, max_nosnoop;
918 u16 max_ltr_enc; /* max LTR latency encoded */
919 s64 lat_ns; /* latency (ns) */
923 if (!hw->adapter->max_frame_size) {
924 e_dbg("max_frame_size not set.\n");
925 return -E1000_ERR_CONFIG;
928 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
930 e_dbg("Speed not set.\n");
931 return -E1000_ERR_CONFIG;
934 /* Rx Packet Buffer Allocation size (KB) */
935 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
937 /* Determine the maximum latency tolerated by the device.
939 * Per the PCIe spec, the tolerated latencies are encoded as
940 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
941 * a 10-bit value (0-1023) to provide a range from 1 ns to
942 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
943 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
945 lat_ns = ((s64)rxa * 1024 -
946 (2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000;
950 do_div(lat_ns, speed);
953 while (value > PCI_LTR_VALUE_MASK) {
955 value = DIV_ROUND_UP(value, (1 << 5));
957 if (scale > E1000_LTRV_SCALE_MAX) {
958 e_dbg("Invalid LTR latency scale %d\n", scale);
959 return -E1000_ERR_CONFIG;
961 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
963 /* Determine the maximum latency tolerated by the platform */
964 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
966 pci_read_config_word(hw->adapter->pdev,
967 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
968 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
970 if (lat_enc > max_ltr_enc)
971 lat_enc = max_ltr_enc;
974 /* Set Snoop and No-Snoop latencies the same */
975 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
982 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
983 * @hw: pointer to the HW structure
985 * Checks to see of the link status of the hardware has changed. If a
986 * change in link status has been detected, then we read the PHY registers
987 * to get the current speed/duplex if link exists.
989 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
991 struct e1000_mac_info *mac = &hw->mac;
996 /* We only want to go out to the PHY registers to see if Auto-Neg
997 * has completed and/or if our link status has changed. The
998 * get_link_status flag is set upon receiving a Link Status
999 * Change or Rx Sequence Error interrupt.
1001 if (!mac->get_link_status)
1004 /* First we want to see if the MII Status Register reports
1005 * link. If so, then we want to get the current speed/duplex
1008 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1012 if (hw->mac.type == e1000_pchlan) {
1013 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1018 /* When connected at 10Mbps half-duplex, 82579 parts are excessively
1019 * aggressive resulting in many collisions. To avoid this, increase
1020 * the IPG and reduce Rx latency in the PHY.
1022 if ((hw->mac.type == e1000_pch2lan) && link) {
1025 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1027 reg &= ~E1000_TIPG_IPGT_MASK;
1031 /* Reduce Rx latency in analog PHY */
1032 ret_val = hw->phy.ops.acquire(hw);
1037 e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0);
1039 hw->phy.ops.release(hw);
1046 /* Work-around I218 hang issue */
1047 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1048 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1049 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1050 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1051 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1056 if (hw->mac.type == e1000_pch_lpt) {
1057 /* Set platform power management values for
1058 * Latency Tolerance Reporting (LTR)
1060 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1065 /* Clear link partner's EEE ability */
1066 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1069 return 0; /* No link detected */
1071 mac->get_link_status = false;
1073 switch (hw->mac.type) {
1075 ret_val = e1000_k1_workaround_lv(hw);
1080 if (hw->phy.type == e1000_phy_82578) {
1081 ret_val = e1000_link_stall_workaround_hv(hw);
1086 /* Workaround for PCHx parts in half-duplex:
1087 * Set the number of preambles removed from the packet
1088 * when it is passed from the PHY to the MAC to prevent
1089 * the MAC from misinterpreting the packet type.
1091 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1092 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1094 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1095 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1097 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1103 /* Check if there was DownShift, must be checked
1104 * immediately after link-up
1106 e1000e_check_downshift(hw);
1108 /* Enable/Disable EEE after link up */
1109 ret_val = e1000_set_eee_pchlan(hw);
1113 /* If we are forcing speed/duplex, then we simply return since
1114 * we have already determined whether we have link or not.
1117 return -E1000_ERR_CONFIG;
1119 /* Auto-Neg is enabled. Auto Speed Detection takes care
1120 * of MAC speed/duplex configuration. So we only need to
1121 * configure Collision Distance in the MAC.
1123 mac->ops.config_collision_dist(hw);
1125 /* Configure Flow Control now that Auto-Neg has completed.
1126 * First, we need to restore the desired flow control
1127 * settings because we may have had to re-autoneg with a
1128 * different link partner.
1130 ret_val = e1000e_config_fc_after_link_up(hw);
1132 e_dbg("Error configuring flow control\n");
1137 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1139 struct e1000_hw *hw = &adapter->hw;
1142 rc = e1000_init_mac_params_ich8lan(hw);
1146 rc = e1000_init_nvm_params_ich8lan(hw);
1150 switch (hw->mac.type) {
1153 case e1000_ich10lan:
1154 rc = e1000_init_phy_params_ich8lan(hw);
1159 rc = e1000_init_phy_params_pchlan(hw);
1167 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1168 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1170 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1171 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1172 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1173 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1174 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
1176 hw->mac.ops.blink_led = NULL;
1179 if ((adapter->hw.mac.type == e1000_ich8lan) &&
1180 (adapter->hw.phy.type != e1000_phy_ife))
1181 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1183 /* Enable workaround for 82579 w/ ME enabled */
1184 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1185 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1186 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1191 static DEFINE_MUTEX(nvm_mutex);
1194 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1195 * @hw: pointer to the HW structure
1197 * Acquires the mutex for performing NVM operations.
1199 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1201 mutex_lock(&nvm_mutex);
1207 * e1000_release_nvm_ich8lan - Release NVM mutex
1208 * @hw: pointer to the HW structure
1210 * Releases the mutex used while performing NVM operations.
1212 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1214 mutex_unlock(&nvm_mutex);
1218 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1219 * @hw: pointer to the HW structure
1221 * Acquires the software control flag for performing PHY and select
1224 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1226 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1229 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1230 &hw->adapter->state)) {
1231 e_dbg("contention for Phy access\n");
1232 return -E1000_ERR_PHY;
1236 extcnf_ctrl = er32(EXTCNF_CTRL);
1237 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1245 e_dbg("SW has already locked the resource.\n");
1246 ret_val = -E1000_ERR_CONFIG;
1250 timeout = SW_FLAG_TIMEOUT;
1252 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1253 ew32(EXTCNF_CTRL, extcnf_ctrl);
1256 extcnf_ctrl = er32(EXTCNF_CTRL);
1257 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1265 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1266 er32(FWSM), extcnf_ctrl);
1267 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1268 ew32(EXTCNF_CTRL, extcnf_ctrl);
1269 ret_val = -E1000_ERR_CONFIG;
1275 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1281 * e1000_release_swflag_ich8lan - Release software control flag
1282 * @hw: pointer to the HW structure
1284 * Releases the software control flag for performing PHY and select
1287 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1291 extcnf_ctrl = er32(EXTCNF_CTRL);
1293 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1294 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1295 ew32(EXTCNF_CTRL, extcnf_ctrl);
1297 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1300 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1304 * e1000_check_mng_mode_ich8lan - Checks management mode
1305 * @hw: pointer to the HW structure
1307 * This checks if the adapter has any manageability enabled.
1308 * This is a function pointer entry point only called by read/write
1309 * routines for the PHY and NVM parts.
1311 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1316 return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
1317 ((fwsm & E1000_FWSM_MODE_MASK) ==
1318 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
1322 * e1000_check_mng_mode_pchlan - Checks management mode
1323 * @hw: pointer to the HW structure
1325 * This checks if the adapter has iAMT enabled.
1326 * This is a function pointer entry point only called by read/write
1327 * routines for the PHY and NVM parts.
1329 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1334 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1335 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1339 * e1000_rar_set_pch2lan - Set receive address register
1340 * @hw: pointer to the HW structure
1341 * @addr: pointer to the receive address
1342 * @index: receive address array register
1344 * Sets the receive address array register at index to the address passed
1345 * in by addr. For 82579, RAR[0] is the base address register that is to
1346 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1347 * Use SHRA[0-3] in place of those reserved for ME.
1349 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1351 u32 rar_low, rar_high;
1353 /* HW expects these in little endian so we reverse the byte order
1354 * from network order (big endian) to little endian
1356 rar_low = ((u32)addr[0] |
1357 ((u32)addr[1] << 8) |
1358 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1360 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1362 /* If MAC address zero, no need to set the AV bit */
1363 if (rar_low || rar_high)
1364 rar_high |= E1000_RAH_AV;
1367 ew32(RAL(index), rar_low);
1369 ew32(RAH(index), rar_high);
1374 if (index < hw->mac.rar_entry_count) {
1377 ret_val = e1000_acquire_swflag_ich8lan(hw);
1381 ew32(SHRAL(index - 1), rar_low);
1383 ew32(SHRAH(index - 1), rar_high);
1386 e1000_release_swflag_ich8lan(hw);
1388 /* verify the register updates */
1389 if ((er32(SHRAL(index - 1)) == rar_low) &&
1390 (er32(SHRAH(index - 1)) == rar_high))
1393 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1394 (index - 1), er32(FWSM));
1398 e_dbg("Failed to write receive address at index %d\n", index);
1402 * e1000_rar_set_pch_lpt - Set receive address registers
1403 * @hw: pointer to the HW structure
1404 * @addr: pointer to the receive address
1405 * @index: receive address array register
1407 * Sets the receive address register array at index to the address passed
1408 * in by addr. For LPT, RAR[0] is the base address register that is to
1409 * contain the MAC address. SHRA[0-10] are the shared receive address
1410 * registers that are shared between the Host and manageability engine (ME).
1412 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1414 u32 rar_low, rar_high;
1417 /* HW expects these in little endian so we reverse the byte order
1418 * from network order (big endian) to little endian
1420 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1421 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1423 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1425 /* If MAC address zero, no need to set the AV bit */
1426 if (rar_low || rar_high)
1427 rar_high |= E1000_RAH_AV;
1430 ew32(RAL(index), rar_low);
1432 ew32(RAH(index), rar_high);
1437 /* The manageability engine (ME) can lock certain SHRAR registers that
1438 * it is using - those registers are unavailable for use.
1440 if (index < hw->mac.rar_entry_count) {
1441 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1442 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1444 /* Check if all SHRAR registers are locked */
1448 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1451 ret_val = e1000_acquire_swflag_ich8lan(hw);
1456 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1458 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1461 e1000_release_swflag_ich8lan(hw);
1463 /* verify the register updates */
1464 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1465 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1471 e_dbg("Failed to write receive address at index %d\n", index);
1475 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1476 * @hw: pointer to the HW structure
1478 * Checks if firmware is blocking the reset of the PHY.
1479 * This is a function pointer entry point only called by
1482 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1488 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
1492 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1493 * @hw: pointer to the HW structure
1495 * Assumes semaphore already acquired.
1498 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1501 u32 strap = er32(STRAP);
1502 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1503 E1000_STRAP_SMT_FREQ_SHIFT;
1506 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1508 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1512 phy_data &= ~HV_SMB_ADDR_MASK;
1513 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1514 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1516 if (hw->phy.type == e1000_phy_i217) {
1517 /* Restore SMBus frequency */
1519 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1520 phy_data |= (freq & (1 << 0)) <<
1521 HV_SMB_ADDR_FREQ_LOW_SHIFT;
1522 phy_data |= (freq & (1 << 1)) <<
1523 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1525 e_dbg("Unsupported SMB frequency in PHY\n");
1529 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1533 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1534 * @hw: pointer to the HW structure
1536 * SW should configure the LCD from the NVM extended configuration region
1537 * as a workaround for certain parts.
1539 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1541 struct e1000_phy_info *phy = &hw->phy;
1542 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1544 u16 word_addr, reg_data, reg_addr, phy_page = 0;
1546 /* Initialize the PHY from the NVM on ICH platforms. This
1547 * is needed due to an issue where the NVM configuration is
1548 * not properly autoloaded after power transitions.
1549 * Therefore, after each PHY reset, we will load the
1550 * configuration data out of the NVM manually.
1552 switch (hw->mac.type) {
1554 if (phy->type != e1000_phy_igp_3)
1557 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1558 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1559 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1566 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1572 ret_val = hw->phy.ops.acquire(hw);
1576 data = er32(FEXTNVM);
1577 if (!(data & sw_cfg_mask))
1580 /* Make sure HW does not configure LCD from PHY
1581 * extended configuration before SW configuration
1583 data = er32(EXTCNF_CTRL);
1584 if ((hw->mac.type < e1000_pch2lan) &&
1585 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1588 cnf_size = er32(EXTCNF_SIZE);
1589 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1590 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1594 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1595 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1597 if (((hw->mac.type == e1000_pchlan) &&
1598 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1599 (hw->mac.type > e1000_pchlan)) {
1600 /* HW configures the SMBus address and LEDs when the
1601 * OEM and LCD Write Enable bits are set in the NVM.
1602 * When both NVM bits are cleared, SW will configure
1605 ret_val = e1000_write_smbus_addr(hw);
1609 data = er32(LEDCTL);
1610 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1616 /* Configure LCD from extended configuration region. */
1618 /* cnf_base_addr is in DWORD */
1619 word_addr = (u16)(cnf_base_addr << 1);
1621 for (i = 0; i < cnf_size; i++) {
1622 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data);
1626 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1631 /* Save off the PHY page for future writes. */
1632 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1633 phy_page = reg_data;
1637 reg_addr &= PHY_REG_MASK;
1638 reg_addr |= phy_page;
1640 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
1646 hw->phy.ops.release(hw);
1651 * e1000_k1_gig_workaround_hv - K1 Si workaround
1652 * @hw: pointer to the HW structure
1653 * @link: link up bool flag
1655 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1656 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1657 * If link is down, the function will restore the default K1 setting located
1660 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1664 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1666 if (hw->mac.type != e1000_pchlan)
1669 /* Wrap the whole flow with the sw flag */
1670 ret_val = hw->phy.ops.acquire(hw);
1674 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1676 if (hw->phy.type == e1000_phy_82578) {
1677 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
1682 status_reg &= (BM_CS_STATUS_LINK_UP |
1683 BM_CS_STATUS_RESOLVED |
1684 BM_CS_STATUS_SPEED_MASK);
1686 if (status_reg == (BM_CS_STATUS_LINK_UP |
1687 BM_CS_STATUS_RESOLVED |
1688 BM_CS_STATUS_SPEED_1000))
1692 if (hw->phy.type == e1000_phy_82577) {
1693 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
1697 status_reg &= (HV_M_STATUS_LINK_UP |
1698 HV_M_STATUS_AUTONEG_COMPLETE |
1699 HV_M_STATUS_SPEED_MASK);
1701 if (status_reg == (HV_M_STATUS_LINK_UP |
1702 HV_M_STATUS_AUTONEG_COMPLETE |
1703 HV_M_STATUS_SPEED_1000))
1707 /* Link stall fix for link up */
1708 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
1713 /* Link stall fix for link down */
1714 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
1719 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1722 hw->phy.ops.release(hw);
1728 * e1000_configure_k1_ich8lan - Configure K1 power state
1729 * @hw: pointer to the HW structure
1730 * @enable: K1 state to configure
1732 * Configure the K1 power state based on the provided parameter.
1733 * Assumes semaphore already acquired.
1735 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1737 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1745 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1751 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1753 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1755 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1760 usleep_range(20, 40);
1761 ctrl_ext = er32(CTRL_EXT);
1762 ctrl_reg = er32(CTRL);
1764 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1765 reg |= E1000_CTRL_FRCSPD;
1768 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1770 usleep_range(20, 40);
1771 ew32(CTRL, ctrl_reg);
1772 ew32(CTRL_EXT, ctrl_ext);
1774 usleep_range(20, 40);
1780 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1781 * @hw: pointer to the HW structure
1782 * @d0_state: boolean if entering d0 or d3 device state
1784 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1785 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1786 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1788 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1794 if (hw->mac.type < e1000_pchlan)
1797 ret_val = hw->phy.ops.acquire(hw);
1801 if (hw->mac.type == e1000_pchlan) {
1802 mac_reg = er32(EXTCNF_CTRL);
1803 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1807 mac_reg = er32(FEXTNVM);
1808 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1811 mac_reg = er32(PHY_CTRL);
1813 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
1817 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1820 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1821 oem_reg |= HV_OEM_BITS_GBE_DIS;
1823 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1824 oem_reg |= HV_OEM_BITS_LPLU;
1826 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1827 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1828 oem_reg |= HV_OEM_BITS_GBE_DIS;
1830 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1831 E1000_PHY_CTRL_NOND0A_LPLU))
1832 oem_reg |= HV_OEM_BITS_LPLU;
1835 /* Set Restart auto-neg to activate the bits */
1836 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
1837 !hw->phy.ops.check_reset_block(hw))
1838 oem_reg |= HV_OEM_BITS_RESTART_AN;
1840 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
1843 hw->phy.ops.release(hw);
1849 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1850 * @hw: pointer to the HW structure
1852 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1857 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1861 data |= HV_KMRN_MDIO_SLOW;
1863 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1869 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1870 * done after every PHY reset.
1872 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1877 if (hw->mac.type != e1000_pchlan)
1880 /* Set MDIO slow mode before any other MDIO access */
1881 if (hw->phy.type == e1000_phy_82577) {
1882 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1887 if (((hw->phy.type == e1000_phy_82577) &&
1888 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1889 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1890 /* Disable generation of early preamble */
1891 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1895 /* Preamble tuning for SSC */
1896 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1901 if (hw->phy.type == e1000_phy_82578) {
1902 /* Return registers to default by doing a soft reset then
1903 * writing 0x3140 to the control register.
1905 if (hw->phy.revision < 2) {
1906 e1000e_phy_sw_reset(hw);
1907 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
1912 ret_val = hw->phy.ops.acquire(hw);
1917 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1918 hw->phy.ops.release(hw);
1922 /* Configure the K1 Si workaround during phy reset assuming there is
1923 * link so that it disables K1 if link is in 1Gbps.
1925 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1929 /* Workaround for link disconnects on a busy hub in half duplex */
1930 ret_val = hw->phy.ops.acquire(hw);
1933 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1936 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
1940 /* set MSE higher to enable link to stay up when noise is high */
1941 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
1943 hw->phy.ops.release(hw);
1949 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1950 * @hw: pointer to the HW structure
1952 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1958 ret_val = hw->phy.ops.acquire(hw);
1961 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1965 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1966 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1967 mac_reg = er32(RAL(i));
1968 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1969 (u16)(mac_reg & 0xFFFF));
1970 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1971 (u16)((mac_reg >> 16) & 0xFFFF));
1973 mac_reg = er32(RAH(i));
1974 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1975 (u16)(mac_reg & 0xFFFF));
1976 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1977 (u16)((mac_reg & E1000_RAH_AV)
1981 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1984 hw->phy.ops.release(hw);
1988 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1990 * @hw: pointer to the HW structure
1991 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1993 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2000 if (hw->mac.type < e1000_pch2lan)
2003 /* disable Rx path while enabling/disabling workaround */
2004 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2005 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
2010 /* Write Rx addresses (rar_entry_count for RAL/H, +4 for
2011 * SHRAL/H) and initial CRC values to the MAC
2013 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
2014 u8 mac_addr[ETH_ALEN] = { 0 };
2015 u32 addr_high, addr_low;
2017 addr_high = er32(RAH(i));
2018 if (!(addr_high & E1000_RAH_AV))
2020 addr_low = er32(RAL(i));
2021 mac_addr[0] = (addr_low & 0xFF);
2022 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2023 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2024 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2025 mac_addr[4] = (addr_high & 0xFF);
2026 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2028 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2031 /* Write Rx addresses to the PHY */
2032 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2034 /* Enable jumbo frame workaround in the MAC */
2035 mac_reg = er32(FFLT_DBG);
2036 mac_reg &= ~(1 << 14);
2037 mac_reg |= (7 << 15);
2038 ew32(FFLT_DBG, mac_reg);
2040 mac_reg = er32(RCTL);
2041 mac_reg |= E1000_RCTL_SECRC;
2042 ew32(RCTL, mac_reg);
2044 ret_val = e1000e_read_kmrn_reg(hw,
2045 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2049 ret_val = e1000e_write_kmrn_reg(hw,
2050 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2054 ret_val = e1000e_read_kmrn_reg(hw,
2055 E1000_KMRNCTRLSTA_HD_CTRL,
2059 data &= ~(0xF << 8);
2061 ret_val = e1000e_write_kmrn_reg(hw,
2062 E1000_KMRNCTRLSTA_HD_CTRL,
2067 /* Enable jumbo frame workaround in the PHY */
2068 e1e_rphy(hw, PHY_REG(769, 23), &data);
2069 data &= ~(0x7F << 5);
2070 data |= (0x37 << 5);
2071 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2074 e1e_rphy(hw, PHY_REG(769, 16), &data);
2076 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2079 e1e_rphy(hw, PHY_REG(776, 20), &data);
2080 data &= ~(0x3FF << 2);
2081 data |= (0x1A << 2);
2082 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2085 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2088 e1e_rphy(hw, HV_PM_CTRL, &data);
2089 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
2093 /* Write MAC register values back to h/w defaults */
2094 mac_reg = er32(FFLT_DBG);
2095 mac_reg &= ~(0xF << 14);
2096 ew32(FFLT_DBG, mac_reg);
2098 mac_reg = er32(RCTL);
2099 mac_reg &= ~E1000_RCTL_SECRC;
2100 ew32(RCTL, mac_reg);
2102 ret_val = e1000e_read_kmrn_reg(hw,
2103 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2107 ret_val = e1000e_write_kmrn_reg(hw,
2108 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2112 ret_val = e1000e_read_kmrn_reg(hw,
2113 E1000_KMRNCTRLSTA_HD_CTRL,
2117 data &= ~(0xF << 8);
2119 ret_val = e1000e_write_kmrn_reg(hw,
2120 E1000_KMRNCTRLSTA_HD_CTRL,
2125 /* Write PHY register values back to h/w defaults */
2126 e1e_rphy(hw, PHY_REG(769, 23), &data);
2127 data &= ~(0x7F << 5);
2128 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2131 e1e_rphy(hw, PHY_REG(769, 16), &data);
2133 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2136 e1e_rphy(hw, PHY_REG(776, 20), &data);
2137 data &= ~(0x3FF << 2);
2139 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2142 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2145 e1e_rphy(hw, HV_PM_CTRL, &data);
2146 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
2151 /* re-enable Rx path after enabling/disabling workaround */
2152 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
2156 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2157 * done after every PHY reset.
2159 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2163 if (hw->mac.type != e1000_pch2lan)
2166 /* Set MDIO slow mode before any other MDIO access */
2167 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2171 ret_val = hw->phy.ops.acquire(hw);
2174 /* set MSE higher to enable link to stay up when noise is high */
2175 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2178 /* drop link after 5 times MSE threshold was reached */
2179 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2181 hw->phy.ops.release(hw);
2187 * e1000_k1_gig_workaround_lv - K1 Si workaround
2188 * @hw: pointer to the HW structure
2190 * Workaround to set the K1 beacon duration for 82579 parts
2192 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2199 if (hw->mac.type != e1000_pch2lan)
2202 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
2203 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2207 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2208 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2209 mac_reg = er32(FEXTNVM4);
2210 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2212 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
2216 if (status_reg & HV_M_STATUS_SPEED_1000) {
2219 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
2220 phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2221 /* LV 1G Packet drop issue wa */
2222 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2225 pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
2226 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2230 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2231 phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2233 ew32(FEXTNVM4, mac_reg);
2234 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
2241 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2242 * @hw: pointer to the HW structure
2243 * @gate: boolean set to true to gate, false to ungate
2245 * Gate/ungate the automatic PHY configuration via hardware; perform
2246 * the configuration via software instead.
2248 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2252 if (hw->mac.type < e1000_pch2lan)
2255 extcnf_ctrl = er32(EXTCNF_CTRL);
2258 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2260 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2262 ew32(EXTCNF_CTRL, extcnf_ctrl);
2266 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2267 * @hw: pointer to the HW structure
2269 * Check the appropriate indication the MAC has finished configuring the
2270 * PHY after a software reset.
2272 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2274 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2276 /* Wait for basic configuration completes before proceeding */
2278 data = er32(STATUS);
2279 data &= E1000_STATUS_LAN_INIT_DONE;
2280 usleep_range(100, 200);
2281 } while ((!data) && --loop);
2283 /* If basic configuration is incomplete before the above loop
2284 * count reaches 0, loading the configuration from NVM will
2285 * leave the PHY in a bad state possibly resulting in no link.
2288 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2290 /* Clear the Init Done bit for the next init event */
2291 data = er32(STATUS);
2292 data &= ~E1000_STATUS_LAN_INIT_DONE;
2297 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2298 * @hw: pointer to the HW structure
2300 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2305 if (hw->phy.ops.check_reset_block(hw))
2308 /* Allow time for h/w to get to quiescent state after reset */
2309 usleep_range(10000, 20000);
2311 /* Perform any necessary post-reset workarounds */
2312 switch (hw->mac.type) {
2314 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2319 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2327 /* Clear the host wakeup bit after lcd reset */
2328 if (hw->mac.type >= e1000_pchlan) {
2329 e1e_rphy(hw, BM_PORT_GEN_CFG, ®);
2330 reg &= ~BM_WUC_HOST_WU_BIT;
2331 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2334 /* Configure the LCD with the extended configuration region in NVM */
2335 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2339 /* Configure the LCD with the OEM bits in NVM */
2340 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2342 if (hw->mac.type == e1000_pch2lan) {
2343 /* Ungate automatic PHY configuration on non-managed 82579 */
2344 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2345 usleep_range(10000, 20000);
2346 e1000_gate_hw_phy_config_ich8lan(hw, false);
2349 /* Set EEE LPI Update Timer to 200usec */
2350 ret_val = hw->phy.ops.acquire(hw);
2353 ret_val = e1000_write_emi_reg_locked(hw,
2354 I82579_LPI_UPDATE_TIMER,
2356 hw->phy.ops.release(hw);
2363 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2364 * @hw: pointer to the HW structure
2367 * This is a function pointer entry point called by drivers
2368 * or other shared routines.
2370 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2374 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2375 if ((hw->mac.type == e1000_pch2lan) &&
2376 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2377 e1000_gate_hw_phy_config_ich8lan(hw, true);
2379 ret_val = e1000e_phy_hw_reset_generic(hw);
2383 return e1000_post_phy_reset_ich8lan(hw);
2387 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2388 * @hw: pointer to the HW structure
2389 * @active: true to enable LPLU, false to disable
2391 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2392 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2393 * the phy speed. This function will manually set the LPLU bit and restart
2394 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2395 * since it configures the same bit.
2397 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2402 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2407 oem_reg |= HV_OEM_BITS_LPLU;
2409 oem_reg &= ~HV_OEM_BITS_LPLU;
2411 if (!hw->phy.ops.check_reset_block(hw))
2412 oem_reg |= HV_OEM_BITS_RESTART_AN;
2414 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2418 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2419 * @hw: pointer to the HW structure
2420 * @active: true to enable LPLU, false to disable
2422 * Sets the LPLU D0 state according to the active flag. When
2423 * activating LPLU this function also disables smart speed
2424 * and vice versa. LPLU will not be activated unless the
2425 * device autonegotiation advertisement meets standards of
2426 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2427 * This is a function pointer entry point only called by
2428 * PHY setup routines.
2430 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2432 struct e1000_phy_info *phy = &hw->phy;
2437 if (phy->type == e1000_phy_ife)
2440 phy_ctrl = er32(PHY_CTRL);
2443 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2444 ew32(PHY_CTRL, phy_ctrl);
2446 if (phy->type != e1000_phy_igp_3)
2449 /* Call gig speed drop workaround on LPLU before accessing
2452 if (hw->mac.type == e1000_ich8lan)
2453 e1000e_gig_downshift_workaround_ich8lan(hw);
2455 /* When LPLU is enabled, we should disable SmartSpeed */
2456 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2459 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2460 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2464 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2465 ew32(PHY_CTRL, phy_ctrl);
2467 if (phy->type != e1000_phy_igp_3)
2470 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2471 * during Dx states where the power conservation is most
2472 * important. During driver activity we should enable
2473 * SmartSpeed, so performance is maintained.
2475 if (phy->smart_speed == e1000_smart_speed_on) {
2476 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2481 data |= IGP01E1000_PSCFR_SMART_SPEED;
2482 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2486 } else if (phy->smart_speed == e1000_smart_speed_off) {
2487 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2492 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2493 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2504 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2505 * @hw: pointer to the HW structure
2506 * @active: true to enable LPLU, false to disable
2508 * Sets the LPLU D3 state according to the active flag. When
2509 * activating LPLU this function also disables smart speed
2510 * and vice versa. LPLU will not be activated unless the
2511 * device autonegotiation advertisement meets standards of
2512 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2513 * This is a function pointer entry point only called by
2514 * PHY setup routines.
2516 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2518 struct e1000_phy_info *phy = &hw->phy;
2523 phy_ctrl = er32(PHY_CTRL);
2526 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2527 ew32(PHY_CTRL, phy_ctrl);
2529 if (phy->type != e1000_phy_igp_3)
2532 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2533 * during Dx states where the power conservation is most
2534 * important. During driver activity we should enable
2535 * SmartSpeed, so performance is maintained.
2537 if (phy->smart_speed == e1000_smart_speed_on) {
2538 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2543 data |= IGP01E1000_PSCFR_SMART_SPEED;
2544 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2548 } else if (phy->smart_speed == e1000_smart_speed_off) {
2549 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2554 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2555 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2560 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2561 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2562 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2563 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2564 ew32(PHY_CTRL, phy_ctrl);
2566 if (phy->type != e1000_phy_igp_3)
2569 /* Call gig speed drop workaround on LPLU before accessing
2572 if (hw->mac.type == e1000_ich8lan)
2573 e1000e_gig_downshift_workaround_ich8lan(hw);
2575 /* When LPLU is enabled, we should disable SmartSpeed */
2576 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2580 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2581 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2588 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2589 * @hw: pointer to the HW structure
2590 * @bank: pointer to the variable that returns the active bank
2592 * Reads signature byte from the NVM using the flash access registers.
2593 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2595 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2598 struct e1000_nvm_info *nvm = &hw->nvm;
2599 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2600 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2604 switch (hw->mac.type) {
2608 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2609 E1000_EECD_SEC1VAL_VALID_MASK) {
2610 if (eecd & E1000_EECD_SEC1VAL)
2617 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2620 /* set bank to 0 in case flash read fails */
2624 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2628 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2629 E1000_ICH_NVM_SIG_VALUE) {
2635 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2640 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2641 E1000_ICH_NVM_SIG_VALUE) {
2646 e_dbg("ERROR: No valid NVM bank present\n");
2647 return -E1000_ERR_NVM;
2652 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2653 * @hw: pointer to the HW structure
2654 * @offset: The offset (in bytes) of the word(s) to read.
2655 * @words: Size of data to read in words
2656 * @data: Pointer to the word(s) to read at offset.
2658 * Reads a word(s) from the NVM using the flash access registers.
2660 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2663 struct e1000_nvm_info *nvm = &hw->nvm;
2664 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2670 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2672 e_dbg("nvm parameter(s) out of bounds\n");
2673 ret_val = -E1000_ERR_NVM;
2677 nvm->ops.acquire(hw);
2679 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2681 e_dbg("Could not detect valid bank, assuming bank 0\n");
2685 act_offset = (bank) ? nvm->flash_bank_size : 0;
2686 act_offset += offset;
2689 for (i = 0; i < words; i++) {
2690 if (dev_spec->shadow_ram[offset + i].modified) {
2691 data[i] = dev_spec->shadow_ram[offset + i].value;
2693 ret_val = e1000_read_flash_word_ich8lan(hw,
2702 nvm->ops.release(hw);
2706 e_dbg("NVM read error: %d\n", ret_val);
2712 * e1000_flash_cycle_init_ich8lan - Initialize flash
2713 * @hw: pointer to the HW structure
2715 * This function does initial flash setup so that a new read/write/erase cycle
2718 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2720 union ich8_hws_flash_status hsfsts;
2721 s32 ret_val = -E1000_ERR_NVM;
2723 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2725 /* Check if the flash descriptor is valid */
2726 if (!hsfsts.hsf_status.fldesvalid) {
2727 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
2728 return -E1000_ERR_NVM;
2731 /* Clear FCERR and DAEL in hw status by writing 1 */
2732 hsfsts.hsf_status.flcerr = 1;
2733 hsfsts.hsf_status.dael = 1;
2735 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2737 /* Either we should have a hardware SPI cycle in progress
2738 * bit to check against, in order to start a new cycle or
2739 * FDONE bit should be changed in the hardware so that it
2740 * is 1 after hardware reset, which can then be used as an
2741 * indication whether a cycle is in progress or has been
2745 if (!hsfsts.hsf_status.flcinprog) {
2746 /* There is no cycle running at present,
2747 * so we can start a cycle.
2748 * Begin by setting Flash Cycle Done.
2750 hsfsts.hsf_status.flcdone = 1;
2751 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2756 /* Otherwise poll for sometime so the current
2757 * cycle has a chance to end before giving up.
2759 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2760 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2761 if (!hsfsts.hsf_status.flcinprog) {
2768 /* Successful in waiting for previous cycle to timeout,
2769 * now set the Flash Cycle Done.
2771 hsfsts.hsf_status.flcdone = 1;
2772 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2774 e_dbg("Flash controller busy, cannot get access\n");
2782 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2783 * @hw: pointer to the HW structure
2784 * @timeout: maximum time to wait for completion
2786 * This function starts a flash cycle and waits for its completion.
2788 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2790 union ich8_hws_flash_ctrl hsflctl;
2791 union ich8_hws_flash_status hsfsts;
2794 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2795 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2796 hsflctl.hsf_ctrl.flcgo = 1;
2797 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2799 /* wait till FDONE bit is set to 1 */
2801 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2802 if (hsfsts.hsf_status.flcdone)
2805 } while (i++ < timeout);
2807 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
2810 return -E1000_ERR_NVM;
2814 * e1000_read_flash_word_ich8lan - Read word from flash
2815 * @hw: pointer to the HW structure
2816 * @offset: offset to data location
2817 * @data: pointer to the location for storing the data
2819 * Reads the flash word at offset into data. Offset is converted
2820 * to bytes before read.
2822 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2825 /* Must convert offset into bytes. */
2828 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2832 * e1000_read_flash_byte_ich8lan - Read byte from flash
2833 * @hw: pointer to the HW structure
2834 * @offset: The offset of the byte to read.
2835 * @data: Pointer to a byte to store the value read.
2837 * Reads a single byte from the NVM using the flash access registers.
2839 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2845 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2855 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2856 * @hw: pointer to the HW structure
2857 * @offset: The offset (in bytes) of the byte or word to read.
2858 * @size: Size of data to read, 1=byte 2=word
2859 * @data: Pointer to the word to store the value read.
2861 * Reads a byte or word from the NVM using the flash access registers.
2863 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2866 union ich8_hws_flash_status hsfsts;
2867 union ich8_hws_flash_ctrl hsflctl;
2868 u32 flash_linear_addr;
2870 s32 ret_val = -E1000_ERR_NVM;
2873 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2874 return -E1000_ERR_NVM;
2876 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2877 hw->nvm.flash_base_addr);
2882 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2886 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2887 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2888 hsflctl.hsf_ctrl.fldbcount = size - 1;
2889 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2890 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2892 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2895 e1000_flash_cycle_ich8lan(hw,
2896 ICH_FLASH_READ_COMMAND_TIMEOUT);
2898 /* Check if FCERR is set to 1, if set to 1, clear it
2899 * and try the whole sequence a few more times, else
2900 * read in (shift in) the Flash Data0, the order is
2901 * least significant byte first msb to lsb
2904 flash_data = er32flash(ICH_FLASH_FDATA0);
2906 *data = (u8)(flash_data & 0x000000FF);
2908 *data = (u16)(flash_data & 0x0000FFFF);
2911 /* If we've gotten here, then things are probably
2912 * completely hosed, but if the error condition is
2913 * detected, it won't hurt to give it another try...
2914 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2916 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2917 if (hsfsts.hsf_status.flcerr) {
2918 /* Repeat for some time before giving up. */
2920 } else if (!hsfsts.hsf_status.flcdone) {
2921 e_dbg("Timeout error - flash cycle did not complete.\n");
2925 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2931 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2932 * @hw: pointer to the HW structure
2933 * @offset: The offset (in bytes) of the word(s) to write.
2934 * @words: Size of data to write in words
2935 * @data: Pointer to the word(s) to write at offset.
2937 * Writes a byte or word to the NVM using the flash access registers.
2939 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2942 struct e1000_nvm_info *nvm = &hw->nvm;
2943 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2946 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2948 e_dbg("nvm parameter(s) out of bounds\n");
2949 return -E1000_ERR_NVM;
2952 nvm->ops.acquire(hw);
2954 for (i = 0; i < words; i++) {
2955 dev_spec->shadow_ram[offset + i].modified = true;
2956 dev_spec->shadow_ram[offset + i].value = data[i];
2959 nvm->ops.release(hw);
2965 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2966 * @hw: pointer to the HW structure
2968 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2969 * which writes the checksum to the shadow ram. The changes in the shadow
2970 * ram are then committed to the EEPROM by processing each bank at a time
2971 * checking for the modified bit and writing only the pending changes.
2972 * After a successful commit, the shadow ram is cleared and is ready for
2975 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2977 struct e1000_nvm_info *nvm = &hw->nvm;
2978 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2979 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2983 ret_val = e1000e_update_nvm_checksum_generic(hw);
2987 if (nvm->type != e1000_nvm_flash_sw)
2990 nvm->ops.acquire(hw);
2992 /* We're writing to the opposite bank so if we're on bank 1,
2993 * write to bank 0 etc. We also need to erase the segment that
2994 * is going to be written
2996 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2998 e_dbg("Could not detect valid bank, assuming bank 0\n");
3003 new_bank_offset = nvm->flash_bank_size;
3004 old_bank_offset = 0;
3005 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3009 old_bank_offset = nvm->flash_bank_size;
3010 new_bank_offset = 0;
3011 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3016 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3017 /* Determine whether to write the value stored
3018 * in the other NVM bank or a modified value stored
3021 if (dev_spec->shadow_ram[i].modified) {
3022 data = dev_spec->shadow_ram[i].value;
3024 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3031 /* If the word is 0x13, then make sure the signature bits
3032 * (15:14) are 11b until the commit has completed.
3033 * This will allow us to write 10b which indicates the
3034 * signature is valid. We want to do this after the write
3035 * has completed so that we don't mark the segment valid
3036 * while the write is still in progress
3038 if (i == E1000_ICH_NVM_SIG_WORD)
3039 data |= E1000_ICH_NVM_SIG_MASK;
3041 /* Convert offset to bytes. */
3042 act_offset = (i + new_bank_offset) << 1;
3044 usleep_range(100, 200);
3045 /* Write the bytes to the new bank. */
3046 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3052 usleep_range(100, 200);
3053 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3060 /* Don't bother writing the segment valid bits if sector
3061 * programming failed.
3064 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3065 e_dbg("Flash commit failed.\n");
3069 /* Finally validate the new segment by setting bit 15:14
3070 * to 10b in word 0x13 , this can be done without an
3071 * erase as well since these bits are 11 to start with
3072 * and we need to change bit 14 to 0b
3074 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3075 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3080 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3086 /* And invalidate the previously valid segment by setting
3087 * its signature word (0x13) high_byte to 0b. This can be
3088 * done without an erase because flash erase sets all bits
3089 * to 1's. We can write 1's to 0's without an erase
3091 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3092 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3096 /* Great! Everything worked, we can now clear the cached entries. */
3097 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3098 dev_spec->shadow_ram[i].modified = false;
3099 dev_spec->shadow_ram[i].value = 0xFFFF;
3103 nvm->ops.release(hw);
3105 /* Reload the EEPROM, or else modifications will not appear
3106 * until after the next adapter reset.
3109 nvm->ops.reload(hw);
3110 usleep_range(10000, 20000);
3115 e_dbg("NVM update error: %d\n", ret_val);
3121 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3122 * @hw: pointer to the HW structure
3124 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3125 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
3126 * calculated, in which case we need to calculate the checksum and set bit 6.
3128 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3133 u16 valid_csum_mask;
3135 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3136 * the checksum needs to be fixed. This bit is an indication that
3137 * the NVM was prepared by OEM software and did not calculate
3138 * the checksum...a likely scenario.
3140 switch (hw->mac.type) {
3143 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3146 word = NVM_FUTURE_INIT_WORD1;
3147 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3151 ret_val = e1000_read_nvm(hw, word, 1, &data);
3155 if (!(data & valid_csum_mask)) {
3156 data |= valid_csum_mask;
3157 ret_val = e1000_write_nvm(hw, word, 1, &data);
3160 ret_val = e1000e_update_nvm_checksum(hw);
3165 return e1000e_validate_nvm_checksum_generic(hw);
3169 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3170 * @hw: pointer to the HW structure
3172 * To prevent malicious write/erase of the NVM, set it to be read-only
3173 * so that the hardware ignores all write/erase cycles of the NVM via
3174 * the flash control registers. The shadow-ram copy of the NVM will
3175 * still be updated, however any updates to this copy will not stick
3176 * across driver reloads.
3178 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3180 struct e1000_nvm_info *nvm = &hw->nvm;
3181 union ich8_flash_protected_range pr0;
3182 union ich8_hws_flash_status hsfsts;
3185 nvm->ops.acquire(hw);
3187 gfpreg = er32flash(ICH_FLASH_GFPREG);
3189 /* Write-protect GbE Sector of NVM */
3190 pr0.regval = er32flash(ICH_FLASH_PR0);
3191 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
3192 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
3193 pr0.range.wpe = true;
3194 ew32flash(ICH_FLASH_PR0, pr0.regval);
3196 /* Lock down a subset of GbE Flash Control Registers, e.g.
3197 * PR0 to prevent the write-protection from being lifted.
3198 * Once FLOCKDN is set, the registers protected by it cannot
3199 * be written until FLOCKDN is cleared by a hardware reset.
3201 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3202 hsfsts.hsf_status.flockdn = true;
3203 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3205 nvm->ops.release(hw);
3209 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3210 * @hw: pointer to the HW structure
3211 * @offset: The offset (in bytes) of the byte/word to read.
3212 * @size: Size of data to read, 1=byte 2=word
3213 * @data: The byte(s) to write to the NVM.
3215 * Writes one/two bytes to the NVM using the flash access registers.
3217 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3220 union ich8_hws_flash_status hsfsts;
3221 union ich8_hws_flash_ctrl hsflctl;
3222 u32 flash_linear_addr;
3227 if (size < 1 || size > 2 || data > size * 0xff ||
3228 offset > ICH_FLASH_LINEAR_ADDR_MASK)
3229 return -E1000_ERR_NVM;
3231 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3232 hw->nvm.flash_base_addr);
3237 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3241 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3242 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3243 hsflctl.hsf_ctrl.fldbcount = size - 1;
3244 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3245 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3247 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3250 flash_data = (u32)data & 0x00FF;
3252 flash_data = (u32)data;
3254 ew32flash(ICH_FLASH_FDATA0, flash_data);
3256 /* check if FCERR is set to 1 , if set to 1, clear it
3257 * and try the whole sequence a few more times else done
3260 e1000_flash_cycle_ich8lan(hw,
3261 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3265 /* If we're here, then things are most likely
3266 * completely hosed, but if the error condition
3267 * is detected, it won't hurt to give it another
3268 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3270 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3271 if (hsfsts.hsf_status.flcerr)
3272 /* Repeat for some time before giving up. */
3274 if (!hsfsts.hsf_status.flcdone) {
3275 e_dbg("Timeout error - flash cycle did not complete.\n");
3278 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3284 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3285 * @hw: pointer to the HW structure
3286 * @offset: The index of the byte to read.
3287 * @data: The byte to write to the NVM.
3289 * Writes a single byte to the NVM using the flash access registers.
3291 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3294 u16 word = (u16)data;
3296 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3300 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3301 * @hw: pointer to the HW structure
3302 * @offset: The offset of the byte to write.
3303 * @byte: The byte to write to the NVM.
3305 * Writes a single byte to the NVM using the flash access registers.
3306 * Goes through a retry algorithm before giving up.
3308 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3309 u32 offset, u8 byte)
3312 u16 program_retries;
3314 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3318 for (program_retries = 0; program_retries < 100; program_retries++) {
3319 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
3320 usleep_range(100, 200);
3321 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3325 if (program_retries == 100)
3326 return -E1000_ERR_NVM;
3332 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3333 * @hw: pointer to the HW structure
3334 * @bank: 0 for first bank, 1 for second bank, etc.
3336 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3337 * bank N is 4096 * N + flash_reg_addr.
3339 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3341 struct e1000_nvm_info *nvm = &hw->nvm;
3342 union ich8_hws_flash_status hsfsts;
3343 union ich8_hws_flash_ctrl hsflctl;
3344 u32 flash_linear_addr;
3345 /* bank size is in 16bit words - adjust to bytes */
3346 u32 flash_bank_size = nvm->flash_bank_size * 2;
3349 s32 j, iteration, sector_size;
3351 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3353 /* Determine HW Sector size: Read BERASE bits of hw flash status
3355 * 00: The Hw sector is 256 bytes, hence we need to erase 16
3356 * consecutive sectors. The start index for the nth Hw sector
3357 * can be calculated as = bank * 4096 + n * 256
3358 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3359 * The start index for the nth Hw sector can be calculated
3361 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3362 * (ich9 only, otherwise error condition)
3363 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3365 switch (hsfsts.hsf_status.berasesz) {
3367 /* Hw sector size 256 */
3368 sector_size = ICH_FLASH_SEG_SIZE_256;
3369 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3372 sector_size = ICH_FLASH_SEG_SIZE_4K;
3376 sector_size = ICH_FLASH_SEG_SIZE_8K;
3380 sector_size = ICH_FLASH_SEG_SIZE_64K;
3384 return -E1000_ERR_NVM;
3387 /* Start with the base address, then add the sector offset. */
3388 flash_linear_addr = hw->nvm.flash_base_addr;
3389 flash_linear_addr += (bank) ? flash_bank_size : 0;
3391 for (j = 0; j < iteration; j++) {
3393 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3396 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3400 /* Write a value 11 (block Erase) in Flash
3401 * Cycle field in hw flash control
3403 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3404 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3405 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3407 /* Write the last 24 bits of an index within the
3408 * block into Flash Linear address field in Flash
3411 flash_linear_addr += (j * sector_size);
3412 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3414 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
3418 /* Check if FCERR is set to 1. If 1,
3419 * clear it and try the whole sequence
3420 * a few more times else Done
3422 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3423 if (hsfsts.hsf_status.flcerr)
3424 /* repeat for some time before giving up */
3426 else if (!hsfsts.hsf_status.flcdone)
3428 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3435 * e1000_valid_led_default_ich8lan - Set the default LED settings
3436 * @hw: pointer to the HW structure
3437 * @data: Pointer to the LED settings
3439 * Reads the LED default settings from the NVM to data. If the NVM LED
3440 * settings is all 0's or F's, set the LED default to a valid LED default
3443 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3447 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3449 e_dbg("NVM Read Error\n");
3453 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3454 *data = ID_LED_DEFAULT_ICH8LAN;
3460 * e1000_id_led_init_pchlan - store LED configurations
3461 * @hw: pointer to the HW structure
3463 * PCH does not control LEDs via the LEDCTL register, rather it uses
3464 * the PHY LED configuration register.
3466 * PCH also does not have an "always on" or "always off" mode which
3467 * complicates the ID feature. Instead of using the "on" mode to indicate
3468 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3469 * use "link_up" mode. The LEDs will still ID on request if there is no
3470 * link based on logic in e1000_led_[on|off]_pchlan().
3472 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3474 struct e1000_mac_info *mac = &hw->mac;
3476 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3477 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3478 u16 data, i, temp, shift;
3480 /* Get default ID LED modes */
3481 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3485 mac->ledctl_default = er32(LEDCTL);
3486 mac->ledctl_mode1 = mac->ledctl_default;
3487 mac->ledctl_mode2 = mac->ledctl_default;
3489 for (i = 0; i < 4; i++) {
3490 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3493 case ID_LED_ON1_DEF2:
3494 case ID_LED_ON1_ON2:
3495 case ID_LED_ON1_OFF2:
3496 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3497 mac->ledctl_mode1 |= (ledctl_on << shift);
3499 case ID_LED_OFF1_DEF2:
3500 case ID_LED_OFF1_ON2:
3501 case ID_LED_OFF1_OFF2:
3502 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3503 mac->ledctl_mode1 |= (ledctl_off << shift);
3510 case ID_LED_DEF1_ON2:
3511 case ID_LED_ON1_ON2:
3512 case ID_LED_OFF1_ON2:
3513 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3514 mac->ledctl_mode2 |= (ledctl_on << shift);
3516 case ID_LED_DEF1_OFF2:
3517 case ID_LED_ON1_OFF2:
3518 case ID_LED_OFF1_OFF2:
3519 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3520 mac->ledctl_mode2 |= (ledctl_off << shift);
3532 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3533 * @hw: pointer to the HW structure
3535 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3536 * register, so the the bus width is hard coded.
3538 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3540 struct e1000_bus_info *bus = &hw->bus;
3543 ret_val = e1000e_get_bus_info_pcie(hw);
3545 /* ICH devices are "PCI Express"-ish. They have
3546 * a configuration space, but do not contain
3547 * PCI Express Capability registers, so bus width
3548 * must be hardcoded.
3550 if (bus->width == e1000_bus_width_unknown)
3551 bus->width = e1000_bus_width_pcie_x1;
3557 * e1000_reset_hw_ich8lan - Reset the hardware
3558 * @hw: pointer to the HW structure
3560 * Does a full reset of the hardware which includes a reset of the PHY and
3563 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3565 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3570 /* Prevent the PCI-E bus from sticking if there is no TLP connection
3571 * on the last TLP read/write transaction when MAC is reset.
3573 ret_val = e1000e_disable_pcie_master(hw);
3575 e_dbg("PCI-E Master disable polling has failed.\n");
3577 e_dbg("Masking off all interrupts\n");
3578 ew32(IMC, 0xffffffff);
3580 /* Disable the Transmit and Receive units. Then delay to allow
3581 * any pending transactions to complete before we hit the MAC
3582 * with the global reset.
3585 ew32(TCTL, E1000_TCTL_PSP);
3588 usleep_range(10000, 20000);
3590 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3591 if (hw->mac.type == e1000_ich8lan) {
3592 /* Set Tx and Rx buffer allocation to 8k apiece. */
3593 ew32(PBA, E1000_PBA_8K);
3594 /* Set Packet Buffer Size to 16k. */
3595 ew32(PBS, E1000_PBS_16K);
3598 if (hw->mac.type == e1000_pchlan) {
3599 /* Save the NVM K1 bit setting */
3600 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3604 if (kum_cfg & E1000_NVM_K1_ENABLE)
3605 dev_spec->nvm_k1_enabled = true;
3607 dev_spec->nvm_k1_enabled = false;
3612 if (!hw->phy.ops.check_reset_block(hw)) {
3613 /* Full-chip reset requires MAC and PHY reset at the same
3614 * time to make sure the interface between MAC and the
3615 * external PHY is reset.
3617 ctrl |= E1000_CTRL_PHY_RST;
3619 /* Gate automatic PHY configuration by hardware on
3622 if ((hw->mac.type == e1000_pch2lan) &&
3623 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3624 e1000_gate_hw_phy_config_ich8lan(hw, true);
3626 ret_val = e1000_acquire_swflag_ich8lan(hw);
3627 e_dbg("Issuing a global reset to ich8lan\n");
3628 ew32(CTRL, (ctrl | E1000_CTRL_RST));
3629 /* cannot issue a flush here because it hangs the hardware */
3632 /* Set Phy Config Counter to 50msec */
3633 if (hw->mac.type == e1000_pch2lan) {
3634 reg = er32(FEXTNVM3);
3635 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3636 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3637 ew32(FEXTNVM3, reg);
3641 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3643 if (ctrl & E1000_CTRL_PHY_RST) {
3644 ret_val = hw->phy.ops.get_cfg_done(hw);
3648 ret_val = e1000_post_phy_reset_ich8lan(hw);
3653 /* For PCH, this write will make sure that any noise
3654 * will be detected as a CRC error and be dropped rather than show up
3655 * as a bad packet to the DMA engine.
3657 if (hw->mac.type == e1000_pchlan)
3658 ew32(CRC_OFFSET, 0x65656565);
3660 ew32(IMC, 0xffffffff);
3663 reg = er32(KABGTXD);
3664 reg |= E1000_KABGTXD_BGSQLBIAS;
3671 * e1000_init_hw_ich8lan - Initialize the hardware
3672 * @hw: pointer to the HW structure
3674 * Prepares the hardware for transmit and receive by doing the following:
3675 * - initialize hardware bits
3676 * - initialize LED identification
3677 * - setup receive address registers
3678 * - setup flow control
3679 * - setup transmit descriptors
3680 * - clear statistics
3682 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3684 struct e1000_mac_info *mac = &hw->mac;
3685 u32 ctrl_ext, txdctl, snoop;
3689 e1000_initialize_hw_bits_ich8lan(hw);
3691 /* Initialize identification LED */
3692 ret_val = mac->ops.id_led_init(hw);
3693 /* An error is not fatal and we should not stop init due to this */
3695 e_dbg("Error initializing identification LED\n");
3697 /* Setup the receive address. */
3698 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3700 /* Zero out the Multicast HASH table */
3701 e_dbg("Zeroing the MTA\n");
3702 for (i = 0; i < mac->mta_reg_count; i++)
3703 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3705 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3706 * the ME. Disable wakeup by clearing the host wakeup bit.
3707 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3709 if (hw->phy.type == e1000_phy_82578) {
3710 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3711 i &= ~BM_WUC_HOST_WU_BIT;
3712 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3713 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3718 /* Setup link and flow control */
3719 ret_val = mac->ops.setup_link(hw);
3721 /* Set the transmit descriptor write-back policy for both queues */
3722 txdctl = er32(TXDCTL(0));
3723 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3724 E1000_TXDCTL_FULL_TX_DESC_WB);
3725 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3726 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
3727 ew32(TXDCTL(0), txdctl);
3728 txdctl = er32(TXDCTL(1));
3729 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3730 E1000_TXDCTL_FULL_TX_DESC_WB);
3731 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3732 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
3733 ew32(TXDCTL(1), txdctl);
3735 /* ICH8 has opposite polarity of no_snoop bits.
3736 * By default, we should use snoop behavior.
3738 if (mac->type == e1000_ich8lan)
3739 snoop = PCIE_ICH8_SNOOP_ALL;
3741 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
3742 e1000e_set_pcie_no_snoop(hw, snoop);
3744 ctrl_ext = er32(CTRL_EXT);
3745 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3746 ew32(CTRL_EXT, ctrl_ext);
3748 /* Clear all of the statistics registers (clear on read). It is
3749 * important that we do this after we have tried to establish link
3750 * because the symbol error count will increment wildly if there
3753 e1000_clear_hw_cntrs_ich8lan(hw);
3759 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3760 * @hw: pointer to the HW structure
3762 * Sets/Clears required hardware bits necessary for correctly setting up the
3763 * hardware for transmit and receive.
3765 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3769 /* Extended Device Control */
3770 reg = er32(CTRL_EXT);
3772 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3773 if (hw->mac.type >= e1000_pchlan)
3774 reg |= E1000_CTRL_EXT_PHYPDEN;
3775 ew32(CTRL_EXT, reg);
3777 /* Transmit Descriptor Control 0 */
3778 reg = er32(TXDCTL(0));
3780 ew32(TXDCTL(0), reg);
3782 /* Transmit Descriptor Control 1 */
3783 reg = er32(TXDCTL(1));
3785 ew32(TXDCTL(1), reg);
3787 /* Transmit Arbitration Control 0 */
3788 reg = er32(TARC(0));
3789 if (hw->mac.type == e1000_ich8lan)
3790 reg |= (1 << 28) | (1 << 29);
3791 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3794 /* Transmit Arbitration Control 1 */
3795 reg = er32(TARC(1));
3796 if (er32(TCTL) & E1000_TCTL_MULR)
3800 reg |= (1 << 24) | (1 << 26) | (1 << 30);
3804 if (hw->mac.type == e1000_ich8lan) {
3810 /* work-around descriptor data corruption issue during nfs v2 udp
3811 * traffic, just disable the nfs filtering capability
3814 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3816 /* Disable IPv6 extension header parsing because some malformed
3817 * IPv6 headers can hang the Rx.
3819 if (hw->mac.type == e1000_ich8lan)
3820 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
3823 /* Enable ECC on Lynxpoint */
3824 if (hw->mac.type == e1000_pch_lpt) {
3825 reg = er32(PBECCSTS);
3826 reg |= E1000_PBECCSTS_ECC_ENABLE;
3827 ew32(PBECCSTS, reg);
3830 reg |= E1000_CTRL_MEHE;
3836 * e1000_setup_link_ich8lan - Setup flow control and link settings
3837 * @hw: pointer to the HW structure
3839 * Determines which flow control settings to use, then configures flow
3840 * control. Calls the appropriate media-specific link configuration
3841 * function. Assuming the adapter has a valid link partner, a valid link
3842 * should be established. Assumes the hardware has previously been reset
3843 * and the transmitter and receiver are not enabled.
3845 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3849 if (hw->phy.ops.check_reset_block(hw))
3852 /* ICH parts do not have a word in the NVM to determine
3853 * the default flow control setting, so we explicitly
3856 if (hw->fc.requested_mode == e1000_fc_default) {
3857 /* Workaround h/w hang when Tx flow control enabled */
3858 if (hw->mac.type == e1000_pchlan)
3859 hw->fc.requested_mode = e1000_fc_rx_pause;
3861 hw->fc.requested_mode = e1000_fc_full;
3864 /* Save off the requested flow control mode for use later. Depending
3865 * on the link partner's capabilities, we may or may not use this mode.
3867 hw->fc.current_mode = hw->fc.requested_mode;
3869 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
3871 /* Continue to configure the copper link. */
3872 ret_val = hw->mac.ops.setup_physical_interface(hw);
3876 ew32(FCTTV, hw->fc.pause_time);
3877 if ((hw->phy.type == e1000_phy_82578) ||
3878 (hw->phy.type == e1000_phy_82579) ||
3879 (hw->phy.type == e1000_phy_i217) ||
3880 (hw->phy.type == e1000_phy_82577)) {
3881 ew32(FCRTV_PCH, hw->fc.refresh_time);
3883 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3889 return e1000e_set_fc_watermarks(hw);
3893 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3894 * @hw: pointer to the HW structure
3896 * Configures the kumeran interface to the PHY to wait the appropriate time
3897 * when polling the PHY, then call the generic setup_copper_link to finish
3898 * configuring the copper link.
3900 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3907 ctrl |= E1000_CTRL_SLU;
3908 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3911 /* Set the mac to wait the maximum time between each iteration
3912 * and increase the max iterations when polling the phy;
3913 * this fixes erroneous timeouts at 10Mbps.
3915 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3918 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3923 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3928 switch (hw->phy.type) {
3929 case e1000_phy_igp_3:
3930 ret_val = e1000e_copper_link_setup_igp(hw);
3935 case e1000_phy_82578:
3936 ret_val = e1000e_copper_link_setup_m88(hw);
3940 case e1000_phy_82577:
3941 case e1000_phy_82579:
3942 ret_val = e1000_copper_link_setup_82577(hw);
3947 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data);
3951 reg_data &= ~IFE_PMC_AUTO_MDIX;
3953 switch (hw->phy.mdix) {
3955 reg_data &= ~IFE_PMC_FORCE_MDIX;
3958 reg_data |= IFE_PMC_FORCE_MDIX;
3962 reg_data |= IFE_PMC_AUTO_MDIX;
3965 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3973 return e1000e_setup_copper_link(hw);
3977 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
3978 * @hw: pointer to the HW structure
3980 * Calls the PHY specific link setup function and then calls the
3981 * generic setup_copper_link to finish configuring the link for
3982 * Lynxpoint PCH devices
3984 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
3990 ctrl |= E1000_CTRL_SLU;
3991 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3994 ret_val = e1000_copper_link_setup_82577(hw);
3998 return e1000e_setup_copper_link(hw);
4002 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4003 * @hw: pointer to the HW structure
4004 * @speed: pointer to store current link speed
4005 * @duplex: pointer to store the current link duplex
4007 * Calls the generic get_speed_and_duplex to retrieve the current link
4008 * information and then calls the Kumeran lock loss workaround for links at
4011 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4016 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
4020 if ((hw->mac.type == e1000_ich8lan) &&
4021 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
4022 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4029 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4030 * @hw: pointer to the HW structure
4032 * Work-around for 82566 Kumeran PCS lock loss:
4033 * On link status change (i.e. PCI reset, speed change) and link is up and
4035 * 0) if workaround is optionally disabled do nothing
4036 * 1) wait 1ms for Kumeran link to come up
4037 * 2) check Kumeran Diagnostic register PCS lock loss bit
4038 * 3) if not set the link is locked (all is good), otherwise...
4040 * 5) repeat up to 10 times
4041 * Note: this is only called for IGP3 copper when speed is 1gb.
4043 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4045 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4051 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4054 /* Make sure link is up before proceeding. If not just return.
4055 * Attempting this while link is negotiating fouled up link
4058 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
4062 for (i = 0; i < 10; i++) {
4063 /* read once to clear */
4064 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4067 /* and again to get new status */
4068 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4072 /* check for PCS lock */
4073 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4076 /* Issue PHY reset */
4077 e1000_phy_hw_reset(hw);
4080 /* Disable GigE link negotiation */
4081 phy_ctrl = er32(PHY_CTRL);
4082 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4083 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4084 ew32(PHY_CTRL, phy_ctrl);
4086 /* Call gig speed drop workaround on Gig disable before accessing
4089 e1000e_gig_downshift_workaround_ich8lan(hw);
4091 /* unable to acquire PCS lock */
4092 return -E1000_ERR_PHY;
4096 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4097 * @hw: pointer to the HW structure
4098 * @state: boolean value used to set the current Kumeran workaround state
4100 * If ICH8, set the current Kumeran workaround state (enabled - true
4101 * /disabled - false).
4103 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4106 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4108 if (hw->mac.type != e1000_ich8lan) {
4109 e_dbg("Workaround applies to ICH8 only.\n");
4113 dev_spec->kmrn_lock_loss_workaround_enabled = state;
4117 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4118 * @hw: pointer to the HW structure
4120 * Workaround for 82566 power-down on D3 entry:
4121 * 1) disable gigabit link
4122 * 2) write VR power-down enable
4124 * Continue if successful, else issue LCD reset and repeat
4126 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4132 if (hw->phy.type != e1000_phy_igp_3)
4135 /* Try the workaround twice (if needed) */
4138 reg = er32(PHY_CTRL);
4139 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4140 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4141 ew32(PHY_CTRL, reg);
4143 /* Call gig speed drop workaround on Gig disable before
4144 * accessing any PHY registers
4146 if (hw->mac.type == e1000_ich8lan)
4147 e1000e_gig_downshift_workaround_ich8lan(hw);
4149 /* Write VR power-down enable */
4150 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4151 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4152 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4154 /* Read it back and test */
4155 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4156 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4157 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4160 /* Issue PHY reset and repeat at most one more time */
4162 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
4168 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4169 * @hw: pointer to the HW structure
4171 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4172 * LPLU, Gig disable, MDIC PHY reset):
4173 * 1) Set Kumeran Near-end loopback
4174 * 2) Clear Kumeran Near-end loopback
4175 * Should only be called for ICH8[m] devices with any 1G Phy.
4177 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4182 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
4185 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4189 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4190 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4194 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4195 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
4199 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4200 * @hw: pointer to the HW structure
4202 * During S0 to Sx transition, it is possible the link remains at gig
4203 * instead of negotiating to a lower speed. Before going to Sx, set
4204 * 'Gig Disable' to force link speed negotiation to a lower speed based on
4205 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
4206 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4207 * needs to be written.
4208 * Parts that support (and are linked to a partner which support) EEE in
4209 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4210 * than 10Mbps w/o EEE.
4212 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4214 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4218 phy_ctrl = er32(PHY_CTRL);
4219 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4221 if (hw->phy.type == e1000_phy_i217) {
4222 u16 phy_reg, device_id = hw->adapter->pdev->device;
4224 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4225 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4226 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4227 (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4228 u32 fextnvm6 = er32(FEXTNVM6);
4230 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4233 ret_val = hw->phy.ops.acquire(hw);
4237 if (!dev_spec->eee_disable) {
4241 e1000_read_emi_reg_locked(hw,
4242 I217_EEE_ADVERTISEMENT,
4247 /* Disable LPLU if both link partners support 100BaseT
4248 * EEE and 100Full is advertised on both ends of the
4251 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4252 (dev_spec->eee_lp_ability &
4253 I82579_EEE_100_SUPPORTED) &&
4254 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4255 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4256 E1000_PHY_CTRL_NOND0A_LPLU);
4259 /* For i217 Intel Rapid Start Technology support,
4260 * when the system is going into Sx and no manageability engine
4261 * is present, the driver must configure proxy to reset only on
4262 * power good. LPI (Low Power Idle) state must also reset only
4263 * on power good, as well as the MTA (Multicast table array).
4264 * The SMBus release must also be disabled on LCD reset.
4266 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4267 /* Enable proxy to reset only on power good. */
4268 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4269 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4270 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4272 /* Set bit enable LPI (EEE) to reset only on
4275 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
4276 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4277 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4279 /* Disable the SMB release on LCD reset. */
4280 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4281 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4282 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4285 /* Enable MTA to reset for Intel Rapid Start Technology
4288 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4289 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4290 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4293 hw->phy.ops.release(hw);
4296 ew32(PHY_CTRL, phy_ctrl);
4298 if (hw->mac.type == e1000_ich8lan)
4299 e1000e_gig_downshift_workaround_ich8lan(hw);
4301 if (hw->mac.type >= e1000_pchlan) {
4302 e1000_oem_bits_config_ich8lan(hw, false);
4304 /* Reset PHY to activate OEM bits on 82577/8 */
4305 if (hw->mac.type == e1000_pchlan)
4306 e1000e_phy_hw_reset_generic(hw);
4308 ret_val = hw->phy.ops.acquire(hw);
4311 e1000_write_smbus_addr(hw);
4312 hw->phy.ops.release(hw);
4317 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4318 * @hw: pointer to the HW structure
4320 * During Sx to S0 transitions on non-managed devices or managed devices
4321 * on which PHY resets are not blocked, if the PHY registers cannot be
4322 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4324 * On i217, setup Intel Rapid Start Technology.
4326 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4330 if (hw->mac.type < e1000_pch2lan)
4333 ret_val = e1000_init_phy_workarounds_pchlan(hw);
4335 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
4339 /* For i217 Intel Rapid Start Technology support when the system
4340 * is transitioning from Sx and no manageability engine is present
4341 * configure SMBus to restore on reset, disable proxy, and enable
4342 * the reset on MTA (Multicast table array).
4344 if (hw->phy.type == e1000_phy_i217) {
4347 ret_val = hw->phy.ops.acquire(hw);
4349 e_dbg("Failed to setup iRST\n");
4353 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4354 /* Restore clear on SMB if no manageability engine
4357 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4360 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4361 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4364 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4366 /* Enable reset on MTA */
4367 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4370 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4371 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4374 e_dbg("Error %d in resume workarounds\n", ret_val);
4375 hw->phy.ops.release(hw);
4380 * e1000_cleanup_led_ich8lan - Restore the default LED operation
4381 * @hw: pointer to the HW structure
4383 * Return the LED back to the default configuration.
4385 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4387 if (hw->phy.type == e1000_phy_ife)
4388 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4390 ew32(LEDCTL, hw->mac.ledctl_default);
4395 * e1000_led_on_ich8lan - Turn LEDs on
4396 * @hw: pointer to the HW structure
4400 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4402 if (hw->phy.type == e1000_phy_ife)
4403 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4404 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4406 ew32(LEDCTL, hw->mac.ledctl_mode2);
4411 * e1000_led_off_ich8lan - Turn LEDs off
4412 * @hw: pointer to the HW structure
4414 * Turn off the LEDs.
4416 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4418 if (hw->phy.type == e1000_phy_ife)
4419 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4420 (IFE_PSCL_PROBE_MODE |
4421 IFE_PSCL_PROBE_LEDS_OFF));
4423 ew32(LEDCTL, hw->mac.ledctl_mode1);
4428 * e1000_setup_led_pchlan - Configures SW controllable LED
4429 * @hw: pointer to the HW structure
4431 * This prepares the SW controllable LED for use.
4433 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4435 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
4439 * e1000_cleanup_led_pchlan - Restore the default LED operation
4440 * @hw: pointer to the HW structure
4442 * Return the LED back to the default configuration.
4444 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4446 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
4450 * e1000_led_on_pchlan - Turn LEDs on
4451 * @hw: pointer to the HW structure
4455 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4457 u16 data = (u16)hw->mac.ledctl_mode2;
4460 /* If no link, then turn LED on by setting the invert bit
4461 * for each LED that's mode is "link_up" in ledctl_mode2.
4463 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4464 for (i = 0; i < 3; i++) {
4465 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4466 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4467 E1000_LEDCTL_MODE_LINK_UP)
4469 if (led & E1000_PHY_LED0_IVRT)
4470 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4472 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4476 return e1e_wphy(hw, HV_LED_CONFIG, data);
4480 * e1000_led_off_pchlan - Turn LEDs off
4481 * @hw: pointer to the HW structure
4483 * Turn off the LEDs.
4485 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4487 u16 data = (u16)hw->mac.ledctl_mode1;
4490 /* If no link, then turn LED off by clearing the invert bit
4491 * for each LED that's mode is "link_up" in ledctl_mode1.
4493 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4494 for (i = 0; i < 3; i++) {
4495 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4496 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4497 E1000_LEDCTL_MODE_LINK_UP)
4499 if (led & E1000_PHY_LED0_IVRT)
4500 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4502 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4506 return e1e_wphy(hw, HV_LED_CONFIG, data);
4510 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4511 * @hw: pointer to the HW structure
4513 * Read appropriate register for the config done bit for completion status
4514 * and configure the PHY through s/w for EEPROM-less parts.
4516 * NOTE: some silicon which is EEPROM-less will fail trying to read the
4517 * config done bit, so only an error is logged and continues. If we were
4518 * to return with error, EEPROM-less silicon would not be able to be reset
4521 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4527 e1000e_get_cfg_done_generic(hw);
4529 /* Wait for indication from h/w that it has completed basic config */
4530 if (hw->mac.type >= e1000_ich10lan) {
4531 e1000_lan_init_done_ich8lan(hw);
4533 ret_val = e1000e_get_auto_rd_done(hw);
4535 /* When auto config read does not complete, do not
4536 * return with an error. This can happen in situations
4537 * where there is no eeprom and prevents getting link.
4539 e_dbg("Auto Read Done did not complete\n");
4544 /* Clear PHY Reset Asserted bit */
4545 status = er32(STATUS);
4546 if (status & E1000_STATUS_PHYRA)
4547 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4549 e_dbg("PHY Reset Asserted not set - needs delay\n");
4551 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4552 if (hw->mac.type <= e1000_ich9lan) {
4553 if (!(er32(EECD) & E1000_EECD_PRES) &&
4554 (hw->phy.type == e1000_phy_igp_3)) {
4555 e1000e_phy_init_script_igp3(hw);
4558 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4559 /* Maybe we should do a basic PHY config */
4560 e_dbg("EEPROM not present\n");
4561 ret_val = -E1000_ERR_CONFIG;
4569 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4570 * @hw: pointer to the HW structure
4572 * In the case of a PHY power down to save power, or to turn off link during a
4573 * driver unload, or wake on lan is not enabled, remove the link.
4575 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4577 /* If the management interface is not enabled, then power down */
4578 if (!(hw->mac.ops.check_mng_mode(hw) ||
4579 hw->phy.ops.check_reset_block(hw)))
4580 e1000_power_down_phy_copper(hw);
4584 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4585 * @hw: pointer to the HW structure
4587 * Clears hardware counters specific to the silicon family and calls
4588 * clear_hw_cntrs_generic to clear all general purpose counters.
4590 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4595 e1000e_clear_hw_cntrs_base(hw);
4611 /* Clear PHY statistics registers */
4612 if ((hw->phy.type == e1000_phy_82578) ||
4613 (hw->phy.type == e1000_phy_82579) ||
4614 (hw->phy.type == e1000_phy_i217) ||
4615 (hw->phy.type == e1000_phy_82577)) {
4616 ret_val = hw->phy.ops.acquire(hw);
4619 ret_val = hw->phy.ops.set_page(hw,
4620 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4623 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4624 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4625 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4626 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4627 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4628 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4629 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4630 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4631 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4632 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4633 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4634 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4635 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4636 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4638 hw->phy.ops.release(hw);
4642 static const struct e1000_mac_operations ich8_mac_ops = {
4643 /* check_mng_mode dependent on mac type */
4644 .check_for_link = e1000_check_for_copper_link_ich8lan,
4645 /* cleanup_led dependent on mac type */
4646 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
4647 .get_bus_info = e1000_get_bus_info_ich8lan,
4648 .set_lan_id = e1000_set_lan_id_single_port,
4649 .get_link_up_info = e1000_get_link_up_info_ich8lan,
4650 /* led_on dependent on mac type */
4651 /* led_off dependent on mac type */
4652 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
4653 .reset_hw = e1000_reset_hw_ich8lan,
4654 .init_hw = e1000_init_hw_ich8lan,
4655 .setup_link = e1000_setup_link_ich8lan,
4656 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
4657 /* id_led_init dependent on mac type */
4658 .config_collision_dist = e1000e_config_collision_dist_generic,
4659 .rar_set = e1000e_rar_set_generic,
4662 static const struct e1000_phy_operations ich8_phy_ops = {
4663 .acquire = e1000_acquire_swflag_ich8lan,
4664 .check_reset_block = e1000_check_reset_block_ich8lan,
4666 .get_cfg_done = e1000_get_cfg_done_ich8lan,
4667 .get_cable_length = e1000e_get_cable_length_igp_2,
4668 .read_reg = e1000e_read_phy_reg_igp,
4669 .release = e1000_release_swflag_ich8lan,
4670 .reset = e1000_phy_hw_reset_ich8lan,
4671 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
4672 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
4673 .write_reg = e1000e_write_phy_reg_igp,
4676 static const struct e1000_nvm_operations ich8_nvm_ops = {
4677 .acquire = e1000_acquire_nvm_ich8lan,
4678 .read = e1000_read_nvm_ich8lan,
4679 .release = e1000_release_nvm_ich8lan,
4680 .reload = e1000e_reload_nvm_generic,
4681 .update = e1000_update_nvm_checksum_ich8lan,
4682 .valid_led_default = e1000_valid_led_default_ich8lan,
4683 .validate = e1000_validate_nvm_checksum_ich8lan,
4684 .write = e1000_write_nvm_ich8lan,
4687 const struct e1000_info e1000_ich8_info = {
4688 .mac = e1000_ich8lan,
4689 .flags = FLAG_HAS_WOL
4691 | FLAG_HAS_CTRLEXT_ON_LOAD
4696 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
4697 .get_variants = e1000_get_variants_ich8lan,
4698 .mac_ops = &ich8_mac_ops,
4699 .phy_ops = &ich8_phy_ops,
4700 .nvm_ops = &ich8_nvm_ops,
4703 const struct e1000_info e1000_ich9_info = {
4704 .mac = e1000_ich9lan,
4705 .flags = FLAG_HAS_JUMBO_FRAMES
4708 | FLAG_HAS_CTRLEXT_ON_LOAD
4713 .max_hw_frame_size = DEFAULT_JUMBO,
4714 .get_variants = e1000_get_variants_ich8lan,
4715 .mac_ops = &ich8_mac_ops,
4716 .phy_ops = &ich8_phy_ops,
4717 .nvm_ops = &ich8_nvm_ops,
4720 const struct e1000_info e1000_ich10_info = {
4721 .mac = e1000_ich10lan,
4722 .flags = FLAG_HAS_JUMBO_FRAMES
4725 | FLAG_HAS_CTRLEXT_ON_LOAD
4730 .max_hw_frame_size = DEFAULT_JUMBO,
4731 .get_variants = e1000_get_variants_ich8lan,
4732 .mac_ops = &ich8_mac_ops,
4733 .phy_ops = &ich8_phy_ops,
4734 .nvm_ops = &ich8_nvm_ops,
4737 const struct e1000_info e1000_pch_info = {
4738 .mac = e1000_pchlan,
4739 .flags = FLAG_IS_ICH
4741 | FLAG_HAS_CTRLEXT_ON_LOAD
4744 | FLAG_HAS_JUMBO_FRAMES
4745 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4747 .flags2 = FLAG2_HAS_PHY_STATS,
4749 .max_hw_frame_size = 4096,
4750 .get_variants = e1000_get_variants_ich8lan,
4751 .mac_ops = &ich8_mac_ops,
4752 .phy_ops = &ich8_phy_ops,
4753 .nvm_ops = &ich8_nvm_ops,
4756 const struct e1000_info e1000_pch2_info = {
4757 .mac = e1000_pch2lan,
4758 .flags = FLAG_IS_ICH
4760 | FLAG_HAS_HW_TIMESTAMP
4761 | FLAG_HAS_CTRLEXT_ON_LOAD
4764 | FLAG_HAS_JUMBO_FRAMES
4766 .flags2 = FLAG2_HAS_PHY_STATS
4769 .max_hw_frame_size = 9018,
4770 .get_variants = e1000_get_variants_ich8lan,
4771 .mac_ops = &ich8_mac_ops,
4772 .phy_ops = &ich8_phy_ops,
4773 .nvm_ops = &ich8_nvm_ops,
4776 const struct e1000_info e1000_pch_lpt_info = {
4777 .mac = e1000_pch_lpt,
4778 .flags = FLAG_IS_ICH
4780 | FLAG_HAS_HW_TIMESTAMP
4781 | FLAG_HAS_CTRLEXT_ON_LOAD
4784 | FLAG_HAS_JUMBO_FRAMES
4786 .flags2 = FLAG2_HAS_PHY_STATS
4789 .max_hw_frame_size = 9018,
4790 .get_variants = e1000_get_variants_ich8lan,
4791 .mac_ops = &ich8_mac_ops,
4792 .phy_ops = &ich8_phy_ops,
4793 .nvm_ops = &ich8_nvm_ops,