1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
31 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
32 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
33 u16 *data, bool read, bool page_set);
34 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
35 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
36 u16 *data, bool read);
38 /* Cable length tables */
39 static const u16 e1000_m88_cable_length_table[] = {
40 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
43 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
44 ARRAY_SIZE(e1000_m88_cable_length_table)
46 static const u16 e1000_igp_2_cable_length_table[] = {
47 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
48 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
49 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
50 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
51 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
52 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
53 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
58 ARRAY_SIZE(e1000_igp_2_cable_length_table)
61 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
62 * @hw: pointer to the HW structure
64 * Read the PHY management control register and check whether a PHY reset
65 * is blocked. If a reset is not blocked return 0, otherwise
66 * return E1000_BLK_PHY_RESET (12).
68 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
74 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
75 E1000_BLK_PHY_RESET : 0;
79 * e1000e_get_phy_id - Retrieve the PHY ID and revision
80 * @hw: pointer to the HW structure
82 * Reads the PHY registers and stores the PHY ID and possibly the PHY
83 * revision in the hardware structure.
85 s32 e1000e_get_phy_id(struct e1000_hw *hw)
87 struct e1000_phy_info *phy = &hw->phy;
92 if (!phy->ops.read_reg)
95 while (retry_count < 2) {
96 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
100 phy->id = (u32)(phy_id << 16);
102 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
106 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
107 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
109 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
119 * e1000e_phy_reset_dsp - Reset PHY DSP
120 * @hw: pointer to the HW structure
122 * Reset the digital signal processor.
124 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
128 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
132 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
136 * e1000e_read_phy_reg_mdic - Read MDI control register
137 * @hw: pointer to the HW structure
138 * @offset: register offset to be read
139 * @data: pointer to the read data
141 * Reads the MDI control register in the PHY at offset and stores the
142 * information read to data.
144 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
146 struct e1000_phy_info *phy = &hw->phy;
149 if (offset > MAX_PHY_REG_ADDRESS) {
150 e_dbg("PHY Address %d is out of range\n", offset);
151 return -E1000_ERR_PARAM;
154 /* Set up Op-code, Phy Address, and register offset in the MDI
155 * Control register. The MAC will take care of interfacing with the
156 * PHY to retrieve the desired data.
158 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
159 (phy->addr << E1000_MDIC_PHY_SHIFT) |
160 (E1000_MDIC_OP_READ));
164 /* Poll the ready bit to see if the MDI read completed
165 * Increasing the time out as testing showed failures with
168 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
171 if (mdic & E1000_MDIC_READY)
174 if (!(mdic & E1000_MDIC_READY)) {
175 e_dbg("MDI Read did not complete\n");
176 return -E1000_ERR_PHY;
178 if (mdic & E1000_MDIC_ERROR) {
179 e_dbg("MDI Error\n");
180 return -E1000_ERR_PHY;
184 /* Allow some time after each MDIC transaction to avoid
185 * reading duplicate data in the next MDIC transaction.
187 if (hw->mac.type == e1000_pch2lan)
194 * e1000e_write_phy_reg_mdic - Write MDI control register
195 * @hw: pointer to the HW structure
196 * @offset: register offset to write to
197 * @data: data to write to register at offset
199 * Writes data to MDI control register in the PHY at offset.
201 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
203 struct e1000_phy_info *phy = &hw->phy;
206 if (offset > MAX_PHY_REG_ADDRESS) {
207 e_dbg("PHY Address %d is out of range\n", offset);
208 return -E1000_ERR_PARAM;
211 /* Set up Op-code, Phy Address, and register offset in the MDI
212 * Control register. The MAC will take care of interfacing with the
213 * PHY to retrieve the desired data.
215 mdic = (((u32)data) |
216 (offset << E1000_MDIC_REG_SHIFT) |
217 (phy->addr << E1000_MDIC_PHY_SHIFT) |
218 (E1000_MDIC_OP_WRITE));
222 /* Poll the ready bit to see if the MDI read completed
223 * Increasing the time out as testing showed failures with
226 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
229 if (mdic & E1000_MDIC_READY)
232 if (!(mdic & E1000_MDIC_READY)) {
233 e_dbg("MDI Write did not complete\n");
234 return -E1000_ERR_PHY;
236 if (mdic & E1000_MDIC_ERROR) {
237 e_dbg("MDI Error\n");
238 return -E1000_ERR_PHY;
241 /* Allow some time after each MDIC transaction to avoid
242 * reading duplicate data in the next MDIC transaction.
244 if (hw->mac.type == e1000_pch2lan)
251 * e1000e_read_phy_reg_m88 - Read m88 PHY register
252 * @hw: pointer to the HW structure
253 * @offset: register offset to be read
254 * @data: pointer to the read data
256 * Acquires semaphore, if necessary, then reads the PHY register at offset
257 * and storing the retrieved information in data. Release any acquired
258 * semaphores before exiting.
260 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
264 ret_val = hw->phy.ops.acquire(hw);
268 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
271 hw->phy.ops.release(hw);
277 * e1000e_write_phy_reg_m88 - Write m88 PHY register
278 * @hw: pointer to the HW structure
279 * @offset: register offset to write to
280 * @data: data to write at register offset
282 * Acquires semaphore, if necessary, then writes the data to PHY register
283 * at the offset. Release any acquired semaphores before exiting.
285 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
289 ret_val = hw->phy.ops.acquire(hw);
293 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
296 hw->phy.ops.release(hw);
302 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
303 * @hw: pointer to the HW structure
304 * @page: page to set (shifted left when necessary)
306 * Sets PHY page required for PHY register access. Assumes semaphore is
307 * already acquired. Note, this function sets phy.addr to 1 so the caller
308 * must set it appropriately (if necessary) after this function returns.
310 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
312 e_dbg("Setting page 0x%x\n", page);
316 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
320 * __e1000e_read_phy_reg_igp - Read igp PHY register
321 * @hw: pointer to the HW structure
322 * @offset: register offset to be read
323 * @data: pointer to the read data
324 * @locked: semaphore has already been acquired or not
326 * Acquires semaphore, if necessary, then reads the PHY register at offset
327 * and stores the retrieved information in data. Release any acquired
328 * semaphores before exiting.
330 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
336 if (!hw->phy.ops.acquire)
339 ret_val = hw->phy.ops.acquire(hw);
344 if (offset > MAX_PHY_MULTI_PAGE_REG)
345 ret_val = e1000e_write_phy_reg_mdic(hw,
346 IGP01E1000_PHY_PAGE_SELECT,
349 ret_val = e1000e_read_phy_reg_mdic(hw,
350 MAX_PHY_REG_ADDRESS & offset,
353 hw->phy.ops.release(hw);
359 * e1000e_read_phy_reg_igp - Read igp PHY register
360 * @hw: pointer to the HW structure
361 * @offset: register offset to be read
362 * @data: pointer to the read data
364 * Acquires semaphore then reads the PHY register at offset and stores the
365 * retrieved information in data.
366 * Release the acquired semaphore before exiting.
368 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
370 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
374 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
375 * @hw: pointer to the HW structure
376 * @offset: register offset to be read
377 * @data: pointer to the read data
379 * Reads the PHY register at offset and stores the retrieved information
380 * in data. Assumes semaphore already acquired.
382 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
384 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
388 * e1000e_write_phy_reg_igp - Write igp PHY register
389 * @hw: pointer to the HW structure
390 * @offset: register offset to write to
391 * @data: data to write at register offset
392 * @locked: semaphore has already been acquired or not
394 * Acquires semaphore, if necessary, then writes the data to PHY register
395 * at the offset. Release any acquired semaphores before exiting.
397 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
403 if (!hw->phy.ops.acquire)
406 ret_val = hw->phy.ops.acquire(hw);
411 if (offset > MAX_PHY_MULTI_PAGE_REG)
412 ret_val = e1000e_write_phy_reg_mdic(hw,
413 IGP01E1000_PHY_PAGE_SELECT,
416 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
419 hw->phy.ops.release(hw);
425 * e1000e_write_phy_reg_igp - Write igp PHY register
426 * @hw: pointer to the HW structure
427 * @offset: register offset to write to
428 * @data: data to write at register offset
430 * Acquires semaphore then writes the data to PHY register
431 * at the offset. Release any acquired semaphores before exiting.
433 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
435 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
439 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
440 * @hw: pointer to the HW structure
441 * @offset: register offset to write to
442 * @data: data to write at register offset
444 * Writes the data to PHY register at the offset.
445 * Assumes semaphore already acquired.
447 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
449 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
453 * __e1000_read_kmrn_reg - Read kumeran register
454 * @hw: pointer to the HW structure
455 * @offset: register offset to be read
456 * @data: pointer to the read data
457 * @locked: semaphore has already been acquired or not
459 * Acquires semaphore, if necessary. Then reads the PHY register at offset
460 * using the kumeran interface. The information retrieved is stored in data.
461 * Release any acquired semaphores before exiting.
463 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
471 if (!hw->phy.ops.acquire)
474 ret_val = hw->phy.ops.acquire(hw);
479 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
480 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
481 ew32(KMRNCTRLSTA, kmrnctrlsta);
486 kmrnctrlsta = er32(KMRNCTRLSTA);
487 *data = (u16)kmrnctrlsta;
490 hw->phy.ops.release(hw);
496 * e1000e_read_kmrn_reg - Read kumeran register
497 * @hw: pointer to the HW structure
498 * @offset: register offset to be read
499 * @data: pointer to the read data
501 * Acquires semaphore then reads the PHY register at offset using the
502 * kumeran interface. The information retrieved is stored in data.
503 * Release the acquired semaphore before exiting.
505 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
507 return __e1000_read_kmrn_reg(hw, offset, data, false);
511 * e1000e_read_kmrn_reg_locked - Read kumeran register
512 * @hw: pointer to the HW structure
513 * @offset: register offset to be read
514 * @data: pointer to the read data
516 * Reads the PHY register at offset using the kumeran interface. The
517 * information retrieved is stored in data.
518 * Assumes semaphore already acquired.
520 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
522 return __e1000_read_kmrn_reg(hw, offset, data, true);
526 * __e1000_write_kmrn_reg - Write kumeran register
527 * @hw: pointer to the HW structure
528 * @offset: register offset to write to
529 * @data: data to write at register offset
530 * @locked: semaphore has already been acquired or not
532 * Acquires semaphore, if necessary. Then write the data to PHY register
533 * at the offset using the kumeran interface. Release any acquired semaphores
536 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
544 if (!hw->phy.ops.acquire)
547 ret_val = hw->phy.ops.acquire(hw);
552 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
553 E1000_KMRNCTRLSTA_OFFSET) | data;
554 ew32(KMRNCTRLSTA, kmrnctrlsta);
560 hw->phy.ops.release(hw);
566 * e1000e_write_kmrn_reg - Write kumeran register
567 * @hw: pointer to the HW structure
568 * @offset: register offset to write to
569 * @data: data to write at register offset
571 * Acquires semaphore then writes the data to the PHY register at the offset
572 * using the kumeran interface. Release the acquired semaphore before exiting.
574 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
576 return __e1000_write_kmrn_reg(hw, offset, data, false);
580 * e1000e_write_kmrn_reg_locked - Write kumeran register
581 * @hw: pointer to the HW structure
582 * @offset: register offset to write to
583 * @data: data to write at register offset
585 * Write the data to PHY register at the offset using the kumeran interface.
586 * Assumes semaphore already acquired.
588 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
590 return __e1000_write_kmrn_reg(hw, offset, data, true);
594 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
595 * @hw: pointer to the HW structure
597 * Sets up Master/slave mode
599 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
604 /* Resolve Master/Slave mode */
605 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
609 /* load defaults for future use */
610 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ?
611 ((phy_data & CTL1000_AS_MASTER) ?
612 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
614 switch (hw->phy.ms_type) {
615 case e1000_ms_force_master:
616 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
618 case e1000_ms_force_slave:
619 phy_data |= CTL1000_ENABLE_MASTER;
620 phy_data &= ~(CTL1000_AS_MASTER);
623 phy_data &= ~CTL1000_ENABLE_MASTER;
629 return e1e_wphy(hw, MII_CTRL1000, phy_data);
633 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
634 * @hw: pointer to the HW structure
636 * Sets up Carrier-sense on Transmit and downshift values.
638 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
643 /* Enable CRS on Tx. This must be set for half-duplex operation. */
644 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
648 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
650 /* Enable downshift */
651 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
653 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
657 /* Set MDI/MDIX mode */
658 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
661 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
667 switch (hw->phy.mdix) {
671 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
675 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
678 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
682 return e1000_set_master_slave_mode(hw);
686 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
687 * @hw: pointer to the HW structure
689 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
690 * and downshift values are set also.
692 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
694 struct e1000_phy_info *phy = &hw->phy;
698 /* Enable CRS on Tx. This must be set for half-duplex operation. */
699 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
703 /* For BM PHY this bit is downshift enable */
704 if (phy->type != e1000_phy_bm)
705 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
708 * MDI/MDI-X = 0 (default)
709 * 0 - Auto for all speeds
712 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
714 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
718 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
721 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
724 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
728 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
733 * disable_polarity_correction = 0 (default)
734 * Automatic Correction for Reversed Cable Polarity
738 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
739 if (phy->disable_polarity_correction)
740 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
742 /* Enable downshift on BM (disabled by default) */
743 if (phy->type == e1000_phy_bm) {
744 /* For 82574/82583, first disable then enable downshift */
745 if (phy->id == BME1000_E_PHY_ID_R2) {
746 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
747 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
751 /* Commit the changes. */
752 ret_val = phy->ops.commit(hw);
754 e_dbg("Error committing the PHY changes\n");
759 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
762 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
766 if ((phy->type == e1000_phy_m88) &&
767 (phy->revision < E1000_REVISION_4) &&
768 (phy->id != BME1000_E_PHY_ID_R2)) {
769 /* Force TX_CLK in the Extended PHY Specific Control Register
772 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
776 phy_data |= M88E1000_EPSCR_TX_CLK_25;
778 if ((phy->revision == 2) &&
779 (phy->id == M88E1111_I_PHY_ID)) {
780 /* 82573L PHY - set the downshift counter to 5x. */
781 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
782 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
784 /* Configure Master and Slave downshift values */
785 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
786 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
787 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
788 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
790 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
795 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
796 /* Set PHY page 0, register 29 to 0x0003 */
797 ret_val = e1e_wphy(hw, 29, 0x0003);
801 /* Set PHY page 0, register 30 to 0x0000 */
802 ret_val = e1e_wphy(hw, 30, 0x0000);
807 /* Commit the changes. */
808 if (phy->ops.commit) {
809 ret_val = phy->ops.commit(hw);
811 e_dbg("Error committing the PHY changes\n");
816 if (phy->type == e1000_phy_82578) {
817 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
821 /* 82578 PHY - set the downshift count to 1x. */
822 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
823 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
824 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
833 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
834 * @hw: pointer to the HW structure
836 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
839 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
841 struct e1000_phy_info *phy = &hw->phy;
845 ret_val = e1000_phy_hw_reset(hw);
847 e_dbg("Error resetting the PHY.\n");
851 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
852 * timeout issues when LFS is enabled.
856 /* disable lplu d0 during driver init */
857 if (hw->phy.ops.set_d0_lplu_state) {
858 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
860 e_dbg("Error Disabling LPLU D0\n");
864 /* Configure mdi-mdix settings */
865 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
869 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
873 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
876 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
880 data |= IGP01E1000_PSCR_AUTO_MDIX;
883 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
887 /* set auto-master slave resolution settings */
888 if (hw->mac.autoneg) {
889 /* when autonegotiation advertisement is only 1000Mbps then we
890 * should disable SmartSpeed and enable Auto MasterSlave
891 * resolution as hardware default.
893 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
894 /* Disable SmartSpeed */
895 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
900 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
901 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
906 /* Set auto Master/Slave resolution process */
907 ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
911 data &= ~CTL1000_ENABLE_MASTER;
912 ret_val = e1e_wphy(hw, MII_CTRL1000, data);
917 ret_val = e1000_set_master_slave_mode(hw);
924 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
925 * @hw: pointer to the HW structure
927 * Reads the MII auto-neg advertisement register and/or the 1000T control
928 * register and if the PHY is already setup for auto-negotiation, then
929 * return successful. Otherwise, setup advertisement and flow control to
930 * the appropriate values for the wanted auto-negotiation.
932 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
934 struct e1000_phy_info *phy = &hw->phy;
936 u16 mii_autoneg_adv_reg;
937 u16 mii_1000t_ctrl_reg = 0;
939 phy->autoneg_advertised &= phy->autoneg_mask;
941 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
942 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg);
946 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
947 /* Read the MII 1000Base-T Control Register (Address 9). */
948 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
953 /* Need to parse both autoneg_advertised and fc and set up
954 * the appropriate PHY registers. First we will parse for
955 * autoneg_advertised software override. Since we can advertise
956 * a plethora of combinations, we need to check each bit
960 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
961 * Advertisement Register (Address 4) and the 1000 mb speed bits in
962 * the 1000Base-T Control Register (Address 9).
964 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
966 ADVERTISE_10FULL | ADVERTISE_10HALF);
967 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
969 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
971 /* Do we want to advertise 10 Mb Half Duplex? */
972 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
973 e_dbg("Advertise 10mb Half duplex\n");
974 mii_autoneg_adv_reg |= ADVERTISE_10HALF;
977 /* Do we want to advertise 10 Mb Full Duplex? */
978 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
979 e_dbg("Advertise 10mb Full duplex\n");
980 mii_autoneg_adv_reg |= ADVERTISE_10FULL;
983 /* Do we want to advertise 100 Mb Half Duplex? */
984 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
985 e_dbg("Advertise 100mb Half duplex\n");
986 mii_autoneg_adv_reg |= ADVERTISE_100HALF;
989 /* Do we want to advertise 100 Mb Full Duplex? */
990 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
991 e_dbg("Advertise 100mb Full duplex\n");
992 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
995 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
996 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
997 e_dbg("Advertise 1000mb Half duplex request denied!\n");
999 /* Do we want to advertise 1000 Mb Full Duplex? */
1000 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1001 e_dbg("Advertise 1000mb Full duplex\n");
1002 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
1005 /* Check for a software override of the flow control settings, and
1006 * setup the PHY advertisement registers accordingly. If
1007 * auto-negotiation is enabled, then software will have to set the
1008 * "PAUSE" bits to the correct value in the Auto-Negotiation
1009 * Advertisement Register (MII_ADVERTISE) and re-start auto-
1012 * The possible values of the "fc" parameter are:
1013 * 0: Flow control is completely disabled
1014 * 1: Rx flow control is enabled (we can receive pause frames
1015 * but not send pause frames).
1016 * 2: Tx flow control is enabled (we can send pause frames
1017 * but we do not support receiving pause frames).
1018 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1019 * other: No software override. The flow control configuration
1020 * in the EEPROM is used.
1022 switch (hw->fc.current_mode) {
1024 /* Flow control (Rx & Tx) is completely disabled by a
1025 * software over-ride.
1027 mii_autoneg_adv_reg &=
1028 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1030 case e1000_fc_rx_pause:
1031 /* Rx Flow control is enabled, and Tx Flow control is
1032 * disabled, by a software over-ride.
1034 * Since there really isn't a way to advertise that we are
1035 * capable of Rx Pause ONLY, we will advertise that we
1036 * support both symmetric and asymmetric Rx PAUSE. Later
1037 * (in e1000e_config_fc_after_link_up) we will disable the
1038 * hw's ability to send PAUSE frames.
1040 mii_autoneg_adv_reg |=
1041 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1043 case e1000_fc_tx_pause:
1044 /* Tx Flow control is enabled, and Rx Flow control is
1045 * disabled, by a software over-ride.
1047 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
1048 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
1051 /* Flow control (both Rx and Tx) is enabled by a software
1054 mii_autoneg_adv_reg |=
1055 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1058 e_dbg("Flow control param set incorrectly\n");
1059 return -E1000_ERR_CONFIG;
1062 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1066 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1068 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1069 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
1075 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1076 * @hw: pointer to the HW structure
1078 * Performs initial bounds checking on autoneg advertisement parameter, then
1079 * configure to advertise the full capability. Setup the PHY to autoneg
1080 * and restart the negotiation process between the link partner. If
1081 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1083 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1085 struct e1000_phy_info *phy = &hw->phy;
1089 /* Perform some bounds checking on the autoneg advertisement
1092 phy->autoneg_advertised &= phy->autoneg_mask;
1094 /* If autoneg_advertised is zero, we assume it was not defaulted
1095 * by the calling code so we set to advertise full capability.
1097 if (!phy->autoneg_advertised)
1098 phy->autoneg_advertised = phy->autoneg_mask;
1100 e_dbg("Reconfiguring auto-neg advertisement params\n");
1101 ret_val = e1000_phy_setup_autoneg(hw);
1103 e_dbg("Error Setting up Auto-Negotiation\n");
1106 e_dbg("Restarting Auto-Neg\n");
1108 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1109 * the Auto Neg Restart bit in the PHY control register.
1111 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1115 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1116 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1120 /* Does the user want to wait for Auto-Neg to complete here, or
1121 * check at a later time (for example, callback routine).
1123 if (phy->autoneg_wait_to_complete) {
1124 ret_val = e1000_wait_autoneg(hw);
1126 e_dbg("Error while waiting for autoneg to complete\n");
1131 hw->mac.get_link_status = true;
1137 * e1000e_setup_copper_link - Configure copper link settings
1138 * @hw: pointer to the HW structure
1140 * Calls the appropriate function to configure the link for auto-neg or forced
1141 * speed and duplex. Then we check for link, once link is established calls
1142 * to configure collision distance and flow control are called. If link is
1143 * not established, we return -E1000_ERR_PHY (-2).
1145 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1150 if (hw->mac.autoneg) {
1151 /* Setup autoneg and flow control advertisement and perform
1154 ret_val = e1000_copper_link_autoneg(hw);
1158 /* PHY will be set to 10H, 10F, 100H or 100F
1159 * depending on user settings.
1161 e_dbg("Forcing Speed and Duplex\n");
1162 ret_val = hw->phy.ops.force_speed_duplex(hw);
1164 e_dbg("Error Forcing Speed and Duplex\n");
1169 /* Check link status. Wait up to 100 microseconds for link to become
1172 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1178 e_dbg("Valid link established!!!\n");
1179 hw->mac.ops.config_collision_dist(hw);
1180 ret_val = e1000e_config_fc_after_link_up(hw);
1182 e_dbg("Unable to establish link!!!\n");
1189 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1190 * @hw: pointer to the HW structure
1192 * Calls the PHY setup function to force speed and duplex. Clears the
1193 * auto-crossover to force MDI manually. Waits for link and returns
1194 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1196 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1198 struct e1000_phy_info *phy = &hw->phy;
1203 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1207 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1209 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1213 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1214 * forced whenever speed and duplex are forced.
1216 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1220 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1221 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1223 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1227 e_dbg("IGP PSCR: %X\n", phy_data);
1231 if (phy->autoneg_wait_to_complete) {
1232 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1234 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1240 e_dbg("Link taking longer than expected.\n");
1243 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1251 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1252 * @hw: pointer to the HW structure
1254 * Calls the PHY setup function to force speed and duplex. Clears the
1255 * auto-crossover to force MDI manually. Resets the PHY to commit the
1256 * changes. If time expires while waiting for link up, we reset the DSP.
1257 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1258 * successful completion, else return corresponding error code.
1260 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1262 struct e1000_phy_info *phy = &hw->phy;
1267 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1268 * forced whenever speed and duplex are forced.
1270 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1274 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1275 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1279 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1281 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1285 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1287 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1291 /* Reset the phy to commit changes. */
1292 if (hw->phy.ops.commit) {
1293 ret_val = hw->phy.ops.commit(hw);
1298 if (phy->autoneg_wait_to_complete) {
1299 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1301 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1307 if (hw->phy.type != e1000_phy_m88) {
1308 e_dbg("Link taking longer than expected.\n");
1310 /* We didn't get link.
1311 * Reset the DSP and cross our fingers.
1313 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1317 ret_val = e1000e_phy_reset_dsp(hw);
1324 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1330 if (hw->phy.type != e1000_phy_m88)
1333 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1337 /* Resetting the phy means we need to re-force TX_CLK in the
1338 * Extended PHY Specific Control Register to 25MHz clock from
1339 * the reset value of 2.5MHz.
1341 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1342 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1346 /* In addition, we must re-enable CRS on Tx for both half and full
1349 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1353 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1354 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1360 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1361 * @hw: pointer to the HW structure
1363 * Forces the speed and duplex settings of the PHY.
1364 * This is a function pointer entry point only called by
1365 * PHY setup routines.
1367 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1369 struct e1000_phy_info *phy = &hw->phy;
1374 ret_val = e1e_rphy(hw, MII_BMCR, &data);
1378 e1000e_phy_force_speed_duplex_setup(hw, &data);
1380 ret_val = e1e_wphy(hw, MII_BMCR, data);
1384 /* Disable MDI-X support for 10/100 */
1385 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1389 data &= ~IFE_PMC_AUTO_MDIX;
1390 data &= ~IFE_PMC_FORCE_MDIX;
1392 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1396 e_dbg("IFE PMC: %X\n", data);
1400 if (phy->autoneg_wait_to_complete) {
1401 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1403 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1409 e_dbg("Link taking longer than expected.\n");
1412 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1422 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1423 * @hw: pointer to the HW structure
1424 * @phy_ctrl: pointer to current value of MII_BMCR
1426 * Forces speed and duplex on the PHY by doing the following: disable flow
1427 * control, force speed/duplex on the MAC, disable auto speed detection,
1428 * disable auto-negotiation, configure duplex, configure speed, configure
1429 * the collision distance, write configuration to CTRL register. The
1430 * caller must write to the MII_BMCR register for these settings to
1433 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1435 struct e1000_mac_info *mac = &hw->mac;
1438 /* Turn off flow control when forcing speed/duplex */
1439 hw->fc.current_mode = e1000_fc_none;
1441 /* Force speed/duplex on the mac */
1443 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1444 ctrl &= ~E1000_CTRL_SPD_SEL;
1446 /* Disable Auto Speed Detection */
1447 ctrl &= ~E1000_CTRL_ASDE;
1449 /* Disable autoneg on the phy */
1450 *phy_ctrl &= ~BMCR_ANENABLE;
1452 /* Forcing Full or Half Duplex? */
1453 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1454 ctrl &= ~E1000_CTRL_FD;
1455 *phy_ctrl &= ~BMCR_FULLDPLX;
1456 e_dbg("Half Duplex\n");
1458 ctrl |= E1000_CTRL_FD;
1459 *phy_ctrl |= BMCR_FULLDPLX;
1460 e_dbg("Full Duplex\n");
1463 /* Forcing 10mb or 100mb? */
1464 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1465 ctrl |= E1000_CTRL_SPD_100;
1466 *phy_ctrl |= BMCR_SPEED100;
1467 *phy_ctrl &= ~BMCR_SPEED1000;
1468 e_dbg("Forcing 100mb\n");
1470 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1471 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
1472 e_dbg("Forcing 10mb\n");
1475 hw->mac.ops.config_collision_dist(hw);
1481 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1482 * @hw: pointer to the HW structure
1483 * @active: boolean used to enable/disable lplu
1485 * Success returns 0, Failure returns 1
1487 * The low power link up (lplu) state is set to the power management level D3
1488 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1489 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1490 * is used during Dx states where the power conservation is most important.
1491 * During driver activity, SmartSpeed should be enabled so performance is
1494 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1496 struct e1000_phy_info *phy = &hw->phy;
1500 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1505 data &= ~IGP02E1000_PM_D3_LPLU;
1506 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1509 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1510 * during Dx states where the power conservation is most
1511 * important. During driver activity we should enable
1512 * SmartSpeed, so performance is maintained.
1514 if (phy->smart_speed == e1000_smart_speed_on) {
1515 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1520 data |= IGP01E1000_PSCFR_SMART_SPEED;
1521 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1525 } else if (phy->smart_speed == e1000_smart_speed_off) {
1526 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1531 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1532 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1537 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1538 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1539 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1540 data |= IGP02E1000_PM_D3_LPLU;
1541 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1545 /* When LPLU is enabled, we should disable SmartSpeed */
1546 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1550 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1551 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1558 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1559 * @hw: pointer to the HW structure
1561 * Success returns 0, Failure returns 1
1563 * A downshift is detected by querying the PHY link health.
1565 s32 e1000e_check_downshift(struct e1000_hw *hw)
1567 struct e1000_phy_info *phy = &hw->phy;
1569 u16 phy_data, offset, mask;
1571 switch (phy->type) {
1573 case e1000_phy_gg82563:
1575 case e1000_phy_82578:
1576 offset = M88E1000_PHY_SPEC_STATUS;
1577 mask = M88E1000_PSSR_DOWNSHIFT;
1579 case e1000_phy_igp_2:
1580 case e1000_phy_igp_3:
1581 offset = IGP01E1000_PHY_LINK_HEALTH;
1582 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1585 /* speed downshift not supported */
1586 phy->speed_downgraded = false;
1590 ret_val = e1e_rphy(hw, offset, &phy_data);
1593 phy->speed_downgraded = !!(phy_data & mask);
1599 * e1000_check_polarity_m88 - Checks the polarity.
1600 * @hw: pointer to the HW structure
1602 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1604 * Polarity is determined based on the PHY specific status register.
1606 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1608 struct e1000_phy_info *phy = &hw->phy;
1612 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1615 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
1616 ? e1000_rev_polarity_reversed
1617 : e1000_rev_polarity_normal);
1623 * e1000_check_polarity_igp - Checks the polarity.
1624 * @hw: pointer to the HW structure
1626 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1628 * Polarity is determined based on the PHY port status register, and the
1629 * current speed (since there is no polarity at 100Mbps).
1631 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1633 struct e1000_phy_info *phy = &hw->phy;
1635 u16 data, offset, mask;
1637 /* Polarity is determined based on the speed of
1640 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1644 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1645 IGP01E1000_PSSR_SPEED_1000MBPS) {
1646 offset = IGP01E1000_PHY_PCS_INIT_REG;
1647 mask = IGP01E1000_PHY_POLARITY_MASK;
1649 /* This really only applies to 10Mbps since
1650 * there is no polarity for 100Mbps (always 0).
1652 offset = IGP01E1000_PHY_PORT_STATUS;
1653 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1656 ret_val = e1e_rphy(hw, offset, &data);
1659 phy->cable_polarity = ((data & mask)
1660 ? e1000_rev_polarity_reversed
1661 : e1000_rev_polarity_normal);
1667 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1668 * @hw: pointer to the HW structure
1670 * Polarity is determined on the polarity reversal feature being enabled.
1672 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1674 struct e1000_phy_info *phy = &hw->phy;
1676 u16 phy_data, offset, mask;
1678 /* Polarity is determined based on the reversal feature being enabled.
1680 if (phy->polarity_correction) {
1681 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1682 mask = IFE_PESC_POLARITY_REVERSED;
1684 offset = IFE_PHY_SPECIAL_CONTROL;
1685 mask = IFE_PSC_FORCE_POLARITY;
1688 ret_val = e1e_rphy(hw, offset, &phy_data);
1691 phy->cable_polarity = ((phy_data & mask)
1692 ? e1000_rev_polarity_reversed
1693 : e1000_rev_polarity_normal);
1699 * e1000_wait_autoneg - Wait for auto-neg completion
1700 * @hw: pointer to the HW structure
1702 * Waits for auto-negotiation to complete or for the auto-negotiation time
1703 * limit to expire, which ever happens first.
1705 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1710 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1711 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1712 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1715 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1718 if (phy_status & BMSR_ANEGCOMPLETE)
1723 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1730 * e1000e_phy_has_link_generic - Polls PHY for link
1731 * @hw: pointer to the HW structure
1732 * @iterations: number of times to poll for link
1733 * @usec_interval: delay between polling attempts
1734 * @success: pointer to whether polling was successful or not
1736 * Polls the PHY status register for link, 'iterations' number of times.
1738 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1739 u32 usec_interval, bool *success)
1744 for (i = 0; i < iterations; i++) {
1745 /* Some PHYs require the MII_BMSR register to be read
1746 * twice due to the link bit being sticky. No harm doing
1747 * it across the board.
1749 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1751 /* If the first read fails, another entity may have
1752 * ownership of the resources, wait and try again to
1753 * see if they have relinquished the resources yet.
1755 udelay(usec_interval);
1756 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1759 if (phy_status & BMSR_LSTATUS)
1761 if (usec_interval >= 1000)
1762 mdelay(usec_interval / 1000);
1764 udelay(usec_interval);
1767 *success = (i < iterations);
1773 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1774 * @hw: pointer to the HW structure
1776 * Reads the PHY specific status register to retrieve the cable length
1777 * information. The cable length is determined by averaging the minimum and
1778 * maximum values to get the "average" cable length. The m88 PHY has four
1779 * possible cable length values, which are:
1780 * Register Value Cable Length
1784 * 3 110 - 140 meters
1787 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1789 struct e1000_phy_info *phy = &hw->phy;
1791 u16 phy_data, index;
1793 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1797 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1798 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
1800 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1801 return -E1000_ERR_PHY;
1803 phy->min_cable_length = e1000_m88_cable_length_table[index];
1804 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1806 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1812 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1813 * @hw: pointer to the HW structure
1815 * The automatic gain control (agc) normalizes the amplitude of the
1816 * received signal, adjusting for the attenuation produced by the
1817 * cable. By reading the AGC registers, which represent the
1818 * combination of coarse and fine gain value, the value can be put
1819 * into a lookup table to obtain the approximate cable length
1822 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1824 struct e1000_phy_info *phy = &hw->phy;
1826 u16 phy_data, i, agc_value = 0;
1827 u16 cur_agc_index, max_agc_index = 0;
1828 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1829 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1830 IGP02E1000_PHY_AGC_A,
1831 IGP02E1000_PHY_AGC_B,
1832 IGP02E1000_PHY_AGC_C,
1833 IGP02E1000_PHY_AGC_D
1836 /* Read the AGC registers for all channels */
1837 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1838 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1842 /* Getting bits 15:9, which represent the combination of
1843 * coarse and fine gain values. The result is a number
1844 * that can be put into the lookup table to obtain the
1845 * approximate cable length.
1847 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1848 IGP02E1000_AGC_LENGTH_MASK);
1850 /* Array index bound check. */
1851 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1852 (cur_agc_index == 0))
1853 return -E1000_ERR_PHY;
1855 /* Remove min & max AGC values from calculation. */
1856 if (e1000_igp_2_cable_length_table[min_agc_index] >
1857 e1000_igp_2_cable_length_table[cur_agc_index])
1858 min_agc_index = cur_agc_index;
1859 if (e1000_igp_2_cable_length_table[max_agc_index] <
1860 e1000_igp_2_cable_length_table[cur_agc_index])
1861 max_agc_index = cur_agc_index;
1863 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1866 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1867 e1000_igp_2_cable_length_table[max_agc_index]);
1868 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1870 /* Calculate cable length with the error range of +/- 10 meters. */
1871 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1872 (agc_value - IGP02E1000_AGC_RANGE) : 0);
1873 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1875 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1881 * e1000e_get_phy_info_m88 - Retrieve PHY information
1882 * @hw: pointer to the HW structure
1884 * Valid for only copper links. Read the PHY status register (sticky read)
1885 * to verify that link is up. Read the PHY special control register to
1886 * determine the polarity and 10base-T extended distance. Read the PHY
1887 * special status register to determine MDI/MDIx and current speed. If
1888 * speed is 1000, then determine cable length, local and remote receiver.
1890 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1892 struct e1000_phy_info *phy = &hw->phy;
1897 if (phy->media_type != e1000_media_type_copper) {
1898 e_dbg("Phy info is only valid for copper media\n");
1899 return -E1000_ERR_CONFIG;
1902 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1907 e_dbg("Phy info is only valid if link is up\n");
1908 return -E1000_ERR_CONFIG;
1911 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1915 phy->polarity_correction = !!(phy_data &
1916 M88E1000_PSCR_POLARITY_REVERSAL);
1918 ret_val = e1000_check_polarity_m88(hw);
1922 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1926 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1928 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1929 ret_val = hw->phy.ops.get_cable_length(hw);
1933 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data);
1937 phy->local_rx = (phy_data & LPA_1000LOCALRXOK)
1938 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1940 phy->remote_rx = (phy_data & LPA_1000REMRXOK)
1941 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1943 /* Set values to "undefined" */
1944 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1945 phy->local_rx = e1000_1000t_rx_status_undefined;
1946 phy->remote_rx = e1000_1000t_rx_status_undefined;
1953 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1954 * @hw: pointer to the HW structure
1956 * Read PHY status to determine if link is up. If link is up, then
1957 * set/determine 10base-T extended distance and polarity correction. Read
1958 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1959 * determine on the cable length, local and remote receiver.
1961 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1963 struct e1000_phy_info *phy = &hw->phy;
1968 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1973 e_dbg("Phy info is only valid if link is up\n");
1974 return -E1000_ERR_CONFIG;
1977 phy->polarity_correction = true;
1979 ret_val = e1000_check_polarity_igp(hw);
1983 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1987 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
1989 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1990 IGP01E1000_PSSR_SPEED_1000MBPS) {
1991 ret_val = phy->ops.get_cable_length(hw);
1995 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
1999 phy->local_rx = (data & LPA_1000LOCALRXOK)
2000 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2002 phy->remote_rx = (data & LPA_1000REMRXOK)
2003 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2005 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2006 phy->local_rx = e1000_1000t_rx_status_undefined;
2007 phy->remote_rx = e1000_1000t_rx_status_undefined;
2014 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2015 * @hw: pointer to the HW structure
2017 * Populates "phy" structure with various feature states.
2019 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2021 struct e1000_phy_info *phy = &hw->phy;
2026 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2031 e_dbg("Phy info is only valid if link is up\n");
2032 return -E1000_ERR_CONFIG;
2035 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2038 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2040 if (phy->polarity_correction) {
2041 ret_val = e1000_check_polarity_ife(hw);
2045 /* Polarity is forced */
2046 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2047 ? e1000_rev_polarity_reversed
2048 : e1000_rev_polarity_normal);
2051 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2055 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2057 /* The following parameters are undefined for 10/100 operation. */
2058 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2059 phy->local_rx = e1000_1000t_rx_status_undefined;
2060 phy->remote_rx = e1000_1000t_rx_status_undefined;
2066 * e1000e_phy_sw_reset - PHY software reset
2067 * @hw: pointer to the HW structure
2069 * Does a software reset of the PHY by reading the PHY control register and
2070 * setting/write the control register reset bit to the PHY.
2072 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2077 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
2081 phy_ctrl |= BMCR_RESET;
2082 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
2092 * e1000e_phy_hw_reset_generic - PHY hardware reset
2093 * @hw: pointer to the HW structure
2095 * Verify the reset block is not blocking us from resetting. Acquire
2096 * semaphore (if necessary) and read/set/write the device control reset
2097 * bit in the PHY. Wait the appropriate delay time for the device to
2098 * reset and release the semaphore (if necessary).
2100 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2102 struct e1000_phy_info *phy = &hw->phy;
2106 if (phy->ops.check_reset_block) {
2107 ret_val = phy->ops.check_reset_block(hw);
2112 ret_val = phy->ops.acquire(hw);
2117 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2120 udelay(phy->reset_delay_us);
2127 phy->ops.release(hw);
2129 return phy->ops.get_cfg_done(hw);
2133 * e1000e_get_cfg_done_generic - Generic configuration done
2134 * @hw: pointer to the HW structure
2136 * Generic function to wait 10 milli-seconds for configuration to complete
2137 * and return success.
2139 s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
2147 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2148 * @hw: pointer to the HW structure
2150 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2152 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2154 e_dbg("Running IGP 3 PHY init script\n");
2156 /* PHY init IGP 3 */
2157 /* Enable rise/fall, 10-mode work in class-A */
2158 e1e_wphy(hw, 0x2F5B, 0x9018);
2159 /* Remove all caps from Replica path filter */
2160 e1e_wphy(hw, 0x2F52, 0x0000);
2161 /* Bias trimming for ADC, AFE and Driver (Default) */
2162 e1e_wphy(hw, 0x2FB1, 0x8B24);
2163 /* Increase Hybrid poly bias */
2164 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2165 /* Add 4% to Tx amplitude in Gig mode */
2166 e1e_wphy(hw, 0x2010, 0x10B0);
2167 /* Disable trimming (TTT) */
2168 e1e_wphy(hw, 0x2011, 0x0000);
2169 /* Poly DC correction to 94.6% + 2% for all channels */
2170 e1e_wphy(hw, 0x20DD, 0x249A);
2171 /* ABS DC correction to 95.9% */
2172 e1e_wphy(hw, 0x20DE, 0x00D3);
2173 /* BG temp curve trim */
2174 e1e_wphy(hw, 0x28B4, 0x04CE);
2175 /* Increasing ADC OPAMP stage 1 currents to max */
2176 e1e_wphy(hw, 0x2F70, 0x29E4);
2177 /* Force 1000 ( required for enabling PHY regs configuration) */
2178 e1e_wphy(hw, 0x0000, 0x0140);
2179 /* Set upd_freq to 6 */
2180 e1e_wphy(hw, 0x1F30, 0x1606);
2182 e1e_wphy(hw, 0x1F31, 0xB814);
2183 /* Disable adaptive fixed FFE (Default) */
2184 e1e_wphy(hw, 0x1F35, 0x002A);
2185 /* Enable FFE hysteresis */
2186 e1e_wphy(hw, 0x1F3E, 0x0067);
2187 /* Fixed FFE for short cable lengths */
2188 e1e_wphy(hw, 0x1F54, 0x0065);
2189 /* Fixed FFE for medium cable lengths */
2190 e1e_wphy(hw, 0x1F55, 0x002A);
2191 /* Fixed FFE for long cable lengths */
2192 e1e_wphy(hw, 0x1F56, 0x002A);
2193 /* Enable Adaptive Clip Threshold */
2194 e1e_wphy(hw, 0x1F72, 0x3FB0);
2195 /* AHT reset limit to 1 */
2196 e1e_wphy(hw, 0x1F76, 0xC0FF);
2197 /* Set AHT master delay to 127 msec */
2198 e1e_wphy(hw, 0x1F77, 0x1DEC);
2199 /* Set scan bits for AHT */
2200 e1e_wphy(hw, 0x1F78, 0xF9EF);
2201 /* Set AHT Preset bits */
2202 e1e_wphy(hw, 0x1F79, 0x0210);
2203 /* Change integ_factor of channel A to 3 */
2204 e1e_wphy(hw, 0x1895, 0x0003);
2205 /* Change prop_factor of channels BCD to 8 */
2206 e1e_wphy(hw, 0x1796, 0x0008);
2207 /* Change cg_icount + enable integbp for channels BCD */
2208 e1e_wphy(hw, 0x1798, 0xD008);
2209 /* Change cg_icount + enable integbp + change prop_factor_master
2210 * to 8 for channel A
2212 e1e_wphy(hw, 0x1898, 0xD918);
2213 /* Disable AHT in Slave mode on channel A */
2214 e1e_wphy(hw, 0x187A, 0x0800);
2215 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2218 e1e_wphy(hw, 0x0019, 0x008D);
2219 /* Enable restart AN on an1000_dis change */
2220 e1e_wphy(hw, 0x001B, 0x2080);
2221 /* Enable wh_fifo read clock in 10/100 modes */
2222 e1e_wphy(hw, 0x0014, 0x0045);
2223 /* Restart AN, Speed selection is 1000 */
2224 e1e_wphy(hw, 0x0000, 0x1340);
2230 * e1000e_get_phy_type_from_id - Get PHY type from id
2231 * @phy_id: phy_id read from the phy
2233 * Returns the phy type from the id.
2235 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2237 enum e1000_phy_type phy_type = e1000_phy_unknown;
2240 case M88E1000_I_PHY_ID:
2241 case M88E1000_E_PHY_ID:
2242 case M88E1111_I_PHY_ID:
2243 case M88E1011_I_PHY_ID:
2244 phy_type = e1000_phy_m88;
2246 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2247 phy_type = e1000_phy_igp_2;
2249 case GG82563_E_PHY_ID:
2250 phy_type = e1000_phy_gg82563;
2252 case IGP03E1000_E_PHY_ID:
2253 phy_type = e1000_phy_igp_3;
2256 case IFE_PLUS_E_PHY_ID:
2257 case IFE_C_E_PHY_ID:
2258 phy_type = e1000_phy_ife;
2260 case BME1000_E_PHY_ID:
2261 case BME1000_E_PHY_ID_R2:
2262 phy_type = e1000_phy_bm;
2264 case I82578_E_PHY_ID:
2265 phy_type = e1000_phy_82578;
2267 case I82577_E_PHY_ID:
2268 phy_type = e1000_phy_82577;
2270 case I82579_E_PHY_ID:
2271 phy_type = e1000_phy_82579;
2274 phy_type = e1000_phy_i217;
2277 phy_type = e1000_phy_unknown;
2284 * e1000e_determine_phy_address - Determines PHY address.
2285 * @hw: pointer to the HW structure
2287 * This uses a trial and error method to loop through possible PHY
2288 * addresses. It tests each by reading the PHY ID registers and
2289 * checking for a match.
2291 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2295 enum e1000_phy_type phy_type = e1000_phy_unknown;
2297 hw->phy.id = phy_type;
2299 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2300 hw->phy.addr = phy_addr;
2304 e1000e_get_phy_id(hw);
2305 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2307 /* If phy_type is valid, break - we found our
2310 if (phy_type != e1000_phy_unknown)
2313 usleep_range(1000, 2000);
2318 return -E1000_ERR_PHY_TYPE;
2322 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2323 * @page: page to access
2325 * Returns the phy address for the page requested.
2327 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2331 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2338 * e1000e_write_phy_reg_bm - Write BM PHY register
2339 * @hw: pointer to the HW structure
2340 * @offset: register offset to write to
2341 * @data: data to write at register offset
2343 * Acquires semaphore, if necessary, then writes the data to PHY register
2344 * at the offset. Release any acquired semaphores before exiting.
2346 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2349 u32 page = offset >> IGP_PAGE_SHIFT;
2351 ret_val = hw->phy.ops.acquire(hw);
2355 /* Page 800 works differently than the rest so it has its own func */
2356 if (page == BM_WUC_PAGE) {
2357 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2362 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2364 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2365 u32 page_shift, page_select;
2367 /* Page select is register 31 for phy address 1 and 22 for
2368 * phy address 2 and 3. Page select is shifted only for
2371 if (hw->phy.addr == 1) {
2372 page_shift = IGP_PAGE_SHIFT;
2373 page_select = IGP01E1000_PHY_PAGE_SELECT;
2376 page_select = BM_PHY_PAGE_SELECT;
2379 /* Page is shifted left, PHY expects (page x 32) */
2380 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2381 (page << page_shift));
2386 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2390 hw->phy.ops.release(hw);
2395 * e1000e_read_phy_reg_bm - Read BM PHY register
2396 * @hw: pointer to the HW structure
2397 * @offset: register offset to be read
2398 * @data: pointer to the read data
2400 * Acquires semaphore, if necessary, then reads the PHY register at offset
2401 * and storing the retrieved information in data. Release any acquired
2402 * semaphores before exiting.
2404 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2407 u32 page = offset >> IGP_PAGE_SHIFT;
2409 ret_val = hw->phy.ops.acquire(hw);
2413 /* Page 800 works differently than the rest so it has its own func */
2414 if (page == BM_WUC_PAGE) {
2415 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2420 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2422 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2423 u32 page_shift, page_select;
2425 /* Page select is register 31 for phy address 1 and 22 for
2426 * phy address 2 and 3. Page select is shifted only for
2429 if (hw->phy.addr == 1) {
2430 page_shift = IGP_PAGE_SHIFT;
2431 page_select = IGP01E1000_PHY_PAGE_SELECT;
2434 page_select = BM_PHY_PAGE_SELECT;
2437 /* Page is shifted left, PHY expects (page x 32) */
2438 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2439 (page << page_shift));
2444 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2447 hw->phy.ops.release(hw);
2452 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2453 * @hw: pointer to the HW structure
2454 * @offset: register offset to be read
2455 * @data: pointer to the read data
2457 * Acquires semaphore, if necessary, then reads the PHY register at offset
2458 * and storing the retrieved information in data. Release any acquired
2459 * semaphores before exiting.
2461 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2464 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2466 ret_val = hw->phy.ops.acquire(hw);
2470 /* Page 800 works differently than the rest so it has its own func */
2471 if (page == BM_WUC_PAGE) {
2472 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2479 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2480 /* Page is shifted left, PHY expects (page x 32) */
2481 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2488 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2491 hw->phy.ops.release(hw);
2496 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2497 * @hw: pointer to the HW structure
2498 * @offset: register offset to write to
2499 * @data: data to write at register offset
2501 * Acquires semaphore, if necessary, then writes the data to PHY register
2502 * at the offset. Release any acquired semaphores before exiting.
2504 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2507 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2509 ret_val = hw->phy.ops.acquire(hw);
2513 /* Page 800 works differently than the rest so it has its own func */
2514 if (page == BM_WUC_PAGE) {
2515 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2522 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2523 /* Page is shifted left, PHY expects (page x 32) */
2524 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2531 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2535 hw->phy.ops.release(hw);
2540 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2541 * @hw: pointer to the HW structure
2542 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2544 * Assumes semaphore already acquired and phy_reg points to a valid memory
2545 * address to store contents of the BM_WUC_ENABLE_REG register.
2547 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2552 /* All page select, port ctrl and wakeup registers use phy address 1 */
2555 /* Select Port Control Registers page */
2556 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2558 e_dbg("Could not set Port Control page\n");
2562 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2564 e_dbg("Could not read PHY register %d.%d\n",
2565 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2569 /* Enable both PHY wakeup mode and Wakeup register page writes.
2570 * Prevent a power state change by disabling ME and Host PHY wakeup.
2573 temp |= BM_WUC_ENABLE_BIT;
2574 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2576 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2578 e_dbg("Could not write PHY register %d.%d\n",
2579 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2583 /* Select Host Wakeup Registers page - caller now able to write
2584 * registers on the Wakeup registers page
2586 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2590 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2591 * @hw: pointer to the HW structure
2592 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2594 * Restore BM_WUC_ENABLE_REG to its original value.
2596 * Assumes semaphore already acquired and *phy_reg is the contents of the
2597 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2600 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2604 /* Select Port Control Registers page */
2605 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2607 e_dbg("Could not set Port Control page\n");
2611 /* Restore 769.17 to its original value */
2612 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2614 e_dbg("Could not restore PHY register %d.%d\n",
2615 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2621 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2622 * @hw: pointer to the HW structure
2623 * @offset: register offset to be read or written
2624 * @data: pointer to the data to read or write
2625 * @read: determines if operation is read or write
2626 * @page_set: BM_WUC_PAGE already set and access enabled
2628 * Read the PHY register at offset and store the retrieved information in
2629 * data, or write data to PHY register at offset. Note the procedure to
2630 * access the PHY wakeup registers is different than reading the other PHY
2631 * registers. It works as such:
2632 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2633 * 2) Set page to 800 for host (801 if we were manageability)
2634 * 3) Write the address using the address opcode (0x11)
2635 * 4) Read or write the data using the data opcode (0x12)
2636 * 5) Restore 769.17.2 to its original value
2638 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2639 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2641 * Assumes semaphore is already acquired. When page_set==true, assumes
2642 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2643 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2645 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2646 u16 *data, bool read, bool page_set)
2649 u16 reg = BM_PHY_REG_NUM(offset);
2650 u16 page = BM_PHY_REG_PAGE(offset);
2653 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2654 if ((hw->mac.type == e1000_pchlan) &&
2655 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2656 e_dbg("Attempting to access page %d while gig enabled.\n",
2660 /* Enable access to PHY wakeup registers */
2661 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2663 e_dbg("Could not enable PHY wakeup reg access\n");
2668 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2670 /* Write the Wakeup register page offset value using opcode 0x11 */
2671 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2673 e_dbg("Could not write address opcode to page %d\n", page);
2678 /* Read the Wakeup register page value using opcode 0x12 */
2679 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2682 /* Write the Wakeup register page value using opcode 0x12 */
2683 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2688 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2693 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2699 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2700 * @hw: pointer to the HW structure
2702 * In the case of a PHY power down to save power, or to turn off link during a
2703 * driver unload, or wake on lan is not enabled, restore the link to previous
2706 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2710 /* The PHY will retain its settings across a power down/up cycle */
2711 e1e_rphy(hw, MII_BMCR, &mii_reg);
2712 mii_reg &= ~BMCR_PDOWN;
2713 e1e_wphy(hw, MII_BMCR, mii_reg);
2717 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2718 * @hw: pointer to the HW structure
2720 * In the case of a PHY power down to save power, or to turn off link during a
2721 * driver unload, or wake on lan is not enabled, restore the link to previous
2724 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2728 /* The PHY will retain its settings across a power down/up cycle */
2729 e1e_rphy(hw, MII_BMCR, &mii_reg);
2730 mii_reg |= BMCR_PDOWN;
2731 e1e_wphy(hw, MII_BMCR, mii_reg);
2732 usleep_range(1000, 2000);
2736 * __e1000_read_phy_reg_hv - Read HV PHY register
2737 * @hw: pointer to the HW structure
2738 * @offset: register offset to be read
2739 * @data: pointer to the read data
2740 * @locked: semaphore has already been acquired or not
2742 * Acquires semaphore, if necessary, then reads the PHY register at offset
2743 * and stores the retrieved information in data. Release any acquired
2744 * semaphore before exiting.
2746 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2747 bool locked, bool page_set)
2750 u16 page = BM_PHY_REG_PAGE(offset);
2751 u16 reg = BM_PHY_REG_NUM(offset);
2752 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2755 ret_val = hw->phy.ops.acquire(hw);
2760 /* Page 800 works differently than the rest so it has its own func */
2761 if (page == BM_WUC_PAGE) {
2762 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2767 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2768 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2774 if (page == HV_INTC_FC_PAGE_START)
2777 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2778 /* Page is shifted left, PHY expects (page x 32) */
2779 ret_val = e1000_set_page_igp(hw,
2780 (page << IGP_PAGE_SHIFT));
2782 hw->phy.addr = phy_addr;
2789 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2790 page << IGP_PAGE_SHIFT, reg);
2792 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
2795 hw->phy.ops.release(hw);
2801 * e1000_read_phy_reg_hv - Read HV PHY register
2802 * @hw: pointer to the HW structure
2803 * @offset: register offset to be read
2804 * @data: pointer to the read data
2806 * Acquires semaphore then reads the PHY register at offset and stores
2807 * the retrieved information in data. Release the acquired semaphore
2810 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2812 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2816 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2817 * @hw: pointer to the HW structure
2818 * @offset: register offset to be read
2819 * @data: pointer to the read data
2821 * Reads the PHY register at offset and stores the retrieved information
2822 * in data. Assumes semaphore already acquired.
2824 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2826 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2830 * e1000_read_phy_reg_page_hv - Read HV PHY register
2831 * @hw: pointer to the HW structure
2832 * @offset: register offset to write to
2833 * @data: data to write at register offset
2835 * Reads the PHY register at offset and stores the retrieved information
2836 * in data. Assumes semaphore already acquired and page already set.
2838 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2840 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2844 * __e1000_write_phy_reg_hv - Write HV PHY register
2845 * @hw: pointer to the HW structure
2846 * @offset: register offset to write to
2847 * @data: data to write at register offset
2848 * @locked: semaphore has already been acquired or not
2850 * Acquires semaphore, if necessary, then writes the data to PHY register
2851 * at the offset. Release any acquired semaphores before exiting.
2853 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2854 bool locked, bool page_set)
2857 u16 page = BM_PHY_REG_PAGE(offset);
2858 u16 reg = BM_PHY_REG_NUM(offset);
2859 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2862 ret_val = hw->phy.ops.acquire(hw);
2867 /* Page 800 works differently than the rest so it has its own func */
2868 if (page == BM_WUC_PAGE) {
2869 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2874 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2875 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2881 if (page == HV_INTC_FC_PAGE_START)
2884 /* Workaround MDIO accesses being disabled after entering IEEE
2885 * Power Down (when bit 11 of the PHY Control register is set)
2887 if ((hw->phy.type == e1000_phy_82578) &&
2888 (hw->phy.revision >= 1) &&
2889 (hw->phy.addr == 2) &&
2890 !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) {
2892 ret_val = e1000_access_phy_debug_regs_hv(hw,
2899 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2900 /* Page is shifted left, PHY expects (page x 32) */
2901 ret_val = e1000_set_page_igp(hw,
2902 (page << IGP_PAGE_SHIFT));
2904 hw->phy.addr = phy_addr;
2911 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2912 page << IGP_PAGE_SHIFT, reg);
2914 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2919 hw->phy.ops.release(hw);
2925 * e1000_write_phy_reg_hv - Write HV PHY register
2926 * @hw: pointer to the HW structure
2927 * @offset: register offset to write to
2928 * @data: data to write at register offset
2930 * Acquires semaphore then writes the data to PHY register at the offset.
2931 * Release the acquired semaphores before exiting.
2933 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2935 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
2939 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2940 * @hw: pointer to the HW structure
2941 * @offset: register offset to write to
2942 * @data: data to write at register offset
2944 * Writes the data to PHY register at the offset. Assumes semaphore
2947 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
2949 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
2953 * e1000_write_phy_reg_page_hv - Write HV PHY register
2954 * @hw: pointer to the HW structure
2955 * @offset: register offset to write to
2956 * @data: data to write at register offset
2958 * Writes the data to PHY register at the offset. Assumes semaphore
2959 * already acquired and page already set.
2961 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
2963 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
2967 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
2968 * @page: page to be accessed
2970 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2974 if (page >= HV_INTC_FC_PAGE_START)
2981 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2982 * @hw: pointer to the HW structure
2983 * @offset: register offset to be read or written
2984 * @data: pointer to the data to be read or written
2985 * @read: determines if operation is read or write
2987 * Reads the PHY register at offset and stores the retreived information
2988 * in data. Assumes semaphore already acquired. Note that the procedure
2989 * to access these regs uses the address port and data port to read/write.
2990 * These accesses done with PHY address 2 and without using pages.
2992 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
2993 u16 *data, bool read)
2999 /* This takes care of the difference with desktop vs mobile phy */
3000 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3001 I82578_ADDR_REG : I82577_ADDR_REG);
3002 data_reg = addr_reg + 1;
3004 /* All operations in this function are phy address 2 */
3007 /* masking with 0x3F to remove the page from offset */
3008 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3010 e_dbg("Could not write the Address Offset port register\n");
3014 /* Read or write the data value next */
3016 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3018 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3021 e_dbg("Could not access the Data port register\n");
3027 * e1000_link_stall_workaround_hv - Si workaround
3028 * @hw: pointer to the HW structure
3030 * This function works around a Si bug where the link partner can get
3031 * a link up indication before the PHY does. If small packets are sent
3032 * by the link partner they can be placed in the packet buffer without
3033 * being properly accounted for by the PHY and will stall preventing
3034 * further packets from being received. The workaround is to clear the
3035 * packet buffer after the PHY detects link up.
3037 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3042 if (hw->phy.type != e1000_phy_82578)
3045 /* Do not apply workaround if in PHY loopback bit 14 set */
3046 e1e_rphy(hw, MII_BMCR, &data);
3047 if (data & BMCR_LOOPBACK)
3050 /* check if link is up and at 1Gbps */
3051 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3055 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3056 BM_CS_STATUS_SPEED_MASK);
3058 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3059 BM_CS_STATUS_SPEED_1000))
3064 /* flush the packets in the fifo buffer */
3065 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
3066 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3067 HV_MUX_DATA_CTRL_FORCE_SPEED));
3071 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3075 * e1000_check_polarity_82577 - Checks the polarity.
3076 * @hw: pointer to the HW structure
3078 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3080 * Polarity is determined based on the PHY specific status register.
3082 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3084 struct e1000_phy_info *phy = &hw->phy;
3088 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3091 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3092 ? e1000_rev_polarity_reversed
3093 : e1000_rev_polarity_normal);
3099 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3100 * @hw: pointer to the HW structure
3102 * Calls the PHY setup function to force speed and duplex.
3104 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3106 struct e1000_phy_info *phy = &hw->phy;
3111 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
3115 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3117 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
3123 if (phy->autoneg_wait_to_complete) {
3124 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3126 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3132 e_dbg("Link taking longer than expected.\n");
3135 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3143 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3144 * @hw: pointer to the HW structure
3146 * Read PHY status to determine if link is up. If link is up, then
3147 * set/determine 10base-T extended distance and polarity correction. Read
3148 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3149 * determine on the cable length, local and remote receiver.
3151 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3153 struct e1000_phy_info *phy = &hw->phy;
3158 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3163 e_dbg("Phy info is only valid if link is up\n");
3164 return -E1000_ERR_CONFIG;
3167 phy->polarity_correction = true;
3169 ret_val = e1000_check_polarity_82577(hw);
3173 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3177 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3179 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3180 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3181 ret_val = hw->phy.ops.get_cable_length(hw);
3185 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
3189 phy->local_rx = (data & LPA_1000LOCALRXOK)
3190 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3192 phy->remote_rx = (data & LPA_1000REMRXOK)
3193 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3195 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3196 phy->local_rx = e1000_1000t_rx_status_undefined;
3197 phy->remote_rx = e1000_1000t_rx_status_undefined;
3204 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3205 * @hw: pointer to the HW structure
3207 * Reads the diagnostic status register and verifies result is valid before
3208 * placing it in the phy_cable_length field.
3210 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3212 struct e1000_phy_info *phy = &hw->phy;
3214 u16 phy_data, length;
3216 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3220 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3221 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
3223 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3224 return -E1000_ERR_PHY;
3226 phy->cable_length = length;