1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
31 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
32 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
33 u16 *data, bool read, bool page_set);
34 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
35 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
36 u16 *data, bool read);
38 /* Cable length tables */
39 static const u16 e1000_m88_cable_length_table[] = {
40 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
41 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
42 ARRAY_SIZE(e1000_m88_cable_length_table)
44 static const u16 e1000_igp_2_cable_length_table[] = {
45 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
46 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
47 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
48 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
49 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
50 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
51 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
53 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
54 ARRAY_SIZE(e1000_igp_2_cable_length_table)
57 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
58 * @hw: pointer to the HW structure
60 * Read the PHY management control register and check whether a PHY reset
61 * is blocked. If a reset is not blocked return 0, otherwise
62 * return E1000_BLK_PHY_RESET (12).
64 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
70 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
71 E1000_BLK_PHY_RESET : 0;
75 * e1000e_get_phy_id - Retrieve the PHY ID and revision
76 * @hw: pointer to the HW structure
78 * Reads the PHY registers and stores the PHY ID and possibly the PHY
79 * revision in the hardware structure.
81 s32 e1000e_get_phy_id(struct e1000_hw *hw)
83 struct e1000_phy_info *phy = &hw->phy;
88 if (!phy->ops.read_reg)
91 while (retry_count < 2) {
92 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
96 phy->id = (u32)(phy_id << 16);
98 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
102 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
103 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
105 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
115 * e1000e_phy_reset_dsp - Reset PHY DSP
116 * @hw: pointer to the HW structure
118 * Reset the digital signal processor.
120 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
124 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
128 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
132 * e1000e_read_phy_reg_mdic - Read MDI control register
133 * @hw: pointer to the HW structure
134 * @offset: register offset to be read
135 * @data: pointer to the read data
137 * Reads the MDI control register in the PHY at offset and stores the
138 * information read to data.
140 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
142 struct e1000_phy_info *phy = &hw->phy;
145 if (offset > MAX_PHY_REG_ADDRESS) {
146 e_dbg("PHY Address %d is out of range\n", offset);
147 return -E1000_ERR_PARAM;
150 /* Set up Op-code, Phy Address, and register offset in the MDI
151 * Control register. The MAC will take care of interfacing with the
152 * PHY to retrieve the desired data.
154 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
155 (phy->addr << E1000_MDIC_PHY_SHIFT) |
156 (E1000_MDIC_OP_READ));
160 /* Poll the ready bit to see if the MDI read completed
161 * Increasing the time out as testing showed failures with
164 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
167 if (mdic & E1000_MDIC_READY)
170 if (!(mdic & E1000_MDIC_READY)) {
171 e_dbg("MDI Read did not complete\n");
172 return -E1000_ERR_PHY;
174 if (mdic & E1000_MDIC_ERROR) {
175 e_dbg("MDI Error\n");
176 return -E1000_ERR_PHY;
180 /* Allow some time after each MDIC transaction to avoid
181 * reading duplicate data in the next MDIC transaction.
183 if (hw->mac.type == e1000_pch2lan)
190 * e1000e_write_phy_reg_mdic - Write MDI control register
191 * @hw: pointer to the HW structure
192 * @offset: register offset to write to
193 * @data: data to write to register at offset
195 * Writes data to MDI control register in the PHY at offset.
197 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
199 struct e1000_phy_info *phy = &hw->phy;
202 if (offset > MAX_PHY_REG_ADDRESS) {
203 e_dbg("PHY Address %d is out of range\n", offset);
204 return -E1000_ERR_PARAM;
207 /* Set up Op-code, Phy Address, and register offset in the MDI
208 * Control register. The MAC will take care of interfacing with the
209 * PHY to retrieve the desired data.
211 mdic = (((u32)data) |
212 (offset << E1000_MDIC_REG_SHIFT) |
213 (phy->addr << E1000_MDIC_PHY_SHIFT) |
214 (E1000_MDIC_OP_WRITE));
218 /* Poll the ready bit to see if the MDI read completed
219 * Increasing the time out as testing showed failures with
222 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
225 if (mdic & E1000_MDIC_READY)
228 if (!(mdic & E1000_MDIC_READY)) {
229 e_dbg("MDI Write did not complete\n");
230 return -E1000_ERR_PHY;
232 if (mdic & E1000_MDIC_ERROR) {
233 e_dbg("MDI Error\n");
234 return -E1000_ERR_PHY;
237 /* Allow some time after each MDIC transaction to avoid
238 * reading duplicate data in the next MDIC transaction.
240 if (hw->mac.type == e1000_pch2lan)
247 * e1000e_read_phy_reg_m88 - Read m88 PHY register
248 * @hw: pointer to the HW structure
249 * @offset: register offset to be read
250 * @data: pointer to the read data
252 * Acquires semaphore, if necessary, then reads the PHY register at offset
253 * and storing the retrieved information in data. Release any acquired
254 * semaphores before exiting.
256 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
260 ret_val = hw->phy.ops.acquire(hw);
264 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
267 hw->phy.ops.release(hw);
273 * e1000e_write_phy_reg_m88 - Write m88 PHY register
274 * @hw: pointer to the HW structure
275 * @offset: register offset to write to
276 * @data: data to write at register offset
278 * Acquires semaphore, if necessary, then writes the data to PHY register
279 * at the offset. Release any acquired semaphores before exiting.
281 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
285 ret_val = hw->phy.ops.acquire(hw);
289 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
292 hw->phy.ops.release(hw);
298 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
299 * @hw: pointer to the HW structure
300 * @page: page to set (shifted left when necessary)
302 * Sets PHY page required for PHY register access. Assumes semaphore is
303 * already acquired. Note, this function sets phy.addr to 1 so the caller
304 * must set it appropriately (if necessary) after this function returns.
306 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
308 e_dbg("Setting page 0x%x\n", page);
312 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
316 * __e1000e_read_phy_reg_igp - Read igp PHY register
317 * @hw: pointer to the HW structure
318 * @offset: register offset to be read
319 * @data: pointer to the read data
320 * @locked: semaphore has already been acquired or not
322 * Acquires semaphore, if necessary, then reads the PHY register at offset
323 * and stores the retrieved information in data. Release any acquired
324 * semaphores before exiting.
326 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
332 if (!hw->phy.ops.acquire)
335 ret_val = hw->phy.ops.acquire(hw);
340 if (offset > MAX_PHY_MULTI_PAGE_REG)
341 ret_val = e1000e_write_phy_reg_mdic(hw,
342 IGP01E1000_PHY_PAGE_SELECT,
345 ret_val = e1000e_read_phy_reg_mdic(hw,
346 MAX_PHY_REG_ADDRESS & offset,
349 hw->phy.ops.release(hw);
355 * e1000e_read_phy_reg_igp - Read igp PHY register
356 * @hw: pointer to the HW structure
357 * @offset: register offset to be read
358 * @data: pointer to the read data
360 * Acquires semaphore then reads the PHY register at offset and stores the
361 * retrieved information in data.
362 * Release the acquired semaphore before exiting.
364 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
366 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
370 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
371 * @hw: pointer to the HW structure
372 * @offset: register offset to be read
373 * @data: pointer to the read data
375 * Reads the PHY register at offset and stores the retrieved information
376 * in data. Assumes semaphore already acquired.
378 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
380 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
384 * e1000e_write_phy_reg_igp - Write igp PHY register
385 * @hw: pointer to the HW structure
386 * @offset: register offset to write to
387 * @data: data to write at register offset
388 * @locked: semaphore has already been acquired or not
390 * Acquires semaphore, if necessary, then writes the data to PHY register
391 * at the offset. Release any acquired semaphores before exiting.
393 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
399 if (!hw->phy.ops.acquire)
402 ret_val = hw->phy.ops.acquire(hw);
407 if (offset > MAX_PHY_MULTI_PAGE_REG)
408 ret_val = e1000e_write_phy_reg_mdic(hw,
409 IGP01E1000_PHY_PAGE_SELECT,
412 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
415 hw->phy.ops.release(hw);
421 * e1000e_write_phy_reg_igp - Write igp PHY register
422 * @hw: pointer to the HW structure
423 * @offset: register offset to write to
424 * @data: data to write at register offset
426 * Acquires semaphore then writes the data to PHY register
427 * at the offset. Release any acquired semaphores before exiting.
429 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
431 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
435 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
436 * @hw: pointer to the HW structure
437 * @offset: register offset to write to
438 * @data: data to write at register offset
440 * Writes the data to PHY register at the offset.
441 * Assumes semaphore already acquired.
443 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
445 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
449 * __e1000_read_kmrn_reg - Read kumeran register
450 * @hw: pointer to the HW structure
451 * @offset: register offset to be read
452 * @data: pointer to the read data
453 * @locked: semaphore has already been acquired or not
455 * Acquires semaphore, if necessary. Then reads the PHY register at offset
456 * using the kumeran interface. The information retrieved is stored in data.
457 * Release any acquired semaphores before exiting.
459 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
467 if (!hw->phy.ops.acquire)
470 ret_val = hw->phy.ops.acquire(hw);
475 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
476 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
477 ew32(KMRNCTRLSTA, kmrnctrlsta);
482 kmrnctrlsta = er32(KMRNCTRLSTA);
483 *data = (u16)kmrnctrlsta;
486 hw->phy.ops.release(hw);
492 * e1000e_read_kmrn_reg - Read kumeran register
493 * @hw: pointer to the HW structure
494 * @offset: register offset to be read
495 * @data: pointer to the read data
497 * Acquires semaphore then reads the PHY register at offset using the
498 * kumeran interface. The information retrieved is stored in data.
499 * Release the acquired semaphore before exiting.
501 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
503 return __e1000_read_kmrn_reg(hw, offset, data, false);
507 * e1000e_read_kmrn_reg_locked - Read kumeran register
508 * @hw: pointer to the HW structure
509 * @offset: register offset to be read
510 * @data: pointer to the read data
512 * Reads the PHY register at offset using the kumeran interface. The
513 * information retrieved is stored in data.
514 * Assumes semaphore already acquired.
516 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
518 return __e1000_read_kmrn_reg(hw, offset, data, true);
522 * __e1000_write_kmrn_reg - Write kumeran register
523 * @hw: pointer to the HW structure
524 * @offset: register offset to write to
525 * @data: data to write at register offset
526 * @locked: semaphore has already been acquired or not
528 * Acquires semaphore, if necessary. Then write the data to PHY register
529 * at the offset using the kumeran interface. Release any acquired semaphores
532 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
540 if (!hw->phy.ops.acquire)
543 ret_val = hw->phy.ops.acquire(hw);
548 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
549 E1000_KMRNCTRLSTA_OFFSET) | data;
550 ew32(KMRNCTRLSTA, kmrnctrlsta);
556 hw->phy.ops.release(hw);
562 * e1000e_write_kmrn_reg - Write kumeran register
563 * @hw: pointer to the HW structure
564 * @offset: register offset to write to
565 * @data: data to write at register offset
567 * Acquires semaphore then writes the data to the PHY register at the offset
568 * using the kumeran interface. Release the acquired semaphore before exiting.
570 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
572 return __e1000_write_kmrn_reg(hw, offset, data, false);
576 * e1000e_write_kmrn_reg_locked - Write kumeran register
577 * @hw: pointer to the HW structure
578 * @offset: register offset to write to
579 * @data: data to write at register offset
581 * Write the data to PHY register at the offset using the kumeran interface.
582 * Assumes semaphore already acquired.
584 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
586 return __e1000_write_kmrn_reg(hw, offset, data, true);
590 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
591 * @hw: pointer to the HW structure
593 * Sets up Master/slave mode
595 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
600 /* Resolve Master/Slave mode */
601 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
605 /* load defaults for future use */
606 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ?
607 ((phy_data & CTL1000_AS_MASTER) ?
608 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
610 switch (hw->phy.ms_type) {
611 case e1000_ms_force_master:
612 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
614 case e1000_ms_force_slave:
615 phy_data |= CTL1000_ENABLE_MASTER;
616 phy_data &= ~(CTL1000_AS_MASTER);
619 phy_data &= ~CTL1000_ENABLE_MASTER;
625 return e1e_wphy(hw, MII_CTRL1000, phy_data);
629 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
630 * @hw: pointer to the HW structure
632 * Sets up Carrier-sense on Transmit and downshift values.
634 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
639 /* Enable CRS on Tx. This must be set for half-duplex operation. */
640 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
644 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
646 /* Enable downshift */
647 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
649 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
653 /* Set MDI/MDIX mode */
654 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
657 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
663 switch (hw->phy.mdix) {
667 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
671 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
674 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
678 return e1000_set_master_slave_mode(hw);
682 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
683 * @hw: pointer to the HW structure
685 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
686 * and downshift values are set also.
688 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
690 struct e1000_phy_info *phy = &hw->phy;
694 /* Enable CRS on Tx. This must be set for half-duplex operation. */
695 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
699 /* For BM PHY this bit is downshift enable */
700 if (phy->type != e1000_phy_bm)
701 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
704 * MDI/MDI-X = 0 (default)
705 * 0 - Auto for all speeds
708 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
710 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
714 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
717 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
720 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
724 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
729 * disable_polarity_correction = 0 (default)
730 * Automatic Correction for Reversed Cable Polarity
734 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
735 if (phy->disable_polarity_correction)
736 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
738 /* Enable downshift on BM (disabled by default) */
739 if (phy->type == e1000_phy_bm) {
740 /* For 82574/82583, first disable then enable downshift */
741 if (phy->id == BME1000_E_PHY_ID_R2) {
742 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
743 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
747 /* Commit the changes. */
748 ret_val = phy->ops.commit(hw);
750 e_dbg("Error committing the PHY changes\n");
755 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
758 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
762 if ((phy->type == e1000_phy_m88) &&
763 (phy->revision < E1000_REVISION_4) &&
764 (phy->id != BME1000_E_PHY_ID_R2)) {
765 /* Force TX_CLK in the Extended PHY Specific Control Register
768 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
772 phy_data |= M88E1000_EPSCR_TX_CLK_25;
774 if ((phy->revision == 2) &&
775 (phy->id == M88E1111_I_PHY_ID)) {
776 /* 82573L PHY - set the downshift counter to 5x. */
777 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
778 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
780 /* Configure Master and Slave downshift values */
781 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
782 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
783 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
784 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
786 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
791 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
792 /* Set PHY page 0, register 29 to 0x0003 */
793 ret_val = e1e_wphy(hw, 29, 0x0003);
797 /* Set PHY page 0, register 30 to 0x0000 */
798 ret_val = e1e_wphy(hw, 30, 0x0000);
803 /* Commit the changes. */
804 if (phy->ops.commit) {
805 ret_val = phy->ops.commit(hw);
807 e_dbg("Error committing the PHY changes\n");
812 if (phy->type == e1000_phy_82578) {
813 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
817 /* 82578 PHY - set the downshift count to 1x. */
818 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
819 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
820 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
829 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
830 * @hw: pointer to the HW structure
832 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
835 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
837 struct e1000_phy_info *phy = &hw->phy;
841 ret_val = e1000_phy_hw_reset(hw);
843 e_dbg("Error resetting the PHY.\n");
847 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
848 * timeout issues when LFS is enabled.
852 /* disable lplu d0 during driver init */
853 if (hw->phy.ops.set_d0_lplu_state) {
854 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
856 e_dbg("Error Disabling LPLU D0\n");
860 /* Configure mdi-mdix settings */
861 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
865 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
869 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
872 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
876 data |= IGP01E1000_PSCR_AUTO_MDIX;
879 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
883 /* set auto-master slave resolution settings */
884 if (hw->mac.autoneg) {
885 /* when autonegotiation advertisement is only 1000Mbps then we
886 * should disable SmartSpeed and enable Auto MasterSlave
887 * resolution as hardware default.
889 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
890 /* Disable SmartSpeed */
891 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
896 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
897 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
902 /* Set auto Master/Slave resolution process */
903 ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
907 data &= ~CTL1000_ENABLE_MASTER;
908 ret_val = e1e_wphy(hw, MII_CTRL1000, data);
913 ret_val = e1000_set_master_slave_mode(hw);
920 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
921 * @hw: pointer to the HW structure
923 * Reads the MII auto-neg advertisement register and/or the 1000T control
924 * register and if the PHY is already setup for auto-negotiation, then
925 * return successful. Otherwise, setup advertisement and flow control to
926 * the appropriate values for the wanted auto-negotiation.
928 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
930 struct e1000_phy_info *phy = &hw->phy;
932 u16 mii_autoneg_adv_reg;
933 u16 mii_1000t_ctrl_reg = 0;
935 phy->autoneg_advertised &= phy->autoneg_mask;
937 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
938 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg);
942 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
943 /* Read the MII 1000Base-T Control Register (Address 9). */
944 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
949 /* Need to parse both autoneg_advertised and fc and set up
950 * the appropriate PHY registers. First we will parse for
951 * autoneg_advertised software override. Since we can advertise
952 * a plethora of combinations, we need to check each bit
956 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
957 * Advertisement Register (Address 4) and the 1000 mb speed bits in
958 * the 1000Base-T Control Register (Address 9).
960 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
962 ADVERTISE_10FULL | ADVERTISE_10HALF);
963 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
965 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
967 /* Do we want to advertise 10 Mb Half Duplex? */
968 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
969 e_dbg("Advertise 10mb Half duplex\n");
970 mii_autoneg_adv_reg |= ADVERTISE_10HALF;
973 /* Do we want to advertise 10 Mb Full Duplex? */
974 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
975 e_dbg("Advertise 10mb Full duplex\n");
976 mii_autoneg_adv_reg |= ADVERTISE_10FULL;
979 /* Do we want to advertise 100 Mb Half Duplex? */
980 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
981 e_dbg("Advertise 100mb Half duplex\n");
982 mii_autoneg_adv_reg |= ADVERTISE_100HALF;
985 /* Do we want to advertise 100 Mb Full Duplex? */
986 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
987 e_dbg("Advertise 100mb Full duplex\n");
988 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
991 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
992 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
993 e_dbg("Advertise 1000mb Half duplex request denied!\n");
995 /* Do we want to advertise 1000 Mb Full Duplex? */
996 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
997 e_dbg("Advertise 1000mb Full duplex\n");
998 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
1001 /* Check for a software override of the flow control settings, and
1002 * setup the PHY advertisement registers accordingly. If
1003 * auto-negotiation is enabled, then software will have to set the
1004 * "PAUSE" bits to the correct value in the Auto-Negotiation
1005 * Advertisement Register (MII_ADVERTISE) and re-start auto-
1008 * The possible values of the "fc" parameter are:
1009 * 0: Flow control is completely disabled
1010 * 1: Rx flow control is enabled (we can receive pause frames
1011 * but not send pause frames).
1012 * 2: Tx flow control is enabled (we can send pause frames
1013 * but we do not support receiving pause frames).
1014 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1015 * other: No software override. The flow control configuration
1016 * in the EEPROM is used.
1018 switch (hw->fc.current_mode) {
1020 /* Flow control (Rx & Tx) is completely disabled by a
1021 * software over-ride.
1023 mii_autoneg_adv_reg &=
1024 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1026 case e1000_fc_rx_pause:
1027 /* Rx Flow control is enabled, and Tx Flow control is
1028 * disabled, by a software over-ride.
1030 * Since there really isn't a way to advertise that we are
1031 * capable of Rx Pause ONLY, we will advertise that we
1032 * support both symmetric and asymmetric Rx PAUSE. Later
1033 * (in e1000e_config_fc_after_link_up) we will disable the
1034 * hw's ability to send PAUSE frames.
1036 mii_autoneg_adv_reg |=
1037 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1039 case e1000_fc_tx_pause:
1040 /* Tx Flow control is enabled, and Rx Flow control is
1041 * disabled, by a software over-ride.
1043 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
1044 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
1047 /* Flow control (both Rx and Tx) is enabled by a software
1050 mii_autoneg_adv_reg |=
1051 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1054 e_dbg("Flow control param set incorrectly\n");
1055 return -E1000_ERR_CONFIG;
1058 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1062 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1064 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1065 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
1071 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1072 * @hw: pointer to the HW structure
1074 * Performs initial bounds checking on autoneg advertisement parameter, then
1075 * configure to advertise the full capability. Setup the PHY to autoneg
1076 * and restart the negotiation process between the link partner. If
1077 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1079 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1081 struct e1000_phy_info *phy = &hw->phy;
1085 /* Perform some bounds checking on the autoneg advertisement
1088 phy->autoneg_advertised &= phy->autoneg_mask;
1090 /* If autoneg_advertised is zero, we assume it was not defaulted
1091 * by the calling code so we set to advertise full capability.
1093 if (!phy->autoneg_advertised)
1094 phy->autoneg_advertised = phy->autoneg_mask;
1096 e_dbg("Reconfiguring auto-neg advertisement params\n");
1097 ret_val = e1000_phy_setup_autoneg(hw);
1099 e_dbg("Error Setting up Auto-Negotiation\n");
1102 e_dbg("Restarting Auto-Neg\n");
1104 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1105 * the Auto Neg Restart bit in the PHY control register.
1107 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1111 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1112 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1116 /* Does the user want to wait for Auto-Neg to complete here, or
1117 * check at a later time (for example, callback routine).
1119 if (phy->autoneg_wait_to_complete) {
1120 ret_val = e1000_wait_autoneg(hw);
1122 e_dbg("Error while waiting for autoneg to complete\n");
1127 hw->mac.get_link_status = true;
1133 * e1000e_setup_copper_link - Configure copper link settings
1134 * @hw: pointer to the HW structure
1136 * Calls the appropriate function to configure the link for auto-neg or forced
1137 * speed and duplex. Then we check for link, once link is established calls
1138 * to configure collision distance and flow control are called. If link is
1139 * not established, we return -E1000_ERR_PHY (-2).
1141 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1146 if (hw->mac.autoneg) {
1147 /* Setup autoneg and flow control advertisement and perform
1150 ret_val = e1000_copper_link_autoneg(hw);
1154 /* PHY will be set to 10H, 10F, 100H or 100F
1155 * depending on user settings.
1157 e_dbg("Forcing Speed and Duplex\n");
1158 ret_val = hw->phy.ops.force_speed_duplex(hw);
1160 e_dbg("Error Forcing Speed and Duplex\n");
1165 /* Check link status. Wait up to 100 microseconds for link to become
1168 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1174 e_dbg("Valid link established!!!\n");
1175 hw->mac.ops.config_collision_dist(hw);
1176 ret_val = e1000e_config_fc_after_link_up(hw);
1178 e_dbg("Unable to establish link!!!\n");
1185 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1186 * @hw: pointer to the HW structure
1188 * Calls the PHY setup function to force speed and duplex. Clears the
1189 * auto-crossover to force MDI manually. Waits for link and returns
1190 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1192 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1194 struct e1000_phy_info *phy = &hw->phy;
1199 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1203 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1205 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1209 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1210 * forced whenever speed and duplex are forced.
1212 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1216 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1217 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1219 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1223 e_dbg("IGP PSCR: %X\n", phy_data);
1227 if (phy->autoneg_wait_to_complete) {
1228 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1230 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1236 e_dbg("Link taking longer than expected.\n");
1239 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1247 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1248 * @hw: pointer to the HW structure
1250 * Calls the PHY setup function to force speed and duplex. Clears the
1251 * auto-crossover to force MDI manually. Resets the PHY to commit the
1252 * changes. If time expires while waiting for link up, we reset the DSP.
1253 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1254 * successful completion, else return corresponding error code.
1256 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1258 struct e1000_phy_info *phy = &hw->phy;
1263 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1264 * forced whenever speed and duplex are forced.
1266 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1270 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1271 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1275 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1277 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1281 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1283 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1287 /* Reset the phy to commit changes. */
1288 if (hw->phy.ops.commit) {
1289 ret_val = hw->phy.ops.commit(hw);
1294 if (phy->autoneg_wait_to_complete) {
1295 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1297 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1303 if (hw->phy.type != e1000_phy_m88) {
1304 e_dbg("Link taking longer than expected.\n");
1306 /* We didn't get link.
1307 * Reset the DSP and cross our fingers.
1309 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1313 ret_val = e1000e_phy_reset_dsp(hw);
1320 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1326 if (hw->phy.type != e1000_phy_m88)
1329 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1333 /* Resetting the phy means we need to re-force TX_CLK in the
1334 * Extended PHY Specific Control Register to 25MHz clock from
1335 * the reset value of 2.5MHz.
1337 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1338 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1342 /* In addition, we must re-enable CRS on Tx for both half and full
1345 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1349 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1350 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1356 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1357 * @hw: pointer to the HW structure
1359 * Forces the speed and duplex settings of the PHY.
1360 * This is a function pointer entry point only called by
1361 * PHY setup routines.
1363 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1365 struct e1000_phy_info *phy = &hw->phy;
1370 ret_val = e1e_rphy(hw, MII_BMCR, &data);
1374 e1000e_phy_force_speed_duplex_setup(hw, &data);
1376 ret_val = e1e_wphy(hw, MII_BMCR, data);
1380 /* Disable MDI-X support for 10/100 */
1381 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1385 data &= ~IFE_PMC_AUTO_MDIX;
1386 data &= ~IFE_PMC_FORCE_MDIX;
1388 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1392 e_dbg("IFE PMC: %X\n", data);
1396 if (phy->autoneg_wait_to_complete) {
1397 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1399 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1405 e_dbg("Link taking longer than expected.\n");
1408 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1418 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1419 * @hw: pointer to the HW structure
1420 * @phy_ctrl: pointer to current value of MII_BMCR
1422 * Forces speed and duplex on the PHY by doing the following: disable flow
1423 * control, force speed/duplex on the MAC, disable auto speed detection,
1424 * disable auto-negotiation, configure duplex, configure speed, configure
1425 * the collision distance, write configuration to CTRL register. The
1426 * caller must write to the MII_BMCR register for these settings to
1429 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1431 struct e1000_mac_info *mac = &hw->mac;
1434 /* Turn off flow control when forcing speed/duplex */
1435 hw->fc.current_mode = e1000_fc_none;
1437 /* Force speed/duplex on the mac */
1439 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1440 ctrl &= ~E1000_CTRL_SPD_SEL;
1442 /* Disable Auto Speed Detection */
1443 ctrl &= ~E1000_CTRL_ASDE;
1445 /* Disable autoneg on the phy */
1446 *phy_ctrl &= ~BMCR_ANENABLE;
1448 /* Forcing Full or Half Duplex? */
1449 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1450 ctrl &= ~E1000_CTRL_FD;
1451 *phy_ctrl &= ~BMCR_FULLDPLX;
1452 e_dbg("Half Duplex\n");
1454 ctrl |= E1000_CTRL_FD;
1455 *phy_ctrl |= BMCR_FULLDPLX;
1456 e_dbg("Full Duplex\n");
1459 /* Forcing 10mb or 100mb? */
1460 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1461 ctrl |= E1000_CTRL_SPD_100;
1462 *phy_ctrl |= BMCR_SPEED100;
1463 *phy_ctrl &= ~BMCR_SPEED1000;
1464 e_dbg("Forcing 100mb\n");
1466 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1467 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
1468 e_dbg("Forcing 10mb\n");
1471 hw->mac.ops.config_collision_dist(hw);
1477 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1478 * @hw: pointer to the HW structure
1479 * @active: boolean used to enable/disable lplu
1481 * Success returns 0, Failure returns 1
1483 * The low power link up (lplu) state is set to the power management level D3
1484 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1485 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1486 * is used during Dx states where the power conservation is most important.
1487 * During driver activity, SmartSpeed should be enabled so performance is
1490 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1492 struct e1000_phy_info *phy = &hw->phy;
1496 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1501 data &= ~IGP02E1000_PM_D3_LPLU;
1502 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1505 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1506 * during Dx states where the power conservation is most
1507 * important. During driver activity we should enable
1508 * SmartSpeed, so performance is maintained.
1510 if (phy->smart_speed == e1000_smart_speed_on) {
1511 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1516 data |= IGP01E1000_PSCFR_SMART_SPEED;
1517 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1521 } else if (phy->smart_speed == e1000_smart_speed_off) {
1522 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1527 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1528 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1533 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1534 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1535 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1536 data |= IGP02E1000_PM_D3_LPLU;
1537 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1541 /* When LPLU is enabled, we should disable SmartSpeed */
1542 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1546 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1547 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1554 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1555 * @hw: pointer to the HW structure
1557 * Success returns 0, Failure returns 1
1559 * A downshift is detected by querying the PHY link health.
1561 s32 e1000e_check_downshift(struct e1000_hw *hw)
1563 struct e1000_phy_info *phy = &hw->phy;
1565 u16 phy_data, offset, mask;
1567 switch (phy->type) {
1569 case e1000_phy_gg82563:
1571 case e1000_phy_82578:
1572 offset = M88E1000_PHY_SPEC_STATUS;
1573 mask = M88E1000_PSSR_DOWNSHIFT;
1575 case e1000_phy_igp_2:
1576 case e1000_phy_igp_3:
1577 offset = IGP01E1000_PHY_LINK_HEALTH;
1578 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1581 /* speed downshift not supported */
1582 phy->speed_downgraded = false;
1586 ret_val = e1e_rphy(hw, offset, &phy_data);
1589 phy->speed_downgraded = !!(phy_data & mask);
1595 * e1000_check_polarity_m88 - Checks the polarity.
1596 * @hw: pointer to the HW structure
1598 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1600 * Polarity is determined based on the PHY specific status register.
1602 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1604 struct e1000_phy_info *phy = &hw->phy;
1608 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1611 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
1612 ? e1000_rev_polarity_reversed
1613 : e1000_rev_polarity_normal);
1619 * e1000_check_polarity_igp - Checks the polarity.
1620 * @hw: pointer to the HW structure
1622 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1624 * Polarity is determined based on the PHY port status register, and the
1625 * current speed (since there is no polarity at 100Mbps).
1627 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1629 struct e1000_phy_info *phy = &hw->phy;
1631 u16 data, offset, mask;
1633 /* Polarity is determined based on the speed of
1636 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1640 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1641 IGP01E1000_PSSR_SPEED_1000MBPS) {
1642 offset = IGP01E1000_PHY_PCS_INIT_REG;
1643 mask = IGP01E1000_PHY_POLARITY_MASK;
1645 /* This really only applies to 10Mbps since
1646 * there is no polarity for 100Mbps (always 0).
1648 offset = IGP01E1000_PHY_PORT_STATUS;
1649 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1652 ret_val = e1e_rphy(hw, offset, &data);
1655 phy->cable_polarity = ((data & mask)
1656 ? e1000_rev_polarity_reversed
1657 : e1000_rev_polarity_normal);
1663 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1664 * @hw: pointer to the HW structure
1666 * Polarity is determined on the polarity reversal feature being enabled.
1668 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1670 struct e1000_phy_info *phy = &hw->phy;
1672 u16 phy_data, offset, mask;
1674 /* Polarity is determined based on the reversal feature being enabled.
1676 if (phy->polarity_correction) {
1677 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1678 mask = IFE_PESC_POLARITY_REVERSED;
1680 offset = IFE_PHY_SPECIAL_CONTROL;
1681 mask = IFE_PSC_FORCE_POLARITY;
1684 ret_val = e1e_rphy(hw, offset, &phy_data);
1687 phy->cable_polarity = ((phy_data & mask)
1688 ? e1000_rev_polarity_reversed
1689 : e1000_rev_polarity_normal);
1695 * e1000_wait_autoneg - Wait for auto-neg completion
1696 * @hw: pointer to the HW structure
1698 * Waits for auto-negotiation to complete or for the auto-negotiation time
1699 * limit to expire, which ever happens first.
1701 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1706 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1707 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1708 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1711 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1714 if (phy_status & BMSR_ANEGCOMPLETE)
1719 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1726 * e1000e_phy_has_link_generic - Polls PHY for link
1727 * @hw: pointer to the HW structure
1728 * @iterations: number of times to poll for link
1729 * @usec_interval: delay between polling attempts
1730 * @success: pointer to whether polling was successful or not
1732 * Polls the PHY status register for link, 'iterations' number of times.
1734 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1735 u32 usec_interval, bool *success)
1740 for (i = 0; i < iterations; i++) {
1741 /* Some PHYs require the MII_BMSR register to be read
1742 * twice due to the link bit being sticky. No harm doing
1743 * it across the board.
1745 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1747 /* If the first read fails, another entity may have
1748 * ownership of the resources, wait and try again to
1749 * see if they have relinquished the resources yet.
1751 udelay(usec_interval);
1752 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1755 if (phy_status & BMSR_LSTATUS)
1757 if (usec_interval >= 1000)
1758 mdelay(usec_interval / 1000);
1760 udelay(usec_interval);
1763 *success = (i < iterations);
1769 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1770 * @hw: pointer to the HW structure
1772 * Reads the PHY specific status register to retrieve the cable length
1773 * information. The cable length is determined by averaging the minimum and
1774 * maximum values to get the "average" cable length. The m88 PHY has four
1775 * possible cable length values, which are:
1776 * Register Value Cable Length
1780 * 3 110 - 140 meters
1783 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1785 struct e1000_phy_info *phy = &hw->phy;
1787 u16 phy_data, index;
1789 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1793 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1794 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
1796 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1797 return -E1000_ERR_PHY;
1799 phy->min_cable_length = e1000_m88_cable_length_table[index];
1800 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1802 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1808 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1809 * @hw: pointer to the HW structure
1811 * The automatic gain control (agc) normalizes the amplitude of the
1812 * received signal, adjusting for the attenuation produced by the
1813 * cable. By reading the AGC registers, which represent the
1814 * combination of coarse and fine gain value, the value can be put
1815 * into a lookup table to obtain the approximate cable length
1818 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1820 struct e1000_phy_info *phy = &hw->phy;
1822 u16 phy_data, i, agc_value = 0;
1823 u16 cur_agc_index, max_agc_index = 0;
1824 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1825 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1826 IGP02E1000_PHY_AGC_A,
1827 IGP02E1000_PHY_AGC_B,
1828 IGP02E1000_PHY_AGC_C,
1829 IGP02E1000_PHY_AGC_D
1832 /* Read the AGC registers for all channels */
1833 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1834 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1838 /* Getting bits 15:9, which represent the combination of
1839 * coarse and fine gain values. The result is a number
1840 * that can be put into the lookup table to obtain the
1841 * approximate cable length.
1843 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1844 IGP02E1000_AGC_LENGTH_MASK);
1846 /* Array index bound check. */
1847 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1848 (cur_agc_index == 0))
1849 return -E1000_ERR_PHY;
1851 /* Remove min & max AGC values from calculation. */
1852 if (e1000_igp_2_cable_length_table[min_agc_index] >
1853 e1000_igp_2_cable_length_table[cur_agc_index])
1854 min_agc_index = cur_agc_index;
1855 if (e1000_igp_2_cable_length_table[max_agc_index] <
1856 e1000_igp_2_cable_length_table[cur_agc_index])
1857 max_agc_index = cur_agc_index;
1859 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1862 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1863 e1000_igp_2_cable_length_table[max_agc_index]);
1864 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1866 /* Calculate cable length with the error range of +/- 10 meters. */
1867 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1868 (agc_value - IGP02E1000_AGC_RANGE) : 0);
1869 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1871 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1877 * e1000e_get_phy_info_m88 - Retrieve PHY information
1878 * @hw: pointer to the HW structure
1880 * Valid for only copper links. Read the PHY status register (sticky read)
1881 * to verify that link is up. Read the PHY special control register to
1882 * determine the polarity and 10base-T extended distance. Read the PHY
1883 * special status register to determine MDI/MDIx and current speed. If
1884 * speed is 1000, then determine cable length, local and remote receiver.
1886 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1888 struct e1000_phy_info *phy = &hw->phy;
1893 if (phy->media_type != e1000_media_type_copper) {
1894 e_dbg("Phy info is only valid for copper media\n");
1895 return -E1000_ERR_CONFIG;
1898 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1903 e_dbg("Phy info is only valid if link is up\n");
1904 return -E1000_ERR_CONFIG;
1907 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1911 phy->polarity_correction = !!(phy_data &
1912 M88E1000_PSCR_POLARITY_REVERSAL);
1914 ret_val = e1000_check_polarity_m88(hw);
1918 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1922 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1924 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1925 ret_val = hw->phy.ops.get_cable_length(hw);
1929 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data);
1933 phy->local_rx = (phy_data & LPA_1000LOCALRXOK)
1934 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1936 phy->remote_rx = (phy_data & LPA_1000REMRXOK)
1937 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1939 /* Set values to "undefined" */
1940 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1941 phy->local_rx = e1000_1000t_rx_status_undefined;
1942 phy->remote_rx = e1000_1000t_rx_status_undefined;
1949 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1950 * @hw: pointer to the HW structure
1952 * Read PHY status to determine if link is up. If link is up, then
1953 * set/determine 10base-T extended distance and polarity correction. Read
1954 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1955 * determine on the cable length, local and remote receiver.
1957 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1959 struct e1000_phy_info *phy = &hw->phy;
1964 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1969 e_dbg("Phy info is only valid if link is up\n");
1970 return -E1000_ERR_CONFIG;
1973 phy->polarity_correction = true;
1975 ret_val = e1000_check_polarity_igp(hw);
1979 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1983 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
1985 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1986 IGP01E1000_PSSR_SPEED_1000MBPS) {
1987 ret_val = phy->ops.get_cable_length(hw);
1991 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
1995 phy->local_rx = (data & LPA_1000LOCALRXOK)
1996 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1998 phy->remote_rx = (data & LPA_1000REMRXOK)
1999 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2001 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2002 phy->local_rx = e1000_1000t_rx_status_undefined;
2003 phy->remote_rx = e1000_1000t_rx_status_undefined;
2010 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2011 * @hw: pointer to the HW structure
2013 * Populates "phy" structure with various feature states.
2015 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2017 struct e1000_phy_info *phy = &hw->phy;
2022 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2027 e_dbg("Phy info is only valid if link is up\n");
2028 return -E1000_ERR_CONFIG;
2031 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2034 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2036 if (phy->polarity_correction) {
2037 ret_val = e1000_check_polarity_ife(hw);
2041 /* Polarity is forced */
2042 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2043 ? e1000_rev_polarity_reversed
2044 : e1000_rev_polarity_normal);
2047 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2051 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2053 /* The following parameters are undefined for 10/100 operation. */
2054 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2055 phy->local_rx = e1000_1000t_rx_status_undefined;
2056 phy->remote_rx = e1000_1000t_rx_status_undefined;
2062 * e1000e_phy_sw_reset - PHY software reset
2063 * @hw: pointer to the HW structure
2065 * Does a software reset of the PHY by reading the PHY control register and
2066 * setting/write the control register reset bit to the PHY.
2068 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2073 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
2077 phy_ctrl |= BMCR_RESET;
2078 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
2088 * e1000e_phy_hw_reset_generic - PHY hardware reset
2089 * @hw: pointer to the HW structure
2091 * Verify the reset block is not blocking us from resetting. Acquire
2092 * semaphore (if necessary) and read/set/write the device control reset
2093 * bit in the PHY. Wait the appropriate delay time for the device to
2094 * reset and release the semaphore (if necessary).
2096 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2098 struct e1000_phy_info *phy = &hw->phy;
2102 if (phy->ops.check_reset_block) {
2103 ret_val = phy->ops.check_reset_block(hw);
2108 ret_val = phy->ops.acquire(hw);
2113 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2116 udelay(phy->reset_delay_us);
2123 phy->ops.release(hw);
2125 return phy->ops.get_cfg_done(hw);
2129 * e1000e_get_cfg_done_generic - Generic configuration done
2130 * @hw: pointer to the HW structure
2132 * Generic function to wait 10 milli-seconds for configuration to complete
2133 * and return success.
2135 s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
2143 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2144 * @hw: pointer to the HW structure
2146 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2148 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2150 e_dbg("Running IGP 3 PHY init script\n");
2152 /* PHY init IGP 3 */
2153 /* Enable rise/fall, 10-mode work in class-A */
2154 e1e_wphy(hw, 0x2F5B, 0x9018);
2155 /* Remove all caps from Replica path filter */
2156 e1e_wphy(hw, 0x2F52, 0x0000);
2157 /* Bias trimming for ADC, AFE and Driver (Default) */
2158 e1e_wphy(hw, 0x2FB1, 0x8B24);
2159 /* Increase Hybrid poly bias */
2160 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2161 /* Add 4% to Tx amplitude in Gig mode */
2162 e1e_wphy(hw, 0x2010, 0x10B0);
2163 /* Disable trimming (TTT) */
2164 e1e_wphy(hw, 0x2011, 0x0000);
2165 /* Poly DC correction to 94.6% + 2% for all channels */
2166 e1e_wphy(hw, 0x20DD, 0x249A);
2167 /* ABS DC correction to 95.9% */
2168 e1e_wphy(hw, 0x20DE, 0x00D3);
2169 /* BG temp curve trim */
2170 e1e_wphy(hw, 0x28B4, 0x04CE);
2171 /* Increasing ADC OPAMP stage 1 currents to max */
2172 e1e_wphy(hw, 0x2F70, 0x29E4);
2173 /* Force 1000 ( required for enabling PHY regs configuration) */
2174 e1e_wphy(hw, 0x0000, 0x0140);
2175 /* Set upd_freq to 6 */
2176 e1e_wphy(hw, 0x1F30, 0x1606);
2178 e1e_wphy(hw, 0x1F31, 0xB814);
2179 /* Disable adaptive fixed FFE (Default) */
2180 e1e_wphy(hw, 0x1F35, 0x002A);
2181 /* Enable FFE hysteresis */
2182 e1e_wphy(hw, 0x1F3E, 0x0067);
2183 /* Fixed FFE for short cable lengths */
2184 e1e_wphy(hw, 0x1F54, 0x0065);
2185 /* Fixed FFE for medium cable lengths */
2186 e1e_wphy(hw, 0x1F55, 0x002A);
2187 /* Fixed FFE for long cable lengths */
2188 e1e_wphy(hw, 0x1F56, 0x002A);
2189 /* Enable Adaptive Clip Threshold */
2190 e1e_wphy(hw, 0x1F72, 0x3FB0);
2191 /* AHT reset limit to 1 */
2192 e1e_wphy(hw, 0x1F76, 0xC0FF);
2193 /* Set AHT master delay to 127 msec */
2194 e1e_wphy(hw, 0x1F77, 0x1DEC);
2195 /* Set scan bits for AHT */
2196 e1e_wphy(hw, 0x1F78, 0xF9EF);
2197 /* Set AHT Preset bits */
2198 e1e_wphy(hw, 0x1F79, 0x0210);
2199 /* Change integ_factor of channel A to 3 */
2200 e1e_wphy(hw, 0x1895, 0x0003);
2201 /* Change prop_factor of channels BCD to 8 */
2202 e1e_wphy(hw, 0x1796, 0x0008);
2203 /* Change cg_icount + enable integbp for channels BCD */
2204 e1e_wphy(hw, 0x1798, 0xD008);
2205 /* Change cg_icount + enable integbp + change prop_factor_master
2206 * to 8 for channel A
2208 e1e_wphy(hw, 0x1898, 0xD918);
2209 /* Disable AHT in Slave mode on channel A */
2210 e1e_wphy(hw, 0x187A, 0x0800);
2211 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2214 e1e_wphy(hw, 0x0019, 0x008D);
2215 /* Enable restart AN on an1000_dis change */
2216 e1e_wphy(hw, 0x001B, 0x2080);
2217 /* Enable wh_fifo read clock in 10/100 modes */
2218 e1e_wphy(hw, 0x0014, 0x0045);
2219 /* Restart AN, Speed selection is 1000 */
2220 e1e_wphy(hw, 0x0000, 0x1340);
2226 * e1000e_get_phy_type_from_id - Get PHY type from id
2227 * @phy_id: phy_id read from the phy
2229 * Returns the phy type from the id.
2231 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2233 enum e1000_phy_type phy_type = e1000_phy_unknown;
2236 case M88E1000_I_PHY_ID:
2237 case M88E1000_E_PHY_ID:
2238 case M88E1111_I_PHY_ID:
2239 case M88E1011_I_PHY_ID:
2240 phy_type = e1000_phy_m88;
2242 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2243 phy_type = e1000_phy_igp_2;
2245 case GG82563_E_PHY_ID:
2246 phy_type = e1000_phy_gg82563;
2248 case IGP03E1000_E_PHY_ID:
2249 phy_type = e1000_phy_igp_3;
2252 case IFE_PLUS_E_PHY_ID:
2253 case IFE_C_E_PHY_ID:
2254 phy_type = e1000_phy_ife;
2256 case BME1000_E_PHY_ID:
2257 case BME1000_E_PHY_ID_R2:
2258 phy_type = e1000_phy_bm;
2260 case I82578_E_PHY_ID:
2261 phy_type = e1000_phy_82578;
2263 case I82577_E_PHY_ID:
2264 phy_type = e1000_phy_82577;
2266 case I82579_E_PHY_ID:
2267 phy_type = e1000_phy_82579;
2270 phy_type = e1000_phy_i217;
2273 phy_type = e1000_phy_unknown;
2280 * e1000e_determine_phy_address - Determines PHY address.
2281 * @hw: pointer to the HW structure
2283 * This uses a trial and error method to loop through possible PHY
2284 * addresses. It tests each by reading the PHY ID registers and
2285 * checking for a match.
2287 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2291 enum e1000_phy_type phy_type = e1000_phy_unknown;
2293 hw->phy.id = phy_type;
2295 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2296 hw->phy.addr = phy_addr;
2300 e1000e_get_phy_id(hw);
2301 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2303 /* If phy_type is valid, break - we found our
2306 if (phy_type != e1000_phy_unknown)
2309 usleep_range(1000, 2000);
2314 return -E1000_ERR_PHY_TYPE;
2318 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2319 * @page: page to access
2321 * Returns the phy address for the page requested.
2323 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2327 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2334 * e1000e_write_phy_reg_bm - Write BM PHY register
2335 * @hw: pointer to the HW structure
2336 * @offset: register offset to write to
2337 * @data: data to write at register offset
2339 * Acquires semaphore, if necessary, then writes the data to PHY register
2340 * at the offset. Release any acquired semaphores before exiting.
2342 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2345 u32 page = offset >> IGP_PAGE_SHIFT;
2347 ret_val = hw->phy.ops.acquire(hw);
2351 /* Page 800 works differently than the rest so it has its own func */
2352 if (page == BM_WUC_PAGE) {
2353 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2358 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2360 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2361 u32 page_shift, page_select;
2363 /* Page select is register 31 for phy address 1 and 22 for
2364 * phy address 2 and 3. Page select is shifted only for
2367 if (hw->phy.addr == 1) {
2368 page_shift = IGP_PAGE_SHIFT;
2369 page_select = IGP01E1000_PHY_PAGE_SELECT;
2372 page_select = BM_PHY_PAGE_SELECT;
2375 /* Page is shifted left, PHY expects (page x 32) */
2376 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2377 (page << page_shift));
2382 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2386 hw->phy.ops.release(hw);
2391 * e1000e_read_phy_reg_bm - Read BM PHY register
2392 * @hw: pointer to the HW structure
2393 * @offset: register offset to be read
2394 * @data: pointer to the read data
2396 * Acquires semaphore, if necessary, then reads the PHY register at offset
2397 * and storing the retrieved information in data. Release any acquired
2398 * semaphores before exiting.
2400 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2403 u32 page = offset >> IGP_PAGE_SHIFT;
2405 ret_val = hw->phy.ops.acquire(hw);
2409 /* Page 800 works differently than the rest so it has its own func */
2410 if (page == BM_WUC_PAGE) {
2411 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2416 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2418 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2419 u32 page_shift, page_select;
2421 /* Page select is register 31 for phy address 1 and 22 for
2422 * phy address 2 and 3. Page select is shifted only for
2425 if (hw->phy.addr == 1) {
2426 page_shift = IGP_PAGE_SHIFT;
2427 page_select = IGP01E1000_PHY_PAGE_SELECT;
2430 page_select = BM_PHY_PAGE_SELECT;
2433 /* Page is shifted left, PHY expects (page x 32) */
2434 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2435 (page << page_shift));
2440 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2443 hw->phy.ops.release(hw);
2448 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2449 * @hw: pointer to the HW structure
2450 * @offset: register offset to be read
2451 * @data: pointer to the read data
2453 * Acquires semaphore, if necessary, then reads the PHY register at offset
2454 * and storing the retrieved information in data. Release any acquired
2455 * semaphores before exiting.
2457 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2460 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2462 ret_val = hw->phy.ops.acquire(hw);
2466 /* Page 800 works differently than the rest so it has its own func */
2467 if (page == BM_WUC_PAGE) {
2468 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2475 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2476 /* Page is shifted left, PHY expects (page x 32) */
2477 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2484 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2487 hw->phy.ops.release(hw);
2492 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2493 * @hw: pointer to the HW structure
2494 * @offset: register offset to write to
2495 * @data: data to write at register offset
2497 * Acquires semaphore, if necessary, then writes the data to PHY register
2498 * at the offset. Release any acquired semaphores before exiting.
2500 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2503 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2505 ret_val = hw->phy.ops.acquire(hw);
2509 /* Page 800 works differently than the rest so it has its own func */
2510 if (page == BM_WUC_PAGE) {
2511 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2518 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2519 /* Page is shifted left, PHY expects (page x 32) */
2520 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2527 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2531 hw->phy.ops.release(hw);
2536 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2537 * @hw: pointer to the HW structure
2538 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2540 * Assumes semaphore already acquired and phy_reg points to a valid memory
2541 * address to store contents of the BM_WUC_ENABLE_REG register.
2543 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2548 /* All page select, port ctrl and wakeup registers use phy address 1 */
2551 /* Select Port Control Registers page */
2552 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2554 e_dbg("Could not set Port Control page\n");
2558 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2560 e_dbg("Could not read PHY register %d.%d\n",
2561 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2565 /* Enable both PHY wakeup mode and Wakeup register page writes.
2566 * Prevent a power state change by disabling ME and Host PHY wakeup.
2569 temp |= BM_WUC_ENABLE_BIT;
2570 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2572 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2574 e_dbg("Could not write PHY register %d.%d\n",
2575 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2579 /* Select Host Wakeup Registers page - caller now able to write
2580 * registers on the Wakeup registers page
2582 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2586 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2587 * @hw: pointer to the HW structure
2588 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2590 * Restore BM_WUC_ENABLE_REG to its original value.
2592 * Assumes semaphore already acquired and *phy_reg is the contents of the
2593 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2596 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2600 /* Select Port Control Registers page */
2601 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2603 e_dbg("Could not set Port Control page\n");
2607 /* Restore 769.17 to its original value */
2608 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2610 e_dbg("Could not restore PHY register %d.%d\n",
2611 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2617 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2618 * @hw: pointer to the HW structure
2619 * @offset: register offset to be read or written
2620 * @data: pointer to the data to read or write
2621 * @read: determines if operation is read or write
2622 * @page_set: BM_WUC_PAGE already set and access enabled
2624 * Read the PHY register at offset and store the retrieved information in
2625 * data, or write data to PHY register at offset. Note the procedure to
2626 * access the PHY wakeup registers is different than reading the other PHY
2627 * registers. It works as such:
2628 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2629 * 2) Set page to 800 for host (801 if we were manageability)
2630 * 3) Write the address using the address opcode (0x11)
2631 * 4) Read or write the data using the data opcode (0x12)
2632 * 5) Restore 769.17.2 to its original value
2634 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2635 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2637 * Assumes semaphore is already acquired. When page_set==true, assumes
2638 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2639 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2641 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2642 u16 *data, bool read, bool page_set)
2645 u16 reg = BM_PHY_REG_NUM(offset);
2646 u16 page = BM_PHY_REG_PAGE(offset);
2649 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2650 if ((hw->mac.type == e1000_pchlan) &&
2651 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2652 e_dbg("Attempting to access page %d while gig enabled.\n",
2656 /* Enable access to PHY wakeup registers */
2657 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2659 e_dbg("Could not enable PHY wakeup reg access\n");
2664 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2666 /* Write the Wakeup register page offset value using opcode 0x11 */
2667 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2669 e_dbg("Could not write address opcode to page %d\n", page);
2674 /* Read the Wakeup register page value using opcode 0x12 */
2675 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2678 /* Write the Wakeup register page value using opcode 0x12 */
2679 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2684 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2689 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2695 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2696 * @hw: pointer to the HW structure
2698 * In the case of a PHY power down to save power, or to turn off link during a
2699 * driver unload, or wake on lan is not enabled, restore the link to previous
2702 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2706 /* The PHY will retain its settings across a power down/up cycle */
2707 e1e_rphy(hw, MII_BMCR, &mii_reg);
2708 mii_reg &= ~BMCR_PDOWN;
2709 e1e_wphy(hw, MII_BMCR, mii_reg);
2713 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2714 * @hw: pointer to the HW structure
2716 * In the case of a PHY power down to save power, or to turn off link during a
2717 * driver unload, or wake on lan is not enabled, restore the link to previous
2720 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2724 /* The PHY will retain its settings across a power down/up cycle */
2725 e1e_rphy(hw, MII_BMCR, &mii_reg);
2726 mii_reg |= BMCR_PDOWN;
2727 e1e_wphy(hw, MII_BMCR, mii_reg);
2728 usleep_range(1000, 2000);
2732 * __e1000_read_phy_reg_hv - Read HV PHY register
2733 * @hw: pointer to the HW structure
2734 * @offset: register offset to be read
2735 * @data: pointer to the read data
2736 * @locked: semaphore has already been acquired or not
2738 * Acquires semaphore, if necessary, then reads the PHY register at offset
2739 * and stores the retrieved information in data. Release any acquired
2740 * semaphore before exiting.
2742 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2743 bool locked, bool page_set)
2746 u16 page = BM_PHY_REG_PAGE(offset);
2747 u16 reg = BM_PHY_REG_NUM(offset);
2748 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2751 ret_val = hw->phy.ops.acquire(hw);
2756 /* Page 800 works differently than the rest so it has its own func */
2757 if (page == BM_WUC_PAGE) {
2758 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2763 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2764 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2770 if (page == HV_INTC_FC_PAGE_START)
2773 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2774 /* Page is shifted left, PHY expects (page x 32) */
2775 ret_val = e1000_set_page_igp(hw,
2776 (page << IGP_PAGE_SHIFT));
2778 hw->phy.addr = phy_addr;
2785 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2786 page << IGP_PAGE_SHIFT, reg);
2788 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
2791 hw->phy.ops.release(hw);
2797 * e1000_read_phy_reg_hv - Read HV PHY register
2798 * @hw: pointer to the HW structure
2799 * @offset: register offset to be read
2800 * @data: pointer to the read data
2802 * Acquires semaphore then reads the PHY register at offset and stores
2803 * the retrieved information in data. Release the acquired semaphore
2806 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2808 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2812 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2813 * @hw: pointer to the HW structure
2814 * @offset: register offset to be read
2815 * @data: pointer to the read data
2817 * Reads the PHY register at offset and stores the retrieved information
2818 * in data. Assumes semaphore already acquired.
2820 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2822 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2826 * e1000_read_phy_reg_page_hv - Read HV PHY register
2827 * @hw: pointer to the HW structure
2828 * @offset: register offset to write to
2829 * @data: data to write at register offset
2831 * Reads the PHY register at offset and stores the retrieved information
2832 * in data. Assumes semaphore already acquired and page already set.
2834 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2836 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2840 * __e1000_write_phy_reg_hv - Write HV PHY register
2841 * @hw: pointer to the HW structure
2842 * @offset: register offset to write to
2843 * @data: data to write at register offset
2844 * @locked: semaphore has already been acquired or not
2846 * Acquires semaphore, if necessary, then writes the data to PHY register
2847 * at the offset. Release any acquired semaphores before exiting.
2849 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2850 bool locked, bool page_set)
2853 u16 page = BM_PHY_REG_PAGE(offset);
2854 u16 reg = BM_PHY_REG_NUM(offset);
2855 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2858 ret_val = hw->phy.ops.acquire(hw);
2863 /* Page 800 works differently than the rest so it has its own func */
2864 if (page == BM_WUC_PAGE) {
2865 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2870 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2871 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2877 if (page == HV_INTC_FC_PAGE_START)
2880 /* Workaround MDIO accesses being disabled after entering IEEE
2881 * Power Down (when bit 11 of the PHY Control register is set)
2883 if ((hw->phy.type == e1000_phy_82578) &&
2884 (hw->phy.revision >= 1) &&
2885 (hw->phy.addr == 2) &&
2886 !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) {
2888 ret_val = e1000_access_phy_debug_regs_hv(hw,
2895 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2896 /* Page is shifted left, PHY expects (page x 32) */
2897 ret_val = e1000_set_page_igp(hw,
2898 (page << IGP_PAGE_SHIFT));
2900 hw->phy.addr = phy_addr;
2907 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2908 page << IGP_PAGE_SHIFT, reg);
2910 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2915 hw->phy.ops.release(hw);
2921 * e1000_write_phy_reg_hv - Write HV PHY register
2922 * @hw: pointer to the HW structure
2923 * @offset: register offset to write to
2924 * @data: data to write at register offset
2926 * Acquires semaphore then writes the data to PHY register at the offset.
2927 * Release the acquired semaphores before exiting.
2929 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2931 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
2935 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2936 * @hw: pointer to the HW structure
2937 * @offset: register offset to write to
2938 * @data: data to write at register offset
2940 * Writes the data to PHY register at the offset. Assumes semaphore
2943 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
2945 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
2949 * e1000_write_phy_reg_page_hv - Write HV PHY register
2950 * @hw: pointer to the HW structure
2951 * @offset: register offset to write to
2952 * @data: data to write at register offset
2954 * Writes the data to PHY register at the offset. Assumes semaphore
2955 * already acquired and page already set.
2957 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
2959 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
2963 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
2964 * @page: page to be accessed
2966 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2970 if (page >= HV_INTC_FC_PAGE_START)
2977 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2978 * @hw: pointer to the HW structure
2979 * @offset: register offset to be read or written
2980 * @data: pointer to the data to be read or written
2981 * @read: determines if operation is read or write
2983 * Reads the PHY register at offset and stores the retreived information
2984 * in data. Assumes semaphore already acquired. Note that the procedure
2985 * to access these regs uses the address port and data port to read/write.
2986 * These accesses done with PHY address 2 and without using pages.
2988 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
2989 u16 *data, bool read)
2995 /* This takes care of the difference with desktop vs mobile phy */
2996 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
2997 I82578_ADDR_REG : I82577_ADDR_REG);
2998 data_reg = addr_reg + 1;
3000 /* All operations in this function are phy address 2 */
3003 /* masking with 0x3F to remove the page from offset */
3004 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3006 e_dbg("Could not write the Address Offset port register\n");
3010 /* Read or write the data value next */
3012 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3014 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3017 e_dbg("Could not access the Data port register\n");
3023 * e1000_link_stall_workaround_hv - Si workaround
3024 * @hw: pointer to the HW structure
3026 * This function works around a Si bug where the link partner can get
3027 * a link up indication before the PHY does. If small packets are sent
3028 * by the link partner they can be placed in the packet buffer without
3029 * being properly accounted for by the PHY and will stall preventing
3030 * further packets from being received. The workaround is to clear the
3031 * packet buffer after the PHY detects link up.
3033 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3038 if (hw->phy.type != e1000_phy_82578)
3041 /* Do not apply workaround if in PHY loopback bit 14 set */
3042 e1e_rphy(hw, MII_BMCR, &data);
3043 if (data & BMCR_LOOPBACK)
3046 /* check if link is up and at 1Gbps */
3047 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3051 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3052 BM_CS_STATUS_SPEED_MASK);
3054 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3055 BM_CS_STATUS_SPEED_1000))
3060 /* flush the packets in the fifo buffer */
3061 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
3062 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3063 HV_MUX_DATA_CTRL_FORCE_SPEED));
3067 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3071 * e1000_check_polarity_82577 - Checks the polarity.
3072 * @hw: pointer to the HW structure
3074 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3076 * Polarity is determined based on the PHY specific status register.
3078 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3080 struct e1000_phy_info *phy = &hw->phy;
3084 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3087 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3088 ? e1000_rev_polarity_reversed
3089 : e1000_rev_polarity_normal);
3095 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3096 * @hw: pointer to the HW structure
3098 * Calls the PHY setup function to force speed and duplex.
3100 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3102 struct e1000_phy_info *phy = &hw->phy;
3107 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
3111 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3113 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
3119 if (phy->autoneg_wait_to_complete) {
3120 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3122 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3128 e_dbg("Link taking longer than expected.\n");
3131 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3139 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3140 * @hw: pointer to the HW structure
3142 * Read PHY status to determine if link is up. If link is up, then
3143 * set/determine 10base-T extended distance and polarity correction. Read
3144 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3145 * determine on the cable length, local and remote receiver.
3147 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3149 struct e1000_phy_info *phy = &hw->phy;
3154 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3159 e_dbg("Phy info is only valid if link is up\n");
3160 return -E1000_ERR_CONFIG;
3163 phy->polarity_correction = true;
3165 ret_val = e1000_check_polarity_82577(hw);
3169 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3173 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3175 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3176 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3177 ret_val = hw->phy.ops.get_cable_length(hw);
3181 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
3185 phy->local_rx = (data & LPA_1000LOCALRXOK)
3186 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3188 phy->remote_rx = (data & LPA_1000REMRXOK)
3189 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3191 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3192 phy->local_rx = e1000_1000t_rx_status_undefined;
3193 phy->remote_rx = e1000_1000t_rx_status_undefined;
3200 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3201 * @hw: pointer to the HW structure
3203 * Reads the diagnostic status register and verifies result is valid before
3204 * placing it in the phy_cable_length field.
3206 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3208 struct e1000_phy_info *phy = &hw->phy;
3210 u16 phy_data, length;
3212 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3216 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3217 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
3219 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3220 return -E1000_ERR_PHY;
3222 phy->cable_length = length;