1 /* Intel Ethernet Switch Host Interface Driver
2 * Copyright(c) 2013 - 2014 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
16 * Contact Information:
17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 * fm10k_reset_hw_pf - PF hardware reset
26 * @hw: pointer to hardware structure
28 * This function should return the hardware to a state similar to the
29 * one it is in after being powered on.
31 static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw)
37 /* Disable interrupts */
38 fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL));
40 /* Lock ITR2 reg 0 into itself and disable interrupt moderation */
41 fm10k_write_reg(hw, FM10K_ITR2(0), 0);
42 fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
44 /* We assume here Tx and Rx queue 0 are owned by the PF */
46 /* Shut off VF access to their queues forcing them to queue 0 */
47 for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) {
48 fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
49 fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
52 /* shut down all rings */
53 err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES);
57 /* Verify that DMA is no longer active */
58 reg = fm10k_read_reg(hw, FM10K_DMA_CTRL);
59 if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE))
60 return FM10K_ERR_DMA_PENDING;
62 /* Inititate data path reset */
63 reg |= FM10K_DMA_CTRL_DATAPATH_RESET;
64 fm10k_write_reg(hw, FM10K_DMA_CTRL, reg);
66 /* Flush write and allow 100us for reset to complete */
67 fm10k_write_flush(hw);
68 udelay(FM10K_RESET_TIMEOUT);
70 /* Verify we made it out of reset */
71 reg = fm10k_read_reg(hw, FM10K_IP);
72 if (!(reg & FM10K_IP_NOTINRESET))
73 err = FM10K_ERR_RESET_FAILED;
79 * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support
80 * @hw: pointer to hardware structure
82 * Looks at the ARI hierarchy bit to determine whether ARI is supported or not.
84 static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw)
86 u16 sriov_ctrl = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_SRIOV_CTRL);
88 return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI);
92 * fm10k_init_hw_pf - PF hardware initialization
93 * @hw: pointer to hardware structure
96 static s32 fm10k_init_hw_pf(struct fm10k_hw *hw)
101 /* Establish default VSI as valid */
102 fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0);
103 fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default),
104 FM10K_DGLORTMAP_ANY);
106 /* Invalidate all other GLORT entries */
107 for (i = 1; i < FM10K_DGLORT_COUNT; i++)
108 fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE);
110 /* reset ITR2(0) to point to itself */
111 fm10k_write_reg(hw, FM10K_ITR2(0), 0);
113 /* reset VF ITR2(0) to point to 0 avoid PF registers */
114 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0);
116 /* loop through all PF ITR2 registers pointing them to the previous */
117 for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++)
118 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
120 /* Enable interrupt moderator if not already enabled */
121 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
123 /* compute the default txqctl configuration */
124 txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW |
125 (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT);
127 for (i = 0; i < FM10K_MAX_QUEUES; i++) {
128 /* configure rings for 256 Queue / 32 Descriptor cache mode */
129 fm10k_write_reg(hw, FM10K_TQDLOC(i),
130 (i * FM10K_TQDLOC_BASE_32_DESC) |
131 FM10K_TQDLOC_SIZE_32_DESC);
132 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
134 /* configure rings to provide TPH processing hints */
135 fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i),
136 FM10K_TPH_TXCTRL_DESC_TPHEN |
137 FM10K_TPH_TXCTRL_DESC_RROEN |
138 FM10K_TPH_TXCTRL_DESC_WROEN |
139 FM10K_TPH_TXCTRL_DATA_RROEN);
140 fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i),
141 FM10K_TPH_RXCTRL_DESC_TPHEN |
142 FM10K_TPH_RXCTRL_DESC_RROEN |
143 FM10K_TPH_RXCTRL_DATA_WROEN |
144 FM10K_TPH_RXCTRL_HDR_WROEN);
147 /* set max hold interval to align with 1.024 usec in all modes */
148 switch (hw->bus.speed) {
149 case fm10k_bus_speed_2500:
150 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1;
152 case fm10k_bus_speed_5000:
153 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2;
155 case fm10k_bus_speed_8000:
156 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3;
163 /* Configure TSO flags */
164 fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW);
165 fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI);
168 * Set Rx Descriptor size to 32
169 * Set Minimum MSS to 64
170 * Set Maximum number of Rx queues to 256 / 32 Descriptor
172 dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE |
173 FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 |
174 FM10K_DMA_CTRL_32_DESC;
176 fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl);
178 /* record maximum queue count, we limit ourselves to 128 */
179 hw->mac.max_queues = FM10K_MAX_QUEUES_PF;
181 /* We support either 64 VFs or 7 VFs depending on if we have ARI */
182 hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7;
188 * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table
189 * @hw: pointer to hardware structure
190 * @vid: VLAN ID to add to table
191 * @vsi: Index indicating VF ID or PF ID in table
192 * @set: Indicates if this is a set or clear operation
194 * This function adds or removes the corresponding VLAN ID from the VLAN
195 * filter table for the corresponding function. In addition to the
196 * standard set/clear that supports one bit a multi-bit write is
197 * supported to set 64 bits at a time.
199 static s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set)
201 u32 vlan_table, reg, mask, bit, len;
203 /* verify the VSI index is valid */
204 if (vsi > FM10K_VLAN_TABLE_VSI_MAX)
205 return FM10K_ERR_PARAM;
207 /* VLAN multi-bit write:
208 * The multi-bit write has several parts to it.
210 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
211 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
212 * | RSVD0 | Length |C|RSVD0| VLAN ID |
213 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
215 * VLAN ID: Vlan Starting value
216 * RSVD0: Reserved section, must be 0
217 * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message)
218 * Length: Number of times to repeat the bit being set
221 vid = (vid << 17) >> 17;
223 /* verify the reserved 0 fields are 0 */
224 if (len >= FM10K_VLAN_TABLE_VID_MAX || vid >= FM10K_VLAN_TABLE_VID_MAX)
225 return FM10K_ERR_PARAM;
227 /* Loop through the table updating all required VLANs */
228 for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32;
229 len < FM10K_VLAN_TABLE_VID_MAX;
230 len -= 32 - bit, reg++, bit = 0) {
231 /* record the initial state of the register */
232 vlan_table = fm10k_read_reg(hw, reg);
234 /* truncate mask if we are at the start or end of the run */
235 mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit;
237 /* make necessary modifications to the register */
238 mask &= set ? ~vlan_table : vlan_table;
240 fm10k_write_reg(hw, reg, vlan_table ^ mask);
247 * fm10k_read_mac_addr_pf - Read device MAC address
248 * @hw: pointer to the HW structure
250 * Reads the device MAC address from the SM_AREA and stores the value.
252 static s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw)
254 u8 perm_addr[ETH_ALEN];
258 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1));
260 /* last byte should be all 1's */
261 if ((~serial_num) << 24)
262 return FM10K_ERR_INVALID_MAC_ADDR;
264 perm_addr[0] = (u8)(serial_num >> 24);
265 perm_addr[1] = (u8)(serial_num >> 16);
266 perm_addr[2] = (u8)(serial_num >> 8);
268 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0));
270 /* first byte should be all 1's */
271 if ((~serial_num) >> 24)
272 return FM10K_ERR_INVALID_MAC_ADDR;
274 perm_addr[3] = (u8)(serial_num >> 16);
275 perm_addr[4] = (u8)(serial_num >> 8);
276 perm_addr[5] = (u8)(serial_num);
278 for (i = 0; i < ETH_ALEN; i++) {
279 hw->mac.perm_addr[i] = perm_addr[i];
280 hw->mac.addr[i] = perm_addr[i];
287 * fm10k_glort_valid_pf - Validate that the provided glort is valid
288 * @hw: pointer to the HW structure
289 * @glort: base glort to be validated
291 * This function will return an error if the provided glort is invalid
293 bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort)
295 glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT;
297 return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE);
301 * fm10k_update_xc_addr_pf - Update device addresses
302 * @hw: pointer to the HW structure
303 * @glort: base resource tag for this request
304 * @mac: MAC address to add/remove from table
305 * @vid: VLAN ID to add/remove from table
306 * @add: Indicates if this is an add or remove operation
307 * @flags: flags field to indicate add and secure
309 * This function generates a message to the Switch API requesting
310 * that the given logical port add/remove the given L2 MAC/VLAN address.
312 static s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort,
313 const u8 *mac, u16 vid, bool add, u8 flags)
315 struct fm10k_mbx_info *mbx = &hw->mbx;
316 struct fm10k_mac_update mac_update;
319 /* clear set bit from VLAN ID */
320 vid &= ~FM10K_VLAN_CLEAR;
322 /* if glort or vlan are not valid return error */
323 if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX)
324 return FM10K_ERR_PARAM;
327 mac_update.mac_lower = cpu_to_le32(((u32)mac[2] << 24) |
328 ((u32)mac[3] << 16) |
331 mac_update.mac_upper = cpu_to_le16(((u32)mac[0] << 8) |
333 mac_update.vlan = cpu_to_le16(vid);
334 mac_update.glort = cpu_to_le16(glort);
335 mac_update.action = add ? 0 : 1;
336 mac_update.flags = flags;
338 /* populate mac_update fields */
339 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE);
340 fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE,
341 &mac_update, sizeof(mac_update));
343 /* load onto outgoing mailbox */
344 return mbx->ops.enqueue_tx(hw, mbx, msg);
348 * fm10k_update_uc_addr_pf - Update device unicast addresses
349 * @hw: pointer to the HW structure
350 * @glort: base resource tag for this request
351 * @mac: MAC address to add/remove from table
352 * @vid: VLAN ID to add/remove from table
353 * @add: Indicates if this is an add or remove operation
354 * @flags: flags field to indicate add and secure
356 * This function is used to add or remove unicast addresses for
359 static s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort,
360 const u8 *mac, u16 vid, bool add, u8 flags)
362 /* verify MAC address is valid */
363 if (!is_valid_ether_addr(mac))
364 return FM10K_ERR_PARAM;
366 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags);
370 * fm10k_update_mc_addr_pf - Update device multicast addresses
371 * @hw: pointer to the HW structure
372 * @glort: base resource tag for this request
373 * @mac: MAC address to add/remove from table
374 * @vid: VLAN ID to add/remove from table
375 * @add: Indicates if this is an add or remove operation
377 * This function is used to add or remove multicast MAC addresses for
380 static s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort,
381 const u8 *mac, u16 vid, bool add)
383 /* verify multicast address is valid */
384 if (!is_multicast_ether_addr(mac))
385 return FM10K_ERR_PARAM;
387 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0);
391 * fm10k_update_xcast_mode_pf - Request update of multicast mode
392 * @hw: pointer to hardware structure
393 * @glort: base resource tag for this request
394 * @mode: integer value indicating mode being requested
396 * This function will attempt to request a higher mode for the port
397 * so that it can enable either multicast, multicast promiscuous, or
398 * promiscuous mode of operation.
400 static s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode)
402 struct fm10k_mbx_info *mbx = &hw->mbx;
403 u32 msg[3], xcast_mode;
405 if (mode > FM10K_XCAST_MODE_NONE)
406 return FM10K_ERR_PARAM;
407 /* if glort is not valid return error */
408 if (!fm10k_glort_valid_pf(hw, glort))
409 return FM10K_ERR_PARAM;
411 /* write xcast mode as a single u32 value,
412 * lower 16 bits: glort
413 * upper 16 bits: mode
415 xcast_mode = ((u32)mode << 16) | glort;
417 /* generate message requesting to change xcast mode */
418 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES);
419 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode);
421 /* load onto outgoing mailbox */
422 return mbx->ops.enqueue_tx(hw, mbx, msg);
426 * fm10k_update_int_moderator_pf - Update interrupt moderator linked list
427 * @hw: pointer to hardware structure
429 * This function walks through the MSI-X vector table to determine the
430 * number of active interrupts and based on that information updates the
431 * interrupt moderator linked list.
433 static void fm10k_update_int_moderator_pf(struct fm10k_hw *hw)
437 /* Disable interrupt moderator */
438 fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
440 /* loop through PF from last to first looking enabled vectors */
441 for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) {
442 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
446 /* always reset VFITR2[0] to point to last enabled PF vector */
447 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i);
449 /* reset ITR2[0] to point to last enabled PF vector */
450 if (!hw->iov.num_vfs)
451 fm10k_write_reg(hw, FM10K_ITR2(0), i);
453 /* Enable interrupt moderator */
454 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
458 * fm10k_update_lport_state_pf - Notify the switch of a change in port state
459 * @hw: pointer to the HW structure
460 * @glort: base resource tag for this request
461 * @count: number of logical ports being updated
462 * @enable: boolean value indicating enable or disable
464 * This function is used to add/remove a logical port from the switch.
466 static s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort,
467 u16 count, bool enable)
469 struct fm10k_mbx_info *mbx = &hw->mbx;
470 u32 msg[3], lport_msg;
472 /* do nothing if we are being asked to create or destroy 0 ports */
476 /* if glort is not valid return error */
477 if (!fm10k_glort_valid_pf(hw, glort))
478 return FM10K_ERR_PARAM;
480 /* construct the lport message from the 2 pieces of data we have */
481 lport_msg = ((u32)count << 16) | glort;
483 /* generate lport create/delete message */
484 fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE :
485 FM10K_PF_MSG_ID_LPORT_DELETE);
486 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg);
488 /* load onto outgoing mailbox */
489 return mbx->ops.enqueue_tx(hw, mbx, msg);
493 * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues
494 * @hw: pointer to hardware structure
495 * @dglort: pointer to dglort configuration structure
497 * Reads the configuration structure contained in dglort_cfg and uses
498 * that information to then populate a DGLORTMAP/DEC entry and the queues
499 * to which it has been assigned.
501 static s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw,
502 struct fm10k_dglort_cfg *dglort)
504 u16 glort, queue_count, vsi_count, pc_count;
505 u16 vsi, queue, pc, q_idx;
506 u32 txqctl, dglortdec, dglortmap;
508 /* verify the dglort pointer */
510 return FM10K_ERR_PARAM;
512 /* verify the dglort values */
513 if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) ||
514 (dglort->vsi_l > 6) || (dglort->vsi_b > 64) ||
515 (dglort->queue_l > 8) || (dglort->queue_b >= 256))
516 return FM10K_ERR_PARAM;
518 /* determine count of VSIs and queues */
519 queue_count = 1 << (dglort->rss_l + dglort->pc_l);
520 vsi_count = 1 << (dglort->vsi_l + dglort->queue_l);
521 glort = dglort->glort;
522 q_idx = dglort->queue_b;
524 /* configure SGLORT for queues */
525 for (vsi = 0; vsi < vsi_count; vsi++, glort++) {
526 for (queue = 0; queue < queue_count; queue++, q_idx++) {
527 if (q_idx >= FM10K_MAX_QUEUES)
530 fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort);
531 fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort);
535 /* determine count of PCs and queues */
536 queue_count = 1 << (dglort->queue_l + dglort->rss_l + dglort->vsi_l);
537 pc_count = 1 << dglort->pc_l;
539 /* configure PC for Tx queues */
540 for (pc = 0; pc < pc_count; pc++) {
541 q_idx = pc + dglort->queue_b;
542 for (queue = 0; queue < queue_count; queue++) {
543 if (q_idx >= FM10K_MAX_QUEUES)
546 txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx));
547 txqctl &= ~FM10K_TXQCTL_PC_MASK;
548 txqctl |= pc << FM10K_TXQCTL_PC_SHIFT;
549 fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl);
555 /* configure DGLORTDEC */
556 dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) |
557 ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) |
558 ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) |
559 ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) |
560 ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) |
561 ((u32)(dglort->queue_l));
562 if (dglort->inner_rss)
563 dglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE;
565 /* configure DGLORTMAP */
566 dglortmap = (dglort->idx == fm10k_dglort_default) ?
567 FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO;
568 dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l;
569 dglortmap |= dglort->glort;
571 /* write values to hardware */
572 fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec);
573 fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap);
578 u16 fm10k_queues_per_pool(struct fm10k_hw *hw)
580 u16 num_pools = hw->iov.num_pools;
582 return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ?
583 8 : FM10K_MAX_QUEUES_POOL;
586 u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx)
588 u16 num_vfs = hw->iov.num_vfs;
589 u16 vf_q_idx = FM10K_MAX_QUEUES;
591 vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx);
596 static u16 fm10k_vectors_per_pool(struct fm10k_hw *hw)
598 u16 num_pools = hw->iov.num_pools;
600 return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 :
601 FM10K_MAX_VECTORS_POOL;
604 static u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx)
606 u16 vf_v_idx = FM10K_MAX_VECTORS_PF;
608 vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx;
614 * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization
615 * @hw: pointer to the HW structure
616 * @num_vfs: number of VFs to be allocated
617 * @num_pools: number of virtualization pools to be allocated
619 * Allocates queues and traffic classes to virtualization entities to prepare
620 * the PF for SR-IOV and VMDq
622 static s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs,
625 u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx;
626 u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT;
629 /* hardware only supports up to 64 pools */
631 return FM10K_ERR_PARAM;
633 /* the number of VFs cannot exceed the number of pools */
634 if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs))
635 return FM10K_ERR_PARAM;
637 /* record number of virtualization entities */
638 hw->iov.num_vfs = num_vfs;
639 hw->iov.num_pools = num_pools;
641 /* determine qmap offsets and counts */
642 qmap_stride = (num_vfs > 8) ? 32 : 256;
643 qpp = fm10k_queues_per_pool(hw);
644 vpp = fm10k_vectors_per_pool(hw);
646 /* calculate starting index for queues */
647 vf_q_idx = fm10k_vf_queue_index(hw, 0);
650 /* establish TCs with -1 credits and no quanta to prevent transmit */
651 for (i = 0; i < num_vfs; i++) {
652 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0);
653 fm10k_write_reg(hw, FM10K_TC_RATE(i), 0);
654 fm10k_write_reg(hw, FM10K_TC_CREDIT(i),
655 FM10K_TC_CREDIT_CREDIT_MASK);
658 /* zero out all mbmem registers */
659 for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;)
660 fm10k_write_reg(hw, FM10K_MBMEM(i), 0);
662 /* clear event notification of VF FLR */
663 fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0);
664 fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0);
666 /* loop through unallocated rings assigning them back to PF */
667 for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) {
668 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
669 fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF |
670 FM10K_TXQCTL_UNLIMITED_BW | vid);
671 fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF);
674 /* PF should have already updated VFITR2[0] */
676 /* update all ITR registers to flow to VFITR2[0] */
677 for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) {
678 if (!(i & (vpp - 1)))
679 fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp);
681 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
684 /* update PF ITR2[0] to reference the last vector */
685 fm10k_write_reg(hw, FM10K_ITR2(0),
686 fm10k_vf_vector_index(hw, num_vfs - 1));
688 /* loop through rings populating rings and TCs */
689 for (i = 0; i < num_vfs; i++) {
690 /* record index for VF queue 0 for use in end of loop */
691 vf_q_idx0 = vf_q_idx;
693 for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) {
694 /* assign VF and locked TC to queues */
695 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
696 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx),
697 (i << FM10K_TXQCTL_TC_SHIFT) | i |
698 FM10K_TXQCTL_VF | vid);
699 fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx),
700 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
701 FM10K_RXDCTL_DROP_ON_EMPTY);
702 fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx),
704 (i << FM10K_RXQCTL_VF_SHIFT));
706 /* map queue pair to VF */
707 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
708 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx);
711 /* repeat the first ring for all of the remaining VF rings */
712 for (; j < qmap_stride; j++, qmap_idx++) {
713 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0);
714 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0);
718 /* loop through remaining indexes assigning all to queue 0 */
719 while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) {
720 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
721 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0);
729 * fm10k_iov_configure_tc_pf - Configure the shaping group for VF
730 * @hw: pointer to the HW structure
731 * @vf_idx: index of VF receiving GLORT
732 * @rate: Rate indicated in Mb/s
734 * Configured the TC for a given VF to allow only up to a given number
735 * of Mb/s of outgoing Tx throughput.
737 static s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate)
739 /* configure defaults */
740 u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3;
741 u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK;
743 /* verify vf is in range */
744 if (vf_idx >= hw->iov.num_vfs)
745 return FM10K_ERR_PARAM;
747 /* set interval to align with 4.096 usec in all modes */
748 switch (hw->bus.speed) {
749 case fm10k_bus_speed_2500:
750 interval = FM10K_TC_RATE_INTERVAL_4US_GEN1;
752 case fm10k_bus_speed_5000:
753 interval = FM10K_TC_RATE_INTERVAL_4US_GEN2;
760 if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN)
761 return FM10K_ERR_PARAM;
763 /* The quanta is measured in Bytes per 4.096 or 8.192 usec
764 * The rate is provided in Mbits per second
765 * To tralslate from rate to quanta we need to multiply the
766 * rate by 8.192 usec and divide by 8 bits/byte. To avoid
767 * dealing with floating point we can round the values up
768 * to the nearest whole number ratio which gives us 128 / 125.
770 tc_rate = (rate * 128) / 125;
772 /* try to keep the rate limiting accurate by increasing
773 * the number of credits and interval for rates less than 4Gb/s
781 /* update rate limiter with new values */
782 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval);
783 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
784 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
790 * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list
791 * @hw: pointer to the HW structure
792 * @vf_idx: index of VF receiving GLORT
794 * Update the interrupt moderator linked list to include any MSI-X
795 * interrupts which the VF has enabled in the MSI-X vector table.
797 static s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx)
799 u16 vf_v_idx, vf_v_limit, i;
801 /* verify vf is in range */
802 if (vf_idx >= hw->iov.num_vfs)
803 return FM10K_ERR_PARAM;
805 /* determine vector offset and count */
806 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
807 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
809 /* search for first vector that is not masked */
810 for (i = vf_v_limit - 1; i > vf_v_idx; i--) {
811 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
815 /* reset linked list so it now includes our active vectors */
816 if (vf_idx == (hw->iov.num_vfs - 1))
817 fm10k_write_reg(hw, FM10K_ITR2(0), i);
819 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i);
825 * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF
826 * @hw: pointer to the HW structure
827 * @vf_info: pointer to VF information structure
829 * Assign a MAC address and default VLAN to a VF and notify it of the update
831 static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw,
832 struct fm10k_vf_info *vf_info)
834 u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i;
835 u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0;
839 /* verify vf is in range */
840 if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs)
841 return FM10K_ERR_PARAM;
843 /* determine qmap offsets and counts */
844 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
845 queues_per_pool = fm10k_queues_per_pool(hw);
847 /* calculate starting index for queues */
848 vf_idx = vf_info->vf_idx;
849 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
850 qmap_idx = qmap_stride * vf_idx;
852 /* MAP Tx queue back to 0 temporarily, and disable it */
853 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
854 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
856 /* determine correct default VLAN ID */
858 vf_vid = vf_info->pf_vid | FM10K_VLAN_CLEAR;
860 vf_vid = vf_info->sw_vid;
862 /* generate MAC_ADDR request */
863 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
864 fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC,
865 vf_info->mac, vf_vid);
867 /* load onto outgoing mailbox, ignore any errors on enqueue */
868 if (vf_info->mbx.ops.enqueue_tx)
869 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
871 /* verify ring has disabled before modifying base address registers */
872 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
873 for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) {
874 /* limit ourselves to a 1ms timeout */
876 err = FM10K_ERR_DMA_PENDING;
880 usleep_range(100, 200);
881 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
884 /* Update base address registers to contain MAC address */
885 if (is_valid_ether_addr(vf_info->mac)) {
886 tdbal = (((u32)vf_info->mac[3]) << 24) |
887 (((u32)vf_info->mac[4]) << 16) |
888 (((u32)vf_info->mac[5]) << 8);
890 tdbah = (((u32)0xFF) << 24) |
891 (((u32)vf_info->mac[0]) << 16) |
892 (((u32)vf_info->mac[1]) << 8) |
893 ((u32)vf_info->mac[2]);
896 /* Record the base address into queue 0 */
897 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal);
898 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah);
901 /* configure Queue control register */
902 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) &
903 FM10K_TXQCTL_VID_MASK;
904 txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
905 FM10K_TXQCTL_VF | vf_idx;
908 for (i = 0; i < queues_per_pool; i++)
909 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl);
911 /* restore the queue back to VF ownership */
912 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
917 * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF
918 * @hw: pointer to the HW structure
919 * @vf_info: pointer to VF information structure
921 * Reassign the interrupts and queues to a VF following an FLR
923 static s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw,
924 struct fm10k_vf_info *vf_info)
926 u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx;
927 u32 tdbal = 0, tdbah = 0, txqctl, rxqctl;
928 u16 vf_v_idx, vf_v_limit, vf_vid;
929 u8 vf_idx = vf_info->vf_idx;
932 /* verify vf is in range */
933 if (vf_idx >= hw->iov.num_vfs)
934 return FM10K_ERR_PARAM;
936 /* clear event notification of VF FLR */
937 fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), 1 << (vf_idx % 32));
939 /* force timeout and then disconnect the mailbox */
940 vf_info->mbx.timeout = 0;
941 if (vf_info->mbx.ops.disconnect)
942 vf_info->mbx.ops.disconnect(hw, &vf_info->mbx);
944 /* determine vector offset and count */
945 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
946 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
948 /* determine qmap offsets and counts */
949 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
950 queues_per_pool = fm10k_queues_per_pool(hw);
951 qmap_idx = qmap_stride * vf_idx;
953 /* make all the queues inaccessible to the VF */
954 for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) {
955 fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
956 fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
959 /* calculate starting index for queues */
960 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
962 /* determine correct default VLAN ID */
964 vf_vid = vf_info->pf_vid;
966 vf_vid = vf_info->sw_vid;
968 /* configure Queue control register */
969 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) |
970 (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
971 FM10K_TXQCTL_VF | vf_idx;
972 rxqctl = FM10K_RXQCTL_VF | (vf_idx << FM10K_RXQCTL_VF_SHIFT);
974 /* stop further DMA and reset queue ownership back to VF */
975 for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) {
976 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
977 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
978 fm10k_write_reg(hw, FM10K_RXDCTL(i),
979 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
980 FM10K_RXDCTL_DROP_ON_EMPTY);
981 fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl);
984 /* reset TC with -1 credits and no quanta to prevent transmit */
985 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0);
986 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0);
987 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx),
988 FM10K_TC_CREDIT_CREDIT_MASK);
990 /* update our first entry in the table based on previous VF */
992 hw->mac.ops.update_int_moderator(hw);
994 hw->iov.ops.assign_int_moderator(hw, vf_idx - 1);
996 /* reset linked list so it now includes our active vectors */
997 if (vf_idx == (hw->iov.num_vfs - 1))
998 fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx);
1000 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx);
1002 /* link remaining vectors so that next points to previous */
1003 for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++)
1004 fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1);
1006 /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */
1007 for (i = FM10K_VFMBMEM_LEN; i--;)
1008 fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0);
1009 for (i = FM10K_VLAN_TABLE_SIZE; i--;)
1010 fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0);
1011 for (i = FM10K_RETA_SIZE; i--;)
1012 fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0);
1013 for (i = FM10K_RSSRK_SIZE; i--;)
1014 fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0);
1015 fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0);
1017 /* Update base address registers to contain MAC address */
1018 if (is_valid_ether_addr(vf_info->mac)) {
1019 tdbal = (((u32)vf_info->mac[3]) << 24) |
1020 (((u32)vf_info->mac[4]) << 16) |
1021 (((u32)vf_info->mac[5]) << 8);
1022 tdbah = (((u32)0xFF) << 24) |
1023 (((u32)vf_info->mac[0]) << 16) |
1024 (((u32)vf_info->mac[1]) << 8) |
1025 ((u32)vf_info->mac[2]);
1028 /* map queue pairs back to VF from last to first */
1029 for (i = queues_per_pool; i--;) {
1030 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal);
1031 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah);
1032 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i);
1033 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i);
1036 /* repeat the first ring for all the remaining VF rings */
1037 for (i = queues_per_pool; i < qmap_stride; i++) {
1038 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx);
1039 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx);
1046 * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF
1047 * @hw: pointer to hardware structure
1048 * @vf_info: pointer to VF information structure
1049 * @lport_idx: Logical port offset from the hardware glort
1050 * @flags: Set of capability flags to extend port beyond basic functionality
1052 * This function allows enabling a VF port by assigning it a GLORT and
1053 * setting the flags so that it can enable an Rx mode.
1055 static s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw,
1056 struct fm10k_vf_info *vf_info,
1057 u16 lport_idx, u8 flags)
1059 u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE;
1061 /* if glort is not valid return error */
1062 if (!fm10k_glort_valid_pf(hw, glort))
1063 return FM10K_ERR_PARAM;
1065 vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE;
1066 vf_info->glort = glort;
1072 * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF
1073 * @hw: pointer to hardware structure
1074 * @vf_info: pointer to VF information structure
1076 * This function disables a VF port by stripping it of a GLORT and
1077 * setting the flags so that it cannot enable any Rx mode.
1079 static void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw,
1080 struct fm10k_vf_info *vf_info)
1084 /* need to disable the port if it is already enabled */
1085 if (FM10K_VF_FLAG_ENABLED(vf_info)) {
1086 /* notify switch that this port has been disabled */
1087 fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false);
1089 /* generate port state response to notify VF it is not ready */
1090 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1091 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1094 /* clear flags and glort if it exists */
1095 vf_info->vf_flags = 0;
1100 * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs
1101 * @hw: pointer to hardware structure
1102 * @q: stats for all queues of a VF
1103 * @vf_idx: index of VF
1105 * This function collects queue stats for VFs.
1107 static void fm10k_iov_update_stats_pf(struct fm10k_hw *hw,
1108 struct fm10k_hw_stats_q *q,
1113 /* get stats for all of the queues */
1114 qpp = fm10k_queues_per_pool(hw);
1115 idx = fm10k_vf_queue_index(hw, vf_idx);
1116 fm10k_update_hw_stats_q(hw, q, idx, qpp);
1119 static s32 fm10k_iov_report_timestamp_pf(struct fm10k_hw *hw,
1120 struct fm10k_vf_info *vf_info,
1125 /* generate port state response to notify VF it is not ready */
1126 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_1588);
1127 fm10k_tlv_attr_put_u64(msg, FM10K_1588_MSG_TIMESTAMP, timestamp);
1129 return vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1133 * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF
1134 * @hw: Pointer to hardware structure
1135 * @results: Pointer array to message, results[0] is pointer to message
1136 * @mbx: Pointer to mailbox information structure
1138 * This function is a default handler for MSI-X requests from the VF. The
1139 * assumption is that in this case it is acceptable to just directly
1140 * hand off the message from the VF to the underlying shared code.
1142 s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results,
1143 struct fm10k_mbx_info *mbx)
1145 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1146 u8 vf_idx = vf_info->vf_idx;
1148 return hw->iov.ops.assign_int_moderator(hw, vf_idx);
1152 * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF
1153 * @hw: Pointer to hardware structure
1154 * @results: Pointer array to message, results[0] is pointer to message
1155 * @mbx: Pointer to mailbox information structure
1157 * This function is a default handler for MAC/VLAN requests from the VF.
1158 * The assumption is that in this case it is acceptable to just directly
1159 * hand off the message from the VF to the underlying shared code.
1161 s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results,
1162 struct fm10k_mbx_info *mbx)
1164 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1171 /* we shouldn't be updating rules on a disabled interface */
1172 if (!FM10K_VF_FLAG_ENABLED(vf_info))
1173 err = FM10K_ERR_PARAM;
1175 if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) {
1176 result = results[FM10K_MAC_VLAN_MSG_VLAN];
1178 /* record VLAN id requested */
1179 err = fm10k_tlv_attr_get_u32(result, &vid);
1183 /* if VLAN ID is 0, set the default VLAN ID instead of 0 */
1184 if (!vid || (vid == FM10K_VLAN_CLEAR)) {
1185 if (vf_info->pf_vid)
1186 vid |= vf_info->pf_vid;
1188 vid |= vf_info->sw_vid;
1189 } else if (vid != vf_info->pf_vid) {
1190 return FM10K_ERR_PARAM;
1193 /* update VSI info for VF in regards to VLAN table */
1194 err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi,
1195 !(vid & FM10K_VLAN_CLEAR));
1198 if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) {
1199 result = results[FM10K_MAC_VLAN_MSG_MAC];
1201 /* record unicast MAC address requested */
1202 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1206 /* block attempts to set MAC for a locked device */
1207 if (is_valid_ether_addr(vf_info->mac) &&
1208 memcmp(mac, vf_info->mac, ETH_ALEN))
1209 return FM10K_ERR_PARAM;
1211 /* if VLAN ID is 0, set the default VLAN ID instead of 0 */
1212 if (!vlan || (vlan == FM10K_VLAN_CLEAR)) {
1213 if (vf_info->pf_vid)
1214 vlan |= vf_info->pf_vid;
1216 vlan |= vf_info->sw_vid;
1217 } else if (vf_info->pf_vid) {
1218 return FM10K_ERR_PARAM;
1221 /* notify switch of request for new unicast address */
1222 err = hw->mac.ops.update_uc_addr(hw, vf_info->glort, mac, vlan,
1223 !(vlan & FM10K_VLAN_CLEAR), 0);
1226 if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) {
1227 result = results[FM10K_MAC_VLAN_MSG_MULTICAST];
1229 /* record multicast MAC address requested */
1230 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1234 /* verify that the VF is allowed to request multicast */
1235 if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED))
1236 return FM10K_ERR_PARAM;
1238 /* if VLAN ID is 0, set the default VLAN ID instead of 0 */
1239 if (!vlan || (vlan == FM10K_VLAN_CLEAR)) {
1240 if (vf_info->pf_vid)
1241 vlan |= vf_info->pf_vid;
1243 vlan |= vf_info->sw_vid;
1244 } else if (vf_info->pf_vid) {
1245 return FM10K_ERR_PARAM;
1248 /* notify switch of request for new multicast address */
1249 err = hw->mac.ops.update_mc_addr(hw, vf_info->glort, mac, vlan,
1250 !(vlan & FM10K_VLAN_CLEAR));
1257 * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode
1258 * @vf_info: VF info structure containing capability flags
1259 * @mode: Requested xcast mode
1261 * This function outputs the mode that most closely matches the requested
1262 * mode. If not modes match it will request we disable the port
1264 static u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info,
1267 u8 vf_flags = vf_info->vf_flags;
1269 /* match up mode to capabilities as best as possible */
1271 case FM10K_XCAST_MODE_PROMISC:
1272 if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE)
1273 return FM10K_XCAST_MODE_PROMISC;
1275 case FM10K_XCAST_MODE_ALLMULTI:
1276 if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE)
1277 return FM10K_XCAST_MODE_ALLMULTI;
1279 case FM10K_XCAST_MODE_MULTI:
1280 if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE)
1281 return FM10K_XCAST_MODE_MULTI;
1283 case FM10K_XCAST_MODE_NONE:
1284 if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)
1285 return FM10K_XCAST_MODE_NONE;
1291 /* disable interface as it should not be able to request any */
1292 return FM10K_XCAST_MODE_DISABLE;
1296 * fm10k_iov_msg_lport_state_pf - Message handler for port state requests
1297 * @hw: Pointer to hardware structure
1298 * @results: Pointer array to message, results[0] is pointer to message
1299 * @mbx: Pointer to mailbox information structure
1301 * This function is a default handler for port state requests. The port
1302 * state requests for now are basic and consist of enabling or disabling
1305 s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results,
1306 struct fm10k_mbx_info *mbx)
1308 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1314 /* verify VF is allowed to enable even minimal mode */
1315 if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE))
1316 return FM10K_ERR_PARAM;
1318 if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) {
1319 result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE];
1321 /* XCAST mode update requested */
1322 err = fm10k_tlv_attr_get_u8(result, &mode);
1324 return FM10K_ERR_PARAM;
1326 /* prep for possible demotion depending on capabilities */
1327 mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode);
1329 /* if mode is not currently enabled, enable it */
1330 if (!(FM10K_VF_FLAG_ENABLED(vf_info) & (1 << mode)))
1331 fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode);
1333 /* swap mode back to a bit flag */
1334 mode = FM10K_VF_FLAG_SET_MODE(mode);
1335 } else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) {
1336 /* need to disable the port if it is already enabled */
1337 if (FM10K_VF_FLAG_ENABLED(vf_info))
1338 err = fm10k_update_lport_state_pf(hw, vf_info->glort,
1341 /* we need to clear VF_FLAG_ENABLED flags in order to ensure
1342 * that we actually re-enable the LPORT state below. Note that
1343 * this has no impact if the VF is already disabled, as the
1344 * flags are already cleared.
1347 vf_info->vf_flags = FM10K_VF_FLAG_CAPABLE(vf_info);
1349 /* when enabling the port we should reset the rate limiters */
1350 hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate);
1352 /* set mode for minimal functionality */
1353 mode = FM10K_VF_FLAG_SET_MODE_NONE;
1355 /* generate port state response to notify VF it is ready */
1356 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1357 fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY);
1358 mbx->ops.enqueue_tx(hw, mbx, msg);
1361 /* if enable state toggled note the update */
1362 if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode))
1363 err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1,
1366 /* if state change succeeded, then update our stored state */
1367 mode |= FM10K_VF_FLAG_CAPABLE(vf_info);
1369 vf_info->vf_flags = mode;
1374 const struct fm10k_msg_data fm10k_iov_msg_data_pf[] = {
1375 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
1376 FM10K_VF_MSG_MSIX_HANDLER(fm10k_iov_msg_msix_pf),
1377 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_iov_msg_mac_vlan_pf),
1378 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_iov_msg_lport_state_pf),
1379 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1383 * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF
1384 * @hw: pointer to hardware structure
1385 * @stats: pointer to the stats structure to update
1387 * This function collects and aggregates global and per queue hardware
1390 static void fm10k_update_hw_stats_pf(struct fm10k_hw *hw,
1391 struct fm10k_hw_stats *stats)
1393 u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop;
1396 /* Use Tx queue 0 as a canary to detect a reset */
1397 id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1399 /* Read Global Statistics */
1401 timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT,
1403 ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur);
1404 ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca);
1405 um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um);
1406 xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec);
1407 vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP,
1409 loopback_drop = fm10k_read_hw_stats_32b(hw,
1410 FM10K_STATS_LOOPBACK_DROP,
1411 &stats->loopback_drop);
1412 nodesc_drop = fm10k_read_hw_stats_32b(hw,
1413 FM10K_STATS_NODESC_DROP,
1414 &stats->nodesc_drop);
1416 /* if value has not changed then we have consistent data */
1418 id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1419 } while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK);
1421 /* drop non-ID bits and set VALID ID bit */
1422 id &= FM10K_TXQCTL_ID_MASK;
1423 id |= FM10K_STAT_VALID;
1425 /* Update Global Statistics */
1426 if (stats->stats_idx == id) {
1427 stats->timeout.count += timeout;
1428 stats->ur.count += ur;
1429 stats->ca.count += ca;
1430 stats->um.count += um;
1431 stats->xec.count += xec;
1432 stats->vlan_drop.count += vlan_drop;
1433 stats->loopback_drop.count += loopback_drop;
1434 stats->nodesc_drop.count += nodesc_drop;
1437 /* Update bases and record current PF id */
1438 fm10k_update_hw_base_32b(&stats->timeout, timeout);
1439 fm10k_update_hw_base_32b(&stats->ur, ur);
1440 fm10k_update_hw_base_32b(&stats->ca, ca);
1441 fm10k_update_hw_base_32b(&stats->um, um);
1442 fm10k_update_hw_base_32b(&stats->xec, xec);
1443 fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop);
1444 fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop);
1445 fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop);
1446 stats->stats_idx = id;
1448 /* Update Queue Statistics */
1449 fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues);
1453 * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF
1454 * @hw: pointer to hardware structure
1455 * @stats: pointer to the stats structure to update
1457 * This function resets the base for global and per queue hardware
1460 static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw,
1461 struct fm10k_hw_stats *stats)
1463 /* Unbind Global Statistics */
1464 fm10k_unbind_hw_stats_32b(&stats->timeout);
1465 fm10k_unbind_hw_stats_32b(&stats->ur);
1466 fm10k_unbind_hw_stats_32b(&stats->ca);
1467 fm10k_unbind_hw_stats_32b(&stats->um);
1468 fm10k_unbind_hw_stats_32b(&stats->xec);
1469 fm10k_unbind_hw_stats_32b(&stats->vlan_drop);
1470 fm10k_unbind_hw_stats_32b(&stats->loopback_drop);
1471 fm10k_unbind_hw_stats_32b(&stats->nodesc_drop);
1473 /* Unbind Queue Statistics */
1474 fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues);
1476 /* Reinitialize bases for all stats */
1477 fm10k_update_hw_stats_pf(hw, stats);
1481 * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system
1482 * @hw: pointer to hardware structure
1483 * @dma_mask: 64 bit DMA mask required for platform
1485 * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order
1486 * to limit the access to memory beyond what is physically in the system.
1488 static void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask)
1490 /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */
1491 u32 phyaddr = (u32)(dma_mask >> 32);
1493 fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr);
1497 * fm10k_get_fault_pf - Record a fault in one of the interface units
1498 * @hw: pointer to hardware structure
1499 * @type: pointer to fault type register offset
1500 * @fault: pointer to memory location to record the fault
1502 * Record the fault register contents to the fault data structure and
1503 * clear the entry from the register.
1505 * Returns ERR_PARAM if invalid register is specified or no error is present.
1507 static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type,
1508 struct fm10k_fault *fault)
1512 /* verify the fault register is in range and is aligned */
1514 case FM10K_PCA_FAULT:
1515 case FM10K_THI_FAULT:
1516 case FM10K_FUM_FAULT:
1519 return FM10K_ERR_PARAM;
1522 /* only service faults that are valid */
1523 func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC);
1524 if (!(func & FM10K_FAULT_FUNC_VALID))
1525 return FM10K_ERR_PARAM;
1527 /* read remaining fields */
1528 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI);
1529 fault->address <<= 32;
1530 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO);
1531 fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO);
1533 /* clear valid bit to allow for next error */
1534 fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID);
1536 /* Record which function triggered the error */
1537 if (func & FM10K_FAULT_FUNC_PF)
1540 fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >>
1541 FM10K_FAULT_FUNC_VF_SHIFT);
1543 /* record fault type */
1544 fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK;
1550 * fm10k_request_lport_map_pf - Request LPORT map from the switch API
1551 * @hw: pointer to hardware structure
1554 static s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw)
1556 struct fm10k_mbx_info *mbx = &hw->mbx;
1559 /* issue request asking for LPORT map */
1560 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP);
1562 /* load onto outgoing mailbox */
1563 return mbx->ops.enqueue_tx(hw, mbx, msg);
1567 * fm10k_get_host_state_pf - Returns the state of the switch and mailbox
1568 * @hw: pointer to hardware structure
1569 * @switch_ready: pointer to boolean value that will record switch state
1571 * This funciton will check the DMA_CTRL2 register and mailbox in order
1572 * to determine if the switch is ready for the PF to begin requesting
1573 * addresses and mapping traffic to the local interface.
1575 static s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready)
1580 /* verify the switch is ready for interaction */
1581 dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2);
1582 if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY))
1585 /* retrieve generic host state info */
1586 ret_val = fm10k_get_host_state_generic(hw, switch_ready);
1590 /* interface cannot receive traffic without logical ports */
1591 if (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE)
1592 ret_val = fm10k_request_lport_map_pf(hw);
1598 /* This structure defines the attibutes to be parsed below */
1599 const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = {
1600 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP),
1605 * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM
1606 * @hw: Pointer to hardware structure
1607 * @results: pointer array containing parsed data
1608 * @mbx: Pointer to mailbox information structure
1610 * This handler configures the lport mapping based on the reply from the
1613 s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results,
1614 struct fm10k_mbx_info *mbx)
1620 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP],
1625 /* extract values out of the header */
1626 glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT);
1627 mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK);
1629 /* verify mask is set and none of the masked bits in glort are set */
1630 if (!mask || (glort & ~mask))
1631 return FM10K_ERR_PARAM;
1633 /* verify the mask is contiguous, and that it is 1's followed by 0's */
1634 if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE)
1635 return FM10K_ERR_PARAM;
1637 /* record the glort, mask, and port count */
1638 hw->mac.dglort_map = dglort_map;
1643 const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = {
1644 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID),
1649 * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM
1650 * @hw: Pointer to hardware structure
1651 * @results: pointer array containing parsed data
1652 * @mbx: Pointer to mailbox information structure
1654 * This handler configures the default VLAN for the PF
1656 s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results,
1657 struct fm10k_mbx_info *mbx)
1663 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID],
1668 /* extract values from the pvid update */
1669 glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT);
1670 pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID);
1672 /* if glort is not valid return error */
1673 if (!fm10k_glort_valid_pf(hw, glort))
1674 return FM10K_ERR_PARAM;
1676 /* verify VID is valid */
1677 if (pvid >= FM10K_VLAN_TABLE_VID_MAX)
1678 return FM10K_ERR_PARAM;
1680 /* record the port VLAN ID value */
1681 hw->mac.default_vid = pvid;
1687 * fm10k_record_global_table_data - Move global table data to swapi table info
1688 * @from: pointer to source table data structure
1689 * @to: pointer to destination table info structure
1691 * This function is will copy table_data to the table_info contained in
1694 static void fm10k_record_global_table_data(struct fm10k_global_table_data *from,
1695 struct fm10k_swapi_table_info *to)
1697 /* convert from le32 struct to CPU byte ordered values */
1698 to->used = le32_to_cpu(from->used);
1699 to->avail = le32_to_cpu(from->avail);
1702 const struct fm10k_tlv_attr fm10k_err_msg_attr[] = {
1703 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR,
1704 sizeof(struct fm10k_swapi_error)),
1709 * fm10k_msg_err_pf - Message handler for error reply
1710 * @hw: Pointer to hardware structure
1711 * @results: pointer array containing parsed data
1712 * @mbx: Pointer to mailbox information structure
1714 * This handler will capture the data for any error replies to previous
1715 * messages that the PF has sent.
1717 s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results,
1718 struct fm10k_mbx_info *mbx)
1720 struct fm10k_swapi_error err_msg;
1723 /* extract structure from message */
1724 err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR],
1725 &err_msg, sizeof(err_msg));
1729 /* record table status */
1730 fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac);
1731 fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop);
1732 fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu);
1734 /* record SW API status value */
1735 hw->swapi.status = le32_to_cpu(err_msg.status);
1740 const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[] = {
1741 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_1588_TIMESTAMP,
1742 sizeof(struct fm10k_swapi_1588_timestamp)),
1746 /* currently there is no shared 1588 timestamp handler */
1749 * fm10k_adjust_systime_pf - Adjust systime frequency
1750 * @hw: pointer to hardware structure
1751 * @ppb: adjustment rate in parts per billion
1753 * This function will adjust the SYSTIME_CFG register contained in BAR 4
1754 * if this function is supported for BAR 4 access. The adjustment amount
1755 * is based on the parts per billion value provided and adjusted to a
1756 * value based on parts per 2^48 clock cycles.
1758 * If adjustment is not supported or the requested value is too large
1759 * we will return an error.
1761 static s32 fm10k_adjust_systime_pf(struct fm10k_hw *hw, s32 ppb)
1765 /* if sw_addr is not set we don't have switch register access */
1767 return ppb ? FM10K_ERR_PARAM : 0;
1769 /* we must convert the value from parts per billion to parts per
1770 * 2^48 cycles. In addition I have opted to only use the 30 most
1771 * significant bits of the adjustment value as the 8 least
1772 * significant bits are located in another register and represent
1773 * a value significantly less than a part per billion, the result
1774 * of dropping the 8 least significant bits is that the adjustment
1775 * value is effectively multiplied by 2^8 when we write it.
1777 * As a result of all this the math for this breaks down as follows:
1778 * ppb / 10^9 == adjust * 2^8 / 2^48
1779 * If we solve this for adjust, and simplify it comes out as:
1780 * ppb * 2^31 / 5^9 == adjust
1782 systime_adjust = (ppb < 0) ? -ppb : ppb;
1783 systime_adjust <<= 31;
1784 do_div(systime_adjust, 1953125);
1786 /* verify the requested adjustment value is in range */
1787 if (systime_adjust > FM10K_SW_SYSTIME_ADJUST_MASK)
1788 return FM10K_ERR_PARAM;
1791 systime_adjust |= FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE;
1793 fm10k_write_sw_reg(hw, FM10K_SW_SYSTIME_ADJUST, (u32)systime_adjust);
1799 * fm10k_read_systime_pf - Reads value of systime registers
1800 * @hw: pointer to the hardware structure
1802 * Function reads the content of 2 registers, combined to represent a 64 bit
1803 * value measured in nanosecods. In order to guarantee the value is accurate
1804 * we check the 32 most significant bits both before and after reading the
1805 * 32 least significant bits to verify they didn't change as we were reading
1808 static u64 fm10k_read_systime_pf(struct fm10k_hw *hw)
1810 u32 systime_l, systime_h, systime_tmp;
1812 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);
1815 systime_tmp = systime_h;
1816 systime_l = fm10k_read_reg(hw, FM10K_SYSTIME);
1817 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);
1818 } while (systime_tmp != systime_h);
1820 return ((u64)systime_h << 32) | systime_l;
1823 static const struct fm10k_msg_data fm10k_msg_data_pf[] = {
1824 FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf),
1825 FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf),
1826 FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf),
1827 FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf),
1828 FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf),
1829 FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf),
1830 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1833 static struct fm10k_mac_ops mac_ops_pf = {
1834 .get_bus_info = &fm10k_get_bus_info_generic,
1835 .reset_hw = &fm10k_reset_hw_pf,
1836 .init_hw = &fm10k_init_hw_pf,
1837 .start_hw = &fm10k_start_hw_generic,
1838 .stop_hw = &fm10k_stop_hw_generic,
1839 .update_vlan = &fm10k_update_vlan_pf,
1840 .read_mac_addr = &fm10k_read_mac_addr_pf,
1841 .update_uc_addr = &fm10k_update_uc_addr_pf,
1842 .update_mc_addr = &fm10k_update_mc_addr_pf,
1843 .update_xcast_mode = &fm10k_update_xcast_mode_pf,
1844 .update_int_moderator = &fm10k_update_int_moderator_pf,
1845 .update_lport_state = &fm10k_update_lport_state_pf,
1846 .update_hw_stats = &fm10k_update_hw_stats_pf,
1847 .rebind_hw_stats = &fm10k_rebind_hw_stats_pf,
1848 .configure_dglort_map = &fm10k_configure_dglort_map_pf,
1849 .set_dma_mask = &fm10k_set_dma_mask_pf,
1850 .get_fault = &fm10k_get_fault_pf,
1851 .get_host_state = &fm10k_get_host_state_pf,
1852 .adjust_systime = &fm10k_adjust_systime_pf,
1853 .read_systime = &fm10k_read_systime_pf,
1856 static struct fm10k_iov_ops iov_ops_pf = {
1857 .assign_resources = &fm10k_iov_assign_resources_pf,
1858 .configure_tc = &fm10k_iov_configure_tc_pf,
1859 .assign_int_moderator = &fm10k_iov_assign_int_moderator_pf,
1860 .assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf,
1861 .reset_resources = &fm10k_iov_reset_resources_pf,
1862 .set_lport = &fm10k_iov_set_lport_pf,
1863 .reset_lport = &fm10k_iov_reset_lport_pf,
1864 .update_stats = &fm10k_iov_update_stats_pf,
1865 .report_timestamp = &fm10k_iov_report_timestamp_pf,
1868 static s32 fm10k_get_invariants_pf(struct fm10k_hw *hw)
1870 fm10k_get_invariants_generic(hw);
1872 return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf);
1875 struct fm10k_info fm10k_pf_info = {
1876 .mac = fm10k_mac_pf,
1877 .get_invariants = &fm10k_get_invariants_pf,
1878 .mac_ops = &mac_ops_pf,
1879 .iov_ops = &iov_ops_pf,