1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
41 i40e_status status = 0;
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
53 case I40E_DEV_ID_10G_BASE_T:
54 case I40E_DEV_ID_20G_KR2:
55 hw->mac.type = I40E_MAC_XL710;
57 case I40E_DEV_ID_SFP_X722:
58 case I40E_DEV_ID_1G_BASE_T_X722:
59 case I40E_DEV_ID_10G_BASE_T_X722:
60 hw->mac.type = I40E_MAC_X722;
62 case I40E_DEV_ID_X722_VF:
63 case I40E_DEV_ID_X722_VF_HV:
64 hw->mac.type = I40E_MAC_X722_VF;
67 case I40E_DEV_ID_VF_HV:
68 hw->mac.type = I40E_MAC_VF;
71 hw->mac.type = I40E_MAC_GENERIC;
75 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
78 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
79 hw->mac.type, status);
84 * i40e_aq_str - convert AQ err code to a string
85 * @hw: pointer to the HW structure
86 * @aq_err: the AQ error code to convert
88 char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
93 case I40E_AQ_RC_EPERM:
94 return "I40E_AQ_RC_EPERM";
95 case I40E_AQ_RC_ENOENT:
96 return "I40E_AQ_RC_ENOENT";
97 case I40E_AQ_RC_ESRCH:
98 return "I40E_AQ_RC_ESRCH";
99 case I40E_AQ_RC_EINTR:
100 return "I40E_AQ_RC_EINTR";
102 return "I40E_AQ_RC_EIO";
103 case I40E_AQ_RC_ENXIO:
104 return "I40E_AQ_RC_ENXIO";
105 case I40E_AQ_RC_E2BIG:
106 return "I40E_AQ_RC_E2BIG";
107 case I40E_AQ_RC_EAGAIN:
108 return "I40E_AQ_RC_EAGAIN";
109 case I40E_AQ_RC_ENOMEM:
110 return "I40E_AQ_RC_ENOMEM";
111 case I40E_AQ_RC_EACCES:
112 return "I40E_AQ_RC_EACCES";
113 case I40E_AQ_RC_EFAULT:
114 return "I40E_AQ_RC_EFAULT";
115 case I40E_AQ_RC_EBUSY:
116 return "I40E_AQ_RC_EBUSY";
117 case I40E_AQ_RC_EEXIST:
118 return "I40E_AQ_RC_EEXIST";
119 case I40E_AQ_RC_EINVAL:
120 return "I40E_AQ_RC_EINVAL";
121 case I40E_AQ_RC_ENOTTY:
122 return "I40E_AQ_RC_ENOTTY";
123 case I40E_AQ_RC_ENOSPC:
124 return "I40E_AQ_RC_ENOSPC";
125 case I40E_AQ_RC_ENOSYS:
126 return "I40E_AQ_RC_ENOSYS";
127 case I40E_AQ_RC_ERANGE:
128 return "I40E_AQ_RC_ERANGE";
129 case I40E_AQ_RC_EFLUSHED:
130 return "I40E_AQ_RC_EFLUSHED";
131 case I40E_AQ_RC_BAD_ADDR:
132 return "I40E_AQ_RC_BAD_ADDR";
133 case I40E_AQ_RC_EMODE:
134 return "I40E_AQ_RC_EMODE";
135 case I40E_AQ_RC_EFBIG:
136 return "I40E_AQ_RC_EFBIG";
139 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
144 * i40e_stat_str - convert status err code to a string
145 * @hw: pointer to the HW structure
146 * @stat_err: the status error code to convert
148 char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
154 return "I40E_ERR_NVM";
155 case I40E_ERR_NVM_CHECKSUM:
156 return "I40E_ERR_NVM_CHECKSUM";
158 return "I40E_ERR_PHY";
159 case I40E_ERR_CONFIG:
160 return "I40E_ERR_CONFIG";
162 return "I40E_ERR_PARAM";
163 case I40E_ERR_MAC_TYPE:
164 return "I40E_ERR_MAC_TYPE";
165 case I40E_ERR_UNKNOWN_PHY:
166 return "I40E_ERR_UNKNOWN_PHY";
167 case I40E_ERR_LINK_SETUP:
168 return "I40E_ERR_LINK_SETUP";
169 case I40E_ERR_ADAPTER_STOPPED:
170 return "I40E_ERR_ADAPTER_STOPPED";
171 case I40E_ERR_INVALID_MAC_ADDR:
172 return "I40E_ERR_INVALID_MAC_ADDR";
173 case I40E_ERR_DEVICE_NOT_SUPPORTED:
174 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
175 case I40E_ERR_MASTER_REQUESTS_PENDING:
176 return "I40E_ERR_MASTER_REQUESTS_PENDING";
177 case I40E_ERR_INVALID_LINK_SETTINGS:
178 return "I40E_ERR_INVALID_LINK_SETTINGS";
179 case I40E_ERR_AUTONEG_NOT_COMPLETE:
180 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
181 case I40E_ERR_RESET_FAILED:
182 return "I40E_ERR_RESET_FAILED";
183 case I40E_ERR_SWFW_SYNC:
184 return "I40E_ERR_SWFW_SYNC";
185 case I40E_ERR_NO_AVAILABLE_VSI:
186 return "I40E_ERR_NO_AVAILABLE_VSI";
187 case I40E_ERR_NO_MEMORY:
188 return "I40E_ERR_NO_MEMORY";
189 case I40E_ERR_BAD_PTR:
190 return "I40E_ERR_BAD_PTR";
191 case I40E_ERR_RING_FULL:
192 return "I40E_ERR_RING_FULL";
193 case I40E_ERR_INVALID_PD_ID:
194 return "I40E_ERR_INVALID_PD_ID";
195 case I40E_ERR_INVALID_QP_ID:
196 return "I40E_ERR_INVALID_QP_ID";
197 case I40E_ERR_INVALID_CQ_ID:
198 return "I40E_ERR_INVALID_CQ_ID";
199 case I40E_ERR_INVALID_CEQ_ID:
200 return "I40E_ERR_INVALID_CEQ_ID";
201 case I40E_ERR_INVALID_AEQ_ID:
202 return "I40E_ERR_INVALID_AEQ_ID";
203 case I40E_ERR_INVALID_SIZE:
204 return "I40E_ERR_INVALID_SIZE";
205 case I40E_ERR_INVALID_ARP_INDEX:
206 return "I40E_ERR_INVALID_ARP_INDEX";
207 case I40E_ERR_INVALID_FPM_FUNC_ID:
208 return "I40E_ERR_INVALID_FPM_FUNC_ID";
209 case I40E_ERR_QP_INVALID_MSG_SIZE:
210 return "I40E_ERR_QP_INVALID_MSG_SIZE";
211 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
212 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
213 case I40E_ERR_INVALID_FRAG_COUNT:
214 return "I40E_ERR_INVALID_FRAG_COUNT";
215 case I40E_ERR_QUEUE_EMPTY:
216 return "I40E_ERR_QUEUE_EMPTY";
217 case I40E_ERR_INVALID_ALIGNMENT:
218 return "I40E_ERR_INVALID_ALIGNMENT";
219 case I40E_ERR_FLUSHED_QUEUE:
220 return "I40E_ERR_FLUSHED_QUEUE";
221 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
222 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
223 case I40E_ERR_INVALID_IMM_DATA_SIZE:
224 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
225 case I40E_ERR_TIMEOUT:
226 return "I40E_ERR_TIMEOUT";
227 case I40E_ERR_OPCODE_MISMATCH:
228 return "I40E_ERR_OPCODE_MISMATCH";
229 case I40E_ERR_CQP_COMPL_ERROR:
230 return "I40E_ERR_CQP_COMPL_ERROR";
231 case I40E_ERR_INVALID_VF_ID:
232 return "I40E_ERR_INVALID_VF_ID";
233 case I40E_ERR_INVALID_HMCFN_ID:
234 return "I40E_ERR_INVALID_HMCFN_ID";
235 case I40E_ERR_BACKING_PAGE_ERROR:
236 return "I40E_ERR_BACKING_PAGE_ERROR";
237 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
238 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
239 case I40E_ERR_INVALID_PBLE_INDEX:
240 return "I40E_ERR_INVALID_PBLE_INDEX";
241 case I40E_ERR_INVALID_SD_INDEX:
242 return "I40E_ERR_INVALID_SD_INDEX";
243 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
244 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
245 case I40E_ERR_INVALID_SD_TYPE:
246 return "I40E_ERR_INVALID_SD_TYPE";
247 case I40E_ERR_MEMCPY_FAILED:
248 return "I40E_ERR_MEMCPY_FAILED";
249 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
250 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
251 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
252 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
253 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
254 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
255 case I40E_ERR_SRQ_ENABLED:
256 return "I40E_ERR_SRQ_ENABLED";
257 case I40E_ERR_ADMIN_QUEUE_ERROR:
258 return "I40E_ERR_ADMIN_QUEUE_ERROR";
259 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
260 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
261 case I40E_ERR_BUF_TOO_SHORT:
262 return "I40E_ERR_BUF_TOO_SHORT";
263 case I40E_ERR_ADMIN_QUEUE_FULL:
264 return "I40E_ERR_ADMIN_QUEUE_FULL";
265 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
266 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
267 case I40E_ERR_BAD_IWARP_CQE:
268 return "I40E_ERR_BAD_IWARP_CQE";
269 case I40E_ERR_NVM_BLANK_MODE:
270 return "I40E_ERR_NVM_BLANK_MODE";
271 case I40E_ERR_NOT_IMPLEMENTED:
272 return "I40E_ERR_NOT_IMPLEMENTED";
273 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
274 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
275 case I40E_ERR_DIAG_TEST_FAILED:
276 return "I40E_ERR_DIAG_TEST_FAILED";
277 case I40E_ERR_NOT_READY:
278 return "I40E_ERR_NOT_READY";
279 case I40E_NOT_SUPPORTED:
280 return "I40E_NOT_SUPPORTED";
281 case I40E_ERR_FIRMWARE_API_VERSION:
282 return "I40E_ERR_FIRMWARE_API_VERSION";
285 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
291 * @hw: debug mask related to admin queue
293 * @desc: pointer to admin queue descriptor
294 * @buffer: pointer to command buffer
295 * @buf_len: max length of buffer
297 * Dumps debug log about adminq command with descriptor contents.
299 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
300 void *buffer, u16 buf_len)
302 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
303 u16 len = le16_to_cpu(aq_desc->datalen);
304 u8 *buf = (u8 *)buffer;
307 if ((!(mask & hw->debug_mask)) || (desc == NULL))
311 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
312 le16_to_cpu(aq_desc->opcode),
313 le16_to_cpu(aq_desc->flags),
314 le16_to_cpu(aq_desc->datalen),
315 le16_to_cpu(aq_desc->retval));
316 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
317 le32_to_cpu(aq_desc->cookie_high),
318 le32_to_cpu(aq_desc->cookie_low));
319 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
320 le32_to_cpu(aq_desc->params.internal.param0),
321 le32_to_cpu(aq_desc->params.internal.param1));
322 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
323 le32_to_cpu(aq_desc->params.external.addr_high),
324 le32_to_cpu(aq_desc->params.external.addr_low));
326 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
327 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
330 /* write the full 16-byte chunks */
331 for (i = 0; i < (len - 16); i += 16)
333 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
334 i, buf[i], buf[i + 1], buf[i + 2],
335 buf[i + 3], buf[i + 4], buf[i + 5],
336 buf[i + 6], buf[i + 7], buf[i + 8],
337 buf[i + 9], buf[i + 10], buf[i + 11],
338 buf[i + 12], buf[i + 13], buf[i + 14],
340 /* write whatever's left over without overrunning the buffer */
345 memset(d_buf, 0, sizeof(d_buf));
346 j += sprintf(d_buf, "\t0x%04X ", i);
348 j += sprintf(&d_buf[j], " %02X", buf[i++]);
349 i40e_debug(hw, mask, "%s\n", d_buf);
355 * i40e_check_asq_alive
356 * @hw: pointer to the hw struct
358 * Returns true if Queue is enabled else false.
360 bool i40e_check_asq_alive(struct i40e_hw *hw)
363 return !!(rd32(hw, hw->aq.asq.len) &
364 I40E_PF_ATQLEN_ATQENABLE_MASK);
370 * i40e_aq_queue_shutdown
371 * @hw: pointer to the hw struct
372 * @unloading: is the driver unloading itself
374 * Tell the Firmware that we're shutting down the AdminQ and whether
375 * or not the driver is unloading as well.
377 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
380 struct i40e_aq_desc desc;
381 struct i40e_aqc_queue_shutdown *cmd =
382 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
385 i40e_fill_default_direct_cmd_desc(&desc,
386 i40e_aqc_opc_queue_shutdown);
389 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
390 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
395 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
396 * hardware to a bit-field that can be used by SW to more easily determine the
399 * Macros are used to shorten the table lines and make this table human
402 * We store the PTYPE in the top byte of the bit field - this is just so that
403 * we can check that the table doesn't have a row missing, as the index into
404 * the table should be the PTYPE.
408 * IF NOT i40e_ptype_lookup[ptype].known
411 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
412 * Use the rest of the fields to look at the tunnels, inner protocols, etc
414 * Use the enum i40e_rx_l2_ptype to decode the packet type
418 /* macro to make the table lines short */
419 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
422 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
423 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
424 I40E_RX_PTYPE_##OUTER_FRAG, \
425 I40E_RX_PTYPE_TUNNEL_##T, \
426 I40E_RX_PTYPE_TUNNEL_END_##TE, \
427 I40E_RX_PTYPE_##TEF, \
428 I40E_RX_PTYPE_INNER_PROT_##I, \
429 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
431 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
432 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
434 /* shorter macros makes the table fit but are terse */
435 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
436 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
437 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
439 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
440 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
441 /* L2 Packet types */
442 I40E_PTT_UNUSED_ENTRY(0),
443 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
444 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
445 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
446 I40E_PTT_UNUSED_ENTRY(4),
447 I40E_PTT_UNUSED_ENTRY(5),
448 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
449 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
450 I40E_PTT_UNUSED_ENTRY(8),
451 I40E_PTT_UNUSED_ENTRY(9),
452 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
453 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
454 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
455 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
456 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
457 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
458 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
459 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
460 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
461 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
462 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
463 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
465 /* Non Tunneled IPv4 */
466 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
467 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
468 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
469 I40E_PTT_UNUSED_ENTRY(25),
470 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
471 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
472 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
475 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
476 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
477 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
478 I40E_PTT_UNUSED_ENTRY(32),
479 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
480 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
481 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
484 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
485 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
486 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
487 I40E_PTT_UNUSED_ENTRY(39),
488 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
489 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
490 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
492 /* IPv4 --> GRE/NAT */
493 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
495 /* IPv4 --> GRE/NAT --> IPv4 */
496 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
497 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
498 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
499 I40E_PTT_UNUSED_ENTRY(47),
500 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
501 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
502 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
504 /* IPv4 --> GRE/NAT --> IPv6 */
505 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
506 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
507 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
508 I40E_PTT_UNUSED_ENTRY(54),
509 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
510 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
511 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
513 /* IPv4 --> GRE/NAT --> MAC */
514 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
516 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
517 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
518 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
519 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
520 I40E_PTT_UNUSED_ENTRY(62),
521 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
522 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
523 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
525 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
526 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
527 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
528 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
529 I40E_PTT_UNUSED_ENTRY(69),
530 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
531 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
532 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
534 /* IPv4 --> GRE/NAT --> MAC/VLAN */
535 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
537 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
538 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
539 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
540 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
541 I40E_PTT_UNUSED_ENTRY(77),
542 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
543 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
544 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
546 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
547 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
548 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
549 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
550 I40E_PTT_UNUSED_ENTRY(84),
551 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
552 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
553 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
555 /* Non Tunneled IPv6 */
556 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
557 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
558 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
559 I40E_PTT_UNUSED_ENTRY(91),
560 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
561 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
562 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
565 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
566 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
567 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
568 I40E_PTT_UNUSED_ENTRY(98),
569 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
570 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
571 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
574 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
575 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
576 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
577 I40E_PTT_UNUSED_ENTRY(105),
578 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
579 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
580 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
582 /* IPv6 --> GRE/NAT */
583 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
585 /* IPv6 --> GRE/NAT -> IPv4 */
586 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
587 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
588 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
589 I40E_PTT_UNUSED_ENTRY(113),
590 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
591 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
592 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
594 /* IPv6 --> GRE/NAT -> IPv6 */
595 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
596 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
597 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
598 I40E_PTT_UNUSED_ENTRY(120),
599 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
600 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
601 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
603 /* IPv6 --> GRE/NAT -> MAC */
604 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
606 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
607 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
608 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
609 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
610 I40E_PTT_UNUSED_ENTRY(128),
611 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
612 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
613 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
615 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
616 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
617 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
618 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
619 I40E_PTT_UNUSED_ENTRY(135),
620 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
621 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
622 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
624 /* IPv6 --> GRE/NAT -> MAC/VLAN */
625 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
627 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
628 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
629 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
630 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
631 I40E_PTT_UNUSED_ENTRY(143),
632 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
633 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
634 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
636 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
637 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
638 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
639 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
640 I40E_PTT_UNUSED_ENTRY(150),
641 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
642 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
643 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
646 I40E_PTT_UNUSED_ENTRY(154),
647 I40E_PTT_UNUSED_ENTRY(155),
648 I40E_PTT_UNUSED_ENTRY(156),
649 I40E_PTT_UNUSED_ENTRY(157),
650 I40E_PTT_UNUSED_ENTRY(158),
651 I40E_PTT_UNUSED_ENTRY(159),
653 I40E_PTT_UNUSED_ENTRY(160),
654 I40E_PTT_UNUSED_ENTRY(161),
655 I40E_PTT_UNUSED_ENTRY(162),
656 I40E_PTT_UNUSED_ENTRY(163),
657 I40E_PTT_UNUSED_ENTRY(164),
658 I40E_PTT_UNUSED_ENTRY(165),
659 I40E_PTT_UNUSED_ENTRY(166),
660 I40E_PTT_UNUSED_ENTRY(167),
661 I40E_PTT_UNUSED_ENTRY(168),
662 I40E_PTT_UNUSED_ENTRY(169),
664 I40E_PTT_UNUSED_ENTRY(170),
665 I40E_PTT_UNUSED_ENTRY(171),
666 I40E_PTT_UNUSED_ENTRY(172),
667 I40E_PTT_UNUSED_ENTRY(173),
668 I40E_PTT_UNUSED_ENTRY(174),
669 I40E_PTT_UNUSED_ENTRY(175),
670 I40E_PTT_UNUSED_ENTRY(176),
671 I40E_PTT_UNUSED_ENTRY(177),
672 I40E_PTT_UNUSED_ENTRY(178),
673 I40E_PTT_UNUSED_ENTRY(179),
675 I40E_PTT_UNUSED_ENTRY(180),
676 I40E_PTT_UNUSED_ENTRY(181),
677 I40E_PTT_UNUSED_ENTRY(182),
678 I40E_PTT_UNUSED_ENTRY(183),
679 I40E_PTT_UNUSED_ENTRY(184),
680 I40E_PTT_UNUSED_ENTRY(185),
681 I40E_PTT_UNUSED_ENTRY(186),
682 I40E_PTT_UNUSED_ENTRY(187),
683 I40E_PTT_UNUSED_ENTRY(188),
684 I40E_PTT_UNUSED_ENTRY(189),
686 I40E_PTT_UNUSED_ENTRY(190),
687 I40E_PTT_UNUSED_ENTRY(191),
688 I40E_PTT_UNUSED_ENTRY(192),
689 I40E_PTT_UNUSED_ENTRY(193),
690 I40E_PTT_UNUSED_ENTRY(194),
691 I40E_PTT_UNUSED_ENTRY(195),
692 I40E_PTT_UNUSED_ENTRY(196),
693 I40E_PTT_UNUSED_ENTRY(197),
694 I40E_PTT_UNUSED_ENTRY(198),
695 I40E_PTT_UNUSED_ENTRY(199),
697 I40E_PTT_UNUSED_ENTRY(200),
698 I40E_PTT_UNUSED_ENTRY(201),
699 I40E_PTT_UNUSED_ENTRY(202),
700 I40E_PTT_UNUSED_ENTRY(203),
701 I40E_PTT_UNUSED_ENTRY(204),
702 I40E_PTT_UNUSED_ENTRY(205),
703 I40E_PTT_UNUSED_ENTRY(206),
704 I40E_PTT_UNUSED_ENTRY(207),
705 I40E_PTT_UNUSED_ENTRY(208),
706 I40E_PTT_UNUSED_ENTRY(209),
708 I40E_PTT_UNUSED_ENTRY(210),
709 I40E_PTT_UNUSED_ENTRY(211),
710 I40E_PTT_UNUSED_ENTRY(212),
711 I40E_PTT_UNUSED_ENTRY(213),
712 I40E_PTT_UNUSED_ENTRY(214),
713 I40E_PTT_UNUSED_ENTRY(215),
714 I40E_PTT_UNUSED_ENTRY(216),
715 I40E_PTT_UNUSED_ENTRY(217),
716 I40E_PTT_UNUSED_ENTRY(218),
717 I40E_PTT_UNUSED_ENTRY(219),
719 I40E_PTT_UNUSED_ENTRY(220),
720 I40E_PTT_UNUSED_ENTRY(221),
721 I40E_PTT_UNUSED_ENTRY(222),
722 I40E_PTT_UNUSED_ENTRY(223),
723 I40E_PTT_UNUSED_ENTRY(224),
724 I40E_PTT_UNUSED_ENTRY(225),
725 I40E_PTT_UNUSED_ENTRY(226),
726 I40E_PTT_UNUSED_ENTRY(227),
727 I40E_PTT_UNUSED_ENTRY(228),
728 I40E_PTT_UNUSED_ENTRY(229),
730 I40E_PTT_UNUSED_ENTRY(230),
731 I40E_PTT_UNUSED_ENTRY(231),
732 I40E_PTT_UNUSED_ENTRY(232),
733 I40E_PTT_UNUSED_ENTRY(233),
734 I40E_PTT_UNUSED_ENTRY(234),
735 I40E_PTT_UNUSED_ENTRY(235),
736 I40E_PTT_UNUSED_ENTRY(236),
737 I40E_PTT_UNUSED_ENTRY(237),
738 I40E_PTT_UNUSED_ENTRY(238),
739 I40E_PTT_UNUSED_ENTRY(239),
741 I40E_PTT_UNUSED_ENTRY(240),
742 I40E_PTT_UNUSED_ENTRY(241),
743 I40E_PTT_UNUSED_ENTRY(242),
744 I40E_PTT_UNUSED_ENTRY(243),
745 I40E_PTT_UNUSED_ENTRY(244),
746 I40E_PTT_UNUSED_ENTRY(245),
747 I40E_PTT_UNUSED_ENTRY(246),
748 I40E_PTT_UNUSED_ENTRY(247),
749 I40E_PTT_UNUSED_ENTRY(248),
750 I40E_PTT_UNUSED_ENTRY(249),
752 I40E_PTT_UNUSED_ENTRY(250),
753 I40E_PTT_UNUSED_ENTRY(251),
754 I40E_PTT_UNUSED_ENTRY(252),
755 I40E_PTT_UNUSED_ENTRY(253),
756 I40E_PTT_UNUSED_ENTRY(254),
757 I40E_PTT_UNUSED_ENTRY(255)
761 * i40e_init_shared_code - Initialize the shared code
762 * @hw: pointer to hardware structure
764 * This assigns the MAC type and PHY code and inits the NVM.
765 * Does not touch the hardware. This function must be called prior to any
766 * other function in the shared code. The i40e_hw structure should be
767 * memset to 0 prior to calling this function. The following fields in
768 * hw structure should be filled in prior to calling this function:
769 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
770 * subsystem_vendor_id, and revision_id
772 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
774 i40e_status status = 0;
775 u32 port, ari, func_rid;
777 i40e_set_mac_type(hw);
779 switch (hw->mac.type) {
784 return I40E_ERR_DEVICE_NOT_SUPPORTED;
787 hw->phy.get_link_info = true;
789 /* Determine port number and PF number*/
790 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
791 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
793 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
794 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
795 func_rid = rd32(hw, I40E_PF_FUNC_RID);
797 hw->pf_id = (u8)(func_rid & 0xff);
799 hw->pf_id = (u8)(func_rid & 0x7);
801 status = i40e_init_nvm(hw);
806 * i40e_aq_mac_address_read - Retrieve the MAC addresses
807 * @hw: pointer to the hw struct
808 * @flags: a return indicator of what addresses were added to the addr store
809 * @addrs: the requestor's mac addr store
810 * @cmd_details: pointer to command details structure or NULL
812 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
814 struct i40e_aqc_mac_address_read_data *addrs,
815 struct i40e_asq_cmd_details *cmd_details)
817 struct i40e_aq_desc desc;
818 struct i40e_aqc_mac_address_read *cmd_data =
819 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
822 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
823 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
825 status = i40e_asq_send_command(hw, &desc, addrs,
826 sizeof(*addrs), cmd_details);
827 *flags = le16_to_cpu(cmd_data->command_flags);
833 * i40e_aq_mac_address_write - Change the MAC addresses
834 * @hw: pointer to the hw struct
835 * @flags: indicates which MAC to be written
836 * @mac_addr: address to write
837 * @cmd_details: pointer to command details structure or NULL
839 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
840 u16 flags, u8 *mac_addr,
841 struct i40e_asq_cmd_details *cmd_details)
843 struct i40e_aq_desc desc;
844 struct i40e_aqc_mac_address_write *cmd_data =
845 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
848 i40e_fill_default_direct_cmd_desc(&desc,
849 i40e_aqc_opc_mac_address_write);
850 cmd_data->command_flags = cpu_to_le16(flags);
851 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
852 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
853 ((u32)mac_addr[3] << 16) |
854 ((u32)mac_addr[4] << 8) |
857 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
863 * i40e_get_mac_addr - get MAC address
864 * @hw: pointer to the HW structure
865 * @mac_addr: pointer to MAC address
867 * Reads the adapter's MAC address from register
869 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
871 struct i40e_aqc_mac_address_read_data addrs;
875 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
877 if (flags & I40E_AQC_LAN_ADDR_VALID)
878 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
884 * i40e_get_port_mac_addr - get Port MAC address
885 * @hw: pointer to the HW structure
886 * @mac_addr: pointer to Port MAC address
888 * Reads the adapter's Port MAC address
890 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
892 struct i40e_aqc_mac_address_read_data addrs;
896 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
900 if (flags & I40E_AQC_PORT_ADDR_VALID)
901 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
903 status = I40E_ERR_INVALID_MAC_ADDR;
909 * i40e_pre_tx_queue_cfg - pre tx queue configure
910 * @hw: pointer to the HW structure
911 * @queue: target PF queue index
912 * @enable: state change request
914 * Handles hw requirement to indicate intention to enable
915 * or disable target queue.
917 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
919 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
923 if (abs_queue_idx >= 128) {
924 reg_block = abs_queue_idx / 128;
925 abs_queue_idx %= 128;
928 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
929 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
930 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
933 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
935 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
937 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
942 * i40e_get_san_mac_addr - get SAN MAC address
943 * @hw: pointer to the HW structure
944 * @mac_addr: pointer to SAN MAC address
946 * Reads the adapter's SAN MAC address from NVM
948 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
950 struct i40e_aqc_mac_address_read_data addrs;
954 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
958 if (flags & I40E_AQC_SAN_ADDR_VALID)
959 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac));
961 status = I40E_ERR_INVALID_MAC_ADDR;
968 * i40e_read_pba_string - Reads part number string from EEPROM
969 * @hw: pointer to hardware structure
970 * @pba_num: stores the part number string from the EEPROM
971 * @pba_num_size: part number string buffer length
973 * Reads the part number string from the EEPROM.
975 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
978 i40e_status status = 0;
984 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
985 if (status || (pba_word != 0xFAFA)) {
986 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
990 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
992 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
996 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
998 hw_dbg(hw, "Failed to read PBA Block size.\n");
1002 /* Subtract one to get PBA word count (PBA Size word is included in
1006 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1007 hw_dbg(hw, "Buffer to small for PBA data.\n");
1008 return I40E_ERR_PARAM;
1011 for (i = 0; i < pba_size; i++) {
1012 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1014 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1018 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1019 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1021 pba_num[(pba_size * 2)] = '\0';
1027 * i40e_get_media_type - Gets media type
1028 * @hw: pointer to the hardware structure
1030 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1032 enum i40e_media_type media;
1034 switch (hw->phy.link_info.phy_type) {
1035 case I40E_PHY_TYPE_10GBASE_SR:
1036 case I40E_PHY_TYPE_10GBASE_LR:
1037 case I40E_PHY_TYPE_1000BASE_SX:
1038 case I40E_PHY_TYPE_1000BASE_LX:
1039 case I40E_PHY_TYPE_40GBASE_SR4:
1040 case I40E_PHY_TYPE_40GBASE_LR4:
1041 media = I40E_MEDIA_TYPE_FIBER;
1043 case I40E_PHY_TYPE_100BASE_TX:
1044 case I40E_PHY_TYPE_1000BASE_T:
1045 case I40E_PHY_TYPE_10GBASE_T:
1046 media = I40E_MEDIA_TYPE_BASET;
1048 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1049 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1050 case I40E_PHY_TYPE_10GBASE_CR1:
1051 case I40E_PHY_TYPE_40GBASE_CR4:
1052 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1053 case I40E_PHY_TYPE_40GBASE_AOC:
1054 case I40E_PHY_TYPE_10GBASE_AOC:
1055 media = I40E_MEDIA_TYPE_DA;
1057 case I40E_PHY_TYPE_1000BASE_KX:
1058 case I40E_PHY_TYPE_10GBASE_KX4:
1059 case I40E_PHY_TYPE_10GBASE_KR:
1060 case I40E_PHY_TYPE_40GBASE_KR4:
1061 case I40E_PHY_TYPE_20GBASE_KR2:
1062 media = I40E_MEDIA_TYPE_BACKPLANE;
1064 case I40E_PHY_TYPE_SGMII:
1065 case I40E_PHY_TYPE_XAUI:
1066 case I40E_PHY_TYPE_XFI:
1067 case I40E_PHY_TYPE_XLAUI:
1068 case I40E_PHY_TYPE_XLPPI:
1070 media = I40E_MEDIA_TYPE_UNKNOWN;
1077 #define I40E_PF_RESET_WAIT_COUNT_A0 200
1078 #define I40E_PF_RESET_WAIT_COUNT 200
1080 * i40e_pf_reset - Reset the PF
1081 * @hw: pointer to the hardware structure
1083 * Assuming someone else has triggered a global reset,
1084 * assure the global reset is complete and then reset the PF
1086 i40e_status i40e_pf_reset(struct i40e_hw *hw)
1093 /* Poll for Global Reset steady state in case of recent GRST.
1094 * The grst delay value is in 100ms units, and we'll wait a
1095 * couple counts longer to be sure we don't just miss the end.
1097 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1098 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1099 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1100 for (cnt = 0; cnt < grst_del + 2; cnt++) {
1101 reg = rd32(hw, I40E_GLGEN_RSTAT);
1102 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1106 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1107 hw_dbg(hw, "Global reset polling failed to complete.\n");
1108 return I40E_ERR_RESET_FAILED;
1111 /* Now Wait for the FW to be ready */
1112 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1113 reg = rd32(hw, I40E_GLNVM_ULD);
1114 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1115 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1116 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1117 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1118 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1121 usleep_range(10000, 20000);
1123 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1124 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1125 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1126 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1127 return I40E_ERR_RESET_FAILED;
1130 /* If there was a Global Reset in progress when we got here,
1131 * we don't need to do the PF Reset
1134 if (hw->revision_id == 0)
1135 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1137 cnt = I40E_PF_RESET_WAIT_COUNT;
1138 reg = rd32(hw, I40E_PFGEN_CTRL);
1139 wr32(hw, I40E_PFGEN_CTRL,
1140 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1141 for (; cnt; cnt--) {
1142 reg = rd32(hw, I40E_PFGEN_CTRL);
1143 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1145 usleep_range(1000, 2000);
1147 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1148 hw_dbg(hw, "PF reset polling failed to complete.\n");
1149 return I40E_ERR_RESET_FAILED;
1153 i40e_clear_pxe_mode(hw);
1159 * i40e_clear_hw - clear out any left over hw state
1160 * @hw: pointer to the hw struct
1162 * Clear queues and interrupts, typically called at init time,
1163 * but after the capabilities have been found so we know how many
1164 * queues and msix vectors have been allocated.
1166 void i40e_clear_hw(struct i40e_hw *hw)
1168 u32 num_queues, base_queue;
1176 /* get number of interrupts, queues, and VFs */
1177 val = rd32(hw, I40E_GLPCI_CNF2);
1178 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1179 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1180 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1181 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1183 val = rd32(hw, I40E_PFLAN_QALLOC);
1184 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1185 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1186 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1187 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1188 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1189 num_queues = (j - base_queue) + 1;
1193 val = rd32(hw, I40E_PF_VT_PFALLOC);
1194 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1195 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1196 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1197 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1198 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1199 num_vfs = (j - i) + 1;
1203 /* stop all the interrupts */
1204 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1205 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1206 for (i = 0; i < num_pf_int - 2; i++)
1207 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1209 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1210 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1211 wr32(hw, I40E_PFINT_LNKLST0, val);
1212 for (i = 0; i < num_pf_int - 2; i++)
1213 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1214 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1215 for (i = 0; i < num_vfs; i++)
1216 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1217 for (i = 0; i < num_vf_int - 2; i++)
1218 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1220 /* warn the HW of the coming Tx disables */
1221 for (i = 0; i < num_queues; i++) {
1222 u32 abs_queue_idx = base_queue + i;
1225 if (abs_queue_idx >= 128) {
1226 reg_block = abs_queue_idx / 128;
1227 abs_queue_idx %= 128;
1230 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1231 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1232 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1233 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1235 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1239 /* stop all the queues */
1240 for (i = 0; i < num_queues; i++) {
1241 wr32(hw, I40E_QINT_TQCTL(i), 0);
1242 wr32(hw, I40E_QTX_ENA(i), 0);
1243 wr32(hw, I40E_QINT_RQCTL(i), 0);
1244 wr32(hw, I40E_QRX_ENA(i), 0);
1247 /* short wait for all queue disables to settle */
1252 * i40e_clear_pxe_mode - clear pxe operations mode
1253 * @hw: pointer to the hw struct
1255 * Make sure all PXE mode settings are cleared, including things
1256 * like descriptor fetch/write-back mode.
1258 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1262 if (i40e_check_asq_alive(hw))
1263 i40e_aq_clear_pxe_mode(hw, NULL);
1265 /* Clear single descriptor fetch/write-back mode */
1266 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1268 if (hw->revision_id == 0) {
1269 /* As a work around clear PXE_MODE instead of setting it */
1270 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1272 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1277 * i40e_led_is_mine - helper to find matching led
1278 * @hw: pointer to the hw struct
1279 * @idx: index into GPIO registers
1281 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1283 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1288 if (!hw->func_caps.led[idx])
1291 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1292 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1293 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1295 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1296 * if it is not our port then ignore
1298 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1305 #define I40E_COMBINED_ACTIVITY 0xA
1306 #define I40E_FILTER_ACTIVITY 0xE
1307 #define I40E_LINK_ACTIVITY 0xC
1308 #define I40E_MAC_ACTIVITY 0xD
1309 #define I40E_LED0 22
1312 * i40e_led_get - return current on/off mode
1313 * @hw: pointer to the hw struct
1315 * The value returned is the 'mode' field as defined in the
1316 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1317 * values are variations of possible behaviors relating to
1318 * blink, link, and wire.
1320 u32 i40e_led_get(struct i40e_hw *hw)
1322 u32 current_mode = 0;
1326 /* as per the documentation GPIO 22-29 are the LED
1327 * GPIO pins named LED0..LED7
1329 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1330 u32 gpio_val = i40e_led_is_mine(hw, i);
1335 /* ignore gpio LED src mode entries related to the activity
1338 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1339 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1340 switch (current_mode) {
1341 case I40E_COMBINED_ACTIVITY:
1342 case I40E_FILTER_ACTIVITY:
1343 case I40E_MAC_ACTIVITY:
1349 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1350 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1358 * i40e_led_set - set new on/off mode
1359 * @hw: pointer to the hw struct
1360 * @mode: 0=off, 0xf=on (else see manual for mode details)
1361 * @blink: true if the LED should blink when on, false if steady
1363 * if this function is used to turn on the blink it should
1364 * be used to disable the blink when restoring the original state.
1366 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1368 u32 current_mode = 0;
1371 if (mode & 0xfffffff0)
1372 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1374 /* as per the documentation GPIO 22-29 are the LED
1375 * GPIO pins named LED0..LED7
1377 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1378 u32 gpio_val = i40e_led_is_mine(hw, i);
1383 /* ignore gpio LED src mode entries related to the activity
1386 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1387 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1388 switch (current_mode) {
1389 case I40E_COMBINED_ACTIVITY:
1390 case I40E_FILTER_ACTIVITY:
1391 case I40E_MAC_ACTIVITY:
1397 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1398 /* this & is a bit of paranoia, but serves as a range check */
1399 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1400 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1402 if (mode == I40E_LINK_ACTIVITY)
1406 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1408 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1410 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1415 /* Admin command wrappers */
1418 * i40e_aq_get_phy_capabilities
1419 * @hw: pointer to the hw struct
1420 * @abilities: structure for PHY capabilities to be filled
1421 * @qualified_modules: report Qualified Modules
1422 * @report_init: report init capabilities (active are default)
1423 * @cmd_details: pointer to command details structure or NULL
1425 * Returns the various PHY abilities supported on the Port.
1427 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1428 bool qualified_modules, bool report_init,
1429 struct i40e_aq_get_phy_abilities_resp *abilities,
1430 struct i40e_asq_cmd_details *cmd_details)
1432 struct i40e_aq_desc desc;
1434 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1437 return I40E_ERR_PARAM;
1439 i40e_fill_default_direct_cmd_desc(&desc,
1440 i40e_aqc_opc_get_phy_abilities);
1442 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1443 if (abilities_size > I40E_AQ_LARGE_BUF)
1444 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1446 if (qualified_modules)
1447 desc.params.external.param0 |=
1448 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1451 desc.params.external.param0 |=
1452 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1454 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1457 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1458 status = I40E_ERR_UNKNOWN_PHY;
1464 * i40e_aq_set_phy_config
1465 * @hw: pointer to the hw struct
1466 * @config: structure with PHY configuration to be set
1467 * @cmd_details: pointer to command details structure or NULL
1469 * Set the various PHY configuration parameters
1470 * supported on the Port.One or more of the Set PHY config parameters may be
1471 * ignored in an MFP mode as the PF may not have the privilege to set some
1472 * of the PHY Config parameters. This status will be indicated by the
1475 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1476 struct i40e_aq_set_phy_config *config,
1477 struct i40e_asq_cmd_details *cmd_details)
1479 struct i40e_aq_desc desc;
1480 struct i40e_aq_set_phy_config *cmd =
1481 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1482 enum i40e_status_code status;
1485 return I40E_ERR_PARAM;
1487 i40e_fill_default_direct_cmd_desc(&desc,
1488 i40e_aqc_opc_set_phy_config);
1492 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1499 * @hw: pointer to the hw struct
1501 * Set the requested flow control mode using set_phy_config.
1503 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1504 bool atomic_restart)
1506 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1507 struct i40e_aq_get_phy_abilities_resp abilities;
1508 struct i40e_aq_set_phy_config config;
1509 enum i40e_status_code status;
1510 u8 pause_mask = 0x0;
1516 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1517 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1519 case I40E_FC_RX_PAUSE:
1520 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1522 case I40E_FC_TX_PAUSE:
1523 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1529 /* Get the current phy config */
1530 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1533 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1537 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1538 /* clear the old pause settings */
1539 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1540 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1541 /* set the new abilities */
1542 config.abilities |= pause_mask;
1543 /* If the abilities have changed, then set the new config */
1544 if (config.abilities != abilities.abilities) {
1545 /* Auto restart link so settings take effect */
1547 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1548 /* Copy over all the old settings */
1549 config.phy_type = abilities.phy_type;
1550 config.link_speed = abilities.link_speed;
1551 config.eee_capability = abilities.eee_capability;
1552 config.eeer = abilities.eeer_val;
1553 config.low_power_ctrl = abilities.d3_lpan;
1554 status = i40e_aq_set_phy_config(hw, &config, NULL);
1557 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1559 /* Update the link info */
1560 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1562 /* Wait a little bit (on 40G cards it sometimes takes a really
1563 * long time for link to come back from the atomic reset)
1567 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1570 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1576 * i40e_aq_clear_pxe_mode
1577 * @hw: pointer to the hw struct
1578 * @cmd_details: pointer to command details structure or NULL
1580 * Tell the firmware that the driver is taking over from PXE
1582 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1583 struct i40e_asq_cmd_details *cmd_details)
1586 struct i40e_aq_desc desc;
1587 struct i40e_aqc_clear_pxe *cmd =
1588 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1590 i40e_fill_default_direct_cmd_desc(&desc,
1591 i40e_aqc_opc_clear_pxe_mode);
1595 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1597 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1603 * i40e_aq_set_link_restart_an
1604 * @hw: pointer to the hw struct
1605 * @enable_link: if true: enable link, if false: disable link
1606 * @cmd_details: pointer to command details structure or NULL
1608 * Sets up the link and restarts the Auto-Negotiation over the link.
1610 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1612 struct i40e_asq_cmd_details *cmd_details)
1614 struct i40e_aq_desc desc;
1615 struct i40e_aqc_set_link_restart_an *cmd =
1616 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1619 i40e_fill_default_direct_cmd_desc(&desc,
1620 i40e_aqc_opc_set_link_restart_an);
1622 cmd->command = I40E_AQ_PHY_RESTART_AN;
1624 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1626 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1628 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1634 * i40e_aq_get_link_info
1635 * @hw: pointer to the hw struct
1636 * @enable_lse: enable/disable LinkStatusEvent reporting
1637 * @link: pointer to link status structure - optional
1638 * @cmd_details: pointer to command details structure or NULL
1640 * Returns the link status of the adapter.
1642 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1643 bool enable_lse, struct i40e_link_status *link,
1644 struct i40e_asq_cmd_details *cmd_details)
1646 struct i40e_aq_desc desc;
1647 struct i40e_aqc_get_link_status *resp =
1648 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1649 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1651 bool tx_pause, rx_pause;
1654 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1657 command_flags = I40E_AQ_LSE_ENABLE;
1659 command_flags = I40E_AQ_LSE_DISABLE;
1660 resp->command_flags = cpu_to_le16(command_flags);
1662 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1665 goto aq_get_link_info_exit;
1667 /* save off old link status information */
1668 hw->phy.link_info_old = *hw_link_info;
1670 /* update link status */
1671 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1672 hw->phy.media_type = i40e_get_media_type(hw);
1673 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1674 hw_link_info->link_info = resp->link_info;
1675 hw_link_info->an_info = resp->an_info;
1676 hw_link_info->ext_info = resp->ext_info;
1677 hw_link_info->loopback = resp->loopback;
1678 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1679 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1681 /* update fc info */
1682 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1683 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1684 if (tx_pause & rx_pause)
1685 hw->fc.current_mode = I40E_FC_FULL;
1687 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1689 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1691 hw->fc.current_mode = I40E_FC_NONE;
1693 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1694 hw_link_info->crc_enable = true;
1696 hw_link_info->crc_enable = false;
1698 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1699 hw_link_info->lse_enable = true;
1701 hw_link_info->lse_enable = false;
1703 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1704 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1705 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1707 /* save link status information */
1709 *link = *hw_link_info;
1711 /* flag cleared so helper functions don't call AQ again */
1712 hw->phy.get_link_info = false;
1714 aq_get_link_info_exit:
1719 * i40e_aq_set_phy_int_mask
1720 * @hw: pointer to the hw struct
1721 * @mask: interrupt mask to be set
1722 * @cmd_details: pointer to command details structure or NULL
1724 * Set link interrupt mask.
1726 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1728 struct i40e_asq_cmd_details *cmd_details)
1730 struct i40e_aq_desc desc;
1731 struct i40e_aqc_set_phy_int_mask *cmd =
1732 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1735 i40e_fill_default_direct_cmd_desc(&desc,
1736 i40e_aqc_opc_set_phy_int_mask);
1738 cmd->event_mask = cpu_to_le16(mask);
1740 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1747 * @hw: pointer to the hw struct
1748 * @vsi_ctx: pointer to a vsi context struct
1749 * @cmd_details: pointer to command details structure or NULL
1751 * Add a VSI context to the hardware.
1753 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1754 struct i40e_vsi_context *vsi_ctx,
1755 struct i40e_asq_cmd_details *cmd_details)
1757 struct i40e_aq_desc desc;
1758 struct i40e_aqc_add_get_update_vsi *cmd =
1759 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1760 struct i40e_aqc_add_get_update_vsi_completion *resp =
1761 (struct i40e_aqc_add_get_update_vsi_completion *)
1765 i40e_fill_default_direct_cmd_desc(&desc,
1766 i40e_aqc_opc_add_vsi);
1768 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1769 cmd->connection_type = vsi_ctx->connection_type;
1770 cmd->vf_id = vsi_ctx->vf_num;
1771 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1773 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1775 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1776 sizeof(vsi_ctx->info), cmd_details);
1779 goto aq_add_vsi_exit;
1781 vsi_ctx->seid = le16_to_cpu(resp->seid);
1782 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1783 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1784 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1791 * i40e_aq_set_vsi_unicast_promiscuous
1792 * @hw: pointer to the hw struct
1794 * @set: set unicast promiscuous enable/disable
1795 * @cmd_details: pointer to command details structure or NULL
1797 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1799 struct i40e_asq_cmd_details *cmd_details)
1801 struct i40e_aq_desc desc;
1802 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1803 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1807 i40e_fill_default_direct_cmd_desc(&desc,
1808 i40e_aqc_opc_set_vsi_promiscuous_modes);
1811 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1813 cmd->promiscuous_flags = cpu_to_le16(flags);
1815 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1817 cmd->seid = cpu_to_le16(seid);
1818 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1824 * i40e_aq_set_vsi_multicast_promiscuous
1825 * @hw: pointer to the hw struct
1827 * @set: set multicast promiscuous enable/disable
1828 * @cmd_details: pointer to command details structure or NULL
1830 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1831 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1833 struct i40e_aq_desc desc;
1834 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1835 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1839 i40e_fill_default_direct_cmd_desc(&desc,
1840 i40e_aqc_opc_set_vsi_promiscuous_modes);
1843 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1845 cmd->promiscuous_flags = cpu_to_le16(flags);
1847 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1849 cmd->seid = cpu_to_le16(seid);
1850 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1856 * i40e_aq_set_vsi_broadcast
1857 * @hw: pointer to the hw struct
1859 * @set_filter: true to set filter, false to clear filter
1860 * @cmd_details: pointer to command details structure or NULL
1862 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1864 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1865 u16 seid, bool set_filter,
1866 struct i40e_asq_cmd_details *cmd_details)
1868 struct i40e_aq_desc desc;
1869 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1870 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1873 i40e_fill_default_direct_cmd_desc(&desc,
1874 i40e_aqc_opc_set_vsi_promiscuous_modes);
1877 cmd->promiscuous_flags
1878 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1880 cmd->promiscuous_flags
1881 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1883 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1884 cmd->seid = cpu_to_le16(seid);
1885 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1891 * i40e_get_vsi_params - get VSI configuration info
1892 * @hw: pointer to the hw struct
1893 * @vsi_ctx: pointer to a vsi context struct
1894 * @cmd_details: pointer to command details structure or NULL
1896 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1897 struct i40e_vsi_context *vsi_ctx,
1898 struct i40e_asq_cmd_details *cmd_details)
1900 struct i40e_aq_desc desc;
1901 struct i40e_aqc_add_get_update_vsi *cmd =
1902 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1903 struct i40e_aqc_add_get_update_vsi_completion *resp =
1904 (struct i40e_aqc_add_get_update_vsi_completion *)
1908 i40e_fill_default_direct_cmd_desc(&desc,
1909 i40e_aqc_opc_get_vsi_parameters);
1911 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1913 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1915 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1916 sizeof(vsi_ctx->info), NULL);
1919 goto aq_get_vsi_params_exit;
1921 vsi_ctx->seid = le16_to_cpu(resp->seid);
1922 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1923 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1924 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1926 aq_get_vsi_params_exit:
1931 * i40e_aq_update_vsi_params
1932 * @hw: pointer to the hw struct
1933 * @vsi_ctx: pointer to a vsi context struct
1934 * @cmd_details: pointer to command details structure or NULL
1936 * Update a VSI context.
1938 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1939 struct i40e_vsi_context *vsi_ctx,
1940 struct i40e_asq_cmd_details *cmd_details)
1942 struct i40e_aq_desc desc;
1943 struct i40e_aqc_add_get_update_vsi *cmd =
1944 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1947 i40e_fill_default_direct_cmd_desc(&desc,
1948 i40e_aqc_opc_update_vsi_parameters);
1949 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1951 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1953 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1954 sizeof(vsi_ctx->info), cmd_details);
1960 * i40e_aq_get_switch_config
1961 * @hw: pointer to the hardware structure
1962 * @buf: pointer to the result buffer
1963 * @buf_size: length of input buffer
1964 * @start_seid: seid to start for the report, 0 == beginning
1965 * @cmd_details: pointer to command details structure or NULL
1967 * Fill the buf with switch configuration returned from AdminQ command
1969 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1970 struct i40e_aqc_get_switch_config_resp *buf,
1971 u16 buf_size, u16 *start_seid,
1972 struct i40e_asq_cmd_details *cmd_details)
1974 struct i40e_aq_desc desc;
1975 struct i40e_aqc_switch_seid *scfg =
1976 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1979 i40e_fill_default_direct_cmd_desc(&desc,
1980 i40e_aqc_opc_get_switch_config);
1981 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1982 if (buf_size > I40E_AQ_LARGE_BUF)
1983 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1984 scfg->seid = cpu_to_le16(*start_seid);
1986 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1987 *start_seid = le16_to_cpu(scfg->seid);
1993 * i40e_aq_get_firmware_version
1994 * @hw: pointer to the hw struct
1995 * @fw_major_version: firmware major version
1996 * @fw_minor_version: firmware minor version
1997 * @fw_build: firmware build number
1998 * @api_major_version: major queue version
1999 * @api_minor_version: minor queue version
2000 * @cmd_details: pointer to command details structure or NULL
2002 * Get the firmware version from the admin queue commands
2004 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2005 u16 *fw_major_version, u16 *fw_minor_version,
2007 u16 *api_major_version, u16 *api_minor_version,
2008 struct i40e_asq_cmd_details *cmd_details)
2010 struct i40e_aq_desc desc;
2011 struct i40e_aqc_get_version *resp =
2012 (struct i40e_aqc_get_version *)&desc.params.raw;
2015 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2017 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2020 if (fw_major_version)
2021 *fw_major_version = le16_to_cpu(resp->fw_major);
2022 if (fw_minor_version)
2023 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2025 *fw_build = le32_to_cpu(resp->fw_build);
2026 if (api_major_version)
2027 *api_major_version = le16_to_cpu(resp->api_major);
2028 if (api_minor_version)
2029 *api_minor_version = le16_to_cpu(resp->api_minor);
2036 * i40e_aq_send_driver_version
2037 * @hw: pointer to the hw struct
2038 * @dv: driver's major, minor version
2039 * @cmd_details: pointer to command details structure or NULL
2041 * Send the driver version to the firmware
2043 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2044 struct i40e_driver_version *dv,
2045 struct i40e_asq_cmd_details *cmd_details)
2047 struct i40e_aq_desc desc;
2048 struct i40e_aqc_driver_version *cmd =
2049 (struct i40e_aqc_driver_version *)&desc.params.raw;
2054 return I40E_ERR_PARAM;
2056 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2058 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2059 cmd->driver_major_ver = dv->major_version;
2060 cmd->driver_minor_ver = dv->minor_version;
2061 cmd->driver_build_ver = dv->build_version;
2062 cmd->driver_subbuild_ver = dv->subbuild_version;
2065 while (len < sizeof(dv->driver_string) &&
2066 (dv->driver_string[len] < 0x80) &&
2067 dv->driver_string[len])
2069 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2076 * i40e_get_link_status - get status of the HW network link
2077 * @hw: pointer to the hw struct
2079 * Returns true if link is up, false if link is down.
2081 * Side effect: LinkStatusEvent reporting becomes enabled
2083 bool i40e_get_link_status(struct i40e_hw *hw)
2085 i40e_status status = 0;
2086 bool link_status = false;
2088 if (hw->phy.get_link_info) {
2089 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2092 goto i40e_get_link_status_exit;
2095 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2097 i40e_get_link_status_exit:
2102 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2103 * @hw: pointer to the hw struct
2104 * @uplink_seid: the MAC or other gizmo SEID
2105 * @downlink_seid: the VSI SEID
2106 * @enabled_tc: bitmap of TCs to be enabled
2107 * @default_port: true for default port VSI, false for control port
2108 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2109 * @veb_seid: pointer to where to put the resulting VEB SEID
2110 * @cmd_details: pointer to command details structure or NULL
2112 * This asks the FW to add a VEB between the uplink and downlink
2113 * elements. If the uplink SEID is 0, this will be a floating VEB.
2115 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2116 u16 downlink_seid, u8 enabled_tc,
2117 bool default_port, bool enable_l2_filtering,
2119 struct i40e_asq_cmd_details *cmd_details)
2121 struct i40e_aq_desc desc;
2122 struct i40e_aqc_add_veb *cmd =
2123 (struct i40e_aqc_add_veb *)&desc.params.raw;
2124 struct i40e_aqc_add_veb_completion *resp =
2125 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2129 /* SEIDs need to either both be set or both be 0 for floating VEB */
2130 if (!!uplink_seid != !!downlink_seid)
2131 return I40E_ERR_PARAM;
2133 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2135 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2136 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2137 cmd->enable_tcs = enabled_tc;
2139 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2141 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2143 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2145 if (enable_l2_filtering)
2146 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2148 cmd->veb_flags = cpu_to_le16(veb_flags);
2150 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2152 if (!status && veb_seid)
2153 *veb_seid = le16_to_cpu(resp->veb_seid);
2159 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2160 * @hw: pointer to the hw struct
2161 * @veb_seid: the SEID of the VEB to query
2162 * @switch_id: the uplink switch id
2163 * @floating: set to true if the VEB is floating
2164 * @statistic_index: index of the stats counter block for this VEB
2165 * @vebs_used: number of VEB's used by function
2166 * @vebs_free: total VEB's not reserved by any function
2167 * @cmd_details: pointer to command details structure or NULL
2169 * This retrieves the parameters for a particular VEB, specified by
2170 * uplink_seid, and returns them to the caller.
2172 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2173 u16 veb_seid, u16 *switch_id,
2174 bool *floating, u16 *statistic_index,
2175 u16 *vebs_used, u16 *vebs_free,
2176 struct i40e_asq_cmd_details *cmd_details)
2178 struct i40e_aq_desc desc;
2179 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2180 (struct i40e_aqc_get_veb_parameters_completion *)
2185 return I40E_ERR_PARAM;
2187 i40e_fill_default_direct_cmd_desc(&desc,
2188 i40e_aqc_opc_get_veb_parameters);
2189 cmd_resp->seid = cpu_to_le16(veb_seid);
2191 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2196 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2197 if (statistic_index)
2198 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2200 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2202 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2204 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2205 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2216 * i40e_aq_add_macvlan
2217 * @hw: pointer to the hw struct
2218 * @seid: VSI for the mac address
2219 * @mv_list: list of macvlans to be added
2220 * @count: length of the list
2221 * @cmd_details: pointer to command details structure or NULL
2223 * Add MAC/VLAN addresses to the HW filtering
2225 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2226 struct i40e_aqc_add_macvlan_element_data *mv_list,
2227 u16 count, struct i40e_asq_cmd_details *cmd_details)
2229 struct i40e_aq_desc desc;
2230 struct i40e_aqc_macvlan *cmd =
2231 (struct i40e_aqc_macvlan *)&desc.params.raw;
2235 if (count == 0 || !mv_list || !hw)
2236 return I40E_ERR_PARAM;
2238 buf_size = count * sizeof(*mv_list);
2240 /* prep the rest of the request */
2241 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2242 cmd->num_addresses = cpu_to_le16(count);
2243 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2247 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2248 if (buf_size > I40E_AQ_LARGE_BUF)
2249 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2251 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2258 * i40e_aq_remove_macvlan
2259 * @hw: pointer to the hw struct
2260 * @seid: VSI for the mac address
2261 * @mv_list: list of macvlans to be removed
2262 * @count: length of the list
2263 * @cmd_details: pointer to command details structure or NULL
2265 * Remove MAC/VLAN addresses from the HW filtering
2267 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2268 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2269 u16 count, struct i40e_asq_cmd_details *cmd_details)
2271 struct i40e_aq_desc desc;
2272 struct i40e_aqc_macvlan *cmd =
2273 (struct i40e_aqc_macvlan *)&desc.params.raw;
2277 if (count == 0 || !mv_list || !hw)
2278 return I40E_ERR_PARAM;
2280 buf_size = count * sizeof(*mv_list);
2282 /* prep the rest of the request */
2283 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2284 cmd->num_addresses = cpu_to_le16(count);
2285 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2289 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2290 if (buf_size > I40E_AQ_LARGE_BUF)
2291 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2293 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2300 * i40e_aq_send_msg_to_vf
2301 * @hw: pointer to the hardware structure
2302 * @vfid: VF id to send msg
2303 * @v_opcode: opcodes for VF-PF communication
2304 * @v_retval: return error code
2305 * @msg: pointer to the msg buffer
2306 * @msglen: msg length
2307 * @cmd_details: pointer to command details
2311 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2312 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2313 struct i40e_asq_cmd_details *cmd_details)
2315 struct i40e_aq_desc desc;
2316 struct i40e_aqc_pf_vf_message *cmd =
2317 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2320 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2321 cmd->id = cpu_to_le32(vfid);
2322 desc.cookie_high = cpu_to_le32(v_opcode);
2323 desc.cookie_low = cpu_to_le32(v_retval);
2324 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2326 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2328 if (msglen > I40E_AQ_LARGE_BUF)
2329 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2330 desc.datalen = cpu_to_le16(msglen);
2332 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2338 * i40e_aq_debug_read_register
2339 * @hw: pointer to the hw struct
2340 * @reg_addr: register address
2341 * @reg_val: register value
2342 * @cmd_details: pointer to command details structure or NULL
2344 * Read the register using the admin queue commands
2346 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2347 u32 reg_addr, u64 *reg_val,
2348 struct i40e_asq_cmd_details *cmd_details)
2350 struct i40e_aq_desc desc;
2351 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2352 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2355 if (reg_val == NULL)
2356 return I40E_ERR_PARAM;
2358 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2360 cmd_resp->address = cpu_to_le32(reg_addr);
2362 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2365 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2366 (u64)le32_to_cpu(cmd_resp->value_low);
2373 * i40e_aq_debug_write_register
2374 * @hw: pointer to the hw struct
2375 * @reg_addr: register address
2376 * @reg_val: register value
2377 * @cmd_details: pointer to command details structure or NULL
2379 * Write to a register using the admin queue commands
2381 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2382 u32 reg_addr, u64 reg_val,
2383 struct i40e_asq_cmd_details *cmd_details)
2385 struct i40e_aq_desc desc;
2386 struct i40e_aqc_debug_reg_read_write *cmd =
2387 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2390 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2392 cmd->address = cpu_to_le32(reg_addr);
2393 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2394 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2396 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2402 * i40e_aq_set_hmc_resource_profile
2403 * @hw: pointer to the hw struct
2404 * @profile: type of profile the HMC is to be set as
2405 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2406 * @cmd_details: pointer to command details structure or NULL
2408 * set the HMC profile of the device.
2410 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2411 enum i40e_aq_hmc_profile profile,
2412 u8 pe_vf_enabled_count,
2413 struct i40e_asq_cmd_details *cmd_details)
2415 struct i40e_aq_desc desc;
2416 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2417 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2420 i40e_fill_default_direct_cmd_desc(&desc,
2421 i40e_aqc_opc_set_hmc_resource_profile);
2423 cmd->pm_profile = (u8)profile;
2424 cmd->pe_vf_enabled = pe_vf_enabled_count;
2426 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2432 * i40e_aq_request_resource
2433 * @hw: pointer to the hw struct
2434 * @resource: resource id
2435 * @access: access type
2436 * @sdp_number: resource number
2437 * @timeout: the maximum time in ms that the driver may hold the resource
2438 * @cmd_details: pointer to command details structure or NULL
2440 * requests common resource using the admin queue commands
2442 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2443 enum i40e_aq_resources_ids resource,
2444 enum i40e_aq_resource_access_type access,
2445 u8 sdp_number, u64 *timeout,
2446 struct i40e_asq_cmd_details *cmd_details)
2448 struct i40e_aq_desc desc;
2449 struct i40e_aqc_request_resource *cmd_resp =
2450 (struct i40e_aqc_request_resource *)&desc.params.raw;
2453 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2455 cmd_resp->resource_id = cpu_to_le16(resource);
2456 cmd_resp->access_type = cpu_to_le16(access);
2457 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2459 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2460 /* The completion specifies the maximum time in ms that the driver
2461 * may hold the resource in the Timeout field.
2462 * If the resource is held by someone else, the command completes with
2463 * busy return value and the timeout field indicates the maximum time
2464 * the current owner of the resource has to free it.
2466 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2467 *timeout = le32_to_cpu(cmd_resp->timeout);
2473 * i40e_aq_release_resource
2474 * @hw: pointer to the hw struct
2475 * @resource: resource id
2476 * @sdp_number: resource number
2477 * @cmd_details: pointer to command details structure or NULL
2479 * release common resource using the admin queue commands
2481 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2482 enum i40e_aq_resources_ids resource,
2484 struct i40e_asq_cmd_details *cmd_details)
2486 struct i40e_aq_desc desc;
2487 struct i40e_aqc_request_resource *cmd =
2488 (struct i40e_aqc_request_resource *)&desc.params.raw;
2491 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2493 cmd->resource_id = cpu_to_le16(resource);
2494 cmd->resource_number = cpu_to_le32(sdp_number);
2496 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2503 * @hw: pointer to the hw struct
2504 * @module_pointer: module pointer location in words from the NVM beginning
2505 * @offset: byte offset from the module beginning
2506 * @length: length of the section to be read (in bytes from the offset)
2507 * @data: command buffer (size [bytes] = length)
2508 * @last_command: tells if this is the last command in a series
2509 * @cmd_details: pointer to command details structure or NULL
2511 * Read the NVM using the admin queue commands
2513 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2514 u32 offset, u16 length, void *data,
2516 struct i40e_asq_cmd_details *cmd_details)
2518 struct i40e_aq_desc desc;
2519 struct i40e_aqc_nvm_update *cmd =
2520 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2523 /* In offset the highest byte must be zeroed. */
2524 if (offset & 0xFF000000) {
2525 status = I40E_ERR_PARAM;
2526 goto i40e_aq_read_nvm_exit;
2529 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2531 /* If this is the last command in a series, set the proper flag. */
2533 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2534 cmd->module_pointer = module_pointer;
2535 cmd->offset = cpu_to_le32(offset);
2536 cmd->length = cpu_to_le16(length);
2538 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2539 if (length > I40E_AQ_LARGE_BUF)
2540 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2542 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2544 i40e_aq_read_nvm_exit:
2550 * @hw: pointer to the hw struct
2551 * @module_pointer: module pointer location in words from the NVM beginning
2552 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2553 * @length: length of the section to be erased (expressed in 4 KB)
2554 * @last_command: tells if this is the last command in a series
2555 * @cmd_details: pointer to command details structure or NULL
2557 * Erase the NVM sector using the admin queue commands
2559 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2560 u32 offset, u16 length, bool last_command,
2561 struct i40e_asq_cmd_details *cmd_details)
2563 struct i40e_aq_desc desc;
2564 struct i40e_aqc_nvm_update *cmd =
2565 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2568 /* In offset the highest byte must be zeroed. */
2569 if (offset & 0xFF000000) {
2570 status = I40E_ERR_PARAM;
2571 goto i40e_aq_erase_nvm_exit;
2574 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2576 /* If this is the last command in a series, set the proper flag. */
2578 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2579 cmd->module_pointer = module_pointer;
2580 cmd->offset = cpu_to_le32(offset);
2581 cmd->length = cpu_to_le16(length);
2583 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2585 i40e_aq_erase_nvm_exit:
2589 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2590 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2591 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2592 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2593 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2594 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2595 #define I40E_DEV_FUNC_CAP_VF 0x13
2596 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2597 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2598 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2599 #define I40E_DEV_FUNC_CAP_VSI 0x17
2600 #define I40E_DEV_FUNC_CAP_DCB 0x18
2601 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2602 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
2603 #define I40E_DEV_FUNC_CAP_RSS 0x40
2604 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2605 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2606 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2607 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2608 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2609 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2610 #define I40E_DEV_FUNC_CAP_FLEX10 0xF1
2611 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2612 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2613 #define I40E_DEV_FUNC_CAP_LED 0x61
2614 #define I40E_DEV_FUNC_CAP_SDP 0x62
2615 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2616 #define I40E_DEV_FUNC_CAP_WR_CSR_PROT 0x64
2619 * i40e_parse_discover_capabilities
2620 * @hw: pointer to the hw struct
2621 * @buff: pointer to a buffer containing device/function capability records
2622 * @cap_count: number of capability records in the list
2623 * @list_type_opc: type of capabilities list to parse
2625 * Parse the device/function capabilities list.
2627 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2629 enum i40e_admin_queue_opc list_type_opc)
2631 struct i40e_aqc_list_capabilities_element_resp *cap;
2632 u32 valid_functions, num_functions;
2633 u32 number, logical_id, phys_id;
2634 struct i40e_hw_capabilities *p;
2639 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2641 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2643 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2648 for (i = 0; i < cap_count; i++, cap++) {
2649 id = le16_to_cpu(cap->id);
2650 number = le32_to_cpu(cap->number);
2651 logical_id = le32_to_cpu(cap->logical_id);
2652 phys_id = le32_to_cpu(cap->phys_id);
2653 major_rev = cap->major_rev;
2656 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2657 p->switch_mode = number;
2659 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2660 p->management_mode = number;
2662 case I40E_DEV_FUNC_CAP_NPAR:
2663 p->npar_enable = number;
2665 case I40E_DEV_FUNC_CAP_OS2BMC:
2668 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2669 p->valid_functions = number;
2671 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2673 p->sr_iov_1_1 = true;
2675 case I40E_DEV_FUNC_CAP_VF:
2676 p->num_vfs = number;
2677 p->vf_base_id = logical_id;
2679 case I40E_DEV_FUNC_CAP_VMDQ:
2683 case I40E_DEV_FUNC_CAP_802_1_QBG:
2685 p->evb_802_1_qbg = true;
2687 case I40E_DEV_FUNC_CAP_802_1_QBH:
2689 p->evb_802_1_qbh = true;
2691 case I40E_DEV_FUNC_CAP_VSI:
2692 p->num_vsis = number;
2694 case I40E_DEV_FUNC_CAP_DCB:
2697 p->enabled_tcmap = logical_id;
2701 case I40E_DEV_FUNC_CAP_FCOE:
2705 case I40E_DEV_FUNC_CAP_ISCSI:
2709 case I40E_DEV_FUNC_CAP_RSS:
2711 p->rss_table_size = number;
2712 p->rss_table_entry_width = logical_id;
2714 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2715 p->num_rx_qp = number;
2716 p->base_queue = phys_id;
2718 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2719 p->num_tx_qp = number;
2720 p->base_queue = phys_id;
2722 case I40E_DEV_FUNC_CAP_MSIX:
2723 p->num_msix_vectors = number;
2725 case I40E_DEV_FUNC_CAP_MSIX_VF:
2726 p->num_msix_vectors_vf = number;
2728 case I40E_DEV_FUNC_CAP_FLEX10:
2729 if (major_rev == 1) {
2731 p->flex10_enable = true;
2732 p->flex10_capable = true;
2735 /* Capability revision >= 2 */
2737 p->flex10_enable = true;
2739 p->flex10_capable = true;
2741 p->flex10_mode = logical_id;
2742 p->flex10_status = phys_id;
2744 case I40E_DEV_FUNC_CAP_CEM:
2748 case I40E_DEV_FUNC_CAP_IWARP:
2752 case I40E_DEV_FUNC_CAP_LED:
2753 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2754 p->led[phys_id] = true;
2756 case I40E_DEV_FUNC_CAP_SDP:
2757 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2758 p->sdp[phys_id] = true;
2760 case I40E_DEV_FUNC_CAP_MDIO:
2762 p->mdio_port_num = phys_id;
2763 p->mdio_port_mode = logical_id;
2766 case I40E_DEV_FUNC_CAP_IEEE_1588:
2768 p->ieee_1588 = true;
2770 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2772 p->fd_filters_guaranteed = number;
2773 p->fd_filters_best_effort = logical_id;
2775 case I40E_DEV_FUNC_CAP_WR_CSR_PROT:
2776 p->wr_csr_prot = (u64)number;
2777 p->wr_csr_prot |= (u64)logical_id << 32;
2785 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
2787 /* Software override ensuring FCoE is disabled if npar or mfp
2788 * mode because it is not supported in these modes.
2790 if (p->npar_enable || p->flex10_enable)
2793 /* count the enabled ports (aka the "not disabled" ports) */
2795 for (i = 0; i < 4; i++) {
2796 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2799 /* use AQ read to get the physical register offset instead
2800 * of the port relative offset
2802 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2803 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2807 valid_functions = p->valid_functions;
2809 while (valid_functions) {
2810 if (valid_functions & 1)
2812 valid_functions >>= 1;
2815 /* partition id is 1-based, and functions are evenly spread
2816 * across the ports as partitions
2818 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
2819 hw->num_partitions = num_functions / hw->num_ports;
2821 /* additional HW specific goodies that might
2822 * someday be HW version specific
2824 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2828 * i40e_aq_discover_capabilities
2829 * @hw: pointer to the hw struct
2830 * @buff: a virtual buffer to hold the capabilities
2831 * @buff_size: Size of the virtual buffer
2832 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2833 * @list_type_opc: capabilities type to discover - pass in the command opcode
2834 * @cmd_details: pointer to command details structure or NULL
2836 * Get the device capabilities descriptions from the firmware
2838 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
2839 void *buff, u16 buff_size, u16 *data_size,
2840 enum i40e_admin_queue_opc list_type_opc,
2841 struct i40e_asq_cmd_details *cmd_details)
2843 struct i40e_aqc_list_capabilites *cmd;
2844 struct i40e_aq_desc desc;
2845 i40e_status status = 0;
2847 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2849 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2850 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2851 status = I40E_ERR_PARAM;
2855 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2857 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2858 if (buff_size > I40E_AQ_LARGE_BUF)
2859 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2861 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2862 *data_size = le16_to_cpu(desc.datalen);
2867 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
2875 * i40e_aq_update_nvm
2876 * @hw: pointer to the hw struct
2877 * @module_pointer: module pointer location in words from the NVM beginning
2878 * @offset: byte offset from the module beginning
2879 * @length: length of the section to be written (in bytes from the offset)
2880 * @data: command buffer (size [bytes] = length)
2881 * @last_command: tells if this is the last command in a series
2882 * @cmd_details: pointer to command details structure or NULL
2884 * Update the NVM using the admin queue commands
2886 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2887 u32 offset, u16 length, void *data,
2889 struct i40e_asq_cmd_details *cmd_details)
2891 struct i40e_aq_desc desc;
2892 struct i40e_aqc_nvm_update *cmd =
2893 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2896 /* In offset the highest byte must be zeroed. */
2897 if (offset & 0xFF000000) {
2898 status = I40E_ERR_PARAM;
2899 goto i40e_aq_update_nvm_exit;
2902 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2904 /* If this is the last command in a series, set the proper flag. */
2906 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2907 cmd->module_pointer = module_pointer;
2908 cmd->offset = cpu_to_le32(offset);
2909 cmd->length = cpu_to_le16(length);
2911 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2912 if (length > I40E_AQ_LARGE_BUF)
2913 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2915 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2917 i40e_aq_update_nvm_exit:
2922 * i40e_aq_get_lldp_mib
2923 * @hw: pointer to the hw struct
2924 * @bridge_type: type of bridge requested
2925 * @mib_type: Local, Remote or both Local and Remote MIBs
2926 * @buff: pointer to a user supplied buffer to store the MIB block
2927 * @buff_size: size of the buffer (in bytes)
2928 * @local_len : length of the returned Local LLDP MIB
2929 * @remote_len: length of the returned Remote LLDP MIB
2930 * @cmd_details: pointer to command details structure or NULL
2932 * Requests the complete LLDP MIB (entire packet).
2934 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2935 u8 mib_type, void *buff, u16 buff_size,
2936 u16 *local_len, u16 *remote_len,
2937 struct i40e_asq_cmd_details *cmd_details)
2939 struct i40e_aq_desc desc;
2940 struct i40e_aqc_lldp_get_mib *cmd =
2941 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2942 struct i40e_aqc_lldp_get_mib *resp =
2943 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2946 if (buff_size == 0 || !buff)
2947 return I40E_ERR_PARAM;
2949 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2950 /* Indirect Command */
2951 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2953 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2954 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2955 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2957 desc.datalen = cpu_to_le16(buff_size);
2959 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2960 if (buff_size > I40E_AQ_LARGE_BUF)
2961 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2963 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2965 if (local_len != NULL)
2966 *local_len = le16_to_cpu(resp->local_len);
2967 if (remote_len != NULL)
2968 *remote_len = le16_to_cpu(resp->remote_len);
2975 * i40e_aq_cfg_lldp_mib_change_event
2976 * @hw: pointer to the hw struct
2977 * @enable_update: Enable or Disable event posting
2978 * @cmd_details: pointer to command details structure or NULL
2980 * Enable or Disable posting of an event on ARQ when LLDP MIB
2981 * associated with the interface changes
2983 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2985 struct i40e_asq_cmd_details *cmd_details)
2987 struct i40e_aq_desc desc;
2988 struct i40e_aqc_lldp_update_mib *cmd =
2989 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2992 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2995 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2997 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3004 * @hw: pointer to the hw struct
3005 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3006 * @cmd_details: pointer to command details structure or NULL
3008 * Stop or Shutdown the embedded LLDP Agent
3010 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3011 struct i40e_asq_cmd_details *cmd_details)
3013 struct i40e_aq_desc desc;
3014 struct i40e_aqc_lldp_stop *cmd =
3015 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3018 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3021 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3023 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3029 * i40e_aq_start_lldp
3030 * @hw: pointer to the hw struct
3031 * @cmd_details: pointer to command details structure or NULL
3033 * Start the embedded LLDP Agent on all ports.
3035 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3036 struct i40e_asq_cmd_details *cmd_details)
3038 struct i40e_aq_desc desc;
3039 struct i40e_aqc_lldp_start *cmd =
3040 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3043 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3045 cmd->command = I40E_AQ_LLDP_AGENT_START;
3047 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3053 * i40e_aq_get_cee_dcb_config
3054 * @hw: pointer to the hw struct
3055 * @buff: response buffer that stores CEE operational configuration
3056 * @buff_size: size of the buffer passed
3057 * @cmd_details: pointer to command details structure or NULL
3059 * Get CEE DCBX mode operational configuration from firmware
3061 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3062 void *buff, u16 buff_size,
3063 struct i40e_asq_cmd_details *cmd_details)
3065 struct i40e_aq_desc desc;
3068 if (buff_size == 0 || !buff)
3069 return I40E_ERR_PARAM;
3071 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3073 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3074 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3081 * i40e_aq_add_udp_tunnel
3082 * @hw: pointer to the hw struct
3083 * @udp_port: the UDP port to add
3084 * @header_len: length of the tunneling header length in DWords
3085 * @protocol_index: protocol index type
3086 * @filter_index: pointer to filter index
3087 * @cmd_details: pointer to command details structure or NULL
3089 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3090 u16 udp_port, u8 protocol_index,
3092 struct i40e_asq_cmd_details *cmd_details)
3094 struct i40e_aq_desc desc;
3095 struct i40e_aqc_add_udp_tunnel *cmd =
3096 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3097 struct i40e_aqc_del_udp_tunnel_completion *resp =
3098 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3101 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3103 cmd->udp_port = cpu_to_le16(udp_port);
3104 cmd->protocol_type = protocol_index;
3106 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3108 if (!status && filter_index)
3109 *filter_index = resp->index;
3115 * i40e_aq_del_udp_tunnel
3116 * @hw: pointer to the hw struct
3117 * @index: filter index
3118 * @cmd_details: pointer to command details structure or NULL
3120 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3121 struct i40e_asq_cmd_details *cmd_details)
3123 struct i40e_aq_desc desc;
3124 struct i40e_aqc_remove_udp_tunnel *cmd =
3125 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3128 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3132 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3138 * i40e_aq_delete_element - Delete switch element
3139 * @hw: pointer to the hw struct
3140 * @seid: the SEID to delete from the switch
3141 * @cmd_details: pointer to command details structure or NULL
3143 * This deletes a switch element from the switch.
3145 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3146 struct i40e_asq_cmd_details *cmd_details)
3148 struct i40e_aq_desc desc;
3149 struct i40e_aqc_switch_seid *cmd =
3150 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3154 return I40E_ERR_PARAM;
3156 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3158 cmd->seid = cpu_to_le16(seid);
3160 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3166 * i40e_aq_dcb_updated - DCB Updated Command
3167 * @hw: pointer to the hw struct
3168 * @cmd_details: pointer to command details structure or NULL
3170 * EMP will return when the shared RPB settings have been
3171 * recomputed and modified. The retval field in the descriptor
3172 * will be set to 0 when RPB is modified.
3174 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3175 struct i40e_asq_cmd_details *cmd_details)
3177 struct i40e_aq_desc desc;
3180 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3182 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3188 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3189 * @hw: pointer to the hw struct
3190 * @seid: seid for the physical port/switching component/vsi
3191 * @buff: Indirect buffer to hold data parameters and response
3192 * @buff_size: Indirect buffer size
3193 * @opcode: Tx scheduler AQ command opcode
3194 * @cmd_details: pointer to command details structure or NULL
3196 * Generic command handler for Tx scheduler AQ commands
3198 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3199 void *buff, u16 buff_size,
3200 enum i40e_admin_queue_opc opcode,
3201 struct i40e_asq_cmd_details *cmd_details)
3203 struct i40e_aq_desc desc;
3204 struct i40e_aqc_tx_sched_ind *cmd =
3205 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3207 bool cmd_param_flag = false;
3210 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3211 case i40e_aqc_opc_configure_vsi_tc_bw:
3212 case i40e_aqc_opc_enable_switching_comp_ets:
3213 case i40e_aqc_opc_modify_switching_comp_ets:
3214 case i40e_aqc_opc_disable_switching_comp_ets:
3215 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3216 case i40e_aqc_opc_configure_switching_comp_bw_config:
3217 cmd_param_flag = true;
3219 case i40e_aqc_opc_query_vsi_bw_config:
3220 case i40e_aqc_opc_query_vsi_ets_sla_config:
3221 case i40e_aqc_opc_query_switching_comp_ets_config:
3222 case i40e_aqc_opc_query_port_ets_config:
3223 case i40e_aqc_opc_query_switching_comp_bw_config:
3224 cmd_param_flag = false;
3227 return I40E_ERR_PARAM;
3230 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3232 /* Indirect command */
3233 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3235 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3236 if (buff_size > I40E_AQ_LARGE_BUF)
3237 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3239 desc.datalen = cpu_to_le16(buff_size);
3241 cmd->vsi_seid = cpu_to_le16(seid);
3243 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3249 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3250 * @hw: pointer to the hw struct
3252 * @credit: BW limit credits (0 = disabled)
3253 * @max_credit: Max BW limit credits
3254 * @cmd_details: pointer to command details structure or NULL
3256 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3257 u16 seid, u16 credit, u8 max_credit,
3258 struct i40e_asq_cmd_details *cmd_details)
3260 struct i40e_aq_desc desc;
3261 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3262 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3265 i40e_fill_default_direct_cmd_desc(&desc,
3266 i40e_aqc_opc_configure_vsi_bw_limit);
3268 cmd->vsi_seid = cpu_to_le16(seid);
3269 cmd->credit = cpu_to_le16(credit);
3270 cmd->max_credit = max_credit;
3272 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3278 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3279 * @hw: pointer to the hw struct
3281 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3282 * @cmd_details: pointer to command details structure or NULL
3284 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3286 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3287 struct i40e_asq_cmd_details *cmd_details)
3289 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3290 i40e_aqc_opc_configure_vsi_tc_bw,
3295 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3296 * @hw: pointer to the hw struct
3297 * @seid: seid of the switching component connected to Physical Port
3298 * @ets_data: Buffer holding ETS parameters
3299 * @cmd_details: pointer to command details structure or NULL
3301 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3303 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3304 enum i40e_admin_queue_opc opcode,
3305 struct i40e_asq_cmd_details *cmd_details)
3307 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3308 sizeof(*ets_data), opcode, cmd_details);
3312 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3313 * @hw: pointer to the hw struct
3314 * @seid: seid of the switching component
3315 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3316 * @cmd_details: pointer to command details structure or NULL
3318 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3320 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3321 struct i40e_asq_cmd_details *cmd_details)
3323 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3324 i40e_aqc_opc_configure_switching_comp_bw_config,
3329 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3330 * @hw: pointer to the hw struct
3331 * @seid: seid of the VSI
3332 * @bw_data: Buffer to hold VSI BW configuration
3333 * @cmd_details: pointer to command details structure or NULL
3335 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3337 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3338 struct i40e_asq_cmd_details *cmd_details)
3340 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3341 i40e_aqc_opc_query_vsi_bw_config,
3346 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3347 * @hw: pointer to the hw struct
3348 * @seid: seid of the VSI
3349 * @bw_data: Buffer to hold VSI BW configuration per TC
3350 * @cmd_details: pointer to command details structure or NULL
3352 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3354 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3355 struct i40e_asq_cmd_details *cmd_details)
3357 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3358 i40e_aqc_opc_query_vsi_ets_sla_config,
3363 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3364 * @hw: pointer to the hw struct
3365 * @seid: seid of the switching component
3366 * @bw_data: Buffer to hold switching component's per TC BW config
3367 * @cmd_details: pointer to command details structure or NULL
3369 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3371 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3372 struct i40e_asq_cmd_details *cmd_details)
3374 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3375 i40e_aqc_opc_query_switching_comp_ets_config,
3380 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3381 * @hw: pointer to the hw struct
3382 * @seid: seid of the VSI or switching component connected to Physical Port
3383 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3384 * @cmd_details: pointer to command details structure or NULL
3386 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3388 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3389 struct i40e_asq_cmd_details *cmd_details)
3391 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3392 i40e_aqc_opc_query_port_ets_config,
3397 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3398 * @hw: pointer to the hw struct
3399 * @seid: seid of the switching component
3400 * @bw_data: Buffer to hold switching component's BW configuration
3401 * @cmd_details: pointer to command details structure or NULL
3403 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3405 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3406 struct i40e_asq_cmd_details *cmd_details)
3408 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3409 i40e_aqc_opc_query_switching_comp_bw_config,
3414 * i40e_validate_filter_settings
3415 * @hw: pointer to the hardware structure
3416 * @settings: Filter control settings
3418 * Check and validate the filter control settings passed.
3419 * The function checks for the valid filter/context sizes being
3420 * passed for FCoE and PE.
3422 * Returns 0 if the values passed are valid and within
3423 * range else returns an error.
3425 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3426 struct i40e_filter_control_settings *settings)
3428 u32 fcoe_cntx_size, fcoe_filt_size;
3429 u32 pe_cntx_size, pe_filt_size;
3433 /* Validate FCoE settings passed */
3434 switch (settings->fcoe_filt_num) {
3435 case I40E_HASH_FILTER_SIZE_1K:
3436 case I40E_HASH_FILTER_SIZE_2K:
3437 case I40E_HASH_FILTER_SIZE_4K:
3438 case I40E_HASH_FILTER_SIZE_8K:
3439 case I40E_HASH_FILTER_SIZE_16K:
3440 case I40E_HASH_FILTER_SIZE_32K:
3441 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3442 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3445 return I40E_ERR_PARAM;
3448 switch (settings->fcoe_cntx_num) {
3449 case I40E_DMA_CNTX_SIZE_512:
3450 case I40E_DMA_CNTX_SIZE_1K:
3451 case I40E_DMA_CNTX_SIZE_2K:
3452 case I40E_DMA_CNTX_SIZE_4K:
3453 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3454 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3457 return I40E_ERR_PARAM;
3460 /* Validate PE settings passed */
3461 switch (settings->pe_filt_num) {
3462 case I40E_HASH_FILTER_SIZE_1K:
3463 case I40E_HASH_FILTER_SIZE_2K:
3464 case I40E_HASH_FILTER_SIZE_4K:
3465 case I40E_HASH_FILTER_SIZE_8K:
3466 case I40E_HASH_FILTER_SIZE_16K:
3467 case I40E_HASH_FILTER_SIZE_32K:
3468 case I40E_HASH_FILTER_SIZE_64K:
3469 case I40E_HASH_FILTER_SIZE_128K:
3470 case I40E_HASH_FILTER_SIZE_256K:
3471 case I40E_HASH_FILTER_SIZE_512K:
3472 case I40E_HASH_FILTER_SIZE_1M:
3473 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3474 pe_filt_size <<= (u32)settings->pe_filt_num;
3477 return I40E_ERR_PARAM;
3480 switch (settings->pe_cntx_num) {
3481 case I40E_DMA_CNTX_SIZE_512:
3482 case I40E_DMA_CNTX_SIZE_1K:
3483 case I40E_DMA_CNTX_SIZE_2K:
3484 case I40E_DMA_CNTX_SIZE_4K:
3485 case I40E_DMA_CNTX_SIZE_8K:
3486 case I40E_DMA_CNTX_SIZE_16K:
3487 case I40E_DMA_CNTX_SIZE_32K:
3488 case I40E_DMA_CNTX_SIZE_64K:
3489 case I40E_DMA_CNTX_SIZE_128K:
3490 case I40E_DMA_CNTX_SIZE_256K:
3491 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3492 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3495 return I40E_ERR_PARAM;
3498 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3499 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3500 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3501 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3502 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3503 return I40E_ERR_INVALID_SIZE;
3509 * i40e_set_filter_control
3510 * @hw: pointer to the hardware structure
3511 * @settings: Filter control settings
3513 * Set the Queue Filters for PE/FCoE and enable filters required
3514 * for a single PF. It is expected that these settings are programmed
3515 * at the driver initialization time.
3517 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3518 struct i40e_filter_control_settings *settings)
3520 i40e_status ret = 0;
3521 u32 hash_lut_size = 0;
3525 return I40E_ERR_PARAM;
3527 /* Validate the input settings */
3528 ret = i40e_validate_filter_settings(hw, settings);
3532 /* Read the PF Queue Filter control register */
3533 val = rd32(hw, I40E_PFQF_CTL_0);
3535 /* Program required PE hash buckets for the PF */
3536 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3537 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3538 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3539 /* Program required PE contexts for the PF */
3540 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3541 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3542 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3544 /* Program required FCoE hash buckets for the PF */
3545 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3546 val |= ((u32)settings->fcoe_filt_num <<
3547 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3548 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3549 /* Program required FCoE DDP contexts for the PF */
3550 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3551 val |= ((u32)settings->fcoe_cntx_num <<
3552 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3553 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3555 /* Program Hash LUT size for the PF */
3556 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3557 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3559 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3560 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3562 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3563 if (settings->enable_fdir)
3564 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3565 if (settings->enable_ethtype)
3566 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3567 if (settings->enable_macvlan)
3568 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3570 wr32(hw, I40E_PFQF_CTL_0, val);
3576 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3577 * @hw: pointer to the hw struct
3578 * @mac_addr: MAC address to use in the filter
3579 * @ethtype: Ethertype to use in the filter
3580 * @flags: Flags that needs to be applied to the filter
3581 * @vsi_seid: seid of the control VSI
3582 * @queue: VSI queue number to send the packet to
3583 * @is_add: Add control packet filter if True else remove
3584 * @stats: Structure to hold information on control filter counts
3585 * @cmd_details: pointer to command details structure or NULL
3587 * This command will Add or Remove control packet filter for a control VSI.
3588 * In return it will update the total number of perfect filter count in
3591 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3592 u8 *mac_addr, u16 ethtype, u16 flags,
3593 u16 vsi_seid, u16 queue, bool is_add,
3594 struct i40e_control_filter_stats *stats,
3595 struct i40e_asq_cmd_details *cmd_details)
3597 struct i40e_aq_desc desc;
3598 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3599 (struct i40e_aqc_add_remove_control_packet_filter *)
3601 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3602 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3607 return I40E_ERR_PARAM;
3610 i40e_fill_default_direct_cmd_desc(&desc,
3611 i40e_aqc_opc_add_control_packet_filter);
3612 cmd->queue = cpu_to_le16(queue);
3614 i40e_fill_default_direct_cmd_desc(&desc,
3615 i40e_aqc_opc_remove_control_packet_filter);
3619 memcpy(cmd->mac, mac_addr, ETH_ALEN);
3621 cmd->etype = cpu_to_le16(ethtype);
3622 cmd->flags = cpu_to_le16(flags);
3623 cmd->seid = cpu_to_le16(vsi_seid);
3625 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3627 if (!status && stats) {
3628 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3629 stats->etype_used = le16_to_cpu(resp->etype_used);
3630 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3631 stats->etype_free = le16_to_cpu(resp->etype_free);
3638 * i40e_aq_alternate_read
3639 * @hw: pointer to the hardware structure
3640 * @reg_addr0: address of first dword to be read
3641 * @reg_val0: pointer for data read from 'reg_addr0'
3642 * @reg_addr1: address of second dword to be read
3643 * @reg_val1: pointer for data read from 'reg_addr1'
3645 * Read one or two dwords from alternate structure. Fields are indicated
3646 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
3647 * is not passed then only register at 'reg_addr0' is read.
3650 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
3651 u32 reg_addr0, u32 *reg_val0,
3652 u32 reg_addr1, u32 *reg_val1)
3654 struct i40e_aq_desc desc;
3655 struct i40e_aqc_alternate_write *cmd_resp =
3656 (struct i40e_aqc_alternate_write *)&desc.params.raw;
3660 return I40E_ERR_PARAM;
3662 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
3663 cmd_resp->address0 = cpu_to_le32(reg_addr0);
3664 cmd_resp->address1 = cpu_to_le32(reg_addr1);
3666 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3669 *reg_val0 = le32_to_cpu(cmd_resp->data0);
3672 *reg_val1 = le32_to_cpu(cmd_resp->data1);
3679 * i40e_aq_resume_port_tx
3680 * @hw: pointer to the hardware structure
3681 * @cmd_details: pointer to command details structure or NULL
3683 * Resume port's Tx traffic
3685 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
3686 struct i40e_asq_cmd_details *cmd_details)
3688 struct i40e_aq_desc desc;
3691 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
3693 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3699 * i40e_set_pci_config_data - store PCI bus info
3700 * @hw: pointer to hardware structure
3701 * @link_status: the link status word from PCI config space
3703 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3705 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
3707 hw->bus.type = i40e_bus_type_pci_express;
3709 switch (link_status & PCI_EXP_LNKSTA_NLW) {
3710 case PCI_EXP_LNKSTA_NLW_X1:
3711 hw->bus.width = i40e_bus_width_pcie_x1;
3713 case PCI_EXP_LNKSTA_NLW_X2:
3714 hw->bus.width = i40e_bus_width_pcie_x2;
3716 case PCI_EXP_LNKSTA_NLW_X4:
3717 hw->bus.width = i40e_bus_width_pcie_x4;
3719 case PCI_EXP_LNKSTA_NLW_X8:
3720 hw->bus.width = i40e_bus_width_pcie_x8;
3723 hw->bus.width = i40e_bus_width_unknown;
3727 switch (link_status & PCI_EXP_LNKSTA_CLS) {
3728 case PCI_EXP_LNKSTA_CLS_2_5GB:
3729 hw->bus.speed = i40e_bus_speed_2500;
3731 case PCI_EXP_LNKSTA_CLS_5_0GB:
3732 hw->bus.speed = i40e_bus_speed_5000;
3734 case PCI_EXP_LNKSTA_CLS_8_0GB:
3735 hw->bus.speed = i40e_bus_speed_8000;
3738 hw->bus.speed = i40e_bus_speed_unknown;
3744 * i40e_aq_debug_dump
3745 * @hw: pointer to the hardware structure
3746 * @cluster_id: specific cluster to dump
3747 * @table_id: table id within cluster
3748 * @start_index: index of line in the block to read
3749 * @buff_size: dump buffer size
3750 * @buff: dump buffer
3751 * @ret_buff_size: actual buffer size returned
3752 * @ret_next_table: next block to read
3753 * @ret_next_index: next index to read
3755 * Dump internal FW/HW data for debug purposes.
3758 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
3759 u8 table_id, u32 start_index, u16 buff_size,
3760 void *buff, u16 *ret_buff_size,
3761 u8 *ret_next_table, u32 *ret_next_index,
3762 struct i40e_asq_cmd_details *cmd_details)
3764 struct i40e_aq_desc desc;
3765 struct i40e_aqc_debug_dump_internals *cmd =
3766 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
3767 struct i40e_aqc_debug_dump_internals *resp =
3768 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
3771 if (buff_size == 0 || !buff)
3772 return I40E_ERR_PARAM;
3774 i40e_fill_default_direct_cmd_desc(&desc,
3775 i40e_aqc_opc_debug_dump_internals);
3776 /* Indirect Command */
3777 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3778 if (buff_size > I40E_AQ_LARGE_BUF)
3779 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3781 cmd->cluster_id = cluster_id;
3782 cmd->table_id = table_id;
3783 cmd->idx = cpu_to_le32(start_index);
3785 desc.datalen = cpu_to_le16(buff_size);
3787 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3790 *ret_buff_size = le16_to_cpu(desc.datalen);
3792 *ret_next_table = resp->table_id;
3794 *ret_next_index = le32_to_cpu(resp->idx);
3801 * i40e_read_bw_from_alt_ram
3802 * @hw: pointer to the hardware structure
3803 * @max_bw: pointer for max_bw read
3804 * @min_bw: pointer for min_bw read
3805 * @min_valid: pointer for bool that is true if min_bw is a valid value
3806 * @max_valid: pointer for bool that is true if max_bw is a valid value
3808 * Read bw from the alternate ram for the given pf
3810 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
3811 u32 *max_bw, u32 *min_bw,
3812 bool *min_valid, bool *max_valid)
3815 u32 max_bw_addr, min_bw_addr;
3817 /* Calculate the address of the min/max bw registers */
3818 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
3819 I40E_ALT_STRUCT_MAX_BW_OFFSET +
3820 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
3821 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
3822 I40E_ALT_STRUCT_MIN_BW_OFFSET +
3823 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
3825 /* Read the bandwidths from alt ram */
3826 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
3827 min_bw_addr, min_bw);
3829 if (*min_bw & I40E_ALT_BW_VALID_MASK)
3834 if (*max_bw & I40E_ALT_BW_VALID_MASK)
3843 * i40e_aq_configure_partition_bw
3844 * @hw: pointer to the hardware structure
3845 * @bw_data: Buffer holding valid pfs and bw limits
3846 * @cmd_details: pointer to command details
3848 * Configure partitions guaranteed/max bw
3850 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
3851 struct i40e_aqc_configure_partition_bw_data *bw_data,
3852 struct i40e_asq_cmd_details *cmd_details)
3855 struct i40e_aq_desc desc;
3856 u16 bwd_size = sizeof(*bw_data);
3858 i40e_fill_default_direct_cmd_desc(&desc,
3859 i40e_aqc_opc_configure_partition_bw);
3861 /* Indirect command */
3862 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3863 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3865 if (bwd_size > I40E_AQ_LARGE_BUF)
3866 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3868 desc.datalen = cpu_to_le16(bwd_size);
3870 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,