1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include <linux/prefetch.h>
29 #include "i40e_prototype.h"
31 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
34 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
35 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
36 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
37 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
38 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
41 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
43 * i40e_program_fdir_filter - Program a Flow Director filter
44 * @fdir_data: Packet data that will be filter parameters
45 * @raw_packet: the pre-allocated packet buffer for FDir
47 * @add: True for add/update, False for remove
49 int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
50 struct i40e_pf *pf, bool add)
52 struct i40e_filter_program_desc *fdir_desc;
53 struct i40e_tx_buffer *tx_buf;
54 struct i40e_tx_desc *tx_desc;
55 struct i40e_ring *tx_ring;
56 unsigned int fpt, dcc;
63 /* find existing FDIR VSI */
65 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
66 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
71 tx_ring = vsi->tx_rings[0];
74 dma = dma_map_single(dev, raw_packet,
75 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
76 if (dma_mapping_error(dev, dma))
79 /* grab the next descriptor */
80 i = tx_ring->next_to_use;
81 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
83 tx_ring->next_to_use = (i + 1 < tx_ring->count) ? i + 1 : 0;
85 fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
86 I40E_TXD_FLTR_QW0_QINDEX_MASK;
88 fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
89 I40E_TXD_FLTR_QW0_FLEXOFF_MASK;
91 fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
92 I40E_TXD_FLTR_QW0_PCTYPE_MASK;
94 /* Use LAN VSI Id if not programmed by user */
95 if (fdir_data->dest_vsi == 0)
96 fpt |= (pf->vsi[pf->lan_vsi]->id) <<
97 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
99 fpt |= ((u32)fdir_data->dest_vsi <<
100 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
101 I40E_TXD_FLTR_QW0_DEST_VSI_MASK;
103 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt);
105 dcc = I40E_TX_DESC_DTYPE_FILTER_PROG;
108 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
109 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
111 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
112 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
114 dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) &
115 I40E_TXD_FLTR_QW1_DEST_MASK;
117 dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
118 I40E_TXD_FLTR_QW1_FD_STATUS_MASK;
120 if (fdir_data->cnt_index != 0) {
121 dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
122 dcc |= ((u32)fdir_data->cnt_index <<
123 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
124 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
127 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc);
128 fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id);
130 /* Now program a dummy descriptor */
131 i = tx_ring->next_to_use;
132 tx_desc = I40E_TX_DESC(tx_ring, i);
133 tx_buf = &tx_ring->tx_bi[i];
135 tx_ring->next_to_use = (i + 1 < tx_ring->count) ? i + 1 : 0;
137 /* record length, and DMA address */
138 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
139 dma_unmap_addr_set(tx_buf, dma, dma);
141 tx_desc->buffer_addr = cpu_to_le64(dma);
142 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
144 tx_desc->cmd_type_offset_bsz =
145 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
147 /* set the timestamp */
148 tx_buf->time_stamp = jiffies;
150 /* Force memory writes to complete before letting h/w
151 * know there are new descriptors to fetch. (Only
152 * applicable for weak-ordered memory model archs,
157 /* Mark the data descriptor to be watched */
158 tx_buf->next_to_watch = tx_desc;
160 writel(tx_ring->next_to_use, tx_ring->tail);
167 #define IP_HEADER_OFFSET 14
168 #define I40E_UDPIP_DUMMY_PACKET_LEN 42
170 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
171 * @vsi: pointer to the targeted VSI
172 * @fd_data: the flow director data required for the FDir descriptor
173 * @raw_packet: the pre-allocated packet buffer for FDir
174 * @add: true adds a filter, false removes it
176 * Returns 0 if the filters were successfully added or removed
178 static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
179 struct i40e_fdir_filter *fd_data,
180 u8 *raw_packet, bool add)
182 struct i40e_pf *pf = vsi->back;
187 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
188 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
189 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
191 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
193 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
194 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
195 + sizeof(struct iphdr));
197 ip->daddr = fd_data->dst_ip[0];
198 udp->dest = fd_data->dst_port;
199 ip->saddr = fd_data->src_ip[0];
200 udp->source = fd_data->src_port;
202 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
203 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
205 dev_info(&pf->pdev->dev,
206 "Filter command send failed for PCTYPE %d (ret = %d)\n",
207 fd_data->pctype, ret);
210 dev_info(&pf->pdev->dev,
211 "Filter OK for PCTYPE %d (ret = %d)\n",
212 fd_data->pctype, ret);
215 return err ? -EOPNOTSUPP : 0;
218 #define I40E_TCPIP_DUMMY_PACKET_LEN 54
220 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
221 * @vsi: pointer to the targeted VSI
222 * @fd_data: the flow director data required for the FDir descriptor
223 * @raw_packet: the pre-allocated packet buffer for FDir
224 * @add: true adds a filter, false removes it
226 * Returns 0 if the filters were successfully added or removed
228 static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
229 struct i40e_fdir_filter *fd_data,
230 u8 *raw_packet, bool add)
232 struct i40e_pf *pf = vsi->back;
238 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
239 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
240 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
241 0x0, 0x72, 0, 0, 0, 0};
243 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
245 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
246 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
247 + sizeof(struct iphdr));
249 ip->daddr = fd_data->dst_ip[0];
250 tcp->dest = fd_data->dst_port;
251 ip->saddr = fd_data->src_ip[0];
252 tcp->source = fd_data->src_port;
255 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) {
256 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
257 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
261 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
262 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
265 dev_info(&pf->pdev->dev,
266 "Filter command send failed for PCTYPE %d (ret = %d)\n",
267 fd_data->pctype, ret);
270 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d (ret = %d)\n",
271 fd_data->pctype, ret);
274 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
276 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
278 dev_info(&pf->pdev->dev,
279 "Filter command send failed for PCTYPE %d (ret = %d)\n",
280 fd_data->pctype, ret);
283 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d (ret = %d)\n",
284 fd_data->pctype, ret);
287 return err ? -EOPNOTSUPP : 0;
291 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
292 * a specific flow spec
293 * @vsi: pointer to the targeted VSI
294 * @fd_data: the flow director data required for the FDir descriptor
295 * @raw_packet: the pre-allocated packet buffer for FDir
296 * @add: true adds a filter, false removes it
298 * Always returns -EOPNOTSUPP
300 static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
301 struct i40e_fdir_filter *fd_data,
302 u8 *raw_packet, bool add)
307 #define I40E_IP_DUMMY_PACKET_LEN 34
309 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
310 * a specific flow spec
311 * @vsi: pointer to the targeted VSI
312 * @fd_data: the flow director data required for the FDir descriptor
313 * @raw_packet: the pre-allocated packet buffer for FDir
314 * @add: true adds a filter, false removes it
316 * Returns 0 if the filters were successfully added or removed
318 static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
319 struct i40e_fdir_filter *fd_data,
320 u8 *raw_packet, bool add)
322 struct i40e_pf *pf = vsi->back;
327 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
328 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
331 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
332 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
334 ip->saddr = fd_data->src_ip[0];
335 ip->daddr = fd_data->dst_ip[0];
338 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
339 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) {
341 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
344 dev_info(&pf->pdev->dev,
345 "Filter command send failed for PCTYPE %d (ret = %d)\n",
346 fd_data->pctype, ret);
349 dev_info(&pf->pdev->dev,
350 "Filter OK for PCTYPE %d (ret = %d)\n",
351 fd_data->pctype, ret);
355 return err ? -EOPNOTSUPP : 0;
359 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
360 * @vsi: pointer to the targeted VSI
361 * @cmd: command to get or set RX flow classification rules
362 * @add: true adds a filter, false removes it
365 int i40e_add_del_fdir(struct i40e_vsi *vsi,
366 struct i40e_fdir_filter *input, bool add)
368 struct i40e_pf *pf = vsi->back;
372 /* Populate the Flow Director that we have at the moment
373 * and allocate the raw packet buffer for the calling functions
375 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
379 switch (input->flow_type & ~FLOW_EXT) {
381 ret = i40e_add_del_fdir_tcpv4(vsi, input, raw_packet,
385 ret = i40e_add_del_fdir_udpv4(vsi, input, raw_packet,
389 ret = i40e_add_del_fdir_sctpv4(vsi, input, raw_packet,
393 ret = i40e_add_del_fdir_ipv4(vsi, input, raw_packet,
397 switch (input->ip4_proto) {
399 ret = i40e_add_del_fdir_tcpv4(vsi, input,
403 ret = i40e_add_del_fdir_udpv4(vsi, input,
407 ret = i40e_add_del_fdir_sctpv4(vsi, input,
411 ret = i40e_add_del_fdir_ipv4(vsi, input,
417 dev_info(&pf->pdev->dev, "Could not specify spec type %d\n",
427 * i40e_fd_handle_status - check the Programming Status for FD
428 * @rx_ring: the Rx ring for this descriptor
429 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor.
430 * @prog_id: the id originally used for programming
432 * This is used to verify if the FD programming or invalidation
433 * requested by SW to the HW is successful or not and take actions accordingly.
435 static void i40e_fd_handle_status(struct i40e_ring *rx_ring,
436 union i40e_rx_desc *rx_desc, u8 prog_id)
438 struct i40e_pf *pf = rx_ring->vsi->back;
439 struct pci_dev *pdev = pf->pdev;
440 u32 fcnt_prog, fcnt_avail;
444 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
445 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
446 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
448 if (error == (0x1 << I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
449 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
450 rx_desc->wb.qword0.hi_dword.fd_id);
452 /* filter programming failed most likely due to table full */
453 fcnt_prog = i40e_get_current_fd_count(pf);
454 fcnt_avail = pf->hw.fdir_shared_filter_count +
455 pf->fdir_pf_filter_count;
457 /* If ATR is running fcnt_prog can quickly change,
458 * if we are very close to full, it makes sense to disable
459 * FD ATR/SB and then re-enable it when there is room.
461 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
462 /* Turn off ATR first */
463 if (pf->flags | I40E_FLAG_FD_ATR_ENABLED) {
464 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
465 dev_warn(&pdev->dev, "FD filter space full, ATR for further flows will be turned off\n");
466 pf->auto_disable_flags |=
467 I40E_FLAG_FD_ATR_ENABLED;
468 pf->flags |= I40E_FLAG_FDIR_REQUIRES_REINIT;
469 } else if (pf->flags | I40E_FLAG_FD_SB_ENABLED) {
470 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
471 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
472 pf->auto_disable_flags |=
473 I40E_FLAG_FD_SB_ENABLED;
474 pf->flags |= I40E_FLAG_FDIR_REQUIRES_REINIT;
477 dev_info(&pdev->dev, "FD filter programming error\n");
480 (0x1 << I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
481 if (I40E_DEBUG_FD & pf->hw.debug_mask)
482 dev_info(&pdev->dev, "ntuple filter loc = %d, could not be removed\n",
483 rx_desc->wb.qword0.hi_dword.fd_id);
488 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
489 * @ring: the ring that owns the buffer
490 * @tx_buffer: the buffer to free
492 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
493 struct i40e_tx_buffer *tx_buffer)
495 if (tx_buffer->skb) {
496 dev_kfree_skb_any(tx_buffer->skb);
497 if (dma_unmap_len(tx_buffer, len))
498 dma_unmap_single(ring->dev,
499 dma_unmap_addr(tx_buffer, dma),
500 dma_unmap_len(tx_buffer, len),
502 } else if (dma_unmap_len(tx_buffer, len)) {
503 dma_unmap_page(ring->dev,
504 dma_unmap_addr(tx_buffer, dma),
505 dma_unmap_len(tx_buffer, len),
508 tx_buffer->next_to_watch = NULL;
509 tx_buffer->skb = NULL;
510 dma_unmap_len_set(tx_buffer, len, 0);
511 /* tx_buffer must be completely set up in the transmit path */
515 * i40e_clean_tx_ring - Free any empty Tx buffers
516 * @tx_ring: ring to be cleaned
518 void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
520 unsigned long bi_size;
523 /* ring already cleared, nothing to do */
527 /* Free all the Tx ring sk_buffs */
528 for (i = 0; i < tx_ring->count; i++)
529 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
531 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
532 memset(tx_ring->tx_bi, 0, bi_size);
534 /* Zero out the descriptor ring */
535 memset(tx_ring->desc, 0, tx_ring->size);
537 tx_ring->next_to_use = 0;
538 tx_ring->next_to_clean = 0;
540 if (!tx_ring->netdev)
543 /* cleanup Tx queue statistics */
544 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
545 tx_ring->queue_index));
549 * i40e_free_tx_resources - Free Tx resources per queue
550 * @tx_ring: Tx descriptor ring for a specific queue
552 * Free all transmit software resources
554 void i40e_free_tx_resources(struct i40e_ring *tx_ring)
556 i40e_clean_tx_ring(tx_ring);
557 kfree(tx_ring->tx_bi);
558 tx_ring->tx_bi = NULL;
561 dma_free_coherent(tx_ring->dev, tx_ring->size,
562 tx_ring->desc, tx_ring->dma);
563 tx_ring->desc = NULL;
568 * i40e_get_tx_pending - how many tx descriptors not processed
569 * @tx_ring: the ring of descriptors
571 * Since there is no access to the ring head register
572 * in XL710, we need to use our local copies
574 static u32 i40e_get_tx_pending(struct i40e_ring *ring)
576 u32 ntu = ((ring->next_to_clean <= ring->next_to_use)
578 : ring->next_to_use + ring->count);
579 return ntu - ring->next_to_clean;
583 * i40e_check_tx_hang - Is there a hang in the Tx queue
584 * @tx_ring: the ring of descriptors
586 static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
588 u32 tx_pending = i40e_get_tx_pending(tx_ring);
591 clear_check_for_tx_hang(tx_ring);
593 /* Check for a hung queue, but be thorough. This verifies
594 * that a transmit has been completed since the previous
595 * check AND there is at least one packet pending. The
596 * ARMED bit is set to indicate a potential hang. The
597 * bit is cleared if a pause frame is received to remove
598 * false hang detection due to PFC or 802.3x frames. By
599 * requiring this to fail twice we avoid races with
600 * PFC clearing the ARMED bit and conditions where we
601 * run the check_tx_hang logic with a transmit completion
602 * pending but without time to complete it yet.
604 if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) &&
606 /* make sure it is true for two checks in a row */
607 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
610 /* update completed stats and disarm the hang check */
611 tx_ring->tx_stats.tx_done_old = tx_ring->stats.packets;
612 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
619 * i40e_get_head - Retrieve head from head writeback
620 * @tx_ring: tx ring to fetch head of
622 * Returns value of Tx ring head based on value stored
623 * in head write-back location
625 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
627 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
629 return le32_to_cpu(*(volatile __le32 *)head);
633 * i40e_clean_tx_irq - Reclaim resources after transmit completes
634 * @tx_ring: tx ring to clean
635 * @budget: how many cleans we're allowed
637 * Returns true if there's any budget left (e.g. the clean is finished)
639 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
641 u16 i = tx_ring->next_to_clean;
642 struct i40e_tx_buffer *tx_buf;
643 struct i40e_tx_desc *tx_head;
644 struct i40e_tx_desc *tx_desc;
645 unsigned int total_packets = 0;
646 unsigned int total_bytes = 0;
648 tx_buf = &tx_ring->tx_bi[i];
649 tx_desc = I40E_TX_DESC(tx_ring, i);
652 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
655 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
657 /* if next_to_watch is not set then there is no work pending */
661 /* prevent any other reads prior to eop_desc */
662 read_barrier_depends();
664 /* we have caught up to head, no work left to do */
665 if (tx_head == tx_desc)
668 /* clear next_to_watch to prevent false hangs */
669 tx_buf->next_to_watch = NULL;
671 /* update the statistics for this packet */
672 total_bytes += tx_buf->bytecount;
673 total_packets += tx_buf->gso_segs;
676 dev_kfree_skb_any(tx_buf->skb);
678 /* unmap skb header data */
679 dma_unmap_single(tx_ring->dev,
680 dma_unmap_addr(tx_buf, dma),
681 dma_unmap_len(tx_buf, len),
684 /* clear tx_buffer data */
686 dma_unmap_len_set(tx_buf, len, 0);
688 /* unmap remaining buffers */
689 while (tx_desc != eop_desc) {
696 tx_buf = tx_ring->tx_bi;
697 tx_desc = I40E_TX_DESC(tx_ring, 0);
700 /* unmap any remaining paged data */
701 if (dma_unmap_len(tx_buf, len)) {
702 dma_unmap_page(tx_ring->dev,
703 dma_unmap_addr(tx_buf, dma),
704 dma_unmap_len(tx_buf, len),
706 dma_unmap_len_set(tx_buf, len, 0);
710 /* move us one more past the eop_desc for start of next pkt */
716 tx_buf = tx_ring->tx_bi;
717 tx_desc = I40E_TX_DESC(tx_ring, 0);
720 /* update budget accounting */
722 } while (likely(budget));
725 tx_ring->next_to_clean = i;
726 u64_stats_update_begin(&tx_ring->syncp);
727 tx_ring->stats.bytes += total_bytes;
728 tx_ring->stats.packets += total_packets;
729 u64_stats_update_end(&tx_ring->syncp);
730 tx_ring->q_vector->tx.total_bytes += total_bytes;
731 tx_ring->q_vector->tx.total_packets += total_packets;
733 if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
734 /* schedule immediate reset if we believe we hung */
735 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
738 " next_to_use <%x>\n"
739 " next_to_clean <%x>\n",
741 tx_ring->queue_index,
742 tx_ring->next_to_use, i);
743 dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n"
744 " time_stamp <%lx>\n"
746 tx_ring->tx_bi[i].time_stamp, jiffies);
748 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
750 dev_info(tx_ring->dev,
751 "tx hang detected on queue %d, resetting adapter\n",
752 tx_ring->queue_index);
754 tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev);
756 /* the adapter is about to reset, no point in enabling stuff */
760 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
761 tx_ring->queue_index),
762 total_packets, total_bytes);
764 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
765 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
766 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
767 /* Make sure that anybody stopping the queue after this
768 * sees the new next_to_clean.
771 if (__netif_subqueue_stopped(tx_ring->netdev,
772 tx_ring->queue_index) &&
773 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
774 netif_wake_subqueue(tx_ring->netdev,
775 tx_ring->queue_index);
776 ++tx_ring->tx_stats.restart_queue;
784 * i40e_set_new_dynamic_itr - Find new ITR level
785 * @rc: structure containing ring performance data
787 * Stores a new ITR value based on packets and byte counts during
788 * the last interrupt. The advantage of per interrupt computation
789 * is faster updates and more accurate ITR for the current traffic
790 * pattern. Constants in this function were computed based on
791 * theoretical maximum wire speed and thresholds were set based on
792 * testing data as well as attempting to minimize response time
793 * while increasing bulk throughput.
795 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
797 enum i40e_latency_range new_latency_range = rc->latency_range;
798 u32 new_itr = rc->itr;
801 if (rc->total_packets == 0 || !rc->itr)
804 /* simple throttlerate management
805 * 0-10MB/s lowest (100000 ints/s)
806 * 10-20MB/s low (20000 ints/s)
807 * 20-1249MB/s bulk (8000 ints/s)
809 bytes_per_int = rc->total_bytes / rc->itr;
811 case I40E_LOWEST_LATENCY:
812 if (bytes_per_int > 10)
813 new_latency_range = I40E_LOW_LATENCY;
815 case I40E_LOW_LATENCY:
816 if (bytes_per_int > 20)
817 new_latency_range = I40E_BULK_LATENCY;
818 else if (bytes_per_int <= 10)
819 new_latency_range = I40E_LOWEST_LATENCY;
821 case I40E_BULK_LATENCY:
822 if (bytes_per_int <= 20)
823 rc->latency_range = I40E_LOW_LATENCY;
827 switch (new_latency_range) {
828 case I40E_LOWEST_LATENCY:
829 new_itr = I40E_ITR_100K;
831 case I40E_LOW_LATENCY:
832 new_itr = I40E_ITR_20K;
834 case I40E_BULK_LATENCY:
835 new_itr = I40E_ITR_8K;
841 if (new_itr != rc->itr) {
842 /* do an exponential smoothing */
843 new_itr = (10 * new_itr * rc->itr) /
844 ((9 * new_itr) + rc->itr);
845 rc->itr = new_itr & I40E_MAX_ITR;
849 rc->total_packets = 0;
853 * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
854 * @q_vector: the vector to adjust
856 static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)
858 u16 vector = q_vector->vsi->base_vector + q_vector->v_idx;
859 struct i40e_hw *hw = &q_vector->vsi->back->hw;
863 reg_addr = I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1);
864 old_itr = q_vector->rx.itr;
865 i40e_set_new_dynamic_itr(&q_vector->rx);
866 if (old_itr != q_vector->rx.itr)
867 wr32(hw, reg_addr, q_vector->rx.itr);
869 reg_addr = I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1);
870 old_itr = q_vector->tx.itr;
871 i40e_set_new_dynamic_itr(&q_vector->tx);
872 if (old_itr != q_vector->tx.itr)
873 wr32(hw, reg_addr, q_vector->tx.itr);
877 * i40e_clean_programming_status - clean the programming status descriptor
878 * @rx_ring: the rx ring that has this descriptor
879 * @rx_desc: the rx descriptor written back by HW
881 * Flow director should handle FD_FILTER_STATUS to check its filter programming
882 * status being successful or not and take actions accordingly. FCoE should
883 * handle its context/filter programming/invalidation status and take actions.
886 static void i40e_clean_programming_status(struct i40e_ring *rx_ring,
887 union i40e_rx_desc *rx_desc)
892 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
893 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
894 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
896 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
897 i40e_fd_handle_status(rx_ring, rx_desc, id);
901 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
902 * @tx_ring: the tx ring to set up
904 * Return 0 on success, negative on error
906 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
908 struct device *dev = tx_ring->dev;
914 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
915 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
919 /* round up to nearest 4K */
920 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
921 /* add u32 for head writeback, align after this takes care of
922 * guaranteeing this is at least one cache line in size
924 tx_ring->size += sizeof(u32);
925 tx_ring->size = ALIGN(tx_ring->size, 4096);
926 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
927 &tx_ring->dma, GFP_KERNEL);
928 if (!tx_ring->desc) {
929 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
934 tx_ring->next_to_use = 0;
935 tx_ring->next_to_clean = 0;
939 kfree(tx_ring->tx_bi);
940 tx_ring->tx_bi = NULL;
945 * i40e_clean_rx_ring - Free Rx buffers
946 * @rx_ring: ring to be cleaned
948 void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
950 struct device *dev = rx_ring->dev;
951 struct i40e_rx_buffer *rx_bi;
952 unsigned long bi_size;
955 /* ring already cleared, nothing to do */
959 /* Free all the Rx ring sk_buffs */
960 for (i = 0; i < rx_ring->count; i++) {
961 rx_bi = &rx_ring->rx_bi[i];
963 dma_unmap_single(dev,
970 dev_kfree_skb(rx_bi->skb);
974 if (rx_bi->page_dma) {
981 __free_page(rx_bi->page);
983 rx_bi->page_offset = 0;
987 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
988 memset(rx_ring->rx_bi, 0, bi_size);
990 /* Zero out the descriptor ring */
991 memset(rx_ring->desc, 0, rx_ring->size);
993 rx_ring->next_to_clean = 0;
994 rx_ring->next_to_use = 0;
998 * i40e_free_rx_resources - Free Rx resources
999 * @rx_ring: ring to clean the resources from
1001 * Free all receive software resources
1003 void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1005 i40e_clean_rx_ring(rx_ring);
1006 kfree(rx_ring->rx_bi);
1007 rx_ring->rx_bi = NULL;
1009 if (rx_ring->desc) {
1010 dma_free_coherent(rx_ring->dev, rx_ring->size,
1011 rx_ring->desc, rx_ring->dma);
1012 rx_ring->desc = NULL;
1017 * i40e_setup_rx_descriptors - Allocate Rx descriptors
1018 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1020 * Returns 0 on success, negative on failure
1022 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1024 struct device *dev = rx_ring->dev;
1027 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1028 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
1029 if (!rx_ring->rx_bi)
1032 /* Round up to nearest 4K */
1033 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
1034 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
1035 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1036 rx_ring->size = ALIGN(rx_ring->size, 4096);
1037 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1038 &rx_ring->dma, GFP_KERNEL);
1040 if (!rx_ring->desc) {
1041 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1046 rx_ring->next_to_clean = 0;
1047 rx_ring->next_to_use = 0;
1051 kfree(rx_ring->rx_bi);
1052 rx_ring->rx_bi = NULL;
1057 * i40e_release_rx_desc - Store the new tail and head values
1058 * @rx_ring: ring to bump
1059 * @val: new head index
1061 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1063 rx_ring->next_to_use = val;
1064 /* Force memory writes to complete before letting h/w
1065 * know there are new descriptors to fetch. (Only
1066 * applicable for weak-ordered memory model archs,
1070 writel(val, rx_ring->tail);
1074 * i40e_alloc_rx_buffers - Replace used receive buffers; packet split
1075 * @rx_ring: ring to place buffers on
1076 * @cleaned_count: number of buffers to replace
1078 void i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
1080 u16 i = rx_ring->next_to_use;
1081 union i40e_rx_desc *rx_desc;
1082 struct i40e_rx_buffer *bi;
1083 struct sk_buff *skb;
1085 /* do nothing if no valid netdev defined */
1086 if (!rx_ring->netdev || !cleaned_count)
1089 while (cleaned_count--) {
1090 rx_desc = I40E_RX_DESC(rx_ring, i);
1091 bi = &rx_ring->rx_bi[i];
1095 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1096 rx_ring->rx_buf_len);
1098 rx_ring->rx_stats.alloc_buff_failed++;
1101 /* initialize queue mapping */
1102 skb_record_rx_queue(skb, rx_ring->queue_index);
1107 bi->dma = dma_map_single(rx_ring->dev,
1109 rx_ring->rx_buf_len,
1111 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1112 rx_ring->rx_stats.alloc_buff_failed++;
1118 if (ring_is_ps_enabled(rx_ring)) {
1120 bi->page = alloc_page(GFP_ATOMIC);
1122 rx_ring->rx_stats.alloc_page_failed++;
1127 if (!bi->page_dma) {
1128 /* use a half page if we're re-using */
1129 bi->page_offset ^= PAGE_SIZE / 2;
1130 bi->page_dma = dma_map_page(rx_ring->dev,
1135 if (dma_mapping_error(rx_ring->dev,
1137 rx_ring->rx_stats.alloc_page_failed++;
1143 /* Refresh the desc even if buffer_addrs didn't change
1144 * because each write-back erases this info.
1146 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1147 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1149 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1150 rx_desc->read.hdr_addr = 0;
1153 if (i == rx_ring->count)
1158 if (rx_ring->next_to_use != i)
1159 i40e_release_rx_desc(rx_ring, i);
1163 * i40e_receive_skb - Send a completed packet up the stack
1164 * @rx_ring: rx ring in play
1165 * @skb: packet to send up
1166 * @vlan_tag: vlan tag for packet
1168 static void i40e_receive_skb(struct i40e_ring *rx_ring,
1169 struct sk_buff *skb, u16 vlan_tag)
1171 struct i40e_q_vector *q_vector = rx_ring->q_vector;
1172 struct i40e_vsi *vsi = rx_ring->vsi;
1173 u64 flags = vsi->back->flags;
1175 if (vlan_tag & VLAN_VID_MASK)
1176 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
1178 if (flags & I40E_FLAG_IN_NETPOLL)
1181 napi_gro_receive(&q_vector->napi, skb);
1185 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1186 * @vsi: the VSI we care about
1187 * @skb: skb currently being received and modified
1188 * @rx_status: status value of last descriptor in packet
1189 * @rx_error: error value of last descriptor in packet
1190 * @rx_ptype: ptype value of last descriptor in packet
1192 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1193 struct sk_buff *skb,
1198 bool ipv4_tunnel, ipv6_tunnel;
1203 ipv4_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
1204 (rx_ptype < I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
1205 ipv6_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
1206 (rx_ptype < I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
1208 skb->encapsulation = ipv4_tunnel || ipv6_tunnel;
1209 skb->ip_summed = CHECKSUM_NONE;
1211 /* Rx csum enabled and ip headers found? */
1212 if (!(vsi->netdev->features & NETIF_F_RXCSUM &&
1213 rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1216 /* likely incorrect csum if alternate IP extension headers found */
1217 if (rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1220 /* IP or L4 or outmost IP checksum error */
1221 if (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
1222 (1 << I40E_RX_DESC_ERROR_L4E_SHIFT) |
1223 (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))) {
1224 vsi->back->hw_csum_rx_error++;
1229 !(rx_status & (1 << I40E_RX_DESC_STATUS_UDP_0_SHIFT))) {
1230 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
1231 * it in the driver, hardware does not do it for us.
1232 * Since L3L4P bit was set we assume a valid IHL value (>=5)
1233 * so the total length of IPv4 header is IHL*4 bytes
1235 skb->transport_header = skb->mac_header +
1236 sizeof(struct ethhdr) +
1237 (ip_hdr(skb)->ihl * 4);
1239 /* Add 4 bytes for VLAN tagged packets */
1240 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
1241 skb->protocol == htons(ETH_P_8021AD))
1244 rx_udp_csum = udp_csum(skb);
1246 csum = csum_tcpudp_magic(
1247 iph->saddr, iph->daddr,
1248 (skb->len - skb_transport_offset(skb)),
1249 IPPROTO_UDP, rx_udp_csum);
1251 if (udp_hdr(skb)->check != csum) {
1252 vsi->back->hw_csum_rx_error++;
1257 skb->ip_summed = CHECKSUM_UNNECESSARY;
1261 * i40e_rx_hash - returns the hash value from the Rx descriptor
1262 * @ring: descriptor ring
1263 * @rx_desc: specific descriptor
1265 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
1266 union i40e_rx_desc *rx_desc)
1268 const __le64 rss_mask =
1269 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1270 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1272 if ((ring->netdev->features & NETIF_F_RXHASH) &&
1273 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
1274 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1280 * i40e_ptype_to_hash - get a hash type
1281 * @ptype: the ptype value from the descriptor
1283 * Returns a hash type to be used by skb_set_hash
1285 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
1287 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1290 return PKT_HASH_TYPE_NONE;
1292 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1293 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1294 return PKT_HASH_TYPE_L4;
1295 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1296 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1297 return PKT_HASH_TYPE_L3;
1299 return PKT_HASH_TYPE_L2;
1303 * i40e_clean_rx_irq - Reclaim resources after receive completes
1304 * @rx_ring: rx ring to clean
1305 * @budget: how many cleans we're allowed
1307 * Returns true if there's any budget left (e.g. the clean is finished)
1309 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
1311 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1312 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
1313 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1314 const int current_node = numa_node_id();
1315 struct i40e_vsi *vsi = rx_ring->vsi;
1316 u16 i = rx_ring->next_to_clean;
1317 union i40e_rx_desc *rx_desc;
1318 u32 rx_error, rx_status;
1325 rx_desc = I40E_RX_DESC(rx_ring, i);
1326 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1327 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1328 I40E_RXD_QW1_STATUS_SHIFT;
1330 while (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1331 union i40e_rx_desc *next_rxd;
1332 struct i40e_rx_buffer *rx_bi;
1333 struct sk_buff *skb;
1335 if (i40e_rx_is_programming_status(qword)) {
1336 i40e_clean_programming_status(rx_ring, rx_desc);
1337 I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd);
1340 rx_bi = &rx_ring->rx_bi[i];
1342 prefetch(skb->data);
1344 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1345 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1346 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1347 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1348 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1349 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1351 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1352 I40E_RXD_QW1_ERROR_SHIFT;
1353 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1354 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1356 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1357 I40E_RXD_QW1_PTYPE_SHIFT;
1360 /* This memory barrier is needed to keep us from reading
1361 * any other fields out of the rx_desc until we know the
1362 * STATUS_DD bit is set
1366 /* Get the header and possibly the whole packet
1367 * If this is an skb from previous receive dma will be 0
1373 len = I40E_RX_HDR_SIZE;
1375 len = rx_header_len;
1376 else if (rx_packet_len)
1377 len = rx_packet_len; /* 1buf/no split found */
1379 len = rx_header_len; /* split always mode */
1382 dma_unmap_single(rx_ring->dev,
1384 rx_ring->rx_buf_len,
1389 /* Get the rest of the data if this was a header split */
1390 if (ring_is_ps_enabled(rx_ring) && rx_packet_len) {
1392 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1397 skb->len += rx_packet_len;
1398 skb->data_len += rx_packet_len;
1399 skb->truesize += rx_packet_len;
1401 if ((page_count(rx_bi->page) == 1) &&
1402 (page_to_nid(rx_bi->page) == current_node))
1403 get_page(rx_bi->page);
1407 dma_unmap_page(rx_ring->dev,
1411 rx_bi->page_dma = 0;
1413 I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd);
1416 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1417 struct i40e_rx_buffer *next_buffer;
1419 next_buffer = &rx_ring->rx_bi[i];
1421 if (ring_is_ps_enabled(rx_ring)) {
1422 rx_bi->skb = next_buffer->skb;
1423 rx_bi->dma = next_buffer->dma;
1424 next_buffer->skb = skb;
1425 next_buffer->dma = 0;
1427 rx_ring->rx_stats.non_eop_descs++;
1431 /* ERR_MASK will only have valid bits if EOP set */
1432 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1433 dev_kfree_skb_any(skb);
1437 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1438 i40e_ptype_to_hash(rx_ptype));
1439 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1440 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1441 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1442 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1443 rx_ring->last_rx_timestamp = jiffies;
1446 /* probably a little skewed due to removing CRC */
1447 total_rx_bytes += skb->len;
1450 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1452 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1454 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1455 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1457 i40e_receive_skb(rx_ring, skb, vlan_tag);
1459 rx_ring->netdev->last_rx = jiffies;
1462 rx_desc->wb.qword1.status_error_len = 0;
1467 /* return some buffers to hardware, one at a time is too slow */
1468 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1469 i40e_alloc_rx_buffers(rx_ring, cleaned_count);
1473 /* use prefetched values */
1475 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1476 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1477 I40E_RXD_QW1_STATUS_SHIFT;
1480 rx_ring->next_to_clean = i;
1481 u64_stats_update_begin(&rx_ring->syncp);
1482 rx_ring->stats.packets += total_rx_packets;
1483 rx_ring->stats.bytes += total_rx_bytes;
1484 u64_stats_update_end(&rx_ring->syncp);
1485 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1486 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1489 i40e_alloc_rx_buffers(rx_ring, cleaned_count);
1495 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
1496 * @napi: napi struct with our devices info in it
1497 * @budget: amount of work driver is allowed to do this pass, in packets
1499 * This function will clean all queues associated with a q_vector.
1501 * Returns the amount of work done
1503 int i40e_napi_poll(struct napi_struct *napi, int budget)
1505 struct i40e_q_vector *q_vector =
1506 container_of(napi, struct i40e_q_vector, napi);
1507 struct i40e_vsi *vsi = q_vector->vsi;
1508 struct i40e_ring *ring;
1509 bool clean_complete = true;
1510 int budget_per_ring;
1512 if (test_bit(__I40E_DOWN, &vsi->state)) {
1513 napi_complete(napi);
1517 /* Since the actual Tx work is minimal, we can give the Tx a larger
1518 * budget and be more aggressive about cleaning up the Tx descriptors.
1520 i40e_for_each_ring(ring, q_vector->tx)
1521 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1523 /* We attempt to distribute budget to each Rx queue fairly, but don't
1524 * allow the budget to go below 1 because that would exit polling early.
1526 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1528 i40e_for_each_ring(ring, q_vector->rx)
1529 clean_complete &= i40e_clean_rx_irq(ring, budget_per_ring);
1531 /* If work not completed, return budget and polling will return */
1532 if (!clean_complete)
1535 /* Work is done so exit the polling mode and re-enable the interrupt */
1536 napi_complete(napi);
1537 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||
1538 ITR_IS_DYNAMIC(vsi->tx_itr_setting))
1539 i40e_update_dynamic_itr(q_vector);
1541 if (!test_bit(__I40E_DOWN, &vsi->state)) {
1542 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
1543 i40e_irq_dynamic_enable(vsi,
1544 q_vector->v_idx + vsi->base_vector);
1546 struct i40e_hw *hw = &vsi->back->hw;
1547 /* We re-enable the queue 0 cause, but
1548 * don't worry about dynamic_enable
1549 * because we left it on for the other
1550 * possible interrupts during napi
1552 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
1553 qval |= I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1554 wr32(hw, I40E_QINT_RQCTL(0), qval);
1556 qval = rd32(hw, I40E_QINT_TQCTL(0));
1557 qval |= I40E_QINT_TQCTL_CAUSE_ENA_MASK;
1558 wr32(hw, I40E_QINT_TQCTL(0), qval);
1560 i40e_irq_dynamic_enable_icr0(vsi->back);
1568 * i40e_atr - Add a Flow Director ATR filter
1569 * @tx_ring: ring to add programming descriptor to
1571 * @flags: send flags
1572 * @protocol: wire protocol
1574 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
1575 u32 flags, __be16 protocol)
1577 struct i40e_filter_program_desc *fdir_desc;
1578 struct i40e_pf *pf = tx_ring->vsi->back;
1580 unsigned char *network;
1582 struct ipv6hdr *ipv6;
1586 u32 flex_ptype, dtype_cmd;
1589 /* make sure ATR is enabled */
1590 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
1593 /* if sampling is disabled do nothing */
1594 if (!tx_ring->atr_sample_rate)
1597 /* snag network header to get L4 type and address */
1598 hdr.network = skb_network_header(skb);
1600 /* Currently only IPv4/IPv6 with TCP is supported */
1601 if (protocol == htons(ETH_P_IP)) {
1602 if (hdr.ipv4->protocol != IPPROTO_TCP)
1605 /* access ihl as a u8 to avoid unaligned access on ia64 */
1606 hlen = (hdr.network[0] & 0x0F) << 2;
1607 } else if (protocol == htons(ETH_P_IPV6)) {
1608 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
1611 hlen = sizeof(struct ipv6hdr);
1616 th = (struct tcphdr *)(hdr.network + hlen);
1618 /* Due to lack of space, no more new filters can be programmed */
1619 if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1622 tx_ring->atr_count++;
1624 /* sample on all syn/fin/rst packets or once every atr sample rate */
1628 (tx_ring->atr_count < tx_ring->atr_sample_rate))
1631 tx_ring->atr_count = 0;
1633 /* grab the next descriptor */
1634 i = tx_ring->next_to_use;
1635 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
1638 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1640 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1641 I40E_TXD_FLTR_QW0_QINDEX_MASK;
1642 flex_ptype |= (protocol == htons(ETH_P_IP)) ?
1643 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
1644 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
1645 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
1646 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
1648 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
1650 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
1652 dtype_cmd |= (th->fin || th->rst) ?
1653 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1654 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
1655 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1656 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1658 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
1659 I40E_TXD_FLTR_QW1_DEST_SHIFT;
1661 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
1662 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
1664 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
1665 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
1669 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1671 * @tx_ring: ring to send buffer on
1672 * @flags: the tx flags to be set
1674 * Checks the skb and set up correspondingly several generic transmit flags
1675 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1677 * Returns error code indicate the frame should be dropped upon error and the
1678 * otherwise returns 0 to indicate the flags has been set properly.
1680 static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
1681 struct i40e_ring *tx_ring,
1684 __be16 protocol = skb->protocol;
1687 /* if we have a HW VLAN tag being added, default to the HW one */
1688 if (vlan_tx_tag_present(skb)) {
1689 tx_flags |= vlan_tx_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1690 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1691 /* else if it is a SW VLAN, check the next protocol and store the tag */
1692 } else if (protocol == htons(ETH_P_8021Q)) {
1693 struct vlan_hdr *vhdr, _vhdr;
1694 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1698 protocol = vhdr->h_vlan_encapsulated_proto;
1699 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1700 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1703 /* Insert 802.1p priority into VLAN header */
1704 if ((tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED) &&
1705 ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
1706 (skb->priority != TC_PRIO_CONTROL))) {
1707 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
1708 tx_flags |= (skb->priority & 0x7) <<
1709 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
1710 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
1711 struct vlan_ethhdr *vhdr;
1714 rc = skb_cow_head(skb, 0);
1717 vhdr = (struct vlan_ethhdr *)skb->data;
1718 vhdr->h_vlan_TCI = htons(tx_flags >>
1719 I40E_TX_FLAGS_VLAN_SHIFT);
1721 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1729 * i40e_tso - set up the tso context descriptor
1730 * @tx_ring: ptr to the ring to send
1731 * @skb: ptr to the skb we're sending
1732 * @tx_flags: the collected send information
1733 * @protocol: the send protocol
1734 * @hdr_len: ptr to the size of the packet header
1735 * @cd_tunneling: ptr to context descriptor bits
1737 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1739 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1740 u32 tx_flags, __be16 protocol, u8 *hdr_len,
1741 u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling)
1743 u32 cd_cmd, cd_tso_len, cd_mss;
1744 struct ipv6hdr *ipv6h;
1745 struct tcphdr *tcph;
1750 if (!skb_is_gso(skb))
1753 err = skb_cow_head(skb, 0);
1757 if (protocol == htons(ETH_P_IP)) {
1758 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1759 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1762 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1764 } else if (skb_is_gso_v6(skb)) {
1766 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb)
1768 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1769 ipv6h->payload_len = 0;
1770 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1774 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1775 *hdr_len = (skb->encapsulation
1776 ? (skb_inner_transport_header(skb) - skb->data)
1777 : skb_transport_offset(skb)) + l4len;
1779 /* find the field values */
1780 cd_cmd = I40E_TX_CTX_DESC_TSO;
1781 cd_tso_len = skb->len - *hdr_len;
1782 cd_mss = skb_shinfo(skb)->gso_size;
1783 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1785 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1786 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1791 * i40e_tsyn - set up the tsyn context descriptor
1792 * @tx_ring: ptr to the ring to send
1793 * @skb: ptr to the skb we're sending
1794 * @tx_flags: the collected send information
1796 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
1798 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
1799 u32 tx_flags, u64 *cd_type_cmd_tso_mss)
1803 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
1806 /* Tx timestamps cannot be sampled when doing TSO */
1807 if (tx_flags & I40E_TX_FLAGS_TSO)
1810 /* only timestamp the outbound packet if the user has requested it and
1811 * we are not already transmitting a packet to be timestamped
1813 pf = i40e_netdev_to_pf(tx_ring->netdev);
1814 if (pf->ptp_tx && !pf->ptp_tx_skb) {
1815 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1816 pf->ptp_tx_skb = skb_get(skb);
1821 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
1822 I40E_TXD_CTX_QW1_CMD_SHIFT;
1828 * i40e_tx_enable_csum - Enable Tx checksum offloads
1830 * @tx_flags: Tx flags currently set
1831 * @td_cmd: Tx descriptor command bits to set
1832 * @td_offset: Tx descriptor header offsets to set
1833 * @cd_tunneling: ptr to context desc bits
1835 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags,
1836 u32 *td_cmd, u32 *td_offset,
1837 struct i40e_ring *tx_ring,
1840 struct ipv6hdr *this_ipv6_hdr;
1841 unsigned int this_tcp_hdrlen;
1842 struct iphdr *this_ip_hdr;
1843 u32 network_hdr_len;
1846 if (skb->encapsulation) {
1847 network_hdr_len = skb_inner_network_header_len(skb);
1848 this_ip_hdr = inner_ip_hdr(skb);
1849 this_ipv6_hdr = inner_ipv6_hdr(skb);
1850 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1852 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1854 if (tx_flags & I40E_TX_FLAGS_TSO) {
1855 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1856 ip_hdr(skb)->check = 0;
1859 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1861 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1862 if (tx_flags & I40E_TX_FLAGS_TSO) {
1863 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1864 ip_hdr(skb)->check = 0;
1867 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1871 /* Now set the ctx descriptor fields */
1872 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1873 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1874 I40E_TXD_CTX_UDP_TUNNELING |
1875 ((skb_inner_network_offset(skb) -
1876 skb_transport_offset(skb)) >> 1) <<
1877 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1880 network_hdr_len = skb_network_header_len(skb);
1881 this_ip_hdr = ip_hdr(skb);
1882 this_ipv6_hdr = ipv6_hdr(skb);
1883 this_tcp_hdrlen = tcp_hdrlen(skb);
1886 /* Enable IP checksum offloads */
1887 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1888 l4_hdr = this_ip_hdr->protocol;
1889 /* the stack computes the IP header already, the only time we
1890 * need the hardware to recompute it is in the case of TSO.
1892 if (tx_flags & I40E_TX_FLAGS_TSO) {
1893 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1894 this_ip_hdr->check = 0;
1896 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1898 /* Now set the td_offset for IP header length */
1899 *td_offset = (network_hdr_len >> 2) <<
1900 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1901 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1902 l4_hdr = this_ipv6_hdr->nexthdr;
1903 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1904 /* Now set the td_offset for IP header length */
1905 *td_offset = (network_hdr_len >> 2) <<
1906 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1908 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1909 *td_offset |= (skb_network_offset(skb) >> 1) <<
1910 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1912 /* Enable L4 checksum offloads */
1915 /* enable checksum offloads */
1916 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1917 *td_offset |= (this_tcp_hdrlen >> 2) <<
1918 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1921 /* enable SCTP checksum offload */
1922 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1923 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1924 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1927 /* enable UDP checksum offload */
1928 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1929 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1930 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1938 * i40e_create_tx_ctx Build the Tx context descriptor
1939 * @tx_ring: ring to create the descriptor on
1940 * @cd_type_cmd_tso_mss: Quad Word 1
1941 * @cd_tunneling: Quad Word 0 - bits 0-31
1942 * @cd_l2tag2: Quad Word 0 - bits 32-63
1944 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1945 const u64 cd_type_cmd_tso_mss,
1946 const u32 cd_tunneling, const u32 cd_l2tag2)
1948 struct i40e_tx_context_desc *context_desc;
1949 int i = tx_ring->next_to_use;
1951 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1952 !cd_tunneling && !cd_l2tag2)
1955 /* grab the next descriptor */
1956 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1959 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1961 /* cpu_to_le32 and assign to struct fields */
1962 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1963 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1964 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1968 * i40e_tx_map - Build the Tx descriptor
1969 * @tx_ring: ring to send buffer on
1971 * @first: first buffer info buffer to use
1972 * @tx_flags: collected send information
1973 * @hdr_len: size of the packet header
1974 * @td_cmd: the command field in the descriptor
1975 * @td_offset: offset for checksum or crc
1977 static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1978 struct i40e_tx_buffer *first, u32 tx_flags,
1979 const u8 hdr_len, u32 td_cmd, u32 td_offset)
1981 unsigned int data_len = skb->data_len;
1982 unsigned int size = skb_headlen(skb);
1983 struct skb_frag_struct *frag;
1984 struct i40e_tx_buffer *tx_bi;
1985 struct i40e_tx_desc *tx_desc;
1986 u16 i = tx_ring->next_to_use;
1991 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1992 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1993 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1994 I40E_TX_FLAGS_VLAN_SHIFT;
1997 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1998 gso_segs = skb_shinfo(skb)->gso_segs;
2002 /* multiply data chunks by size of headers */
2003 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
2004 first->gso_segs = gso_segs;
2006 first->tx_flags = tx_flags;
2008 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
2010 tx_desc = I40E_TX_DESC(tx_ring, i);
2013 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
2014 if (dma_mapping_error(tx_ring->dev, dma))
2017 /* record length, and DMA address */
2018 dma_unmap_len_set(tx_bi, len, size);
2019 dma_unmap_addr_set(tx_bi, dma, dma);
2021 tx_desc->buffer_addr = cpu_to_le64(dma);
2023 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
2024 tx_desc->cmd_type_offset_bsz =
2025 build_ctob(td_cmd, td_offset,
2026 I40E_MAX_DATA_PER_TXD, td_tag);
2030 if (i == tx_ring->count) {
2031 tx_desc = I40E_TX_DESC(tx_ring, 0);
2035 dma += I40E_MAX_DATA_PER_TXD;
2036 size -= I40E_MAX_DATA_PER_TXD;
2038 tx_desc->buffer_addr = cpu_to_le64(dma);
2041 if (likely(!data_len))
2044 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2049 if (i == tx_ring->count) {
2050 tx_desc = I40E_TX_DESC(tx_ring, 0);
2054 size = skb_frag_size(frag);
2057 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2060 tx_bi = &tx_ring->tx_bi[i];
2063 /* Place RS bit on last descriptor of any packet that spans across the
2064 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
2066 #define WB_STRIDE 0x3
2067 if (((i & WB_STRIDE) != WB_STRIDE) &&
2068 (first <= &tx_ring->tx_bi[i]) &&
2069 (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
2070 tx_desc->cmd_type_offset_bsz =
2071 build_ctob(td_cmd, td_offset, size, td_tag) |
2072 cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
2073 I40E_TXD_QW1_CMD_SHIFT);
2075 tx_desc->cmd_type_offset_bsz =
2076 build_ctob(td_cmd, td_offset, size, td_tag) |
2077 cpu_to_le64((u64)I40E_TXD_CMD <<
2078 I40E_TXD_QW1_CMD_SHIFT);
2081 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
2082 tx_ring->queue_index),
2085 /* set the timestamp */
2086 first->time_stamp = jiffies;
2088 /* Force memory writes to complete before letting h/w
2089 * know there are new descriptors to fetch. (Only
2090 * applicable for weak-ordered memory model archs,
2095 /* set next_to_watch value indicating a packet is present */
2096 first->next_to_watch = tx_desc;
2099 if (i == tx_ring->count)
2102 tx_ring->next_to_use = i;
2104 /* notify HW of packet */
2105 writel(i, tx_ring->tail);
2110 dev_info(tx_ring->dev, "TX DMA map failed\n");
2112 /* clear dma mappings for failed tx_bi map */
2114 tx_bi = &tx_ring->tx_bi[i];
2115 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
2123 tx_ring->next_to_use = i;
2127 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
2128 * @tx_ring: the ring to be checked
2129 * @size: the size buffer we want to assure is available
2131 * Returns -EBUSY if a stop is needed, else 0
2133 static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2135 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
2136 /* Memory barrier before checking head and tail */
2139 /* Check again in a case another CPU has just made room available. */
2140 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
2143 /* A reprieve! - use start_queue because it doesn't call schedule */
2144 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
2145 ++tx_ring->tx_stats.restart_queue;
2150 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
2151 * @tx_ring: the ring to be checked
2152 * @size: the size buffer we want to assure is available
2154 * Returns 0 if stop is not needed
2156 static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2158 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
2160 return __i40e_maybe_stop_tx(tx_ring, size);
2164 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
2166 * @tx_ring: ring to send buffer on
2168 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
2169 * there is not enough descriptors available in this ring since we need at least
2172 static int i40e_xmit_descriptor_count(struct sk_buff *skb,
2173 struct i40e_ring *tx_ring)
2175 #if PAGE_SIZE > I40E_MAX_DATA_PER_TXD
2180 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2181 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
2182 * + 4 desc gap to avoid the cache line where head is,
2183 * + 1 desc for context descriptor,
2184 * otherwise try next time
2186 #if PAGE_SIZE > I40E_MAX_DATA_PER_TXD
2187 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
2188 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
2190 count += skb_shinfo(skb)->nr_frags;
2192 count += TXD_USE_COUNT(skb_headlen(skb));
2193 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2194 tx_ring->tx_stats.tx_busy++;
2201 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2203 * @tx_ring: ring to send buffer on
2205 * Returns NETDEV_TX_OK if sent, else an error code
2207 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2208 struct i40e_ring *tx_ring)
2210 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2211 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2212 struct i40e_tx_buffer *first;
2220 if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
2221 return NETDEV_TX_BUSY;
2223 /* prepare the xmit flags */
2224 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2227 /* obtain protocol of skb */
2228 protocol = skb->protocol;
2230 /* record the location of the first descriptor for this packet */
2231 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2233 /* setup IPv4/IPv6 offloads */
2234 if (protocol == htons(ETH_P_IP))
2235 tx_flags |= I40E_TX_FLAGS_IPV4;
2236 else if (protocol == htons(ETH_P_IPV6))
2237 tx_flags |= I40E_TX_FLAGS_IPV6;
2239 tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len,
2240 &cd_type_cmd_tso_mss, &cd_tunneling);
2245 tx_flags |= I40E_TX_FLAGS_TSO;
2247 skb_tx_timestamp(skb);
2249 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
2252 tx_flags |= I40E_TX_FLAGS_TSYN;
2254 /* always enable CRC insertion offload */
2255 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2257 /* Always offload the checksum, since it's in the data descriptor */
2258 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2259 tx_flags |= I40E_TX_FLAGS_CSUM;
2261 i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset,
2262 tx_ring, &cd_tunneling);
2265 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2266 cd_tunneling, cd_l2tag2);
2268 /* Add Flow Director ATR if it's enabled.
2270 * NOTE: this must always be directly before the data descriptor.
2272 i40e_atr(tx_ring, skb, tx_flags, protocol);
2274 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2277 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
2279 return NETDEV_TX_OK;
2282 dev_kfree_skb_any(skb);
2283 return NETDEV_TX_OK;
2287 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2289 * @netdev: network interface device structure
2291 * Returns NETDEV_TX_OK if sent, else an error code
2293 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2295 struct i40e_netdev_priv *np = netdev_priv(netdev);
2296 struct i40e_vsi *vsi = np->vsi;
2297 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
2299 /* hardware can't handle really short frames, hardware padding works
2302 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2303 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2304 return NETDEV_TX_OK;
2305 skb->len = I40E_MIN_TX_LEN;
2306 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2309 return i40e_xmit_frame_ring(skb, tx_ring);