drivers/net/ethernet/intel/i40e/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29 #include "i40e.h"
  30 #include "i40e_prototype.h"
  31
  32 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  33                                 u32 td_tag)
  34 {
  35         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  36                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  37                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  38                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  39                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  40 }
  41
  42 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  43 #define I40E_FD_CLEAN_DELAY 10
  44 /**
  45  * i40e_program_fdir_filter - Program a Flow Director filter
  46  * @fdir_data: Packet data that will be filter parameters
  47  * @raw_packet: the pre-allocated packet buffer for FDir
  48  * @pf: The PF pointer
  49  * @add: True for add/update, False for remove
  50  **/
  51 int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
  52                              struct i40e_pf *pf, bool add)
  53 {
  54         struct i40e_filter_program_desc *fdir_desc;
  55         struct i40e_tx_buffer *tx_buf, *first;
  56         struct i40e_tx_desc *tx_desc;
  57         struct i40e_ring *tx_ring;
  58         unsigned int fpt, dcc;
  59         struct i40e_vsi *vsi;
  60         struct device *dev;
  61         dma_addr_t dma;
  62         u32 td_cmd = 0;
  63         u16 delay = 0;
  64         u16 i;
  65
  66         /* find existing FDIR VSI */
  67         vsi = NULL;
  68         for (i = 0; i < pf->num_alloc_vsi; i++)
  69                 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
  70                         vsi = pf->vsi[i];
  71         if (!vsi)
  72                 return -ENOENT;
  73
  74         tx_ring = vsi->tx_rings[0];
  75         dev = tx_ring->dev;
  76
  77         /* we need two descriptors to add/del a filter and we can wait */
  78         do {
  79                 if (I40E_DESC_UNUSED(tx_ring) > 1)
  80                         break;
  81                 msleep_interruptible(1);
  82                 delay++;
  83         } while (delay < I40E_FD_CLEAN_DELAY);
  84
  85         if (!(I40E_DESC_UNUSED(tx_ring) > 1))
  86                 return -EAGAIN;
  87
  88         dma = dma_map_single(dev, raw_packet,
  89                              I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
  90         if (dma_mapping_error(dev, dma))
  91                 goto dma_fail;
  92
  93         /* grab the next descriptor */
  94         i = tx_ring->next_to_use;
  95         fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
  96         first = &tx_ring->tx_bi[i];
  97         memset(first, 0, sizeof(struct i40e_tx_buffer));
  98
  99         tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
 100
 101         fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
 102               I40E_TXD_FLTR_QW0_QINDEX_MASK;
 103
 104         fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
 105                I40E_TXD_FLTR_QW0_FLEXOFF_MASK;
 106
 107         fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
 108                I40E_TXD_FLTR_QW0_PCTYPE_MASK;
 109
 110         /* Use LAN VSI Id if not programmed by user */
 111         if (fdir_data->dest_vsi == 0)
 112                 fpt |= (pf->vsi[pf->lan_vsi]->id) <<
 113                        I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
 114         else
 115                 fpt |= ((u32)fdir_data->dest_vsi <<
 116                         I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
 117                        I40E_TXD_FLTR_QW0_DEST_VSI_MASK;
 118
 119         dcc = I40E_TX_DESC_DTYPE_FILTER_PROG;
 120
 121         if (add)
 122                 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
 123                        I40E_TXD_FLTR_QW1_PCMD_SHIFT;
 124         else
 125                 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
 126                        I40E_TXD_FLTR_QW1_PCMD_SHIFT;
 127
 128         dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) &
 129                I40E_TXD_FLTR_QW1_DEST_MASK;
 130
 131         dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
 132                I40E_TXD_FLTR_QW1_FD_STATUS_MASK;
 133
 134         if (fdir_data->cnt_index != 0) {
 135                 dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
 136                 dcc |= ((u32)fdir_data->cnt_index <<
 137                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
 138                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
 139         }
 140
 141         fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt);
 142         fdir_desc->rsvd = cpu_to_le32(0);
 143         fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc);
 144         fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id);
 145
 146         /* Now program a dummy descriptor */
 147         i = tx_ring->next_to_use;
 148         tx_desc = I40E_TX_DESC(tx_ring, i);
 149         tx_buf = &tx_ring->tx_bi[i];
 150
 151         tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
 152
 153         memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
 154
 155         /* record length, and DMA address */
 156         dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
 157         dma_unmap_addr_set(tx_buf, dma, dma);
 158
 159         tx_desc->buffer_addr = cpu_to_le64(dma);
 160         td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
 161
 162         tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
 163         tx_buf->raw_buf = (void *)raw_packet;
 164
 165         tx_desc->cmd_type_offset_bsz =
 166                 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
 167
 168         /* Force memory writes to complete before letting h/w
 169          * know there are new descriptors to fetch.
 170          */
 171         wmb();
 172
 173         /* Mark the data descriptor to be watched */
 174         first->next_to_watch = tx_desc;
 175
 176         writel(tx_ring->next_to_use, tx_ring->tail);
 177         return 0;
 178
 179 dma_fail:
 180         return -1;
 181 }
 182
 183 #define IP_HEADER_OFFSET 14
 184 #define I40E_UDPIP_DUMMY_PACKET_LEN 42
 185 /**
 186  * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
 187  * @vsi: pointer to the targeted VSI
 188  * @fd_data: the flow director data required for the FDir descriptor
 189  * @add: true adds a filter, false removes it
 190  *
 191  * Returns 0 if the filters were successfully added or removed
 192  **/
 193 static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
 194                                    struct i40e_fdir_filter *fd_data,
 195                                    bool add)
 196 {
 197         struct i40e_pf *pf = vsi->back;
 198         struct udphdr *udp;
 199         struct iphdr *ip;
 200         bool err = false;
 201         u8 *raw_packet;
 202         int ret;
 203         static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
 204                 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
 205                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 206
 207         raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
 208         if (!raw_packet)
 209                 return -ENOMEM;
 210         memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
 211
 212         ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
 213         udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
 214               + sizeof(struct iphdr));
 215
 216         ip->daddr = fd_data->dst_ip[0];
 217         udp->dest = fd_data->dst_port;
 218         ip->saddr = fd_data->src_ip[0];
 219         udp->source = fd_data->src_port;
 220
 221         fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 222         ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
 223         if (ret) {
 224                 dev_info(&pf->pdev->dev,
 225                          "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
 226                          fd_data->pctype, fd_data->fd_id, ret);
 227                 err = true;
 228         } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
 229                 if (add)
 230                         dev_info(&pf->pdev->dev,
 231                                  "Filter OK for PCTYPE %d loc = %d\n",
 232                                  fd_data->pctype, fd_data->fd_id);
 233                 else
 234                         dev_info(&pf->pdev->dev,
 235                                  "Filter deleted for PCTYPE %d loc = %d\n",
 236                                  fd_data->pctype, fd_data->fd_id);
 237         }
 238         return err ? -EOPNOTSUPP : 0;
 239 }
 240
 241 #define I40E_TCPIP_DUMMY_PACKET_LEN 54
 242 /**
 243  * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
 244  * @vsi: pointer to the targeted VSI
 245  * @fd_data: the flow director data required for the FDir descriptor
 246  * @add: true adds a filter, false removes it
 247  *
 248  * Returns 0 if the filters were successfully added or removed
 249  **/
 250 static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
 251                                    struct i40e_fdir_filter *fd_data,
 252                                    bool add)
 253 {
 254         struct i40e_pf *pf = vsi->back;
 255         struct tcphdr *tcp;
 256         struct iphdr *ip;
 257         bool err = false;
 258         u8 *raw_packet;
 259         int ret;
 260         /* Dummy packet */
 261         static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
 262                 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
 263                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
 264                 0x0, 0x72, 0, 0, 0, 0};
 265
 266         raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
 267         if (!raw_packet)
 268                 return -ENOMEM;
 269         memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
 270
 271         ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
 272         tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
 273               + sizeof(struct iphdr));
 274
 275         ip->daddr = fd_data->dst_ip[0];
 276         tcp->dest = fd_data->dst_port;
 277         ip->saddr = fd_data->src_ip[0];
 278         tcp->source = fd_data->src_port;
 279
 280         if (add) {
 281                 pf->fd_tcp_rule++;
 282                 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) {
 283                         if (I40E_DEBUG_FD & pf->hw.debug_mask)
 284                                 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
 285                         pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
 286                 }
 287         } else {
 288                 pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ?
 289                                   (pf->fd_tcp_rule - 1) : 0;
 290                 if (pf->fd_tcp_rule == 0) {
 291                         pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
 292                         if (I40E_DEBUG_FD & pf->hw.debug_mask)
 293                                 dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n");
 294                 }
 295         }
 296
 297         fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
 298         ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
 299
 300         if (ret) {
 301                 dev_info(&pf->pdev->dev,
 302                          "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
 303                          fd_data->pctype, fd_data->fd_id, ret);
 304                 err = true;
 305         } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
 306                 if (add)
 307                         dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
 308                                  fd_data->pctype, fd_data->fd_id);
 309                 else
 310                         dev_info(&pf->pdev->dev,
 311                                  "Filter deleted for PCTYPE %d loc = %d\n",
 312                                  fd_data->pctype, fd_data->fd_id);
 313         }
 314
 315         return err ? -EOPNOTSUPP : 0;
 316 }
 317
 318 /**
 319  * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
 320  * a specific flow spec
 321  * @vsi: pointer to the targeted VSI
 322  * @fd_data: the flow director data required for the FDir descriptor
 323  * @add: true adds a filter, false removes it
 324  *
 325  * Always returns -EOPNOTSUPP
 326  **/
 327 static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
 328                                     struct i40e_fdir_filter *fd_data,
 329                                     bool add)
 330 {
 331         return -EOPNOTSUPP;
 332 }
 333
 334 #define I40E_IP_DUMMY_PACKET_LEN 34
 335 /**
 336  * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
 337  * a specific flow spec
 338  * @vsi: pointer to the targeted VSI
 339  * @fd_data: the flow director data required for the FDir descriptor
 340  * @add: true adds a filter, false removes it
 341  *
 342  * Returns 0 if the filters were successfully added or removed
 343  **/
 344 static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
 345                                   struct i40e_fdir_filter *fd_data,
 346                                   bool add)
 347 {
 348         struct i40e_pf *pf = vsi->back;
 349         struct iphdr *ip;
 350         bool err = false;
 351         u8 *raw_packet;
 352         int ret;
 353         int i;
 354         static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
 355                 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
 356                 0, 0, 0, 0};
 357
 358         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
 359              i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) {
 360                 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
 361                 if (!raw_packet)
 362                         return -ENOMEM;
 363                 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
 364                 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
 365
 366                 ip->saddr = fd_data->src_ip[0];
 367                 ip->daddr = fd_data->dst_ip[0];
 368                 ip->protocol = 0;
 369
 370                 fd_data->pctype = i;
 371                 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
 372
 373                 if (ret) {
 374                         dev_info(&pf->pdev->dev,
 375                                  "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
 376                                  fd_data->pctype, fd_data->fd_id, ret);
 377                         err = true;
 378                 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
 379                         if (add)
 380                                 dev_info(&pf->pdev->dev,
 381                                          "Filter OK for PCTYPE %d loc = %d\n",
 382                                          fd_data->pctype, fd_data->fd_id);
 383                         else
 384                                 dev_info(&pf->pdev->dev,
 385                                          "Filter deleted for PCTYPE %d loc = %d\n",
 386                                          fd_data->pctype, fd_data->fd_id);
 387                 }
 388         }
 389
 390         return err ? -EOPNOTSUPP : 0;
 391 }
 392
 393 /**
 394  * i40e_add_del_fdir - Build raw packets to add/del fdir filter
 395  * @vsi: pointer to the targeted VSI
 396  * @cmd: command to get or set RX flow classification rules
 397  * @add: true adds a filter, false removes it
 398  *
 399  **/
 400 int i40e_add_del_fdir(struct i40e_vsi *vsi,
 401                       struct i40e_fdir_filter *input, bool add)
 402 {
 403         struct i40e_pf *pf = vsi->back;
 404         int ret;
 405
 406         switch (input->flow_type & ~FLOW_EXT) {
 407         case TCP_V4_FLOW:
 408                 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
 409                 break;
 410         case UDP_V4_FLOW:
 411                 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
 412                 break;
 413         case SCTP_V4_FLOW:
 414                 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
 415                 break;
 416         case IPV4_FLOW:
 417                 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
 418                 break;
 419         case IP_USER_FLOW:
 420                 switch (input->ip4_proto) {
 421                 case IPPROTO_TCP:
 422                         ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
 423                         break;
 424                 case IPPROTO_UDP:
 425                         ret = i40e_add_del_fdir_udpv4(vsi, input, add);
 426                         break;
 427                 case IPPROTO_SCTP:
 428                         ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
 429                         break;
 430                 default:
 431                         ret = i40e_add_del_fdir_ipv4(vsi, input, add);
 432                         break;
 433                 }
 434                 break;
 435         default:
 436                 dev_info(&pf->pdev->dev, "Could not specify spec type %d\n",
 437                          input->flow_type);
 438                 ret = -EINVAL;
 439         }
 440
 441         /* The buffer allocated here is freed by the i40e_clean_tx_ring() */
 442         return ret;
 443 }
 444
 445 /**
 446  * i40e_fd_handle_status - check the Programming Status for FD
 447  * @rx_ring: the Rx ring for this descriptor
 448  * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor.
 449  * @prog_id: the id originally used for programming
 450  *
 451  * This is used to verify if the FD programming or invalidation
 452  * requested by SW to the HW is successful or not and take actions accordingly.
 453  **/
 454 static void i40e_fd_handle_status(struct i40e_ring *rx_ring,
 455                                   union i40e_rx_desc *rx_desc, u8 prog_id)
 456 {
 457         struct i40e_pf *pf = rx_ring->vsi->back;
 458         struct pci_dev *pdev = pf->pdev;
 459         u32 fcnt_prog, fcnt_avail;
 460         u32 error;
 461         u64 qw;
 462
 463         qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 464         error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
 465                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
 466
 467         if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
 468                 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) ||
 469                     (I40E_DEBUG_FD & pf->hw.debug_mask))
 470                         dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
 471                                  rx_desc->wb.qword0.hi_dword.fd_id);
 472
 473                 /* Check if the programming error is for ATR.
 474                  * If so, auto disable ATR and set a state for
 475                  * flush in progress. Next time we come here if flush is in
 476                  * progress do nothing, once flush is complete the state will
 477                  * be cleared.
 478                  */
 479                 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
 480                         return;
 481
 482                 pf->fd_add_err++;
 483                 /* store the current atr filter count */
 484                 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
 485
 486                 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) &&
 487                     (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
 488                         pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED;
 489                         set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
 490                 }
 491
 492                 /* filter programming failed most likely due to table full */
 493                 fcnt_prog = i40e_get_global_fd_count(pf);
 494                 fcnt_avail = pf->fdir_pf_filter_count;
 495                 /* If ATR is running fcnt_prog can quickly change,
 496                  * if we are very close to full, it makes sense to disable
 497                  * FD ATR/SB and then re-enable it when there is room.
 498                  */
 499                 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
 500                         if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
 501                             !(pf->auto_disable_flags &
 502                                      I40E_FLAG_FD_SB_ENABLED)) {
 503                                 if (I40E_DEBUG_FD & pf->hw.debug_mask)
 504                                         dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
 505                                 pf->auto_disable_flags |=
 506                                                         I40E_FLAG_FD_SB_ENABLED;
 507                         }
 508                 } else {
 509                         dev_info(&pdev->dev,
 510                                 "FD filter programming failed due to incorrect filter parameters\n");
 511                 }
 512         } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
 513                 if (I40E_DEBUG_FD & pf->hw.debug_mask)
 514                         dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
 515                                  rx_desc->wb.qword0.hi_dword.fd_id);
 516         }
 517 }
 518
 519 /**
 520  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
 521  * @ring:      the ring that owns the buffer
 522  * @tx_buffer: the buffer to free
 523  **/
 524 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
 525                                             struct i40e_tx_buffer *tx_buffer)
 526 {
 527         if (tx_buffer->skb) {
 528                 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
 529                         kfree(tx_buffer->raw_buf);
 530                 else
 531                         dev_kfree_skb_any(tx_buffer->skb);
 532
 533                 if (dma_unmap_len(tx_buffer, len))
 534                         dma_unmap_single(ring->dev,
 535                                          dma_unmap_addr(tx_buffer, dma),
 536                                          dma_unmap_len(tx_buffer, len),
 537                                          DMA_TO_DEVICE);
 538         } else if (dma_unmap_len(tx_buffer, len)) {
 539                 dma_unmap_page(ring->dev,
 540                                dma_unmap_addr(tx_buffer, dma),
 541                                dma_unmap_len(tx_buffer, len),
 542                                DMA_TO_DEVICE);
 543         }
 544         tx_buffer->next_to_watch = NULL;
 545         tx_buffer->skb = NULL;
 546         dma_unmap_len_set(tx_buffer, len, 0);
 547         /* tx_buffer must be completely set up in the transmit path */
 548 }
 549
 550 /**
 551  * i40e_clean_tx_ring - Free any empty Tx buffers
 552  * @tx_ring: ring to be cleaned
 553  **/
 554 void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
 555 {
 556         unsigned long bi_size;
 557         u16 i;
 558
 559         /* ring already cleared, nothing to do */
 560         if (!tx_ring->tx_bi)
 561                 return;
 562
 563         /* Free all the Tx ring sk_buffs */
 564         for (i = 0; i < tx_ring->count; i++)
 565                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
 566
 567         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 568         memset(tx_ring->tx_bi, 0, bi_size);
 569
 570         /* Zero out the descriptor ring */
 571         memset(tx_ring->desc, 0, tx_ring->size);
 572
 573         tx_ring->next_to_use = 0;
 574         tx_ring->next_to_clean = 0;
 575
 576         if (!tx_ring->netdev)
 577                 return;
 578
 579         /* cleanup Tx queue statistics */
 580         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 581                                                   tx_ring->queue_index));
 582 }
 583
 584 /**
 585  * i40e_free_tx_resources - Free Tx resources per queue
 586  * @tx_ring: Tx descriptor ring for a specific queue
 587  *
 588  * Free all transmit software resources
 589  **/
 590 void i40e_free_tx_resources(struct i40e_ring *tx_ring)
 591 {
 592         i40e_clean_tx_ring(tx_ring);
 593         kfree(tx_ring->tx_bi);
 594         tx_ring->tx_bi = NULL;
 595
 596         if (tx_ring->desc) {
 597                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 598                                   tx_ring->desc, tx_ring->dma);
 599                 tx_ring->desc = NULL;
 600         }
 601 }
 602
 603 /**
 604  * i40e_get_tx_pending - how many tx descriptors not processed
 605  * @tx_ring: the ring of descriptors
 606  *
 607  * Since there is no access to the ring head register
 608  * in XL710, we need to use our local copies
 609  **/
 610 u32 i40e_get_tx_pending(struct i40e_ring *ring)
 611 {
 612         u32 head, tail;
 613
 614         head = i40e_get_head(ring);
 615         tail = readl(ring->tail);
 616
 617         if (head != tail)
 618                 return (head < tail) ?
 619                         tail - head : (tail + ring->count - head);
 620
 621         return 0;
 622 }
 623
 624 #define WB_STRIDE 0x3
 625
 626 /**
 627  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 628  * @tx_ring:  tx ring to clean
 629  * @budget:   how many cleans we're allowed
 630  *
 631  * Returns true if there's any budget left (e.g. the clean is finished)
 632  **/
 633 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 634 {
 635         u16 i = tx_ring->next_to_clean;
 636         struct i40e_tx_buffer *tx_buf;
 637         struct i40e_tx_desc *tx_head;
 638         struct i40e_tx_desc *tx_desc;
 639         unsigned int total_packets = 0;
 640         unsigned int total_bytes = 0;
 641
 642         tx_buf = &tx_ring->tx_bi[i];
 643         tx_desc = I40E_TX_DESC(tx_ring, i);
 644         i -= tx_ring->count;
 645
 646         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 647
 648         do {
 649                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 650
 651                 /* if next_to_watch is not set then there is no work pending */
 652                 if (!eop_desc)
 653                         break;
 654
 655                 /* prevent any other reads prior to eop_desc */
 656                 read_barrier_depends();
 657
 658                 /* we have caught up to head, no work left to do */
 659                 if (tx_head == tx_desc)
 660                         break;
 661
 662                 /* clear next_to_watch to prevent false hangs */
 663                 tx_buf->next_to_watch = NULL;
 664
 665                 /* update the statistics for this packet */
 666                 total_bytes += tx_buf->bytecount;
 667                 total_packets += tx_buf->gso_segs;
 668
 669                 /* free the skb */
 670                 dev_consume_skb_any(tx_buf->skb);
 671
 672                 /* unmap skb header data */
 673                 dma_unmap_single(tx_ring->dev,
 674                                  dma_unmap_addr(tx_buf, dma),
 675                                  dma_unmap_len(tx_buf, len),
 676                                  DMA_TO_DEVICE);
 677
 678                 /* clear tx_buffer data */
 679                 tx_buf->skb = NULL;
 680                 dma_unmap_len_set(tx_buf, len, 0);
 681
 682                 /* unmap remaining buffers */
 683                 while (tx_desc != eop_desc) {
 684
 685                         tx_buf++;
 686                         tx_desc++;
 687                         i++;
 688                         if (unlikely(!i)) {
 689                                 i -= tx_ring->count;
 690                                 tx_buf = tx_ring->tx_bi;
 691                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 692                         }
 693
 694                         /* unmap any remaining paged data */
 695                         if (dma_unmap_len(tx_buf, len)) {
 696                                 dma_unmap_page(tx_ring->dev,
 697                                                dma_unmap_addr(tx_buf, dma),
 698                                                dma_unmap_len(tx_buf, len),
 699                                                DMA_TO_DEVICE);
 700                                 dma_unmap_len_set(tx_buf, len, 0);
 701                         }
 702                 }
 703
 704                 /* move us one more past the eop_desc for start of next pkt */
 705                 tx_buf++;
 706                 tx_desc++;
 707                 i++;
 708                 if (unlikely(!i)) {
 709                         i -= tx_ring->count;
 710                         tx_buf = tx_ring->tx_bi;
 711                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 712                 }
 713
 714                 prefetch(tx_desc);
 715
 716                 /* update budget accounting */
 717                 budget--;
 718         } while (likely(budget));
 719
 720         i += tx_ring->count;
 721         tx_ring->next_to_clean = i;
 722         u64_stats_update_begin(&tx_ring->syncp);
 723         tx_ring->stats.bytes += total_bytes;
 724         tx_ring->stats.packets += total_packets;
 725         u64_stats_update_end(&tx_ring->syncp);
 726         tx_ring->q_vector->tx.total_bytes += total_bytes;
 727         tx_ring->q_vector->tx.total_packets += total_packets;
 728
 729         if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 730                 unsigned int j = 0;
 731
 732                 /* check to see if there are < 4 descriptors
 733                  * waiting to be written back, then kick the hardware to force
 734                  * them to be written back in case we stay in NAPI.
 735                  * In this mode on X722 we do not enable Interrupt.
 736                  */
 737                 j = i40e_get_tx_pending(tx_ring);
 738
 739                 if (budget &&
 740                     ((j / (WB_STRIDE + 1)) == 0) && (j != 0) &&
 741                     !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
 742                     (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
 743                         tx_ring->arm_wb = true;
 744         }
 745
 746         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 747                                                       tx_ring->queue_index),
 748                                   total_packets, total_bytes);
 749
 750 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 751         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 752                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 753                 /* Make sure that anybody stopping the queue after this
 754                  * sees the new next_to_clean.
 755                  */
 756                 smp_mb();
 757                 if (__netif_subqueue_stopped(tx_ring->netdev,
 758                                              tx_ring->queue_index) &&
 759                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 760                         netif_wake_subqueue(tx_ring->netdev,
 761                                             tx_ring->queue_index);
 762                         ++tx_ring->tx_stats.restart_queue;
 763                 }
 764         }
 765
 766         return !!budget;
 767 }
 768
 769 /**
 770  * i40e_force_wb - Arm hardware to do a wb on noncache aligned descriptors
 771  * @vsi: the VSI we care about
 772  * @q_vector: the vector  on which to force writeback
 773  *
 774  **/
 775 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 776 {
 777         u16 flags = q_vector->tx.ring[0].flags;
 778
 779         if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 780                 u32 val;
 781
 782                 if (q_vector->arm_wb_state)
 783                         return;
 784
 785                 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK;
 786
 787                 wr32(&vsi->back->hw,
 788                      I40E_PFINT_DYN_CTLN(q_vector->v_idx +
 789                                          vsi->base_vector - 1),
 790                      val);
 791                 q_vector->arm_wb_state = true;
 792         } else if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
 793                 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
 794                           I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
 795                           I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
 796                           I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
 797                           /* allow 00 to be written to the index */
 798
 799                 wr32(&vsi->back->hw,
 800                      I40E_PFINT_DYN_CTLN(q_vector->v_idx +
 801                                          vsi->base_vector - 1), val);
 802         } else {
 803                 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
 804                           I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
 805                           I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
 806                           I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
 807                         /* allow 00 to be written to the index */
 808
 809                 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
 810         }
 811 }
 812
 813 /**
 814  * i40e_set_new_dynamic_itr - Find new ITR level
 815  * @rc: structure containing ring performance data
 816  *
 817  * Stores a new ITR value based on packets and byte counts during
 818  * the last interrupt.  The advantage of per interrupt computation
 819  * is faster updates and more accurate ITR for the current traffic
 820  * pattern.  Constants in this function were computed based on
 821  * theoretical maximum wire speed and thresholds were set based on
 822  * testing data as well as attempting to minimize response time
 823  * while increasing bulk throughput.
 824  **/
 825 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 826 {
 827         enum i40e_latency_range new_latency_range = rc->latency_range;
 828         u32 new_itr = rc->itr;
 829         int bytes_per_int;
 830
 831         if (rc->total_packets == 0 || !rc->itr)
 832                 return;
 833
 834         /* simple throttlerate management
 835          *   0-10MB/s   lowest (100000 ints/s)
 836          *  10-20MB/s   low    (20000 ints/s)
 837          *  20-1249MB/s bulk   (8000 ints/s)
 838          */
 839         bytes_per_int = rc->total_bytes / rc->itr;
 840         switch (new_latency_range) {
 841         case I40E_LOWEST_LATENCY:
 842                 if (bytes_per_int > 10)
 843                         new_latency_range = I40E_LOW_LATENCY;
 844                 break;
 845         case I40E_LOW_LATENCY:
 846                 if (bytes_per_int > 20)
 847                         new_latency_range = I40E_BULK_LATENCY;
 848                 else if (bytes_per_int <= 10)
 849                         new_latency_range = I40E_LOWEST_LATENCY;
 850                 break;
 851         case I40E_BULK_LATENCY:
 852                 if (bytes_per_int <= 20)
 853                         new_latency_range = I40E_LOW_LATENCY;
 854                 break;
 855         default:
 856                 if (bytes_per_int <= 20)
 857                         new_latency_range = I40E_LOW_LATENCY;
 858                 break;
 859         }
 860         rc->latency_range = new_latency_range;
 861
 862         switch (new_latency_range) {
 863         case I40E_LOWEST_LATENCY:
 864                 new_itr = I40E_ITR_100K;
 865                 break;
 866         case I40E_LOW_LATENCY:
 867                 new_itr = I40E_ITR_20K;
 868                 break;
 869         case I40E_BULK_LATENCY:
 870                 new_itr = I40E_ITR_8K;
 871                 break;
 872         default:
 873                 break;
 874         }
 875
 876         if (new_itr != rc->itr)
 877                 rc->itr = new_itr;
 878
 879         rc->total_bytes = 0;
 880         rc->total_packets = 0;
 881 }
 882
 883 /**
 884  * i40e_clean_programming_status - clean the programming status descriptor
 885  * @rx_ring: the rx ring that has this descriptor
 886  * @rx_desc: the rx descriptor written back by HW
 887  *
 888  * Flow director should handle FD_FILTER_STATUS to check its filter programming
 889  * status being successful or not and take actions accordingly. FCoE should
 890  * handle its context/filter programming/invalidation status and take actions.
 891  *
 892  **/
 893 static void i40e_clean_programming_status(struct i40e_ring *rx_ring,
 894                                           union i40e_rx_desc *rx_desc)
 895 {
 896         u64 qw;
 897         u8 id;
 898
 899         qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 900         id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
 901                   I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
 902
 903         if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
 904                 i40e_fd_handle_status(rx_ring, rx_desc, id);
 905 #ifdef I40E_FCOE
 906         else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) ||
 907                  (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS))
 908                 i40e_fcoe_handle_status(rx_ring, rx_desc, id);
 909 #endif
 910 }
 911
 912 /**
 913  * i40e_setup_tx_descriptors - Allocate the Tx descriptors
 914  * @tx_ring: the tx ring to set up
 915  *
 916  * Return 0 on success, negative on error
 917  **/
 918 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
 919 {
 920         struct device *dev = tx_ring->dev;
 921         int bi_size;
 922
 923         if (!dev)
 924                 return -ENOMEM;
 925
 926         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 927         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 928         if (!tx_ring->tx_bi)
 929                 goto err;
 930
 931         /* round up to nearest 4K */
 932         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 933         /* add u32 for head writeback, align after this takes care of
 934          * guaranteeing this is at least one cache line in size
 935          */
 936         tx_ring->size += sizeof(u32);
 937         tx_ring->size = ALIGN(tx_ring->size, 4096);
 938         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 939                                            &tx_ring->dma, GFP_KERNEL);
 940         if (!tx_ring->desc) {
 941                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 942                          tx_ring->size);
 943                 goto err;
 944         }
 945
 946         tx_ring->next_to_use = 0;
 947         tx_ring->next_to_clean = 0;
 948         return 0;
 949
 950 err:
 951         kfree(tx_ring->tx_bi);
 952         tx_ring->tx_bi = NULL;
 953         return -ENOMEM;
 954 }
 955
 956 /**
 957  * i40e_clean_rx_ring - Free Rx buffers
 958  * @rx_ring: ring to be cleaned
 959  **/
 960 void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
 961 {
 962         struct device *dev = rx_ring->dev;
 963         struct i40e_rx_buffer *rx_bi;
 964         unsigned long bi_size;
 965         u16 i;
 966
 967         /* ring already cleared, nothing to do */
 968         if (!rx_ring->rx_bi)
 969                 return;
 970
 971         if (ring_is_ps_enabled(rx_ring)) {
 972                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
 973
 974                 rx_bi = &rx_ring->rx_bi[0];
 975                 if (rx_bi->hdr_buf) {
 976                         dma_free_coherent(dev,
 977                                           bufsz,
 978                                           rx_bi->hdr_buf,
 979                                           rx_bi->dma);
 980                         for (i = 0; i < rx_ring->count; i++) {
 981                                 rx_bi = &rx_ring->rx_bi[i];
 982                                 rx_bi->dma = 0;
 983                                 rx_bi->hdr_buf = NULL;
 984                         }
 985                 }
 986         }
 987         /* Free all the Rx ring sk_buffs */
 988         for (i = 0; i < rx_ring->count; i++) {
 989                 rx_bi = &rx_ring->rx_bi[i];
 990                 if (rx_bi->dma) {
 991                         dma_unmap_single(dev,
 992                                          rx_bi->dma,
 993                                          rx_ring->rx_buf_len,
 994                                          DMA_FROM_DEVICE);
 995                         rx_bi->dma = 0;
 996                 }
 997                 if (rx_bi->skb) {
 998                         dev_kfree_skb(rx_bi->skb);
 999                         rx_bi->skb = NULL;
1000                 }
1001                 if (rx_bi->page) {
1002                         if (rx_bi->page_dma) {
1003                                 dma_unmap_page(dev,
1004                                                rx_bi->page_dma,
1005                                                PAGE_SIZE / 2,
1006                                                DMA_FROM_DEVICE);
1007                                 rx_bi->page_dma = 0;
1008                         }
1009                         __free_page(rx_bi->page);
1010                         rx_bi->page = NULL;
1011                         rx_bi->page_offset = 0;
1012                 }
1013         }
1014
1015         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1016         memset(rx_ring->rx_bi, 0, bi_size);
1017
1018         /* Zero out the descriptor ring */
1019         memset(rx_ring->desc, 0, rx_ring->size);
1020
1021         rx_ring->next_to_clean = 0;
1022         rx_ring->next_to_use = 0;
1023 }
1024
1025 /**
1026  * i40e_free_rx_resources - Free Rx resources
1027  * @rx_ring: ring to clean the resources from
1028  *
1029  * Free all receive software resources
1030  **/
1031 void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1032 {
1033         i40e_clean_rx_ring(rx_ring);
1034         kfree(rx_ring->rx_bi);
1035         rx_ring->rx_bi = NULL;
1036
1037         if (rx_ring->desc) {
1038                 dma_free_coherent(rx_ring->dev, rx_ring->size,
1039                                   rx_ring->desc, rx_ring->dma);
1040                 rx_ring->desc = NULL;
1041         }
1042 }
1043
1044 /**
1045  * i40e_alloc_rx_headers - allocate rx header buffers
1046  * @rx_ring: ring to alloc buffers
1047  *
1048  * Allocate rx header buffers for the entire ring. As these are static,
1049  * this is only called when setting up a new ring.
1050  **/
1051 void i40e_alloc_rx_headers(struct i40e_ring *rx_ring)
1052 {
1053         struct device *dev = rx_ring->dev;
1054         struct i40e_rx_buffer *rx_bi;
1055         dma_addr_t dma;
1056         void *buffer;
1057         int buf_size;
1058         int i;
1059
1060         if (rx_ring->rx_bi[0].hdr_buf)
1061                 return;
1062         /* Make sure the buffers don't cross cache line boundaries. */
1063         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
1064         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
1065                                     &dma, GFP_KERNEL);
1066         if (!buffer)
1067                 return;
1068         for (i = 0; i < rx_ring->count; i++) {
1069                 rx_bi = &rx_ring->rx_bi[i];
1070                 rx_bi->dma = dma + (i * buf_size);
1071                 rx_bi->hdr_buf = buffer + (i * buf_size);
1072         }
1073 }
1074
1075 /**
1076  * i40e_setup_rx_descriptors - Allocate Rx descriptors
1077  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1078  *
1079  * Returns 0 on success, negative on failure
1080  **/
1081 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1082 {
1083         struct device *dev = rx_ring->dev;
1084         int bi_size;
1085
1086         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1087         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
1088         if (!rx_ring->rx_bi)
1089                 goto err;
1090
1091         u64_stats_init(&rx_ring->syncp);
1092
1093         /* Round up to nearest 4K */
1094         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
1095                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
1096                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1097         rx_ring->size = ALIGN(rx_ring->size, 4096);
1098         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1099                                            &rx_ring->dma, GFP_KERNEL);
1100
1101         if (!rx_ring->desc) {
1102                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1103                          rx_ring->size);
1104                 goto err;
1105         }
1106
1107         rx_ring->next_to_clean = 0;
1108         rx_ring->next_to_use = 0;
1109
1110         return 0;
1111 err:
1112         kfree(rx_ring->rx_bi);
1113         rx_ring->rx_bi = NULL;
1114         return -ENOMEM;
1115 }
1116
1117 /**
1118  * i40e_release_rx_desc - Store the new tail and head values
1119  * @rx_ring: ring to bump
1120  * @val: new head index
1121  **/
1122 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1123 {
1124         rx_ring->next_to_use = val;
1125         /* Force memory writes to complete before letting h/w
1126          * know there are new descriptors to fetch.  (Only
1127          * applicable for weak-ordered memory model archs,
1128          * such as IA-64).
1129          */
1130         wmb();
1131         writel(val, rx_ring->tail);
1132 }
1133
1134 /**
1135  * i40e_alloc_rx_buffers_ps - Replace used receive buffers; packet split
1136  * @rx_ring: ring to place buffers on
1137  * @cleaned_count: number of buffers to replace
1138  **/
1139 void i40e_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
1140 {
1141         u16 i = rx_ring->next_to_use;
1142         union i40e_rx_desc *rx_desc;
1143         struct i40e_rx_buffer *bi;
1144
1145         /* do nothing if no valid netdev defined */
1146         if (!rx_ring->netdev || !cleaned_count)
1147                 return;
1148
1149         while (cleaned_count--) {
1150                 rx_desc = I40E_RX_DESC(rx_ring, i);
1151                 bi = &rx_ring->rx_bi[i];
1152
1153                 if (bi->skb) /* desc is in use */
1154                         goto no_buffers;
1155                 if (!bi->page) {
1156                         bi->page = alloc_page(GFP_ATOMIC);
1157                         if (!bi->page) {
1158                                 rx_ring->rx_stats.alloc_page_failed++;
1159                                 goto no_buffers;
1160                         }
1161                 }
1162
1163                 if (!bi->page_dma) {
1164                         /* use a half page if we're re-using */
1165                         bi->page_offset ^= PAGE_SIZE / 2;
1166                         bi->page_dma = dma_map_page(rx_ring->dev,
1167                                                     bi->page,
1168                                                     bi->page_offset,
1169                                                     PAGE_SIZE / 2,
1170                                                     DMA_FROM_DEVICE);
1171                         if (dma_mapping_error(rx_ring->dev,
1172                                               bi->page_dma)) {
1173                                 rx_ring->rx_stats.alloc_page_failed++;
1174                                 bi->page_dma = 0;
1175                                 goto no_buffers;
1176                         }
1177                 }
1178
1179                 dma_sync_single_range_for_device(rx_ring->dev,
1180                                                  bi->dma,
1181                                                  0,
1182                                                  rx_ring->rx_hdr_len,
1183                                                  DMA_FROM_DEVICE);
1184                 /* Refresh the desc even if buffer_addrs didn't change
1185                  * because each write-back erases this info.
1186                  */
1187                 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1188                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1189                 i++;
1190                 if (i == rx_ring->count)
1191                         i = 0;
1192         }
1193
1194 no_buffers:
1195         if (rx_ring->next_to_use != i)
1196                 i40e_release_rx_desc(rx_ring, i);
1197 }
1198
1199 /**
1200  * i40e_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
1201  * @rx_ring: ring to place buffers on
1202  * @cleaned_count: number of buffers to replace
1203  **/
1204 void i40e_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
1205 {
1206         u16 i = rx_ring->next_to_use;
1207         union i40e_rx_desc *rx_desc;
1208         struct i40e_rx_buffer *bi;
1209         struct sk_buff *skb;
1210
1211         /* do nothing if no valid netdev defined */
1212         if (!rx_ring->netdev || !cleaned_count)
1213                 return;
1214
1215         while (cleaned_count--) {
1216                 rx_desc = I40E_RX_DESC(rx_ring, i);
1217                 bi = &rx_ring->rx_bi[i];
1218                 skb = bi->skb;
1219
1220                 if (!skb) {
1221                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1222                                                         rx_ring->rx_buf_len);
1223                         if (!skb) {
1224                                 rx_ring->rx_stats.alloc_buff_failed++;
1225                                 goto no_buffers;
1226                         }
1227                         /* initialize queue mapping */
1228                         skb_record_rx_queue(skb, rx_ring->queue_index);
1229                         bi->skb = skb;
1230                 }
1231
1232                 if (!bi->dma) {
1233                         bi->dma = dma_map_single(rx_ring->dev,
1234                                                  skb->data,
1235                                                  rx_ring->rx_buf_len,
1236                                                  DMA_FROM_DEVICE);
1237                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1238                                 rx_ring->rx_stats.alloc_buff_failed++;
1239                                 bi->dma = 0;
1240                                 goto no_buffers;
1241                         }
1242                 }
1243
1244                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1245                 rx_desc->read.hdr_addr = 0;
1246                 i++;
1247                 if (i == rx_ring->count)
1248                         i = 0;
1249         }
1250
1251 no_buffers:
1252         if (rx_ring->next_to_use != i)
1253                 i40e_release_rx_desc(rx_ring, i);
1254 }
1255
1256 /**
1257  * i40e_receive_skb - Send a completed packet up the stack
1258  * @rx_ring:  rx ring in play
1259  * @skb: packet to send up
1260  * @vlan_tag: vlan tag for packet
1261  **/
1262 static void i40e_receive_skb(struct i40e_ring *rx_ring,
1263                              struct sk_buff *skb, u16 vlan_tag)
1264 {
1265         struct i40e_q_vector *q_vector = rx_ring->q_vector;
1266         struct i40e_vsi *vsi = rx_ring->vsi;
1267         u64 flags = vsi->back->flags;
1268
1269         if (vlan_tag & VLAN_VID_MASK)
1270                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
1271
1272         if (flags & I40E_FLAG_IN_NETPOLL)
1273                 netif_rx(skb);
1274         else
1275                 napi_gro_receive(&q_vector->napi, skb);
1276 }
1277
1278 /**
1279  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1280  * @vsi: the VSI we care about
1281  * @skb: skb currently being received and modified
1282  * @rx_status: status value of last descriptor in packet
1283  * @rx_error: error value of last descriptor in packet
1284  * @rx_ptype: ptype value of last descriptor in packet
1285  **/
1286 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1287                                     struct sk_buff *skb,
1288                                     u32 rx_status,
1289                                     u32 rx_error,
1290                                     u16 rx_ptype)
1291 {
1292         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
1293         bool ipv4 = false, ipv6 = false;
1294         bool ipv4_tunnel, ipv6_tunnel;
1295         __wsum rx_udp_csum;
1296         struct iphdr *iph;
1297         __sum16 csum;
1298
1299         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
1300                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
1301         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
1302                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
1303
1304         skb->ip_summed = CHECKSUM_NONE;
1305
1306         /* Rx csum enabled and ip headers found? */
1307         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1308                 return;
1309
1310         /* did the hardware decode the packet and checksum? */
1311         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1312                 return;
1313
1314         /* both known and outer_ip must be set for the below code to work */
1315         if (!(decoded.known && decoded.outer_ip))
1316                 return;
1317
1318         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1319             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
1320                 ipv4 = true;
1321         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1322                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
1323                 ipv6 = true;
1324
1325         if (ipv4 &&
1326             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1327                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1328                 goto checksum_fail;
1329
1330         /* likely incorrect csum if alternate IP extension headers found */
1331         if (ipv6 &&
1332             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1333                 /* don't increment checksum err here, non-fatal err */
1334                 return;
1335
1336         /* there was some L4 error, count error and punt packet to the stack */
1337         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
1338                 goto checksum_fail;
1339
1340         /* handle packets that were not able to be checksummed due
1341          * to arrival speed, in this case the stack can compute
1342          * the csum.
1343          */
1344         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
1345                 return;
1346
1347         /* If VXLAN traffic has an outer UDPv4 checksum we need to check
1348          * it in the driver, hardware does not do it for us.
1349          * Since L3L4P bit was set we assume a valid IHL value (>=5)
1350          * so the total length of IPv4 header is IHL*4 bytes
1351          * The UDP_0 bit *may* bet set if the *inner* header is UDP
1352          */
1353         if (!(vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE) &&
1354             (ipv4_tunnel)) {
1355                 skb->transport_header = skb->mac_header +
1356                                         sizeof(struct ethhdr) +
1357                                         (ip_hdr(skb)->ihl * 4);
1358
1359                 /* Add 4 bytes for VLAN tagged packets */
1360                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
1361                                           skb->protocol == htons(ETH_P_8021AD))
1362                                           ? VLAN_HLEN : 0;
1363
1364                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
1365                     (udp_hdr(skb)->check != 0)) {
1366                         rx_udp_csum = udp_csum(skb);
1367                         iph = ip_hdr(skb);
1368                         csum = csum_tcpudp_magic(
1369                                         iph->saddr, iph->daddr,
1370                                         (skb->len - skb_transport_offset(skb)),
1371                                         IPPROTO_UDP, rx_udp_csum);
1372
1373                         if (udp_hdr(skb)->check != csum)
1374                                 goto checksum_fail;
1375
1376                 } /* else its GRE and so no outer UDP header */
1377         }
1378
1379         skb->ip_summed = CHECKSUM_UNNECESSARY;
1380         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
1381
1382         return;
1383
1384 checksum_fail:
1385         vsi->back->hw_csum_rx_error++;
1386 }
1387
1388 /**
1389  * i40e_rx_hash - returns the hash value from the Rx descriptor
1390  * @ring: descriptor ring
1391  * @rx_desc: specific descriptor
1392  **/
1393 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
1394                                union i40e_rx_desc *rx_desc)
1395 {
1396         const __le64 rss_mask =
1397                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1398                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1399
1400         if ((ring->netdev->features & NETIF_F_RXHASH) &&
1401             (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
1402                 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1403         else
1404                 return 0;
1405 }
1406
1407 /**
1408  * i40e_ptype_to_hash - get a hash type
1409  * @ptype: the ptype value from the descriptor
1410  *
1411  * Returns a hash type to be used by skb_set_hash
1412  **/
1413 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
1414 {
1415         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1416
1417         if (!decoded.known)
1418                 return PKT_HASH_TYPE_NONE;
1419
1420         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1421             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1422                 return PKT_HASH_TYPE_L4;
1423         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1424                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1425                 return PKT_HASH_TYPE_L3;
1426         else
1427                 return PKT_HASH_TYPE_L2;
1428 }
1429
1430 /**
1431  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
1432  * @rx_ring:  rx ring to clean
1433  * @budget:   how many cleans we're allowed
1434  *
1435  * Returns true if there's any budget left (e.g. the clean is finished)
1436  **/
1437 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
1438 {
1439         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1440         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
1441         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1442         const int current_node = numa_node_id();
1443         struct i40e_vsi *vsi = rx_ring->vsi;
1444         u16 i = rx_ring->next_to_clean;
1445         union i40e_rx_desc *rx_desc;
1446         u32 rx_error, rx_status;
1447         u8 rx_ptype;
1448         u64 qword;
1449
1450         if (budget <= 0)
1451                 return 0;
1452
1453         do {
1454                 struct i40e_rx_buffer *rx_bi;
1455                 struct sk_buff *skb;
1456                 u16 vlan_tag;
1457                 /* return some buffers to hardware, one at a time is too slow */
1458                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1459                         i40e_alloc_rx_buffers_ps(rx_ring, cleaned_count);
1460                         cleaned_count = 0;
1461                 }
1462
1463                 i = rx_ring->next_to_clean;
1464                 rx_desc = I40E_RX_DESC(rx_ring, i);
1465                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1466                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1467                         I40E_RXD_QW1_STATUS_SHIFT;
1468
1469                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1470                         break;
1471
1472                 /* This memory barrier is needed to keep us from reading
1473                  * any other fields out of the rx_desc until we know the
1474                  * DD bit is set.
1475                  */
1476                 dma_rmb();
1477                 if (i40e_rx_is_programming_status(qword)) {
1478                         i40e_clean_programming_status(rx_ring, rx_desc);
1479                         I40E_RX_INCREMENT(rx_ring, i);
1480                         continue;
1481                 }
1482                 rx_bi = &rx_ring->rx_bi[i];
1483                 skb = rx_bi->skb;
1484                 if (likely(!skb)) {
1485                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1486                                                         rx_ring->rx_hdr_len);
1487                         if (!skb) {
1488                                 rx_ring->rx_stats.alloc_buff_failed++;
1489                                 break;
1490                         }
1491
1492                         /* initialize queue mapping */
1493                         skb_record_rx_queue(skb, rx_ring->queue_index);
1494                         /* we are reusing so sync this buffer for CPU use */
1495                         dma_sync_single_range_for_cpu(rx_ring->dev,
1496                                                       rx_bi->dma,
1497                                                       0,
1498                                                       rx_ring->rx_hdr_len,
1499                                                       DMA_FROM_DEVICE);
1500                 }
1501                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1502                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1503                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1504                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1505                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1506                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1507
1508                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1509                            I40E_RXD_QW1_ERROR_SHIFT;
1510                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1511                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1512
1513                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1514                            I40E_RXD_QW1_PTYPE_SHIFT;
1515                 prefetch(rx_bi->page);
1516                 rx_bi->skb = NULL;
1517                 cleaned_count++;
1518                 if (rx_hbo || rx_sph) {
1519                         int len;
1520                         if (rx_hbo)
1521                                 len = I40E_RX_HDR_SIZE;
1522                         else
1523                                 len = rx_header_len;
1524                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1525                 } else if (skb->len == 0) {
1526                         int len;
1527
1528                         len = (rx_packet_len > skb_headlen(skb) ?
1529                                 skb_headlen(skb) : rx_packet_len);
1530                         memcpy(__skb_put(skb, len),
1531                                rx_bi->page + rx_bi->page_offset,
1532                                len);
1533                         rx_bi->page_offset += len;
1534                         rx_packet_len -= len;
1535                 }
1536
1537                 /* Get the rest of the data if this was a header split */
1538                 if (rx_packet_len) {
1539                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1540                                            rx_bi->page,
1541                                            rx_bi->page_offset,
1542                                            rx_packet_len);
1543
1544                         skb->len += rx_packet_len;
1545                         skb->data_len += rx_packet_len;
1546                         skb->truesize += rx_packet_len;
1547
1548                         if ((page_count(rx_bi->page) == 1) &&
1549                             (page_to_nid(rx_bi->page) == current_node))
1550                                 get_page(rx_bi->page);
1551                         else
1552                                 rx_bi->page = NULL;
1553
1554                         dma_unmap_page(rx_ring->dev,
1555                                        rx_bi->page_dma,
1556                                        PAGE_SIZE / 2,
1557                                        DMA_FROM_DEVICE);
1558                         rx_bi->page_dma = 0;
1559                 }
1560                 I40E_RX_INCREMENT(rx_ring, i);
1561
1562                 if (unlikely(
1563                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1564                         struct i40e_rx_buffer *next_buffer;
1565
1566                         next_buffer = &rx_ring->rx_bi[i];
1567                         next_buffer->skb = skb;
1568                         rx_ring->rx_stats.non_eop_descs++;
1569                         continue;
1570                 }
1571
1572                 /* ERR_MASK will only have valid bits if EOP set */
1573                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1574                         dev_kfree_skb_any(skb);
1575                         continue;
1576                 }
1577
1578                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1579                              i40e_ptype_to_hash(rx_ptype));
1580                 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1581                         i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1582                                            I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1583                                            I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1584                         rx_ring->last_rx_timestamp = jiffies;
1585                 }
1586
1587                 /* probably a little skewed due to removing CRC */
1588                 total_rx_bytes += skb->len;
1589                 total_rx_packets++;
1590
1591                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1592
1593                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1594
1595                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1596                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1597                          : 0;
1598 #ifdef I40E_FCOE
1599                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1600                         dev_kfree_skb_any(skb);
1601                         continue;
1602                 }
1603 #endif
1604                 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
1605                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1606
1607                 rx_desc->wb.qword1.status_error_len = 0;
1608
1609         } while (likely(total_rx_packets < budget));
1610
1611         u64_stats_update_begin(&rx_ring->syncp);
1612         rx_ring->stats.packets += total_rx_packets;
1613         rx_ring->stats.bytes += total_rx_bytes;
1614         u64_stats_update_end(&rx_ring->syncp);
1615         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1616         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1617
1618         return total_rx_packets;
1619 }
1620
1621 /**
1622  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1623  * @rx_ring:  rx ring to clean
1624  * @budget:   how many cleans we're allowed
1625  *
1626  * Returns number of packets cleaned
1627  **/
1628 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1629 {
1630         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1631         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1632         struct i40e_vsi *vsi = rx_ring->vsi;
1633         union i40e_rx_desc *rx_desc;
1634         u32 rx_error, rx_status;
1635         u16 rx_packet_len;
1636         u8 rx_ptype;
1637         u64 qword;
1638         u16 i;
1639
1640         do {
1641                 struct i40e_rx_buffer *rx_bi;
1642                 struct sk_buff *skb;
1643                 u16 vlan_tag;
1644                 /* return some buffers to hardware, one at a time is too slow */
1645                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1646                         i40e_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1647                         cleaned_count = 0;
1648                 }
1649
1650                 i = rx_ring->next_to_clean;
1651                 rx_desc = I40E_RX_DESC(rx_ring, i);
1652                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1653                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1654                         I40E_RXD_QW1_STATUS_SHIFT;
1655
1656                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1657                         break;
1658
1659                 /* This memory barrier is needed to keep us from reading
1660                  * any other fields out of the rx_desc until we know the
1661                  * DD bit is set.
1662                  */
1663                 dma_rmb();
1664
1665                 if (i40e_rx_is_programming_status(qword)) {
1666                         i40e_clean_programming_status(rx_ring, rx_desc);
1667                         I40E_RX_INCREMENT(rx_ring, i);
1668                         continue;
1669                 }
1670                 rx_bi = &rx_ring->rx_bi[i];
1671                 skb = rx_bi->skb;
1672                 prefetch(skb->data);
1673
1674                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1675                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1676
1677                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1678                            I40E_RXD_QW1_ERROR_SHIFT;
1679                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1680
1681                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1682                            I40E_RXD_QW1_PTYPE_SHIFT;
1683                 rx_bi->skb = NULL;
1684                 cleaned_count++;
1685
1686                 /* Get the header and possibly the whole packet
1687                  * If this is an skb from previous receive dma will be 0
1688                  */
1689                 skb_put(skb, rx_packet_len);
1690                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1691                                  DMA_FROM_DEVICE);
1692                 rx_bi->dma = 0;
1693
1694                 I40E_RX_INCREMENT(rx_ring, i);
1695
1696                 if (unlikely(
1697                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1698                         rx_ring->rx_stats.non_eop_descs++;
1699                         continue;
1700                 }
1701
1702                 /* ERR_MASK will only have valid bits if EOP set */
1703                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1704                         dev_kfree_skb_any(skb);
1705                         /* TODO: shouldn't we increment a counter indicating the
1706                          * drop?
1707                          */
1708                         continue;
1709                 }
1710
1711                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1712                              i40e_ptype_to_hash(rx_ptype));
1713                 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1714                         i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1715                                            I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1716                                            I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1717                         rx_ring->last_rx_timestamp = jiffies;
1718                 }
1719
1720                 /* probably a little skewed due to removing CRC */
1721                 total_rx_bytes += skb->len;
1722                 total_rx_packets++;
1723
1724                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1725
1726                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1727
1728                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1729                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1730                          : 0;
1731 #ifdef I40E_FCOE
1732                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1733                         dev_kfree_skb_any(skb);
1734                         continue;
1735                 }
1736 #endif
1737                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1738
1739                 rx_desc->wb.qword1.status_error_len = 0;
1740         } while (likely(total_rx_packets < budget));
1741
1742         u64_stats_update_begin(&rx_ring->syncp);
1743         rx_ring->stats.packets += total_rx_packets;
1744         rx_ring->stats.bytes += total_rx_bytes;
1745         u64_stats_update_end(&rx_ring->syncp);
1746         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1747         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1748
1749         return total_rx_packets;
1750 }
1751
1752 /**
1753  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1754  * @vsi: the VSI we care about
1755  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1756  *
1757  **/
1758 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1759                                           struct i40e_q_vector *q_vector)
1760 {
1761         struct i40e_hw *hw = &vsi->back->hw;
1762         u16 old_itr;
1763         int vector;
1764         u32 val;
1765
1766         vector = (q_vector->v_idx + vsi->base_vector);
1767         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1768                 old_itr = q_vector->rx.itr;
1769                 i40e_set_new_dynamic_itr(&q_vector->rx);
1770                 if (old_itr != q_vector->rx.itr) {
1771                         val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1772                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1773                         (I40E_RX_ITR <<
1774                                 I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1775                         (q_vector->rx.itr <<
1776                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);
1777                 } else {
1778                         val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1779                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1780                         (I40E_ITR_NONE <<
1781                                 I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1782                 }
1783                 if (!test_bit(__I40E_DOWN, &vsi->state))
1784                         wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1785         } else {
1786                 i40e_irq_dynamic_enable(vsi,
1787                                         q_vector->v_idx + vsi->base_vector);
1788         }
1789         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1790                 old_itr = q_vector->tx.itr;
1791                 i40e_set_new_dynamic_itr(&q_vector->tx);
1792                 if (old_itr != q_vector->tx.itr) {
1793                         val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1794                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1795                                 (I40E_TX_ITR <<
1796                                    I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1797                                 (q_vector->tx.itr <<
1798                                    I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);
1799                 } else {
1800                         val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1801                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1802                                 (I40E_ITR_NONE <<
1803                                    I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1804                 }
1805                 if (!test_bit(__I40E_DOWN, &vsi->state))
1806                         wr32(hw, I40E_PFINT_DYN_CTLN(q_vector->v_idx +
1807                               vsi->base_vector - 1), val);
1808         } else {
1809                 i40e_irq_dynamic_enable(vsi,
1810                                         q_vector->v_idx + vsi->base_vector);
1811         }
1812 }
1813
1814 /**
1815  * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
1816  * @napi: napi struct with our devices info in it
1817  * @budget: amount of work driver is allowed to do this pass, in packets
1818  *
1819  * This function will clean all queues associated with a q_vector.
1820  *
1821  * Returns the amount of work done
1822  **/
1823 int i40e_napi_poll(struct napi_struct *napi, int budget)
1824 {
1825         struct i40e_q_vector *q_vector =
1826                                container_of(napi, struct i40e_q_vector, napi);
1827         struct i40e_vsi *vsi = q_vector->vsi;
1828         struct i40e_ring *ring;
1829         bool clean_complete = true;
1830         bool arm_wb = false;
1831         int budget_per_ring;
1832         int cleaned;
1833
1834         if (test_bit(__I40E_DOWN, &vsi->state)) {
1835                 napi_complete(napi);
1836                 return 0;
1837         }
1838
1839         /* Since the actual Tx work is minimal, we can give the Tx a larger
1840          * budget and be more aggressive about cleaning up the Tx descriptors.
1841          */
1842         i40e_for_each_ring(ring, q_vector->tx) {
1843                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1844                 arm_wb |= ring->arm_wb;
1845                 ring->arm_wb = false;
1846         }
1847
1848         /* We attempt to distribute budget to each Rx queue fairly, but don't
1849          * allow the budget to go below 1 because that would exit polling early.
1850          */
1851         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1852
1853         i40e_for_each_ring(ring, q_vector->rx) {
1854                 if (ring_is_ps_enabled(ring))
1855                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1856                 else
1857                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1858                 /* if we didn't clean as many as budgeted, we must be done */
1859                 clean_complete &= (budget_per_ring != cleaned);
1860         }
1861
1862         /* If work not completed, return budget and polling will return */
1863         if (!clean_complete) {
1864                 if (arm_wb)
1865                         i40e_force_wb(vsi, q_vector);
1866                 return budget;
1867         }
1868
1869         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1870                 q_vector->arm_wb_state = false;
1871
1872         /* Work is done so exit the polling mode and re-enable the interrupt */
1873         napi_complete(napi);
1874         if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
1875                 i40e_update_enable_itr(vsi, q_vector);
1876         } else { /* Legacy mode */
1877                 struct i40e_hw *hw = &vsi->back->hw;
1878                 /* We re-enable the queue 0 cause, but
1879                  * don't worry about dynamic_enable
1880                  * because we left it on for the other
1881                  * possible interrupts during napi
1882                  */
1883                 u32 qval = rd32(hw, I40E_QINT_RQCTL(0)) |
1884                            I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1885
1886                 wr32(hw, I40E_QINT_RQCTL(0), qval);
1887                 qval = rd32(hw, I40E_QINT_TQCTL(0)) |
1888                        I40E_QINT_TQCTL_CAUSE_ENA_MASK;
1889                 wr32(hw, I40E_QINT_TQCTL(0), qval);
1890                 i40e_irq_dynamic_enable_icr0(vsi->back);
1891         }
1892         return 0;
1893 }
1894
1895 /**
1896  * i40e_atr - Add a Flow Director ATR filter
1897  * @tx_ring:  ring to add programming descriptor to
1898  * @skb:      send buffer
1899  * @tx_flags: send tx flags
1900  * @protocol: wire protocol
1901  **/
1902 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
1903                      u32 tx_flags, __be16 protocol)
1904 {
1905         struct i40e_filter_program_desc *fdir_desc;
1906         struct i40e_pf *pf = tx_ring->vsi->back;
1907         union {
1908                 unsigned char *network;
1909                 struct iphdr *ipv4;
1910                 struct ipv6hdr *ipv6;
1911         } hdr;
1912         struct tcphdr *th;
1913         unsigned int hlen;
1914         u32 flex_ptype, dtype_cmd;
1915         u16 i;
1916
1917         /* make sure ATR is enabled */
1918         if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
1919                 return;
1920
1921         if ((pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1922                 return;
1923
1924         /* if sampling is disabled do nothing */
1925         if (!tx_ring->atr_sample_rate)
1926                 return;
1927
1928         if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
1929                 return;
1930
1931         if (!(tx_flags & I40E_TX_FLAGS_VXLAN_TUNNEL)) {
1932                 /* snag network header to get L4 type and address */
1933                 hdr.network = skb_network_header(skb);
1934
1935                 /* Currently only IPv4/IPv6 with TCP is supported
1936                  * access ihl as u8 to avoid unaligned access on ia64
1937                  */
1938                 if (tx_flags & I40E_TX_FLAGS_IPV4)
1939                         hlen = (hdr.network[0] & 0x0F) << 2;
1940                 else if (protocol == htons(ETH_P_IPV6))
1941                         hlen = sizeof(struct ipv6hdr);
1942                 else
1943                         return;
1944         } else {
1945                 hdr.network = skb_inner_network_header(skb);
1946                 hlen = skb_inner_network_header_len(skb);
1947         }
1948
1949         /* Currently only IPv4/IPv6 with TCP is supported
1950          * Note: tx_flags gets modified to reflect inner protocols in
1951          * tx_enable_csum function if encap is enabled.
1952          */
1953         if ((tx_flags & I40E_TX_FLAGS_IPV4) &&
1954             (hdr.ipv4->protocol != IPPROTO_TCP))
1955                 return;
1956         else if ((tx_flags & I40E_TX_FLAGS_IPV6) &&
1957                  (hdr.ipv6->nexthdr != IPPROTO_TCP))
1958                 return;
1959
1960         th = (struct tcphdr *)(hdr.network + hlen);
1961
1962         /* Due to lack of space, no more new filters can be programmed */
1963         if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1964                 return;
1965         if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) {
1966                 /* HW ATR eviction will take care of removing filters on FIN
1967                  * and RST packets.
1968                  */
1969                 if (th->fin || th->rst)
1970                         return;
1971         }
1972
1973         tx_ring->atr_count++;
1974
1975         /* sample on all syn/fin/rst packets or once every atr sample rate */
1976         if (!th->fin &&
1977             !th->syn &&
1978             !th->rst &&
1979             (tx_ring->atr_count < tx_ring->atr_sample_rate))
1980                 return;
1981
1982         tx_ring->atr_count = 0;
1983
1984         /* grab the next descriptor */
1985         i = tx_ring->next_to_use;
1986         fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
1987
1988         i++;
1989         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1990
1991         flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1992                       I40E_TXD_FLTR_QW0_QINDEX_MASK;
1993         flex_ptype |= (protocol == htons(ETH_P_IP)) ?
1994                       (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
1995                        I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
1996                       (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
1997                        I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
1998
1999         flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2000
2001         dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2002
2003         dtype_cmd |= (th->fin || th->rst) ?
2004                      (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2005                       I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2006                      (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2007                       I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2008
2009         dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2010                      I40E_TXD_FLTR_QW1_DEST_SHIFT;
2011
2012         dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2013                      I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2014
2015         dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2016         if (!(tx_flags & I40E_TX_FLAGS_VXLAN_TUNNEL))
2017                 dtype_cmd |=
2018                         ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
2019                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2020                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2021         else
2022                 dtype_cmd |=
2023                         ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
2024                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2025                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2026
2027         if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE)
2028                 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2029
2030         fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
2031         fdir_desc->rsvd = cpu_to_le32(0);
2032         fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
2033         fdir_desc->fd_id = cpu_to_le32(0);
2034 }
2035
2036 /**
2037  * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2038  * @skb:     send buffer
2039  * @tx_ring: ring to send buffer on
2040  * @flags:   the tx flags to be set
2041  *
2042  * Checks the skb and set up correspondingly several generic transmit flags
2043  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2044  *
2045  * Returns error code indicate the frame should be dropped upon error and the
2046  * otherwise  returns 0 to indicate the flags has been set properly.
2047  **/
2048 #ifdef I40E_FCOE
2049 inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2050                                       struct i40e_ring *tx_ring,
2051                                       u32 *flags)
2052 #else
2053 static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2054                                              struct i40e_ring *tx_ring,
2055                                              u32 *flags)
2056 #endif
2057 {
2058         __be16 protocol = skb->protocol;
2059         u32  tx_flags = 0;
2060
2061         if (protocol == htons(ETH_P_8021Q) &&
2062             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
2063                 /* When HW VLAN acceleration is turned off by the user the
2064                  * stack sets the protocol to 8021q so that the driver
2065                  * can take any steps required to support the SW only
2066                  * VLAN handling.  In our case the driver doesn't need
2067                  * to take any further steps so just set the protocol
2068                  * to the encapsulated ethertype.
2069                  */
2070                 skb->protocol = vlan_get_protocol(skb);
2071                 goto out;
2072         }
2073
2074         /* if we have a HW VLAN tag being added, default to the HW one */
2075         if (skb_vlan_tag_present(skb)) {
2076                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
2077                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2078         /* else if it is a SW VLAN, check the next protocol and store the tag */
2079         } else if (protocol == htons(ETH_P_8021Q)) {
2080                 struct vlan_hdr *vhdr, _vhdr;
2081                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2082                 if (!vhdr)
2083                         return -EINVAL;
2084
2085                 protocol = vhdr->h_vlan_encapsulated_proto;
2086                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2087                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2088         }
2089
2090         if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2091                 goto out;
2092
2093         /* Insert 802.1p priority into VLAN header */
2094         if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2095             (skb->priority != TC_PRIO_CONTROL)) {
2096                 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2097                 tx_flags |= (skb->priority & 0x7) <<
2098                                 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2099                 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2100                         struct vlan_ethhdr *vhdr;
2101                         int rc;
2102
2103                         rc = skb_cow_head(skb, 0);
2104                         if (rc < 0)
2105                                 return rc;
2106                         vhdr = (struct vlan_ethhdr *)skb->data;
2107                         vhdr->h_vlan_TCI = htons(tx_flags >>
2108                                                  I40E_TX_FLAGS_VLAN_SHIFT);
2109                 } else {
2110                         tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2111                 }
2112         }
2113
2114 out:
2115         *flags = tx_flags;
2116         return 0;
2117 }
2118
2119 /**
2120  * i40e_tso - set up the tso context descriptor
2121  * @tx_ring:  ptr to the ring to send
2122  * @skb:      ptr to the skb we're sending
2123  * @hdr_len:  ptr to the size of the packet header
2124  * @cd_tunneling: ptr to context descriptor bits
2125  *
2126  * Returns 0 if no TSO can happen, 1 if tso is going, or error
2127  **/
2128 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
2129                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss,
2130                     u32 *cd_tunneling)
2131 {
2132         u32 cd_cmd, cd_tso_len, cd_mss;
2133         struct ipv6hdr *ipv6h;
2134         struct tcphdr *tcph;
2135         struct iphdr *iph;
2136         u32 l4len;
2137         int err;
2138
2139         if (!skb_is_gso(skb))
2140                 return 0;
2141
2142         err = skb_cow_head(skb, 0);
2143         if (err < 0)
2144                 return err;
2145
2146         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
2147         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
2148
2149         if (iph->version == 4) {
2150                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2151                 iph->tot_len = 0;
2152                 iph->check = 0;
2153                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
2154                                                  0, IPPROTO_TCP, 0);
2155         } else if (ipv6h->version == 6) {
2156                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2157                 ipv6h->payload_len = 0;
2158                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
2159                                                0, IPPROTO_TCP, 0);
2160         }
2161
2162         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
2163         *hdr_len = (skb->encapsulation
2164                     ? (skb_inner_transport_header(skb) - skb->data)
2165                     : skb_transport_offset(skb)) + l4len;
2166
2167         /* find the field values */
2168         cd_cmd = I40E_TX_CTX_DESC_TSO;
2169         cd_tso_len = skb->len - *hdr_len;
2170         cd_mss = skb_shinfo(skb)->gso_size;
2171         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
2172                                 ((u64)cd_tso_len <<
2173                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2174                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
2175         return 1;
2176 }
2177
2178 /**
2179  * i40e_tsyn - set up the tsyn context descriptor
2180  * @tx_ring:  ptr to the ring to send
2181  * @skb:      ptr to the skb we're sending
2182  * @tx_flags: the collected send information
2183  *
2184  * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
2185  **/
2186 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
2187                      u32 tx_flags, u64 *cd_type_cmd_tso_mss)
2188 {
2189         struct i40e_pf *pf;
2190
2191         if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
2192                 return 0;
2193
2194         /* Tx timestamps cannot be sampled when doing TSO */
2195         if (tx_flags & I40E_TX_FLAGS_TSO)
2196                 return 0;
2197
2198         /* only timestamp the outbound packet if the user has requested it and
2199          * we are not already transmitting a packet to be timestamped
2200          */
2201         pf = i40e_netdev_to_pf(tx_ring->netdev);
2202         if (!(pf->flags & I40E_FLAG_PTP))
2203                 return 0;
2204
2205         if (pf->ptp_tx &&
2206             !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) {
2207                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2208                 pf->ptp_tx_skb = skb_get(skb);
2209         } else {
2210                 return 0;
2211         }
2212
2213         *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
2214                                 I40E_TXD_CTX_QW1_CMD_SHIFT;
2215
2216         return 1;
2217 }
2218
2219 /**
2220  * i40e_tx_enable_csum - Enable Tx checksum offloads
2221  * @skb: send buffer
2222  * @tx_flags: pointer to Tx flags currently set
2223  * @td_cmd: Tx descriptor command bits to set
2224  * @td_offset: Tx descriptor header offsets to set
2225  * @cd_tunneling: ptr to context desc bits
2226  **/
2227 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
2228                                 u32 *td_cmd, u32 *td_offset,
2229                                 struct i40e_ring *tx_ring,
2230                                 u32 *cd_tunneling)
2231 {
2232         struct ipv6hdr *this_ipv6_hdr;
2233         unsigned int this_tcp_hdrlen;
2234         struct iphdr *this_ip_hdr;
2235         u32 network_hdr_len;
2236         u8 l4_hdr = 0;
2237         struct udphdr *oudph;
2238         struct iphdr *oiph;
2239         u32 l4_tunnel = 0;
2240
2241         if (skb->encapsulation) {
2242                 switch (ip_hdr(skb)->protocol) {
2243                 case IPPROTO_UDP:
2244                         oudph = udp_hdr(skb);
2245                         oiph = ip_hdr(skb);
2246                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
2247                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
2248                         break;
2249                 case IPPROTO_GRE:
2250                         l4_tunnel = I40E_TXD_CTX_GRE_TUNNELING;
2251                         break;
2252                 default:
2253                         return;
2254                 }
2255                 network_hdr_len = skb_inner_network_header_len(skb);
2256                 this_ip_hdr = inner_ip_hdr(skb);
2257                 this_ipv6_hdr = inner_ipv6_hdr(skb);
2258                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
2259
2260                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
2261                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
2262                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
2263                                 ip_hdr(skb)->check = 0;
2264                         } else {
2265                                 *cd_tunneling |=
2266                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
2267                         }
2268                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
2269                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
2270                         if (*tx_flags & I40E_TX_FLAGS_TSO)
2271                                 ip_hdr(skb)->check = 0;
2272                 }
2273
2274                 /* Now set the ctx descriptor fields */
2275                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
2276                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
2277                                    l4_tunnel                             |
2278                                    ((skb_inner_network_offset(skb) -
2279                                         skb_transport_offset(skb)) >> 1) <<
2280                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
2281                 if (this_ip_hdr->version == 6) {
2282                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
2283                         *tx_flags |= I40E_TX_FLAGS_IPV6;
2284                 }
2285                 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
2286                     (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
2287                     (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
2288                         oudph->check = ~csum_tcpudp_magic(oiph->saddr,
2289                                         oiph->daddr,
2290                                         (skb->len - skb_transport_offset(skb)),
2291                                         IPPROTO_UDP, 0);
2292                         *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
2293                 }
2294         } else {
2295                 network_hdr_len = skb_network_header_len(skb);
2296                 this_ip_hdr = ip_hdr(skb);
2297                 this_ipv6_hdr = ipv6_hdr(skb);
2298                 this_tcp_hdrlen = tcp_hdrlen(skb);
2299         }
2300
2301         /* Enable IP checksum offloads */
2302         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
2303                 l4_hdr = this_ip_hdr->protocol;
2304                 /* the stack computes the IP header already, the only time we
2305                  * need the hardware to recompute it is in the case of TSO.
2306                  */
2307                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
2308                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
2309                         this_ip_hdr->check = 0;
2310                 } else {
2311                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
2312                 }
2313                 /* Now set the td_offset for IP header length */
2314                 *td_offset = (network_hdr_len >> 2) <<
2315                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2316         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
2317                 l4_hdr = this_ipv6_hdr->nexthdr;
2318                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
2319                 /* Now set the td_offset for IP header length */
2320                 *td_offset = (network_hdr_len >> 2) <<
2321                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2322         }
2323         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
2324         *td_offset |= (skb_network_offset(skb) >> 1) <<
2325                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
2326
2327         /* Enable L4 checksum offloads */
2328         switch (l4_hdr) {
2329         case IPPROTO_TCP:
2330                 /* enable checksum offloads */
2331                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
2332                 *td_offset |= (this_tcp_hdrlen >> 2) <<
2333                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2334                 break;
2335         case IPPROTO_SCTP:
2336                 /* enable SCTP checksum offload */
2337                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
2338                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
2339                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2340                 break;
2341         case IPPROTO_UDP:
2342                 /* enable UDP checksum offload */
2343                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
2344                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
2345                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2346                 break;
2347         default:
2348                 break;
2349         }
2350 }
2351
2352 /**
2353  * i40e_create_tx_ctx Build the Tx context descriptor
2354  * @tx_ring:  ring to create the descriptor on
2355  * @cd_type_cmd_tso_mss: Quad Word 1
2356  * @cd_tunneling: Quad Word 0 - bits 0-31
2357  * @cd_l2tag2: Quad Word 0 - bits 32-63
2358  **/
2359 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
2360                                const u64 cd_type_cmd_tso_mss,
2361                                const u32 cd_tunneling, const u32 cd_l2tag2)
2362 {
2363         struct i40e_tx_context_desc *context_desc;
2364         int i = tx_ring->next_to_use;
2365
2366         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
2367             !cd_tunneling && !cd_l2tag2)
2368                 return;
2369
2370         /* grab the next descriptor */
2371         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
2372
2373         i++;
2374         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2375
2376         /* cpu_to_le32 and assign to struct fields */
2377         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
2378         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
2379         context_desc->rsvd = cpu_to_le16(0);
2380         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
2381 }
2382
2383 /**
2384  * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
2385  * @tx_ring: the ring to be checked
2386  * @size:    the size buffer we want to assure is available
2387  *
2388  * Returns -EBUSY if a stop is needed, else 0
2389  **/
2390 static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2391 {
2392         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
2393         /* Memory barrier before checking head and tail */
2394         smp_mb();
2395
2396         /* Check again in a case another CPU has just made room available. */
2397         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
2398                 return -EBUSY;
2399
2400         /* A reprieve! - use start_queue because it doesn't call schedule */
2401         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
2402         ++tx_ring->tx_stats.restart_queue;
2403         return 0;
2404 }
2405
2406 /**
2407  * i40e_maybe_stop_tx - 1st level check for tx stop conditions
2408  * @tx_ring: the ring to be checked
2409  * @size:    the size buffer we want to assure is available
2410  *
2411  * Returns 0 if stop is not needed
2412  **/
2413 #ifdef I40E_FCOE
2414 inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2415 #else
2416 static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2417 #endif
2418 {
2419         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
2420                 return 0;
2421         return __i40e_maybe_stop_tx(tx_ring, size);
2422 }
2423
2424 /**
2425  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
2426  * @skb:      send buffer
2427  * @tx_flags: collected send information
2428  *
2429  * Note: Our HW can't scatter-gather more than 8 fragments to build
2430  * a packet on the wire and so we need to figure out the cases where we
2431  * need to linearize the skb.
2432  **/
2433 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
2434 {
2435         struct skb_frag_struct *frag;
2436         bool linearize = false;
2437         unsigned int size = 0;
2438         u16 num_frags;
2439         u16 gso_segs;
2440
2441         num_frags = skb_shinfo(skb)->nr_frags;
2442         gso_segs = skb_shinfo(skb)->gso_segs;
2443
2444         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
2445                 u16 j = 0;
2446
2447                 if (num_frags < (I40E_MAX_BUFFER_TXD))
2448                         goto linearize_chk_done;
2449                 /* try the simple math, if we have too many frags per segment */
2450                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
2451                     I40E_MAX_BUFFER_TXD) {
2452                         linearize = true;
2453                         goto linearize_chk_done;
2454                 }
2455                 frag = &skb_shinfo(skb)->frags[0];
2456                 /* we might still have more fragments per segment */
2457                 do {
2458                         size += skb_frag_size(frag);
2459                         frag++; j++;
2460                         if ((size >= skb_shinfo(skb)->gso_size) &&
2461                             (j < I40E_MAX_BUFFER_TXD)) {
2462                                 size = (size % skb_shinfo(skb)->gso_size);
2463                                 j = (size) ? 1 : 0;
2464                         }
2465                         if (j == I40E_MAX_BUFFER_TXD) {
2466                                 linearize = true;
2467                                 break;
2468                         }
2469                         num_frags--;
2470                 } while (num_frags);
2471         } else {
2472                 if (num_frags >= I40E_MAX_BUFFER_TXD)
2473                         linearize = true;
2474         }
2475
2476 linearize_chk_done:
2477         return linearize;
2478 }
2479
2480 /**
2481  * i40e_tx_map - Build the Tx descriptor
2482  * @tx_ring:  ring to send buffer on
2483  * @skb:      send buffer
2484  * @first:    first buffer info buffer to use
2485  * @tx_flags: collected send information
2486  * @hdr_len:  size of the packet header
2487  * @td_cmd:   the command field in the descriptor
2488  * @td_offset: offset for checksum or crc
2489  **/
2490 #ifdef I40E_FCOE
2491 inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2492                         struct i40e_tx_buffer *first, u32 tx_flags,
2493                         const u8 hdr_len, u32 td_cmd, u32 td_offset)
2494 #else
2495 static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2496                                struct i40e_tx_buffer *first, u32 tx_flags,
2497                                const u8 hdr_len, u32 td_cmd, u32 td_offset)
2498 #endif
2499 {
2500         unsigned int data_len = skb->data_len;
2501         unsigned int size = skb_headlen(skb);
2502         struct skb_frag_struct *frag;
2503         struct i40e_tx_buffer *tx_bi;
2504         struct i40e_tx_desc *tx_desc;
2505         u16 i = tx_ring->next_to_use;
2506         u32 td_tag = 0;
2507         dma_addr_t dma;
2508         u16 gso_segs;
2509         u16 desc_count = 0;
2510         bool tail_bump = true;
2511         bool do_rs = false;
2512
2513         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
2514                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
2515                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
2516                          I40E_TX_FLAGS_VLAN_SHIFT;
2517         }
2518
2519         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
2520                 gso_segs = skb_shinfo(skb)->gso_segs;
2521         else
2522                 gso_segs = 1;
2523
2524         /* multiply data chunks by size of headers */
2525         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
2526         first->gso_segs = gso_segs;
2527         first->skb = skb;
2528         first->tx_flags = tx_flags;
2529
2530         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
2531
2532         tx_desc = I40E_TX_DESC(tx_ring, i);
2533         tx_bi = first;
2534
2535         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
2536                 if (dma_mapping_error(tx_ring->dev, dma))
2537                         goto dma_error;
2538
2539                 /* record length, and DMA address */
2540                 dma_unmap_len_set(tx_bi, len, size);
2541                 dma_unmap_addr_set(tx_bi, dma, dma);
2542
2543                 tx_desc->buffer_addr = cpu_to_le64(dma);
2544
2545                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
2546                         tx_desc->cmd_type_offset_bsz =
2547                                 build_ctob(td_cmd, td_offset,
2548                                            I40E_MAX_DATA_PER_TXD, td_tag);
2549
2550                         tx_desc++;
2551                         i++;
2552                         desc_count++;
2553
2554                         if (i == tx_ring->count) {
2555                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
2556                                 i = 0;
2557                         }
2558
2559                         dma += I40E_MAX_DATA_PER_TXD;
2560                         size -= I40E_MAX_DATA_PER_TXD;
2561
2562                         tx_desc->buffer_addr = cpu_to_le64(dma);
2563                 }
2564
2565                 if (likely(!data_len))
2566                         break;
2567
2568                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2569                                                           size, td_tag);
2570
2571                 tx_desc++;
2572                 i++;
2573                 desc_count++;
2574
2575                 if (i == tx_ring->count) {
2576                         tx_desc = I40E_TX_DESC(tx_ring, 0);
2577                         i = 0;
2578                 }
2579
2580                 size = skb_frag_size(frag);
2581                 data_len -= size;
2582
2583                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2584                                        DMA_TO_DEVICE);
2585
2586                 tx_bi = &tx_ring->tx_bi[i];
2587         }
2588
2589         /* set next_to_watch value indicating a packet is present */
2590         first->next_to_watch = tx_desc;
2591
2592         i++;
2593         if (i == tx_ring->count)
2594                 i = 0;
2595
2596         tx_ring->next_to_use = i;
2597
2598         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
2599                                                  tx_ring->queue_index),
2600                                                  first->bytecount);
2601         i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
2602
2603         /* Algorithm to optimize tail and RS bit setting:
2604          * if xmit_more is supported
2605          *      if xmit_more is true
2606          *              do not update tail and do not mark RS bit.
2607          *      if xmit_more is false and last xmit_more was false
2608          *              if every packet spanned less than 4 desc
2609          *                      then set RS bit on 4th packet and update tail
2610          *                      on every packet
2611          *              else
2612          *                      update tail and set RS bit on every packet.
2613          *      if xmit_more is false and last_xmit_more was true
2614          *              update tail and set RS bit.
2615          *
2616          * Optimization: wmb to be issued only in case of tail update.
2617          * Also optimize the Descriptor WB path for RS bit with the same
2618          * algorithm.
2619          *
2620          * Note: If there are less than 4 packets
2621          * pending and interrupts were disabled the service task will
2622          * trigger a force WB.
2623          */
2624         if (skb->xmit_more  &&
2625             !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2626                                                     tx_ring->queue_index))) {
2627                 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2628                 tail_bump = false;
2629         } else if (!skb->xmit_more &&
2630                    !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2631                                                        tx_ring->queue_index)) &&
2632                    (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
2633                    (tx_ring->packet_stride < WB_STRIDE) &&
2634                    (desc_count < WB_STRIDE)) {
2635                 tx_ring->packet_stride++;
2636         } else {
2637                 tx_ring->packet_stride = 0;
2638                 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2639                 do_rs = true;
2640         }
2641         if (do_rs)
2642                 tx_ring->packet_stride = 0;
2643
2644         tx_desc->cmd_type_offset_bsz =
2645                         build_ctob(td_cmd, td_offset, size, td_tag) |
2646                         cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
2647                                                   I40E_TX_DESC_CMD_EOP) <<
2648                                                   I40E_TXD_QW1_CMD_SHIFT);
2649
2650         /* notify HW of packet */
2651         if (!tail_bump)
2652                 prefetchw(tx_desc + 1);
2653
2654         if (tail_bump) {
2655                 /* Force memory writes to complete before letting h/w
2656                  * know there are new descriptors to fetch.  (Only
2657                  * applicable for weak-ordered memory model archs,
2658                  * such as IA-64).
2659                  */
2660                 wmb();
2661                 writel(i, tx_ring->tail);
2662         }
2663
2664         return;
2665
2666 dma_error:
2667         dev_info(tx_ring->dev, "TX DMA map failed\n");
2668
2669         /* clear dma mappings for failed tx_bi map */
2670         for (;;) {
2671                 tx_bi = &tx_ring->tx_bi[i];
2672                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
2673                 if (tx_bi == first)
2674                         break;
2675                 if (i == 0)
2676                         i = tx_ring->count;
2677                 i--;
2678         }
2679
2680         tx_ring->next_to_use = i;
2681 }
2682
2683 /**
2684  * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
2685  * @skb:     send buffer
2686  * @tx_ring: ring to send buffer on
2687  *
2688  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
2689  * there is not enough descriptors available in this ring since we need at least
2690  * one descriptor.
2691  **/
2692 #ifdef I40E_FCOE
2693 inline int i40e_xmit_descriptor_count(struct sk_buff *skb,
2694                                       struct i40e_ring *tx_ring)
2695 #else
2696 static inline int i40e_xmit_descriptor_count(struct sk_buff *skb,
2697                                              struct i40e_ring *tx_ring)
2698 #endif
2699 {
2700         unsigned int f;
2701         int count = 0;
2702
2703         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2704          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
2705          *       + 4 desc gap to avoid the cache line where head is,
2706          *       + 1 desc for context descriptor,
2707          * otherwise try next time
2708          */
2709         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
2710                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
2711
2712         count += TXD_USE_COUNT(skb_headlen(skb));
2713         if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2714                 tx_ring->tx_stats.tx_busy++;
2715                 return 0;
2716         }
2717         return count;
2718 }
2719
2720 /**
2721  * i40e_xmit_frame_ring - Sends buffer on Tx ring
2722  * @skb:     send buffer
2723  * @tx_ring: ring to send buffer on
2724  *
2725  * Returns NETDEV_TX_OK if sent, else an error code
2726  **/
2727 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2728                                         struct i40e_ring *tx_ring)
2729 {
2730         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2731         u32 cd_tunneling = 0, cd_l2tag2 = 0;
2732         struct i40e_tx_buffer *first;
2733         u32 td_offset = 0;
2734         u32 tx_flags = 0;
2735         __be16 protocol;
2736         u32 td_cmd = 0;
2737         u8 hdr_len = 0;
2738         int tsyn;
2739         int tso;
2740         if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
2741                 return NETDEV_TX_BUSY;
2742
2743         /* prepare the xmit flags */
2744         if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2745                 goto out_drop;
2746
2747         /* obtain protocol of skb */
2748         protocol = vlan_get_protocol(skb);
2749
2750         /* record the location of the first descriptor for this packet */
2751         first = &tx_ring->tx_bi[tx_ring->next_to_use];
2752
2753         /* setup IPv4/IPv6 offloads */
2754         if (protocol == htons(ETH_P_IP))
2755                 tx_flags |= I40E_TX_FLAGS_IPV4;
2756         else if (protocol == htons(ETH_P_IPV6))
2757                 tx_flags |= I40E_TX_FLAGS_IPV6;
2758
2759         tso = i40e_tso(tx_ring, skb, &hdr_len,
2760                        &cd_type_cmd_tso_mss, &cd_tunneling);
2761
2762         if (tso < 0)
2763                 goto out_drop;
2764         else if (tso)
2765                 tx_flags |= I40E_TX_FLAGS_TSO;
2766
2767         tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
2768
2769         if (tsyn)
2770                 tx_flags |= I40E_TX_FLAGS_TSYN;
2771
2772         if (i40e_chk_linearize(skb, tx_flags))
2773                 if (skb_linearize(skb))
2774                         goto out_drop;
2775
2776         skb_tx_timestamp(skb);
2777
2778         /* always enable CRC insertion offload */
2779         td_cmd |= I40E_TX_DESC_CMD_ICRC;
2780
2781         /* Always offload the checksum, since it's in the data descriptor */
2782         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2783                 tx_flags |= I40E_TX_FLAGS_CSUM;
2784
2785                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2786                                     tx_ring, &cd_tunneling);
2787         }
2788
2789         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2790                            cd_tunneling, cd_l2tag2);
2791
2792         /* Add Flow Director ATR if it's enabled.
2793          *
2794          * NOTE: this must always be directly before the data descriptor.
2795          */
2796         i40e_atr(tx_ring, skb, tx_flags, protocol);
2797
2798         i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2799                     td_cmd, td_offset);
2800
2801         return NETDEV_TX_OK;
2802
2803 out_drop:
2804         dev_kfree_skb_any(skb);
2805         return NETDEV_TX_OK;
2806 }
2807
2808 /**
2809  * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2810  * @skb:    send buffer
2811  * @netdev: network interface device structure
2812  *
2813  * Returns NETDEV_TX_OK if sent, else an error code
2814  **/
2815 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2816 {
2817         struct i40e_netdev_priv *np = netdev_priv(netdev);
2818         struct i40e_vsi *vsi = np->vsi;
2819         struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
2820
2821         /* hardware can't handle really short frames, hardware padding works
2822          * beyond this point
2823          */
2824         if (skb_put_padto(skb, I40E_MIN_TX_LEN))
2825                 return NETDEV_TX_OK;
2826
2827         return i40e_xmit_frame_ring(skb, tx_ring);
2828 }