drivers/net/ethernet/intel/i40evf/i40e_adminq.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include "i40e_status.h"
  28 #include "i40e_type.h"
  29 #include "i40e_register.h"
  30 #include "i40e_adminq.h"
  31 #include "i40e_prototype.h"
  32
  33 /**
  34  * i40e_is_nvm_update_op - return true if this is an NVM update operation
  35  * @desc: API request descriptor
  36  **/
  37 static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc)
  38 {
  39         return (desc->opcode == i40e_aqc_opc_nvm_erase) ||
  40                (desc->opcode == i40e_aqc_opc_nvm_update);
  41 }
  42
  43 /**
  44  *  i40e_adminq_init_regs - Initialize AdminQ registers
  45  *  @hw: pointer to the hardware structure
  46  *
  47  *  This assumes the alloc_asq and alloc_arq functions have already been called
  48  **/
  49 static void i40e_adminq_init_regs(struct i40e_hw *hw)
  50 {
  51         /* set head and tail registers in our local struct */
  52         if (hw->mac.type == I40E_MAC_VF) {
  53                 hw->aq.asq.tail = I40E_VF_ATQT1;
  54                 hw->aq.asq.head = I40E_VF_ATQH1;
  55                 hw->aq.asq.len  = I40E_VF_ATQLEN1;
  56                 hw->aq.arq.tail = I40E_VF_ARQT1;
  57                 hw->aq.arq.head = I40E_VF_ARQH1;
  58                 hw->aq.arq.len  = I40E_VF_ARQLEN1;
  59         } else {
  60                 hw->aq.asq.tail = I40E_PF_ATQT;
  61                 hw->aq.asq.head = I40E_PF_ATQH;
  62                 hw->aq.asq.len  = I40E_PF_ATQLEN;
  63                 hw->aq.arq.tail = I40E_PF_ARQT;
  64                 hw->aq.arq.head = I40E_PF_ARQH;
  65                 hw->aq.arq.len  = I40E_PF_ARQLEN;
  66         }
  67 }
  68
  69 /**
  70  *  i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
  71  *  @hw: pointer to the hardware structure
  72  **/
  73 static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
  74 {
  75         i40e_status ret_code;
  76
  77         ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
  78                                          i40e_mem_atq_ring,
  79                                          (hw->aq.num_asq_entries *
  80                                          sizeof(struct i40e_aq_desc)),
  81                                          I40E_ADMINQ_DESC_ALIGNMENT);
  82         if (ret_code)
  83                 return ret_code;
  84
  85         ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
  86                                           (hw->aq.num_asq_entries *
  87                                           sizeof(struct i40e_asq_cmd_details)));
  88         if (ret_code) {
  89                 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
  90                 return ret_code;
  91         }
  92
  93         return ret_code;
  94 }
  95
  96 /**
  97  *  i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
  98  *  @hw: pointer to the hardware structure
  99  **/
 100 static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
 101 {
 102         i40e_status ret_code;
 103
 104         ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
 105                                          i40e_mem_arq_ring,
 106                                          (hw->aq.num_arq_entries *
 107                                          sizeof(struct i40e_aq_desc)),
 108                                          I40E_ADMINQ_DESC_ALIGNMENT);
 109
 110         return ret_code;
 111 }
 112
 113 /**
 114  *  i40e_free_adminq_asq - Free Admin Queue send rings
 115  *  @hw: pointer to the hardware structure
 116  *
 117  *  This assumes the posted send buffers have already been cleaned
 118  *  and de-allocated
 119  **/
 120 static void i40e_free_adminq_asq(struct i40e_hw *hw)
 121 {
 122         i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
 123 }
 124
 125 /**
 126  *  i40e_free_adminq_arq - Free Admin Queue receive rings
 127  *  @hw: pointer to the hardware structure
 128  *
 129  *  This assumes the posted receive buffers have already been cleaned
 130  *  and de-allocated
 131  **/
 132 static void i40e_free_adminq_arq(struct i40e_hw *hw)
 133 {
 134         i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
 135 }
 136
 137 /**
 138  *  i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
 139  *  @hw: pointer to the hardware structure
 140  **/
 141 static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
 142 {
 143         i40e_status ret_code;
 144         struct i40e_aq_desc *desc;
 145         struct i40e_dma_mem *bi;
 146         int i;
 147
 148         /* We'll be allocating the buffer info memory first, then we can
 149          * allocate the mapped buffers for the event processing
 150          */
 151
 152         /* buffer_info structures do not need alignment */
 153         ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
 154                 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
 155         if (ret_code)
 156                 goto alloc_arq_bufs;
 157         hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
 158
 159         /* allocate the mapped buffers */
 160         for (i = 0; i < hw->aq.num_arq_entries; i++) {
 161                 bi = &hw->aq.arq.r.arq_bi[i];
 162                 ret_code = i40e_allocate_dma_mem(hw, bi,
 163                                                  i40e_mem_arq_buf,
 164                                                  hw->aq.arq_buf_size,
 165                                                  I40E_ADMINQ_DESC_ALIGNMENT);
 166                 if (ret_code)
 167                         goto unwind_alloc_arq_bufs;
 168
 169                 /* now configure the descriptors for use */
 170                 desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
 171
 172                 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
 173                 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
 174                         desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
 175                 desc->opcode = 0;
 176                 /* This is in accordance with Admin queue design, there is no
 177                  * register for buffer size configuration
 178                  */
 179                 desc->datalen = cpu_to_le16((u16)bi->size);
 180                 desc->retval = 0;
 181                 desc->cookie_high = 0;
 182                 desc->cookie_low = 0;
 183                 desc->params.external.addr_high =
 184                         cpu_to_le32(upper_32_bits(bi->pa));
 185                 desc->params.external.addr_low =
 186                         cpu_to_le32(lower_32_bits(bi->pa));
 187                 desc->params.external.param0 = 0;
 188                 desc->params.external.param1 = 0;
 189         }
 190
 191 alloc_arq_bufs:
 192         return ret_code;
 193
 194 unwind_alloc_arq_bufs:
 195         /* don't try to free the one that failed... */
 196         i--;
 197         for (; i >= 0; i--)
 198                 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
 199         i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
 200
 201         return ret_code;
 202 }
 203
 204 /**
 205  *  i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue
 206  *  @hw: pointer to the hardware structure
 207  **/
 208 static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw)
 209 {
 210         i40e_status ret_code;
 211         struct i40e_dma_mem *bi;
 212         int i;
 213
 214         /* No mapped memory needed yet, just the buffer info structures */
 215         ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
 216                 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));
 217         if (ret_code)
 218                 goto alloc_asq_bufs;
 219         hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
 220
 221         /* allocate the mapped buffers */
 222         for (i = 0; i < hw->aq.num_asq_entries; i++) {
 223                 bi = &hw->aq.asq.r.asq_bi[i];
 224                 ret_code = i40e_allocate_dma_mem(hw, bi,
 225                                                  i40e_mem_asq_buf,
 226                                                  hw->aq.asq_buf_size,
 227                                                  I40E_ADMINQ_DESC_ALIGNMENT);
 228                 if (ret_code)
 229                         goto unwind_alloc_asq_bufs;
 230         }
 231 alloc_asq_bufs:
 232         return ret_code;
 233
 234 unwind_alloc_asq_bufs:
 235         /* don't try to free the one that failed... */
 236         i--;
 237         for (; i >= 0; i--)
 238                 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
 239         i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
 240
 241         return ret_code;
 242 }
 243
 244 /**
 245  *  i40e_free_arq_bufs - Free receive queue buffer info elements
 246  *  @hw: pointer to the hardware structure
 247  **/
 248 static void i40e_free_arq_bufs(struct i40e_hw *hw)
 249 {
 250         int i;
 251
 252         /* free descriptors */
 253         for (i = 0; i < hw->aq.num_arq_entries; i++)
 254                 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
 255
 256         /* free the descriptor memory */
 257         i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
 258
 259         /* free the dma header */
 260         i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
 261 }
 262
 263 /**
 264  *  i40e_free_asq_bufs - Free send queue buffer info elements
 265  *  @hw: pointer to the hardware structure
 266  **/
 267 static void i40e_free_asq_bufs(struct i40e_hw *hw)
 268 {
 269         int i;
 270
 271         /* only unmap if the address is non-NULL */
 272         for (i = 0; i < hw->aq.num_asq_entries; i++)
 273                 if (hw->aq.asq.r.asq_bi[i].pa)
 274                         i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
 275
 276         /* free the buffer info list */
 277         i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
 278
 279         /* free the descriptor memory */
 280         i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
 281
 282         /* free the dma header */
 283         i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
 284 }
 285
 286 /**
 287  *  i40e_config_asq_regs - configure ASQ registers
 288  *  @hw: pointer to the hardware structure
 289  *
 290  *  Configure base address and length registers for the transmit queue
 291  **/
 292 static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
 293 {
 294         i40e_status ret_code = 0;
 295         u32 reg = 0;
 296
 297         if (hw->mac.type == I40E_MAC_VF) {
 298                 /* configure the transmit queue */
 299                 wr32(hw, I40E_VF_ATQBAH1,
 300                     upper_32_bits(hw->aq.asq.desc_buf.pa));
 301                 wr32(hw, I40E_VF_ATQBAL1,
 302                     lower_32_bits(hw->aq.asq.desc_buf.pa));
 303                 wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries |
 304                                           I40E_VF_ATQLEN1_ATQENABLE_MASK));
 305                 reg = rd32(hw, I40E_VF_ATQBAL1);
 306         } else {
 307                 /* configure the transmit queue */
 308                 wr32(hw, I40E_PF_ATQBAH,
 309                     upper_32_bits(hw->aq.asq.desc_buf.pa));
 310                 wr32(hw, I40E_PF_ATQBAL,
 311                     lower_32_bits(hw->aq.asq.desc_buf.pa));
 312                 wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries |
 313                                           I40E_PF_ATQLEN_ATQENABLE_MASK));
 314                 reg = rd32(hw, I40E_PF_ATQBAL);
 315         }
 316
 317         /* Check one register to verify that config was applied */
 318         if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
 319                 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
 320
 321         return ret_code;
 322 }
 323
 324 /**
 325  *  i40e_config_arq_regs - ARQ register configuration
 326  *  @hw: pointer to the hardware structure
 327  *
 328  * Configure base address and length registers for the receive (event queue)
 329  **/
 330 static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
 331 {
 332         i40e_status ret_code = 0;
 333         u32 reg = 0;
 334
 335         if (hw->mac.type == I40E_MAC_VF) {
 336                 /* configure the receive queue */
 337                 wr32(hw, I40E_VF_ARQBAH1,
 338                     upper_32_bits(hw->aq.arq.desc_buf.pa));
 339                 wr32(hw, I40E_VF_ARQBAL1,
 340                     lower_32_bits(hw->aq.arq.desc_buf.pa));
 341                 wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries |
 342                                           I40E_VF_ARQLEN1_ARQENABLE_MASK));
 343                 reg = rd32(hw, I40E_VF_ARQBAL1);
 344         } else {
 345                 /* configure the receive queue */
 346                 wr32(hw, I40E_PF_ARQBAH,
 347                     upper_32_bits(hw->aq.arq.desc_buf.pa));
 348                 wr32(hw, I40E_PF_ARQBAL,
 349                     lower_32_bits(hw->aq.arq.desc_buf.pa));
 350                 wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries |
 351                                           I40E_PF_ARQLEN_ARQENABLE_MASK));
 352                 reg = rd32(hw, I40E_PF_ARQBAL);
 353         }
 354
 355         /* Update tail in the HW to post pre-allocated buffers */
 356         wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
 357
 358         /* Check one register to verify that config was applied */
 359         if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
 360                 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
 361
 362         return ret_code;
 363 }
 364
 365 /**
 366  *  i40e_init_asq - main initialization routine for ASQ
 367  *  @hw: pointer to the hardware structure
 368  *
 369  *  This is the main initialization routine for the Admin Send Queue
 370  *  Prior to calling this function, drivers *MUST* set the following fields
 371  *  in the hw->aq structure:
 372  *     - hw->aq.num_asq_entries
 373  *     - hw->aq.arq_buf_size
 374  *
 375  *  Do *NOT* hold the lock when calling this as the memory allocation routines
 376  *  called are not going to be atomic context safe
 377  **/
 378 static i40e_status i40e_init_asq(struct i40e_hw *hw)
 379 {
 380         i40e_status ret_code = 0;
 381
 382         if (hw->aq.asq.count > 0) {
 383                 /* queue already initialized */
 384                 ret_code = I40E_ERR_NOT_READY;
 385                 goto init_adminq_exit;
 386         }
 387
 388         /* verify input for valid configuration */
 389         if ((hw->aq.num_asq_entries == 0) ||
 390             (hw->aq.asq_buf_size == 0)) {
 391                 ret_code = I40E_ERR_CONFIG;
 392                 goto init_adminq_exit;
 393         }
 394
 395         hw->aq.asq.next_to_use = 0;
 396         hw->aq.asq.next_to_clean = 0;
 397         hw->aq.asq.count = hw->aq.num_asq_entries;
 398
 399         /* allocate the ring memory */
 400         ret_code = i40e_alloc_adminq_asq_ring(hw);
 401         if (ret_code)
 402                 goto init_adminq_exit;
 403
 404         /* allocate buffers in the rings */
 405         ret_code = i40e_alloc_asq_bufs(hw);
 406         if (ret_code)
 407                 goto init_adminq_free_rings;
 408
 409         /* initialize base registers */
 410         ret_code = i40e_config_asq_regs(hw);
 411         if (ret_code)
 412                 goto init_adminq_free_rings;
 413
 414         /* success! */
 415         goto init_adminq_exit;
 416
 417 init_adminq_free_rings:
 418         i40e_free_adminq_asq(hw);
 419
 420 init_adminq_exit:
 421         return ret_code;
 422 }
 423
 424 /**
 425  *  i40e_init_arq - initialize ARQ
 426  *  @hw: pointer to the hardware structure
 427  *
 428  *  The main initialization routine for the Admin Receive (Event) Queue.
 429  *  Prior to calling this function, drivers *MUST* set the following fields
 430  *  in the hw->aq structure:
 431  *     - hw->aq.num_asq_entries
 432  *     - hw->aq.arq_buf_size
 433  *
 434  *  Do *NOT* hold the lock when calling this as the memory allocation routines
 435  *  called are not going to be atomic context safe
 436  **/
 437 static i40e_status i40e_init_arq(struct i40e_hw *hw)
 438 {
 439         i40e_status ret_code = 0;
 440
 441         if (hw->aq.arq.count > 0) {
 442                 /* queue already initialized */
 443                 ret_code = I40E_ERR_NOT_READY;
 444                 goto init_adminq_exit;
 445         }
 446
 447         /* verify input for valid configuration */
 448         if ((hw->aq.num_arq_entries == 0) ||
 449             (hw->aq.arq_buf_size == 0)) {
 450                 ret_code = I40E_ERR_CONFIG;
 451                 goto init_adminq_exit;
 452         }
 453
 454         hw->aq.arq.next_to_use = 0;
 455         hw->aq.arq.next_to_clean = 0;
 456         hw->aq.arq.count = hw->aq.num_arq_entries;
 457
 458         /* allocate the ring memory */
 459         ret_code = i40e_alloc_adminq_arq_ring(hw);
 460         if (ret_code)
 461                 goto init_adminq_exit;
 462
 463         /* allocate buffers in the rings */
 464         ret_code = i40e_alloc_arq_bufs(hw);
 465         if (ret_code)
 466                 goto init_adminq_free_rings;
 467
 468         /* initialize base registers */
 469         ret_code = i40e_config_arq_regs(hw);
 470         if (ret_code)
 471                 goto init_adminq_free_rings;
 472
 473         /* success! */
 474         goto init_adminq_exit;
 475
 476 init_adminq_free_rings:
 477         i40e_free_adminq_arq(hw);
 478
 479 init_adminq_exit:
 480         return ret_code;
 481 }
 482
 483 /**
 484  *  i40e_shutdown_asq - shutdown the ASQ
 485  *  @hw: pointer to the hardware structure
 486  *
 487  *  The main shutdown routine for the Admin Send Queue
 488  **/
 489 static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
 490 {
 491         i40e_status ret_code = 0;
 492
 493         if (hw->aq.asq.count == 0)
 494                 return I40E_ERR_NOT_READY;
 495
 496         /* Stop firmware AdminQ processing */
 497         wr32(hw, hw->aq.asq.head, 0);
 498         wr32(hw, hw->aq.asq.tail, 0);
 499         wr32(hw, hw->aq.asq.len, 0);
 500
 501         /* make sure lock is available */
 502         mutex_lock(&hw->aq.asq_mutex);
 503
 504         hw->aq.asq.count = 0; /* to indicate uninitialized queue */
 505
 506         /* free ring buffers */
 507         i40e_free_asq_bufs(hw);
 508
 509         mutex_unlock(&hw->aq.asq_mutex);
 510
 511         return ret_code;
 512 }
 513
 514 /**
 515  *  i40e_shutdown_arq - shutdown ARQ
 516  *  @hw: pointer to the hardware structure
 517  *
 518  *  The main shutdown routine for the Admin Receive Queue
 519  **/
 520 static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
 521 {
 522         i40e_status ret_code = 0;
 523
 524         if (hw->aq.arq.count == 0)
 525                 return I40E_ERR_NOT_READY;
 526
 527         /* Stop firmware AdminQ processing */
 528         wr32(hw, hw->aq.arq.head, 0);
 529         wr32(hw, hw->aq.arq.tail, 0);
 530         wr32(hw, hw->aq.arq.len, 0);
 531
 532         /* make sure lock is available */
 533         mutex_lock(&hw->aq.arq_mutex);
 534
 535         hw->aq.arq.count = 0; /* to indicate uninitialized queue */
 536
 537         /* free ring buffers */
 538         i40e_free_arq_bufs(hw);
 539
 540         mutex_unlock(&hw->aq.arq_mutex);
 541
 542         return ret_code;
 543 }
 544
 545 /**
 546  *  i40evf_init_adminq - main initialization routine for Admin Queue
 547  *  @hw: pointer to the hardware structure
 548  *
 549  *  Prior to calling this function, drivers *MUST* set the following fields
 550  *  in the hw->aq structure:
 551  *     - hw->aq.num_asq_entries
 552  *     - hw->aq.num_arq_entries
 553  *     - hw->aq.arq_buf_size
 554  *     - hw->aq.asq_buf_size
 555  **/
 556 i40e_status i40evf_init_adminq(struct i40e_hw *hw)
 557 {
 558         i40e_status ret_code;
 559
 560         /* verify input for valid configuration */
 561         if ((hw->aq.num_arq_entries == 0) ||
 562             (hw->aq.num_asq_entries == 0) ||
 563             (hw->aq.arq_buf_size == 0) ||
 564             (hw->aq.asq_buf_size == 0)) {
 565                 ret_code = I40E_ERR_CONFIG;
 566                 goto init_adminq_exit;
 567         }
 568
 569         /* initialize locks */
 570         mutex_init(&hw->aq.asq_mutex);
 571         mutex_init(&hw->aq.arq_mutex);
 572
 573         /* Set up register offsets */
 574         i40e_adminq_init_regs(hw);
 575
 576         /* allocate the ASQ */
 577         ret_code = i40e_init_asq(hw);
 578         if (ret_code)
 579                 goto init_adminq_destroy_locks;
 580
 581         /* allocate the ARQ */
 582         ret_code = i40e_init_arq(hw);
 583         if (ret_code)
 584                 goto init_adminq_free_asq;
 585
 586         /* success! */
 587         goto init_adminq_exit;
 588
 589 init_adminq_free_asq:
 590         i40e_shutdown_asq(hw);
 591 init_adminq_destroy_locks:
 592
 593 init_adminq_exit:
 594         return ret_code;
 595 }
 596
 597 /**
 598  *  i40evf_shutdown_adminq - shutdown routine for the Admin Queue
 599  *  @hw: pointer to the hardware structure
 600  **/
 601 i40e_status i40evf_shutdown_adminq(struct i40e_hw *hw)
 602 {
 603         i40e_status ret_code = 0;
 604
 605         if (i40evf_check_asq_alive(hw))
 606                 i40evf_aq_queue_shutdown(hw, true);
 607
 608         i40e_shutdown_asq(hw);
 609         i40e_shutdown_arq(hw);
 610
 611         /* destroy the locks */
 612
 613         return ret_code;
 614 }
 615
 616 /**
 617  *  i40e_clean_asq - cleans Admin send queue
 618  *  @hw: pointer to the hardware structure
 619  *
 620  *  returns the number of free desc
 621  **/
 622 static u16 i40e_clean_asq(struct i40e_hw *hw)
 623 {
 624         struct i40e_adminq_ring *asq = &(hw->aq.asq);
 625         struct i40e_asq_cmd_details *details;
 626         u16 ntc = asq->next_to_clean;
 627         struct i40e_aq_desc desc_cb;
 628         struct i40e_aq_desc *desc;
 629
 630         desc = I40E_ADMINQ_DESC(*asq, ntc);
 631         details = I40E_ADMINQ_DETAILS(*asq, ntc);
 632         while (rd32(hw, hw->aq.asq.head) != ntc) {
 633                 if (details->callback) {
 634                         I40E_ADMINQ_CALLBACK cb_func =
 635                                         (I40E_ADMINQ_CALLBACK)details->callback;
 636                         desc_cb = *desc;
 637                         cb_func(hw, &desc_cb);
 638                 }
 639                 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
 640                 memset((void *)details, 0,
 641                        sizeof(struct i40e_asq_cmd_details));
 642                 ntc++;
 643                 if (ntc == asq->count)
 644                         ntc = 0;
 645                 desc = I40E_ADMINQ_DESC(*asq, ntc);
 646                 details = I40E_ADMINQ_DETAILS(*asq, ntc);
 647         }
 648
 649         asq->next_to_clean = ntc;
 650
 651         return I40E_DESC_UNUSED(asq);
 652 }
 653
 654 /**
 655  *  i40evf_asq_done - check if FW has processed the Admin Send Queue
 656  *  @hw: pointer to the hw struct
 657  *
 658  *  Returns true if the firmware has processed all descriptors on the
 659  *  admin send queue. Returns false if there are still requests pending.
 660  **/
 661 bool i40evf_asq_done(struct i40e_hw *hw)
 662 {
 663         /* AQ designers suggest use of head for better
 664          * timing reliability than DD bit
 665          */
 666         return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
 667
 668 }
 669
 670 /**
 671  *  i40evf_asq_send_command - send command to Admin Queue
 672  *  @hw: pointer to the hw struct
 673  *  @desc: prefilled descriptor describing the command (non DMA mem)
 674  *  @buff: buffer to use for indirect commands
 675  *  @buff_size: size of buffer for indirect commands
 676  *  @cmd_details: pointer to command details structure
 677  *
 678  *  This is the main send command driver routine for the Admin Queue send
 679  *  queue.  It runs the queue, cleans the queue, etc
 680  **/
 681 i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
 682                                 struct i40e_aq_desc *desc,
 683                                 void *buff, /* can be NULL */
 684                                 u16  buff_size,
 685                                 struct i40e_asq_cmd_details *cmd_details)
 686 {
 687         i40e_status status = 0;
 688         struct i40e_dma_mem *dma_buff = NULL;
 689         struct i40e_asq_cmd_details *details;
 690         struct i40e_aq_desc *desc_on_ring;
 691         bool cmd_completed = false;
 692         u16  retval = 0;
 693
 694         if (hw->aq.asq.count == 0) {
 695                 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
 696                            "AQTX: Admin queue not initialized.\n");
 697                 status = I40E_ERR_QUEUE_EMPTY;
 698                 goto asq_send_command_exit;
 699         }
 700
 701         if (i40e_is_nvm_update_op(desc) && hw->aq.nvm_busy) {
 702                 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: NVM busy.\n");
 703                 status = I40E_ERR_NVM;
 704                 goto asq_send_command_exit;
 705         }
 706
 707         details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
 708         if (cmd_details) {
 709                 *details = *cmd_details;
 710
 711                 /* If the cmd_details are defined copy the cookie.  The
 712                  * cpu_to_le32 is not needed here because the data is ignored
 713                  * by the FW, only used by the driver
 714                  */
 715                 if (details->cookie) {
 716                         desc->cookie_high =
 717                                 cpu_to_le32(upper_32_bits(details->cookie));
 718                         desc->cookie_low =
 719                                 cpu_to_le32(lower_32_bits(details->cookie));
 720                 }
 721         } else {
 722                 memset(details, 0, sizeof(struct i40e_asq_cmd_details));
 723         }
 724
 725         /* clear requested flags and then set additional flags if defined */
 726         desc->flags &= ~cpu_to_le16(details->flags_dis);
 727         desc->flags |= cpu_to_le16(details->flags_ena);
 728
 729         mutex_lock(&hw->aq.asq_mutex);
 730
 731         if (buff_size > hw->aq.asq_buf_size) {
 732                 i40e_debug(hw,
 733                            I40E_DEBUG_AQ_MESSAGE,
 734                            "AQTX: Invalid buffer size: %d.\n",
 735                            buff_size);
 736                 status = I40E_ERR_INVALID_SIZE;
 737                 goto asq_send_command_error;
 738         }
 739
 740         if (details->postpone && !details->async) {
 741                 i40e_debug(hw,
 742                            I40E_DEBUG_AQ_MESSAGE,
 743                            "AQTX: Async flag not set along with postpone flag");
 744                 status = I40E_ERR_PARAM;
 745                 goto asq_send_command_error;
 746         }
 747
 748         /* call clean and check queue available function to reclaim the
 749          * descriptors that were processed by FW, the function returns the
 750          * number of desc available
 751          */
 752         /* the clean function called here could be called in a separate thread
 753          * in case of asynchronous completions
 754          */
 755         if (i40e_clean_asq(hw) == 0) {
 756                 i40e_debug(hw,
 757                            I40E_DEBUG_AQ_MESSAGE,
 758                            "AQTX: Error queue is full.\n");
 759                 status = I40E_ERR_ADMIN_QUEUE_FULL;
 760                 goto asq_send_command_error;
 761         }
 762
 763         /* initialize the temp desc pointer with the right desc */
 764         desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
 765
 766         /* if the desc is available copy the temp desc to the right place */
 767         *desc_on_ring = *desc;
 768
 769         /* if buff is not NULL assume indirect command */
 770         if (buff != NULL) {
 771                 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
 772                 /* copy the user buff into the respective DMA buff */
 773                 memcpy(dma_buff->va, buff, buff_size);
 774                 desc_on_ring->datalen = cpu_to_le16(buff_size);
 775
 776                 /* Update the address values in the desc with the pa value
 777                  * for respective buffer
 778                  */
 779                 desc_on_ring->params.external.addr_high =
 780                                 cpu_to_le32(upper_32_bits(dma_buff->pa));
 781                 desc_on_ring->params.external.addr_low =
 782                                 cpu_to_le32(lower_32_bits(dma_buff->pa));
 783         }
 784
 785         /* bump the tail */
 786         i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff);
 787         (hw->aq.asq.next_to_use)++;
 788         if (hw->aq.asq.next_to_use == hw->aq.asq.count)
 789                 hw->aq.asq.next_to_use = 0;
 790         if (!details->postpone)
 791                 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
 792
 793         /* if cmd_details are not defined or async flag is not set,
 794          * we need to wait for desc write back
 795          */
 796         if (!details->async && !details->postpone) {
 797                 u32 total_delay = 0;
 798                 u32 delay_len = 10;
 799
 800                 do {
 801                         /* AQ designers suggest use of head for better
 802                          * timing reliability than DD bit
 803                          */
 804                         if (i40evf_asq_done(hw))
 805                                 break;
 806                         /* ugh! delay while spin_lock */
 807                         udelay(delay_len);
 808                         total_delay += delay_len;
 809                 } while (total_delay <  I40E_ASQ_CMD_TIMEOUT);
 810         }
 811
 812         /* if ready, copy the desc back to temp */
 813         if (i40evf_asq_done(hw)) {
 814                 *desc = *desc_on_ring;
 815                 if (buff != NULL)
 816                         memcpy(buff, dma_buff->va, buff_size);
 817                 retval = le16_to_cpu(desc->retval);
 818                 if (retval != 0) {
 819                         i40e_debug(hw,
 820                                    I40E_DEBUG_AQ_MESSAGE,
 821                                    "AQTX: Command completed with error 0x%X.\n",
 822                                    retval);
 823                         /* strip off FW internal code */
 824                         retval &= 0xff;
 825                 }
 826                 cmd_completed = true;
 827                 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
 828                         status = 0;
 829                 else
 830                         status = I40E_ERR_ADMIN_QUEUE_ERROR;
 831                 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
 832         }
 833
 834         if (i40e_is_nvm_update_op(desc))
 835                 hw->aq.nvm_busy = true;
 836
 837         /* update the error if time out occurred */
 838         if ((!cmd_completed) &&
 839             (!details->async && !details->postpone)) {
 840                 i40e_debug(hw,
 841                            I40E_DEBUG_AQ_MESSAGE,
 842                            "AQTX: Writeback timeout.\n");
 843                 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
 844         }
 845
 846 asq_send_command_error:
 847         mutex_unlock(&hw->aq.asq_mutex);
 848 asq_send_command_exit:
 849         return status;
 850 }
 851
 852 /**
 853  *  i40evf_fill_default_direct_cmd_desc - AQ descriptor helper function
 854  *  @desc:     pointer to the temp descriptor (non DMA mem)
 855  *  @opcode:   the opcode can be used to decide which flags to turn off or on
 856  *
 857  *  Fill the desc with default values
 858  **/
 859 void i40evf_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
 860                                        u16 opcode)
 861 {
 862         /* zero out the desc */
 863         memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
 864         desc->opcode = cpu_to_le16(opcode);
 865         desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI);
 866 }
 867
 868 /**
 869  *  i40evf_clean_arq_element
 870  *  @hw: pointer to the hw struct
 871  *  @e: event info from the receive descriptor, includes any buffers
 872  *  @pending: number of events that could be left to process
 873  *
 874  *  This function cleans one Admin Receive Queue element and returns
 875  *  the contents through e.  It can also return how many events are
 876  *  left to process through 'pending'
 877  **/
 878 i40e_status i40evf_clean_arq_element(struct i40e_hw *hw,
 879                                              struct i40e_arq_event_info *e,
 880                                              u16 *pending)
 881 {
 882         i40e_status ret_code = 0;
 883         u16 ntc = hw->aq.arq.next_to_clean;
 884         struct i40e_aq_desc *desc;
 885         struct i40e_dma_mem *bi;
 886         u16 desc_idx;
 887         u16 datalen;
 888         u16 flags;
 889         u16 ntu;
 890
 891         /* take the lock before we start messing with the ring */
 892         mutex_lock(&hw->aq.arq_mutex);
 893
 894         /* set next_to_use to head */
 895         ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);
 896         if (ntu == ntc) {
 897                 /* nothing to do - shouldn't need to update ring's values */
 898                 i40e_debug(hw,
 899                            I40E_DEBUG_AQ_MESSAGE,
 900                            "AQRX: Queue is empty.\n");
 901                 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
 902                 goto clean_arq_element_out;
 903         }
 904
 905         /* now clean the next descriptor */
 906         desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
 907         desc_idx = ntc;
 908         i40evf_debug_aq(hw,
 909                       I40E_DEBUG_AQ_COMMAND,
 910                       (void *)desc,
 911                       hw->aq.arq.r.arq_bi[desc_idx].va);
 912
 913         flags = le16_to_cpu(desc->flags);
 914         if (flags & I40E_AQ_FLAG_ERR) {
 915                 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
 916                 hw->aq.arq_last_status =
 917                         (enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
 918                 i40e_debug(hw,
 919                            I40E_DEBUG_AQ_MESSAGE,
 920                            "AQRX: Event received with error 0x%X.\n",
 921                            hw->aq.arq_last_status);
 922         } else {
 923                 e->desc = *desc;
 924                 datalen = le16_to_cpu(desc->datalen);
 925                 e->msg_size = min(datalen, e->msg_size);
 926                 if (e->msg_buf != NULL && (e->msg_size != 0))
 927                         memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,
 928                                e->msg_size);
 929         }
 930
 931         if (i40e_is_nvm_update_op(&e->desc))
 932                 hw->aq.nvm_busy = false;
 933
 934         /* Restore the original datalen and buffer address in the desc,
 935          * FW updates datalen to indicate the event message
 936          * size
 937          */
 938         bi = &hw->aq.arq.r.arq_bi[ntc];
 939         memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
 940
 941         desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
 942         if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
 943                 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
 944         desc->datalen = cpu_to_le16((u16)bi->size);
 945         desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
 946         desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
 947
 948         /* set tail = the last cleaned desc index. */
 949         wr32(hw, hw->aq.arq.tail, ntc);
 950         /* ntc is updated to tail + 1 */
 951         ntc++;
 952         if (ntc == hw->aq.num_arq_entries)
 953                 ntc = 0;
 954         hw->aq.arq.next_to_clean = ntc;
 955         hw->aq.arq.next_to_use = ntu;
 956
 957 clean_arq_element_out:
 958         /* Set pending if needed, unlock and return */
 959         if (pending != NULL)
 960                 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
 961         mutex_unlock(&hw->aq.arq_mutex);
 962
 963         return ret_code;
 964 }
 965
 966 void i40evf_resume_aq(struct i40e_hw *hw)
 967 {
 968         /* Registers are reset after PF reset */
 969         hw->aq.asq.next_to_use = 0;
 970         hw->aq.asq.next_to_clean = 0;
 971
 972         i40e_config_asq_regs(hw);
 973
 974         hw->aq.arq.next_to_use = 0;
 975         hw->aq.arq.next_to_clean = 0;
 976
 977         i40e_config_arq_regs(hw);
 978 }