drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29
  30 #include "i40evf.h"
  31 #include "i40e_prototype.h"
  32
  33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  34                                 u32 td_tag)
  35 {
  36         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  37                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  38                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  39                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  40                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  41 }
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 /**
  46  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  47  * @ring:      the ring that owns the buffer
  48  * @tx_buffer: the buffer to free
  49  **/
  50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  51                                             struct i40e_tx_buffer *tx_buffer)
  52 {
  53         if (tx_buffer->skb) {
  54                 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
  55                         kfree(tx_buffer->raw_buf);
  56                 else
  57                         dev_kfree_skb_any(tx_buffer->skb);
  58
  59                 if (dma_unmap_len(tx_buffer, len))
  60                         dma_unmap_single(ring->dev,
  61                                          dma_unmap_addr(tx_buffer, dma),
  62                                          dma_unmap_len(tx_buffer, len),
  63                                          DMA_TO_DEVICE);
  64         } else if (dma_unmap_len(tx_buffer, len)) {
  65                 dma_unmap_page(ring->dev,
  66                                dma_unmap_addr(tx_buffer, dma),
  67                                dma_unmap_len(tx_buffer, len),
  68                                DMA_TO_DEVICE);
  69         }
  70         tx_buffer->next_to_watch = NULL;
  71         tx_buffer->skb = NULL;
  72         dma_unmap_len_set(tx_buffer, len, 0);
  73         /* tx_buffer must be completely set up in the transmit path */
  74 }
  75
  76 /**
  77  * i40evf_clean_tx_ring - Free any empty Tx buffers
  78  * @tx_ring: ring to be cleaned
  79  **/
  80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  81 {
  82         unsigned long bi_size;
  83         u16 i;
  84
  85         /* ring already cleared, nothing to do */
  86         if (!tx_ring->tx_bi)
  87                 return;
  88
  89         /* Free all the Tx ring sk_buffs */
  90         for (i = 0; i < tx_ring->count; i++)
  91                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  92
  93         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  94         memset(tx_ring->tx_bi, 0, bi_size);
  95
  96         /* Zero out the descriptor ring */
  97         memset(tx_ring->desc, 0, tx_ring->size);
  98
  99         tx_ring->next_to_use = 0;
 100         tx_ring->next_to_clean = 0;
 101
 102         if (!tx_ring->netdev)
 103                 return;
 104
 105         /* cleanup Tx queue statistics */
 106         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 107                                                   tx_ring->queue_index));
 108 }
 109
 110 /**
 111  * i40evf_free_tx_resources - Free Tx resources per queue
 112  * @tx_ring: Tx descriptor ring for a specific queue
 113  *
 114  * Free all transmit software resources
 115  **/
 116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 117 {
 118         i40evf_clean_tx_ring(tx_ring);
 119         kfree(tx_ring->tx_bi);
 120         tx_ring->tx_bi = NULL;
 121
 122         if (tx_ring->desc) {
 123                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 124                                   tx_ring->desc, tx_ring->dma);
 125                 tx_ring->desc = NULL;
 126         }
 127 }
 128
 129 /**
 130  * i40e_get_head - Retrieve head from head writeback
 131  * @tx_ring:  tx ring to fetch head of
 132  *
 133  * Returns value of Tx ring head based on value stored
 134  * in head write-back location
 135  **/
 136 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
 137 {
 138         void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
 139
 140         return le32_to_cpu(*(volatile __le32 *)head);
 141 }
 142
 143 #define WB_STRIDE 0x3
 144
 145 /**
 146  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 147  * @tx_ring:  tx ring to clean
 148  * @budget:   how many cleans we're allowed
 149  *
 150  * Returns true if there's any budget left (e.g. the clean is finished)
 151  **/
 152 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 153 {
 154         u16 i = tx_ring->next_to_clean;
 155         struct i40e_tx_buffer *tx_buf;
 156         struct i40e_tx_desc *tx_head;
 157         struct i40e_tx_desc *tx_desc;
 158         unsigned int total_packets = 0;
 159         unsigned int total_bytes = 0;
 160
 161         tx_buf = &tx_ring->tx_bi[i];
 162         tx_desc = I40E_TX_DESC(tx_ring, i);
 163         i -= tx_ring->count;
 164
 165         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 166
 167         do {
 168                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 169
 170                 /* if next_to_watch is not set then there is no work pending */
 171                 if (!eop_desc)
 172                         break;
 173
 174                 /* prevent any other reads prior to eop_desc */
 175                 read_barrier_depends();
 176
 177                 /* we have caught up to head, no work left to do */
 178                 if (tx_head == tx_desc)
 179                         break;
 180
 181                 /* clear next_to_watch to prevent false hangs */
 182                 tx_buf->next_to_watch = NULL;
 183
 184                 /* update the statistics for this packet */
 185                 total_bytes += tx_buf->bytecount;
 186                 total_packets += tx_buf->gso_segs;
 187
 188                 /* free the skb */
 189                 dev_kfree_skb_any(tx_buf->skb);
 190
 191                 /* unmap skb header data */
 192                 dma_unmap_single(tx_ring->dev,
 193                                  dma_unmap_addr(tx_buf, dma),
 194                                  dma_unmap_len(tx_buf, len),
 195                                  DMA_TO_DEVICE);
 196
 197                 /* clear tx_buffer data */
 198                 tx_buf->skb = NULL;
 199                 dma_unmap_len_set(tx_buf, len, 0);
 200
 201                 /* unmap remaining buffers */
 202                 while (tx_desc != eop_desc) {
 203
 204                         tx_buf++;
 205                         tx_desc++;
 206                         i++;
 207                         if (unlikely(!i)) {
 208                                 i -= tx_ring->count;
 209                                 tx_buf = tx_ring->tx_bi;
 210                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 211                         }
 212
 213                         /* unmap any remaining paged data */
 214                         if (dma_unmap_len(tx_buf, len)) {
 215                                 dma_unmap_page(tx_ring->dev,
 216                                                dma_unmap_addr(tx_buf, dma),
 217                                                dma_unmap_len(tx_buf, len),
 218                                                DMA_TO_DEVICE);
 219                                 dma_unmap_len_set(tx_buf, len, 0);
 220                         }
 221                 }
 222
 223                 /* move us one more past the eop_desc for start of next pkt */
 224                 tx_buf++;
 225                 tx_desc++;
 226                 i++;
 227                 if (unlikely(!i)) {
 228                         i -= tx_ring->count;
 229                         tx_buf = tx_ring->tx_bi;
 230                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 231                 }
 232
 233                 prefetch(tx_desc);
 234
 235                 /* update budget accounting */
 236                 budget--;
 237         } while (likely(budget));
 238
 239         i += tx_ring->count;
 240         tx_ring->next_to_clean = i;
 241         u64_stats_update_begin(&tx_ring->syncp);
 242         tx_ring->stats.bytes += total_bytes;
 243         tx_ring->stats.packets += total_packets;
 244         u64_stats_update_end(&tx_ring->syncp);
 245         tx_ring->q_vector->tx.total_bytes += total_bytes;
 246         tx_ring->q_vector->tx.total_packets += total_packets;
 247
 248         /* check to see if there are any non-cache aligned descriptors
 249          * waiting to be written back, and kick the hardware to force
 250          * them to be written back in case of napi polling
 251          */
 252         if (budget &&
 253             !((i & WB_STRIDE) == WB_STRIDE) &&
 254             !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
 255             (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
 256                 tx_ring->arm_wb = true;
 257
 258         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 259                                                       tx_ring->queue_index),
 260                                   total_packets, total_bytes);
 261
 262 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 263         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 264                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 265                 /* Make sure that anybody stopping the queue after this
 266                  * sees the new next_to_clean.
 267                  */
 268                 smp_mb();
 269                 if (__netif_subqueue_stopped(tx_ring->netdev,
 270                                              tx_ring->queue_index) &&
 271                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 272                         netif_wake_subqueue(tx_ring->netdev,
 273                                             tx_ring->queue_index);
 274                         ++tx_ring->tx_stats.restart_queue;
 275                 }
 276         }
 277
 278         return !!budget;
 279 }
 280
 281 /**
 282  * i40evf_force_wb -Arm hardware to do a wb on noncache aligned descriptors
 283  * @vsi: the VSI we care about
 284  * @q_vector: the vector  on which to force writeback
 285  *
 286  **/
 287 static void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 288 {
 289         u16 flags = q_vector->tx.ring[0].flags;
 290
 291         if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 292                 u32 val;
 293
 294                 if (q_vector->arm_wb_state)
 295                         return;
 296
 297                 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK;
 298
 299                 wr32(&vsi->back->hw,
 300                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 301                                           vsi->base_vector - 1),
 302                      val);
 303                 q_vector->arm_wb_state = true;
 304         } else {
 305                 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
 306                           I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
 307                           I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
 308                           I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK;
 309                           /* allow 00 to be written to the index */
 310
 311                 wr32(&vsi->back->hw,
 312                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 313                                           vsi->base_vector - 1), val);
 314         }
 315 }
 316
 317 /**
 318  * i40e_set_new_dynamic_itr - Find new ITR level
 319  * @rc: structure containing ring performance data
 320  *
 321  * Returns true if ITR changed, false if not
 322  *
 323  * Stores a new ITR value based on packets and byte counts during
 324  * the last interrupt.  The advantage of per interrupt computation
 325  * is faster updates and more accurate ITR for the current traffic
 326  * pattern.  Constants in this function were computed based on
 327  * theoretical maximum wire speed and thresholds were set based on
 328  * testing data as well as attempting to minimize response time
 329  * while increasing bulk throughput.
 330  **/
 331 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 332 {
 333         enum i40e_latency_range new_latency_range = rc->latency_range;
 334         u32 new_itr = rc->itr;
 335         int bytes_per_int;
 336
 337         if (rc->total_packets == 0 || !rc->itr)
 338                 return false;
 339
 340         /* simple throttlerate management
 341          *   0-10MB/s   lowest (100000 ints/s)
 342          *  10-20MB/s   low    (20000 ints/s)
 343          *  20-1249MB/s bulk   (8000 ints/s)
 344          */
 345         bytes_per_int = rc->total_bytes / rc->itr;
 346         switch (new_latency_range) {
 347         case I40E_LOWEST_LATENCY:
 348                 if (bytes_per_int > 10)
 349                         new_latency_range = I40E_LOW_LATENCY;
 350                 break;
 351         case I40E_LOW_LATENCY:
 352                 if (bytes_per_int > 20)
 353                         new_latency_range = I40E_BULK_LATENCY;
 354                 else if (bytes_per_int <= 10)
 355                         new_latency_range = I40E_LOWEST_LATENCY;
 356                 break;
 357         case I40E_BULK_LATENCY:
 358                 if (bytes_per_int <= 20)
 359                         new_latency_range = I40E_LOW_LATENCY;
 360                 break;
 361         default:
 362                 if (bytes_per_int <= 20)
 363                         new_latency_range = I40E_LOW_LATENCY;
 364                 break;
 365         }
 366         rc->latency_range = new_latency_range;
 367
 368         switch (new_latency_range) {
 369         case I40E_LOWEST_LATENCY:
 370                 new_itr = I40E_ITR_100K;
 371                 break;
 372         case I40E_LOW_LATENCY:
 373                 new_itr = I40E_ITR_20K;
 374                 break;
 375         case I40E_BULK_LATENCY:
 376                 new_itr = I40E_ITR_8K;
 377                 break;
 378         default:
 379                 break;
 380         }
 381
 382         rc->total_bytes = 0;
 383         rc->total_packets = 0;
 384
 385         if (new_itr != rc->itr) {
 386                 rc->itr = new_itr;
 387                 return true;
 388         }
 389
 390         return false;
 391 }
 392
 393 /*
 394  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 395  * @tx_ring: the tx ring to set up
 396  *
 397  * Return 0 on success, negative on error
 398  **/
 399 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 400 {
 401         struct device *dev = tx_ring->dev;
 402         int bi_size;
 403
 404         if (!dev)
 405                 return -ENOMEM;
 406
 407         /* warn if we are about to overwrite the pointer */
 408         WARN_ON(tx_ring->tx_bi);
 409         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 410         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 411         if (!tx_ring->tx_bi)
 412                 goto err;
 413
 414         /* round up to nearest 4K */
 415         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 416         /* add u32 for head writeback, align after this takes care of
 417          * guaranteeing this is at least one cache line in size
 418          */
 419         tx_ring->size += sizeof(u32);
 420         tx_ring->size = ALIGN(tx_ring->size, 4096);
 421         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 422                                            &tx_ring->dma, GFP_KERNEL);
 423         if (!tx_ring->desc) {
 424                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 425                          tx_ring->size);
 426                 goto err;
 427         }
 428
 429         tx_ring->next_to_use = 0;
 430         tx_ring->next_to_clean = 0;
 431         return 0;
 432
 433 err:
 434         kfree(tx_ring->tx_bi);
 435         tx_ring->tx_bi = NULL;
 436         return -ENOMEM;
 437 }
 438
 439 /**
 440  * i40evf_clean_rx_ring - Free Rx buffers
 441  * @rx_ring: ring to be cleaned
 442  **/
 443 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 444 {
 445         struct device *dev = rx_ring->dev;
 446         struct i40e_rx_buffer *rx_bi;
 447         unsigned long bi_size;
 448         u16 i;
 449
 450         /* ring already cleared, nothing to do */
 451         if (!rx_ring->rx_bi)
 452                 return;
 453
 454         if (ring_is_ps_enabled(rx_ring)) {
 455                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
 456
 457                 rx_bi = &rx_ring->rx_bi[0];
 458                 if (rx_bi->hdr_buf) {
 459                         dma_free_coherent(dev,
 460                                           bufsz,
 461                                           rx_bi->hdr_buf,
 462                                           rx_bi->dma);
 463                         for (i = 0; i < rx_ring->count; i++) {
 464                                 rx_bi = &rx_ring->rx_bi[i];
 465                                 rx_bi->dma = 0;
 466                                 rx_bi->hdr_buf = NULL;
 467                         }
 468                 }
 469         }
 470         /* Free all the Rx ring sk_buffs */
 471         for (i = 0; i < rx_ring->count; i++) {
 472                 rx_bi = &rx_ring->rx_bi[i];
 473                 if (rx_bi->dma) {
 474                         dma_unmap_single(dev,
 475                                          rx_bi->dma,
 476                                          rx_ring->rx_buf_len,
 477                                          DMA_FROM_DEVICE);
 478                         rx_bi->dma = 0;
 479                 }
 480                 if (rx_bi->skb) {
 481                         dev_kfree_skb(rx_bi->skb);
 482                         rx_bi->skb = NULL;
 483                 }
 484                 if (rx_bi->page) {
 485                         if (rx_bi->page_dma) {
 486                                 dma_unmap_page(dev,
 487                                                rx_bi->page_dma,
 488                                                PAGE_SIZE / 2,
 489                                                DMA_FROM_DEVICE);
 490                                 rx_bi->page_dma = 0;
 491                         }
 492                         __free_page(rx_bi->page);
 493                         rx_bi->page = NULL;
 494                         rx_bi->page_offset = 0;
 495                 }
 496         }
 497
 498         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 499         memset(rx_ring->rx_bi, 0, bi_size);
 500
 501         /* Zero out the descriptor ring */
 502         memset(rx_ring->desc, 0, rx_ring->size);
 503
 504         rx_ring->next_to_clean = 0;
 505         rx_ring->next_to_use = 0;
 506 }
 507
 508 /**
 509  * i40evf_free_rx_resources - Free Rx resources
 510  * @rx_ring: ring to clean the resources from
 511  *
 512  * Free all receive software resources
 513  **/
 514 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 515 {
 516         i40evf_clean_rx_ring(rx_ring);
 517         kfree(rx_ring->rx_bi);
 518         rx_ring->rx_bi = NULL;
 519
 520         if (rx_ring->desc) {
 521                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 522                                   rx_ring->desc, rx_ring->dma);
 523                 rx_ring->desc = NULL;
 524         }
 525 }
 526
 527 /**
 528  * i40evf_alloc_rx_headers - allocate rx header buffers
 529  * @rx_ring: ring to alloc buffers
 530  *
 531  * Allocate rx header buffers for the entire ring. As these are static,
 532  * this is only called when setting up a new ring.
 533  **/
 534 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
 535 {
 536         struct device *dev = rx_ring->dev;
 537         struct i40e_rx_buffer *rx_bi;
 538         dma_addr_t dma;
 539         void *buffer;
 540         int buf_size;
 541         int i;
 542
 543         if (rx_ring->rx_bi[0].hdr_buf)
 544                 return;
 545         /* Make sure the buffers don't cross cache line boundaries. */
 546         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
 547         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
 548                                     &dma, GFP_KERNEL);
 549         if (!buffer)
 550                 return;
 551         for (i = 0; i < rx_ring->count; i++) {
 552                 rx_bi = &rx_ring->rx_bi[i];
 553                 rx_bi->dma = dma + (i * buf_size);
 554                 rx_bi->hdr_buf = buffer + (i * buf_size);
 555         }
 556 }
 557
 558 /**
 559  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 560  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 561  *
 562  * Returns 0 on success, negative on failure
 563  **/
 564 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 565 {
 566         struct device *dev = rx_ring->dev;
 567         int bi_size;
 568
 569         /* warn if we are about to overwrite the pointer */
 570         WARN_ON(rx_ring->rx_bi);
 571         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 572         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 573         if (!rx_ring->rx_bi)
 574                 goto err;
 575
 576         u64_stats_init(&rx_ring->syncp);
 577
 578         /* Round up to nearest 4K */
 579         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 580                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 581                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 582         rx_ring->size = ALIGN(rx_ring->size, 4096);
 583         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 584                                            &rx_ring->dma, GFP_KERNEL);
 585
 586         if (!rx_ring->desc) {
 587                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 588                          rx_ring->size);
 589                 goto err;
 590         }
 591
 592         rx_ring->next_to_clean = 0;
 593         rx_ring->next_to_use = 0;
 594
 595         return 0;
 596 err:
 597         kfree(rx_ring->rx_bi);
 598         rx_ring->rx_bi = NULL;
 599         return -ENOMEM;
 600 }
 601
 602 /**
 603  * i40e_release_rx_desc - Store the new tail and head values
 604  * @rx_ring: ring to bump
 605  * @val: new head index
 606  **/
 607 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 608 {
 609         rx_ring->next_to_use = val;
 610         /* Force memory writes to complete before letting h/w
 611          * know there are new descriptors to fetch.  (Only
 612          * applicable for weak-ordered memory model archs,
 613          * such as IA-64).
 614          */
 615         wmb();
 616         writel(val, rx_ring->tail);
 617 }
 618
 619 /**
 620  * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
 621  * @rx_ring: ring to place buffers on
 622  * @cleaned_count: number of buffers to replace
 623  **/
 624 void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
 625 {
 626         u16 i = rx_ring->next_to_use;
 627         union i40e_rx_desc *rx_desc;
 628         struct i40e_rx_buffer *bi;
 629
 630         /* do nothing if no valid netdev defined */
 631         if (!rx_ring->netdev || !cleaned_count)
 632                 return;
 633
 634         while (cleaned_count--) {
 635                 rx_desc = I40E_RX_DESC(rx_ring, i);
 636                 bi = &rx_ring->rx_bi[i];
 637
 638                 if (bi->skb) /* desc is in use */
 639                         goto no_buffers;
 640                 if (!bi->page) {
 641                         bi->page = alloc_page(GFP_ATOMIC);
 642                         if (!bi->page) {
 643                                 rx_ring->rx_stats.alloc_page_failed++;
 644                                 goto no_buffers;
 645                         }
 646                 }
 647
 648                 if (!bi->page_dma) {
 649                         /* use a half page if we're re-using */
 650                         bi->page_offset ^= PAGE_SIZE / 2;
 651                         bi->page_dma = dma_map_page(rx_ring->dev,
 652                                                     bi->page,
 653                                                     bi->page_offset,
 654                                                     PAGE_SIZE / 2,
 655                                                     DMA_FROM_DEVICE);
 656                         if (dma_mapping_error(rx_ring->dev,
 657                                               bi->page_dma)) {
 658                                 rx_ring->rx_stats.alloc_page_failed++;
 659                                 bi->page_dma = 0;
 660                                 goto no_buffers;
 661                         }
 662                 }
 663
 664                 dma_sync_single_range_for_device(rx_ring->dev,
 665                                                  bi->dma,
 666                                                  0,
 667                                                  rx_ring->rx_hdr_len,
 668                                                  DMA_FROM_DEVICE);
 669                 /* Refresh the desc even if buffer_addrs didn't change
 670                  * because each write-back erases this info.
 671                  */
 672                 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 673                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 674                 i++;
 675                 if (i == rx_ring->count)
 676                         i = 0;
 677         }
 678
 679 no_buffers:
 680         if (rx_ring->next_to_use != i)
 681                 i40e_release_rx_desc(rx_ring, i);
 682 }
 683
 684 /**
 685  * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
 686  * @rx_ring: ring to place buffers on
 687  * @cleaned_count: number of buffers to replace
 688  **/
 689 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
 690 {
 691         u16 i = rx_ring->next_to_use;
 692         union i40e_rx_desc *rx_desc;
 693         struct i40e_rx_buffer *bi;
 694         struct sk_buff *skb;
 695
 696         /* do nothing if no valid netdev defined */
 697         if (!rx_ring->netdev || !cleaned_count)
 698                 return;
 699
 700         while (cleaned_count--) {
 701                 rx_desc = I40E_RX_DESC(rx_ring, i);
 702                 bi = &rx_ring->rx_bi[i];
 703                 skb = bi->skb;
 704
 705                 if (!skb) {
 706                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 707                                                         rx_ring->rx_buf_len);
 708                         if (!skb) {
 709                                 rx_ring->rx_stats.alloc_buff_failed++;
 710                                 goto no_buffers;
 711                         }
 712                         /* initialize queue mapping */
 713                         skb_record_rx_queue(skb, rx_ring->queue_index);
 714                         bi->skb = skb;
 715                 }
 716
 717                 if (!bi->dma) {
 718                         bi->dma = dma_map_single(rx_ring->dev,
 719                                                  skb->data,
 720                                                  rx_ring->rx_buf_len,
 721                                                  DMA_FROM_DEVICE);
 722                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 723                                 rx_ring->rx_stats.alloc_buff_failed++;
 724                                 bi->dma = 0;
 725                                 goto no_buffers;
 726                         }
 727                 }
 728
 729                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 730                 rx_desc->read.hdr_addr = 0;
 731                 i++;
 732                 if (i == rx_ring->count)
 733                         i = 0;
 734         }
 735
 736 no_buffers:
 737         if (rx_ring->next_to_use != i)
 738                 i40e_release_rx_desc(rx_ring, i);
 739 }
 740
 741 /**
 742  * i40e_receive_skb - Send a completed packet up the stack
 743  * @rx_ring:  rx ring in play
 744  * @skb: packet to send up
 745  * @vlan_tag: vlan tag for packet
 746  **/
 747 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 748                              struct sk_buff *skb, u16 vlan_tag)
 749 {
 750         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 751
 752         if (vlan_tag & VLAN_VID_MASK)
 753                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 754
 755         napi_gro_receive(&q_vector->napi, skb);
 756 }
 757
 758 /**
 759  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 760  * @vsi: the VSI we care about
 761  * @skb: skb currently being received and modified
 762  * @rx_status: status value of last descriptor in packet
 763  * @rx_error: error value of last descriptor in packet
 764  * @rx_ptype: ptype value of last descriptor in packet
 765  **/
 766 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 767                                     struct sk_buff *skb,
 768                                     u32 rx_status,
 769                                     u32 rx_error,
 770                                     u16 rx_ptype)
 771 {
 772         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
 773         bool ipv4 = false, ipv6 = false;
 774         bool ipv4_tunnel, ipv6_tunnel;
 775         __wsum rx_udp_csum;
 776         struct iphdr *iph;
 777         __sum16 csum;
 778
 779         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 780                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 781         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 782                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 783
 784         skb->ip_summed = CHECKSUM_NONE;
 785
 786         /* Rx csum enabled and ip headers found? */
 787         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
 788                 return;
 789
 790         /* did the hardware decode the packet and checksum? */
 791         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 792                 return;
 793
 794         /* both known and outer_ip must be set for the below code to work */
 795         if (!(decoded.known && decoded.outer_ip))
 796                 return;
 797
 798         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 799             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
 800                 ipv4 = true;
 801         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 802                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
 803                 ipv6 = true;
 804
 805         if (ipv4 &&
 806             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
 807                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
 808                 goto checksum_fail;
 809
 810         /* likely incorrect csum if alternate IP extension headers found */
 811         if (ipv6 &&
 812             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 813                 /* don't increment checksum err here, non-fatal err */
 814                 return;
 815
 816         /* there was some L4 error, count error and punt packet to the stack */
 817         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
 818                 goto checksum_fail;
 819
 820         /* handle packets that were not able to be checksummed due
 821          * to arrival speed, in this case the stack can compute
 822          * the csum.
 823          */
 824         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
 825                 return;
 826
 827         /* If VXLAN traffic has an outer UDPv4 checksum we need to check
 828          * it in the driver, hardware does not do it for us.
 829          * Since L3L4P bit was set we assume a valid IHL value (>=5)
 830          * so the total length of IPv4 header is IHL*4 bytes
 831          * The UDP_0 bit *may* bet set if the *inner* header is UDP
 832          */
 833         if (ipv4_tunnel) {
 834                 skb->transport_header = skb->mac_header +
 835                                         sizeof(struct ethhdr) +
 836                                         (ip_hdr(skb)->ihl * 4);
 837
 838                 /* Add 4 bytes for VLAN tagged packets */
 839                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
 840                                           skb->protocol == htons(ETH_P_8021AD))
 841                                           ? VLAN_HLEN : 0;
 842
 843                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
 844                     (udp_hdr(skb)->check != 0)) {
 845                         rx_udp_csum = udp_csum(skb);
 846                         iph = ip_hdr(skb);
 847                         csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
 848                                                  (skb->len -
 849                                                   skb_transport_offset(skb)),
 850                                                  IPPROTO_UDP, rx_udp_csum);
 851
 852                         if (udp_hdr(skb)->check != csum)
 853                                 goto checksum_fail;
 854
 855                 } /* else its GRE and so no outer UDP header */
 856         }
 857
 858         skb->ip_summed = CHECKSUM_UNNECESSARY;
 859         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
 860
 861         return;
 862
 863 checksum_fail:
 864         vsi->back->hw_csum_rx_error++;
 865 }
 866
 867 /**
 868  * i40e_rx_hash - returns the hash value from the Rx descriptor
 869  * @ring: descriptor ring
 870  * @rx_desc: specific descriptor
 871  **/
 872 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
 873                                union i40e_rx_desc *rx_desc)
 874 {
 875         const __le64 rss_mask =
 876                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 877                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 878
 879         if ((ring->netdev->features & NETIF_F_RXHASH) &&
 880             (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
 881                 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 882         else
 883                 return 0;
 884 }
 885
 886 /**
 887  * i40e_ptype_to_hash - get a hash type
 888  * @ptype: the ptype value from the descriptor
 889  *
 890  * Returns a hash type to be used by skb_set_hash
 891  **/
 892 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
 893 {
 894         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
 895
 896         if (!decoded.known)
 897                 return PKT_HASH_TYPE_NONE;
 898
 899         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 900             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
 901                 return PKT_HASH_TYPE_L4;
 902         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 903                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
 904                 return PKT_HASH_TYPE_L3;
 905         else
 906                 return PKT_HASH_TYPE_L2;
 907 }
 908
 909 /**
 910  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
 911  * @rx_ring:  rx ring to clean
 912  * @budget:   how many cleans we're allowed
 913  *
 914  * Returns true if there's any budget left (e.g. the clean is finished)
 915  **/
 916 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
 917 {
 918         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 919         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
 920         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
 921         const int current_node = numa_mem_id();
 922         struct i40e_vsi *vsi = rx_ring->vsi;
 923         u16 i = rx_ring->next_to_clean;
 924         union i40e_rx_desc *rx_desc;
 925         u32 rx_error, rx_status;
 926         u8 rx_ptype;
 927         u64 qword;
 928
 929         do {
 930                 struct i40e_rx_buffer *rx_bi;
 931                 struct sk_buff *skb;
 932                 u16 vlan_tag;
 933                 /* return some buffers to hardware, one at a time is too slow */
 934                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
 935                         i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
 936                         cleaned_count = 0;
 937                 }
 938
 939                 i = rx_ring->next_to_clean;
 940                 rx_desc = I40E_RX_DESC(rx_ring, i);
 941                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 942                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
 943                         I40E_RXD_QW1_STATUS_SHIFT;
 944
 945                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
 946                         break;
 947
 948                 /* This memory barrier is needed to keep us from reading
 949                  * any other fields out of the rx_desc until we know the
 950                  * DD bit is set.
 951                  */
 952                 dma_rmb();
 953                 rx_bi = &rx_ring->rx_bi[i];
 954                 skb = rx_bi->skb;
 955                 if (likely(!skb)) {
 956                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 957                                                         rx_ring->rx_hdr_len);
 958                         if (!skb) {
 959                                 rx_ring->rx_stats.alloc_buff_failed++;
 960                                 break;
 961                         }
 962
 963                         /* initialize queue mapping */
 964                         skb_record_rx_queue(skb, rx_ring->queue_index);
 965                         /* we are reusing so sync this buffer for CPU use */
 966                         dma_sync_single_range_for_cpu(rx_ring->dev,
 967                                                       rx_bi->dma,
 968                                                       0,
 969                                                       rx_ring->rx_hdr_len,
 970                                                       DMA_FROM_DEVICE);
 971                 }
 972                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 973                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 974                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
 975                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
 976                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
 977                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
 978
 979                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
 980                            I40E_RXD_QW1_ERROR_SHIFT;
 981                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
 982                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
 983
 984                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
 985                            I40E_RXD_QW1_PTYPE_SHIFT;
 986                 prefetch(rx_bi->page);
 987                 rx_bi->skb = NULL;
 988                 cleaned_count++;
 989                 if (rx_hbo || rx_sph) {
 990                         int len;
 991
 992                         if (rx_hbo)
 993                                 len = I40E_RX_HDR_SIZE;
 994                         else
 995                                 len = rx_header_len;
 996                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
 997                 } else if (skb->len == 0) {
 998                         int len;
 999
1000                         len = (rx_packet_len > skb_headlen(skb) ?
1001                                 skb_headlen(skb) : rx_packet_len);
1002                         memcpy(__skb_put(skb, len),
1003                                rx_bi->page + rx_bi->page_offset,
1004                                len);
1005                         rx_bi->page_offset += len;
1006                         rx_packet_len -= len;
1007                 }
1008
1009                 /* Get the rest of the data if this was a header split */
1010                 if (rx_packet_len) {
1011                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1012                                            rx_bi->page,
1013                                            rx_bi->page_offset,
1014                                            rx_packet_len);
1015
1016                         skb->len += rx_packet_len;
1017                         skb->data_len += rx_packet_len;
1018                         skb->truesize += rx_packet_len;
1019
1020                         if ((page_count(rx_bi->page) == 1) &&
1021                             (page_to_nid(rx_bi->page) == current_node))
1022                                 get_page(rx_bi->page);
1023                         else
1024                                 rx_bi->page = NULL;
1025
1026                         dma_unmap_page(rx_ring->dev,
1027                                        rx_bi->page_dma,
1028                                        PAGE_SIZE / 2,
1029                                        DMA_FROM_DEVICE);
1030                         rx_bi->page_dma = 0;
1031                 }
1032                 I40E_RX_INCREMENT(rx_ring, i);
1033
1034                 if (unlikely(
1035                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1036                         struct i40e_rx_buffer *next_buffer;
1037
1038                         next_buffer = &rx_ring->rx_bi[i];
1039                         next_buffer->skb = skb;
1040                         rx_ring->rx_stats.non_eop_descs++;
1041                         continue;
1042                 }
1043
1044                 /* ERR_MASK will only have valid bits if EOP set */
1045                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1046                         dev_kfree_skb_any(skb);
1047                         continue;
1048                 }
1049
1050                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1051                              i40e_ptype_to_hash(rx_ptype));
1052                 /* probably a little skewed due to removing CRC */
1053                 total_rx_bytes += skb->len;
1054                 total_rx_packets++;
1055
1056                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1057
1058                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1059
1060                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1061                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1062                          : 0;
1063 #ifdef I40E_FCOE
1064                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1065                         dev_kfree_skb_any(skb);
1066                         continue;
1067                 }
1068 #endif
1069                 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
1070                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1071
1072                 rx_desc->wb.qword1.status_error_len = 0;
1073
1074         } while (likely(total_rx_packets < budget));
1075
1076         u64_stats_update_begin(&rx_ring->syncp);
1077         rx_ring->stats.packets += total_rx_packets;
1078         rx_ring->stats.bytes += total_rx_bytes;
1079         u64_stats_update_end(&rx_ring->syncp);
1080         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1081         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1082
1083         return total_rx_packets;
1084 }
1085
1086 /**
1087  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1088  * @rx_ring:  rx ring to clean
1089  * @budget:   how many cleans we're allowed
1090  *
1091  * Returns number of packets cleaned
1092  **/
1093 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1094 {
1095         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1096         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1097         struct i40e_vsi *vsi = rx_ring->vsi;
1098         union i40e_rx_desc *rx_desc;
1099         u32 rx_error, rx_status;
1100         u16 rx_packet_len;
1101         u8 rx_ptype;
1102         u64 qword;
1103         u16 i;
1104
1105         do {
1106                 struct i40e_rx_buffer *rx_bi;
1107                 struct sk_buff *skb;
1108                 u16 vlan_tag;
1109                 /* return some buffers to hardware, one at a time is too slow */
1110                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1111                         i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1112                         cleaned_count = 0;
1113                 }
1114
1115                 i = rx_ring->next_to_clean;
1116                 rx_desc = I40E_RX_DESC(rx_ring, i);
1117                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1118                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1119                         I40E_RXD_QW1_STATUS_SHIFT;
1120
1121                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1122                         break;
1123
1124                 /* This memory barrier is needed to keep us from reading
1125                  * any other fields out of the rx_desc until we know the
1126                  * DD bit is set.
1127                  */
1128                 dma_rmb();
1129
1130                 rx_bi = &rx_ring->rx_bi[i];
1131                 skb = rx_bi->skb;
1132                 prefetch(skb->data);
1133
1134                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1135                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1136
1137                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1138                            I40E_RXD_QW1_ERROR_SHIFT;
1139                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1140
1141                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1142                            I40E_RXD_QW1_PTYPE_SHIFT;
1143                 rx_bi->skb = NULL;
1144                 cleaned_count++;
1145
1146                 /* Get the header and possibly the whole packet
1147                  * If this is an skb from previous receive dma will be 0
1148                  */
1149                 skb_put(skb, rx_packet_len);
1150                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1151                                  DMA_FROM_DEVICE);
1152                 rx_bi->dma = 0;
1153
1154                 I40E_RX_INCREMENT(rx_ring, i);
1155
1156                 if (unlikely(
1157                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1158                         rx_ring->rx_stats.non_eop_descs++;
1159                         continue;
1160                 }
1161
1162                 /* ERR_MASK will only have valid bits if EOP set */
1163                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1164                         dev_kfree_skb_any(skb);
1165                         continue;
1166                 }
1167
1168                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1169                              i40e_ptype_to_hash(rx_ptype));
1170                 /* probably a little skewed due to removing CRC */
1171                 total_rx_bytes += skb->len;
1172                 total_rx_packets++;
1173
1174                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1175
1176                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1177
1178                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1179                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1180                          : 0;
1181                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1182
1183                 rx_desc->wb.qword1.status_error_len = 0;
1184         } while (likely(total_rx_packets < budget));
1185
1186         u64_stats_update_begin(&rx_ring->syncp);
1187         rx_ring->stats.packets += total_rx_packets;
1188         rx_ring->stats.bytes += total_rx_bytes;
1189         u64_stats_update_end(&rx_ring->syncp);
1190         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1191         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1192
1193         return total_rx_packets;
1194 }
1195
1196 static u32 i40e_buildreg_itr(const int type, const u16 itr)
1197 {
1198         u32 val;
1199
1200         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1201               I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1202               (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1203               (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1204
1205         return val;
1206 }
1207
1208 /* a small macro to shorten up some long lines */
1209 #define INTREG I40E_VFINT_DYN_CTLN1
1210
1211 /**
1212  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1213  * @vsi: the VSI we care about
1214  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1215  *
1216  **/
1217 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1218                                           struct i40e_q_vector *q_vector)
1219 {
1220         struct i40e_hw *hw = &vsi->back->hw;
1221         bool rx = false, tx = false;
1222         u32 rxval, txval;
1223         int vector;
1224
1225         vector = (q_vector->v_idx + vsi->base_vector);
1226         rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1227
1228         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1229                 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1230                 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1231         }
1232         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1233                 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1234                 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1235         }
1236         if (rx || tx) {
1237                 /* get the higher of the two ITR adjustments and
1238                  * use the same value for both ITR registers
1239                  * when in adaptive mode (Rx and/or Tx)
1240                  */
1241                 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1242
1243                 q_vector->tx.itr = q_vector->rx.itr = itr;
1244                 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1245                 tx = true;
1246                 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1247                 rx = true;
1248         }
1249
1250         /* only need to enable the interrupt once, but need
1251          * to possibly update both ITR values
1252          */
1253         if (rx) {
1254                 /* set the INTENA_MSK_MASK so that this first write
1255                  * won't actually enable the interrupt, instead just
1256                  * updating the ITR (it's bit 31 PF and VF)
1257                  */
1258                 rxval |= BIT(31);
1259                 /* don't check _DOWN because interrupt isn't being enabled */
1260                 wr32(hw, INTREG(vector - 1), rxval);
1261         }
1262
1263         if (!test_bit(__I40E_DOWN, &vsi->state))
1264                 wr32(hw, INTREG(vector - 1), txval);
1265 }
1266
1267 /**
1268  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1269  * @napi: napi struct with our devices info in it
1270  * @budget: amount of work driver is allowed to do this pass, in packets
1271  *
1272  * This function will clean all queues associated with a q_vector.
1273  *
1274  * Returns the amount of work done
1275  **/
1276 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1277 {
1278         struct i40e_q_vector *q_vector =
1279                                container_of(napi, struct i40e_q_vector, napi);
1280         struct i40e_vsi *vsi = q_vector->vsi;
1281         struct i40e_ring *ring;
1282         bool clean_complete = true;
1283         bool arm_wb = false;
1284         int budget_per_ring;
1285         int work_done = 0;
1286
1287         if (test_bit(__I40E_DOWN, &vsi->state)) {
1288                 napi_complete(napi);
1289                 return 0;
1290         }
1291
1292         /* Since the actual Tx work is minimal, we can give the Tx a larger
1293          * budget and be more aggressive about cleaning up the Tx descriptors.
1294          */
1295         i40e_for_each_ring(ring, q_vector->tx) {
1296                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1297                 arm_wb |= ring->arm_wb;
1298                 ring->arm_wb = false;
1299         }
1300
1301         /* Handle case where we are called by netpoll with a budget of 0 */
1302         if (budget <= 0)
1303                 goto tx_only;
1304
1305         /* We attempt to distribute budget to each Rx queue fairly, but don't
1306          * allow the budget to go below 1 because that would exit polling early.
1307          */
1308         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1309
1310         i40e_for_each_ring(ring, q_vector->rx) {
1311                 int cleaned;
1312
1313                 if (ring_is_ps_enabled(ring))
1314                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1315                 else
1316                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1317
1318                 work_done += cleaned;
1319                 /* if we didn't clean as many as budgeted, we must be done */
1320                 clean_complete &= (budget_per_ring != cleaned);
1321         }
1322
1323         /* If work not completed, return budget and polling will return */
1324         if (!clean_complete) {
1325 tx_only:
1326                 if (arm_wb)
1327                         i40evf_force_wb(vsi, q_vector);
1328                 return budget;
1329         }
1330
1331         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1332                 q_vector->arm_wb_state = false;
1333
1334         /* Work is done so exit the polling mode and re-enable the interrupt */
1335         napi_complete_done(napi, work_done);
1336         i40e_update_enable_itr(vsi, q_vector);
1337         return 0;
1338 }
1339
1340 /**
1341  * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1342  * @skb:     send buffer
1343  * @tx_ring: ring to send buffer on
1344  * @flags:   the tx flags to be set
1345  *
1346  * Checks the skb and set up correspondingly several generic transmit flags
1347  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1348  *
1349  * Returns error code indicate the frame should be dropped upon error and the
1350  * otherwise  returns 0 to indicate the flags has been set properly.
1351  **/
1352 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1353                                                struct i40e_ring *tx_ring,
1354                                                u32 *flags)
1355 {
1356         __be16 protocol = skb->protocol;
1357         u32  tx_flags = 0;
1358
1359         if (protocol == htons(ETH_P_8021Q) &&
1360             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1361                 /* When HW VLAN acceleration is turned off by the user the
1362                  * stack sets the protocol to 8021q so that the driver
1363                  * can take any steps required to support the SW only
1364                  * VLAN handling.  In our case the driver doesn't need
1365                  * to take any further steps so just set the protocol
1366                  * to the encapsulated ethertype.
1367                  */
1368                 skb->protocol = vlan_get_protocol(skb);
1369                 goto out;
1370         }
1371
1372         /* if we have a HW VLAN tag being added, default to the HW one */
1373         if (skb_vlan_tag_present(skb)) {
1374                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1375                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1376         /* else if it is a SW VLAN, check the next protocol and store the tag */
1377         } else if (protocol == htons(ETH_P_8021Q)) {
1378                 struct vlan_hdr *vhdr, _vhdr;
1379
1380                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1381                 if (!vhdr)
1382                         return -EINVAL;
1383
1384                 protocol = vhdr->h_vlan_encapsulated_proto;
1385                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1386                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1387         }
1388
1389 out:
1390         *flags = tx_flags;
1391         return 0;
1392 }
1393
1394 /**
1395  * i40e_tso - set up the tso context descriptor
1396  * @tx_ring:  ptr to the ring to send
1397  * @skb:      ptr to the skb we're sending
1398  * @hdr_len:  ptr to the size of the packet header
1399  * @cd_tunneling: ptr to context descriptor bits
1400  *
1401  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1402  **/
1403 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1404                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss,
1405                     u32 *cd_tunneling)
1406 {
1407         u32 cd_cmd, cd_tso_len, cd_mss;
1408         struct ipv6hdr *ipv6h;
1409         struct tcphdr *tcph;
1410         struct iphdr *iph;
1411         u32 l4len;
1412         int err;
1413
1414         if (!skb_is_gso(skb))
1415                 return 0;
1416
1417         err = skb_cow_head(skb, 0);
1418         if (err < 0)
1419                 return err;
1420
1421         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1422         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1423
1424         if (iph->version == 4) {
1425                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1426                 iph->tot_len = 0;
1427                 iph->check = 0;
1428                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1429                                                  0, IPPROTO_TCP, 0);
1430         } else if (ipv6h->version == 6) {
1431                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1432                 ipv6h->payload_len = 0;
1433                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1434                                                0, IPPROTO_TCP, 0);
1435         }
1436
1437         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1438         *hdr_len = (skb->encapsulation
1439                     ? (skb_inner_transport_header(skb) - skb->data)
1440                     : skb_transport_offset(skb)) + l4len;
1441
1442         /* find the field values */
1443         cd_cmd = I40E_TX_CTX_DESC_TSO;
1444         cd_tso_len = skb->len - *hdr_len;
1445         cd_mss = skb_shinfo(skb)->gso_size;
1446         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1447                                 ((u64)cd_tso_len <<
1448                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1449                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1450         return 1;
1451 }
1452
1453 /**
1454  * i40e_tx_enable_csum - Enable Tx checksum offloads
1455  * @skb: send buffer
1456  * @tx_flags: pointer to Tx flags currently set
1457  * @td_cmd: Tx descriptor command bits to set
1458  * @td_offset: Tx descriptor header offsets to set
1459  * @cd_tunneling: ptr to context desc bits
1460  **/
1461 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1462                                 u32 *td_cmd, u32 *td_offset,
1463                                 struct i40e_ring *tx_ring,
1464                                 u32 *cd_tunneling)
1465 {
1466         struct ipv6hdr *this_ipv6_hdr;
1467         unsigned int this_tcp_hdrlen;
1468         struct iphdr *this_ip_hdr;
1469         u32 network_hdr_len;
1470         u8 l4_hdr = 0;
1471         struct udphdr *oudph;
1472         struct iphdr *oiph;
1473         u32 l4_tunnel = 0;
1474
1475         if (skb->encapsulation) {
1476                 switch (ip_hdr(skb)->protocol) {
1477                 case IPPROTO_UDP:
1478                         oudph = udp_hdr(skb);
1479                         oiph = ip_hdr(skb);
1480                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
1481                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1482                         break;
1483                 default:
1484                         return;
1485                 }
1486                 network_hdr_len = skb_inner_network_header_len(skb);
1487                 this_ip_hdr = inner_ip_hdr(skb);
1488                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1489                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1490
1491                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1492                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
1493                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1494                                 ip_hdr(skb)->check = 0;
1495                         } else {
1496                                 *cd_tunneling |=
1497                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1498                         }
1499                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1500                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1501                         if (*tx_flags & I40E_TX_FLAGS_TSO)
1502                                 ip_hdr(skb)->check = 0;
1503                 }
1504
1505                 /* Now set the ctx descriptor fields */
1506                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1507                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
1508                                    l4_tunnel                             |
1509                                    ((skb_inner_network_offset(skb) -
1510                                         skb_transport_offset(skb)) >> 1) <<
1511                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1512                 if (this_ip_hdr->version == 6) {
1513                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1514                         *tx_flags |= I40E_TX_FLAGS_IPV6;
1515                 }
1516
1517
1518                 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1519                     (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
1520                     (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1521                         oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1522                                         oiph->daddr,
1523                                         (skb->len - skb_transport_offset(skb)),
1524                                         IPPROTO_UDP, 0);
1525                         *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1526                 }
1527         } else {
1528                 network_hdr_len = skb_network_header_len(skb);
1529                 this_ip_hdr = ip_hdr(skb);
1530                 this_ipv6_hdr = ipv6_hdr(skb);
1531                 this_tcp_hdrlen = tcp_hdrlen(skb);
1532         }
1533
1534         /* Enable IP checksum offloads */
1535         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1536                 l4_hdr = this_ip_hdr->protocol;
1537                 /* the stack computes the IP header already, the only time we
1538                  * need the hardware to recompute it is in the case of TSO.
1539                  */
1540                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1541                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1542                         this_ip_hdr->check = 0;
1543                 } else {
1544                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1545                 }
1546                 /* Now set the td_offset for IP header length */
1547                 *td_offset = (network_hdr_len >> 2) <<
1548                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1549         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1550                 l4_hdr = this_ipv6_hdr->nexthdr;
1551                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1552                 /* Now set the td_offset for IP header length */
1553                 *td_offset = (network_hdr_len >> 2) <<
1554                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1555         }
1556         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1557         *td_offset |= (skb_network_offset(skb) >> 1) <<
1558                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1559
1560         /* Enable L4 checksum offloads */
1561         switch (l4_hdr) {
1562         case IPPROTO_TCP:
1563                 /* enable checksum offloads */
1564                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1565                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1566                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1567                 break;
1568         case IPPROTO_SCTP:
1569                 /* enable SCTP checksum offload */
1570                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1571                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1572                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1573                 break;
1574         case IPPROTO_UDP:
1575                 /* enable UDP checksum offload */
1576                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1577                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1578                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1579                 break;
1580         default:
1581                 break;
1582         }
1583 }
1584
1585 /**
1586  * i40e_create_tx_ctx Build the Tx context descriptor
1587  * @tx_ring:  ring to create the descriptor on
1588  * @cd_type_cmd_tso_mss: Quad Word 1
1589  * @cd_tunneling: Quad Word 0 - bits 0-31
1590  * @cd_l2tag2: Quad Word 0 - bits 32-63
1591  **/
1592 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1593                                const u64 cd_type_cmd_tso_mss,
1594                                const u32 cd_tunneling, const u32 cd_l2tag2)
1595 {
1596         struct i40e_tx_context_desc *context_desc;
1597         int i = tx_ring->next_to_use;
1598
1599         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1600             !cd_tunneling && !cd_l2tag2)
1601                 return;
1602
1603         /* grab the next descriptor */
1604         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1605
1606         i++;
1607         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1608
1609         /* cpu_to_le32 and assign to struct fields */
1610         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1611         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1612         context_desc->rsvd = cpu_to_le16(0);
1613         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1614 }
1615
1616  /**
1617  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1618  * @skb:      send buffer
1619  * @tx_flags: collected send information
1620  *
1621  * Note: Our HW can't scatter-gather more than 8 fragments to build
1622  * a packet on the wire and so we need to figure out the cases where we
1623  * need to linearize the skb.
1624  **/
1625 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
1626 {
1627         struct skb_frag_struct *frag;
1628         bool linearize = false;
1629         unsigned int size = 0;
1630         u16 num_frags;
1631         u16 gso_segs;
1632
1633         num_frags = skb_shinfo(skb)->nr_frags;
1634         gso_segs = skb_shinfo(skb)->gso_segs;
1635
1636         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1637                 u16 j = 0;
1638
1639                 if (num_frags < (I40E_MAX_BUFFER_TXD))
1640                         goto linearize_chk_done;
1641                 /* try the simple math, if we have too many frags per segment */
1642                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1643                     I40E_MAX_BUFFER_TXD) {
1644                         linearize = true;
1645                         goto linearize_chk_done;
1646                 }
1647                 frag = &skb_shinfo(skb)->frags[0];
1648                 /* we might still have more fragments per segment */
1649                 do {
1650                         size += skb_frag_size(frag);
1651                         frag++; j++;
1652                         if ((size >= skb_shinfo(skb)->gso_size) &&
1653                             (j < I40E_MAX_BUFFER_TXD)) {
1654                                 size = (size % skb_shinfo(skb)->gso_size);
1655                                 j = (size) ? 1 : 0;
1656                         }
1657                         if (j == I40E_MAX_BUFFER_TXD) {
1658                                 linearize = true;
1659                                 break;
1660                         }
1661                         num_frags--;
1662                 } while (num_frags);
1663         } else {
1664                 if (num_frags >= I40E_MAX_BUFFER_TXD)
1665                         linearize = true;
1666         }
1667
1668 linearize_chk_done:
1669         return linearize;
1670 }
1671
1672 /**
1673  * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1674  * @tx_ring: the ring to be checked
1675  * @size:    the size buffer we want to assure is available
1676  *
1677  * Returns -EBUSY if a stop is needed, else 0
1678  **/
1679 static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1680 {
1681         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1682         /* Memory barrier before checking head and tail */
1683         smp_mb();
1684
1685         /* Check again in a case another CPU has just made room available. */
1686         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1687                 return -EBUSY;
1688
1689         /* A reprieve! - use start_queue because it doesn't call schedule */
1690         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1691         ++tx_ring->tx_stats.restart_queue;
1692         return 0;
1693 }
1694
1695 /**
1696  * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1697  * @tx_ring: the ring to be checked
1698  * @size:    the size buffer we want to assure is available
1699  *
1700  * Returns 0 if stop is not needed
1701  **/
1702 static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1703 {
1704         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1705                 return 0;
1706         return __i40evf_maybe_stop_tx(tx_ring, size);
1707 }
1708
1709 /**
1710  * i40evf_tx_map - Build the Tx descriptor
1711  * @tx_ring:  ring to send buffer on
1712  * @skb:      send buffer
1713  * @first:    first buffer info buffer to use
1714  * @tx_flags: collected send information
1715  * @hdr_len:  size of the packet header
1716  * @td_cmd:   the command field in the descriptor
1717  * @td_offset: offset for checksum or crc
1718  **/
1719 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1720                                  struct i40e_tx_buffer *first, u32 tx_flags,
1721                                  const u8 hdr_len, u32 td_cmd, u32 td_offset)
1722 {
1723         unsigned int data_len = skb->data_len;
1724         unsigned int size = skb_headlen(skb);
1725         struct skb_frag_struct *frag;
1726         struct i40e_tx_buffer *tx_bi;
1727         struct i40e_tx_desc *tx_desc;
1728         u16 i = tx_ring->next_to_use;
1729         u32 td_tag = 0;
1730         dma_addr_t dma;
1731         u16 gso_segs;
1732
1733         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1734                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1735                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1736                          I40E_TX_FLAGS_VLAN_SHIFT;
1737         }
1738
1739         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1740                 gso_segs = skb_shinfo(skb)->gso_segs;
1741         else
1742                 gso_segs = 1;
1743
1744         /* multiply data chunks by size of headers */
1745         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1746         first->gso_segs = gso_segs;
1747         first->skb = skb;
1748         first->tx_flags = tx_flags;
1749
1750         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1751
1752         tx_desc = I40E_TX_DESC(tx_ring, i);
1753         tx_bi = first;
1754
1755         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1756                 if (dma_mapping_error(tx_ring->dev, dma))
1757                         goto dma_error;
1758
1759                 /* record length, and DMA address */
1760                 dma_unmap_len_set(tx_bi, len, size);
1761                 dma_unmap_addr_set(tx_bi, dma, dma);
1762
1763                 tx_desc->buffer_addr = cpu_to_le64(dma);
1764
1765                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1766                         tx_desc->cmd_type_offset_bsz =
1767                                 build_ctob(td_cmd, td_offset,
1768                                            I40E_MAX_DATA_PER_TXD, td_tag);
1769
1770                         tx_desc++;
1771                         i++;
1772                         if (i == tx_ring->count) {
1773                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1774                                 i = 0;
1775                         }
1776
1777                         dma += I40E_MAX_DATA_PER_TXD;
1778                         size -= I40E_MAX_DATA_PER_TXD;
1779
1780                         tx_desc->buffer_addr = cpu_to_le64(dma);
1781                 }
1782
1783                 if (likely(!data_len))
1784                         break;
1785
1786                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1787                                                           size, td_tag);
1788
1789                 tx_desc++;
1790                 i++;
1791                 if (i == tx_ring->count) {
1792                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1793                         i = 0;
1794                 }
1795
1796                 size = skb_frag_size(frag);
1797                 data_len -= size;
1798
1799                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1800                                        DMA_TO_DEVICE);
1801
1802                 tx_bi = &tx_ring->tx_bi[i];
1803         }
1804
1805         /* Place RS bit on last descriptor of any packet that spans across the
1806          * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1807          */
1808 #define WB_STRIDE 0x3
1809         if (((i & WB_STRIDE) != WB_STRIDE) &&
1810             (first <= &tx_ring->tx_bi[i]) &&
1811             (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1812                 tx_desc->cmd_type_offset_bsz =
1813                         build_ctob(td_cmd, td_offset, size, td_tag) |
1814                         cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1815                                          I40E_TXD_QW1_CMD_SHIFT);
1816         } else {
1817                 tx_desc->cmd_type_offset_bsz =
1818                         build_ctob(td_cmd, td_offset, size, td_tag) |
1819                         cpu_to_le64((u64)I40E_TXD_CMD <<
1820                                          I40E_TXD_QW1_CMD_SHIFT);
1821         }
1822
1823         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1824                                                  tx_ring->queue_index),
1825                              first->bytecount);
1826
1827         /* Force memory writes to complete before letting h/w
1828          * know there are new descriptors to fetch.  (Only
1829          * applicable for weak-ordered memory model archs,
1830          * such as IA-64).
1831          */
1832         wmb();
1833
1834         /* set next_to_watch value indicating a packet is present */
1835         first->next_to_watch = tx_desc;
1836
1837         i++;
1838         if (i == tx_ring->count)
1839                 i = 0;
1840
1841         tx_ring->next_to_use = i;
1842
1843         i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
1844         /* notify HW of packet */
1845         if (!skb->xmit_more ||
1846             netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1847                                                    tx_ring->queue_index)))
1848                 writel(i, tx_ring->tail);
1849         else
1850                 prefetchw(tx_desc + 1);
1851
1852         return;
1853
1854 dma_error:
1855         dev_info(tx_ring->dev, "TX DMA map failed\n");
1856
1857         /* clear dma mappings for failed tx_bi map */
1858         for (;;) {
1859                 tx_bi = &tx_ring->tx_bi[i];
1860                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1861                 if (tx_bi == first)
1862                         break;
1863                 if (i == 0)
1864                         i = tx_ring->count;
1865                 i--;
1866         }
1867
1868         tx_ring->next_to_use = i;
1869 }
1870
1871 /**
1872  * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
1873  * @skb:     send buffer
1874  * @tx_ring: ring to send buffer on
1875  *
1876  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1877  * there is not enough descriptors available in this ring since we need at least
1878  * one descriptor.
1879  **/
1880 static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1881                                                struct i40e_ring *tx_ring)
1882 {
1883         unsigned int f;
1884         int count = 0;
1885
1886         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1887          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1888          *       + 4 desc gap to avoid the cache line where head is,
1889          *       + 1 desc for context descriptor,
1890          * otherwise try next time
1891          */
1892         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1893                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1894
1895         count += TXD_USE_COUNT(skb_headlen(skb));
1896         if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1897                 tx_ring->tx_stats.tx_busy++;
1898                 return 0;
1899         }
1900         return count;
1901 }
1902
1903 /**
1904  * i40e_xmit_frame_ring - Sends buffer on Tx ring
1905  * @skb:     send buffer
1906  * @tx_ring: ring to send buffer on
1907  *
1908  * Returns NETDEV_TX_OK if sent, else an error code
1909  **/
1910 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1911                                         struct i40e_ring *tx_ring)
1912 {
1913         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1914         u32 cd_tunneling = 0, cd_l2tag2 = 0;
1915         struct i40e_tx_buffer *first;
1916         u32 td_offset = 0;
1917         u32 tx_flags = 0;
1918         __be16 protocol;
1919         u32 td_cmd = 0;
1920         u8 hdr_len = 0;
1921         int tso;
1922
1923         if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
1924                 return NETDEV_TX_BUSY;
1925
1926         /* prepare the xmit flags */
1927         if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1928                 goto out_drop;
1929
1930         /* obtain protocol of skb */
1931         protocol = vlan_get_protocol(skb);
1932
1933         /* record the location of the first descriptor for this packet */
1934         first = &tx_ring->tx_bi[tx_ring->next_to_use];
1935
1936         /* setup IPv4/IPv6 offloads */
1937         if (protocol == htons(ETH_P_IP))
1938                 tx_flags |= I40E_TX_FLAGS_IPV4;
1939         else if (protocol == htons(ETH_P_IPV6))
1940                 tx_flags |= I40E_TX_FLAGS_IPV6;
1941
1942         tso = i40e_tso(tx_ring, skb, &hdr_len,
1943                        &cd_type_cmd_tso_mss, &cd_tunneling);
1944
1945         if (tso < 0)
1946                 goto out_drop;
1947         else if (tso)
1948                 tx_flags |= I40E_TX_FLAGS_TSO;
1949
1950         if (i40e_chk_linearize(skb, tx_flags)) {
1951                 if (skb_linearize(skb))
1952                         goto out_drop;
1953                 tx_ring->tx_stats.tx_linearize++;
1954         }
1955         skb_tx_timestamp(skb);
1956
1957         /* always enable CRC insertion offload */
1958         td_cmd |= I40E_TX_DESC_CMD_ICRC;
1959
1960         /* Always offload the checksum, since it's in the data descriptor */
1961         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1962                 tx_flags |= I40E_TX_FLAGS_CSUM;
1963
1964                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
1965                                     tx_ring, &cd_tunneling);
1966         }
1967
1968         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1969                            cd_tunneling, cd_l2tag2);
1970
1971         i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1972                       td_cmd, td_offset);
1973
1974         return NETDEV_TX_OK;
1975
1976 out_drop:
1977         dev_kfree_skb_any(skb);
1978         return NETDEV_TX_OK;
1979 }
1980
1981 /**
1982  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1983  * @skb:    send buffer
1984  * @netdev: network interface device structure
1985  *
1986  * Returns NETDEV_TX_OK if sent, else an error code
1987  **/
1988 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1989 {
1990         struct i40evf_adapter *adapter = netdev_priv(netdev);
1991         struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1992
1993         /* hardware can't handle really short frames, hardware padding works
1994          * beyond this point
1995          */
1996         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1997                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1998                         return NETDEV_TX_OK;
1999                 skb->len = I40E_MIN_TX_LEN;
2000                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2001         }
2002
2003         return i40e_xmit_frame_ring(skb, tx_ring);
2004 }