drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28
  29 #include "i40evf.h"
  30 #include "i40e_prototype.h"
  31
  32 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  33                                 u32 td_tag)
  34 {
  35         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  36                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  37                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  38                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  39                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  40 }
  41
  42 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  43
  44 /**
  45  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  46  * @ring:      the ring that owns the buffer
  47  * @tx_buffer: the buffer to free
  48  **/
  49 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  50                                             struct i40e_tx_buffer *tx_buffer)
  51 {
  52         if (tx_buffer->skb) {
  53                 dev_kfree_skb_any(tx_buffer->skb);
  54                 if (dma_unmap_len(tx_buffer, len))
  55                         dma_unmap_single(ring->dev,
  56                                          dma_unmap_addr(tx_buffer, dma),
  57                                          dma_unmap_len(tx_buffer, len),
  58                                          DMA_TO_DEVICE);
  59         } else if (dma_unmap_len(tx_buffer, len)) {
  60                 dma_unmap_page(ring->dev,
  61                                dma_unmap_addr(tx_buffer, dma),
  62                                dma_unmap_len(tx_buffer, len),
  63                                DMA_TO_DEVICE);
  64         }
  65         tx_buffer->next_to_watch = NULL;
  66         tx_buffer->skb = NULL;
  67         dma_unmap_len_set(tx_buffer, len, 0);
  68         /* tx_buffer must be completely set up in the transmit path */
  69 }
  70
  71 /**
  72  * i40evf_clean_tx_ring - Free any empty Tx buffers
  73  * @tx_ring: ring to be cleaned
  74  **/
  75 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  76 {
  77         unsigned long bi_size;
  78         u16 i;
  79
  80         /* ring already cleared, nothing to do */
  81         if (!tx_ring->tx_bi)
  82                 return;
  83
  84         /* Free all the Tx ring sk_buffs */
  85         for (i = 0; i < tx_ring->count; i++)
  86                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  87
  88         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  89         memset(tx_ring->tx_bi, 0, bi_size);
  90
  91         /* Zero out the descriptor ring */
  92         memset(tx_ring->desc, 0, tx_ring->size);
  93
  94         tx_ring->next_to_use = 0;
  95         tx_ring->next_to_clean = 0;
  96
  97         if (!tx_ring->netdev)
  98                 return;
  99
 100         /* cleanup Tx queue statistics */
 101         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 102                                                   tx_ring->queue_index));
 103 }
 104
 105 /**
 106  * i40evf_free_tx_resources - Free Tx resources per queue
 107  * @tx_ring: Tx descriptor ring for a specific queue
 108  *
 109  * Free all transmit software resources
 110  **/
 111 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 112 {
 113         i40evf_clean_tx_ring(tx_ring);
 114         kfree(tx_ring->tx_bi);
 115         tx_ring->tx_bi = NULL;
 116
 117         if (tx_ring->desc) {
 118                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 119                                   tx_ring->desc, tx_ring->dma);
 120                 tx_ring->desc = NULL;
 121         }
 122 }
 123
 124 /**
 125  * i40e_get_tx_pending - how many tx descriptors not processed
 126  * @tx_ring: the ring of descriptors
 127  *
 128  * Since there is no access to the ring head register
 129  * in XL710, we need to use our local copies
 130  **/
 131 static u32 i40e_get_tx_pending(struct i40e_ring *ring)
 132 {
 133         u32 ntu = ((ring->next_to_clean <= ring->next_to_use)
 134                         ? ring->next_to_use
 135                         : ring->next_to_use + ring->count);
 136         return ntu - ring->next_to_clean;
 137 }
 138
 139 /**
 140  * i40e_check_tx_hang - Is there a hang in the Tx queue
 141  * @tx_ring: the ring of descriptors
 142  **/
 143 static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
 144 {
 145         u32 tx_pending = i40e_get_tx_pending(tx_ring);
 146         bool ret = false;
 147
 148         clear_check_for_tx_hang(tx_ring);
 149
 150         /* Check for a hung queue, but be thorough. This verifies
 151          * that a transmit has been completed since the previous
 152          * check AND there is at least one packet pending. The
 153          * ARMED bit is set to indicate a potential hang. The
 154          * bit is cleared if a pause frame is received to remove
 155          * false hang detection due to PFC or 802.3x frames. By
 156          * requiring this to fail twice we avoid races with
 157          * PFC clearing the ARMED bit and conditions where we
 158          * run the check_tx_hang logic with a transmit completion
 159          * pending but without time to complete it yet.
 160          */
 161         if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) &&
 162             tx_pending) {
 163                 /* make sure it is true for two checks in a row */
 164                 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
 165                                        &tx_ring->state);
 166         } else {
 167                 /* update completed stats and disarm the hang check */
 168                 tx_ring->tx_stats.tx_done_old = tx_ring->stats.packets;
 169                 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
 170         }
 171
 172         return ret;
 173 }
 174
 175 /**
 176  * i40e_get_head - Retrieve head from head writeback
 177  * @tx_ring:  tx ring to fetch head of
 178  *
 179  * Returns value of Tx ring head based on value stored
 180  * in head write-back location
 181  **/
 182 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
 183 {
 184         void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
 185
 186         return le32_to_cpu(*(volatile __le32 *)head);
 187 }
 188
 189 /**
 190  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 191  * @tx_ring:  tx ring to clean
 192  * @budget:   how many cleans we're allowed
 193  *
 194  * Returns true if there's any budget left (e.g. the clean is finished)
 195  **/
 196 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 197 {
 198         u16 i = tx_ring->next_to_clean;
 199         struct i40e_tx_buffer *tx_buf;
 200         struct i40e_tx_desc *tx_head;
 201         struct i40e_tx_desc *tx_desc;
 202         unsigned int total_packets = 0;
 203         unsigned int total_bytes = 0;
 204
 205         tx_buf = &tx_ring->tx_bi[i];
 206         tx_desc = I40E_TX_DESC(tx_ring, i);
 207         i -= tx_ring->count;
 208
 209         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 210
 211         do {
 212                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 213
 214                 /* if next_to_watch is not set then there is no work pending */
 215                 if (!eop_desc)
 216                         break;
 217
 218                 /* prevent any other reads prior to eop_desc */
 219                 read_barrier_depends();
 220
 221                 /* we have caught up to head, no work left to do */
 222                 if (tx_head == tx_desc)
 223                         break;
 224
 225                 /* clear next_to_watch to prevent false hangs */
 226                 tx_buf->next_to_watch = NULL;
 227
 228                 /* update the statistics for this packet */
 229                 total_bytes += tx_buf->bytecount;
 230                 total_packets += tx_buf->gso_segs;
 231
 232                 /* free the skb */
 233                 dev_kfree_skb_any(tx_buf->skb);
 234
 235                 /* unmap skb header data */
 236                 dma_unmap_single(tx_ring->dev,
 237                                  dma_unmap_addr(tx_buf, dma),
 238                                  dma_unmap_len(tx_buf, len),
 239                                  DMA_TO_DEVICE);
 240
 241                 /* clear tx_buffer data */
 242                 tx_buf->skb = NULL;
 243                 dma_unmap_len_set(tx_buf, len, 0);
 244
 245                 /* unmap remaining buffers */
 246                 while (tx_desc != eop_desc) {
 247
 248                         tx_buf++;
 249                         tx_desc++;
 250                         i++;
 251                         if (unlikely(!i)) {
 252                                 i -= tx_ring->count;
 253                                 tx_buf = tx_ring->tx_bi;
 254                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 255                         }
 256
 257                         /* unmap any remaining paged data */
 258                         if (dma_unmap_len(tx_buf, len)) {
 259                                 dma_unmap_page(tx_ring->dev,
 260                                                dma_unmap_addr(tx_buf, dma),
 261                                                dma_unmap_len(tx_buf, len),
 262                                                DMA_TO_DEVICE);
 263                                 dma_unmap_len_set(tx_buf, len, 0);
 264                         }
 265                 }
 266
 267                 /* move us one more past the eop_desc for start of next pkt */
 268                 tx_buf++;
 269                 tx_desc++;
 270                 i++;
 271                 if (unlikely(!i)) {
 272                         i -= tx_ring->count;
 273                         tx_buf = tx_ring->tx_bi;
 274                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 275                 }
 276
 277                 /* update budget accounting */
 278                 budget--;
 279         } while (likely(budget));
 280
 281         i += tx_ring->count;
 282         tx_ring->next_to_clean = i;
 283         u64_stats_update_begin(&tx_ring->syncp);
 284         tx_ring->stats.bytes += total_bytes;
 285         tx_ring->stats.packets += total_packets;
 286         u64_stats_update_end(&tx_ring->syncp);
 287         tx_ring->q_vector->tx.total_bytes += total_bytes;
 288         tx_ring->q_vector->tx.total_packets += total_packets;
 289
 290         if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
 291                 /* schedule immediate reset if we believe we hung */
 292                 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
 293                          "  VSI                  <%d>\n"
 294                          "  Tx Queue             <%d>\n"
 295                          "  next_to_use          <%x>\n"
 296                          "  next_to_clean        <%x>\n",
 297                          tx_ring->vsi->seid,
 298                          tx_ring->queue_index,
 299                          tx_ring->next_to_use, i);
 300                 dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n"
 301                          "  time_stamp           <%lx>\n"
 302                          "  jiffies              <%lx>\n",
 303                          tx_ring->tx_bi[i].time_stamp, jiffies);
 304
 305                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 306
 307                 dev_info(tx_ring->dev,
 308                          "tx hang detected on queue %d, resetting adapter\n",
 309                          tx_ring->queue_index);
 310
 311                 tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev);
 312
 313                 /* the adapter is about to reset, no point in enabling stuff */
 314                 return true;
 315         }
 316
 317         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 318                                                       tx_ring->queue_index),
 319                                   total_packets, total_bytes);
 320
 321 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 322         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 323                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 324                 /* Make sure that anybody stopping the queue after this
 325                  * sees the new next_to_clean.
 326                  */
 327                 smp_mb();
 328                 if (__netif_subqueue_stopped(tx_ring->netdev,
 329                                              tx_ring->queue_index) &&
 330                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 331                         netif_wake_subqueue(tx_ring->netdev,
 332                                             tx_ring->queue_index);
 333                         ++tx_ring->tx_stats.restart_queue;
 334                 }
 335         }
 336
 337         return budget > 0;
 338 }
 339
 340 /**
 341  * i40e_set_new_dynamic_itr - Find new ITR level
 342  * @rc: structure containing ring performance data
 343  *
 344  * Stores a new ITR value based on packets and byte counts during
 345  * the last interrupt.  The advantage of per interrupt computation
 346  * is faster updates and more accurate ITR for the current traffic
 347  * pattern.  Constants in this function were computed based on
 348  * theoretical maximum wire speed and thresholds were set based on
 349  * testing data as well as attempting to minimize response time
 350  * while increasing bulk throughput.
 351  **/
 352 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 353 {
 354         enum i40e_latency_range new_latency_range = rc->latency_range;
 355         u32 new_itr = rc->itr;
 356         int bytes_per_int;
 357
 358         if (rc->total_packets == 0 || !rc->itr)
 359                 return;
 360
 361         /* simple throttlerate management
 362          *   0-10MB/s   lowest (100000 ints/s)
 363          *  10-20MB/s   low    (20000 ints/s)
 364          *  20-1249MB/s bulk   (8000 ints/s)
 365          */
 366         bytes_per_int = rc->total_bytes / rc->itr;
 367         switch (rc->itr) {
 368         case I40E_LOWEST_LATENCY:
 369                 if (bytes_per_int > 10)
 370                         new_latency_range = I40E_LOW_LATENCY;
 371                 break;
 372         case I40E_LOW_LATENCY:
 373                 if (bytes_per_int > 20)
 374                         new_latency_range = I40E_BULK_LATENCY;
 375                 else if (bytes_per_int <= 10)
 376                         new_latency_range = I40E_LOWEST_LATENCY;
 377                 break;
 378         case I40E_BULK_LATENCY:
 379                 if (bytes_per_int <= 20)
 380                         rc->latency_range = I40E_LOW_LATENCY;
 381                 break;
 382         }
 383
 384         switch (new_latency_range) {
 385         case I40E_LOWEST_LATENCY:
 386                 new_itr = I40E_ITR_100K;
 387                 break;
 388         case I40E_LOW_LATENCY:
 389                 new_itr = I40E_ITR_20K;
 390                 break;
 391         case I40E_BULK_LATENCY:
 392                 new_itr = I40E_ITR_8K;
 393                 break;
 394         default:
 395                 break;
 396         }
 397
 398         if (new_itr != rc->itr) {
 399                 /* do an exponential smoothing */
 400                 new_itr = (10 * new_itr * rc->itr) /
 401                           ((9 * new_itr) + rc->itr);
 402                 rc->itr = new_itr & I40E_MAX_ITR;
 403         }
 404
 405         rc->total_bytes = 0;
 406         rc->total_packets = 0;
 407 }
 408
 409 /**
 410  * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
 411  * @q_vector: the vector to adjust
 412  **/
 413 static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)
 414 {
 415         u16 vector = q_vector->vsi->base_vector + q_vector->v_idx;
 416         struct i40e_hw *hw = &q_vector->vsi->back->hw;
 417         u32 reg_addr;
 418         u16 old_itr;
 419
 420         reg_addr = I40E_VFINT_ITRN1(I40E_RX_ITR, vector - 1);
 421         old_itr = q_vector->rx.itr;
 422         i40e_set_new_dynamic_itr(&q_vector->rx);
 423         if (old_itr != q_vector->rx.itr)
 424                 wr32(hw, reg_addr, q_vector->rx.itr);
 425
 426         reg_addr = I40E_VFINT_ITRN1(I40E_TX_ITR, vector - 1);
 427         old_itr = q_vector->tx.itr;
 428         i40e_set_new_dynamic_itr(&q_vector->tx);
 429         if (old_itr != q_vector->tx.itr)
 430                 wr32(hw, reg_addr, q_vector->tx.itr);
 431 }
 432
 433 /**
 434  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 435  * @tx_ring: the tx ring to set up
 436  *
 437  * Return 0 on success, negative on error
 438  **/
 439 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 440 {
 441         struct device *dev = tx_ring->dev;
 442         int bi_size;
 443
 444         if (!dev)
 445                 return -ENOMEM;
 446
 447         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 448         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 449         if (!tx_ring->tx_bi)
 450                 goto err;
 451
 452         /* round up to nearest 4K */
 453         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 454         /* add u32 for head writeback, align after this takes care of
 455          * guaranteeing this is at least one cache line in size
 456          */
 457         tx_ring->size += sizeof(u32);
 458         tx_ring->size = ALIGN(tx_ring->size, 4096);
 459         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 460                                            &tx_ring->dma, GFP_KERNEL);
 461         if (!tx_ring->desc) {
 462                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 463                          tx_ring->size);
 464                 goto err;
 465         }
 466
 467         tx_ring->next_to_use = 0;
 468         tx_ring->next_to_clean = 0;
 469         return 0;
 470
 471 err:
 472         kfree(tx_ring->tx_bi);
 473         tx_ring->tx_bi = NULL;
 474         return -ENOMEM;
 475 }
 476
 477 /**
 478  * i40evf_clean_rx_ring - Free Rx buffers
 479  * @rx_ring: ring to be cleaned
 480  **/
 481 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 482 {
 483         struct device *dev = rx_ring->dev;
 484         struct i40e_rx_buffer *rx_bi;
 485         unsigned long bi_size;
 486         u16 i;
 487
 488         /* ring already cleared, nothing to do */
 489         if (!rx_ring->rx_bi)
 490                 return;
 491
 492         /* Free all the Rx ring sk_buffs */
 493         for (i = 0; i < rx_ring->count; i++) {
 494                 rx_bi = &rx_ring->rx_bi[i];
 495                 if (rx_bi->dma) {
 496                         dma_unmap_single(dev,
 497                                          rx_bi->dma,
 498                                          rx_ring->rx_buf_len,
 499                                          DMA_FROM_DEVICE);
 500                         rx_bi->dma = 0;
 501                 }
 502                 if (rx_bi->skb) {
 503                         dev_kfree_skb(rx_bi->skb);
 504                         rx_bi->skb = NULL;
 505                 }
 506                 if (rx_bi->page) {
 507                         if (rx_bi->page_dma) {
 508                                 dma_unmap_page(dev,
 509                                                rx_bi->page_dma,
 510                                                PAGE_SIZE / 2,
 511                                                DMA_FROM_DEVICE);
 512                                 rx_bi->page_dma = 0;
 513                         }
 514                         __free_page(rx_bi->page);
 515                         rx_bi->page = NULL;
 516                         rx_bi->page_offset = 0;
 517                 }
 518         }
 519
 520         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 521         memset(rx_ring->rx_bi, 0, bi_size);
 522
 523         /* Zero out the descriptor ring */
 524         memset(rx_ring->desc, 0, rx_ring->size);
 525
 526         rx_ring->next_to_clean = 0;
 527         rx_ring->next_to_use = 0;
 528 }
 529
 530 /**
 531  * i40evf_free_rx_resources - Free Rx resources
 532  * @rx_ring: ring to clean the resources from
 533  *
 534  * Free all receive software resources
 535  **/
 536 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 537 {
 538         i40evf_clean_rx_ring(rx_ring);
 539         kfree(rx_ring->rx_bi);
 540         rx_ring->rx_bi = NULL;
 541
 542         if (rx_ring->desc) {
 543                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 544                                   rx_ring->desc, rx_ring->dma);
 545                 rx_ring->desc = NULL;
 546         }
 547 }
 548
 549 /**
 550  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 551  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 552  *
 553  * Returns 0 on success, negative on failure
 554  **/
 555 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 556 {
 557         struct device *dev = rx_ring->dev;
 558         int bi_size;
 559
 560         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 561         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 562         if (!rx_ring->rx_bi)
 563                 goto err;
 564
 565         /* Round up to nearest 4K */
 566         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 567                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 568                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 569         rx_ring->size = ALIGN(rx_ring->size, 4096);
 570         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 571                                            &rx_ring->dma, GFP_KERNEL);
 572
 573         if (!rx_ring->desc) {
 574                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 575                          rx_ring->size);
 576                 goto err;
 577         }
 578
 579         rx_ring->next_to_clean = 0;
 580         rx_ring->next_to_use = 0;
 581
 582         return 0;
 583 err:
 584         kfree(rx_ring->rx_bi);
 585         rx_ring->rx_bi = NULL;
 586         return -ENOMEM;
 587 }
 588
 589 /**
 590  * i40e_release_rx_desc - Store the new tail and head values
 591  * @rx_ring: ring to bump
 592  * @val: new head index
 593  **/
 594 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 595 {
 596         rx_ring->next_to_use = val;
 597         /* Force memory writes to complete before letting h/w
 598          * know there are new descriptors to fetch.  (Only
 599          * applicable for weak-ordered memory model archs,
 600          * such as IA-64).
 601          */
 602         wmb();
 603         writel(val, rx_ring->tail);
 604 }
 605
 606 /**
 607  * i40evf_alloc_rx_buffers - Replace used receive buffers; packet split
 608  * @rx_ring: ring to place buffers on
 609  * @cleaned_count: number of buffers to replace
 610  **/
 611 void i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
 612 {
 613         u16 i = rx_ring->next_to_use;
 614         union i40e_rx_desc *rx_desc;
 615         struct i40e_rx_buffer *bi;
 616         struct sk_buff *skb;
 617
 618         /* do nothing if no valid netdev defined */
 619         if (!rx_ring->netdev || !cleaned_count)
 620                 return;
 621
 622         while (cleaned_count--) {
 623                 rx_desc = I40E_RX_DESC(rx_ring, i);
 624                 bi = &rx_ring->rx_bi[i];
 625                 skb = bi->skb;
 626
 627                 if (!skb) {
 628                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 629                                                         rx_ring->rx_buf_len);
 630                         if (!skb) {
 631                                 rx_ring->rx_stats.alloc_buff_failed++;
 632                                 goto no_buffers;
 633                         }
 634                         /* initialize queue mapping */
 635                         skb_record_rx_queue(skb, rx_ring->queue_index);
 636                         bi->skb = skb;
 637                 }
 638
 639                 if (!bi->dma) {
 640                         bi->dma = dma_map_single(rx_ring->dev,
 641                                                  skb->data,
 642                                                  rx_ring->rx_buf_len,
 643                                                  DMA_FROM_DEVICE);
 644                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 645                                 rx_ring->rx_stats.alloc_buff_failed++;
 646                                 bi->dma = 0;
 647                                 goto no_buffers;
 648                         }
 649                 }
 650
 651                 if (ring_is_ps_enabled(rx_ring)) {
 652                         if (!bi->page) {
 653                                 bi->page = alloc_page(GFP_ATOMIC);
 654                                 if (!bi->page) {
 655                                         rx_ring->rx_stats.alloc_page_failed++;
 656                                         goto no_buffers;
 657                                 }
 658                         }
 659
 660                         if (!bi->page_dma) {
 661                                 /* use a half page if we're re-using */
 662                                 bi->page_offset ^= PAGE_SIZE / 2;
 663                                 bi->page_dma = dma_map_page(rx_ring->dev,
 664                                                             bi->page,
 665                                                             bi->page_offset,
 666                                                             PAGE_SIZE / 2,
 667                                                             DMA_FROM_DEVICE);
 668                                 if (dma_mapping_error(rx_ring->dev,
 669                                                       bi->page_dma)) {
 670                                         rx_ring->rx_stats.alloc_page_failed++;
 671                                         bi->page_dma = 0;
 672                                         goto no_buffers;
 673                                 }
 674                         }
 675
 676                         /* Refresh the desc even if buffer_addrs didn't change
 677                          * because each write-back erases this info.
 678                          */
 679                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 680                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 681                 } else {
 682                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 683                         rx_desc->read.hdr_addr = 0;
 684                 }
 685                 i++;
 686                 if (i == rx_ring->count)
 687                         i = 0;
 688         }
 689
 690 no_buffers:
 691         if (rx_ring->next_to_use != i)
 692                 i40e_release_rx_desc(rx_ring, i);
 693 }
 694
 695 /**
 696  * i40e_receive_skb - Send a completed packet up the stack
 697  * @rx_ring:  rx ring in play
 698  * @skb: packet to send up
 699  * @vlan_tag: vlan tag for packet
 700  **/
 701 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 702                              struct sk_buff *skb, u16 vlan_tag)
 703 {
 704         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 705         struct i40e_vsi *vsi = rx_ring->vsi;
 706         u64 flags = vsi->back->flags;
 707
 708         if (vlan_tag & VLAN_VID_MASK)
 709                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 710
 711         if (flags & I40E_FLAG_IN_NETPOLL)
 712                 netif_rx(skb);
 713         else
 714                 napi_gro_receive(&q_vector->napi, skb);
 715 }
 716
 717 /**
 718  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 719  * @vsi: the VSI we care about
 720  * @skb: skb currently being received and modified
 721  * @rx_status: status value of last descriptor in packet
 722  * @rx_error: error value of last descriptor in packet
 723  * @rx_ptype: ptype value of last descriptor in packet
 724  **/
 725 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 726                                     struct sk_buff *skb,
 727                                     u32 rx_status,
 728                                     u32 rx_error,
 729                                     u16 rx_ptype)
 730 {
 731         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
 732         bool ipv4 = false, ipv6 = false;
 733         bool ipv4_tunnel, ipv6_tunnel;
 734         __wsum rx_udp_csum;
 735         struct iphdr *iph;
 736         __sum16 csum;
 737
 738         ipv4_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 739                       (rx_ptype < I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 740         ipv6_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 741                       (rx_ptype < I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 742
 743         skb->encapsulation = ipv4_tunnel || ipv6_tunnel;
 744         skb->ip_summed = CHECKSUM_NONE;
 745
 746         /* Rx csum enabled and ip headers found? */
 747         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
 748                 return;
 749
 750         /* did the hardware decode the packet and checksum? */
 751         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 752                 return;
 753
 754         /* both known and outer_ip must be set for the below code to work */
 755         if (!(decoded.known && decoded.outer_ip))
 756                 return;
 757
 758         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 759             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
 760                 ipv4 = true;
 761         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 762                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
 763                 ipv6 = true;
 764
 765         if (ipv4 &&
 766             (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
 767                          (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))))
 768                 goto checksum_fail;
 769
 770         /* likely incorrect csum if alternate IP extension headers found */
 771         if (ipv6 &&
 772             decoded.inner_prot == I40E_RX_PTYPE_INNER_PROT_TCP &&
 773             rx_error & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT) &&
 774             rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 775                 /* don't increment checksum err here, non-fatal err */
 776                 return;
 777
 778         /* there was some L4 error, count error and punt packet to the stack */
 779         if (rx_error & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT))
 780                 goto checksum_fail;
 781
 782         /* handle packets that were not able to be checksummed due
 783          * to arrival speed, in this case the stack can compute
 784          * the csum.
 785          */
 786         if (rx_error & (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT))
 787                 return;
 788
 789         /* If VXLAN traffic has an outer UDPv4 checksum we need to check
 790          * it in the driver, hardware does not do it for us.
 791          * Since L3L4P bit was set we assume a valid IHL value (>=5)
 792          * so the total length of IPv4 header is IHL*4 bytes
 793          * The UDP_0 bit *may* bet set if the *inner* header is UDP
 794          */
 795         if (ipv4_tunnel &&
 796             (decoded.inner_prot != I40E_RX_PTYPE_INNER_PROT_UDP) &&
 797             !(rx_status & (1 << I40E_RX_DESC_STATUS_UDP_0_SHIFT))) {
 798                 skb->transport_header = skb->mac_header +
 799                                         sizeof(struct ethhdr) +
 800                                         (ip_hdr(skb)->ihl * 4);
 801
 802                 /* Add 4 bytes for VLAN tagged packets */
 803                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
 804                                           skb->protocol == htons(ETH_P_8021AD))
 805                                           ? VLAN_HLEN : 0;
 806
 807                 rx_udp_csum = udp_csum(skb);
 808                 iph = ip_hdr(skb);
 809                 csum = csum_tcpudp_magic(
 810                                 iph->saddr, iph->daddr,
 811                                 (skb->len - skb_transport_offset(skb)),
 812                                 IPPROTO_UDP, rx_udp_csum);
 813
 814                 if (udp_hdr(skb)->check != csum)
 815                         goto checksum_fail;
 816         }
 817
 818         skb->ip_summed = CHECKSUM_UNNECESSARY;
 819
 820         return;
 821
 822 checksum_fail:
 823         vsi->back->hw_csum_rx_error++;
 824 }
 825
 826 /**
 827  * i40e_rx_hash - returns the hash value from the Rx descriptor
 828  * @ring: descriptor ring
 829  * @rx_desc: specific descriptor
 830  **/
 831 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
 832                                union i40e_rx_desc *rx_desc)
 833 {
 834         const __le64 rss_mask =
 835                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 836                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 837
 838         if ((ring->netdev->features & NETIF_F_RXHASH) &&
 839             (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
 840                 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 841         else
 842                 return 0;
 843 }
 844
 845 /**
 846  * i40e_ptype_to_hash - get a hash type
 847  * @ptype: the ptype value from the descriptor
 848  *
 849  * Returns a hash type to be used by skb_set_hash
 850  **/
 851 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
 852 {
 853         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
 854
 855         if (!decoded.known)
 856                 return PKT_HASH_TYPE_NONE;
 857
 858         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 859             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
 860                 return PKT_HASH_TYPE_L4;
 861         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 862                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
 863                 return PKT_HASH_TYPE_L3;
 864         else
 865                 return PKT_HASH_TYPE_L2;
 866 }
 867
 868 /**
 869  * i40e_clean_rx_irq - Reclaim resources after receive completes
 870  * @rx_ring:  rx ring to clean
 871  * @budget:   how many cleans we're allowed
 872  *
 873  * Returns true if there's any budget left (e.g. the clean is finished)
 874  **/
 875 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
 876 {
 877         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 878         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
 879         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
 880         const int current_node = numa_node_id();
 881         struct i40e_vsi *vsi = rx_ring->vsi;
 882         u16 i = rx_ring->next_to_clean;
 883         union i40e_rx_desc *rx_desc;
 884         u32 rx_error, rx_status;
 885         u8 rx_ptype;
 886         u64 qword;
 887
 888         rx_desc = I40E_RX_DESC(rx_ring, i);
 889         qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 890         rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
 891                     I40E_RXD_QW1_STATUS_SHIFT;
 892
 893         while (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
 894                 union i40e_rx_desc *next_rxd;
 895                 struct i40e_rx_buffer *rx_bi;
 896                 struct sk_buff *skb;
 897                 u16 vlan_tag;
 898                 rx_bi = &rx_ring->rx_bi[i];
 899                 skb = rx_bi->skb;
 900                 prefetch(skb->data);
 901
 902                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 903                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 904                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
 905                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
 906                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
 907                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
 908
 909                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
 910                            I40E_RXD_QW1_ERROR_SHIFT;
 911                 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
 912                 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
 913
 914                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
 915                            I40E_RXD_QW1_PTYPE_SHIFT;
 916                 rx_bi->skb = NULL;
 917
 918                 /* This memory barrier is needed to keep us from reading
 919                  * any other fields out of the rx_desc until we know the
 920                  * STATUS_DD bit is set
 921                  */
 922                 rmb();
 923
 924                 /* Get the header and possibly the whole packet
 925                  * If this is an skb from previous receive dma will be 0
 926                  */
 927                 if (rx_bi->dma) {
 928                         u16 len;
 929
 930                         if (rx_hbo)
 931                                 len = I40E_RX_HDR_SIZE;
 932                         else if (rx_sph)
 933                                 len = rx_header_len;
 934                         else if (rx_packet_len)
 935                                 len = rx_packet_len;   /* 1buf/no split found */
 936                         else
 937                                 len = rx_header_len;   /* split always mode */
 938
 939                         skb_put(skb, len);
 940                         dma_unmap_single(rx_ring->dev,
 941                                          rx_bi->dma,
 942                                          rx_ring->rx_buf_len,
 943                                          DMA_FROM_DEVICE);
 944                         rx_bi->dma = 0;
 945                 }
 946
 947                 /* Get the rest of the data if this was a header split */
 948                 if (ring_is_ps_enabled(rx_ring) && rx_packet_len) {
 949
 950                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 951                                            rx_bi->page,
 952                                            rx_bi->page_offset,
 953                                            rx_packet_len);
 954
 955                         skb->len += rx_packet_len;
 956                         skb->data_len += rx_packet_len;
 957                         skb->truesize += rx_packet_len;
 958
 959                         if ((page_count(rx_bi->page) == 1) &&
 960                             (page_to_nid(rx_bi->page) == current_node))
 961                                 get_page(rx_bi->page);
 962                         else
 963                                 rx_bi->page = NULL;
 964
 965                         dma_unmap_page(rx_ring->dev,
 966                                        rx_bi->page_dma,
 967                                        PAGE_SIZE / 2,
 968                                        DMA_FROM_DEVICE);
 969                         rx_bi->page_dma = 0;
 970                 }
 971                 I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd);
 972
 973                 if (unlikely(
 974                     !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
 975                         struct i40e_rx_buffer *next_buffer;
 976
 977                         next_buffer = &rx_ring->rx_bi[i];
 978
 979                         if (ring_is_ps_enabled(rx_ring)) {
 980                                 rx_bi->skb = next_buffer->skb;
 981                                 rx_bi->dma = next_buffer->dma;
 982                                 next_buffer->skb = skb;
 983                                 next_buffer->dma = 0;
 984                         }
 985                         rx_ring->rx_stats.non_eop_descs++;
 986                         goto next_desc;
 987                 }
 988
 989                 /* ERR_MASK will only have valid bits if EOP set */
 990                 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 991                         dev_kfree_skb_any(skb);
 992                         /* TODO: shouldn't we increment a counter indicating the
 993                          * drop?
 994                          */
 995                         goto next_desc;
 996                 }
 997
 998                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
 999                              i40e_ptype_to_hash(rx_ptype));
1000                 /* probably a little skewed due to removing CRC */
1001                 total_rx_bytes += skb->len;
1002                 total_rx_packets++;
1003
1004                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1005
1006                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1007
1008                 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1009                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1010                          : 0;
1011                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1012
1013                 rx_ring->netdev->last_rx = jiffies;
1014                 budget--;
1015 next_desc:
1016                 rx_desc->wb.qword1.status_error_len = 0;
1017                 if (!budget)
1018                         break;
1019
1020                 cleaned_count++;
1021                 /* return some buffers to hardware, one at a time is too slow */
1022                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1023                         i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
1024                         cleaned_count = 0;
1025                 }
1026
1027                 /* use prefetched values */
1028                 rx_desc = next_rxd;
1029                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1030                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1031                             I40E_RXD_QW1_STATUS_SHIFT;
1032         }
1033
1034         rx_ring->next_to_clean = i;
1035         u64_stats_update_begin(&rx_ring->syncp);
1036         rx_ring->stats.packets += total_rx_packets;
1037         rx_ring->stats.bytes += total_rx_bytes;
1038         u64_stats_update_end(&rx_ring->syncp);
1039         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1040         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1041
1042         if (cleaned_count)
1043                 i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
1044
1045         return budget > 0;
1046 }
1047
1048 /**
1049  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1050  * @napi: napi struct with our devices info in it
1051  * @budget: amount of work driver is allowed to do this pass, in packets
1052  *
1053  * This function will clean all queues associated with a q_vector.
1054  *
1055  * Returns the amount of work done
1056  **/
1057 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1058 {
1059         struct i40e_q_vector *q_vector =
1060                                container_of(napi, struct i40e_q_vector, napi);
1061         struct i40e_vsi *vsi = q_vector->vsi;
1062         struct i40e_ring *ring;
1063         bool clean_complete = true;
1064         int budget_per_ring;
1065
1066         if (test_bit(__I40E_DOWN, &vsi->state)) {
1067                 napi_complete(napi);
1068                 return 0;
1069         }
1070
1071         /* Since the actual Tx work is minimal, we can give the Tx a larger
1072          * budget and be more aggressive about cleaning up the Tx descriptors.
1073          */
1074         i40e_for_each_ring(ring, q_vector->tx)
1075                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1076
1077         /* We attempt to distribute budget to each Rx queue fairly, but don't
1078          * allow the budget to go below 1 because that would exit polling early.
1079          */
1080         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1081
1082         i40e_for_each_ring(ring, q_vector->rx)
1083                 clean_complete &= i40e_clean_rx_irq(ring, budget_per_ring);
1084
1085         /* If work not completed, return budget and polling will return */
1086         if (!clean_complete)
1087                 return budget;
1088
1089         /* Work is done so exit the polling mode and re-enable the interrupt */
1090         napi_complete(napi);
1091         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||
1092             ITR_IS_DYNAMIC(vsi->tx_itr_setting))
1093                 i40e_update_dynamic_itr(q_vector);
1094
1095         if (!test_bit(__I40E_DOWN, &vsi->state))
1096                 i40evf_irq_enable_queues(vsi->back, 1 << q_vector->v_idx);
1097
1098         return 0;
1099 }
1100
1101 /**
1102  * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1103  * @skb:     send buffer
1104  * @tx_ring: ring to send buffer on
1105  * @flags:   the tx flags to be set
1106  *
1107  * Checks the skb and set up correspondingly several generic transmit flags
1108  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1109  *
1110  * Returns error code indicate the frame should be dropped upon error and the
1111  * otherwise  returns 0 to indicate the flags has been set properly.
1112  **/
1113 static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
1114                                       struct i40e_ring *tx_ring,
1115                                       u32 *flags)
1116 {
1117         __be16 protocol = skb->protocol;
1118         u32  tx_flags = 0;
1119
1120         /* if we have a HW VLAN tag being added, default to the HW one */
1121         if (vlan_tx_tag_present(skb)) {
1122                 tx_flags |= vlan_tx_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1123                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1124         /* else if it is a SW VLAN, check the next protocol and store the tag */
1125         } else if (protocol == htons(ETH_P_8021Q)) {
1126                 struct vlan_hdr *vhdr, _vhdr;
1127                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1128                 if (!vhdr)
1129                         return -EINVAL;
1130
1131                 protocol = vhdr->h_vlan_encapsulated_proto;
1132                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1133                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1134         }
1135
1136         *flags = tx_flags;
1137         return 0;
1138 }
1139
1140 /**
1141  * i40e_tso - set up the tso context descriptor
1142  * @tx_ring:  ptr to the ring to send
1143  * @skb:      ptr to the skb we're sending
1144  * @tx_flags: the collected send information
1145  * @protocol: the send protocol
1146  * @hdr_len:  ptr to the size of the packet header
1147  * @cd_tunneling: ptr to context descriptor bits
1148  *
1149  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1150  **/
1151 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1152                     u32 tx_flags, __be16 protocol, u8 *hdr_len,
1153                     u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling)
1154 {
1155         u32 cd_cmd, cd_tso_len, cd_mss;
1156         struct ipv6hdr *ipv6h;
1157         struct tcphdr *tcph;
1158         struct iphdr *iph;
1159         u32 l4len;
1160         int err;
1161
1162         if (!skb_is_gso(skb))
1163                 return 0;
1164
1165         err = skb_cow_head(skb, 0);
1166         if (err < 0)
1167                 return err;
1168
1169         if (protocol == htons(ETH_P_IP)) {
1170                 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1171                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1172                 iph->tot_len = 0;
1173                 iph->check = 0;
1174                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1175                                                  0, IPPROTO_TCP, 0);
1176         } else if (skb_is_gso_v6(skb)) {
1177
1178                 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb)
1179                                            : ipv6_hdr(skb);
1180                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1181                 ipv6h->payload_len = 0;
1182                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1183                                                0, IPPROTO_TCP, 0);
1184         }
1185
1186         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1187         *hdr_len = (skb->encapsulation
1188                     ? (skb_inner_transport_header(skb) - skb->data)
1189                     : skb_transport_offset(skb)) + l4len;
1190
1191         /* find the field values */
1192         cd_cmd = I40E_TX_CTX_DESC_TSO;
1193         cd_tso_len = skb->len - *hdr_len;
1194         cd_mss = skb_shinfo(skb)->gso_size;
1195         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1196                                 ((u64)cd_tso_len <<
1197                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1198                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1199         return 1;
1200 }
1201
1202 /**
1203  * i40e_tx_enable_csum - Enable Tx checksum offloads
1204  * @skb: send buffer
1205  * @tx_flags: Tx flags currently set
1206  * @td_cmd: Tx descriptor command bits to set
1207  * @td_offset: Tx descriptor header offsets to set
1208  * @cd_tunneling: ptr to context desc bits
1209  **/
1210 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags,
1211                                 u32 *td_cmd, u32 *td_offset,
1212                                 struct i40e_ring *tx_ring,
1213                                 u32 *cd_tunneling)
1214 {
1215         struct ipv6hdr *this_ipv6_hdr;
1216         unsigned int this_tcp_hdrlen;
1217         struct iphdr *this_ip_hdr;
1218         u32 network_hdr_len;
1219         u8 l4_hdr = 0;
1220
1221         if (skb->encapsulation) {
1222                 network_hdr_len = skb_inner_network_header_len(skb);
1223                 this_ip_hdr = inner_ip_hdr(skb);
1224                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1225                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1226
1227                 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1228
1229                         if (tx_flags & I40E_TX_FLAGS_TSO) {
1230                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1231                                 ip_hdr(skb)->check = 0;
1232                         } else {
1233                                 *cd_tunneling |=
1234                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1235                         }
1236                 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1237                         if (tx_flags & I40E_TX_FLAGS_TSO) {
1238                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1239                                 ip_hdr(skb)->check = 0;
1240                         } else {
1241                                 *cd_tunneling |=
1242                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1243                         }
1244                 }
1245
1246                 /* Now set the ctx descriptor fields */
1247                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1248                                         I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1249                                    I40E_TXD_CTX_UDP_TUNNELING            |
1250                                    ((skb_inner_network_offset(skb) -
1251                                         skb_transport_offset(skb)) >> 1) <<
1252                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1253
1254         } else {
1255                 network_hdr_len = skb_network_header_len(skb);
1256                 this_ip_hdr = ip_hdr(skb);
1257                 this_ipv6_hdr = ipv6_hdr(skb);
1258                 this_tcp_hdrlen = tcp_hdrlen(skb);
1259         }
1260
1261         /* Enable IP checksum offloads */
1262         if (tx_flags & I40E_TX_FLAGS_IPV4) {
1263                 l4_hdr = this_ip_hdr->protocol;
1264                 /* the stack computes the IP header already, the only time we
1265                  * need the hardware to recompute it is in the case of TSO.
1266                  */
1267                 if (tx_flags & I40E_TX_FLAGS_TSO) {
1268                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1269                         this_ip_hdr->check = 0;
1270                 } else {
1271                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1272                 }
1273                 /* Now set the td_offset for IP header length */
1274                 *td_offset = (network_hdr_len >> 2) <<
1275                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1276         } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1277                 l4_hdr = this_ipv6_hdr->nexthdr;
1278                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1279                 /* Now set the td_offset for IP header length */
1280                 *td_offset = (network_hdr_len >> 2) <<
1281                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1282         }
1283         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1284         *td_offset |= (skb_network_offset(skb) >> 1) <<
1285                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1286
1287         /* Enable L4 checksum offloads */
1288         switch (l4_hdr) {
1289         case IPPROTO_TCP:
1290                 /* enable checksum offloads */
1291                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1292                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1293                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1294                 break;
1295         case IPPROTO_SCTP:
1296                 /* enable SCTP checksum offload */
1297                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1298                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1299                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1300                 break;
1301         case IPPROTO_UDP:
1302                 /* enable UDP checksum offload */
1303                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1304                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1305                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1306                 break;
1307         default:
1308                 break;
1309         }
1310 }
1311
1312 /**
1313  * i40e_create_tx_ctx Build the Tx context descriptor
1314  * @tx_ring:  ring to create the descriptor on
1315  * @cd_type_cmd_tso_mss: Quad Word 1
1316  * @cd_tunneling: Quad Word 0 - bits 0-31
1317  * @cd_l2tag2: Quad Word 0 - bits 32-63
1318  **/
1319 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1320                                const u64 cd_type_cmd_tso_mss,
1321                                const u32 cd_tunneling, const u32 cd_l2tag2)
1322 {
1323         struct i40e_tx_context_desc *context_desc;
1324         int i = tx_ring->next_to_use;
1325
1326         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1327             !cd_tunneling && !cd_l2tag2)
1328                 return;
1329
1330         /* grab the next descriptor */
1331         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1332
1333         i++;
1334         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1335
1336         /* cpu_to_le32 and assign to struct fields */
1337         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1338         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1339         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1340 }
1341
1342 /**
1343  * i40e_tx_map - Build the Tx descriptor
1344  * @tx_ring:  ring to send buffer on
1345  * @skb:      send buffer
1346  * @first:    first buffer info buffer to use
1347  * @tx_flags: collected send information
1348  * @hdr_len:  size of the packet header
1349  * @td_cmd:   the command field in the descriptor
1350  * @td_offset: offset for checksum or crc
1351  **/
1352 static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1353                         struct i40e_tx_buffer *first, u32 tx_flags,
1354                         const u8 hdr_len, u32 td_cmd, u32 td_offset)
1355 {
1356         unsigned int data_len = skb->data_len;
1357         unsigned int size = skb_headlen(skb);
1358         struct skb_frag_struct *frag;
1359         struct i40e_tx_buffer *tx_bi;
1360         struct i40e_tx_desc *tx_desc;
1361         u16 i = tx_ring->next_to_use;
1362         u32 td_tag = 0;
1363         dma_addr_t dma;
1364         u16 gso_segs;
1365
1366         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1367                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1368                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1369                          I40E_TX_FLAGS_VLAN_SHIFT;
1370         }
1371
1372         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1373                 gso_segs = skb_shinfo(skb)->gso_segs;
1374         else
1375                 gso_segs = 1;
1376
1377         /* multiply data chunks by size of headers */
1378         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1379         first->gso_segs = gso_segs;
1380         first->skb = skb;
1381         first->tx_flags = tx_flags;
1382
1383         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1384
1385         tx_desc = I40E_TX_DESC(tx_ring, i);
1386         tx_bi = first;
1387
1388         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1389                 if (dma_mapping_error(tx_ring->dev, dma))
1390                         goto dma_error;
1391
1392                 /* record length, and DMA address */
1393                 dma_unmap_len_set(tx_bi, len, size);
1394                 dma_unmap_addr_set(tx_bi, dma, dma);
1395
1396                 tx_desc->buffer_addr = cpu_to_le64(dma);
1397
1398                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1399                         tx_desc->cmd_type_offset_bsz =
1400                                 build_ctob(td_cmd, td_offset,
1401                                            I40E_MAX_DATA_PER_TXD, td_tag);
1402
1403                         tx_desc++;
1404                         i++;
1405                         if (i == tx_ring->count) {
1406                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1407                                 i = 0;
1408                         }
1409
1410                         dma += I40E_MAX_DATA_PER_TXD;
1411                         size -= I40E_MAX_DATA_PER_TXD;
1412
1413                         tx_desc->buffer_addr = cpu_to_le64(dma);
1414                 }
1415
1416                 if (likely(!data_len))
1417                         break;
1418
1419                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1420                                                           size, td_tag);
1421
1422                 tx_desc++;
1423                 i++;
1424                 if (i == tx_ring->count) {
1425                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1426                         i = 0;
1427                 }
1428
1429                 size = skb_frag_size(frag);
1430                 data_len -= size;
1431
1432                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1433                                        DMA_TO_DEVICE);
1434
1435                 tx_bi = &tx_ring->tx_bi[i];
1436         }
1437
1438         /* Place RS bit on last descriptor of any packet that spans across the
1439          * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1440          */
1441 #define WB_STRIDE 0x3
1442         if (((i & WB_STRIDE) != WB_STRIDE) &&
1443             (first <= &tx_ring->tx_bi[i]) &&
1444             (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1445                 tx_desc->cmd_type_offset_bsz =
1446                         build_ctob(td_cmd, td_offset, size, td_tag) |
1447                         cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1448                                          I40E_TXD_QW1_CMD_SHIFT);
1449         } else {
1450                 tx_desc->cmd_type_offset_bsz =
1451                         build_ctob(td_cmd, td_offset, size, td_tag) |
1452                         cpu_to_le64((u64)I40E_TXD_CMD <<
1453                                          I40E_TXD_QW1_CMD_SHIFT);
1454         }
1455
1456         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1457                                                  tx_ring->queue_index),
1458                              first->bytecount);
1459
1460         /* set the timestamp */
1461         first->time_stamp = jiffies;
1462
1463         /* Force memory writes to complete before letting h/w
1464          * know there are new descriptors to fetch.  (Only
1465          * applicable for weak-ordered memory model archs,
1466          * such as IA-64).
1467          */
1468         wmb();
1469
1470         /* set next_to_watch value indicating a packet is present */
1471         first->next_to_watch = tx_desc;
1472
1473         i++;
1474         if (i == tx_ring->count)
1475                 i = 0;
1476
1477         tx_ring->next_to_use = i;
1478
1479         /* notify HW of packet */
1480         writel(i, tx_ring->tail);
1481
1482         return;
1483
1484 dma_error:
1485         dev_info(tx_ring->dev, "TX DMA map failed\n");
1486
1487         /* clear dma mappings for failed tx_bi map */
1488         for (;;) {
1489                 tx_bi = &tx_ring->tx_bi[i];
1490                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1491                 if (tx_bi == first)
1492                         break;
1493                 if (i == 0)
1494                         i = tx_ring->count;
1495                 i--;
1496         }
1497
1498         tx_ring->next_to_use = i;
1499 }
1500
1501 /**
1502  * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
1503  * @tx_ring: the ring to be checked
1504  * @size:    the size buffer we want to assure is available
1505  *
1506  * Returns -EBUSY if a stop is needed, else 0
1507  **/
1508 static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1509 {
1510         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1511         /* Memory barrier before checking head and tail */
1512         smp_mb();
1513
1514         /* Check again in a case another CPU has just made room available. */
1515         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1516                 return -EBUSY;
1517
1518         /* A reprieve! - use start_queue because it doesn't call schedule */
1519         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1520         ++tx_ring->tx_stats.restart_queue;
1521         return 0;
1522 }
1523
1524 /**
1525  * i40e_maybe_stop_tx - 1st level check for tx stop conditions
1526  * @tx_ring: the ring to be checked
1527  * @size:    the size buffer we want to assure is available
1528  *
1529  * Returns 0 if stop is not needed
1530  **/
1531 static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1532 {
1533         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1534                 return 0;
1535         return __i40e_maybe_stop_tx(tx_ring, size);
1536 }
1537
1538 /**
1539  * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
1540  * @skb:     send buffer
1541  * @tx_ring: ring to send buffer on
1542  *
1543  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1544  * there is not enough descriptors available in this ring since we need at least
1545  * one descriptor.
1546  **/
1547 static int i40e_xmit_descriptor_count(struct sk_buff *skb,
1548                                       struct i40e_ring *tx_ring)
1549 {
1550         unsigned int f;
1551         int count = 0;
1552
1553         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1554          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1555          *       + 4 desc gap to avoid the cache line where head is,
1556          *       + 1 desc for context descriptor,
1557          * otherwise try next time
1558          */
1559         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1560                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1561
1562         count += TXD_USE_COUNT(skb_headlen(skb));
1563         if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1564                 tx_ring->tx_stats.tx_busy++;
1565                 return 0;
1566         }
1567         return count;
1568 }
1569
1570 /**
1571  * i40e_xmit_frame_ring - Sends buffer on Tx ring
1572  * @skb:     send buffer
1573  * @tx_ring: ring to send buffer on
1574  *
1575  * Returns NETDEV_TX_OK if sent, else an error code
1576  **/
1577 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1578                                         struct i40e_ring *tx_ring)
1579 {
1580         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1581         u32 cd_tunneling = 0, cd_l2tag2 = 0;
1582         struct i40e_tx_buffer *first;
1583         u32 td_offset = 0;
1584         u32 tx_flags = 0;
1585         __be16 protocol;
1586         u32 td_cmd = 0;
1587         u8 hdr_len = 0;
1588         int tso;
1589         if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
1590                 return NETDEV_TX_BUSY;
1591
1592         /* prepare the xmit flags */
1593         if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1594                 goto out_drop;
1595
1596         /* obtain protocol of skb */
1597         protocol = skb->protocol;
1598
1599         /* record the location of the first descriptor for this packet */
1600         first = &tx_ring->tx_bi[tx_ring->next_to_use];
1601
1602         /* setup IPv4/IPv6 offloads */
1603         if (protocol == htons(ETH_P_IP))
1604                 tx_flags |= I40E_TX_FLAGS_IPV4;
1605         else if (protocol == htons(ETH_P_IPV6))
1606                 tx_flags |= I40E_TX_FLAGS_IPV6;
1607
1608         tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len,
1609                        &cd_type_cmd_tso_mss, &cd_tunneling);
1610
1611         if (tso < 0)
1612                 goto out_drop;
1613         else if (tso)
1614                 tx_flags |= I40E_TX_FLAGS_TSO;
1615
1616         skb_tx_timestamp(skb);
1617
1618         /* always enable CRC insertion offload */
1619         td_cmd |= I40E_TX_DESC_CMD_ICRC;
1620
1621         /* Always offload the checksum, since it's in the data descriptor */
1622         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1623                 tx_flags |= I40E_TX_FLAGS_CSUM;
1624
1625                 i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset,
1626                                     tx_ring, &cd_tunneling);
1627         }
1628
1629         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1630                            cd_tunneling, cd_l2tag2);
1631
1632         i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1633                     td_cmd, td_offset);
1634
1635         i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
1636
1637         return NETDEV_TX_OK;
1638
1639 out_drop:
1640         dev_kfree_skb_any(skb);
1641         return NETDEV_TX_OK;
1642 }
1643
1644 /**
1645  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1646  * @skb:    send buffer
1647  * @netdev: network interface device structure
1648  *
1649  * Returns NETDEV_TX_OK if sent, else an error code
1650  **/
1651 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1652 {
1653         struct i40evf_adapter *adapter = netdev_priv(netdev);
1654         struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1655
1656         /* hardware can't handle really short frames, hardware padding works
1657          * beyond this point
1658          */
1659         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1660                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1661                         return NETDEV_TX_OK;
1662                 skb->len = I40E_MIN_TX_LEN;
1663                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
1664         }
1665
1666         return i40e_xmit_frame_ring(skb, tx_ring);
1667 }