1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
35 #include "i40e_lan_hmc.h"
38 #define I40E_DEV_ID_SFP_XL710 0x1572
39 #define I40E_DEV_ID_QEMU 0x1574
40 #define I40E_DEV_ID_KX_A 0x157F
41 #define I40E_DEV_ID_KX_B 0x1580
42 #define I40E_DEV_ID_KX_C 0x1581
43 #define I40E_DEV_ID_QSFP_A 0x1583
44 #define I40E_DEV_ID_QSFP_B 0x1584
45 #define I40E_DEV_ID_QSFP_C 0x1585
46 #define I40E_DEV_ID_VF 0x154C
47 #define I40E_DEV_ID_VF_HV 0x1571
49 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
50 (d) == I40E_DEV_ID_QSFP_B || \
51 (d) == I40E_DEV_ID_QSFP_C)
53 #define I40E_MAX_VSI_QP 16
54 #define I40E_MAX_VF_VSI 3
55 #define I40E_MAX_CHAINED_RX_BUFFERS 5
56 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
58 /* Max default timeout in ms, */
59 #define I40E_MAX_NVM_TIMEOUT 18000
61 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
62 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
64 /* forward declaration */
66 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
68 /* Data type manipulation macros. */
70 #define I40E_DESC_UNUSED(R) \
71 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
72 (R)->next_to_clean - (R)->next_to_use - 1)
74 /* bitfields for Tx queue mapping in QTX_CTL */
75 #define I40E_QTX_CTL_VF_QUEUE 0x0
76 #define I40E_QTX_CTL_VM_QUEUE 0x1
77 #define I40E_QTX_CTL_PF_QUEUE 0x2
79 /* debug masks - set these bits in hw->debug_mask to control output */
80 enum i40e_debug_mask {
81 I40E_DEBUG_INIT = 0x00000001,
82 I40E_DEBUG_RELEASE = 0x00000002,
84 I40E_DEBUG_LINK = 0x00000010,
85 I40E_DEBUG_PHY = 0x00000020,
86 I40E_DEBUG_HMC = 0x00000040,
87 I40E_DEBUG_NVM = 0x00000080,
88 I40E_DEBUG_LAN = 0x00000100,
89 I40E_DEBUG_FLOW = 0x00000200,
90 I40E_DEBUG_DCB = 0x00000400,
91 I40E_DEBUG_DIAG = 0x00000800,
92 I40E_DEBUG_FD = 0x00001000,
94 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
95 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
96 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
97 I40E_DEBUG_AQ_COMMAND = 0x06000000,
98 I40E_DEBUG_AQ = 0x0F000000,
100 I40E_DEBUG_USER = 0xF0000000,
102 I40E_DEBUG_ALL = 0xFFFFFFFF
105 /* These are structs for managing the hardware information and the operations.
106 * The structures of function pointers are filled out at init time when we
107 * know for sure exactly which hardware we're working with. This gives us the
108 * flexibility of using the same main driver code but adapting to slightly
109 * different hardware needs as new parts are developed. For this architecture,
110 * the Firmware and AdminQ are intended to insulate the driver from most of the
111 * future changes, but these structures will also do part of the job.
114 I40E_MAC_UNKNOWN = 0,
121 enum i40e_media_type {
122 I40E_MEDIA_TYPE_UNKNOWN = 0,
123 I40E_MEDIA_TYPE_FIBER,
124 I40E_MEDIA_TYPE_BASET,
125 I40E_MEDIA_TYPE_BACKPLANE,
128 I40E_MEDIA_TYPE_VIRTUAL
149 I40E_VSI_TYPE_UNKNOWN
152 enum i40e_queue_type {
153 I40E_QUEUE_TYPE_RX = 0,
155 I40E_QUEUE_TYPE_PE_CEQ,
156 I40E_QUEUE_TYPE_UNKNOWN
159 struct i40e_link_status {
160 enum i40e_aq_phy_type phy_type;
161 enum i40e_aq_link_speed link_speed;
166 /* is Link Status Event notification to SW enabled */
173 struct i40e_phy_info {
174 struct i40e_link_status link_info;
175 struct i40e_link_status link_info_old;
176 u32 autoneg_advertised;
180 enum i40e_media_type media_type;
183 #define I40E_HW_CAP_MAX_GPIO 30
184 /* Capabilities of a PF or a VF or the whole device */
185 struct i40e_hw_capabilities {
187 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
188 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
189 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
197 bool evb_802_1_qbg; /* Edge Virtual Bridging */
198 bool evb_802_1_qbh; /* Bridge Port Extension */
206 u32 fd_filters_guaranteed;
207 u32 fd_filters_best_effort;
210 u32 rss_table_entry_width;
211 bool led[I40E_HW_CAP_MAX_GPIO];
212 bool sdp[I40E_HW_CAP_MAX_GPIO];
214 u32 num_flow_director_filters;
221 u32 num_msix_vectors;
222 u32 num_msix_vectors_vf;
232 struct i40e_mac_info {
233 enum i40e_mac_type type;
235 u8 perm_addr[ETH_ALEN];
236 u8 san_addr[ETH_ALEN];
240 enum i40e_aq_resources_ids {
241 I40E_NVM_RESOURCE_ID = 1
244 enum i40e_aq_resource_access_type {
245 I40E_RESOURCE_READ = 1,
249 struct i40e_nvm_info {
250 u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
251 u64 hw_semaphore_wait; /* - || - */
252 u32 timeout; /* [ms] */
253 u16 sr_size; /* Shadow RAM size in words */
254 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
255 u16 version; /* NVM package version */
256 u32 eetrack; /* NVM data version */
261 i40e_bus_type_unknown = 0,
264 i40e_bus_type_pci_express,
265 i40e_bus_type_reserved
269 enum i40e_bus_speed {
270 i40e_bus_speed_unknown = 0,
271 i40e_bus_speed_33 = 33,
272 i40e_bus_speed_66 = 66,
273 i40e_bus_speed_100 = 100,
274 i40e_bus_speed_120 = 120,
275 i40e_bus_speed_133 = 133,
276 i40e_bus_speed_2500 = 2500,
277 i40e_bus_speed_5000 = 5000,
278 i40e_bus_speed_8000 = 8000,
279 i40e_bus_speed_reserved
283 enum i40e_bus_width {
284 i40e_bus_width_unknown = 0,
285 i40e_bus_width_pcie_x1 = 1,
286 i40e_bus_width_pcie_x2 = 2,
287 i40e_bus_width_pcie_x4 = 4,
288 i40e_bus_width_pcie_x8 = 8,
289 i40e_bus_width_32 = 32,
290 i40e_bus_width_64 = 64,
291 i40e_bus_width_reserved
295 struct i40e_bus_info {
296 enum i40e_bus_speed speed;
297 enum i40e_bus_width width;
298 enum i40e_bus_type type;
305 /* Flow control (FC) parameters */
306 struct i40e_fc_info {
307 enum i40e_fc_mode current_mode; /* FC mode in effect */
308 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
311 #define I40E_MAX_TRAFFIC_CLASS 8
312 #define I40E_MAX_USER_PRIORITY 8
313 #define I40E_DCBX_MAX_APPS 32
314 #define I40E_LLDPDU_SIZE 1500
316 /* IEEE 802.1Qaz ETS Configuration data */
317 struct i40e_ieee_ets_config {
321 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
322 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
323 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
326 /* IEEE 802.1Qaz ETS Recommendation data */
327 struct i40e_ieee_ets_recommend {
328 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
329 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
330 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
333 /* IEEE 802.1Qaz PFC Configuration data */
334 struct i40e_ieee_pfc_config {
341 /* IEEE 802.1Qaz Application Priority data */
342 struct i40e_ieee_app_priority_table {
348 struct i40e_dcbx_config {
350 struct i40e_ieee_ets_config etscfg;
351 struct i40e_ieee_ets_recommend etsrec;
352 struct i40e_ieee_pfc_config pfc;
353 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
356 /* Port hardware description */
361 /* function pointer structs */
362 struct i40e_phy_info phy;
363 struct i40e_mac_info mac;
364 struct i40e_bus_info bus;
365 struct i40e_nvm_info nvm;
366 struct i40e_fc_info fc;
371 u16 subsystem_device_id;
372 u16 subsystem_vendor_id;
375 bool adapter_stopped;
377 /* capabilities for entire device and PCI func */
378 struct i40e_hw_capabilities dev_caps;
379 struct i40e_hw_capabilities func_caps;
381 /* Flow Director shared filter space */
382 u16 fdir_shared_filter_count;
384 /* device profile info */
388 /* Closest numa node to the device */
391 /* Admin Queue info */
392 struct i40e_adminq_info aq;
395 struct i40e_hmc_info hmc; /* HMC info struct */
397 /* LLDP/DCBX Status */
401 struct i40e_dcbx_config local_dcbx_config;
402 struct i40e_dcbx_config remote_dcbx_config;
408 struct i40e_driver_version {
413 u8 driver_string[32];
417 union i40e_16byte_rx_desc {
419 __le64 pkt_addr; /* Packet buffer address */
420 __le64 hdr_addr; /* Header buffer address */
426 __le16 mirroring_status;
432 __le32 rss; /* RSS Hash */
433 __le32 fd_id; /* Flow director filter id */
434 __le32 fcoe_param; /* FCoE DDP Context id */
438 /* ext status/error/pktype/length */
439 __le64 status_error_len;
441 } wb; /* writeback */
444 union i40e_32byte_rx_desc {
446 __le64 pkt_addr; /* Packet buffer address */
447 __le64 hdr_addr; /* Header buffer address */
448 /* bit 0 of hdr_buffer_addr is DD bit */
456 __le16 mirroring_status;
462 __le32 rss; /* RSS Hash */
463 __le32 fcoe_param; /* FCoE DDP Context id */
464 /* Flow director filter id in case of
465 * Programming status desc WB
471 /* status/error/pktype/length */
472 __le64 status_error_len;
475 __le16 ext_status; /* extended status */
482 __le32 flex_bytes_lo;
486 __le32 flex_bytes_hi;
490 } wb; /* writeback */
493 enum i40e_rx_desc_status_bits {
494 /* Note: These are predefined bit offsets */
495 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
496 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
497 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
498 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
499 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
500 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
501 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
502 I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
503 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
504 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
505 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
506 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
507 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
508 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
509 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
510 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
513 #define I40E_RXD_QW1_STATUS_SHIFT 0
514 #define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) \
515 << I40E_RXD_QW1_STATUS_SHIFT)
517 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
518 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
519 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
521 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
522 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
523 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
525 enum i40e_rx_desc_fltstat_values {
526 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
527 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
528 I40E_RX_DESC_FLTSTAT_RSV = 2,
529 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
532 #define I40E_RXD_QW1_ERROR_SHIFT 19
533 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
535 enum i40e_rx_desc_error_bits {
536 /* Note: These are predefined bit offsets */
537 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
538 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
539 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
540 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
541 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
542 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
543 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
544 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
545 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
548 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
549 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
550 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
551 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
552 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
553 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
556 #define I40E_RXD_QW1_PTYPE_SHIFT 30
557 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
559 /* Packet type non-ip values */
560 enum i40e_rx_l2_ptype {
561 I40E_RX_PTYPE_L2_RESERVED = 0,
562 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
563 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
564 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
565 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
566 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
567 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
568 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
569 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
570 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
571 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
572 I40E_RX_PTYPE_L2_ARP = 11,
573 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
574 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
575 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
576 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
577 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
578 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
579 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
580 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
581 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
582 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
583 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
584 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
585 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
586 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
589 struct i40e_rx_ptype_decoded {
596 u32 tunnel_end_prot:2;
597 u32 tunnel_end_frag:1;
602 enum i40e_rx_ptype_outer_ip {
603 I40E_RX_PTYPE_OUTER_L2 = 0,
604 I40E_RX_PTYPE_OUTER_IP = 1
607 enum i40e_rx_ptype_outer_ip_ver {
608 I40E_RX_PTYPE_OUTER_NONE = 0,
609 I40E_RX_PTYPE_OUTER_IPV4 = 0,
610 I40E_RX_PTYPE_OUTER_IPV6 = 1
613 enum i40e_rx_ptype_outer_fragmented {
614 I40E_RX_PTYPE_NOT_FRAG = 0,
615 I40E_RX_PTYPE_FRAG = 1
618 enum i40e_rx_ptype_tunnel_type {
619 I40E_RX_PTYPE_TUNNEL_NONE = 0,
620 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
621 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
622 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
623 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
626 enum i40e_rx_ptype_tunnel_end_prot {
627 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
628 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
629 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
632 enum i40e_rx_ptype_inner_prot {
633 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
634 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
635 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
636 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
637 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
638 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
641 enum i40e_rx_ptype_payload_layer {
642 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
643 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
644 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
645 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
648 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
649 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
650 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
652 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
653 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
654 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
656 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
657 #define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
658 I40E_RXD_QW1_LENGTH_SPH_SHIFT)
660 enum i40e_rx_desc_ext_status_bits {
661 /* Note: These are predefined bit offsets */
662 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
663 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
664 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
665 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
666 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
667 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
668 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
671 enum i40e_rx_desc_pe_status_bits {
672 /* Note: These are predefined bit offsets */
673 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
674 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
675 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
676 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
677 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
678 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
679 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
680 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
681 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
684 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
685 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
687 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
688 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
689 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
691 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
692 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
693 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
695 enum i40e_rx_prog_status_desc_status_bits {
696 /* Note: These are predefined bit offsets */
697 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
698 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
701 enum i40e_rx_prog_status_desc_prog_id_masks {
702 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
703 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
704 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
707 enum i40e_rx_prog_status_desc_error_bits {
708 /* Note: These are predefined bit offsets */
709 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
710 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
711 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
712 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
716 struct i40e_tx_desc {
717 __le64 buffer_addr; /* Address of descriptor's data buf */
718 __le64 cmd_type_offset_bsz;
721 #define I40E_TXD_QW1_DTYPE_SHIFT 0
722 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
724 enum i40e_tx_desc_dtype_value {
725 I40E_TX_DESC_DTYPE_DATA = 0x0,
726 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
727 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
728 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
729 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
730 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
731 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
732 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
733 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
734 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
737 #define I40E_TXD_QW1_CMD_SHIFT 4
738 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
740 enum i40e_tx_desc_cmd_bits {
741 I40E_TX_DESC_CMD_EOP = 0x0001,
742 I40E_TX_DESC_CMD_RS = 0x0002,
743 I40E_TX_DESC_CMD_ICRC = 0x0004,
744 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
745 I40E_TX_DESC_CMD_DUMMY = 0x0010,
746 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
747 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
748 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
749 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
750 I40E_TX_DESC_CMD_FCOET = 0x0080,
751 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
752 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
753 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
754 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
755 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
756 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
757 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
758 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
761 #define I40E_TXD_QW1_OFFSET_SHIFT 16
762 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
763 I40E_TXD_QW1_OFFSET_SHIFT)
765 enum i40e_tx_desc_length_fields {
766 /* Note: These are predefined bit offsets */
767 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
768 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
769 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
772 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
773 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
774 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
776 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
777 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
779 /* Context descriptors */
780 struct i40e_tx_context_desc {
781 __le32 tunneling_params;
784 __le64 type_cmd_tso_mss;
787 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
788 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
790 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
791 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
793 enum i40e_tx_ctx_desc_cmd_bits {
794 I40E_TX_CTX_DESC_TSO = 0x01,
795 I40E_TX_CTX_DESC_TSYN = 0x02,
796 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
797 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
798 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
799 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
800 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
801 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
802 I40E_TX_CTX_DESC_SWPE = 0x40
805 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
806 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
807 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
809 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
810 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
811 I40E_TXD_CTX_QW1_MSS_SHIFT)
813 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
814 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
816 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
817 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
818 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
820 enum i40e_tx_ctx_desc_eipt_offload {
821 I40E_TX_CTX_EXT_IP_NONE = 0x0,
822 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
823 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
824 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
827 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
828 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
829 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
831 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
832 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
834 #define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
835 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
837 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
838 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
839 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
841 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
843 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
844 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
845 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
847 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
848 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
849 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
851 struct i40e_filter_program_desc {
852 __le32 qindex_flex_ptype_vsi;
854 __le32 dtype_cmd_cntindex;
857 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
858 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
859 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
860 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
861 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
862 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
863 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
864 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
865 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
867 /* Packet Classifier Types for filters */
868 enum i40e_filter_pctype {
869 /* Note: Values 0-30 are reserved for future use */
870 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
871 /* Note: Value 32 is reserved for future use */
872 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
873 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
874 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
875 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
876 /* Note: Values 37-40 are reserved for future use */
877 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
878 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN = 42,
879 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
880 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
881 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
882 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
883 /* Note: Value 47 is reserved for future use */
884 I40E_FILTER_PCTYPE_FCOE_OX = 48,
885 I40E_FILTER_PCTYPE_FCOE_RX = 49,
886 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
887 /* Note: Values 51-62 are reserved for future use */
888 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
891 enum i40e_filter_program_desc_dest {
892 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
893 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
894 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
897 enum i40e_filter_program_desc_fd_status {
898 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
899 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
900 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
901 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
904 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
905 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
906 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
908 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
909 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
910 I40E_TXD_FLTR_QW1_CMD_SHIFT)
912 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
913 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
915 enum i40e_filter_program_desc_pcmd {
916 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
917 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
920 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
921 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
923 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
924 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
925 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
927 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
928 I40E_TXD_FLTR_QW1_CMD_SHIFT)
929 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
930 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
932 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
933 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
934 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
936 enum i40e_filter_type {
937 I40E_FLOW_DIRECTOR_FLTR = 0,
938 I40E_PE_QUAD_HASH_FLTR = 1,
945 struct i40e_vsi_context {
950 u16 vsis_unallocated;
955 struct i40e_aqc_vsi_properties_data info;
958 struct i40e_veb_context {
963 u16 vebs_unallocated;
965 struct i40e_aqc_get_veb_parameters_completion info;
968 /* Statistics collected by each port, VSI, VEB, and S-channel */
969 struct i40e_eth_stats {
970 u64 rx_bytes; /* gorc */
971 u64 rx_unicast; /* uprc */
972 u64 rx_multicast; /* mprc */
973 u64 rx_broadcast; /* bprc */
974 u64 rx_discards; /* rdpc */
975 u64 rx_unknown_protocol; /* rupp */
976 u64 tx_bytes; /* gotc */
977 u64 tx_unicast; /* uptc */
978 u64 tx_multicast; /* mptc */
979 u64 tx_broadcast; /* bptc */
980 u64 tx_discards; /* tdpc */
981 u64 tx_errors; /* tepc */
984 /* Statistics collected by the MAC */
985 struct i40e_hw_port_stats {
986 /* eth stats collected by the port */
987 struct i40e_eth_stats eth;
989 /* additional port specific stats */
990 u64 tx_dropped_link_down; /* tdold */
991 u64 crc_errors; /* crcerrs */
992 u64 illegal_bytes; /* illerrc */
993 u64 error_bytes; /* errbc */
994 u64 mac_local_faults; /* mlfc */
995 u64 mac_remote_faults; /* mrfc */
996 u64 rx_length_errors; /* rlec */
997 u64 link_xon_rx; /* lxonrxc */
998 u64 link_xoff_rx; /* lxoffrxc */
999 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1000 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1001 u64 link_xon_tx; /* lxontxc */
1002 u64 link_xoff_tx; /* lxofftxc */
1003 u64 priority_xon_tx[8]; /* pxontxc[8] */
1004 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1005 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1006 u64 rx_size_64; /* prc64 */
1007 u64 rx_size_127; /* prc127 */
1008 u64 rx_size_255; /* prc255 */
1009 u64 rx_size_511; /* prc511 */
1010 u64 rx_size_1023; /* prc1023 */
1011 u64 rx_size_1522; /* prc1522 */
1012 u64 rx_size_big; /* prc9522 */
1013 u64 rx_undersize; /* ruc */
1014 u64 rx_fragments; /* rfc */
1015 u64 rx_oversize; /* roc */
1016 u64 rx_jabber; /* rjc */
1017 u64 tx_size_64; /* ptc64 */
1018 u64 tx_size_127; /* ptc127 */
1019 u64 tx_size_255; /* ptc255 */
1020 u64 tx_size_511; /* ptc511 */
1021 u64 tx_size_1023; /* ptc1023 */
1022 u64 tx_size_1522; /* ptc1522 */
1023 u64 tx_size_big; /* ptc9522 */
1024 u64 mac_short_packet_dropped; /* mspdc */
1025 u64 checksum_error; /* xec */
1026 /* flow director stats */
1032 u64 tx_lpi_count; /* etlpic */
1033 u64 rx_lpi_count; /* erlpic */
1036 /* Checksum and Shadow RAM pointers */
1037 #define I40E_SR_NVM_CONTROL_WORD 0x00
1038 #define I40E_SR_EMP_MODULE_PTR 0x0F
1039 #define I40E_SR_NVM_IMAGE_VERSION 0x18
1040 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1041 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1042 #define I40E_SR_NVM_EETRACK_LO 0x2D
1043 #define I40E_SR_NVM_EETRACK_HI 0x2E
1044 #define I40E_SR_VPD_PTR 0x2F
1045 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1046 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1048 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1049 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1050 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1051 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1052 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1054 /* Shadow RAM related */
1055 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1056 #define I40E_SR_WORDS_IN_1KB 512
1057 /* Checksum should be calculated such that after adding all the words,
1058 * including the checksum word itself, the sum should be 0xBABA.
1060 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1062 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1064 enum i40e_switch_element_types {
1065 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1066 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1067 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1068 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1069 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1070 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1071 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1072 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1073 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1076 /* Supported EtherType filters */
1077 enum i40e_ether_type_index {
1078 I40E_ETHER_TYPE_1588 = 0,
1079 I40E_ETHER_TYPE_FIP = 1,
1080 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1081 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1082 I40E_ETHER_TYPE_LLDP = 4,
1083 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1084 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1085 I40E_ETHER_TYPE_QCN_CNM = 7,
1086 I40E_ETHER_TYPE_8021X = 8,
1087 I40E_ETHER_TYPE_ARP = 9,
1088 I40E_ETHER_TYPE_RSV1 = 10,
1089 I40E_ETHER_TYPE_RSV2 = 11,
1092 /* Filter context base size is 1K */
1093 #define I40E_HASH_FILTER_BASE_SIZE 1024
1094 /* Supported Hash filter values */
1095 enum i40e_hash_filter_size {
1096 I40E_HASH_FILTER_SIZE_1K = 0,
1097 I40E_HASH_FILTER_SIZE_2K = 1,
1098 I40E_HASH_FILTER_SIZE_4K = 2,
1099 I40E_HASH_FILTER_SIZE_8K = 3,
1100 I40E_HASH_FILTER_SIZE_16K = 4,
1101 I40E_HASH_FILTER_SIZE_32K = 5,
1102 I40E_HASH_FILTER_SIZE_64K = 6,
1103 I40E_HASH_FILTER_SIZE_128K = 7,
1104 I40E_HASH_FILTER_SIZE_256K = 8,
1105 I40E_HASH_FILTER_SIZE_512K = 9,
1106 I40E_HASH_FILTER_SIZE_1M = 10,
1109 /* DMA context base size is 0.5K */
1110 #define I40E_DMA_CNTX_BASE_SIZE 512
1111 /* Supported DMA context values */
1112 enum i40e_dma_cntx_size {
1113 I40E_DMA_CNTX_SIZE_512 = 0,
1114 I40E_DMA_CNTX_SIZE_1K = 1,
1115 I40E_DMA_CNTX_SIZE_2K = 2,
1116 I40E_DMA_CNTX_SIZE_4K = 3,
1117 I40E_DMA_CNTX_SIZE_8K = 4,
1118 I40E_DMA_CNTX_SIZE_16K = 5,
1119 I40E_DMA_CNTX_SIZE_32K = 6,
1120 I40E_DMA_CNTX_SIZE_64K = 7,
1121 I40E_DMA_CNTX_SIZE_128K = 8,
1122 I40E_DMA_CNTX_SIZE_256K = 9,
1125 /* Supported Hash look up table (LUT) sizes */
1126 enum i40e_hash_lut_size {
1127 I40E_HASH_LUT_SIZE_128 = 0,
1128 I40E_HASH_LUT_SIZE_512 = 1,
1131 /* Structure to hold a per PF filter control settings */
1132 struct i40e_filter_control_settings {
1133 /* number of PE Quad Hash filter buckets */
1134 enum i40e_hash_filter_size pe_filt_num;
1135 /* number of PE Quad Hash contexts */
1136 enum i40e_dma_cntx_size pe_cntx_num;
1137 /* number of FCoE filter buckets */
1138 enum i40e_hash_filter_size fcoe_filt_num;
1139 /* number of FCoE DDP contexts */
1140 enum i40e_dma_cntx_size fcoe_cntx_num;
1141 /* size of the Hash LUT */
1142 enum i40e_hash_lut_size hash_lut_size;
1143 /* enable FDIR filters for PF and its VFs */
1145 /* enable Ethertype filters for PF and its VFs */
1146 bool enable_ethtype;
1147 /* enable MAC/VLAN filters for PF and its VFs */
1148 bool enable_macvlan;
1151 /* Structure to hold device level control filter counts */
1152 struct i40e_control_filter_stats {
1153 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1154 u16 etype_used; /* Used perfect EtherType filters */
1155 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1156 u16 etype_free; /* Un-used perfect EtherType filters */
1159 enum i40e_reset_type {
1161 I40E_RESET_CORER = 1,
1162 I40E_RESET_GLOBR = 2,
1163 I40E_RESET_EMPR = 3,
1165 #endif /* _I40E_TYPE_H_ */