drivers/net/ethernet/intel/igb/e1000_82575.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* e1000_82575
  29  * e1000_82576
  30  */
  31
  32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  33
  34 #include <linux/types.h>
  35 #include <linux/if_ether.h>
  36 #include <linux/i2c.h>
  37
  38 #include "e1000_mac.h"
  39 #include "e1000_82575.h"
  40 #include "e1000_i210.h"
  41
  42 static s32  igb_get_invariants_82575(struct e1000_hw *);
  43 static s32  igb_acquire_phy_82575(struct e1000_hw *);
  44 static void igb_release_phy_82575(struct e1000_hw *);
  45 static s32  igb_acquire_nvm_82575(struct e1000_hw *);
  46 static void igb_release_nvm_82575(struct e1000_hw *);
  47 static s32  igb_check_for_link_82575(struct e1000_hw *);
  48 static s32  igb_get_cfg_done_82575(struct e1000_hw *);
  49 static s32  igb_init_hw_82575(struct e1000_hw *);
  50 static s32  igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
  51 static s32  igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
  52 static s32  igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
  53 static s32  igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
  54 static s32  igb_reset_hw_82575(struct e1000_hw *);
  55 static s32  igb_reset_hw_82580(struct e1000_hw *);
  56 static s32  igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
  57 static s32  igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
  58 static s32  igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
  59 static s32  igb_setup_copper_link_82575(struct e1000_hw *);
  60 static s32  igb_setup_serdes_link_82575(struct e1000_hw *);
  61 static s32  igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
  62 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
  63 static s32  igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
  64 static s32  igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
  65                                                  u16 *);
  66 static s32  igb_get_phy_id_82575(struct e1000_hw *);
  67 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
  68 static bool igb_sgmii_active_82575(struct e1000_hw *);
  69 static s32  igb_reset_init_script_82575(struct e1000_hw *);
  70 static s32  igb_read_mac_addr_82575(struct e1000_hw *);
  71 static s32  igb_set_pcie_completion_timeout(struct e1000_hw *hw);
  72 static s32  igb_reset_mdicnfg_82580(struct e1000_hw *hw);
  73 static s32  igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
  74 static s32  igb_update_nvm_checksum_82580(struct e1000_hw *hw);
  75 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
  76 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
  77 static const u16 e1000_82580_rxpbs_table[] =
  78         { 36, 72, 144, 1, 2, 4, 8, 16,
  79           35, 70, 140 };
  80 #define E1000_82580_RXPBS_TABLE_SIZE \
  81         (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
  82
  83 /**
  84  *  igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
  85  *  @hw: pointer to the HW structure
  86  *
  87  *  Called to determine if the I2C pins are being used for I2C or as an
  88  *  external MDIO interface since the two options are mutually exclusive.
  89  **/
  90 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
  91 {
  92         u32 reg = 0;
  93         bool ext_mdio = false;
  94
  95         switch (hw->mac.type) {
  96         case e1000_82575:
  97         case e1000_82576:
  98                 reg = rd32(E1000_MDIC);
  99                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 100                 break;
 101         case e1000_82580:
 102         case e1000_i350:
 103         case e1000_i354:
 104         case e1000_i210:
 105         case e1000_i211:
 106                 reg = rd32(E1000_MDICNFG);
 107                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 108                 break;
 109         default:
 110                 break;
 111         }
 112         return ext_mdio;
 113 }
 114
 115 /**
 116  *  igb_init_phy_params_82575 - Init PHY func ptrs.
 117  *  @hw: pointer to the HW structure
 118  **/
 119 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
 120 {
 121         struct e1000_phy_info *phy = &hw->phy;
 122         s32 ret_val = 0;
 123         u32 ctrl_ext;
 124
 125         if (hw->phy.media_type != e1000_media_type_copper) {
 126                 phy->type = e1000_phy_none;
 127                 goto out;
 128         }
 129
 130         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 131         phy->reset_delay_us     = 100;
 132
 133         ctrl_ext = rd32(E1000_CTRL_EXT);
 134
 135         if (igb_sgmii_active_82575(hw)) {
 136                 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
 137                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 138         } else {
 139                 phy->ops.reset = igb_phy_hw_reset;
 140                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 141         }
 142
 143         wr32(E1000_CTRL_EXT, ctrl_ext);
 144         igb_reset_mdicnfg_82580(hw);
 145
 146         if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
 147                 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
 148                 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
 149         } else {
 150                 switch (hw->mac.type) {
 151                 case e1000_82580:
 152                 case e1000_i350:
 153                 case e1000_i354:
 154                         phy->ops.read_reg = igb_read_phy_reg_82580;
 155                         phy->ops.write_reg = igb_write_phy_reg_82580;
 156                         break;
 157                 case e1000_i210:
 158                 case e1000_i211:
 159                         phy->ops.read_reg = igb_read_phy_reg_gs40g;
 160                         phy->ops.write_reg = igb_write_phy_reg_gs40g;
 161                         break;
 162                 default:
 163                         phy->ops.read_reg = igb_read_phy_reg_igp;
 164                         phy->ops.write_reg = igb_write_phy_reg_igp;
 165                 }
 166         }
 167
 168         /* set lan id */
 169         hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
 170                         E1000_STATUS_FUNC_SHIFT;
 171
 172         /* Set phy->phy_addr and phy->id. */
 173         ret_val = igb_get_phy_id_82575(hw);
 174         if (ret_val)
 175                 return ret_val;
 176
 177         /* Verify phy id and set remaining function pointers */
 178         switch (phy->id) {
 179         case M88E1543_E_PHY_ID:
 180         case I347AT4_E_PHY_ID:
 181         case M88E1112_E_PHY_ID:
 182         case M88E1111_I_PHY_ID:
 183                 phy->type               = e1000_phy_m88;
 184                 phy->ops.check_polarity = igb_check_polarity_m88;
 185                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 186                 if (phy->id != M88E1111_I_PHY_ID)
 187                         phy->ops.get_cable_length =
 188                                          igb_get_cable_length_m88_gen2;
 189                 else
 190                         phy->ops.get_cable_length = igb_get_cable_length_m88;
 191                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 192                 break;
 193         case IGP03E1000_E_PHY_ID:
 194                 phy->type = e1000_phy_igp_3;
 195                 phy->ops.get_phy_info = igb_get_phy_info_igp;
 196                 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
 197                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
 198                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
 199                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
 200                 break;
 201         case I82580_I_PHY_ID:
 202         case I350_I_PHY_ID:
 203                 phy->type = e1000_phy_82580;
 204                 phy->ops.force_speed_duplex =
 205                                          igb_phy_force_speed_duplex_82580;
 206                 phy->ops.get_cable_length = igb_get_cable_length_82580;
 207                 phy->ops.get_phy_info = igb_get_phy_info_82580;
 208                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 209                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 210                 break;
 211         case I210_I_PHY_ID:
 212                 phy->type               = e1000_phy_i210;
 213                 phy->ops.check_polarity = igb_check_polarity_m88;
 214                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 215                 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
 216                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 217                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 218                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 219                 break;
 220         default:
 221                 ret_val = -E1000_ERR_PHY;
 222                 goto out;
 223         }
 224
 225 out:
 226         return ret_val;
 227 }
 228
 229 /**
 230  *  igb_init_nvm_params_82575 - Init NVM func ptrs.
 231  *  @hw: pointer to the HW structure
 232  **/
 233 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
 234 {
 235         struct e1000_nvm_info *nvm = &hw->nvm;
 236         u32 eecd = rd32(E1000_EECD);
 237         u16 size;
 238
 239         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 240                      E1000_EECD_SIZE_EX_SHIFT);
 241
 242         /* Added to a constant, "size" becomes the left-shift value
 243          * for setting word_size.
 244          */
 245         size += NVM_WORD_SIZE_BASE_SHIFT;
 246
 247         /* Just in case size is out of range, cap it to the largest
 248          * EEPROM size supported
 249          */
 250         if (size > 15)
 251                 size = 15;
 252
 253         nvm->word_size = 1 << size;
 254         nvm->opcode_bits = 8;
 255         nvm->delay_usec = 1;
 256
 257         switch (nvm->override) {
 258         case e1000_nvm_override_spi_large:
 259                 nvm->page_size = 32;
 260                 nvm->address_bits = 16;
 261                 break;
 262         case e1000_nvm_override_spi_small:
 263                 nvm->page_size = 8;
 264                 nvm->address_bits = 8;
 265                 break;
 266         default:
 267                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 268                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 269                                     16 : 8;
 270                 break;
 271         }
 272         if (nvm->word_size == (1 << 15))
 273                 nvm->page_size = 128;
 274
 275         nvm->type = e1000_nvm_eeprom_spi;
 276
 277         /* NVM Function Pointers */
 278         nvm->ops.acquire = igb_acquire_nvm_82575;
 279         nvm->ops.release = igb_release_nvm_82575;
 280         nvm->ops.write = igb_write_nvm_spi;
 281         nvm->ops.validate = igb_validate_nvm_checksum;
 282         nvm->ops.update = igb_update_nvm_checksum;
 283         if (nvm->word_size < (1 << 15))
 284                 nvm->ops.read = igb_read_nvm_eerd;
 285         else
 286                 nvm->ops.read = igb_read_nvm_spi;
 287
 288         /* override generic family function pointers for specific descendants */
 289         switch (hw->mac.type) {
 290         case e1000_82580:
 291                 nvm->ops.validate = igb_validate_nvm_checksum_82580;
 292                 nvm->ops.update = igb_update_nvm_checksum_82580;
 293                 break;
 294         case e1000_i354:
 295         case e1000_i350:
 296                 nvm->ops.validate = igb_validate_nvm_checksum_i350;
 297                 nvm->ops.update = igb_update_nvm_checksum_i350;
 298                 break;
 299         default:
 300                 break;
 301         }
 302
 303         return 0;
 304 }
 305
 306 /**
 307  *  igb_init_mac_params_82575 - Init MAC func ptrs.
 308  *  @hw: pointer to the HW structure
 309  **/
 310 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
 311 {
 312         struct e1000_mac_info *mac = &hw->mac;
 313         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 314
 315         /* Set mta register count */
 316         mac->mta_reg_count = 128;
 317         /* Set rar entry count */
 318         switch (mac->type) {
 319         case e1000_82576:
 320                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 321                 break;
 322         case e1000_82580:
 323                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 324                 break;
 325         case e1000_i350:
 326         case e1000_i354:
 327                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 328                 break;
 329         default:
 330                 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 331                 break;
 332         }
 333         /* reset */
 334         if (mac->type >= e1000_82580)
 335                 mac->ops.reset_hw = igb_reset_hw_82580;
 336         else
 337                 mac->ops.reset_hw = igb_reset_hw_82575;
 338
 339         if (mac->type >= e1000_i210) {
 340                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
 341                 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
 342
 343         } else {
 344                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
 345                 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
 346         }
 347
 348         /* Set if part includes ASF firmware */
 349         mac->asf_firmware_present = true;
 350         /* Set if manageability features are enabled. */
 351         mac->arc_subsystem_valid =
 352                 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
 353                         ? true : false;
 354         /* enable EEE on i350 parts and later parts */
 355         if (mac->type >= e1000_i350)
 356                 dev_spec->eee_disable = false;
 357         else
 358                 dev_spec->eee_disable = true;
 359         /* Allow a single clear of the SW semaphore on I210 and newer */
 360         if (mac->type >= e1000_i210)
 361                 dev_spec->clear_semaphore_once = true;
 362         /* physical interface link setup */
 363         mac->ops.setup_physical_interface =
 364                 (hw->phy.media_type == e1000_media_type_copper)
 365                         ? igb_setup_copper_link_82575
 366                         : igb_setup_serdes_link_82575;
 367
 368         return 0;
 369 }
 370
 371 /**
 372  *  igb_set_sfp_media_type_82575 - derives SFP module media type.
 373  *  @hw: pointer to the HW structure
 374  *
 375  *  The media type is chosen based on SFP module.
 376  *  compatibility flags retrieved from SFP ID EEPROM.
 377  **/
 378 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
 379 {
 380         s32 ret_val = E1000_ERR_CONFIG;
 381         u32 ctrl_ext = 0;
 382         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 383         struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
 384         u8 tranceiver_type = 0;
 385         s32 timeout = 3;
 386
 387         /* Turn I2C interface ON and power on sfp cage */
 388         ctrl_ext = rd32(E1000_CTRL_EXT);
 389         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
 390         wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
 391
 392         wrfl();
 393
 394         /* Read SFP module data */
 395         while (timeout) {
 396                 ret_val = igb_read_sfp_data_byte(hw,
 397                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
 398                         &tranceiver_type);
 399                 if (ret_val == 0)
 400                         break;
 401                 msleep(100);
 402                 timeout--;
 403         }
 404         if (ret_val != 0)
 405                 goto out;
 406
 407         ret_val = igb_read_sfp_data_byte(hw,
 408                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
 409                         (u8 *)eth_flags);
 410         if (ret_val != 0)
 411                 goto out;
 412
 413         /* Check if there is some SFP module plugged and powered */
 414         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
 415             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
 416                 dev_spec->module_plugged = true;
 417                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
 418                         hw->phy.media_type = e1000_media_type_internal_serdes;
 419                 } else if (eth_flags->e100_base_fx) {
 420                         dev_spec->sgmii_active = true;
 421                         hw->phy.media_type = e1000_media_type_internal_serdes;
 422                 } else if (eth_flags->e1000_base_t) {
 423                         dev_spec->sgmii_active = true;
 424                         hw->phy.media_type = e1000_media_type_copper;
 425                 } else {
 426                         hw->phy.media_type = e1000_media_type_unknown;
 427                         hw_dbg("PHY module has not been recognized\n");
 428                         goto out;
 429                 }
 430         } else {
 431                 hw->phy.media_type = e1000_media_type_unknown;
 432         }
 433         ret_val = 0;
 434 out:
 435         /* Restore I2C interface setting */
 436         wr32(E1000_CTRL_EXT, ctrl_ext);
 437         return ret_val;
 438 }
 439
 440 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
 441 {
 442         struct e1000_mac_info *mac = &hw->mac;
 443         struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
 444         s32 ret_val;
 445         u32 ctrl_ext = 0;
 446         u32 link_mode = 0;
 447
 448         switch (hw->device_id) {
 449         case E1000_DEV_ID_82575EB_COPPER:
 450         case E1000_DEV_ID_82575EB_FIBER_SERDES:
 451         case E1000_DEV_ID_82575GB_QUAD_COPPER:
 452                 mac->type = e1000_82575;
 453                 break;
 454         case E1000_DEV_ID_82576:
 455         case E1000_DEV_ID_82576_NS:
 456         case E1000_DEV_ID_82576_NS_SERDES:
 457         case E1000_DEV_ID_82576_FIBER:
 458         case E1000_DEV_ID_82576_SERDES:
 459         case E1000_DEV_ID_82576_QUAD_COPPER:
 460         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
 461         case E1000_DEV_ID_82576_SERDES_QUAD:
 462                 mac->type = e1000_82576;
 463                 break;
 464         case E1000_DEV_ID_82580_COPPER:
 465         case E1000_DEV_ID_82580_FIBER:
 466         case E1000_DEV_ID_82580_QUAD_FIBER:
 467         case E1000_DEV_ID_82580_SERDES:
 468         case E1000_DEV_ID_82580_SGMII:
 469         case E1000_DEV_ID_82580_COPPER_DUAL:
 470         case E1000_DEV_ID_DH89XXCC_SGMII:
 471         case E1000_DEV_ID_DH89XXCC_SERDES:
 472         case E1000_DEV_ID_DH89XXCC_BACKPLANE:
 473         case E1000_DEV_ID_DH89XXCC_SFP:
 474                 mac->type = e1000_82580;
 475                 break;
 476         case E1000_DEV_ID_I350_COPPER:
 477         case E1000_DEV_ID_I350_FIBER:
 478         case E1000_DEV_ID_I350_SERDES:
 479         case E1000_DEV_ID_I350_SGMII:
 480                 mac->type = e1000_i350;
 481                 break;
 482         case E1000_DEV_ID_I210_COPPER:
 483         case E1000_DEV_ID_I210_FIBER:
 484         case E1000_DEV_ID_I210_SERDES:
 485         case E1000_DEV_ID_I210_SGMII:
 486         case E1000_DEV_ID_I210_COPPER_FLASHLESS:
 487         case E1000_DEV_ID_I210_SERDES_FLASHLESS:
 488                 mac->type = e1000_i210;
 489                 break;
 490         case E1000_DEV_ID_I211_COPPER:
 491                 mac->type = e1000_i211;
 492                 break;
 493         case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
 494         case E1000_DEV_ID_I354_SGMII:
 495         case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
 496                 mac->type = e1000_i354;
 497                 break;
 498         default:
 499                 return -E1000_ERR_MAC_INIT;
 500                 break;
 501         }
 502
 503         /* Set media type */
 504         /* The 82575 uses bits 22:23 for link mode. The mode can be changed
 505          * based on the EEPROM. We cannot rely upon device ID. There
 506          * is no distinguishable difference between fiber and internal
 507          * SerDes mode on the 82575. There can be an external PHY attached
 508          * on the SGMII interface. For this, we'll set sgmii_active to true.
 509          */
 510         hw->phy.media_type = e1000_media_type_copper;
 511         dev_spec->sgmii_active = false;
 512         dev_spec->module_plugged = false;
 513
 514         ctrl_ext = rd32(E1000_CTRL_EXT);
 515
 516         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
 517         switch (link_mode) {
 518         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
 519                 hw->phy.media_type = e1000_media_type_internal_serdes;
 520                 break;
 521         case E1000_CTRL_EXT_LINK_MODE_SGMII:
 522                 /* Get phy control interface type set (MDIO vs. I2C)*/
 523                 if (igb_sgmii_uses_mdio_82575(hw)) {
 524                         hw->phy.media_type = e1000_media_type_copper;
 525                         dev_spec->sgmii_active = true;
 526                         break;
 527                 }
 528                 /* fall through for I2C based SGMII */
 529         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
 530                 /* read media type from SFP EEPROM */
 531                 ret_val = igb_set_sfp_media_type_82575(hw);
 532                 if ((ret_val != 0) ||
 533                     (hw->phy.media_type == e1000_media_type_unknown)) {
 534                         /* If media type was not identified then return media
 535                          * type defined by the CTRL_EXT settings.
 536                          */
 537                         hw->phy.media_type = e1000_media_type_internal_serdes;
 538
 539                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
 540                                 hw->phy.media_type = e1000_media_type_copper;
 541                                 dev_spec->sgmii_active = true;
 542                         }
 543
 544                         break;
 545                 }
 546
 547                 /* do not change link mode for 100BaseFX */
 548                 if (dev_spec->eth_flags.e100_base_fx)
 549                         break;
 550
 551                 /* change current link mode setting */
 552                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
 553
 554                 if (hw->phy.media_type == e1000_media_type_copper)
 555                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
 556                 else
 557                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
 558
 559                 wr32(E1000_CTRL_EXT, ctrl_ext);
 560
 561                 break;
 562         default:
 563                 break;
 564         }
 565
 566         /* mac initialization and operations */
 567         ret_val = igb_init_mac_params_82575(hw);
 568         if (ret_val)
 569                 goto out;
 570
 571         /* NVM initialization */
 572         ret_val = igb_init_nvm_params_82575(hw);
 573         switch (hw->mac.type) {
 574         case e1000_i210:
 575         case e1000_i211:
 576                 ret_val = igb_init_nvm_params_i210(hw);
 577                 break;
 578         default:
 579                 break;
 580         }
 581
 582         if (ret_val)
 583                 goto out;
 584
 585         /* if part supports SR-IOV then initialize mailbox parameters */
 586         switch (mac->type) {
 587         case e1000_82576:
 588         case e1000_i350:
 589                 igb_init_mbx_params_pf(hw);
 590                 break;
 591         default:
 592                 break;
 593         }
 594
 595         /* setup PHY parameters */
 596         ret_val = igb_init_phy_params_82575(hw);
 597
 598 out:
 599         return ret_val;
 600 }
 601
 602 /**
 603  *  igb_acquire_phy_82575 - Acquire rights to access PHY
 604  *  @hw: pointer to the HW structure
 605  *
 606  *  Acquire access rights to the correct PHY.  This is a
 607  *  function pointer entry point called by the api module.
 608  **/
 609 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
 610 {
 611         u16 mask = E1000_SWFW_PHY0_SM;
 612
 613         if (hw->bus.func == E1000_FUNC_1)
 614                 mask = E1000_SWFW_PHY1_SM;
 615         else if (hw->bus.func == E1000_FUNC_2)
 616                 mask = E1000_SWFW_PHY2_SM;
 617         else if (hw->bus.func == E1000_FUNC_3)
 618                 mask = E1000_SWFW_PHY3_SM;
 619
 620         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 621 }
 622
 623 /**
 624  *  igb_release_phy_82575 - Release rights to access PHY
 625  *  @hw: pointer to the HW structure
 626  *
 627  *  A wrapper to release access rights to the correct PHY.  This is a
 628  *  function pointer entry point called by the api module.
 629  **/
 630 static void igb_release_phy_82575(struct e1000_hw *hw)
 631 {
 632         u16 mask = E1000_SWFW_PHY0_SM;
 633
 634         if (hw->bus.func == E1000_FUNC_1)
 635                 mask = E1000_SWFW_PHY1_SM;
 636         else if (hw->bus.func == E1000_FUNC_2)
 637                 mask = E1000_SWFW_PHY2_SM;
 638         else if (hw->bus.func == E1000_FUNC_3)
 639                 mask = E1000_SWFW_PHY3_SM;
 640
 641         hw->mac.ops.release_swfw_sync(hw, mask);
 642 }
 643
 644 /**
 645  *  igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 646  *  @hw: pointer to the HW structure
 647  *  @offset: register offset to be read
 648  *  @data: pointer to the read data
 649  *
 650  *  Reads the PHY register at offset using the serial gigabit media independent
 651  *  interface and stores the retrieved information in data.
 652  **/
 653 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 654                                           u16 *data)
 655 {
 656         s32 ret_val = -E1000_ERR_PARAM;
 657
 658         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 659                 hw_dbg("PHY Address %u is out of range\n", offset);
 660                 goto out;
 661         }
 662
 663         ret_val = hw->phy.ops.acquire(hw);
 664         if (ret_val)
 665                 goto out;
 666
 667         ret_val = igb_read_phy_reg_i2c(hw, offset, data);
 668
 669         hw->phy.ops.release(hw);
 670
 671 out:
 672         return ret_val;
 673 }
 674
 675 /**
 676  *  igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 677  *  @hw: pointer to the HW structure
 678  *  @offset: register offset to write to
 679  *  @data: data to write at register offset
 680  *
 681  *  Writes the data to PHY register at the offset using the serial gigabit
 682  *  media independent interface.
 683  **/
 684 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 685                                            u16 data)
 686 {
 687         s32 ret_val = -E1000_ERR_PARAM;
 688
 689
 690         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 691                 hw_dbg("PHY Address %d is out of range\n", offset);
 692                 goto out;
 693         }
 694
 695         ret_val = hw->phy.ops.acquire(hw);
 696         if (ret_val)
 697                 goto out;
 698
 699         ret_val = igb_write_phy_reg_i2c(hw, offset, data);
 700
 701         hw->phy.ops.release(hw);
 702
 703 out:
 704         return ret_val;
 705 }
 706
 707 /**
 708  *  igb_get_phy_id_82575 - Retrieve PHY addr and id
 709  *  @hw: pointer to the HW structure
 710  *
 711  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 712  *  sgmi interface.
 713  **/
 714 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
 715 {
 716         struct e1000_phy_info *phy = &hw->phy;
 717         s32  ret_val = 0;
 718         u16 phy_id;
 719         u32 ctrl_ext;
 720         u32 mdic;
 721
 722         /* For SGMII PHYs, we try the list of possible addresses until
 723          * we find one that works.  For non-SGMII PHYs
 724          * (e.g. integrated copper PHYs), an address of 1 should
 725          * work.  The result of this function should mean phy->phy_addr
 726          * and phy->id are set correctly.
 727          */
 728         if (!(igb_sgmii_active_82575(hw))) {
 729                 phy->addr = 1;
 730                 ret_val = igb_get_phy_id(hw);
 731                 goto out;
 732         }
 733
 734         if (igb_sgmii_uses_mdio_82575(hw)) {
 735                 switch (hw->mac.type) {
 736                 case e1000_82575:
 737                 case e1000_82576:
 738                         mdic = rd32(E1000_MDIC);
 739                         mdic &= E1000_MDIC_PHY_MASK;
 740                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 741                         break;
 742                 case e1000_82580:
 743                 case e1000_i350:
 744                 case e1000_i354:
 745                 case e1000_i210:
 746                 case e1000_i211:
 747                         mdic = rd32(E1000_MDICNFG);
 748                         mdic &= E1000_MDICNFG_PHY_MASK;
 749                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 750                         break;
 751                 default:
 752                         ret_val = -E1000_ERR_PHY;
 753                         goto out;
 754                         break;
 755                 }
 756                 ret_val = igb_get_phy_id(hw);
 757                 goto out;
 758         }
 759
 760         /* Power on sgmii phy if it is disabled */
 761         ctrl_ext = rd32(E1000_CTRL_EXT);
 762         wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 763         wrfl();
 764         msleep(300);
 765
 766         /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
 767          * Therefore, we need to test 1-7
 768          */
 769         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 770                 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 771                 if (ret_val == 0) {
 772                         hw_dbg("Vendor ID 0x%08X read at address %u\n",
 773                                phy_id, phy->addr);
 774                         /* At the time of this writing, The M88 part is
 775                          * the only supported SGMII PHY product.
 776                          */
 777                         if (phy_id == M88_VENDOR)
 778                                 break;
 779                 } else {
 780                         hw_dbg("PHY address %u was unreadable\n", phy->addr);
 781                 }
 782         }
 783
 784         /* A valid PHY type couldn't be found. */
 785         if (phy->addr == 8) {
 786                 phy->addr = 0;
 787                 ret_val = -E1000_ERR_PHY;
 788                 goto out;
 789         } else {
 790                 ret_val = igb_get_phy_id(hw);
 791         }
 792
 793         /* restore previous sfp cage power state */
 794         wr32(E1000_CTRL_EXT, ctrl_ext);
 795
 796 out:
 797         return ret_val;
 798 }
 799
 800 /**
 801  *  igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 802  *  @hw: pointer to the HW structure
 803  *
 804  *  Resets the PHY using the serial gigabit media independent interface.
 805  **/
 806 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 807 {
 808         s32 ret_val;
 809
 810         /* This isn't a true "hard" reset, but is the only reset
 811          * available to us at this time.
 812          */
 813
 814         hw_dbg("Soft resetting SGMII attached PHY...\n");
 815
 816         /* SFP documentation requires the following to configure the SPF module
 817          * to work on SGMII.  No further documentation is given.
 818          */
 819         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 820         if (ret_val)
 821                 goto out;
 822
 823         ret_val = igb_phy_sw_reset(hw);
 824
 825 out:
 826         return ret_val;
 827 }
 828
 829 /**
 830  *  igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 831  *  @hw: pointer to the HW structure
 832  *  @active: true to enable LPLU, false to disable
 833  *
 834  *  Sets the LPLU D0 state according to the active flag.  When
 835  *  activating LPLU this function also disables smart speed
 836  *  and vice versa.  LPLU will not be activated unless the
 837  *  device autonegotiation advertisement meets standards of
 838  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 839  *  This is a function pointer entry point only called by
 840  *  PHY setup routines.
 841  **/
 842 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 843 {
 844         struct e1000_phy_info *phy = &hw->phy;
 845         s32 ret_val;
 846         u16 data;
 847
 848         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 849         if (ret_val)
 850                 goto out;
 851
 852         if (active) {
 853                 data |= IGP02E1000_PM_D0_LPLU;
 854                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 855                                                  data);
 856                 if (ret_val)
 857                         goto out;
 858
 859                 /* When LPLU is enabled, we should disable SmartSpeed */
 860                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 861                                                 &data);
 862                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 863                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 864                                                  data);
 865                 if (ret_val)
 866                         goto out;
 867         } else {
 868                 data &= ~IGP02E1000_PM_D0_LPLU;
 869                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 870                                                  data);
 871                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 872                  * during Dx states where the power conservation is most
 873                  * important.  During driver activity we should enable
 874                  * SmartSpeed, so performance is maintained.
 875                  */
 876                 if (phy->smart_speed == e1000_smart_speed_on) {
 877                         ret_val = phy->ops.read_reg(hw,
 878                                         IGP01E1000_PHY_PORT_CONFIG, &data);
 879                         if (ret_val)
 880                                 goto out;
 881
 882                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 883                         ret_val = phy->ops.write_reg(hw,
 884                                         IGP01E1000_PHY_PORT_CONFIG, data);
 885                         if (ret_val)
 886                                 goto out;
 887                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 888                         ret_val = phy->ops.read_reg(hw,
 889                                         IGP01E1000_PHY_PORT_CONFIG, &data);
 890                         if (ret_val)
 891                                 goto out;
 892
 893                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 894                         ret_val = phy->ops.write_reg(hw,
 895                                         IGP01E1000_PHY_PORT_CONFIG, data);
 896                         if (ret_val)
 897                                 goto out;
 898                 }
 899         }
 900
 901 out:
 902         return ret_val;
 903 }
 904
 905 /**
 906  *  igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 907  *  @hw: pointer to the HW structure
 908  *  @active: true to enable LPLU, false to disable
 909  *
 910  *  Sets the LPLU D0 state according to the active flag.  When
 911  *  activating LPLU this function also disables smart speed
 912  *  and vice versa.  LPLU will not be activated unless the
 913  *  device autonegotiation advertisement meets standards of
 914  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 915  *  This is a function pointer entry point only called by
 916  *  PHY setup routines.
 917  **/
 918 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 919 {
 920         struct e1000_phy_info *phy = &hw->phy;
 921         s32 ret_val = 0;
 922         u16 data;
 923
 924         data = rd32(E1000_82580_PHY_POWER_MGMT);
 925
 926         if (active) {
 927                 data |= E1000_82580_PM_D0_LPLU;
 928
 929                 /* When LPLU is enabled, we should disable SmartSpeed */
 930                 data &= ~E1000_82580_PM_SPD;
 931         } else {
 932                 data &= ~E1000_82580_PM_D0_LPLU;
 933
 934                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 935                  * during Dx states where the power conservation is most
 936                  * important.  During driver activity we should enable
 937                  * SmartSpeed, so performance is maintained.
 938                  */
 939                 if (phy->smart_speed == e1000_smart_speed_on)
 940                         data |= E1000_82580_PM_SPD;
 941                 else if (phy->smart_speed == e1000_smart_speed_off)
 942                         data &= ~E1000_82580_PM_SPD; }
 943
 944         wr32(E1000_82580_PHY_POWER_MGMT, data);
 945         return ret_val;
 946 }
 947
 948 /**
 949  *  igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
 950  *  @hw: pointer to the HW structure
 951  *  @active: boolean used to enable/disable lplu
 952  *
 953  *  Success returns 0, Failure returns 1
 954  *
 955  *  The low power link up (lplu) state is set to the power management level D3
 956  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 957  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 958  *  is used during Dx states where the power conservation is most important.
 959  *  During driver activity, SmartSpeed should be enabled so performance is
 960  *  maintained.
 961  **/
 962 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 963 {
 964         struct e1000_phy_info *phy = &hw->phy;
 965         s32 ret_val = 0;
 966         u16 data;
 967
 968         data = rd32(E1000_82580_PHY_POWER_MGMT);
 969
 970         if (!active) {
 971                 data &= ~E1000_82580_PM_D3_LPLU;
 972                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 973                  * during Dx states where the power conservation is most
 974                  * important.  During driver activity we should enable
 975                  * SmartSpeed, so performance is maintained.
 976                  */
 977                 if (phy->smart_speed == e1000_smart_speed_on)
 978                         data |= E1000_82580_PM_SPD;
 979                 else if (phy->smart_speed == e1000_smart_speed_off)
 980                         data &= ~E1000_82580_PM_SPD;
 981         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 982                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 983                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 984                 data |= E1000_82580_PM_D3_LPLU;
 985                 /* When LPLU is enabled, we should disable SmartSpeed */
 986                 data &= ~E1000_82580_PM_SPD;
 987         }
 988
 989         wr32(E1000_82580_PHY_POWER_MGMT, data);
 990         return ret_val;
 991 }
 992
 993 /**
 994  *  igb_acquire_nvm_82575 - Request for access to EEPROM
 995  *  @hw: pointer to the HW structure
 996  *
 997  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 998  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 999  *  Return successful if access grant bit set, else clear the request for
1000  *  EEPROM access and return -E1000_ERR_NVM (-1).
1001  **/
1002 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1003 {
1004         s32 ret_val;
1005
1006         ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1007         if (ret_val)
1008                 goto out;
1009
1010         ret_val = igb_acquire_nvm(hw);
1011
1012         if (ret_val)
1013                 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1014
1015 out:
1016         return ret_val;
1017 }
1018
1019 /**
1020  *  igb_release_nvm_82575 - Release exclusive access to EEPROM
1021  *  @hw: pointer to the HW structure
1022  *
1023  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1024  *  then release the semaphores acquired.
1025  **/
1026 static void igb_release_nvm_82575(struct e1000_hw *hw)
1027 {
1028         igb_release_nvm(hw);
1029         hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1030 }
1031
1032 /**
1033  *  igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1034  *  @hw: pointer to the HW structure
1035  *  @mask: specifies which semaphore to acquire
1036  *
1037  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1038  *  will also specify which port we're acquiring the lock for.
1039  **/
1040 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1041 {
1042         u32 swfw_sync;
1043         u32 swmask = mask;
1044         u32 fwmask = mask << 16;
1045         s32 ret_val = 0;
1046         s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1047
1048         while (i < timeout) {
1049                 if (igb_get_hw_semaphore(hw)) {
1050                         ret_val = -E1000_ERR_SWFW_SYNC;
1051                         goto out;
1052                 }
1053
1054                 swfw_sync = rd32(E1000_SW_FW_SYNC);
1055                 if (!(swfw_sync & (fwmask | swmask)))
1056                         break;
1057
1058                 /* Firmware currently using resource (fwmask)
1059                  * or other software thread using resource (swmask)
1060                  */
1061                 igb_put_hw_semaphore(hw);
1062                 mdelay(5);
1063                 i++;
1064         }
1065
1066         if (i == timeout) {
1067                 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1068                 ret_val = -E1000_ERR_SWFW_SYNC;
1069                 goto out;
1070         }
1071
1072         swfw_sync |= swmask;
1073         wr32(E1000_SW_FW_SYNC, swfw_sync);
1074
1075         igb_put_hw_semaphore(hw);
1076
1077 out:
1078         return ret_val;
1079 }
1080
1081 /**
1082  *  igb_release_swfw_sync_82575 - Release SW/FW semaphore
1083  *  @hw: pointer to the HW structure
1084  *  @mask: specifies which semaphore to acquire
1085  *
1086  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1087  *  will also specify which port we're releasing the lock for.
1088  **/
1089 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1090 {
1091         u32 swfw_sync;
1092
1093         while (igb_get_hw_semaphore(hw) != 0);
1094         /* Empty */
1095
1096         swfw_sync = rd32(E1000_SW_FW_SYNC);
1097         swfw_sync &= ~mask;
1098         wr32(E1000_SW_FW_SYNC, swfw_sync);
1099
1100         igb_put_hw_semaphore(hw);
1101 }
1102
1103 /**
1104  *  igb_get_cfg_done_82575 - Read config done bit
1105  *  @hw: pointer to the HW structure
1106  *
1107  *  Read the management control register for the config done bit for
1108  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1109  *  to read the config done bit, so an error is *ONLY* logged and returns
1110  *  0.  If we were to return with error, EEPROM-less silicon
1111  *  would not be able to be reset or change link.
1112  **/
1113 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1114 {
1115         s32 timeout = PHY_CFG_TIMEOUT;
1116         s32 ret_val = 0;
1117         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1118
1119         if (hw->bus.func == 1)
1120                 mask = E1000_NVM_CFG_DONE_PORT_1;
1121         else if (hw->bus.func == E1000_FUNC_2)
1122                 mask = E1000_NVM_CFG_DONE_PORT_2;
1123         else if (hw->bus.func == E1000_FUNC_3)
1124                 mask = E1000_NVM_CFG_DONE_PORT_3;
1125
1126         while (timeout) {
1127                 if (rd32(E1000_EEMNGCTL) & mask)
1128                         break;
1129                 msleep(1);
1130                 timeout--;
1131         }
1132         if (!timeout)
1133                 hw_dbg("MNG configuration cycle has not completed.\n");
1134
1135         /* If EEPROM is not marked present, init the PHY manually */
1136         if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1137             (hw->phy.type == e1000_phy_igp_3))
1138                 igb_phy_init_script_igp3(hw);
1139
1140         return ret_val;
1141 }
1142
1143 /**
1144  *  igb_check_for_link_82575 - Check for link
1145  *  @hw: pointer to the HW structure
1146  *
1147  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1148  *  use the generic interface for determining link.
1149  **/
1150 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1151 {
1152         s32 ret_val;
1153         u16 speed, duplex;
1154
1155         if (hw->phy.media_type != e1000_media_type_copper) {
1156                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1157                                                              &duplex);
1158                 /* Use this flag to determine if link needs to be checked or
1159                  * not.  If  we have link clear the flag so that we do not
1160                  * continue to check for link.
1161                  */
1162                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1163
1164                 /* Configure Flow Control now that Auto-Neg has completed.
1165                  * First, we need to restore the desired flow control
1166                  * settings because we may have had to re-autoneg with a
1167                  * different link partner.
1168                  */
1169                 ret_val = igb_config_fc_after_link_up(hw);
1170                 if (ret_val)
1171                         hw_dbg("Error configuring flow control\n");
1172         } else {
1173                 ret_val = igb_check_for_copper_link(hw);
1174         }
1175
1176         return ret_val;
1177 }
1178
1179 /**
1180  *  igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1181  *  @hw: pointer to the HW structure
1182  **/
1183 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1184 {
1185         u32 reg;
1186
1187
1188         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1189             !igb_sgmii_active_82575(hw))
1190                 return;
1191
1192         /* Enable PCS to turn on link */
1193         reg = rd32(E1000_PCS_CFG0);
1194         reg |= E1000_PCS_CFG_PCS_EN;
1195         wr32(E1000_PCS_CFG0, reg);
1196
1197         /* Power up the laser */
1198         reg = rd32(E1000_CTRL_EXT);
1199         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1200         wr32(E1000_CTRL_EXT, reg);
1201
1202         /* flush the write to verify completion */
1203         wrfl();
1204         msleep(1);
1205 }
1206
1207 /**
1208  *  igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1209  *  @hw: pointer to the HW structure
1210  *  @speed: stores the current speed
1211  *  @duplex: stores the current duplex
1212  *
1213  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1214  *  duplex, then store the values in the pointers provided.
1215  **/
1216 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1217                                                 u16 *duplex)
1218 {
1219         struct e1000_mac_info *mac = &hw->mac;
1220         u32 pcs;
1221
1222         /* Set up defaults for the return values of this function */
1223         mac->serdes_has_link = false;
1224         *speed = 0;
1225         *duplex = 0;
1226
1227         /* Read the PCS Status register for link state. For non-copper mode,
1228          * the status register is not accurate. The PCS status register is
1229          * used instead.
1230          */
1231         pcs = rd32(E1000_PCS_LSTAT);
1232
1233         /* The link up bit determines when link is up on autoneg. The sync ok
1234          * gets set once both sides sync up and agree upon link. Stable link
1235          * can be determined by checking for both link up and link sync ok
1236          */
1237         if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1238                 mac->serdes_has_link = true;
1239
1240                 /* Detect and store PCS speed */
1241                 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
1242                         *speed = SPEED_1000;
1243                 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
1244                         *speed = SPEED_100;
1245                 } else {
1246                         *speed = SPEED_10;
1247                 }
1248
1249                 /* Detect and store PCS duplex */
1250                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
1251                         *duplex = FULL_DUPLEX;
1252                 } else {
1253                         *duplex = HALF_DUPLEX;
1254                 }
1255         }
1256
1257         return 0;
1258 }
1259
1260 /**
1261  *  igb_shutdown_serdes_link_82575 - Remove link during power down
1262  *  @hw: pointer to the HW structure
1263  *
1264  *  In the case of fiber serdes, shut down optics and PCS on driver unload
1265  *  when management pass thru is not enabled.
1266  **/
1267 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1268 {
1269         u32 reg;
1270
1271         if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1272             igb_sgmii_active_82575(hw))
1273                 return;
1274
1275         if (!igb_enable_mng_pass_thru(hw)) {
1276                 /* Disable PCS to turn off link */
1277                 reg = rd32(E1000_PCS_CFG0);
1278                 reg &= ~E1000_PCS_CFG_PCS_EN;
1279                 wr32(E1000_PCS_CFG0, reg);
1280
1281                 /* shutdown the laser */
1282                 reg = rd32(E1000_CTRL_EXT);
1283                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1284                 wr32(E1000_CTRL_EXT, reg);
1285
1286                 /* flush the write to verify completion */
1287                 wrfl();
1288                 msleep(1);
1289         }
1290 }
1291
1292 /**
1293  *  igb_reset_hw_82575 - Reset hardware
1294  *  @hw: pointer to the HW structure
1295  *
1296  *  This resets the hardware into a known state.  This is a
1297  *  function pointer entry point called by the api module.
1298  **/
1299 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1300 {
1301         u32 ctrl;
1302         s32 ret_val;
1303
1304         /* Prevent the PCI-E bus from sticking if there is no TLP connection
1305          * on the last TLP read/write transaction when MAC is reset.
1306          */
1307         ret_val = igb_disable_pcie_master(hw);
1308         if (ret_val)
1309                 hw_dbg("PCI-E Master disable polling has failed.\n");
1310
1311         /* set the completion timeout for interface */
1312         ret_val = igb_set_pcie_completion_timeout(hw);
1313         if (ret_val) {
1314                 hw_dbg("PCI-E Set completion timeout has failed.\n");
1315         }
1316
1317         hw_dbg("Masking off all interrupts\n");
1318         wr32(E1000_IMC, 0xffffffff);
1319
1320         wr32(E1000_RCTL, 0);
1321         wr32(E1000_TCTL, E1000_TCTL_PSP);
1322         wrfl();
1323
1324         msleep(10);
1325
1326         ctrl = rd32(E1000_CTRL);
1327
1328         hw_dbg("Issuing a global reset to MAC\n");
1329         wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1330
1331         ret_val = igb_get_auto_rd_done(hw);
1332         if (ret_val) {
1333                 /* When auto config read does not complete, do not
1334                  * return with an error. This can happen in situations
1335                  * where there is no eeprom and prevents getting link.
1336                  */
1337                 hw_dbg("Auto Read Done did not complete\n");
1338         }
1339
1340         /* If EEPROM is not present, run manual init scripts */
1341         if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1342                 igb_reset_init_script_82575(hw);
1343
1344         /* Clear any pending interrupt events. */
1345         wr32(E1000_IMC, 0xffffffff);
1346         rd32(E1000_ICR);
1347
1348         /* Install any alternate MAC address into RAR0 */
1349         ret_val = igb_check_alt_mac_addr(hw);
1350
1351         return ret_val;
1352 }
1353
1354 /**
1355  *  igb_init_hw_82575 - Initialize hardware
1356  *  @hw: pointer to the HW structure
1357  *
1358  *  This inits the hardware readying it for operation.
1359  **/
1360 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1361 {
1362         struct e1000_mac_info *mac = &hw->mac;
1363         s32 ret_val;
1364         u16 i, rar_count = mac->rar_entry_count;
1365
1366         /* Initialize identification LED */
1367         ret_val = igb_id_led_init(hw);
1368         if (ret_val) {
1369                 hw_dbg("Error initializing identification LED\n");
1370                 /* This is not fatal and we should not stop init due to this */
1371         }
1372
1373         /* Disabling VLAN filtering */
1374         hw_dbg("Initializing the IEEE VLAN\n");
1375         if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
1376                 igb_clear_vfta_i350(hw);
1377         else
1378                 igb_clear_vfta(hw);
1379
1380         /* Setup the receive address */
1381         igb_init_rx_addrs(hw, rar_count);
1382
1383         /* Zero out the Multicast HASH table */
1384         hw_dbg("Zeroing the MTA\n");
1385         for (i = 0; i < mac->mta_reg_count; i++)
1386                 array_wr32(E1000_MTA, i, 0);
1387
1388         /* Zero out the Unicast HASH table */
1389         hw_dbg("Zeroing the UTA\n");
1390         for (i = 0; i < mac->uta_reg_count; i++)
1391                 array_wr32(E1000_UTA, i, 0);
1392
1393         /* Setup link and flow control */
1394         ret_val = igb_setup_link(hw);
1395
1396         /* Clear all of the statistics registers (clear on read).  It is
1397          * important that we do this after we have tried to establish link
1398          * because the symbol error count will increment wildly if there
1399          * is no link.
1400          */
1401         igb_clear_hw_cntrs_82575(hw);
1402         return ret_val;
1403 }
1404
1405 /**
1406  *  igb_setup_copper_link_82575 - Configure copper link settings
1407  *  @hw: pointer to the HW structure
1408  *
1409  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1410  *  for link, once link is established calls to configure collision distance
1411  *  and flow control are called.
1412  **/
1413 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1414 {
1415         u32 ctrl;
1416         s32  ret_val;
1417         u32 phpm_reg;
1418
1419         ctrl = rd32(E1000_CTRL);
1420         ctrl |= E1000_CTRL_SLU;
1421         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1422         wr32(E1000_CTRL, ctrl);
1423
1424         /* Clear Go Link Disconnect bit on supported devices */
1425         switch (hw->mac.type) {
1426         case e1000_82580:
1427         case e1000_i350:
1428         case e1000_i210:
1429         case e1000_i211:
1430                 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1431                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1432                 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1433                 break;
1434         default:
1435                 break;
1436         }
1437
1438         ret_val = igb_setup_serdes_link_82575(hw);
1439         if (ret_val)
1440                 goto out;
1441
1442         if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1443                 /* allow time for SFP cage time to power up phy */
1444                 msleep(300);
1445
1446                 ret_val = hw->phy.ops.reset(hw);
1447                 if (ret_val) {
1448                         hw_dbg("Error resetting the PHY.\n");
1449                         goto out;
1450                 }
1451         }
1452         switch (hw->phy.type) {
1453         case e1000_phy_i210:
1454         case e1000_phy_m88:
1455                 switch (hw->phy.id) {
1456                 case I347AT4_E_PHY_ID:
1457                 case M88E1112_E_PHY_ID:
1458                 case M88E1543_E_PHY_ID:
1459                 case I210_I_PHY_ID:
1460                         ret_val = igb_copper_link_setup_m88_gen2(hw);
1461                         break;
1462                 default:
1463                         ret_val = igb_copper_link_setup_m88(hw);
1464                         break;
1465                 }
1466                 break;
1467         case e1000_phy_igp_3:
1468                 ret_val = igb_copper_link_setup_igp(hw);
1469                 break;
1470         case e1000_phy_82580:
1471                 ret_val = igb_copper_link_setup_82580(hw);
1472                 break;
1473         default:
1474                 ret_val = -E1000_ERR_PHY;
1475                 break;
1476         }
1477
1478         if (ret_val)
1479                 goto out;
1480
1481         ret_val = igb_setup_copper_link(hw);
1482 out:
1483         return ret_val;
1484 }
1485
1486 /**
1487  *  igb_setup_serdes_link_82575 - Setup link for serdes
1488  *  @hw: pointer to the HW structure
1489  *
1490  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1491  *  used on copper connections where the serialized gigabit media independent
1492  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1493  *  for auto-negotiation or forces speed/duplex.
1494  **/
1495 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1496 {
1497         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1498         bool pcs_autoneg;
1499         s32 ret_val = E1000_SUCCESS;
1500         u16 data;
1501
1502         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1503             !igb_sgmii_active_82575(hw))
1504                 return ret_val;
1505
1506
1507         /* On the 82575, SerDes loopback mode persists until it is
1508          * explicitly turned off or a power cycle is performed.  A read to
1509          * the register does not indicate its status.  Therefore, we ensure
1510          * loopback mode is disabled during initialization.
1511          */
1512         wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1513
1514         /* power on the sfp cage if present and turn on I2C */
1515         ctrl_ext = rd32(E1000_CTRL_EXT);
1516         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1517         ctrl_ext |= E1000_CTRL_I2C_ENA;
1518         wr32(E1000_CTRL_EXT, ctrl_ext);
1519
1520         ctrl_reg = rd32(E1000_CTRL);
1521         ctrl_reg |= E1000_CTRL_SLU;
1522
1523         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1524                 /* set both sw defined pins */
1525                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1526
1527                 /* Set switch control to serdes energy detect */
1528                 reg = rd32(E1000_CONNSW);
1529                 reg |= E1000_CONNSW_ENRGSRC;
1530                 wr32(E1000_CONNSW, reg);
1531         }
1532
1533         reg = rd32(E1000_PCS_LCTL);
1534
1535         /* default pcs_autoneg to the same setting as mac autoneg */
1536         pcs_autoneg = hw->mac.autoneg;
1537
1538         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1539         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1540                 /* sgmii mode lets the phy handle forcing speed/duplex */
1541                 pcs_autoneg = true;
1542                 /* autoneg time out should be disabled for SGMII mode */
1543                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1544                 break;
1545         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1546                 /* disable PCS autoneg and support parallel detect only */
1547                 pcs_autoneg = false;
1548         default:
1549                 if (hw->mac.type == e1000_82575 ||
1550                     hw->mac.type == e1000_82576) {
1551                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1552                         if (ret_val) {
1553                                 printk(KERN_DEBUG "NVM Read Error\n\n");
1554                                 return ret_val;
1555                         }
1556
1557                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1558                                 pcs_autoneg = false;
1559                 }
1560
1561                 /* non-SGMII modes only supports a speed of 1000/Full for the
1562                  * link so it is best to just force the MAC and let the pcs
1563                  * link either autoneg or be forced to 1000/Full
1564                  */
1565                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1566                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1567
1568                 /* set speed of 1000/Full if speed/duplex is forced */
1569                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1570                 break;
1571         }
1572
1573         wr32(E1000_CTRL, ctrl_reg);
1574
1575         /* New SerDes mode allows for forcing speed or autonegotiating speed
1576          * at 1gb. Autoneg should be default set by most drivers. This is the
1577          * mode that will be compatible with older link partners and switches.
1578          * However, both are supported by the hardware and some drivers/tools.
1579          */
1580         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1581                 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1582
1583         if (pcs_autoneg) {
1584                 /* Set PCS register for autoneg */
1585                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1586                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1587
1588                 /* Disable force flow control for autoneg */
1589                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1590
1591                 /* Configure flow control advertisement for autoneg */
1592                 anadv_reg = rd32(E1000_PCS_ANADV);
1593                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1594                 switch (hw->fc.requested_mode) {
1595                 case e1000_fc_full:
1596                 case e1000_fc_rx_pause:
1597                         anadv_reg |= E1000_TXCW_ASM_DIR;
1598                         anadv_reg |= E1000_TXCW_PAUSE;
1599                         break;
1600                 case e1000_fc_tx_pause:
1601                         anadv_reg |= E1000_TXCW_ASM_DIR;
1602                         break;
1603                 default:
1604                         break;
1605                 }
1606                 wr32(E1000_PCS_ANADV, anadv_reg);
1607
1608                 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1609         } else {
1610                 /* Set PCS register for forced link */
1611                 reg |= E1000_PCS_LCTL_FSD;        /* Force Speed */
1612
1613                 /* Force flow control for forced link */
1614                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1615
1616                 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1617         }
1618
1619         wr32(E1000_PCS_LCTL, reg);
1620
1621         if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1622                 igb_force_mac_fc(hw);
1623
1624         return ret_val;
1625 }
1626
1627 /**
1628  *  igb_sgmii_active_82575 - Return sgmii state
1629  *  @hw: pointer to the HW structure
1630  *
1631  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1632  *  which can be enabled for use in the embedded applications.  Simply
1633  *  return the current state of the sgmii interface.
1634  **/
1635 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1636 {
1637         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1638         return dev_spec->sgmii_active;
1639 }
1640
1641 /**
1642  *  igb_reset_init_script_82575 - Inits HW defaults after reset
1643  *  @hw: pointer to the HW structure
1644  *
1645  *  Inits recommended HW defaults after a reset when there is no EEPROM
1646  *  detected. This is only for the 82575.
1647  **/
1648 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1649 {
1650         if (hw->mac.type == e1000_82575) {
1651                 hw_dbg("Running reset init script for 82575\n");
1652                 /* SerDes configuration via SERDESCTRL */
1653                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1654                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1655                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1656                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1657
1658                 /* CCM configuration via CCMCTL register */
1659                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1660                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1661
1662                 /* PCIe lanes configuration */
1663                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1664                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1665                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1666                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1667
1668                 /* PCIe PLL Configuration */
1669                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1670                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1671                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1672         }
1673
1674         return 0;
1675 }
1676
1677 /**
1678  *  igb_read_mac_addr_82575 - Read device MAC address
1679  *  @hw: pointer to the HW structure
1680  **/
1681 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1682 {
1683         s32 ret_val = 0;
1684
1685         /* If there's an alternate MAC address place it in RAR0
1686          * so that it will override the Si installed default perm
1687          * address.
1688          */
1689         ret_val = igb_check_alt_mac_addr(hw);
1690         if (ret_val)
1691                 goto out;
1692
1693         ret_val = igb_read_mac_addr(hw);
1694
1695 out:
1696         return ret_val;
1697 }
1698
1699 /**
1700  * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1701  * @hw: pointer to the HW structure
1702  *
1703  * In the case of a PHY power down to save power, or to turn off link during a
1704  * driver unload, or wake on lan is not enabled, remove the link.
1705  **/
1706 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1707 {
1708         /* If the management interface is not enabled, then power down */
1709         if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1710                 igb_power_down_phy_copper(hw);
1711 }
1712
1713 /**
1714  *  igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1715  *  @hw: pointer to the HW structure
1716  *
1717  *  Clears the hardware counters by reading the counter registers.
1718  **/
1719 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1720 {
1721         igb_clear_hw_cntrs_base(hw);
1722
1723         rd32(E1000_PRC64);
1724         rd32(E1000_PRC127);
1725         rd32(E1000_PRC255);
1726         rd32(E1000_PRC511);
1727         rd32(E1000_PRC1023);
1728         rd32(E1000_PRC1522);
1729         rd32(E1000_PTC64);
1730         rd32(E1000_PTC127);
1731         rd32(E1000_PTC255);
1732         rd32(E1000_PTC511);
1733         rd32(E1000_PTC1023);
1734         rd32(E1000_PTC1522);
1735
1736         rd32(E1000_ALGNERRC);
1737         rd32(E1000_RXERRC);
1738         rd32(E1000_TNCRS);
1739         rd32(E1000_CEXTERR);
1740         rd32(E1000_TSCTC);
1741         rd32(E1000_TSCTFC);
1742
1743         rd32(E1000_MGTPRC);
1744         rd32(E1000_MGTPDC);
1745         rd32(E1000_MGTPTC);
1746
1747         rd32(E1000_IAC);
1748         rd32(E1000_ICRXOC);
1749
1750         rd32(E1000_ICRXPTC);
1751         rd32(E1000_ICRXATC);
1752         rd32(E1000_ICTXPTC);
1753         rd32(E1000_ICTXATC);
1754         rd32(E1000_ICTXQEC);
1755         rd32(E1000_ICTXQMTC);
1756         rd32(E1000_ICRXDMTC);
1757
1758         rd32(E1000_CBTMPC);
1759         rd32(E1000_HTDPMC);
1760         rd32(E1000_CBRMPC);
1761         rd32(E1000_RPTHC);
1762         rd32(E1000_HGPTC);
1763         rd32(E1000_HTCBDPC);
1764         rd32(E1000_HGORCL);
1765         rd32(E1000_HGORCH);
1766         rd32(E1000_HGOTCL);
1767         rd32(E1000_HGOTCH);
1768         rd32(E1000_LENERRS);
1769
1770         /* This register should not be read in copper configurations */
1771         if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1772             igb_sgmii_active_82575(hw))
1773                 rd32(E1000_SCVPC);
1774 }
1775
1776 /**
1777  *  igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1778  *  @hw: pointer to the HW structure
1779  *
1780  *  After rx enable if managability is enabled then there is likely some
1781  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
1782  *  function clears the fifos and flushes any packets that came in as rx was
1783  *  being enabled.
1784  **/
1785 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1786 {
1787         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1788         int i, ms_wait;
1789
1790         if (hw->mac.type != e1000_82575 ||
1791             !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1792                 return;
1793
1794         /* Disable all RX queues */
1795         for (i = 0; i < 4; i++) {
1796                 rxdctl[i] = rd32(E1000_RXDCTL(i));
1797                 wr32(E1000_RXDCTL(i),
1798                      rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1799         }
1800         /* Poll all queues to verify they have shut down */
1801         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1802                 msleep(1);
1803                 rx_enabled = 0;
1804                 for (i = 0; i < 4; i++)
1805                         rx_enabled |= rd32(E1000_RXDCTL(i));
1806                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1807                         break;
1808         }
1809
1810         if (ms_wait == 10)
1811                 hw_dbg("Queue disable timed out after 10ms\n");
1812
1813         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1814          * incoming packets are rejected.  Set enable and wait 2ms so that
1815          * any packet that was coming in as RCTL.EN was set is flushed
1816          */
1817         rfctl = rd32(E1000_RFCTL);
1818         wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1819
1820         rlpml = rd32(E1000_RLPML);
1821         wr32(E1000_RLPML, 0);
1822
1823         rctl = rd32(E1000_RCTL);
1824         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1825         temp_rctl |= E1000_RCTL_LPE;
1826
1827         wr32(E1000_RCTL, temp_rctl);
1828         wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1829         wrfl();
1830         msleep(2);
1831
1832         /* Enable RX queues that were previously enabled and restore our
1833          * previous state
1834          */
1835         for (i = 0; i < 4; i++)
1836                 wr32(E1000_RXDCTL(i), rxdctl[i]);
1837         wr32(E1000_RCTL, rctl);
1838         wrfl();
1839
1840         wr32(E1000_RLPML, rlpml);
1841         wr32(E1000_RFCTL, rfctl);
1842
1843         /* Flush receive errors generated by workaround */
1844         rd32(E1000_ROC);
1845         rd32(E1000_RNBC);
1846         rd32(E1000_MPC);
1847 }
1848
1849 /**
1850  *  igb_set_pcie_completion_timeout - set pci-e completion timeout
1851  *  @hw: pointer to the HW structure
1852  *
1853  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1854  *  however the hardware default for these parts is 500us to 1ms which is less
1855  *  than the 10ms recommended by the pci-e spec.  To address this we need to
1856  *  increase the value to either 10ms to 200ms for capability version 1 config,
1857  *  or 16ms to 55ms for version 2.
1858  **/
1859 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1860 {
1861         u32 gcr = rd32(E1000_GCR);
1862         s32 ret_val = 0;
1863         u16 pcie_devctl2;
1864
1865         /* only take action if timeout value is defaulted to 0 */
1866         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1867                 goto out;
1868
1869         /* if capabilities version is type 1 we can write the
1870          * timeout of 10ms to 200ms through the GCR register
1871          */
1872         if (!(gcr & E1000_GCR_CAP_VER2)) {
1873                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1874                 goto out;
1875         }
1876
1877         /* for version 2 capabilities we need to write the config space
1878          * directly in order to set the completion timeout value for
1879          * 16ms to 55ms
1880          */
1881         ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1882                                         &pcie_devctl2);
1883         if (ret_val)
1884                 goto out;
1885
1886         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1887
1888         ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1889                                          &pcie_devctl2);
1890 out:
1891         /* disable completion timeout resend */
1892         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1893
1894         wr32(E1000_GCR, gcr);
1895         return ret_val;
1896 }
1897
1898 /**
1899  *  igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1900  *  @hw: pointer to the hardware struct
1901  *  @enable: state to enter, either enabled or disabled
1902  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
1903  *
1904  *  enables/disables L2 switch anti-spoofing functionality.
1905  **/
1906 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1907 {
1908         u32 reg_val, reg_offset;
1909
1910         switch (hw->mac.type) {
1911         case e1000_82576:
1912                 reg_offset = E1000_DTXSWC;
1913                 break;
1914         case e1000_i350:
1915         case e1000_i354:
1916                 reg_offset = E1000_TXSWC;
1917                 break;
1918         default:
1919                 return;
1920         }
1921
1922         reg_val = rd32(reg_offset);
1923         if (enable) {
1924                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1925                              E1000_DTXSWC_VLAN_SPOOF_MASK);
1926                 /* The PF can spoof - it has to in order to
1927                  * support emulation mode NICs
1928                  */
1929                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1930         } else {
1931                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1932                              E1000_DTXSWC_VLAN_SPOOF_MASK);
1933         }
1934         wr32(reg_offset, reg_val);
1935 }
1936
1937 /**
1938  *  igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1939  *  @hw: pointer to the hardware struct
1940  *  @enable: state to enter, either enabled or disabled
1941  *
1942  *  enables/disables L2 switch loopback functionality.
1943  **/
1944 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1945 {
1946         u32 dtxswc;
1947
1948         switch (hw->mac.type) {
1949         case e1000_82576:
1950                 dtxswc = rd32(E1000_DTXSWC);
1951                 if (enable)
1952                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1953                 else
1954                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1955                 wr32(E1000_DTXSWC, dtxswc);
1956                 break;
1957         case e1000_i354:
1958         case e1000_i350:
1959                 dtxswc = rd32(E1000_TXSWC);
1960                 if (enable)
1961                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1962                 else
1963                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1964                 wr32(E1000_TXSWC, dtxswc);
1965                 break;
1966         default:
1967                 /* Currently no other hardware supports loopback */
1968                 break;
1969         }
1970
1971 }
1972
1973 /**
1974  *  igb_vmdq_set_replication_pf - enable or disable vmdq replication
1975  *  @hw: pointer to the hardware struct
1976  *  @enable: state to enter, either enabled or disabled
1977  *
1978  *  enables/disables replication of packets across multiple pools.
1979  **/
1980 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1981 {
1982         u32 vt_ctl = rd32(E1000_VT_CTL);
1983
1984         if (enable)
1985                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1986         else
1987                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1988
1989         wr32(E1000_VT_CTL, vt_ctl);
1990 }
1991
1992 /**
1993  *  igb_read_phy_reg_82580 - Read 82580 MDI control register
1994  *  @hw: pointer to the HW structure
1995  *  @offset: register offset to be read
1996  *  @data: pointer to the read data
1997  *
1998  *  Reads the MDI control register in the PHY at offset and stores the
1999  *  information read to data.
2000  **/
2001 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2002 {
2003         s32 ret_val;
2004
2005         ret_val = hw->phy.ops.acquire(hw);
2006         if (ret_val)
2007                 goto out;
2008
2009         ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2010
2011         hw->phy.ops.release(hw);
2012
2013 out:
2014         return ret_val;
2015 }
2016
2017 /**
2018  *  igb_write_phy_reg_82580 - Write 82580 MDI control register
2019  *  @hw: pointer to the HW structure
2020  *  @offset: register offset to write to
2021  *  @data: data to write to register at offset
2022  *
2023  *  Writes data to MDI control register in the PHY at offset.
2024  **/
2025 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2026 {
2027         s32 ret_val;
2028
2029
2030         ret_val = hw->phy.ops.acquire(hw);
2031         if (ret_val)
2032                 goto out;
2033
2034         ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2035
2036         hw->phy.ops.release(hw);
2037
2038 out:
2039         return ret_val;
2040 }
2041
2042 /**
2043  *  igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2044  *  @hw: pointer to the HW structure
2045  *
2046  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2047  *  the values found in the EEPROM.  This addresses an issue in which these
2048  *  bits are not restored from EEPROM after reset.
2049  **/
2050 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2051 {
2052         s32 ret_val = 0;
2053         u32 mdicnfg;
2054         u16 nvm_data = 0;
2055
2056         if (hw->mac.type != e1000_82580)
2057                 goto out;
2058         if (!igb_sgmii_active_82575(hw))
2059                 goto out;
2060
2061         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2062                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2063                                    &nvm_data);
2064         if (ret_val) {
2065                 hw_dbg("NVM Read Error\n");
2066                 goto out;
2067         }
2068
2069         mdicnfg = rd32(E1000_MDICNFG);
2070         if (nvm_data & NVM_WORD24_EXT_MDIO)
2071                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2072         if (nvm_data & NVM_WORD24_COM_MDIO)
2073                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2074         wr32(E1000_MDICNFG, mdicnfg);
2075 out:
2076         return ret_val;
2077 }
2078
2079 /**
2080  *  igb_reset_hw_82580 - Reset hardware
2081  *  @hw: pointer to the HW structure
2082  *
2083  *  This resets function or entire device (all ports, etc.)
2084  *  to a known state.
2085  **/
2086 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2087 {
2088         s32 ret_val = 0;
2089         /* BH SW mailbox bit in SW_FW_SYNC */
2090         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2091         u32 ctrl;
2092         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2093
2094         hw->dev_spec._82575.global_device_reset = false;
2095
2096         /* due to hw errata, global device reset doesn't always
2097          * work on 82580
2098          */
2099         if (hw->mac.type == e1000_82580)
2100                 global_device_reset = false;
2101
2102         /* Get current control state. */
2103         ctrl = rd32(E1000_CTRL);
2104
2105         /* Prevent the PCI-E bus from sticking if there is no TLP connection
2106          * on the last TLP read/write transaction when MAC is reset.
2107          */
2108         ret_val = igb_disable_pcie_master(hw);
2109         if (ret_val)
2110                 hw_dbg("PCI-E Master disable polling has failed.\n");
2111
2112         hw_dbg("Masking off all interrupts\n");
2113         wr32(E1000_IMC, 0xffffffff);
2114         wr32(E1000_RCTL, 0);
2115         wr32(E1000_TCTL, E1000_TCTL_PSP);
2116         wrfl();
2117
2118         msleep(10);
2119
2120         /* Determine whether or not a global dev reset is requested */
2121         if (global_device_reset &&
2122                 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2123                         global_device_reset = false;
2124
2125         if (global_device_reset &&
2126                 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2127                 ctrl |= E1000_CTRL_DEV_RST;
2128         else
2129                 ctrl |= E1000_CTRL_RST;
2130
2131         wr32(E1000_CTRL, ctrl);
2132         wrfl();
2133
2134         /* Add delay to insure DEV_RST has time to complete */
2135         if (global_device_reset)
2136                 msleep(5);
2137
2138         ret_val = igb_get_auto_rd_done(hw);
2139         if (ret_val) {
2140                 /* When auto config read does not complete, do not
2141                  * return with an error. This can happen in situations
2142                  * where there is no eeprom and prevents getting link.
2143                  */
2144                 hw_dbg("Auto Read Done did not complete\n");
2145         }
2146
2147         /* clear global device reset status bit */
2148         wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2149
2150         /* Clear any pending interrupt events. */
2151         wr32(E1000_IMC, 0xffffffff);
2152         rd32(E1000_ICR);
2153
2154         ret_val = igb_reset_mdicnfg_82580(hw);
2155         if (ret_val)
2156                 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2157
2158         /* Install any alternate MAC address into RAR0 */
2159         ret_val = igb_check_alt_mac_addr(hw);
2160
2161         /* Release semaphore */
2162         if (global_device_reset)
2163                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2164
2165         return ret_val;
2166 }
2167
2168 /**
2169  *  igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2170  *  @data: data received by reading RXPBS register
2171  *
2172  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2173  *  This function converts the retrieved value into the correct table value
2174  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2175  *  0x0 36  72 144   1   2   4   8  16
2176  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2177  */
2178 u16 igb_rxpbs_adjust_82580(u32 data)
2179 {
2180         u16 ret_val = 0;
2181
2182         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2183                 ret_val = e1000_82580_rxpbs_table[data];
2184
2185         return ret_val;
2186 }
2187
2188 /**
2189  *  igb_validate_nvm_checksum_with_offset - Validate EEPROM
2190  *  checksum
2191  *  @hw: pointer to the HW structure
2192  *  @offset: offset in words of the checksum protected region
2193  *
2194  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2195  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2196  **/
2197 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2198                                                  u16 offset)
2199 {
2200         s32 ret_val = 0;
2201         u16 checksum = 0;
2202         u16 i, nvm_data;
2203
2204         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2205                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2206                 if (ret_val) {
2207                         hw_dbg("NVM Read Error\n");
2208                         goto out;
2209                 }
2210                 checksum += nvm_data;
2211         }
2212
2213         if (checksum != (u16) NVM_SUM) {
2214                 hw_dbg("NVM Checksum Invalid\n");
2215                 ret_val = -E1000_ERR_NVM;
2216                 goto out;
2217         }
2218
2219 out:
2220         return ret_val;
2221 }
2222
2223 /**
2224  *  igb_update_nvm_checksum_with_offset - Update EEPROM
2225  *  checksum
2226  *  @hw: pointer to the HW structure
2227  *  @offset: offset in words of the checksum protected region
2228  *
2229  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2230  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2231  *  value to the EEPROM.
2232  **/
2233 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2234 {
2235         s32 ret_val;
2236         u16 checksum = 0;
2237         u16 i, nvm_data;
2238
2239         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2240                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2241                 if (ret_val) {
2242                         hw_dbg("NVM Read Error while updating checksum.\n");
2243                         goto out;
2244                 }
2245                 checksum += nvm_data;
2246         }
2247         checksum = (u16) NVM_SUM - checksum;
2248         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2249                                 &checksum);
2250         if (ret_val)
2251                 hw_dbg("NVM Write Error while updating checksum.\n");
2252
2253 out:
2254         return ret_val;
2255 }
2256
2257 /**
2258  *  igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2259  *  @hw: pointer to the HW structure
2260  *
2261  *  Calculates the EEPROM section checksum by reading/adding each word of
2262  *  the EEPROM and then verifies that the sum of the EEPROM is
2263  *  equal to 0xBABA.
2264  **/
2265 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2266 {
2267         s32 ret_val = 0;
2268         u16 eeprom_regions_count = 1;
2269         u16 j, nvm_data;
2270         u16 nvm_offset;
2271
2272         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2273         if (ret_val) {
2274                 hw_dbg("NVM Read Error\n");
2275                 goto out;
2276         }
2277
2278         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2279                 /* if checksums compatibility bit is set validate checksums
2280                  * for all 4 ports.
2281                  */
2282                 eeprom_regions_count = 4;
2283         }
2284
2285         for (j = 0; j < eeprom_regions_count; j++) {
2286                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2287                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2288                                                                 nvm_offset);
2289                 if (ret_val != 0)
2290                         goto out;
2291         }
2292
2293 out:
2294         return ret_val;
2295 }
2296
2297 /**
2298  *  igb_update_nvm_checksum_82580 - Update EEPROM checksum
2299  *  @hw: pointer to the HW structure
2300  *
2301  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2302  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2303  *  checksum and writes the value to the EEPROM.
2304  **/
2305 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2306 {
2307         s32 ret_val;
2308         u16 j, nvm_data;
2309         u16 nvm_offset;
2310
2311         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2312         if (ret_val) {
2313                 hw_dbg("NVM Read Error while updating checksum"
2314                         " compatibility bit.\n");
2315                 goto out;
2316         }
2317
2318         if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2319                 /* set compatibility bit to validate checksums appropriately */
2320                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2321                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2322                                         &nvm_data);
2323                 if (ret_val) {
2324                         hw_dbg("NVM Write Error while updating checksum"
2325                                 " compatibility bit.\n");
2326                         goto out;
2327                 }
2328         }
2329
2330         for (j = 0; j < 4; j++) {
2331                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2332                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2333                 if (ret_val)
2334                         goto out;
2335         }
2336
2337 out:
2338         return ret_val;
2339 }
2340
2341 /**
2342  *  igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2343  *  @hw: pointer to the HW structure
2344  *
2345  *  Calculates the EEPROM section checksum by reading/adding each word of
2346  *  the EEPROM and then verifies that the sum of the EEPROM is
2347  *  equal to 0xBABA.
2348  **/
2349 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2350 {
2351         s32 ret_val = 0;
2352         u16 j;
2353         u16 nvm_offset;
2354
2355         for (j = 0; j < 4; j++) {
2356                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2357                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2358                                                                 nvm_offset);
2359                 if (ret_val != 0)
2360                         goto out;
2361         }
2362
2363 out:
2364         return ret_val;
2365 }
2366
2367 /**
2368  *  igb_update_nvm_checksum_i350 - Update EEPROM checksum
2369  *  @hw: pointer to the HW structure
2370  *
2371  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2372  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2373  *  checksum and writes the value to the EEPROM.
2374  **/
2375 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2376 {
2377         s32 ret_val = 0;
2378         u16 j;
2379         u16 nvm_offset;
2380
2381         for (j = 0; j < 4; j++) {
2382                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2383                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2384                 if (ret_val != 0)
2385                         goto out;
2386         }
2387
2388 out:
2389         return ret_val;
2390 }
2391
2392 /**
2393  *  __igb_access_emi_reg - Read/write EMI register
2394  *  @hw: pointer to the HW structure
2395  *  @addr: EMI address to program
2396  *  @data: pointer to value to read/write from/to the EMI address
2397  *  @read: boolean flag to indicate read or write
2398  **/
2399 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2400                                   u16 *data, bool read)
2401 {
2402         s32 ret_val = E1000_SUCCESS;
2403
2404         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2405         if (ret_val)
2406                 return ret_val;
2407
2408         if (read)
2409                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2410         else
2411                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2412
2413         return ret_val;
2414 }
2415
2416 /**
2417  *  igb_read_emi_reg - Read Extended Management Interface register
2418  *  @hw: pointer to the HW structure
2419  *  @addr: EMI address to program
2420  *  @data: value to be read from the EMI address
2421  **/
2422 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2423 {
2424         return __igb_access_emi_reg(hw, addr, data, true);
2425 }
2426
2427 /**
2428  *  igb_set_eee_i350 - Enable/disable EEE support
2429  *  @hw: pointer to the HW structure
2430  *
2431  *  Enable/disable EEE based on setting in dev_spec structure.
2432  *
2433  **/
2434 s32 igb_set_eee_i350(struct e1000_hw *hw)
2435 {
2436         s32 ret_val = 0;
2437         u32 ipcnfg, eeer;
2438
2439         if ((hw->mac.type < e1000_i350) ||
2440             (hw->phy.media_type != e1000_media_type_copper))
2441                 goto out;
2442         ipcnfg = rd32(E1000_IPCNFG);
2443         eeer = rd32(E1000_EEER);
2444
2445         /* enable or disable per user setting */
2446         if (!(hw->dev_spec._82575.eee_disable)) {
2447                 u32 eee_su = rd32(E1000_EEE_SU);
2448
2449                 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2450                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2451                         E1000_EEER_LPI_FC);
2452
2453                 /* This bit should not be set in normal operation. */
2454                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2455                         hw_dbg("LPI Clock Stop Bit should not be set!\n");
2456
2457         } else {
2458                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2459                         E1000_IPCNFG_EEE_100M_AN);
2460                 eeer &= ~(E1000_EEER_TX_LPI_EN |
2461                         E1000_EEER_RX_LPI_EN |
2462                         E1000_EEER_LPI_FC);
2463         }
2464         wr32(E1000_IPCNFG, ipcnfg);
2465         wr32(E1000_EEER, eeer);
2466         rd32(E1000_IPCNFG);
2467         rd32(E1000_EEER);
2468 out:
2469
2470         return ret_val;
2471 }
2472
2473 /**
2474  *  igb_set_eee_i354 - Enable/disable EEE support
2475  *  @hw: pointer to the HW structure
2476  *
2477  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2478  *
2479  **/
2480 s32 igb_set_eee_i354(struct e1000_hw *hw)
2481 {
2482         struct e1000_phy_info *phy = &hw->phy;
2483         s32 ret_val = 0;
2484         u16 phy_data;
2485
2486         if ((hw->phy.media_type != e1000_media_type_copper) ||
2487             (phy->id != M88E1543_E_PHY_ID))
2488                 goto out;
2489
2490         if (!hw->dev_spec._82575.eee_disable) {
2491                 /* Switch to PHY page 18. */
2492                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2493                 if (ret_val)
2494                         goto out;
2495
2496                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2497                                             &phy_data);
2498                 if (ret_val)
2499                         goto out;
2500
2501                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2502                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2503                                              phy_data);
2504                 if (ret_val)
2505                         goto out;
2506
2507                 /* Return the PHY to page 0. */
2508                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2509                 if (ret_val)
2510                         goto out;
2511
2512                 /* Turn on EEE advertisement. */
2513                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2514                                              E1000_EEE_ADV_DEV_I354,
2515                                              &phy_data);
2516                 if (ret_val)
2517                         goto out;
2518
2519                 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2520                             E1000_EEE_ADV_1000_SUPPORTED;
2521                 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2522                                                 E1000_EEE_ADV_DEV_I354,
2523                                                 phy_data);
2524         } else {
2525                 /* Turn off EEE advertisement. */
2526                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2527                                              E1000_EEE_ADV_DEV_I354,
2528                                              &phy_data);
2529                 if (ret_val)
2530                         goto out;
2531
2532                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2533                               E1000_EEE_ADV_1000_SUPPORTED);
2534                 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2535                                               E1000_EEE_ADV_DEV_I354,
2536                                               phy_data);
2537         }
2538
2539 out:
2540         return ret_val;
2541 }
2542
2543 /**
2544  *  igb_get_eee_status_i354 - Get EEE status
2545  *  @hw: pointer to the HW structure
2546  *  @status: EEE status
2547  *
2548  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
2549  *  been received.
2550  **/
2551 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2552 {
2553         struct e1000_phy_info *phy = &hw->phy;
2554         s32 ret_val = 0;
2555         u16 phy_data;
2556
2557         /* Check if EEE is supported on this device. */
2558         if ((hw->phy.media_type != e1000_media_type_copper) ||
2559             (phy->id != M88E1543_E_PHY_ID))
2560                 goto out;
2561
2562         ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2563                                      E1000_PCS_STATUS_DEV_I354,
2564                                      &phy_data);
2565         if (ret_val)
2566                 goto out;
2567
2568         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2569                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2570
2571 out:
2572         return ret_val;
2573 }
2574
2575 static const u8 e1000_emc_temp_data[4] = {
2576         E1000_EMC_INTERNAL_DATA,
2577         E1000_EMC_DIODE1_DATA,
2578         E1000_EMC_DIODE2_DATA,
2579         E1000_EMC_DIODE3_DATA
2580 };
2581 static const u8 e1000_emc_therm_limit[4] = {
2582         E1000_EMC_INTERNAL_THERM_LIMIT,
2583         E1000_EMC_DIODE1_THERM_LIMIT,
2584         E1000_EMC_DIODE2_THERM_LIMIT,
2585         E1000_EMC_DIODE3_THERM_LIMIT
2586 };
2587
2588 /**
2589  *  igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2590  *  @hw: pointer to hardware structure
2591  *
2592  *  Updates the temperatures in mac.thermal_sensor_data
2593  **/
2594 s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2595 {
2596         s32 status = E1000_SUCCESS;
2597         u16 ets_offset;
2598         u16 ets_cfg;
2599         u16 ets_sensor;
2600         u8  num_sensors;
2601         u8  sensor_index;
2602         u8  sensor_location;
2603         u8  i;
2604         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2605
2606         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2607                 return E1000_NOT_IMPLEMENTED;
2608
2609         data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2610
2611         /* Return the internal sensor only if ETS is unsupported */
2612         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2613         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2614                 return status;
2615
2616         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2617         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2618             != NVM_ETS_TYPE_EMC)
2619                 return E1000_NOT_IMPLEMENTED;
2620
2621         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2622         if (num_sensors > E1000_MAX_SENSORS)
2623                 num_sensors = E1000_MAX_SENSORS;
2624
2625         for (i = 1; i < num_sensors; i++) {
2626                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2627                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2628                                 NVM_ETS_DATA_INDEX_SHIFT);
2629                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2630                                    NVM_ETS_DATA_LOC_SHIFT);
2631
2632                 if (sensor_location != 0)
2633                         hw->phy.ops.read_i2c_byte(hw,
2634                                         e1000_emc_temp_data[sensor_index],
2635                                         E1000_I2C_THERMAL_SENSOR_ADDR,
2636                                         &data->sensor[i].temp);
2637         }
2638         return status;
2639 }
2640
2641 /**
2642  *  igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2643  *  @hw: pointer to hardware structure
2644  *
2645  *  Sets the thermal sensor thresholds according to the NVM map
2646  *  and save off the threshold and location values into mac.thermal_sensor_data
2647  **/
2648 s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2649 {
2650         s32 status = E1000_SUCCESS;
2651         u16 ets_offset;
2652         u16 ets_cfg;
2653         u16 ets_sensor;
2654         u8  low_thresh_delta;
2655         u8  num_sensors;
2656         u8  sensor_index;
2657         u8  sensor_location;
2658         u8  therm_limit;
2659         u8  i;
2660         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2661
2662         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2663                 return E1000_NOT_IMPLEMENTED;
2664
2665         memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2666
2667         data->sensor[0].location = 0x1;
2668         data->sensor[0].caution_thresh =
2669                 (rd32(E1000_THHIGHTC) & 0xFF);
2670         data->sensor[0].max_op_thresh =
2671                 (rd32(E1000_THLOWTC) & 0xFF);
2672
2673         /* Return the internal sensor only if ETS is unsupported */
2674         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2675         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2676                 return status;
2677
2678         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2679         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2680             != NVM_ETS_TYPE_EMC)
2681                 return E1000_NOT_IMPLEMENTED;
2682
2683         low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2684                             NVM_ETS_LTHRES_DELTA_SHIFT);
2685         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2686
2687         for (i = 1; i <= num_sensors; i++) {
2688                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2689                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2690                                 NVM_ETS_DATA_INDEX_SHIFT);
2691                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2692                                    NVM_ETS_DATA_LOC_SHIFT);
2693                 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2694
2695                 hw->phy.ops.write_i2c_byte(hw,
2696                         e1000_emc_therm_limit[sensor_index],
2697                         E1000_I2C_THERMAL_SENSOR_ADDR,
2698                         therm_limit);
2699
2700                 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2701                         data->sensor[i].location = sensor_location;
2702                         data->sensor[i].caution_thresh = therm_limit;
2703                         data->sensor[i].max_op_thresh = therm_limit -
2704                                                         low_thresh_delta;
2705                 }
2706         }
2707         return status;
2708 }
2709
2710 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2711         .init_hw              = igb_init_hw_82575,
2712         .check_for_link       = igb_check_for_link_82575,
2713         .rar_set              = igb_rar_set,
2714         .read_mac_addr        = igb_read_mac_addr_82575,
2715         .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
2716 #ifdef CONFIG_IGB_HWMON
2717         .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2718         .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2719 #endif
2720 };
2721
2722 static struct e1000_phy_operations e1000_phy_ops_82575 = {
2723         .acquire              = igb_acquire_phy_82575,
2724         .get_cfg_done         = igb_get_cfg_done_82575,
2725         .release              = igb_release_phy_82575,
2726         .write_i2c_byte       = igb_write_i2c_byte,
2727         .read_i2c_byte        = igb_read_i2c_byte,
2728 };
2729
2730 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2731         .acquire              = igb_acquire_nvm_82575,
2732         .read                 = igb_read_nvm_eerd,
2733         .release              = igb_release_nvm_82575,
2734         .write                = igb_write_nvm_spi,
2735 };
2736
2737 const struct e1000_info e1000_82575_info = {
2738         .get_invariants = igb_get_invariants_82575,
2739         .mac_ops = &e1000_mac_ops_82575,
2740         .phy_ops = &e1000_phy_ops_82575,
2741         .nvm_ops = &e1000_nvm_ops_82575,
2742 };
2743